From aa2db8fdde1227d3b0a6fc3117d4b79e4f848f04 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 25 Mar 2008 13:42:48 +0000 Subject: [PATCH] Fix no-module include files on command line. [Stefan Thiede] git-svn-id: file://localhost/svn/verilator/trunk/verilator@1009 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- Changes | 4 ++++ src/V3LinkDot.cpp | 23 +++++++++++++---------- src/verilog.y | 10 +++++++--- test_regress/t/t_flag_nomod_bad.pl | 19 +++++++++++++++++++ test_regress/t/t_flag_nomod_bad.v | 7 +++++++ 5 files changed, 50 insertions(+), 13 deletions(-) create mode 100755 test_regress/t/t_flag_nomod_bad.pl create mode 100644 test_regress/t/t_flag_nomod_bad.v diff --git a/Changes b/Changes index 4c9482352..36148b327 100644 --- a/Changes +++ b/Changes @@ -3,6 +3,10 @@ Revision history for Verilator The contributors that suggested a given feature are shown in []. [by ...] indicates the contributor was also the author of the fix; Thanks! +* Verilator 3.66*** + +**** Fix no-module include files on command line. [Stefan Thiede] + * Verilator 3.660 2008/03/23 *** Add support for hard-coding VERILATOR_ROOT etc in the executables, diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 44a527531..e0343ecc2 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -379,17 +379,20 @@ private: // This may not be the module with isTop() set, as early in the steps, // wrapTop may have not been created yet. AstModule* topmodp = nodep->modulesp(); - if (!topmodp) nodep->v3fatalSrc("No top level module"); - UINFO(8,"Top Module: "<insertTopCell(topmodp, m_scope); - m_inlineVxp = m_cellVxp; - { - topmodp->accept(*this); + if (!topmodp) { + nodep->v3error("No top level module found"); + } else { + UINFO(8,"Top Module: "<insertTopCell(topmodp, m_scope); + m_inlineVxp = m_cellVxp; + { + topmodp->accept(*this); + } + m_scope = ""; + m_cellVxp = NULL; + m_inlineVxp = m_cellVxp; } - m_scope = ""; - m_cellVxp = NULL; - m_inlineVxp = m_cellVxp; } virtual void visit(AstModule* nodep, AstNUser*) { UINFO(8," "< pslDecl %type pslSequence pslSere pslExpr -%start file +%start fileE %% //********************************************************************** @@ -445,8 +445,12 @@ statePop: /* empty */ { V3Read::statePop(); } //********************************************************************** // Files -file: description { } - | file description { } +fileE: /* empty */ { } + | file { } + ; + +file: description { } + | file description { } ; // IEEE: description diff --git a/test_regress/t/t_flag_nomod_bad.pl b/test_regress/t/t_flag_nomod_bad.pl new file mode 100755 index 000000000..2b7049696 --- /dev/null +++ b/test_regress/t/t_flag_nomod_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } +# $Id$ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2008 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# General Public License or the Perl Artistic License. + +compile ( + v_flags2 => ["--lint-only"], + fails=>$Last_Self->{v3}, + expect=> +'%Error: No top level module found +%Error: Exiting due to', + ) if $Last_Self->{v3}; + +ok(1); +1; diff --git a/test_regress/t/t_flag_nomod_bad.v b/test_regress/t/t_flag_nomod_bad.v new file mode 100644 index 000000000..579cf70b0 --- /dev/null +++ b/test_regress/t/t_flag_nomod_bad.v @@ -0,0 +1,7 @@ +// $Id$ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +`define EMPTY 1