From aa2630f837794c3b2ac30cbeb294f47635c4a04e Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 24 Apr 2008 15:04:01 +0000 Subject: [PATCH] Ignore old standard(ish) Verilog-XL defines git-svn-id: file://localhost/svn/verilator/trunk/verilator@1035 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- Changes | 8 +++-- src/verilog.l | 21 +++++++++++- test_regress/t/t_pp_pragmas.pl | 18 ++++++++++ test_regress/t/t_pp_pragmas.v | 62 ++++++++++++++++++++++++++++++++++ 4 files changed, 105 insertions(+), 4 deletions(-) create mode 100755 test_regress/t/t_pp_pragmas.pl create mode 100644 test_regress/t/t_pp_pragmas.v diff --git a/Changes b/Changes index 455812ebc..281c7544f 100644 --- a/Changes +++ b/Changes @@ -7,11 +7,13 @@ indicates the contributor was also the author of the fix; Thanks! *** Add Verilog 2005 $clog2() function. -**** Add error message when modules have duplicate names. [Stefan Thiede] +*** Add error message when modules have duplicate names. [Stefan Thiede] -**** Allow defines terminated in EOF, though against spec. [Stefan Thiede] +*** Allow defines terminated in EOF, though against spec. [Stefan Thiede] -**** Support optional argument to $finish and $stop. [by Stefan Thiede] +*** Support optional argument to $finish and $stop. [by Stefan Thiede] + +*** Ignore old standard(ish) Verilog-XL defines. [by Stefan Thiede] **** Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu] diff --git a/src/verilog.l b/src/verilog.l index b47965b83..071088431 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -714,22 +714,41 @@ escid \\[^ \t\f\r\n]+ /* Common for all SYSC header states */ /* OPTIMIZE: we return one per line, make it one for the entire block */ { + "`accelerate" { } // Verilog-XL compatibility + "`autoexpand_vectornets" { } // Verilog-XL compatibility "`celldefine" { V3Read::inCellDefine(true); } + "`default_decay_time"{ws}+[^\n]* { } // Verilog spec - delays only + "`delay_mode_distributed" { } // Verilog spec - delays only + "`delay_mode_path" { } // Verilog spec - delays only + "`delay_mode_unit" { } // Verilog spec - delays only + "`delay_mode_zero" { } // Verilog spec - delays only + "`disable_portfaults" { } // Verilog-XL compatibility + "`enable_portfaults" { } // Verilog-XL compatibility "`endcelldefine" { V3Read::inCellDefine(false); } "`endprotect" { } + "`expand_vectornets" { } // Verilog-XL compatibility "`inline" { } "`line"{ws}+[^\n]*\n { V3Read::ppline(yytext); } + "`noaccelerate" { } // Verilog-XL compatibility + "`noexpand_vectornets" { } // Verilog-XL compatibility + "`noremove_gatenames" { } // Verilog-XL compatibility + "`noremove_netnames" { } // Verilog-XL compatibility + "`nosuppress_faults" { } // Verilog-XL compatibility + "`nounconnected_drive" { } // Verilog-XL compatibility "`portcoerce" { } "`protect" { } "`psl" { if (V3Read::optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } } + "`remove_gatenames" { } // Verilog-XL compatibility + "`remove_netnames" { } // Verilog-XL compatibility "`resetall" { } + "`suppress_faults" { } // Verilog-XL compatibility "`systemc_ctor" { BEGIN SYSCCTOR; } "`systemc_dtor" { BEGIN SYSCDTOR; } "`systemc_header" { BEGIN SYSCHDR; } "`systemc_imp_header" { BEGIN SYSCIMPH; } "`systemc_implementation" { BEGIN SYSCIMP; } "`systemc_interface" { BEGIN SYSCINT; } - "`timescale"{ws}+[^\n]* {} + "`timescale"{ws}+[^\n]* { } // Verilog spec - not supported "`verilog" { BEGIN V3Read::lastVerilogState(); } "`begin_keywords"[ \t]*\"1364-1995\" { yy_push_state(V95); V3Read::pushBeginKeywords(YY_START);} diff --git a/test_regress/t/t_pp_pragmas.pl b/test_regress/t/t_pp_pragmas.pl new file mode 100755 index 000000000..7bfdbe852 --- /dev/null +++ b/test_regress/t/t_pp_pragmas.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } +# $Id$ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# General Public License or the Perl Artistic License. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_pp_pragmas.v b/test_regress/t/t_pp_pragmas.v new file mode 100644 index 000000000..de597c51d --- /dev/null +++ b/test_regress/t/t_pp_pragmas.v @@ -0,0 +1,62 @@ +// $Id$ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +`timescale 1ns/10ps +`verilog + +`suppress_faults +`nosuppress_faults +`enable_portfaults +`disable_portfaults + +`delay_mode_distributed +`delay_mode_path +`delay_mode_unit +`delay_mode_zero + +`default_decay_time 1 +`default_decay_time 1.0 +`default_decay_time infinite +// unsupported (recommended not to): `default_trireg_strength 10 + +// unsupported: `default_nettype wire +// unsupported: `default_nettype tri +// unsupported: `default_nettype tri0 +// unsupported: `default_nettype wand +// unsupported: `default_nettype triand +// unsupported: `default_nettype wor +// unsupported: `default_nettype trior +// unsupported: `default_nettype trireg +// unsupported: `default_nettype none + +`autoexpand_vectornets + +`accelerate +`noaccelerate +`expand_vectornets +`noexpand_vectornets +`remove_gatenames +`noremove_gatenames +`remove_netnames +`noremove_netnames +`resetall + +// unsupported: `unconnected_drive pull1 +// unsupported: `unconnected_drive pull0 +`nounconnected_drive +`nounconnected_drive + +`line 100 "hallo.v" 0 + +// unsupported: `uselib file=../moto_lib.v +// unsupported: `uselib dir=../lib.dir libext=.v + +module t; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule