diff --git a/test_regress/t/t_select_2d.pl b/test_regress/t/t_select_2d.pl
new file mode 100755
index 000000000..2cb5eeaff
--- /dev/null
+++ b/test_regress/t/t_select_2d.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2021 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_select_2d.v b/test_regress/t/t_select_2d.v
new file mode 100644
index 000000000..bbe492e52
--- /dev/null
+++ b/test_regress/t/t_select_2d.v
@@ -0,0 +1,78 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc=0;
+   reg [63:0] crc;
+   reg [63:0] sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [4:0] cnt_i = (crc[4:0] <= 5'd17) ? crc[4:0] : 5'd0;
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   logic [63:0]         out_o;                  // From test of Test.v
+   // End of automatics
+
+   Test test(/*AUTOINST*/
+             // Outputs
+             .out_o                     (out_o[63:0]),
+             // Inputs
+             .cnt_i                     (cnt_i[4:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = out_o;
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc == 0) begin
+         // Setup
+         crc <= 64'h5aef0c8d_d70a4497;
+         sum <= '0;
+      end
+      else if (cyc < 10) begin
+         sum <= '0;
+      end
+      else if (cyc < 90) begin
+      end
+      else if (cyc == 99) begin
+         $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+         if (crc !== 64'hc77bb9b3784ea091) $stop;
+         // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h1f324087bbba0bfa
+         if (sum !== `EXPECTED_SUM) $stop;
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
+
+module Test
+  (input logic [4:0]   cnt_i,
+   output logic [63:0] out_o);
+
+   logic [17:0][63:0]  data;
+   initial begin
+      for (int a = 0; a < 18; ++a)
+        data[a] = {8{a[7:0]}};
+   end
+
+   // verilator lint_off WIDTH
+   assign out_o = data[5'd17 - cnt_i];
+
+endmodule