From a89502be9ffa0aaa503bdcdce5e337efbb02aed7 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 22 Feb 2015 11:41:10 -0500 Subject: [PATCH] Fix comma-separated instantiations with parameters, bug884. --- Changes | 2 + src/verilog.y | 8 ++-- test_regress/t/t_inst_comma.v | 66 +++++++++++++++++++++++++++++ test_regress/t/t_inst_comma_inl0.pl | 21 +++++++++ test_regress/t/t_inst_comma_inl1.pl | 21 +++++++++ 5 files changed, 115 insertions(+), 3 deletions(-) create mode 100644 test_regress/t/t_inst_comma.v create mode 100755 test_regress/t/t_inst_comma_inl0.pl create mode 100755 test_regress/t/t_inst_comma_inl1.pl diff --git a/Changes b/Changes index 5271beb89..280c1bd40 100644 --- a/Changes +++ b/Changes @@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks! * Verilator 3.871 devel +**** Fix comma-instantiations with parameters, bug884. [Franck Jullien] + * Verilator 3.870 2015-02-12 diff --git a/src/verilog.y b/src/verilog.y index d0b535523..fb16ac308 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -2013,7 +2013,8 @@ etcInst: // IEEE: module_instantiation + gate_instantiation + udp_insta instDecl: id parameter_value_assignmentE {INSTPREP(*$1,$2);} instnameList ';' - { $$ = $4; GRAMMARP->m_impliedDecl=false;} + { $$ = $4; GRAMMARP->m_impliedDecl=false; + if (GRAMMARP->m_instParamp) { GRAMMARP->m_instParamp->deleteTree(); GRAMMARP->m_instParamp = NULL; } } // // IEEE: interface_identifier' .' modport_identifier list_of_interface_identifiers | id/*interface*/ '.' id/*modport*/ { VARRESET_NONLIST(AstVarType::IFACEREF); @@ -2038,9 +2039,10 @@ instnameList: ; instnameParen: - id instRangeE '(' cellpinList ')' { $$ = new AstCell($1,*$1,GRAMMARP->m_instModule,$4, GRAMMARP->m_instParamp,$2); + // // Must clone m_instParamp as may be comma'ed list of instances + id instRangeE '(' cellpinList ')' { $$ = new AstCell($1,*$1,GRAMMARP->m_instModule,$4, GRAMMARP->m_instParamp->cloneTree(true),$2); $$->trace(GRAMMARP->allTracingOn($1)); } - | id instRangeE { $$ = new AstCell($1,*$1,GRAMMARP->m_instModule,NULL,GRAMMARP->m_instParamp,$2); + | id instRangeE { $$ = new AstCell($1,*$1,GRAMMARP->m_instModule,NULL,GRAMMARP->m_instParamp->cloneTree(true),$2); $$->trace(GRAMMARP->allTracingOn($1)); } //UNSUP instRangeE '(' cellpinList ')' { UNSUP } // UDP // // Adding above and switching to the Verilog-Perl syntax diff --git a/test_regress/t/t_inst_comma.v b/test_regress/t/t_inst_comma.v new file mode 100644 index 000000000..3d5dbba83 --- /dev/null +++ b/test_regress/t/t_inst_comma.v @@ -0,0 +1,66 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2015 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=1; + parameter ONE = 1; + + wire [17:10] bitout; + reg [7:0] allbits; + reg [15:0] onebit; + + sub #(1) + sub0 (allbits, onebit[1:0], bitout[10]), + sub1 (allbits, onebit[3:2], bitout[11]), + sub2 (allbits, onebit[5:4], bitout[12]), + sub3 (allbits, onebit[7:6], bitout[13]), + sub4 (allbits, onebit[9:8], bitout[14]), + sub5 (allbits, onebit[11:10], bitout[15]), + sub6 (allbits, onebit[13:12], bitout[16]), + sub7 (allbits, onebit[15:14], bitout[17]); + + integer x; + + always @ (posedge clk) begin + //$write("%x\n", bitout); + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + allbits <= 8'hac; + onebit <= 16'hc01a; + end + if (cyc==2) begin + if (bitout !== 8'h07) $stop; + allbits <= 8'hca; + onebit <= 16'h1f01; + end + if (cyc==3) begin + if (bitout !== 8'h41) $stop; + if (sub0.bitout !== 1'b1) $stop; + if (sub1.bitout !== 1'b0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule + +`ifdef USE_INLINE + `define INLINE_MODULE /*verilator inline_module*/ +`else + `define INLINE_MODULE /*verilator public_module*/ +`endif + +module sub (input [7:0] allbits, input [1:0] onebit, output bitout); + `INLINE_MODULE + parameter integer P = 0; + initial if (P != 1) $stop; + wire bitout = (^ onebit) ^ (^ allbits); +endmodule diff --git a/test_regress/t/t_inst_comma_inl0.pl b/test_regress/t/t_inst_comma_inl0.pl new file mode 100755 index 000000000..1edc160f1 --- /dev/null +++ b/test_regress/t/t_inst_comma_inl0.pl @@ -0,0 +1,21 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +top_filename("t/t_inst_comma.v"); + +compile ( + v_flags2 => ['+define+NOUSE_INLINE',], + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_inst_comma_inl1.pl b/test_regress/t/t_inst_comma_inl1.pl new file mode 100755 index 000000000..7f7f4aeda --- /dev/null +++ b/test_regress/t/t_inst_comma_inl1.pl @@ -0,0 +1,21 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +top_filename("t/t_inst_comma.v"); + +compile ( + v_flags2 => ['+define+USE_INLINE',], + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1;