From a7e5cccf3390783a5e3460e1ec71742f5477738a Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 11 Jul 2019 22:36:32 -0400
Subject: [PATCH] In errors, single quote signals and other from-user data.

---
 src/V3EmitC.cpp                      | 2 +-
 src/V3LinkResolve.cpp                | 2 +-
 src/V3PreProc.cpp                    | 2 +-
 src/V3Width.cpp                      | 2 +-
 src/verilog.y                        | 4 ++--
 test_regress/t/t_display_bad.out     | 2 +-
 test_regress/t/t_gen_missing_bad.out | 2 +-
 test_regress/t/t_pp_dupdef_bad.out   | 4 ++--
 test_regress/t/t_var_bad_sv.out      | 4 ++--
 9 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp
index 3ae9c0827..188c02af9 100644
--- a/src/V3EmitC.cpp
+++ b/src/V3EmitC.cpp
@@ -1666,7 +1666,7 @@ void EmitCStmts::displayNode(AstNode* nodep, AstScopeName* scopenamep,
                 break;
             }
             default:
-                nodep->v3error("Unknown $display-like format code: %"<<pos[0]);
+                nodep->v3error("Unknown $display-like format code: '%"<<pos[0]<<"'");
                 break;
             }
         }
diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp
index 06065dc95..f4dcc7425 100644
--- a/src/V3LinkResolve.cpp
+++ b/src/V3LinkResolve.cpp
@@ -287,7 +287,7 @@ private:
                     break;
                 default:  // Most operators, just move to next argument
                     if (!V3Number::displayedFmtLegal(ch)) {
-                        nodep->v3error("Unknown $display-like format code: %"<<ch);
+                        nodep->v3error("Unknown $display-like format code: '%"<<ch<<"'");
                     } else {
                         if (!argp) {
                             nodep->v3error("Missing arguments for $display-like format");
diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp
index fe1f8a49e..d4df1eed1 100644
--- a/src/V3PreProc.cpp
+++ b/src/V3PreProc.cpp
@@ -329,7 +329,7 @@ void V3PreProcImp::define(FileLine* fl, const string& name, const string& value,
     UINFO(4,"DEFINE '"<<name<<"' as '"<<value<<"' params '"<<params<<"'"<<endl);
     if (defExists(name)) {
         if (!(defValue(name)==value && defParams(name)==params)) {  // Duplicate defs are OK
-            fl->v3warn(REDEFMACRO, "Redefining existing define: "<<name<<", with different value: "
+            fl->v3warn(REDEFMACRO, "Redefining existing define: '"<<name<<"', with different value: "
                        <<value<<(params=="" ? "":" ")<<params);
             defFileline(name)->v3warn(REDEFMACRO, "Previous definition is here, with value: "
                                       <<defValue(name)
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index f95b542a5..8161a50f8 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -2513,7 +2513,7 @@ private:
                 // We've resolved parameters and hit a module that we couldn't resolve.  It's
                 // finally time to report it.
                 // Note only here in V3Width as this is first visitor after V3Dead.
-                nodep->v3error("Cannot find file containing module: "<<nodep->modName());
+                nodep->v3error("Cannot find file containing module: '"<<nodep->modName()<<"'");
                 v3Global.opt.filePathLookedMsg(nodep->fileline(), nodep->modName());
             }
             if (nodep->rangep()) {
diff --git a/src/verilog.y b/src/verilog.y
index e32d52370..e4b2e4e70 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -214,8 +214,8 @@ int V3ParseGrammar::s_modTypeImpNum = 0;
 
 static void ERRSVKWD(FileLine* fileline, const string& tokname) {
     static int toldonce = 0;
-    fileline->v3error(string("Unexpected \"")+tokname+"\": \""+tokname
-                      +"\" is a SystemVerilog keyword misused as an identifier."
+    fileline->v3error(string("Unexpected '")+tokname+"': '"+tokname
+                      +"' is a SystemVerilog keyword misused as an identifier."
                       +(!toldonce++
                         ? "\n"+V3Error::warnMore()
                           +"... Suggest modify the Verilog-2001 code to avoid SV keywords,"
diff --git a/test_regress/t/t_display_bad.out b/test_regress/t/t_display_bad.out
index 53abb34d6..cb354b9cf 100644
--- a/test_regress/t/t_display_bad.out
+++ b/test_regress/t/t_display_bad.out
@@ -1,3 +1,3 @@
 %Error: t/t_display_bad.v:10: Missing arguments for $display-like format
-%Error: t/t_display_bad.v:12: Unknown $display-like format code: %q
+%Error: t/t_display_bad.v:12: Unknown $display-like format code: '%q'
 %Error: Exiting due to
diff --git a/test_regress/t/t_gen_missing_bad.out b/test_regress/t/t_gen_missing_bad.out
index 80183717e..b12e952a6 100644
--- a/test_regress/t/t_gen_missing_bad.out
+++ b/test_regress/t/t_gen_missing_bad.out
@@ -1,4 +1,4 @@
-%Error: t/t_gen_missing.v:42: Cannot find file containing module: foo_not_needed
+%Error: t/t_gen_missing.v:42: Cannot find file containing module: 'foo_not_needed'
         ... Looked in:
              t/foo_not_needed
              t/foo_not_needed.v
diff --git a/test_regress/t/t_pp_dupdef_bad.out b/test_regress/t/t_pp_dupdef_bad.out
index 53e0992e1..f0fdab49e 100644
--- a/test_regress/t/t_pp_dupdef_bad.out
+++ b/test_regress/t/t_pp_dupdef_bad.out
@@ -1,6 +1,6 @@
-%Warning-REDEFMACRO: t/t_pp_dupdef.v:10: Redefining existing define: DUP, with different value: barney
+%Warning-REDEFMACRO: t/t_pp_dupdef.v:10: Redefining existing define: 'DUP', with different value: barney
                      ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message.
 %Warning-REDEFMACRO: t/t_pp_dupdef.v:10: Previous definition is here, with value: fred
-%Warning-REDEFMACRO: t/t_pp_dupdef.v:13: Redefining existing define: DUPP, with different value: paramed(x,z) (x*z)
+%Warning-REDEFMACRO: t/t_pp_dupdef.v:13: Redefining existing define: 'DUPP', with different value: paramed(x,z) (x*z)
 %Warning-REDEFMACRO: t/t_pp_dupdef.v:13: Previous definition is here, with value: paramed(x) (x)
 %Error: Exiting due to
diff --git a/test_regress/t/t_var_bad_sv.out b/test_regress/t/t_var_bad_sv.out
index eec55acb8..6e26bc0fa 100644
--- a/test_regress/t/t_var_bad_sv.out
+++ b/test_regress/t/t_var_bad_sv.out
@@ -1,5 +1,5 @@
-%Error: t/t_var_bad_sv.v:7: Unexpected "do": "do" is a SystemVerilog keyword misused as an identifier.
+%Error: t/t_var_bad_sv.v:7: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.
         ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.
-%Error: t/t_var_bad_sv.v:8: Unexpected "do": "do" is a SystemVerilog keyword misused as an identifier.
+%Error: t/t_var_bad_sv.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier.
 %Error: t/t_var_bad_sv.v:8: syntax error, unexpected '(', expecting ')'
 %Error: Exiting due to