diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index 2691e9acf..0a85765c7 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -1174,7 +1174,7 @@ List Of Warnings Warns that a feature requires a newer standard of Verilog or SystemVerilog than the one specified by the :vlopt:`--language` option. For example, unsized - unbased literals (`'0`, `'1`, `'z`, `'x`) require 1800-2005 or later. + unbased literals (`'0`, `'1`, `'z`, `'x`) require IEEE 1800-2005 or later. To avoid this warning, use a Verilog or SystemVerilog standard that supports the feature. Alternatively, modify your code to use a different diff --git a/include/verilated.cpp b/include/verilated.cpp index 41a1df170..0794d4dd2 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -2094,7 +2094,7 @@ bool VlReadMem::get(QData& addrr, std::string& valuer) { if (VL_UNLIKELY(m_end != ~0ULL && m_addr <= m_end && !m_anyAddr)) { VL_WARN_MT(m_filename.c_str(), m_linenum, "", - "$readmem file ended before specified final address (IEEE 2017 21.4)"); + "$readmem file ended before specified final address (IEEE 1800-2017 21.4)"); } return false; // EOF diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp index 3f8278e5b..f99a9ced8 100644 --- a/src/V3Assert.cpp +++ b/src/V3Assert.cpp @@ -154,7 +154,7 @@ private: if (m_procedurep) { // To support this need queue of asserts to activate nodep->v3error("Unsupported: Procedural concurrent assertion with" - " clocking event inside always (IEEE 1800-2917 16.14.6)"); + " clocking event inside always (IEEE 1800-2017 16.14.6)"); } } // diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp index d0689361f..c06f3b93f 100644 --- a/src/V3AssertPre.cpp +++ b/src/V3AssertPre.cpp @@ -15,7 +15,7 @@ //************************************************************************* // Pre steps: // Attach clocks to each assertion -// Substitute property references by property body (IEEE Std 1800-2012, section 16.12.1). +// Substitute property references by property body (IEEE 1800-2012 16.12.1). // Transform clocking blocks into imperative logic //************************************************************************* diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 473545166..a6f052659 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -2127,7 +2127,7 @@ private: new AstNew{fl, nullptr}}; AstNodeStmt* const superNewStmtp = superNewp->makeStmt(); for (AstNode* stmtp = nodep->stmtsp(); stmtp; stmtp = stmtp->nextp()) { - // super.new shall be the first statement (section 8.15 of IEEE Std 1800-2017) + // super.new shall be the first statement (IEEE 1800-2017 8.15) // but some nodes (such as variable declarations and typedefs) should stay before if (VN_IS(stmtp, NodeStmt)) { stmtp->addHereThisAsNext(superNewStmtp); diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index b3371c2a3..9c9b349e2 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -573,8 +573,8 @@ private: } else if (VN_IS(bracketp, SelLoopVars)) { // Ok } else { - nodep->v3error("Syntax error; foreach missing bracketed loop variable (IEEE " - "1800-2017 12.7.3)"); + nodep->v3error("Syntax error; foreach missing bracketed loop variable" + " (IEEE 1800-2017 12.7.3)"); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); return; } diff --git a/src/V3Number.cpp b/src/V3Number.cpp index acc6e6639..91403a532 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -252,8 +252,8 @@ void V3Number::create(const char* sourcep) { << width() << " bit number: " << sourcep << '\n' << ((!sized() && !warned++) ? ( V3Error::warnMore() + "... As that number was unsized" - + " ('d...) it is limited to 32 bits (IEEE 1800-2017 " - "5.7.1)\n" + + " ('d...) it is limited to 32 bits" + " (IEEE 1800-2017 5.7.1)\n" + V3Error::warnMore() + "... Suggest adding a size to it.") : "")); while (*(cp + 1)) cp++; // Skip ahead so don't get multiple warnings diff --git a/test_regress/t/t_assert_disable_bad.v b/test_regress/t/t_assert_disable_bad.v index cb0f84b7d..07b3bc342 100644 --- a/test_regress/t/t_assert_disable_bad.v +++ b/test_regress/t/t_assert_disable_bad.v @@ -23,6 +23,6 @@ module t (/*AUTOARG*/ endproperty // Test should fail due to duplicated disable iff statements - // (IEEE Std 1800-2012, section 16.12.1). + // (IEEE 1800-2012 16.12.1). assert property (disable iff (val == 0) check(1, 1)); endmodule diff --git a/test_regress/t/t_assert_procedural_clk.out b/test_regress/t/t_assert_procedural_clk.out index 98cbce1d6..365914727 100644 --- a/test_regress/t/t_assert_procedural_clk.out +++ b/test_regress/t/t_assert_procedural_clk.out @@ -1,8 +1,8 @@ -%Error: t/t_assert_procedural_clk.v:21:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2917 16.14.6) +%Error: t/t_assert_procedural_clk.v:21:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2017 16.14.6) : ... note: In instance 't' 21 | assume property (@(posedge clk) cyc == 9); | ^~~~~~ -%Error: t/t_assert_procedural_clk.v:22:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2917 16.14.6) +%Error: t/t_assert_procedural_clk.v:22:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2017 16.14.6) : ... note: In instance 't' 22 | assume property (@(negedge clk) cyc == 9); | ^~~~~~ diff --git a/test_regress/t/t_class_param_enum_bad.v b/test_regress/t/t_class_param_enum_bad.v index 55b5e824c..8a3fe88bb 100644 --- a/test_regress/t/t_class_param_enum_bad.v +++ b/test_regress/t/t_class_param_enum_bad.v @@ -15,7 +15,7 @@ endclass module t; initial begin Converter#(enum_t) conv1 = new; - // enum types does not match with other types (sections 6.22.1 and 6.22.4 of IEEE Std 1800-2017) + // enum types does not match with other types (IEEE 1800-2017 6.22.1 and 6.22.4) // The assignment and the function call should throw an error. Converter#(bit) conv2 = conv1; conv1.toInt(0); diff --git a/test_regress/t/t_event_copy.v b/test_regress/t/t_event_copy.v index 7a26fb3d9..88882259f 100644 --- a/test_regress/t/t_event_copy.v +++ b/test_regress/t/t_event_copy.v @@ -99,7 +99,7 @@ module t(/*AUTOARG*/ // are ever pointed to by an EVENTREF. e4 = e3; // Old handle to e4 e3 = e2; // Same event, also triggers e2 - // IEEE 2017 15.5.5.1 says that this causes a merge, and the below + // IEEE 1800-2017 15.5.5.1 says that this causes a merge, and the below // should also activate the "old e3". However we could not find any // simulator that actually does this. Instead the "old e3" becomes // unreachable (via old handle), but is reachable by "e4" as assigned diff --git a/test_regress/t/t_interface_import_param.v b/test_regress/t/t_interface_import_param.v index 82969649d..043c9d184 100644 --- a/test_regress/t/t_interface_import_param.v +++ b/test_regress/t/t_interface_import_param.v @@ -1,7 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // A test that a package import declaration can preceed a parameter port list -// in an interface declaration. See 25.3 of the 1800-2017 LRM. +// in an interface declaration. See IEEE 1800-2017 25.3. // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. diff --git a/test_regress/t/t_math_arith.v b/test_regress/t/t_math_arith.v index f2c1d366e..4477c931e 100644 --- a/test_regress/t/t_math_arith.v +++ b/test_regress/t/t_math_arith.v @@ -159,7 +159,7 @@ module t (/*AUTOARG*/ if (bug764_p11 !== 4'b000x) $stop; if (~& bug764_p11 !== 1'b1) $stop; //verilator lint_on WIDTH - // However IEEE 2017 5.7.1 says for constants that smaller-sizes do extend + // However IEEE 1800-2017 5.7.1 says for constants that smaller-sizes do extend if (4'bx !== 4'bxxxx) $stop; if (4'bz !== 4'bzzzz) $stop; if (4'b1 !== 4'b0001) $stop; diff --git a/test_regress/t/t_param_array3.v b/test_regress/t/t_param_array3.v index 667276578..fe38c5ecd 100644 --- a/test_regress/t/t_param_array3.v +++ b/test_regress/t/t_param_array3.v @@ -25,7 +25,7 @@ module t; if (SUMS[1] != 4+3) $stop; if (SUMS[2] != 4+3+2) $stop; if (SUMS[3] != 4+3+2+1) $stop; - // According to section 13.4.3 of IEEE Std 1800-2017, + // According to IEEE 1800-2017 13.4.3 // execution at elaboration has no effect on the initial values // of the variables used either at simulation time or among // multiple invocations of a function at elaboration time diff --git a/test_regress/t/t_queue_method.v b/test_regress/t/t_queue_method.v index 090ac5a9f..fb05890bb 100644 --- a/test_regress/t/t_queue_method.v +++ b/test_regress/t/t_queue_method.v @@ -81,7 +81,7 @@ module t (/*AUTOARG*/); string_qv = string_q.unique(s) with (s.toupper); `checkh(string_qv.size(), 2); qi = q.unique_index; qv.sort; - // According to 7.12.1 of IEEE Std 1800-2017, it is not specified which index of duplicated value should be returned + // According to IEEE 1800-2017 7.12.1, it is not specified which index of duplicated value should be returned `checkh(qi.size(), 4); qi.delete(1); v = $sformatf("%p", qi); `checks(v, "'{'h0, 'h3, 'h4} "); diff --git a/test_regress/t/t_stream_integer_type_unsup.v b/test_regress/t/t_stream_integer_type_unsup.v index bb7c94533..91dec557e 100644 --- a/test_regress/t/t_stream_integer_type_unsup.v +++ b/test_regress/t/t_stream_integer_type_unsup.v @@ -1,5 +1,5 @@ // DESCRIPTION: Verilator: Verilog Test module -// Ref. to IEEE Std 1800-2017 11.4.14 & A.8.1 +// Ref. to IEEE 1800-2017 11.4.14 & A.8.1 // // stream pack/unpack for integer_type only // slice_size ::= simple_type | constant_expression diff --git a/test_regress/t/t_structu_dataType_assignment.v b/test_regress/t/t_structu_dataType_assignment.v index 5839b375a..6f6a32d44 100644 --- a/test_regress/t/t_structu_dataType_assignment.v +++ b/test_regress/t/t_structu_dataType_assignment.v @@ -8,17 +8,17 @@ module top(); - typedef struct { // IEEE 1800-2017 SV CH:5.10 + typedef struct { // IEEE 1800-2017 5.10 int a; shortint b; } ab_struct; - typedef struct { // IEEE 1800-2017 SV CH:10.9.2 + typedef struct { // IEEE 1800-2017 10.9.2 int x; int y; } st_struct; - typedef struct { // IEEE 1800-2017 SV CH:10.9.2 + typedef struct { // IEEE 1800-2017 10.9.2 logic [7:0] a; bit b; bit signed [31:0] c; @@ -26,7 +26,7 @@ module top(); } sa_struct; - typedef struct { // IEEE 1800-2017 SV CH:10.9.2 + typedef struct { // IEEE 1800-2017 10.9.2 int A; struct { int B, C; @@ -34,7 +34,7 @@ module top(); } DEF_struct; - typedef struct { // IEEE 1800-2017 SV CH:10.9.2 + typedef struct { // IEEE 1800-2017 10.9.2 int A; struct { int B, C; diff --git a/test_regress/t/t_structu_dataType_assignment_bad.v b/test_regress/t/t_structu_dataType_assignment_bad.v index 6ab523bbf..4733d46ca 100644 --- a/test_regress/t/t_structu_dataType_assignment_bad.v +++ b/test_regress/t/t_structu_dataType_assignment_bad.v @@ -9,7 +9,7 @@ module top(); - typedef struct { // IEEE 1800-2017 SV CH:10.9.2 + typedef struct { // IEEE 1800-2017 10.9.2 int A; struct { int B, C; diff --git a/test_regress/t/t_sys_readmem_bad_end.out b/test_regress/t/t_sys_readmem_bad_end.out index 4c6aaf01f..a9de0a692 100644 --- a/test_regress/t/t_sys_readmem_bad_end.out +++ b/test_regress/t/t_sys_readmem_bad_end.out @@ -1,2 +1,2 @@ -%Warning: t/t_sys_readmem_bad_end.mem:12: $readmem file ended before specified final address (IEEE 2017 21.4) +%Warning: t/t_sys_readmem_bad_end.mem:12: $readmem file ended before specified final address (IEEE 1800-2017 21.4) *-* All Finished *-*