From a6f608c616265ee3ed4620edd646c8d9f1f25292 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 21 Dec 2025 15:28:10 -0500 Subject: [PATCH] Tests: Add t_rand_stability_class --- test_regress/t/t_rand_stability_class.py | 18 +++++++++++++ test_regress/t/t_rand_stability_class.v | 33 ++++++++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100755 test_regress/t/t_rand_stability_class.py create mode 100644 test_regress/t/t_rand_stability_class.v diff --git a/test_regress/t/t_rand_stability_class.py b/test_regress/t/t_rand_stability_class.py new file mode 100755 index 000000000..f989a35fb --- /dev/null +++ b/test_regress/t/t_rand_stability_class.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_rand_stability_class.v b/test_regress/t/t_rand_stability_class.v new file mode 100644 index 000000000..f139994ae --- /dev/null +++ b/test_regress/t/t_rand_stability_class.v @@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + class Cls; + task test_srandom; + int i, j, k; + // $urandom is per-process thread, not affected by object stability/this.srandom(seed) + // "Each object maintains its own internal RNG, which is used exclusively by its randomize() method." + // THis was moved to t_rand_stability_class.v + this.srandom(1234); + i = $urandom; + this.srandom(1234); + j = $urandom; + this.srandom(1234); + k = $urandom; + if (i == j && i == k) $stop; // Small chance randomly i == j, or j == k + endtask + endclass + + Cls c1; + + initial begin + c1 = new; + c1.test_srandom; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule