diff --git a/src/verilog.l b/src/verilog.l index 085edd87d..fbc690583 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -567,6 +567,7 @@ escid \\[^ \t\f\r\n]+ "~^" {yylval.fileline = CRELINE(); return yP_XNOR;} "~&" {yylval.fileline = CRELINE(); return yP_NAND;} "~|" {yylval.fileline = CRELINE(); return yP_NOR;} + "->" {yylval.fileline = CRELINE(); return yP_MINUSGT;} } /* Verilog 2001 Operators */ @@ -588,7 +589,6 @@ escid \\[^ \t\f\r\n]+ { "{" {yylval.fileline = CRELINE(); return yPSL_BRA;} // Avoid parser hitting concatenate. "}" {yylval.fileline = CRELINE(); return yPSL_KET;} // Avoid parser hitting concatenate. - "->" {yylval.fileline = CRELINE(); return yP_LOGIF;} "<->" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} //Unsup in other tools "[*" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_STAR "[*]" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_STAR_KET diff --git a/src/verilog.y b/src/verilog.y index 8bbcee967..ca4483fe5 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -256,7 +256,7 @@ class AstSenTree; //******************** // PSL op precedence -%right yP_LOGIF yP_LOGIFF +%right yP_MINUSGT yP_LOGIFF /* MinusGT == -> == PSL LogIf operator */ %right yP_OR_MINUS_GT yP_OR_EQ_GT %left prPSLCLK @@ -927,7 +927,7 @@ exprNoStr: expr yP_OROR expr { $$ = new AstLogOr ($2,$1,$3); } | expr '/' expr { $$ = new AstDiv ($2,$1,$3); } | expr '%' expr { $$ = new AstModDiv ($2,$1,$3); } | expr yP_POW expr { $$ = new AstPow ($2,$1,$3); } - | expr yP_LOGIF expr { $$ = new AstLogIf ($2,$1,$3); } + | expr yP_MINUSGT expr { $$ = new AstLogIf ($2,$1,$3); } | expr yP_LOGIFF expr { $$ = new AstLogIff ($2,$1,$3); } | '-' expr %prec prUNARYARITH { $$ = new AstUnaryMin ($1,$2); } @@ -1113,7 +1113,7 @@ specifyJunk: dlyTerm {} /* ignored */ | yP_PLUSCOLON {} | yP_MINUSCOLON {} | yP_POW {} - | yP_LOGIF {} + | yP_MINUSGT {} | yP_LOGIFF {} | yPSL_BRA {} | yPSL_KET {}