diff --git a/test_regress/t/t_param_width_loc_bad.out b/test_regress/t/t_param_width_loc_bad.out
new file mode 100644
index 000000000..f29a54f07
--- /dev/null
+++ b/test_regress/t/t_param_width_loc_bad.out
@@ -0,0 +1,19 @@
+%Warning-WIDTH: t/t_param_width_loc_bad.v:22: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
+                                              : ... In instance t.test_i
+    parameter logic param = 1'b0
+                    ^~~~~
+                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
+%Error: Exiting due to
+
+# I believe this warning message should be pointing to line 12 instead, i.e., wherever the wrongly sized parameter is given as an input rather than the parameter definition.
+# It would be more informative if it looked like this:
+
+%Warning-WIDTH: t/t_param_width_loc_bad.v:12: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
+      test #(.param(32'd0)) test_i;
+                    ^~~~
+                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
+%Error: Exiting due to
+
+
+
+
diff --git a/test_regress/t/t_param_width_loc_bad.pl b/test_regress/t/t_param_width_loc_bad.pl
new file mode 100755
index 000000000..1611882c2
--- /dev/null
+++ b/test_regress/t/t_param_width_loc_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug1624");
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_param_width_loc_bad.v b/test_regress/t/t_param_width_loc_bad.v
new file mode 100644
index 000000000..70b175888
--- /dev/null
+++ b/test_regress/t/t_param_width_loc_bad.v
@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Driss Hafdi.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   test #(.param(32'd0)) test_i;
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+module test
+  #(
+    parameter logic param = 1'b0
+    ) ();
+endmodule