diff --git a/test_regress/t/t_trace_counter.v b/test_regress/t/t_trace_counter.v new file mode 100644 index 000000000..efc5c4d88 --- /dev/null +++ b/test_regress/t/t_trace_counter.v @@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2025 by Antmicro. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module t ( + // Outputs + state, + // Inputs + clk); + + input clk; + reg rst; + output [7:0] state; + + counter c0 ( + .clk (clk), + .rst (rst), + .out (state)); + + int cyc; + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + rst <= 1; + end + else if (cyc == 10) begin + rst <= 0; + end + else if (cyc == 11) begin + rst <= 1; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + +module counter ( + input clk, + input rst, + output reg[7:0] out); + + always @ (posedge clk) begin + if (!rst) + out <= 0; + else + out <= out + 1; + end +endmodule diff --git a/test_regress/t/t_trace_counter_saif.py b/test_regress/t/t_trace_counter_saif.py new file mode 100755 index 000000000..c551cc91d --- /dev/null +++ b/test_regress/t/t_trace_counter_saif.py @@ -0,0 +1,22 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test module +# +# Copyright 2025 by Antmicro. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_trace_counter.v" + +test.compile(verilator_flags2=['--cc --trace-saif']) + +test.execute() + +#TODO: add function checking if two SAIF files are identical +#test.saif_identical(test.trace_filename, test.golden_filename) + +test.passes()