From a2b125a33eec3c9c55f66b331a65c518f3c388f9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=EC=9D=B4=EC=9E=AC=EC=9A=B1?= <126692701+skku970412@users.noreply.github.com> Date: Tue, 7 Jul 2026 08:37:45 +0900 Subject: [PATCH] Fix display of streaming concat arguments --- src/V3Width.cpp | 4 ++++ test_regress/t/t_display_stream_bad.out | 6 ++++++ test_regress/t/t_display_stream_bad.py | 16 ++++++++++++++++ test_regress/t/t_display_stream_bad.v | 13 +++++++++++++ 4 files changed, 39 insertions(+) create mode 100644 test_regress/t/t_display_stream_bad.out create mode 100755 test_regress/t/t_display_stream_bad.py create mode 100644 test_regress/t/t_display_stream_bad.v diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 802fe155d..9d3c02a4b 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -8567,6 +8567,10 @@ class WidthVisitor final : public VNVisitor { ch = std::tolower(ch); switch (ch) { case '?': // Unspecified by user, guess + if (VN_IS(subargp, StreamL) || VN_IS(subargp, StreamR)) { + subargp->v3error("Streaming concatenation cannot be used as an implicit " + "$display-like argument."); + } if (dtypep->isDouble()) { ch = 'g'; } else if (dtypep->isString()) { diff --git a/test_regress/t/t_display_stream_bad.out b/test_regress/t/t_display_stream_bad.out new file mode 100644 index 000000000..0b92967eb --- /dev/null +++ b/test_regress/t/t_display_stream_bad.out @@ -0,0 +1,6 @@ +%Error: t/t_display_stream_bad.v:11:15: Streaming concatenation cannot be used as an implicit $display-like argument. + : ... note: In instance 't' + 11 | $display({<<{value}}); + | ^~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_display_stream_bad.py b/test_regress/t/t_display_stream_bad.py new file mode 100755 index 000000000..38cf36b43 --- /dev/null +++ b/test_regress/t/t_display_stream_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_display_stream_bad.v b/test_regress/t/t_display_stream_bad.v new file mode 100644 index 000000000..a9b7e5a04 --- /dev/null +++ b/test_regress/t/t_display_stream_bad.v @@ -0,0 +1,13 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + int value = 1; + + initial begin + $display({<<{value}}); + end +endmodule