diff --git a/Changes b/Changes
index dfcdfcd1f..f3ad483c2 100644
--- a/Changes
+++ b/Changes
@@ -17,6 +17,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***   Inline C functions that are used only once, msg1525. [Jie Xu]
 
+****  Fix bare generates in interfaces, bug789. [Bob Newgard]
+
 
 * Verilator 3.866 2014-11-15
 
diff --git a/src/verilog.y b/src/verilog.y
index 61ada34a1..d77a53d6c 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -971,7 +971,8 @@ interface_itemList<nodep>:
 interface_item<nodep>:		// IEEE: interface_item + non_port_interface_item
 		port_declaration ';'			{ $$ = $1; }
 	//			// IEEE: non_port_interface_item
-	//UNSUP	generate_region				{ $$ = $1; }
+	//			// IEEE: generate_region
+	|	interface_generate_region		{ $$ = $1; }
 	|	interface_or_generate_item		{ $$ = $1; }
 	//UNSUP	program_declaration			{ $$ = $1; }
 	//UNSUP	interface_declaration			{ $$ = $1; }
@@ -980,6 +981,11 @@ interface_item<nodep>:		// IEEE: interface_item + non_port_interface_item
 	|	module_common_item			{ $$ = $1; }
 	;
 
+interface_generate_region<nodep>:		// ==IEEE: generate_region
+		yGENERATE interface_itemList yENDGENERATE	{ $$ = new AstGenerate($1, $2); }
+	|	yGENERATE yENDGENERATE			{ $$ = NULL; }
+	;
+
 interface_or_generate_item<nodep>:  // ==IEEE: interface_or_generate_item
 	//			    // module_common_item in interface_item, as otherwise duplicated
 	//			    // with module_or_generate_item's module_common_item
diff --git a/test_regress/t/t_interface_gen4.pl b/test_regress/t/t_interface_gen4.pl
new file mode 100755
index 000000000..1118f2e0e
--- /dev/null
+++ b/test_regress/t/t_interface_gen4.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_gen4.v b/test_regress/t/t_interface_gen4.v
new file mode 100644
index 000000000..7678ac0a2
--- /dev/null
+++ b/test_regress/t/t_interface_gen4.v
@@ -0,0 +1,58 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2013 by Wilson Snyder.
+
+// bug789 generates
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc=1;
+
+   ifc #(1) itopa();
+   ifc #(2) itopb();
+
+   sub #(1) ca (.isub(itopa),
+		.i_value(4));
+   sub #(2) cb (.isub(itopb),
+		.i_value(5));
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc==1) begin
+	 if (itopa.MODE != 1) $stop;
+	 if (itopb.MODE != 2) $stop;
+      end
+      if (cyc==20) begin
+	 if (itopa.i != 4) $stop;
+	 if (itopb.i != 5) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+endmodule
+
+module sub
+  #(parameter MODE = 0)
+   (
+    ifc isub,
+    input integer i_value
+   );
+
+   // Commercial unsupported Xmrs into scopes within interfaces
+   generate
+      always_comb isub.i = i_value;
+   endgenerate
+endmodule
+
+interface ifc;
+   parameter MODE = 0;
+   // Commercial unsupported Xmrs into scopes within interfaces
+   generate
+      integer 	  i;
+   endgenerate
+endinterface