diff --git a/test_regress/t/t_const_op_red_scope.v b/test_regress/t/t_const_op_red_scope.v
index 7ac8d9699..5e43e01c1 100644
--- a/test_regress/t/t_const_op_red_scope.v
+++ b/test_regress/t/t_const_op_red_scope.v
@@ -1,19 +1,7 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// Use this file as a template for submitting bugs, etc.
-// This module takes a single clock input, and should either
-//      $write("*-* All Finished *-*\n");
-//      $finish;
-// on success, or $stop.
-//
-// The code as shown applies a random vector to the Test
-// module, then calculates a CRC on the Test module's outputs.
-//
-// **If you do not wish for your code to be released to the public
-// please note it here, otherwise:**
-//
 // This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2021 by ____YOUR_NAME_HERE____.
+// any use, without warranty, 2021 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
 module t(/*AUTOARG*/
diff --git a/test_regress/t/t_genfor_signed.v b/test_regress/t/t_genfor_signed.v
index e79d64bac..bcddeb761 100644
--- a/test_regress/t/t_genfor_signed.v
+++ b/test_regress/t/t_genfor_signed.v
@@ -1,19 +1,7 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// Use this file as a template for submitting bugs, etc.
-// This module takes a single clock input, and should either
-//      $write("*-* All Finished *-*\n");
-//      $finish;
-// on success, or $stop.
-//
-// The code as shown applies a random vector to the Test
-// module, then calculates a CRC on the Test module's outputs.
-//
-// **If you do not wish for your code to be released to the public
-// please note it here, otherwise:**
-//
 // This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2020 by ____YOUR_NAME_HERE____.
+// any use, without warranty, 2020 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
 module t #
diff --git a/test_regress/t/t_string_dyn_num.v b/test_regress/t/t_string_dyn_num.v
index 639c578a1..1a36dc7bb 100644
--- a/test_regress/t/t_string_dyn_num.v
+++ b/test_regress/t/t_string_dyn_num.v
@@ -1,17 +1,5 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// Use this file as a template for submitting bugs, etc.
-// This module takes a single clock input, and should either
-//      $write("*-* All Finished *-*\n");
-//      $finish;
-// on success, or $stop.
-//
-// The code as shown applies a random vector to the Test
-// module, then calculates a CRC on the Test module's outputs.
-//
-// **If you do not wish for your code to be released to the public
-// please note it here, otherwise:**
-//
 // This file ONLY is placed under the Creative Commons Public Domain, for
 // any use, without warranty, 2022 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
diff --git a/test_regress/t/t_string_repl.v b/test_regress/t/t_string_repl.v
index eb148644a..b385ca09a 100644
--- a/test_regress/t/t_string_repl.v
+++ b/test_regress/t/t_string_repl.v
@@ -1,17 +1,5 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// Use this file as a template for submitting bugs, etc.
-// This module takes a single clock input, and should either
-//      $write("*-* All Finished *-*\n");
-//      $finish;
-// on success, or $stop.
-//
-// The code as shown applies a random vector to the Test
-// module, then calculates a CRC on the Test module's outputs.
-//
-// **If you do not wish for your code to be released to the public
-// please note it here, otherwise:**
-//
 // This file ONLY is placed under the Creative Commons Public Domain, for
 // any use, without warranty, 2023 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
diff --git a/test_regress/t/t_type_non_type.v b/test_regress/t/t_type_non_type.v
index 730f1c314..2aca3bc16 100644
--- a/test_regress/t/t_type_non_type.v
+++ b/test_regress/t/t_type_non_type.v
@@ -1,17 +1,5 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// Use this file as a template for submitting bugs, etc.
-// This module takes a single clock input, and should either
-//      $write("*-* All Finished *-*\n");
-//      $finish;
-// on success, or $stop.
-//
-// The code as shown applies a random vector to the Test
-// module, then calculates a CRC on the Test module's outputs.
-//
-// **If you do not wish for your code to be released to the public
-// please note it here, otherwise:**
-//
 // This file ONLY is placed under the Creative Commons Public Domain, for
 // any use, without warranty, 2025 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
diff --git a/test_regress/t/t_unpacked_struct_eq.v b/test_regress/t/t_unpacked_struct_eq.v
index b2a064a65..2394909f5 100644
--- a/test_regress/t/t_unpacked_struct_eq.v
+++ b/test_regress/t/t_unpacked_struct_eq.v
@@ -1,17 +1,5 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
-// Use this file as a template for submitting bugs, etc.
-// This module takes a single clock input, and should either
-//      $write("*-* All Finished *-*\n");
-//      $finish;
-// on success, or $stop.
-//
-// The code as shown applies a random vector to the Test
-// module, then calculates a CRC on the Test module's outputs.
-//
-// **If you do not wish for your code to be released to the public
-// please note it here, otherwise:**
-//
 // This file ONLY is placed under the Creative Commons Public Domain, for
 // any use, without warranty, 2023 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0