diff --git a/test_regress/t/t_lint_multidriven_taskcall_bad.v b/test_regress/t/t_lint_multidriven_taskcall_bad.v
index b7943087a..1d693acd1 100644
--- a/test_regress/t/t_lint_multidriven_taskcall_bad.v
+++ b/test_regress/t/t_lint_multidriven_taskcall_bad.v
@@ -5,10 +5,10 @@
 // SPDX-License-Identifier: CC0-1.0
 
 module t (
-  input  logic sel,
-  input  logic sel2,
-  input  logic d,
-  output logic out
+    input logic sel,
+    input logic sel2,
+    input logic d,
+    output logic out
 );
 
   task automatic do_stuff(input logic din);
@@ -23,10 +23,10 @@ module t (
 
   // Driver #2 (separate process)
   // I only want the MULTIDRIVEN.
-/* verilator lint_off LATCH */
+  /* verilator lint_off LATCH */
   always_comb begin
     if (sel2) out = 1'b1;
   end
-/* verilator lint_on LATCH */
+  /* verilator lint_on LATCH */
 
 endmodule
diff --git a/test_regress/t/t_multidriven_class.v b/test_regress/t/t_multidriven_class.v
index 9e93c55b6..65e0bb3a1 100644
--- a/test_regress/t/t_multidriven_class.v
+++ b/test_regress/t/t_multidriven_class.v
@@ -24,9 +24,10 @@ class C0;
   endtask
 endclass
 
-module class0 #()(
-  input logic sel
-  ,output logic val
+module class0 #(
+) (
+    input logic sel,
+    output logic val
 );
 
   logic l0;
@@ -57,9 +58,10 @@ class C1;
   endtask
 endclass
 
-module class1 #()(
-  input logic sel
-  ,output logic val
+module class1 #(
+) (
+    input logic sel,
+    output logic val
 );
 
   logic l0;
@@ -87,10 +89,11 @@ class C2;
   endtask
 endclass
 
-module class2 #()(
-  input logic sel
-  ,output logic val
-  ,C2 c
+module class2 #(
+) (
+    input logic sel,
+    output logic val,
+    C2 c
 );
 
   logic l0;
@@ -115,9 +118,10 @@ class C3;
   endtask
 endclass
 
-module class3 #()(
-  input logic sel
-  ,output logic val
+module class3 #(
+) (
+    input logic sel,
+    output logic val
 );
 
   logic l0;
@@ -152,9 +156,10 @@ class C4Outer;
   endtask
 endclass
 
-module class4 #()(
-  input logic sel
-  ,output logic val
+module class4 #(
+) (
+    input logic sel,
+    output logic val
 );
 
   logic l0;
@@ -182,9 +187,10 @@ class Cf0;
   endfunction
 endclass
 
-module classf0 #()(
-  input logic sel
-  ,output logic val
+module classf0 #(
+) (
+    input logic sel,
+    output logic val
 );
 
   logic l0;
@@ -212,9 +218,10 @@ class Cf1;
   endfunction
 endclass
 
-module classf1 #()(
-  input logic sel
-  ,output logic val
+module classf1 #(
+) (
+    input logic sel,
+    output logic val
 );
 
   logic l0;
@@ -233,7 +240,7 @@ endmodule
 //----------------------------------------------------------------------
 // Shared TB
 
-module m_tb#()();
+module m_tb #() ();
 
   logic sel;
 
@@ -242,13 +249,35 @@ module m_tb#()();
   C2 c2;
   initial c2 = new;
 
-  class0 u0(.sel(sel), .val(val0));
-  class1 u1(.sel(sel), .val(val1));
-  class2 u2(.sel(sel), .val(val2), .c(c2));
-  class3 u3(.sel(sel), .val(val3));
-  class4 u4(.sel(sel), .val(val4));
-  classf0 uf0(.sel(sel), .val(valf0));
-  classf1 uf1(.sel(sel), .val(valf1));
+  class0 u0 (
+      .sel(sel),
+      .val(val0)
+  );
+  class1 u1 (
+      .sel(sel),
+      .val(val1)
+  );
+  class2 u2 (
+      .sel(sel),
+      .val(val2),
+      .c(c2)
+  );
+  class3 u3 (
+      .sel(sel),
+      .val(val3)
+  );
+  class4 u4 (
+      .sel(sel),
+      .val(val4)
+  );
+  classf0 uf0 (
+      .sel(sel),
+      .val(valf0)
+  );
+  classf1 uf1 (
+      .sel(sel),
+      .val(valf1)
+  );
 
   task automatic check_all(input logic exp);
     `checkd(val0, exp);
diff --git a/test_regress/t/t_multidriven_funcret0.v b/test_regress/t/t_multidriven_funcret0.v
index 0e82e300b..cd8e4a616 100644
--- a/test_regress/t/t_multidriven_funcret0.v
+++ b/test_regress/t/t_multidriven_funcret0.v
@@ -9,8 +9,10 @@
 // Minimal reproducer for: package function with "return expr" used in always_comb expression.
 // The function return variable must not be treated as a side-effect "writeSummary" target.
 
+// verilog_format: off
 `define stop $stop
 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
+// verilog_format: on
 
 package p;
   function automatic int num_bytes(input int size);
@@ -21,7 +23,7 @@ endpackage
 module t;
   typedef struct packed {
     logic [31:0] addr;
-    logic [2:0]  size;
+    logic [2:0] size;
   } meta_t;
 
   meta_t rd_meta_q;
diff --git a/test_regress/t/t_multidriven_iface.v b/test_regress/t/t_multidriven_iface.v
index 4a028ac9f..fb57c93e5 100644
--- a/test_regress/t/t_multidriven_iface.v
+++ b/test_regress/t/t_multidriven_iface.v
@@ -17,15 +17,20 @@
 
 interface my_if0;
   logic l0;
-  task set_l0_1(); l0 = 1'b1; endtask
-  task set_l0_0(); l0 = 1'b0; endtask
+  task set_l0_1();
+    l0 = 1'b1;
+  endtask
+  task set_l0_0();
+    l0 = 1'b0;
+  endtask
 endinterface
 
-module iface0 #()(
-  input logic sel,
-  output logic val
+module iface0 #(
+) (
+    input logic sel,
+    output logic val
 );
-  my_if0 if0();
+  my_if0 if0 ();
   always_comb begin
     if0.l0 = 1'b0;
     if (sel) begin
@@ -40,15 +45,20 @@ endmodule
 
 interface my_if1;
   logic l0;
-  task set_l0_1_inner(); l0 = 1'b1; endtask
-  task set_l0_1_outer(); set_l0_1_inner(); endtask
+  task set_l0_1_inner();
+    l0 = 1'b1;
+  endtask
+  task set_l0_1_outer();
+    set_l0_1_inner();
+  endtask
 endinterface
 
-module iface1 #()(
-  input logic sel,
-  output logic val
+module iface1 #(
+) (
+    input logic sel,
+    output logic val
 );
-  my_if1 if0();
+  my_if1 if0 ();
   always_comb begin
     if0.l0 = 1'b0;
     if (sel) begin
@@ -63,14 +73,19 @@ endmodule
 
 interface my_if2;
   logic l0;
-  task set_l0_1(); l0 = 1'b1; endtask
-  task set_l0_0(); l0 = 1'b0; endtask
+  task set_l0_1();
+    l0 = 1'b1;
+  endtask
+  task set_l0_0();
+    l0 = 1'b0;
+  endtask
 endinterface
 
-module iface2 #()(
-  input logic sel,
-  output logic val,
-  my_if2 ifp
+module iface2 #(
+) (
+    input logic sel,
+    output logic val,
+    my_if2 ifp
 );
   always_comb begin
     ifp.l0 = 1'b0;
@@ -86,17 +101,17 @@ endmodule
 
 interface my_if3;
   logic l0;
-  task set_l0_1(); l0 = 1'b1; endtask
-  modport mp (
-    output l0,
-    import set_l0_1
-  );
+  task set_l0_1();
+    l0 = 1'b1;
+  endtask
+  modport mp(output l0, import set_l0_1);
 endinterface
 
-module iface3 #()(
-  input logic sel,
-  output logic val,
-  my_if3.mp ifp
+module iface3 #(
+) (
+    input logic sel,
+    output logic val,
+    my_if3.mp ifp
 );
   always_comb begin
     ifp.l0 = 1'b0;
@@ -117,11 +132,12 @@ interface my_if4;
   endtask
 endinterface
 
-module iface4 #()(
-  input logic sel,
-  output logic val
+module iface4 #(
+) (
+    input logic sel,
+    output logic val
 );
-  my_if4 if0();
+  my_if4 if0 ();
   always_comb begin
     if0.l0 = 1'b0;
     if (sel) begin
@@ -136,18 +152,21 @@ endmodule
 
 interface leaf_if5;
   logic l0;
-  task set1(); l0 = 1'b1; endtask
+  task set1();
+    l0 = 1'b1;
+  endtask
 endinterface
 
 interface top_if5;
-  leaf_if5 sub();
+  leaf_if5 sub ();
 endinterface
 
-module iface5 #()(
-  input logic sel,
-  output logic val
+module iface5 #(
+) (
+    input logic sel,
+    output logic val
 );
-  top_if5 if0();
+  top_if5 if0 ();
   always_comb begin
     if0.sub.l0 = 1'b0;
     if (sel) begin
@@ -162,19 +181,22 @@ endmodule
 
 interface chan_if6;
   logic b0;
-  task set1(); b0 = 1'b1; endtask
+  task set1();
+    b0 = 1'b1;
+  endtask
 endinterface
 
 interface agg_if6;
-  chan_if6 tlb();
-  chan_if6 ic();
+  chan_if6 tlb ();
+  chan_if6 ic ();
 endinterface
 
-module iface6 #()(
-  input logic sel,
-  output logic val
+module iface6 #(
+) (
+    input logic sel,
+    output logic val
 );
-  agg_if6 a();
+  agg_if6 a ();
   always_comb begin
     a.tlb.b0 = 1'b0;
     if (sel) a.tlb.set1();
@@ -185,21 +207,44 @@ endmodule
 //----------------------------------------------------------------------
 // Shared TB
 
-module m_tb#()();
+module m_tb #() ();
 
   logic sel;
   logic val0, val1, val2, val3, val4, val5, val6;
 
-  my_if2 if2();
-  my_if3 if3();
+  my_if2 if2 ();
+  my_if3 if3 ();
 
-  iface0 u0(.sel(sel), .val(val0));
-  iface1 u1(.sel(sel), .val(val1));
-  iface2 u2(.sel(sel), .val(val2), .ifp(if2));
-  iface3 u3(.sel(sel), .val(val3), .ifp(if3));
-  iface4 u4(.sel(sel), .val(val4));
-  iface5 u5(.sel(sel), .val(val5));
-  iface6 u6(.sel(sel), .val(val6));
+  iface0 u0 (
+      .sel(sel),
+      .val(val0)
+  );
+  iface1 u1 (
+      .sel(sel),
+      .val(val1)
+  );
+  iface2 u2 (
+      .sel(sel),
+      .val(val2),
+      .ifp(if2)
+  );
+  iface3 u3 (
+      .sel(sel),
+      .val(val3),
+      .ifp(if3)
+  );
+  iface4 u4 (
+      .sel(sel),
+      .val(val4)
+  );
+  iface5 u5 (
+      .sel(sel),
+      .val(val5)
+  );
+  iface6 u6 (
+      .sel(sel),
+      .val(val6)
+  );
 
   task automatic check_all(input logic exp);
     `checkd(val0, exp);
diff --git a/test_regress/t/t_multidriven_simple.v b/test_regress/t/t_multidriven_simple.v
index e1a240578..1fa431e75 100644
--- a/test_regress/t/t_multidriven_simple.v
+++ b/test_regress/t/t_multidriven_simple.v
@@ -11,9 +11,10 @@
 // verilog_format: on
 
 // direct task call
-module mod0 #()(
-  input logic sel,
-  output logic val
+module mod0 #(
+) (
+    input logic sel,
+    output logic val
 );
   logic l0;
   task do_stuff();
@@ -21,7 +22,7 @@ module mod0 #()(
   endtask
   always_comb begin
     l0 = 'b0;
-    if(sel) begin
+    if (sel) begin
       do_stuff();
     end
   end
@@ -29,9 +30,10 @@ module mod0 #()(
 endmodule
 
 // nested task call chain
-module mod1 #()(
-  input logic sel,
-  output logic val
+module mod1 #(
+) (
+    input logic sel,
+    output logic val
 );
   logic l0;
   task do_inner();
@@ -48,9 +50,10 @@ module mod1 #()(
 endmodule
 
 // task writes through an output arguement
-module mod2 #()(
-  input logic sel,
-  output logic val
+module mod2 #(
+) (
+    input logic sel,
+    output logic val
 );
   logic l0;
   task automatic do_stuff(output logic q);
@@ -64,9 +67,10 @@ module mod2 #()(
 endmodule
 
 // function call that writes
-module mod3 #()(
-  input logic sel,
-  output logic val
+module mod3 #(
+) (
+    input logic sel,
+    output logic val
 );
   logic l0;
   function automatic void do_func();
@@ -80,13 +84,18 @@ module mod3 #()(
 endmodule
 
 // two tasks set0/set1
-module mod4 #()(
-  input logic sel,
-  output logic val
+module mod4 #(
+) (
+    input logic sel,
+    output logic val
 );
   logic l0;
-  task automatic set1(); l0 = 1'b1; endtask
-  task automatic set0(); l0 = 1'b0; endtask
+  task automatic set1();
+    l0 = 1'b1;
+  endtask
+  task automatic set0();
+    l0 = 1'b0;
+  endtask
   always_comb begin
     set0();
     if (sel) begin
@@ -100,19 +109,49 @@ module m_tb;
   logic sel;
   logic v0, v1, v2, v3, v4;
 
-  mod0 u0(.sel(sel), .val(v0));
-  mod1 u1(.sel(sel), .val(v1));
-  mod2 u2(.sel(sel), .val(v2));
-  mod3 u3(.sel(sel), .val(v3));
-  mod4 u4(.sel(sel), .val(v4));
+  mod0 u0 (
+      .sel(sel),
+      .val(v0)
+  );
+  mod1 u1 (
+      .sel(sel),
+      .val(v1)
+  );
+  mod2 u2 (
+      .sel(sel),
+      .val(v2)
+  );
+  mod3 u3 (
+      .sel(sel),
+      .val(v3)
+  );
+  mod4 u4 (
+      .sel(sel),
+      .val(v4)
+  );
 
   initial begin
-    #1; sel = 0;
-    `checkd(v0, 0); `checkd(v1, 0); `checkd(v2, 0); `checkd(v3, 0); `checkd(v4, 0);
-    #1; sel = 1;
-    `checkd(v0, 1); `checkd(v1, 1); `checkd(v2, 1); `checkd(v3, 1); `checkd(v4, 1);
-    #1; sel = 0;
-    `checkd(v0, 0); `checkd(v1, 0); `checkd(v2, 0); `checkd(v3, 0); `checkd(v4, 0);
+    #1;
+    sel = 0;
+    `checkd(v0, 0);
+    `checkd(v1, 0);
+    `checkd(v2, 0);
+    `checkd(v3, 0);
+    `checkd(v4, 0);
+    #1;
+    sel = 1;
+    `checkd(v0, 1);
+    `checkd(v1, 1);
+    `checkd(v2, 1);
+    `checkd(v3, 1);
+    `checkd(v4, 1);
+    #1;
+    sel = 0;
+    `checkd(v0, 0);
+    `checkd(v1, 0);
+    `checkd(v2, 0);
+    `checkd(v3, 0);
+    `checkd(v4, 0);
     #1;
     $write("*-* All Finished *-*\n");
     $finish;