From 9e25c21fed23358a9e41cdd869eecc8aa1aadb14 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 14 Mar 2023 19:35:40 -0400
Subject: [PATCH] Fix unpacked struct clocking

---
 src/V3EmitV.cpp                      |  5 +++
 test_regress/t/t_interface_typedef.v |  1 +
 test_regress/t/t_struct_clk.pl       | 21 +++++++++++
 test_regress/t/t_struct_clk.v        | 52 ++++++++++++++++++++++++++++
 4 files changed, 79 insertions(+)
 create mode 100755 test_regress/t/t_struct_clk.pl
 create mode 100644 test_regress/t/t_struct_clk.v

diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp
index d9f05b302..61be14c49 100644
--- a/src/V3EmitV.cpp
+++ b/src/V3EmitV.cpp
@@ -510,6 +510,11 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor {
         puts(".");
         puts(nodep->prettyName());
     }
+    void visit(AstStructSel* nodep) override {
+        iterate(nodep->fromp());
+        puts(".");
+        puts(nodep->prettyName());
+    }
     void visit(AstAttrOf* nodep) override {
         putfs(nodep, "$_ATTROF(");
         iterateAndNextConstNull(nodep->fromp());
diff --git a/test_regress/t/t_interface_typedef.v b/test_regress/t/t_interface_typedef.v
index a8faecb9b..c3491894d 100644
--- a/test_regress/t/t_interface_typedef.v
+++ b/test_regress/t/t_interface_typedef.v
@@ -50,6 +50,7 @@ module sub #(
    initial begin
       struct_t substruct;
       substruct.data = '1;
+      `checkh($bits(struct_t), EXP_WIDTH);
       `checkh(substruct.data, expval);
    end
 
diff --git a/test_regress/t/t_struct_clk.pl b/test_regress/t/t_struct_clk.pl
new file mode 100755
index 000000000..859050d63
--- /dev/null
+++ b/test_regress/t/t_struct_clk.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_struct_clk.v b/test_regress/t/t_struct_clk.v
new file mode 100644
index 000000000..e09b4f3de
--- /dev/null
+++ b/test_regress/t/t_struct_clk.v
@@ -0,0 +1,52 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+typedef struct {
+   logic       clk1;
+   logic       clk2;
+   logic       rst;
+} clks_t;
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk, fastclk
+   );
+   input clk;
+   input fastclk;
+
+   int cyc = 0;
+
+   clks_t clks;
+   always_comb begin
+      clks.clk1 = clk;
+      clks.clk2 = fastclk;
+   end
+
+   // verilator lint_off MULTIDRIVEN
+   int cyc1 = 0;
+   int cyc2 = 0;
+
+   always @ (negedge clks.clk1) cyc1 <= cyc1 + 1;
+   always @ (negedge clks.clk2) cyc2 <= cyc2 + 1;
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc < 10) begin
+         cyc1 <= '0;
+         cyc2 <= '0;
+      end
+      else if (cyc == 99) begin
+         `checkd(cyc1, 90);
+         `checkd(cyc2, 90*5);
+
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule