From 9c044a918412182dcfb0fcd857e566e96b5d8902 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 11 Mar 2025 17:47:58 -0400 Subject: [PATCH] Commentary --- docs/guide/contributing.rst | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/docs/guide/contributing.rst b/docs/guide/contributing.rst index 051b69869..5aace3c78 100644 --- a/docs/guide/contributing.rst +++ b/docs/guide/contributing.rst @@ -77,8 +77,12 @@ reduce a SystemVerilog design to the smallest possible reproducer. It can be used to automatically reduce a design with hundreds of thousands of lines to a minimal test case while preserving the bug-inducing behavior. -Please refer to the `README -`_ file for more +With :vlopt:`--debug`, Verilator will write a *{prefix}*\ __inputs\ .vpp +file which has all of the individual input files combined and +pre-processed, this is often useful as the input design into `sv-bugpoint`. + +Please refer to `sv-bugpoint README +`_ for more information on how to use `sv-bugpoint`. .. Contributing