diff --git a/Changes b/Changes
index e3d2df32e..eb4a729ca 100644
--- a/Changes
+++ b/Changes
@@ -56,6 +56,7 @@ Verilator 5.035 devel
 * Fix Windows paths in Perl (#5858) (#5860). [Tobias Jensen]
 * Fix algorithm header portability in V3Os.cpp (for std::replace) (#5861). [William D. Jones]
 * Fix `$fscanf` not returning -1 on EOF (#5881).
+* Fix process comparisons (#5896).
 
 
 Verilator 5.034 2025-02-24
diff --git a/include/verilated_std.sv b/include/verilated_std.sv
index 4ef8df547..03da57ccb 100644
--- a/include/verilated_std.sv
+++ b/include/verilated_std.sv
@@ -175,6 +175,26 @@ package std;
 `endif
       endtask
 
+      // Two process references are equal if the different classes' containing
+      // m_process are equal. Can't yet use <=> as the base class template
+      // comparisons doesn't define <=> as they don't yet require --timing and C++20.
+`ifdef VERILATOR_TIMING
+`systemc_header_post
+template<> template<>
+bool VlClassRef<`systemc_class_name>::operator==(const VlClassRef<`systemc_class_name>& rhs) const {
+    return m_objp->__PVT__m_process == rhs.m_objp->__PVT__m_process;
+};
+template<> template<>
+bool VlClassRef<`systemc_class_name>::operator!=(const VlClassRef<`systemc_class_name>& rhs) const {
+    return m_objp->__PVT__m_process != rhs.m_objp->__PVT__m_process;
+};
+template<> template<>
+bool VlClassRef<`systemc_class_name>::operator<(const VlClassRef<`systemc_class_name>& rhs) const {
+    return m_objp->__PVT__m_process < rhs.m_objp->__PVT__m_process;
+};
+`verilog
+`endif
+
       // When really implemented, srandom must operate on the process, but for
       // now rely on the srandom() that is automatically generated for all
       // classes.
diff --git a/test_regress/t/t_process_compare.py b/test_regress/t/t_process_compare.py
new file mode 100755
index 000000000..bd059b0f2
--- /dev/null
+++ b/test_regress/t/t_process_compare.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_process_compare.v b/test_regress/t/t_process_compare.v
new file mode 100644
index 000000000..ab2b7e233
--- /dev/null
+++ b/test_regress/t/t_process_compare.v
@@ -0,0 +1,40 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class A;
+   local process proc2;
+   task run;
+      process proc1;
+      proc1 = process::self();
+
+      if (proc2 == null) begin
+         proc2 = proc1;
+      end
+      else if (proc1 == proc2) begin
+         $display("process is equal %p %p", proc1, proc2);
+      end
+      else begin
+         $display("process is not equal (using ! ==) %p %p", proc1, proc2);
+         $stop;
+      end
+
+      if (proc2 != null && proc1 != proc2) begin
+         $display("process is not equal (using !=) %p %p", proc1, proc2);
+         $stop;
+      end
+   endtask
+endclass
+
+module t;
+   initial begin
+      A a;
+      a = new();
+      a.run();
+      a.run();
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule