diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 9c22ac4a9..c310de4ec 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -2274,8 +2274,6 @@ class ConstVisitor final : public VNVisitor {
             if (VN_IS(dstDTypep, UnpackArrayDType)) {
                 streamp = new AstCvtPackedToArray{nodep->fileline(), streamp, dstDTypep};
             } else {
-                UASSERT_OBJ(sWidth >= dWidth, nodep,
-                            "sWidth >= dWidth should have caused an error earlier");
                 if (dWidth == 0) {
                     streamp = new AstCvtPackedToArray{nodep->fileline(), streamp, dstDTypep};
                 } else if (sWidth >= dWidth) {
diff --git a/test_regress/t/t_stream_queue.py b/test_regress/t/t_stream_queue.py
new file mode 100755
index 000000000..f989a35fb
--- /dev/null
+++ b/test_regress/t/t_stream_queue.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_stream_queue.v b/test_regress/t/t_stream_queue.v
new file mode 100644
index 000000000..5d5e76d7f
--- /dev/null
+++ b/test_regress/t/t_stream_queue.v
@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+  int i_header;
+  int i_len;
+  byte i_data[];
+  int i_crc;
+
+  int o_header;
+  int o_len;
+  byte o_data[];
+  int o_crc;
+
+  initial begin
+    byte pkt[$];
+
+    i_header = 12;
+    i_len = 5;
+    i_data = new[5];
+    i_crc = 42;
+
+    pkt = {<<8{i_header, i_len, i_data, i_crc}};
+
+    {<<8{o_header, o_len, o_data, o_crc}} = pkt;
+
+    $finish;
+  end
+
+endmodule