diff --git a/include/verilated_timing.cpp b/include/verilated_timing.cpp
index c84ce508e..b55086416 100644
--- a/include/verilated_timing.cpp
+++ b/include/verilated_timing.cpp
@@ -67,19 +67,6 @@ void VlDelayScheduler::resume() {
         resumed = true;
     }
 
-    if (!m_zeroDelayed.empty()) {
-        // First, we need to move the coroutines out of the queue, as a resumed coroutine can
-        // suspend on #0 again, adding itself to the queue, which can result in reallocating the
-        // queue mid-iteration.
-        // We swap with the m_zeroDlyResumed field to keep the allocated buffer.
-        m_zeroDlyResumed.swap(m_zeroDelayed);
-        for (auto&& handle : m_zeroDlyResumed) handle.resume();
-        m_zeroDlyResumed.clear();
-        resumed = true;
-        // We are now in the Active region, so any coroutines added to m_zeroDelayed in the
-        // meantime will have to wait until the next Inactive region.
-    }
-
     if (!resumed) {
         if (m_context.time() == 0) {
             // Nothing was scheduled at time 0, but resume() got called due to --x-initial-edge
@@ -92,6 +79,12 @@ void VlDelayScheduler::resume() {
     }
 }
 
+void VlDelayScheduler::resumeZeroDelay() {
+    m_zeroDelayesSwap.swap(m_zeroDelayed);
+    for (VlCoroutineHandle& handle : m_zeroDelayesSwap) handle.resume();
+    m_zeroDelayesSwap.clear();
+}
+
 uint64_t VlDelayScheduler::nextTimeSlot() const {
     if (!m_queue.empty()) return m_queue.cbegin()->first;
     if (m_zeroDelayed.empty())
diff --git a/include/verilated_timing.h b/include/verilated_timing.h
index 203d25000..faceb8926 100644
--- a/include/verilated_timing.h
+++ b/include/verilated_timing.h
@@ -170,9 +170,8 @@ class VlDelayScheduler final {
     VerilatedContext& m_context;
     VlDelayedCoroutineQueue m_queue;  // Coroutines to be restored at a certain simulation time
     std::vector<VlCoroutineHandle> m_zeroDelayed;  // Coroutines waiting for #0
-    std::vector<VlCoroutineHandle> m_zeroDlyResumed;  // Coroutines that waited for #0 and are
-                                                      // to be resumed. Kept as a field to avoid
-                                                      // reallocation.
+    // Coroutines that waited for #0 and are being resumed now. As member to avoid reallocations
+    std::vector<VlCoroutineHandle> m_zeroDelayesSwap;
 
 public:
     // CONSTRUCTORS
@@ -181,6 +180,8 @@ public:
     // METHODS
     // Resume coroutines waiting for the current simulation time
     void resume();
+    // Resume coroutines waiting for #0
+    void resumeZeroDelay();
     // Returns the simulation time of the next time slot (aborts if there are no delayed
     // coroutines)
     uint64_t nextTimeSlot() const;
@@ -188,9 +189,10 @@ public:
     bool empty() const { return m_queue.empty() && m_zeroDelayed.empty(); }
     // Are there coroutines to resume at the current simulation time?
     bool awaitingCurrentTime() const {
-        return (!m_queue.empty() && (m_queue.cbegin()->first <= m_context.time()))
-               || !m_zeroDelayed.empty();
+        return (!m_queue.empty() && (m_queue.cbegin()->first <= m_context.time()));
     }
+    // Are there coroutines to resume in the inactive region after a #0 delay?
+    bool awaitingZeroDelay() const { return !m_zeroDelayed.empty(); }
 #ifdef VL_DEBUG
     void dump() const;
 #endif
@@ -217,14 +219,6 @@ public:
         };
 
         const VlDelayPhase phase = (delay == 0) ? VlDelayPhase::INACTIVE : VlDelayPhase::ACTIVE;
-#ifdef VL_DEBUG
-        if (phase == VlDelayPhase::INACTIVE) {
-            VL_WARN_MT(filename, lineno, VL_UNKNOWN,
-                       "Encountered #0 delay. #0 scheduling support is incomplete and the "
-                       "process will be resumed before combinational logic evaluation.");
-        }
-#endif
-
         return Awaitable{process,       m_queue,
                          m_zeroDelayed, m_context.time() + delay,
                          phase,         VlFileLineDebug{filename, lineno}};
diff --git a/src/V3AstAttr.h b/src/V3AstAttr.h
index 5be4c9506..93fd6249e 100644
--- a/src/V3AstAttr.h
+++ b/src/V3AstAttr.h
@@ -821,6 +821,7 @@ public:
         RNG_SET_RANDSTATE,
         SCHED_ANY_TRIGGERED,
         SCHED_AWAITING_CURRENT_TIME,
+        SCHED_AWAITING_ZERO_DELAY,
         SCHED_READY,
         SCHED_COMMIT,
         SCHED_MOVE_TO_RESUME_QUEUE,
@@ -831,6 +832,7 @@ public:
         SCHED_EVALUATION,
         SCHED_POST_UPDATE,
         SCHED_RESUME,
+        SCHED_RESUME_ZERO_DELAY,
         SCHED_RESUMPTION,
         SCHED_TRIGGER,
         UNPACKED_ASSIGN,
@@ -954,6 +956,7 @@ inline std::ostream& operator<<(std::ostream& os, const VCMethod& rhs) {
            {RNG_SET_RANDSTATE, "__Vm_rng.set_randstate", false}, \
            {SCHED_ANY_TRIGGERED, "anyTriggered", false}, \
            {SCHED_AWAITING_CURRENT_TIME, "awaitingCurrentTime", true}, \
+           {SCHED_AWAITING_ZERO_DELAY, "awaitingZeroDelay", true}, \
            {SCHED_READY, "ready", false}, \
            {SCHED_COMMIT, "commit", false}, \
            {SCHED_MOVE_TO_RESUME_QUEUE, "moveToResumeQueue", false}, \
@@ -964,6 +967,7 @@ inline std::ostream& operator<<(std::ostream& os, const VCMethod& rhs) {
            {SCHED_EVALUATION, "evaluation", false}, \
            {SCHED_POST_UPDATE, "postUpdate", false}, \
            {SCHED_RESUME, "resume", false}, \
+           {SCHED_RESUME_ZERO_DELAY, "resumeZeroDelay", false}, \
            {SCHED_RESUMPTION, "resumption", false}, \
            {SCHED_TRIGGER, "trigger", false}, \
            {UNPACKED_ASSIGN, "assign", false}, \
diff --git a/src/V3Global.h b/src/V3Global.h
index 3d806f99f..245cc05db 100644
--- a/src/V3Global.h
+++ b/src/V3Global.h
@@ -125,6 +125,7 @@ class V3Global final {
     bool m_usesProbDist = false;  // Uses $dist_*
     bool m_usesStdPackage = false;  // Design uses the std package
     bool m_usesTiming = false;  // Design uses timing constructs
+    bool m_usesZeroDelay = false;  // Design uses #0 delay (or non-constant delay)
     bool m_hasForceableSignals = false;  // Need to apply V3Force pass
     bool m_hasSystemCSections = false;  // Has AstSystemCSection that need to be emitted
     bool m_useParallelBuild = false;  // Use parallel build for model
@@ -200,6 +201,8 @@ public:
     void setUsesStdPackage() { m_usesStdPackage = true; }
     bool usesTiming() const { return m_usesTiming; }
     void setUsesTiming() { m_usesTiming = true; }
+    bool usesZeroDelay() const { return m_usesZeroDelay; }
+    void setUsesZeroDelay() { m_usesZeroDelay = true; }
     bool hasForceableSignals() const { return m_hasForceableSignals; }
     void setHasForceableSignals() { m_hasForceableSignals = true; }
     bool hasSystemCSections() const VL_MT_SAFE { return m_hasSystemCSections; }
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index 86a703515..f8b369267 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -1700,6 +1700,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc,
         if (m_reloopLimit < 2) fl->v3error("--reloop-limit must be >= 2: " << valp);
     });
     DECL_OPTION("-report-unoptflat", OnOff, &m_reportUnoptflat);
+    DECL_OPTION("-runtime-zero-delay", OnOff, &m_runtimeZeroDelay);
     DECL_OPTION("-rr", CbCall, []() {});  // Processed only in bin/verilator shell
     DECL_OPTION("-runtime-debug", CbCall, [this, fl]() {
         decorations(fl, "node");
diff --git a/src/V3Options.h b/src/V3Options.h
index c761455d5..230d743e8 100644
--- a/src/V3Options.h
+++ b/src/V3Options.h
@@ -284,6 +284,7 @@ private:
     bool m_quietStats = false;      // main switch: --quiet-stats
     bool m_relativeIncludes = false;  // main switch: --relative-includes
     bool m_reportUnoptflat = false;  // main switch: --report-unoptflat
+    VOptionBool m_runtimeZeroDelay;  // main switch: --runtime-zero-delay
     bool m_savable = false;         // main switch: --savable
     bool m_stdPackage = true;       // main switch: --std-package
     bool m_stdWaiver = true;        // main switch: --std-waiver
@@ -582,6 +583,7 @@ public:
     bool quietExit() const VL_MT_SAFE { return m_quietExit; }
     bool quietStats() const VL_MT_SAFE { return m_quietStats; }
     bool reportUnoptflat() const { return m_reportUnoptflat; }
+    VOptionBool runtimeZeroDelay() const { return m_runtimeZeroDelay; }
     bool verilate() const { return m_verilate; }
     bool vpi() const { return m_vpi; }
     bool waiverMultiline() const { return m_waiverMultiline; }
diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp
index d3bb92ca3..e79e692ad 100644
--- a/src/V3Sched.cpp
+++ b/src/V3Sched.cpp
@@ -132,7 +132,8 @@ EvalLoop createEvalLoop(
     const string& name,  // Name of current phase
     bool slow,  // Should create slow functions
     const TriggerKit& trigKit,  // The trigger kit
-    AstVarScope* trigp,  // The trigger vector - may be nullptr if no triggers
+    AstVarScope* trigp,  // The trigger vector - may be nullptr if no triggers or using 'condp'
+    AstNodeExpr* condp,  // Explicit condition that must be true to run 'phaseWorkp'
     AstNodeStmt* innerp,  // The inner loop, if any
     AstNodeStmt* phasePrepp,  // Prep statements run before checking triggers
     AstNodeStmt* phaseWorkp,  // The work to do if anything triggered
@@ -141,9 +142,11 @@ EvalLoop createEvalLoop(
     // and must be unmodified otherwise.
     std::function<AstNodeStmt*(AstVarScope*)> phaseExtra = [](AstVarScope*) { return nullptr; }  //
 ) {
-    // All work is under a trigger, so if there are no triggers, there is
-    // nothing to do besides executing the inner loop.
-    if (!trigp) return {nullptr, innerp};
+    UASSERT(!trigp || !condp, "Cannot use both 'trigp' and 'condp' in 'createEvalLoop'");
+
+    // All work is under a trigger or condition, so if there are none,
+    // there is nothing to do besides executing the inner loop.
+    if (!trigp && !condp) return {nullptr, innerp};
 
     const std::string varPrefix = "__V" + tag;
     AstScope* const scopeTopp = netlistp->topScopep()->scopep();
@@ -161,9 +164,10 @@ EvalLoop createEvalLoop(
 
         // If there is work in this phase, execute it if any triggers fired
         if (phaseWorkp) {
-            // Check if any triggers are fired, save the result
             AstNodeExpr* const lhsp = new AstVarRef{flp, executeFlagp, VAccess::WRITE};
-            AstNodeExpr* const rhsp = trigKit.newAnySetCall(trigp);
+            // If using explicit condition, that directly determines whether to execute,
+            // otherwise check if any triggers are fired
+            AstNodeExpr* const rhsp = condp ? condp : trigKit.newAnySetCall(trigp);
             phaseFuncp->addStmtsp(new AstAssign{flp, lhsp, rhsp});
 
             // Add the work
@@ -216,8 +220,8 @@ EvalLoop createEvalLoop(
         AstLoop* const loopp = new AstLoop{flp};
         stmtps->addNext(loopp);
 
-        // Check the iteration limit (aborts if exceeded)
-        AstNodeStmt* const dumpCallp = trigKit.newDumpCall(trigp, tag, false);
+        // Check the iteration limit (aborts if exceeded). Dump triggers if using triggers.
+        AstNodeStmt* dumpCallp = trigp ? trigKit.newDumpCall(trigp, tag, false) : nullptr;
         loopp->addStmtsp(util::checkIterationLimit(netlistp, name, counterp, dumpCallp));
         // Increment the iteration counter
         loopp->addStmtsp(util::incrementVar(counterp));
@@ -442,7 +446,10 @@ void createSettle(AstNetlist* netlistp, AstCFunc* const initFuncp, SenExprBuilde
 
     // Create the eval loop
     const EvalLoop stlLoop = createEvalLoop(  //
-        netlistp, "stl", "Settle", /* slow: */ true, trigKit, trigKit.vscp(),
+        netlistp, "stl", "Settle", /* slow: */ true, trigKit,
+        // Use trigger
+        trigKit.vscp(), nullptr,
+        // Explicit condition
         // Inner loop statements
         nullptr,
         // Prep statements: Compute the current 'stl' triggers
@@ -550,7 +557,9 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp,
 
     // Create the eval loop
     const EvalLoop icoLoop = createEvalLoop(  //
-        netlistp, "ico", "Input combinational", /* slow: */ false, trigKit, trigKit.vscp(),
+        netlistp, "ico", "Input combinational", /* slow: */ false, trigKit,
+        // Use trigger
+        trigKit.vscp(), nullptr,
         // Inner loop statements
         nullptr,
         // Prep statements: Compute the current 'ico' triggers
@@ -595,13 +604,18 @@ void createEval(AstNetlist* netlistp,  //
 ) {
     FileLine* const flp = netlistp->fileline();
 
+    // Grab the delay scheduler variable, if any
+    AstVarScope* const delaySchedVscp = timingKit.getDelayScheduler(netlistp);
+
     // 'createResume' consumes the contents that 'createReady' needs, so do the right order
     AstCCall* const timingReadyp = timingKit.createReady(netlistp);
     AstCCall* const timingResumep = timingKit.createResume(netlistp);
 
     // Create the active eval loop
     EvalLoop topLoop = createEvalLoop(  //
-        netlistp, "act", "Active", /* slow: */ false, trigKit, actKit.m_vscp,
+        netlistp, "act", "Active", /* slow: */ false, trigKit,
+        // Use trigger
+        actKit.m_vscp, nullptr,
         // Inner loop statements
         nullptr,
         // Prep statements
@@ -640,9 +654,54 @@ void createEval(AstNetlist* netlistp,  //
             return workp;
         }());
 
+    // Create if there are any delays, so we can check at runtime if a #0 is unexpected
+    if (delaySchedVscp) {
+        topLoop = createEvalLoop(  //
+            netlistp, "inact", "Inactive", /* slow: */ false, trigKit,
+            // Use explicit condition
+            nullptr,
+            [&]() {
+                // Run if any zero delays are pending
+                AstNodeExpr* const callp
+                    = new AstCMethodHard{flp, new AstVarRef{flp, delaySchedVscp, VAccess::READ},
+                                         VCMethod::SCHED_AWAITING_ZERO_DELAY};
+                callp->dtypeSetBit();
+                return callp;
+            }(),
+            // Inner loop statements
+            topLoop.stmtsp,
+            // Prep statements
+            nullptr,
+            // Work statements
+            [&]() -> AstNodeStmt* {
+                if (v3Global.usesZeroDelay()) {
+                    // Resume processes watiting for #0 delay
+                    AstCMethodHard* const callp = new AstCMethodHard{
+                        flp, new AstVarRef{flp, delaySchedVscp, VAccess::READWRITE},
+                        VCMethod::SCHED_RESUME_ZERO_DELAY};
+                    callp->dtypeSetVoid();
+                    return callp->makeStmt();
+                } else {
+                    // Assumption was that the design doesn't use #0 delays.
+                    // Die at run-time if it does.
+                    AstCStmt* const stmtp = new AstCStmt{flp};
+                    const FileLine* const locp = netlistp->topModulep()->fileline();
+                    const std::string& file = VIdProtect::protect(locp->filename());
+                    const std::string& line = std::to_string(locp->lineno());
+                    stmtp->add(
+                        "VL_FATAL_MT(\"" + V3OutFormatter::quoteNameControls(file) + "\", " + line
+                        + ", \"\", \"ZERODLY: Design verilated with '--no-runtime-zero-delay', "
+                        + "but #0 delay encountered at runtime\");");
+                    return stmtp;
+                }
+            }());
+    }
+
     // Create the NBA eval loop, which is the default top level loop.
     topLoop = createEvalLoop(  //
-        netlistp, "nba", "NBA", /* slow: */ false, trigKit, nbaKit.m_vscp,
+        netlistp, "nba", "NBA", /* slow: */ false, trigKit,
+        // Use trigger
+        nbaKit.m_vscp, nullptr,
         // Inner loop statements
         topLoop.stmtsp,
         // Prep statements
@@ -687,7 +746,9 @@ void createEval(AstNetlist* netlistp,  //
     if (!obsKit.empty()) {
         // Create the Observed eval loop, which becomes the top level loop.
         topLoop = createEvalLoop(  //
-            netlistp, "obs", "Observed", /* slow: */ false, trigKit, obsKit.m_vscp,
+            netlistp, "obs", "Observed", /* slow: */ false, trigKit,
+            // Use trigger
+            obsKit.m_vscp, nullptr,
             // Inner loop statements
             topLoop.stmtsp,
             // Prep statements
@@ -711,7 +772,9 @@ void createEval(AstNetlist* netlistp,  //
     if (!reactKit.empty()) {
         // Create the Reactive eval loop, which becomes the top level loop.
         topLoop = createEvalLoop(  //
-            netlistp, "react", "Reactive", /* slow: */ false, trigKit, reactKit.m_vscp,
+            netlistp, "react", "Reactive", /* slow: */ false, trigKit,
+            // Use trigger
+            reactKit.m_vscp, nullptr,
             // Inner loop statements
             topLoop.stmtsp,
             // Prep statements
diff --git a/src/V3Sched.h b/src/V3Sched.h
index 711eb4949..870d6d4a9 100644
--- a/src/V3Sched.h
+++ b/src/V3Sched.h
@@ -329,6 +329,8 @@ public:
     // Remaps external domains using the specified trigger map
     std::map<const AstVarScope*, std::vector<AstSenTree*>> remapDomains(
         const std::unordered_map<const AstSenTree*, AstSenTree*>& trigMap) const VL_MT_DISABLED;
+    // Get the delay scheduler variable
+    AstVarScope* getDelayScheduler(AstNetlist* const netlistp) VL_MT_DISABLED;
     // Creates a timing resume call (if needed, else returns null)
     AstCCall* createResume(AstNetlist* const netlistp) VL_MT_DISABLED;
     // Creates a timing ready call (if needed, else returns null)
diff --git a/src/V3SchedPartition.cpp b/src/V3SchedPartition.cpp
index c2264d0c8..1de20a5da 100644
--- a/src/V3SchedPartition.cpp
+++ b/src/V3SchedPartition.cpp
@@ -354,7 +354,14 @@ LogicRegions partition(LogicByScope& clockedLogic, LogicByScope& combinationalLo
 
     for (V3GraphVertex& vtx : graphp->vertices()) {
         if (const auto lvtxp = vtx.cast<SchedLogicVertex>()) {
-            LogicByScope& lbs = lvtxp->color() ? result.m_act : result.m_nba;
+            // Move to 'act'/'nba' based on coloring by default ...
+            bool toAct = lvtxp->color();
+            // ... however, if a #0 delay is possible, then the 'inact' region is required,
+            // in which case **EVERYTHING** that is not a Post block needs to go to 'act'.
+            // This severely limits downstream optimizations (e.g. V3LifePost), and severely
+            // reduces available parallelism in 'nba' for multi-threaded execution.
+            if (v3Global.usesZeroDelay() && !VN_IS(lvtxp->logicp(), AlwaysPost)) toAct = true;
+            LogicByScope& lbs = toAct ? result.m_act : result.m_nba;
             AstNode* const logicp = lvtxp->logicp();
             logicp->unlinkFrBack();
             lbs.add(lvtxp->scopep(), lvtxp->senTreep(), logicp);
diff --git a/src/V3SchedTiming.cpp b/src/V3SchedTiming.cpp
index 81330696b..e1c675579 100644
--- a/src/V3SchedTiming.cpp
+++ b/src/V3SchedTiming.cpp
@@ -90,8 +90,8 @@ AstCCall* TimingKit::createResume(AstNetlist* const netlistp) {
         AstIf* dlyShedIfp = nullptr;
         for (auto& p : m_lbs) {
             AstActive* const activep = p.second;
-            // Hack to ensure that #0 delays will be executed after any other `act` events.
-            // Just handle delayed coroutines last.
+            // Resume time delays last. For no particular reason other than
+            // that's what we used to do prior to proper #0 support.
             AstVarRef* const schedrefp = VN_AS(
                 VN_AS(VN_AS(activep->stmtsp(), StmtExpr)->exprp(), CMethodHard)->fromp(), VarRef);
 
@@ -113,6 +113,19 @@ AstCCall* TimingKit::createResume(AstNetlist* const netlistp) {
     return callp;
 }
 
+AstVarScope* TimingKit::getDelayScheduler(AstNetlist* const netlistp) {
+    for (auto& p : m_lbs) {
+        AstActive* const ap = p.second;
+        // TODO: this triple VN_AS expression is ridiculous
+        AstVarRef* const schedrefp
+            = VN_AS(VN_AS(VN_AS(ap->stmtsp(), StmtExpr)->exprp(), CMethodHard)->fromp(), VarRef);
+        AstVarScope* const vscp = schedrefp->varScopep();
+        if (vscp->dtypep()->basicp()->isDelayScheduler()) return vscp;
+    }
+    // None found. Design doesn't use any time delays
+    return nullptr;
+}
+
 //============================================================================
 // Creates a timing ready call (if needed, else returns null)
 
diff --git a/src/V3SchedUtil.cpp b/src/V3SchedUtil.cpp
index 16e08be75..0c5eba4d9 100644
--- a/src/V3SchedUtil.cpp
+++ b/src/V3SchedUtil.cpp
@@ -89,7 +89,7 @@ AstNodeStmt* checkIterationLimit(AstNetlist* netlistp, const string& name, AstVa
     AstNodeExpr* const condp = new AstGt{flp, counterRefp, constp};
     AstIf* const ifp = new AstIf{flp, condp};
     ifp->branchPred(VBranchPred::BP_UNLIKELY);
-    ifp->addThensp(dumpCallp);
+    if (dumpCallp) ifp->addThensp(dumpCallp);
     AstCStmt* const stmtp = new AstCStmt{flp};
     ifp->addThensp(stmtp);
     const FileLine* const locp = netlistp->topModulep()->fileline();
diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp
index 17a7244b3..16eaacb61 100644
--- a/src/V3Timing.cpp
+++ b/src/V3Timing.cpp
@@ -66,6 +66,7 @@
 
 #include "V3Const.h"
 #include "V3EmitV.h"
+#include "V3Global.h"
 #include "V3Graph.h"
 #include "V3MemberMap.h"
 #include "V3SenExprBuilder.h"
@@ -475,6 +476,8 @@ class TimingControlVisitor final : public VNVisitor {
     int m_forkCnt = 0;  // Number of forks inside a module
     bool m_underJumpBlock = false;  // True if we are inside of a jump-block
     bool m_underProcedure = false;  // True if we are under an always or initial
+    bool m_hasStaticZeroDelay = false;  // True if we have a static #0 delay
+    std::vector<FileLine*> m_unknownDelayFlps;  // Locations of AstDelay with non-constant value
 
     // Unique names
     V3UniqueNames m_dlyforkNames{"__Vdlyfork"};  // Names for temp AssignW vars
@@ -919,26 +922,58 @@ class TimingControlVisitor final : public VNVisitor {
         UASSERT_OBJ(!nodep->isCycleDelay(), nodep,
                     "Cycle delays should have been handled in V3AssertPre");
         FileLine* const flp = nodep->fileline();
-        AstNodeExpr* valuep = V3Const::constifyEdit(nodep->lhsp()->unlinkFrBack());
-        AstConst* const constp = VN_CAST(valuep, Const);
-        if (!constp || !constp->isZero()) {
-            // Scale the delay
-            const double timescaleFactor = calculateTimescaleFactor(nodep, nodep->timeunit());
-            if (valuep->dtypep()->skipRefp()->isDouble()) {
-                valuep = new AstRToIRoundS{
-                    flp, new AstMulD{flp, valuep,
-                                     new AstConst{flp, AstConst::RealDouble{}, timescaleFactor}}};
-                valuep->dtypeSetBitSized(64, VSigning::UNSIGNED);
-            } else {
-                valuep->dtypeSetBitSized(64, VSigning::UNSIGNED);
-                valuep = new AstMul{flp, valuep,
-                                    new AstConst{flp, AstConst::Unsized64{},
-                                                 static_cast<uint64_t>(timescaleFactor)}};
-            }
-        } else if (constp->num().is1Step()) {
+
+        AstNodeExpr* valuep = nodep->lhsp()->unlinkFrBack();
+        if (VN_IS(valuep, Const) && VN_AS(valuep, Const)->num().is1Step()) {
+            // #1step special case
             VL_DO_DANGLING(valuep->deleteTree(), valuep);
             valuep = new AstConst{flp, AstConst::Unsized64{}, 1};
             valuep->dtypeSetBitSized(64, VSigning::UNSIGNED);
+        } else {
+            // Scale the delay
+            const double timescaleFactorD = calculateTimescaleFactor(nodep, nodep->timeunit());
+            if (valuep->dtypep()->skipRefp()->isDouble()) {
+                AstConst* const tsfp = new AstConst{flp, AstConst::RealDouble{}, timescaleFactorD};
+                valuep = new AstMulD{flp, valuep, tsfp};
+                valuep = new AstRToIRoundS{flp, valuep};
+                valuep->dtypeSetBitSized(64, VSigning::UNSIGNED);
+            } else {
+                valuep->dtypeSetBitSized(64, VSigning::UNSIGNED);
+                const uint64_t timescaleFactorU = static_cast<uint64_t>(timescaleFactorD);
+                AstConst* const tsfp = new AstConst{flp, AstConst::Unsized64{}, timescaleFactorU};
+                valuep = new AstMul{flp, valuep, tsfp};
+            }
+            // Simplify
+            valuep = V3Const::constifyEdit(valuep);
+        }
+        // Check if a #0 delay is used
+        if (AstConst* const constp = VN_CAST(valuep, Const)) {
+            // Delay statically known constant. Check if zero
+            if (constp->num().isEqZero()) {
+                m_hasStaticZeroDelay = true;
+                if (v3Global.opt.runtimeZeroDelay().isSetFalse()) {
+                    // User promised there will not be #0 delays executed at runtime.
+                    // Trust them but warn a #0 delay statically exists.
+                    nodep->v3warn(
+                        ZERODLY,
+                        "Static #0 delay exists, but '--no-runtime-zero-delay' was given.\n"
+                            << nodep->warnMore()  //
+                            << "... Can proceed, but this will fail at runtime if executed.");
+                } else {
+                    // Sadly we have a #0
+                    v3Global.setUsesZeroDelay();
+                }
+            }
+        } else {
+            // Delay is not statically known
+            if (v3Global.opt.runtimeZeroDelay().isSetFalse()) {
+                // User promised there will not be #0 delays executed at runtime, trust them.
+            } else {
+                // Record location. We will warn if no static #0 delays used.
+                m_unknownDelayFlps.push_back(nodep->fileline());
+                // Assume it can be a #0
+                v3Global.setUsesZeroDelay();
+            }
         }
         // Replace self with a 'co_await dlySched.delay(<valuep>)'
         AstCMethodHard* const delayMethodp = new AstCMethodHard{
@@ -1329,6 +1364,27 @@ public:
     explicit TimingControlVisitor(AstNetlist* nodep)
         : m_netlistp{nodep} {
         iterate(nodep);
+
+        // If there is no static #0 in the design, but an unknown delay was found,
+        // and '--runtime-zero-delay' was not given, then warn on all unknown delays
+        // as we will be assuming they can be #0, which can cause performance degradation.
+        if (!m_hasStaticZeroDelay  //
+            && !v3Global.opt.runtimeZeroDelay().isSetTrue()  //
+            && !m_unknownDelayFlps.empty()) {
+            UASSERT_OBJ(v3Global.usesZeroDelay(), nodep, "Should have assumed can be #0");
+            for (FileLine* const flp : m_unknownDelayFlps) {
+                flp->v3warn(ZERODLY,
+                            "Value of # delay control statically unknown. Assuming it can be #0.\n"
+                                << flp->warnMore()  //
+                                << "... If all # delays are non-zero at runtime,\n"
+                                << flp->warnMore()  //
+                                << "... use '--no-runtime-zero-delay' for improved performance.\n"
+                                << flp->warnMore()  //
+                                << "... If a real #0 is expected at runtime,\n"
+                                << flp->warnMore()  //
+                                << "... use '--runtime-zero-delay' to suppress this warning.");
+            }
+        }
     }
     ~TimingControlVisitor() override = default;
 };
diff --git a/test_regress/t/t_delay_compare.v b/test_regress/t/t_delay_compare.v
index edd95b3f1..31723d1be 100644
--- a/test_regress/t/t_delay_compare.v
+++ b/test_regress/t/t_delay_compare.v
@@ -10,6 +10,7 @@ module t;
    real rtim1;
    real rtim2;
 
+   // verilator lint_off ZERODLY
    initial begin
       tim1 = 2;
       tim2 = 3;
@@ -31,5 +32,6 @@ module t;
       $write("*-* All Finished *-*\n");
       $finish;
    end
+   // verilator lint_on ZERODLY
 
 endmodule
diff --git a/test_regress/t/t_flag_runtime_zero_delay_none_bad.out b/test_regress/t/t_flag_runtime_zero_delay_none_bad.out
new file mode 100644
index 000000000..82c11c195
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_none_bad.out
@@ -0,0 +1,17 @@
+%Warning-ZERODLY: t/t_flag_runtime_zero_delay_none_bad.v:12:5: Value of # delay control statically unknown. Assuming it can be #0.
+                                                             : ... If all # delays are non-zero at runtime,
+                                                             : ... use '--no-runtime-zero-delay' for improved performance.
+                                                             : ... If a real #0 is expected at runtime,
+                                                             : ... use '--runtime-zero-delay' to suppress this warning.
+   12 |     #a;
+      |     ^
+                  ... For warning description see https://verilator.org/warn/ZERODLY?v=latest
+                  ... Use "/* verilator lint_off ZERODLY */" and lint_on around source to disable this message.
+%Warning-ZERODLY: t/t_flag_runtime_zero_delay_none_bad.v:14:5: Value of # delay control statically unknown. Assuming it can be #0.
+                                                             : ... If all # delays are non-zero at runtime,
+                                                             : ... use '--no-runtime-zero-delay' for improved performance.
+                                                             : ... If a real #0 is expected at runtime,
+                                                             : ... use '--runtime-zero-delay' to suppress this warning.
+   14 |     #a;
+      |     ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_flag_runtime_zero_delay_none_bad.py b/test_regress/t/t_flag_runtime_zero_delay_none_bad.py
new file mode 100755
index 000000000..e242acd20
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_none_bad.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile(verilator_flags2=["--binary"], fails=True, expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_flag_runtime_zero_delay_none_bad.v b/test_regress/t/t_flag_runtime_zero_delay_none_bad.v
new file mode 100644
index 000000000..1d6ca0ad7
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_none_bad.v
@@ -0,0 +1,16 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of either the GNU Lesser General Public License Version 3
+// or the Perl Artistic License Version 2.0.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+module top;
+  int a = 1;
+  initial begin
+    #a;
+    a=2;
+    #a;
+  end
+endmodule
diff --git a/test_regress/t/t_flag_runtime_zero_delay_off_bad.out b/test_regress/t/t_flag_runtime_zero_delay_off_bad.out
new file mode 100644
index 000000000..b344e8e25
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_off_bad.out
@@ -0,0 +1,7 @@
+%Warning-ZERODLY: t/t_flag_runtime_zero_delay_off_bad.v:10:11: Static #0 delay exists, but '--no-runtime-zero-delay' was given.
+                                                             : ... Can proceed, but this will fail at runtime if executed.
+   10 |   initial #0;
+      |           ^
+                  ... For warning description see https://verilator.org/warn/ZERODLY?v=latest
+                  ... Use "/* verilator lint_off ZERODLY */" and lint_on around source to disable this message.
+%Error: Exiting due to
diff --git a/test_regress/t/t_flag_runtime_zero_delay_off_bad.py b/test_regress/t/t_flag_runtime_zero_delay_off_bad.py
new file mode 100755
index 000000000..76ac341cf
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_off_bad.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile(verilator_flags2=["--binary", "--no-runtime-zero-delay"],
+             fails=True,
+             expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_flag_runtime_zero_delay_off_bad.v b/test_regress/t/t_flag_runtime_zero_delay_off_bad.v
new file mode 100644
index 000000000..e0e03f3c3
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_off_bad.v
@@ -0,0 +1,11 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of either the GNU Lesser General Public License Version 3
+// or the Perl Artistic License Version 2.0.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+module top;
+  initial #0;
+endmodule
diff --git a/test_regress/t/t_flag_runtime_zero_delay_off_run.out b/test_regress/t/t_flag_runtime_zero_delay_off_run.out
new file mode 100644
index 000000000..db76d0864
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_off_run.out
@@ -0,0 +1,6 @@
+%Warning-ZERODLY: t/t_flag_runtime_zero_delay_off_run.v:17:9: Static #0 delay exists, but '--no-runtime-zero-delay' was given.
+                                                            : ... Can proceed, but this will fail at runtime if executed.
+   17 |         #0;  
+      |         ^
+                  ... For warning description see https://verilator.org/warn/ZERODLY?v=latest
+                  ... Use "/* verilator lint_off ZERODLY */" and lint_on around source to disable this message.
diff --git a/test_regress/t/t_flag_runtime_zero_delay_off_run.py b/test_regress/t/t_flag_runtime_zero_delay_off_run.py
new file mode 100755
index 000000000..1f838cf2b
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_off_run.py
@@ -0,0 +1,21 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile(verilator_flags2=[
+    "--timing", "--main", "--exe", "--no-skip-identical", "--no-runtime-zero-delay", "-Wno-fatal"
+],
+             expect_filename=test.golden_filename)
+
+test.execute(check_finished=True)
+
+test.passes()
diff --git a/test_regress/t/t_flag_runtime_zero_delay_off_run.v b/test_regress/t/t_flag_runtime_zero_delay_off_run.v
new file mode 100644
index 000000000..c1db0b7ae
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_off_run.v
@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of either the GNU Lesser General Public License Version 3
+// or the Perl Artistic License Version 2.0.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+module top;
+  int n = 0;
+  initial begin
+    repeat (5) begin
+      #10;
+      $display("%02t tick", $time);
+      ++n;
+      if (n > 5) begin
+        #0; // Will not execute
+        $stop;
+      end
+    end
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule
diff --git a/test_regress/t/t_flag_runtime_zero_delay_off_run_bad.out b/test_regress/t/t_flag_runtime_zero_delay_off_run_bad.out
new file mode 100644
index 000000000..aef3d6ee7
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_off_run_bad.out
@@ -0,0 +1,2 @@
+%Error-ZERODLY: t/t_flag_runtime_zero_delay_off_bad.v:9: Design verilated with '--no-runtime-zero-delay', but #0 delay encountered at runtime
+Aborting...
diff --git a/test_regress/t/t_flag_runtime_zero_delay_off_run_bad.py b/test_regress/t/t_flag_runtime_zero_delay_off_run_bad.py
new file mode 100755
index 000000000..5bbcb58a8
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_off_run_bad.py
@@ -0,0 +1,20 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.top_filename = "t_flag_runtime_zero_delay_off_bad.v"
+
+test.compile(verilator_flags2=["--binary", "--no-runtime-zero-delay", "-Wno-fatal"])
+
+test.execute(fails=True, expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_flag_runtime_zero_delay_on.py b/test_regress/t/t_flag_runtime_zero_delay_on.py
new file mode 100755
index 000000000..d5526db6b
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_on.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile(verilator_flags2=["--binary", "--runtime-zero-delay"])
+
+test.execute(check_finished=True)
+
+test.passes()
diff --git a/test_regress/t/t_flag_runtime_zero_delay_on.v b/test_regress/t/t_flag_runtime_zero_delay_on.v
new file mode 100644
index 000000000..d96eadab2
--- /dev/null
+++ b/test_regress/t/t_flag_runtime_zero_delay_on.v
@@ -0,0 +1,15 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of either the GNU Lesser General Public License Version 3
+// or the Perl Artistic License Version 2.0.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+module top;
+  initial begin
+    #0;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule
diff --git a/test_regress/t/t_fork_block_item_declaration.py b/test_regress/t/t_fork_block_item_declaration.py
index 7ded63f3a..4f9081a6d 100755
--- a/test_regress/t/t_fork_block_item_declaration.py
+++ b/test_regress/t/t_fork_block_item_declaration.py
@@ -11,7 +11,7 @@ import vltest_bootstrap
 
 test.scenarios('simulator')
 
-test.compile(verilator_flags2=["--binary"])
+test.compile(verilator_flags2=["--binary", "--no-runtime-zero-delay"])
 
 test.execute()
 
diff --git a/test_regress/t/t_scheduling_0delay.out b/test_regress/t/t_scheduling_0delay.out
new file mode 100644
index 000000000..1e7bd02af
--- /dev/null
+++ b/test_regress/t/t_scheduling_0delay.out
@@ -0,0 +1,22 @@
+ 0 Waiting for 'a'
+ 5 Waiting for 'a'
+ 5 a= 1 b=11
+15 Waiting for 'a'
+15 a= 2 b=12
+25 Waiting for 'a'
+25 a= 3 b=13
+35 Waiting for 'a'
+35 a= 4 b=14
+45 Waiting for 'a'
+45 a= 5 b=15
+55 Waiting for 'a'
+55 a= 6 b=16
+65 Waiting for 'a'
+65 a= 7 b=17
+75 Waiting for 'a'
+75 a= 8 b=18
+85 Waiting for 'a'
+85 a= 9 b=19
+95 Waiting for 'a'
+95 a=10 b=20
+*-* All Finished *-*
diff --git a/test_regress/t/t_scheduling_0delay.py b/test_regress/t/t_scheduling_0delay.py
new file mode 100755
index 000000000..fe0ab6714
--- /dev/null
+++ b/test_regress/t/t_scheduling_0delay.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--binary", "--timing"])
+
+test.execute(expect_filename=test.golden_filename)
+
+test.passes()
diff --git a/test_regress/t/t_scheduling_0delay.v b/test_regress/t/t_scheduling_0delay.v
new file mode 100644
index 000000000..83698225b
--- /dev/null
+++ b/test_regress/t/t_scheduling_0delay.v
@@ -0,0 +1,42 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This program is free software; you can redistribute it and/or modify it
+// under the terms of either the GNU Lesser General Public License Version 3
+// or the Perl Artistic License Version 2.0.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+`define stop $stop
+`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: time=%t got='h%x exp='h%x\n", `__FILE__,`__LINE__, $time, (got), (exp)); `stop; end while(0)
+
+module top;
+
+  logic clk = 0;
+  always #5 clk = ~clk;
+
+  int a = 0;
+  int b;
+
+  always begin
+    $display("%2t Waiting for 'a'", $time);
+    @a;
+    b = a + 10;
+  end
+
+  always @(posedge clk) begin
+    ++a;
+  end
+
+  always @(posedge clk) begin
+    #0;
+    $display("%2t a=%2d b=%2d", $time, a, b);
+    `check(b, a + 10);
+  end
+
+  initial begin
+    #99;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule
diff --git a/test_regress/t/t_timing_debug1.out b/test_regress/t/t_timing_debug1.out
index afb059e47..3c603fba5 100644
--- a/test_regress/t/t_timing_debug1.out
+++ b/test_regress/t/t_timing_debug1.out
@@ -92,6 +92,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -105,6 +106,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -204,6 +206,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -220,6 +223,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -302,6 +306,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -316,6 +321,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -360,6 +366,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -374,6 +381,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -466,6 +474,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -482,6 +491,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -575,6 +585,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -590,6 +601,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -677,6 +689,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -691,6 +704,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -736,6 +750,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -750,6 +765,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -849,6 +865,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -865,6 +882,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -947,6 +965,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -961,6 +980,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1005,6 +1025,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -1019,6 +1040,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1111,6 +1133,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -1127,6 +1150,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1209,6 +1233,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -1223,6 +1248,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1305,6 +1331,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -1319,6 +1346,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1363,6 +1391,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -1377,6 +1406,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1469,6 +1499,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -1485,6 +1516,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1567,6 +1599,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -1581,6 +1614,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1625,6 +1659,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -1639,6 +1674,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1748,6 +1784,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -1764,6 +1801,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1808,6 +1846,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -1822,6 +1861,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1907,6 +1947,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -1921,6 +1962,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1966,6 +2008,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -1980,6 +2023,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -2079,6 +2123,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -2095,6 +2140,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -2177,6 +2223,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -2191,6 +2238,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -2235,6 +2283,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -2249,6 +2298,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -2336,6 +2386,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -2350,6 +2401,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -2442,6 +2494,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -2458,6 +2511,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -2540,6 +2594,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -2554,6 +2609,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -2598,6 +2654,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -2612,6 +2669,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -2704,6 +2762,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -2720,6 +2779,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -2802,6 +2862,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -2816,6 +2877,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -2915,6 +2977,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -2930,6 +2993,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -2974,6 +3038,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -2988,6 +3053,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -3087,6 +3153,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -3103,6 +3170,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -3185,6 +3253,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -3199,6 +3268,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -3243,6 +3313,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -3257,6 +3328,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -3349,6 +3421,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -3365,6 +3438,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -3454,6 +3528,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -3468,6 +3543,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -3512,6 +3588,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -3526,6 +3603,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -3618,6 +3696,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -3634,6 +3713,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -3716,6 +3796,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -3730,6 +3811,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -3774,6 +3856,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -3788,6 +3871,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -3880,6 +3964,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -3896,6 +3981,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -3989,6 +4075,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -4004,6 +4091,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -4087,6 +4175,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug1___024root___eval_nba
@@ -4101,6 +4190,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug1___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug1___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug1___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
diff --git a/test_regress/t/t_timing_debug2.out b/test_regress/t/t_timing_debug2.out
index 6ea056108..c06e2c359 100644
--- a/test_regress/t/t_timing_debug2.out
+++ b/test_regress/t/t_timing_debug2.out
@@ -97,6 +97,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -171,6 +172,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -188,6 +190,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -245,6 +248,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -262,6 +266,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -335,6 +340,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -352,6 +358,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -441,6 +448,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -468,6 +476,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -559,6 +568,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -584,6 +594,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -652,6 +663,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -677,6 +689,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -768,6 +781,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -793,6 +807,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -884,6 +899,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -907,6 +923,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -980,6 +997,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -997,6 +1015,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1044,6 +1063,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -1061,6 +1081,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1107,6 +1128,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -1124,6 +1146,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1195,6 +1218,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -1212,6 +1236,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1258,6 +1283,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -1275,6 +1301,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1364,6 +1391,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -1378,6 +1406,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1418,6 +1447,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -1432,6 +1462,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1499,6 +1530,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -1513,6 +1545,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1552,6 +1585,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -1566,6 +1600,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1605,6 +1640,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -1619,6 +1655,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1656,6 +1693,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -1670,6 +1708,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -1709,6 +1748,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_debug2___024root___eval_nba
@@ -1723,6 +1763,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_debug2___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_debug2___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_debug2___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
diff --git a/test_regress/t/t_timing_eval_act.out b/test_regress/t/t_timing_eval_act.out
index 1940cb07e..1d71dde4f 100644
--- a/test_regress/t/t_timing_eval_act.out
+++ b/test_regress/t/t_timing_eval_act.out
@@ -42,6 +42,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_eval_act___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_eval_act___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_eval_act___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_eval_act___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
@@ -161,6 +162,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_eval_act___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_eval_act___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_eval_act___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_eval_act___024root___trigger_anySet__act
 -V{t#,#}+    Vt_timing_eval_act___024root___eval_nba
@@ -175,6 +177,7 @@
 -V{t#,#}         No 'act' region triggers active
 -V{t#,#}+    Vt_timing_eval_act___024root___trigger_orInto__act_vec_vec
 -V{t#,#}+    Vt_timing_eval_act___024root___trigger_anySet__act
+-V{t#,#}+    Vt_timing_eval_act___024root___eval_phase__inact
 -V{t#,#}+    Vt_timing_eval_act___024root___eval_phase__nba
 -V{t#,#}+    Vt_timing_eval_act___024root___trigger_anySet__act
 -V{t#,#}End-of-eval cleanup
diff --git a/test_regress/t/t_timing_timescale.py b/test_regress/t/t_timing_timescale.py
index 55248e18d..4b3c0bda2 100755
--- a/test_regress/t/t_timing_timescale.py
+++ b/test_regress/t/t_timing_timescale.py
@@ -11,7 +11,7 @@ import vltest_bootstrap
 
 test.scenarios('simulator')
 
-test.compile(verilator_flags2=["--binary"])
+test.compile(verilator_flags2=["--binary", "--no-runtime-zero-delay"])
 
 test.execute(expect_filename=test.golden_filename)
 
diff --git a/test_regress/t/t_timing_wait_long.py b/test_regress/t/t_timing_wait_long.py
index 55248e18d..4b3c0bda2 100755
--- a/test_regress/t/t_timing_wait_long.py
+++ b/test_regress/t/t_timing_wait_long.py
@@ -11,7 +11,7 @@ import vltest_bootstrap
 
 test.scenarios('simulator')
 
-test.compile(verilator_flags2=["--binary"])
+test.compile(verilator_flags2=["--binary", "--no-runtime-zero-delay"])
 
 test.execute(expect_filename=test.golden_filename)
 
diff --git a/test_regress/t/t_timing_zerodly_unsup.py b/test_regress/t/t_timing_zerodly_2.py
similarity index 89%
rename from test_regress/t/t_timing_zerodly_unsup.py
rename to test_regress/t/t_timing_zerodly_2.py
index eb60b5cf1..b857f2819 100755
--- a/test_regress/t/t_timing_zerodly_unsup.py
+++ b/test_regress/t/t_timing_zerodly_2.py
@@ -13,6 +13,6 @@ test.scenarios('simulator')
 
 test.compile(verilator_flags2=["--exe --main --timing"])
 
-test.execute(fails=True, expect_filename=test.golden_filename)
+test.execute(check_finished=True)
 
 test.passes()
diff --git a/test_regress/t/t_timing_zerodly_unsup.v b/test_regress/t/t_timing_zerodly_2.v
similarity index 84%
rename from test_regress/t/t_timing_zerodly_unsup.v
rename to test_regress/t/t_timing_zerodly_2.v
index 906841360..b0c6417e6 100644
--- a/test_regress/t/t_timing_zerodly_unsup.v
+++ b/test_regress/t/t_timing_zerodly_2.v
@@ -4,23 +4,28 @@
 // SPDX-FileCopyrightText: 2022 Antmicro Ltd
 // SPDX-License-Identifier: CC0-1.0
 
-module t;
+module top;
   logic v;
   int num;
+  time t;
 
   initial begin
     num = 1;
     #1;
     if (v) $stop;
     num = 21;
+    t = $time;
     // Zero delay should postpone the execution and resume it after
     // evaluating combinational logic which would update `v`. However,
     // currently we can't postpone the resumption in the current timeframe
     // past the combinatorial logic evaluation as that is intertwined with
     // NBA evaluation and partitioned for multithreading. This causes `v`
     // to not have its value updated despite being checked after #0 delay.
-    #0 if (v) $finish;
-    $stop;
+    #0;
+    if (!v) $stop;
+    if (t != $time) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
   end
 
   always_comb v = (num == 21);
diff --git a/test_regress/t/t_timing_zerodly_unsup.out b/test_regress/t/t_timing_zerodly_unsup.out
deleted file mode 100644
index 8e56ef2cf..000000000
--- a/test_regress/t/t_timing_zerodly_unsup.out
+++ /dev/null
@@ -1,3 +0,0 @@
-%Warning: t/t_timing_zerodly_unsup.v:22: Encountered #0 delay. #0 scheduling support is incomplete and the process will be resumed before combinational logic evaluation.
-%Error: t/t_timing_zerodly_unsup.v:23: Verilog $stop
-Aborting...
diff --git a/test_regress/t/t_var_extern_method_lifetime.py b/test_regress/t/t_var_extern_method_lifetime.py
index 7ded63f3a..4f9081a6d 100755
--- a/test_regress/t/t_var_extern_method_lifetime.py
+++ b/test_regress/t/t_var_extern_method_lifetime.py
@@ -11,7 +11,7 @@ import vltest_bootstrap
 
 test.scenarios('simulator')
 
-test.compile(verilator_flags2=["--binary"])
+test.compile(verilator_flags2=["--binary", "--no-runtime-zero-delay"])
 
 test.execute()