diff --git a/test_regress/t/t_trace_param_saif.out b/test_regress/t/t_trace_param_saif.out
new file mode 100644
index 000000000..a3bb886d6
--- /dev/null
+++ b/test_regress/t/t_trace_param_saif.out
@@ -0,0 +1,24 @@
+(SAIFILE
+(SAIFVERSION "2.0")
+(DIRECTION "backward")
+(DESIGN "t")
+(DIVIDER / )
+(TIMESCALE 1ps)
+(DURATION 0)
+(INSTANCE top
+  (NET
+  )
+  (INSTANCE my_module_types
+    (NET
+      (MY_PARAM\[0\] (T0 0) (T1 0) (TX 0) (TC 1))
+      (MY_PARAM\[1\] (T0 0) (T1 0) (TX 0) (TC 1))
+      (MY_PARAM2\[2\] (T0 0) (T1 0) (TX 0) (TC 1))
+      (MY_PARAM2\[3\] (T0 0) (T1 0) (TX 0) (TC 1))
+    )
+  )
+  (INSTANCE t
+    (NET
+    )
+  )
+)
+)
diff --git a/test_regress/t/t_trace_param_saif.py b/test_regress/t/t_trace_param_saif.py
new file mode 100755
index 000000000..981062c76
--- /dev/null
+++ b/test_regress/t/t_trace_param_saif.py
@@ -0,0 +1,19 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt_all')
+test.top_filename = "t/t_trace_param.v"
+
+test.compile(v_flags2=["--trace-saif"])
+
+test.execute()
+
+test.passes()