diff --git a/Changes b/Changes
index 236348357..ac0e128ce 100644
--- a/Changes
+++ b/Changes
@@ -53,6 +53,7 @@ Verilator 5.045 devel
 * Fix null pointer dereference in class member trigger expressions (#6946). [Cameron Waite]
 * Fix type assignments for arrays of parameter types (#6955). [Todd Strader]
 * Fix accessing non-rand struct member in constraints (#6960). [Pawel Kojma, Antmicro Ltd.]
+* Fix associative array of events causes C++ compile error (#6962).
 
 
 Verilator 5.044 2026-01-01
diff --git a/src/V3EmitCFunc.cpp b/src/V3EmitCFunc.cpp
index 8da704cda..ce569230d 100644
--- a/src/V3EmitCFunc.cpp
+++ b/src/V3EmitCFunc.cpp
@@ -666,6 +666,8 @@ string EmitCFunc::emitVarResetRecurse(const AstVar* varp, bool constructing,
         return "";
     } else if (basicp && (basicp->isRandomGenerator() || basicp->isStdRandomGenerator())) {
         return "";
+    } else if (basicp && (basicp->isEvent())) {
+        return "VlAssignableEvent{};\n";
     } else if (basicp) {
         const bool zeroit
             = (varp->attrFileDescr()  // Zero so we don't do file IO if never $fopen
diff --git a/test_regress/t/t_array_event.py b/test_regress/t/t_array_event.py
new file mode 100755
index 000000000..46d1fe4c0
--- /dev/null
+++ b/test_regress/t/t_array_event.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_array_event.v b/test_regress/t/t_array_event.v
new file mode 100644
index 000000000..c3bb7aa3e
--- /dev/null
+++ b/test_regress/t/t_array_event.v
@@ -0,0 +1,55 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+class Foo;
+  event write_events[int];
+
+  function void add_event(int index, event in);
+    write_events[index] = in;
+  endfunction
+
+  task trigger_event(int index);
+    ->write_events[index];
+  endtask
+
+  function void delete_event(int index);
+    write_events.delete(index);
+  endfunction
+endclass
+
+class Bar;
+  Foo foo;
+  event baz;
+
+  function new(Foo foo);
+    this.foo = foo;
+  endfunction
+
+  task go();
+    foo.add_event(3, baz);
+    @baz;
+    $display("got here");
+    foo.delete_event(3);
+  endtask
+endclass
+
+module top;
+  Bar bar;
+  Foo foo;
+
+  initial begin
+    foo = new();
+    bar = new(foo);
+    bar.go();
+  end
+
+  initial begin
+    #10;
+    foo.trigger_event(3);
+    $finish;
+  end
+
+endmodule