From 98b0d193634b494e1e0cf65ac29cae1756c1a552 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 5 Oct 2018 18:38:52 -0400 Subject: [PATCH] Tests: Add enum to trace test. --- test_regress/driver.pl | 6 +- test_regress/t/t_trace_complex.out | 68 ++++++++------ test_regress/t/t_trace_complex.v | 4 + test_regress/t/t_trace_complex_fst.out | 36 ++++--- test_regress/t/t_trace_complex_lxt2.out | 74 ++++++++------- test_regress/t/t_trace_complex_params.out | 68 ++++++++------ test_regress/t/t_trace_complex_params_fst.out | 36 ++++--- .../t/t_trace_complex_params_lxt2.out | 74 ++++++++------- test_regress/t/t_trace_complex_structs.out | 58 +++++++----- .../t/t_trace_complex_structs_fst.out | 28 ++++-- .../t/t_trace_complex_structs_lxt2.out | 94 ++++++++++--------- 11 files changed, 311 insertions(+), 235 deletions(-) diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 0ff4fdd25..09472bd0c 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -1577,7 +1577,7 @@ sub vcd_identical { my $cmd = qq{vcddiff --help}; print "\t$cmd\n" if $::Debug; my $out = `$cmd`; - if ($out !~ /Usage:/) { $self->skip("No vcddiff installed\n"); return 0; } + if (!$out || $out !~ /Usage:/) { $self->skip("No vcddiff installed\n"); return 0; } $cmd = qq{vcddiff "$fn1" "$fn2"}; print "\t$cmd\n" if $::Debug; @@ -1618,7 +1618,7 @@ sub fst2vcd { my $cmd = qq{fst2vcd --help}; print "\t$cmd\n" if $::Debug; my $out = `$cmd`; - if ($out !~ /Usage:/) { $self->skip("No fst2vcd installed\n"); return 0; } + if (!$out || $out !~ /Usage:/) { $self->skip("No fst2vcd installed\n"); return 0; } $cmd = qq{fst2vcd "$fn1" -o "$fn2"}; print "\t$cmd\n" if $::Debug; @@ -1634,7 +1634,7 @@ sub lxt2vcd { my $cmd = qq{lxt2vcd --help}; print "\t$cmd\n" if $::Debug; my $out = `$cmd`; - if ($out !~ /Usage:/) { $self->skip("No lxt2vcd installed\n"); return 0; } + if (!$out || $out !~ /Usage:/) { $self->skip("No lxt2vcd installed\n"); return 0; } $cmd = qq{lxt2vcd "$fn1" -o "$fn2"}; print "\t$cmd\n" if $::Debug; diff --git a/test_regress/t/t_trace_complex.out b/test_regress/t/t_trace_complex.out index 8182e06a9..1d3ca7362 100644 --- a/test_regress/t/t_trace_complex.out +++ b/test_regress/t/t_trace_complex.out @@ -1,46 +1,47 @@ $version Generated by VerilatedVcd $end -$date Tue Apr 15 19:42:28 2014 +$date Fri Oct 5 18:30:09 2018 $end -$timescale 1ns $end +$timescale 1ns $end $scope module top $end - $var wire 1 9 clk $end + $var wire 1 : clk $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end $scope module t $end - $var wire 1 9 clk $end + $var wire 1 : clk $end $var wire 32 $ cyc [31:0] $end $var real 64 3 v_arr_real(0) $end $var real 64 5 v_arr_real(1) $end $var wire 2 * v_arrp [2:1] $end $var wire 4 + v_arrp_arrp [3:0] $end $var wire 4 , v_arrp_strp [3:0] $end - $var wire 1 : v_arru(1) $end - $var wire 1 ; v_arru(2) $end + $var wire 1 ; v_arru(1) $end + $var wire 1 < v_arru(2) $end $var wire 2 - v_arru_arrp(3) [2:1] $end $var wire 2 . v_arru_arrp(4) [2:1] $end - $var wire 1 < v_arru_arru(3)(1) $end - $var wire 1 = v_arru_arru(3)(2) $end - $var wire 1 > v_arru_arru(4)(1) $end - $var wire 1 ? v_arru_arru(4)(2) $end + $var wire 1 = v_arru_arru(3)(1) $end + $var wire 1 > v_arru_arru(3)(2) $end + $var wire 1 ? v_arru_arru(4)(1) $end + $var wire 1 @ v_arru_arru(4)(2) $end $var wire 2 / v_arru_strp(3) [1:0] $end $var wire 2 0 v_arru_strp(4) [1:0] $end + $var wire 32 7 v_enumed [31:0] $end $var real 64 1 v_real $end $var wire 64 % v_str32x2 [63:0] $end $var wire 2 ' v_strp [1:0] $end $var wire 4 ( v_strp_strp [3:0] $end $var wire 2 ) v_unip_strp [1:0] $end $scope module p2 $end - $var wire 32 @ PARAM [31:0] $end - $upscope $end - $scope module p3 $end $var wire 32 A PARAM [31:0] $end $upscope $end + $scope module p3 $end + $var wire 32 B PARAM [31:0] $end + $upscope $end $scope module unnamedblk1 $end - $var wire 32 7 b [31:0] $end + $var wire 32 8 b [31:0] $end $scope module unnamedblk2 $end - $var wire 32 8 a [31:0] $end + $var wire 32 9 a [31:0] $end $upscope $end $upscope $end $upscope $end @@ -67,15 +68,16 @@ r0 3 r0 5 b00000000000000000000000000000000 7 b00000000000000000000000000000000 8 -09 +b00000000000000000000000000000000 9 0: 0; 0< 0= 0> 0? -b00000000000000000000000000000010 @ -b00000000000000000000000000000011 A +0@ +b00000000000000000000000000000010 A +b00000000000000000000000000000011 B #10 b00000000000000000000000000000001 $ b0000000000000000000000000000000100000000000000000000000011111110 % @@ -92,11 +94,12 @@ b11 0 r0.1 1 r0.2 3 r0.3 5 -b00000000000000000000000000000101 7 +b00000000000000000000000000000001 7 b00000000000000000000000000000101 8 -19 +b00000000000000000000000000000101 9 +1: #15 -09 +0: #20 b00000000000000000000000000000010 $ b0000000000000000000000000000001000000000000000000000000011111101 % @@ -113,9 +116,10 @@ b00 0 r0.2 1 r0.4 3 r0.6 5 -19 +b00000000000000000000000000000010 7 +1: #25 -09 +0: #30 b00000000000000000000000000000011 $ b0000000000000000000000000000001100000000000000000000000011111100 % @@ -132,9 +136,10 @@ b11 0 r0.3 1 r0.6000000000000001 3 r0.8999999999999999 5 -19 +b00000000000000000000000000000011 7 +1: #35 -09 +0: #40 b00000000000000000000000000000100 $ b0000000000000000000000000000010000000000000000000000000011111011 % @@ -151,9 +156,10 @@ b00 0 r0.4 1 r0.8 3 r1.2 5 -19 +b00000000000000000000000000000100 7 +1: #45 -09 +0: #50 b00000000000000000000000000000101 $ b0000000000000000000000000000010100000000000000000000000011111010 % @@ -170,9 +176,10 @@ b11 0 r0.5 1 r1 3 r1.5 5 -19 +b00000000000000000000000000000101 7 +1: #55 -09 +0: #60 b00000000000000000000000000000110 $ b0000000000000000000000000000011000000000000000000000000011111001 % @@ -189,4 +196,5 @@ b00 0 r0.6 1 r1.2 3 r1.8 5 -19 +b00000000000000000000000000000110 7 +1: diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v index 732e813a4..2c37c222f 100644 --- a/test_regress/t/t_trace_complex.v +++ b/test_regress/t/t_trace_complex.v @@ -56,6 +56,9 @@ module t (clk); initial v_str32x2[0] = 32'hff; initial v_str32x2[1] = 0; + typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t; + enumed_t v_enumed; + p #(.PARAM(2)) p2 (); p #(.PARAM(3)) p3 (); @@ -71,6 +74,7 @@ module t (clk); v_string <= cyc[0] ? "foo" : "bar"; v_arr_real[0] <= v_arr_real[0] + 0.2; v_arr_real[1] <= v_arr_real[1] + 0.3; + v_enumed <= v_enumed + 1; for (integer b=3; b<=4; b++) begin v_arru[b] <= ~v_arru[b]; v_arru_strp[b] <= ~v_arru_strp[b]; diff --git a/test_regress/t/t_trace_complex_fst.out b/test_regress/t/t_trace_complex_fst.out index 6eeb15cfb..c735d729c 100644 --- a/test_regress/t/t_trace_complex_fst.out +++ b/test_regress/t/t_trace_complex_fst.out @@ -1,5 +1,5 @@ $date - Thu Oct 4 19:33:39 2018 + Fri Oct 5 18:31:31 2018 $end $version @@ -33,21 +33,22 @@ $var real 64 3 v_real $end $var real 64 4 v_arr_real(0) $end $var real 64 5 v_arr_real(1) $end $var logic 64 6 v_str32x2 $end +$var logic 32 7 v_enumed $end $scope module unnamedblk1 $end -$var integer 32 7 b $end +$var integer 32 8 b $end $scope module unnamedblk2 $end -$var integer 32 8 a $end +$var integer 32 9 a $end $upscope $end $upscope $end $scope module p2 $end -$var parameter 32 9 PARAM $end +$var parameter 32 : PARAM $end $upscope $end $scope module p3 $end -$var parameter 32 : PARAM $end +$var parameter 32 ; PARAM $end $upscope $end $upscope $end $scope module $unit $end -$var bit 1 ; global_bit $end +$var bit 1 < global_bit $end $upscope $end $upscope $end $enddefinitions $end @@ -76,12 +77,14 @@ r0 5 b0000000000000000000000000000000000000000000000000000000011111111 6 b00000000000000000000000000000000 7 b00000000000000000000000000000000 8 -b00000000000000000000000000000010 9 -b00000000000000000000000000000011 : -1; +b00000000000000000000000000000000 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; +1< #10 +b00000000000000000000000000000101 9 b00000000000000000000000000000101 8 -b00000000000000000000000000000101 7 +b00000000000000000000000000000001 7 b0000000000000000000000000000000100000000000000000000000011111110 6 r0.3 5 r0.2 4 @@ -117,14 +120,16 @@ r0.2 3 r0.4 4 r0.6 5 b0000000000000000000000000000001000000000000000000000000011111101 6 -b00000000000000000000000000000101 7 +b00000000000000000000000000000010 7 b00000000000000000000000000000101 8 +b00000000000000000000000000000101 9 #25 0! #30 1! +b00000000000000000000000000000101 9 b00000000000000000000000000000101 8 -b00000000000000000000000000000101 7 +b00000000000000000000000000000011 7 b0000000000000000000000000000001100000000000000000000000011111100 6 r0.8999999999999999 5 r0.6000000000000001 4 @@ -159,12 +164,14 @@ r0.4 3 r0.8 4 r1.2 5 b0000000000000000000000000000010000000000000000000000000011111011 6 -b00000000000000000000000000000101 7 +b00000000000000000000000000000100 7 b00000000000000000000000000000101 8 +b00000000000000000000000000000101 9 #45 0! #50 1! +b00000000000000000000000000000101 9 b00000000000000000000000000000101 8 b00000000000000000000000000000101 7 b0000000000000000000000000000010100000000000000000000000011111010 6 @@ -201,5 +208,6 @@ r0.6 3 r1.2 4 r1.8 5 b0000000000000000000000000000011000000000000000000000000011111001 6 -b00000000000000000000000000000101 7 +b00000000000000000000000000000110 7 b00000000000000000000000000000101 8 +b00000000000000000000000000000101 9 diff --git a/test_regress/t/t_trace_complex_lxt2.out b/test_regress/t/t_trace_complex_lxt2.out index 8b6ba1fc8..78cc39d16 100644 --- a/test_regress/t/t_trace_complex_lxt2.out +++ b/test_regress/t/t_trace_complex_lxt2.out @@ -1,5 +1,5 @@ $date - Tue Aug 28 15:03:55 2018 + Fri Oct 5 18:31:36 2018 $end $version lxt2vcd @@ -39,11 +39,12 @@ $var wire 1 3 v_arru_arru(4)(1) $end $var wire 1 4 v_arru_arru(4)(2) $end $var wire 2 5 v_arru_strp(3) [1:0] $end $var wire 2 6 v_arru_strp(4) [1:0] $end -$var real 1 7 v_real $end -$var wire 64 8 v_str32x2 [63:0] $end -$var wire 2 9 v_strp [1:0] $end -$var wire 4 : v_strp_strp [3:0] $end -$var wire 2 ; v_unip_strp [1:0] $end +$var wire 32 7 v_enumed [31:0] $end +$var real 1 8 v_real $end +$var wire 64 9 v_str32x2 [63:0] $end +$var wire 2 : v_strp [1:0] $end +$var wire 4 ; v_strp_strp [3:0] $end +$var wire 2 < v_unip_strp [1:0] $end $var wire 1 " clk $end $upscope $end $upscope $end @@ -72,17 +73,19 @@ b0 0 04 b0 5 b0 6 -r0 7 -b11111111 8 -b0 9 +b0 7 +r0 8 +b11111111 9 b0 : b0 ; +b0 < #10 -b11 ; -b1111 : -b11 9 -b100000000000000000000000011111110 8 -r0.1 7 +b11 < +b1111 ; +b11 : +b100000000000000000000000011111110 9 +r0.1 8 +b1 7 b11 6 b11 5 b11 0 @@ -110,20 +113,22 @@ b0 / b0 0 b0 5 b0 6 -r0.2 7 -b1000000000000000000000000011111101 8 -b0 9 +b10 7 +r0.2 8 +b1000000000000000000000000011111101 9 b0 : b0 ; +b0 < #25 0" #30 1" -b11 ; -b1111 : -b11 9 -b1100000000000000000000000011111100 8 -r0.3 7 +b11 < +b1111 ; +b11 : +b1100000000000000000000000011111100 9 +r0.3 8 +b11 7 b11 6 b11 5 b11 0 @@ -148,20 +153,22 @@ b0 / b0 0 b0 5 b0 6 -r0.4 7 -b10000000000000000000000000011111011 8 -b0 9 +b100 7 +r0.4 8 +b10000000000000000000000000011111011 9 b0 : b0 ; +b0 < #45 0" #50 1" -b11 ; -b1111 : -b11 9 -b10100000000000000000000000011111010 8 -r0.5 7 +b11 < +b1111 ; +b11 : +b10100000000000000000000000011111010 9 +r0.5 8 +b101 7 b11 6 b11 5 b11 0 @@ -186,8 +193,9 @@ b0 / b0 0 b0 5 b0 6 -r0.6 7 -b11000000000000000000000000011111001 8 -b0 9 +b110 7 +r0.6 8 +b11000000000000000000000000011111001 9 b0 : b0 ; +b0 < diff --git a/test_regress/t/t_trace_complex_params.out b/test_regress/t/t_trace_complex_params.out index 156554949..fb847ff3e 100644 --- a/test_regress/t/t_trace_complex_params.out +++ b/test_regress/t/t_trace_complex_params.out @@ -1,46 +1,47 @@ $version Generated by VerilatedVcd $end -$date Tue Apr 15 19:42:37 2014 +$date Fri Oct 5 18:38:00 2018 $end -$timescale 1ns $end +$timescale 1ns $end $scope module top $end - $var wire 1 9 clk $end + $var wire 1 : clk $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end $scope module t $end - $var wire 1 9 clk $end + $var wire 1 : clk $end $var wire 32 $ cyc [31:0] $end $var real 64 3 v_arr_real(0) $end $var real 64 5 v_arr_real(1) $end $var wire 2 * v_arrp [2:1] $end $var wire 4 + v_arrp_arrp [3:0] $end $var wire 4 , v_arrp_strp [3:0] $end - $var wire 1 : v_arru(1) $end - $var wire 1 ; v_arru(2) $end + $var wire 1 ; v_arru(1) $end + $var wire 1 < v_arru(2) $end $var wire 2 - v_arru_arrp(3) [2:1] $end $var wire 2 . v_arru_arrp(4) [2:1] $end - $var wire 1 < v_arru_arru(3)(1) $end - $var wire 1 = v_arru_arru(3)(2) $end - $var wire 1 > v_arru_arru(4)(1) $end - $var wire 1 ? v_arru_arru(4)(2) $end + $var wire 1 = v_arru_arru(3)(1) $end + $var wire 1 > v_arru_arru(3)(2) $end + $var wire 1 ? v_arru_arru(4)(1) $end + $var wire 1 @ v_arru_arru(4)(2) $end $var wire 2 / v_arru_strp(3) [1:0] $end $var wire 2 0 v_arru_strp(4) [1:0] $end + $var wire 32 7 v_enumed [31:0] $end $var real 64 1 v_real $end $var wire 64 % v_str32x2 [63:0] $end $var wire 2 ' v_strp [1:0] $end $var wire 4 ( v_strp_strp [3:0] $end $var wire 2 ) v_unip_strp [1:0] $end $scope module p2 $end - $var wire 32 @ PARAM [31:0] $end - $upscope $end - $scope module p3 $end $var wire 32 A PARAM [31:0] $end $upscope $end + $scope module p3 $end + $var wire 32 B PARAM [31:0] $end + $upscope $end $scope module unnamedblk1 $end - $var wire 32 7 b [31:0] $end + $var wire 32 8 b [31:0] $end $scope module unnamedblk2 $end - $var wire 32 8 a [31:0] $end + $var wire 32 9 a [31:0] $end $upscope $end $upscope $end $upscope $end @@ -67,15 +68,16 @@ r0 3 r0 5 b00000000000000000000000000000000 7 b00000000000000000000000000000000 8 -09 +b00000000000000000000000000000000 9 0: 0; 0< 0= 0> 0? -b00000000000000000000000000000010 @ -b00000000000000000000000000000011 A +0@ +b00000000000000000000000000000010 A +b00000000000000000000000000000011 B #10 b00000000000000000000000000000001 $ b0000000000000000000000000000000100000000000000000000000011111110 % @@ -92,11 +94,12 @@ b11 0 r0.1 1 r0.2 3 r0.3 5 -b00000000000000000000000000000101 7 +b00000000000000000000000000000001 7 b00000000000000000000000000000101 8 -19 +b00000000000000000000000000000101 9 +1: #15 -09 +0: #20 b00000000000000000000000000000010 $ b0000000000000000000000000000001000000000000000000000000011111101 % @@ -113,9 +116,10 @@ b00 0 r0.2 1 r0.4 3 r0.6 5 -19 +b00000000000000000000000000000010 7 +1: #25 -09 +0: #30 b00000000000000000000000000000011 $ b0000000000000000000000000000001100000000000000000000000011111100 % @@ -132,9 +136,10 @@ b11 0 r0.3 1 r0.6000000000000001 3 r0.8999999999999999 5 -19 +b00000000000000000000000000000011 7 +1: #35 -09 +0: #40 b00000000000000000000000000000100 $ b0000000000000000000000000000010000000000000000000000000011111011 % @@ -151,9 +156,10 @@ b00 0 r0.4 1 r0.8 3 r1.2 5 -19 +b00000000000000000000000000000100 7 +1: #45 -09 +0: #50 b00000000000000000000000000000101 $ b0000000000000000000000000000010100000000000000000000000011111010 % @@ -170,9 +176,10 @@ b11 0 r0.5 1 r1 3 r1.5 5 -19 +b00000000000000000000000000000101 7 +1: #55 -09 +0: #60 b00000000000000000000000000000110 $ b0000000000000000000000000000011000000000000000000000000011111001 % @@ -189,4 +196,5 @@ b00 0 r0.6 1 r1.2 3 r1.8 5 -19 +b00000000000000000000000000000110 7 +1: diff --git a/test_regress/t/t_trace_complex_params_fst.out b/test_regress/t/t_trace_complex_params_fst.out index 5d13160b5..136238d14 100644 --- a/test_regress/t/t_trace_complex_params_fst.out +++ b/test_regress/t/t_trace_complex_params_fst.out @@ -1,5 +1,5 @@ $date - Thu Oct 4 19:33:40 2018 + Fri Oct 5 18:38:01 2018 $end $version @@ -33,21 +33,22 @@ $var real 64 3 v_real $end $var real 64 4 v_arr_real(0) $end $var real 64 5 v_arr_real(1) $end $var logic 64 6 v_str32x2 $end +$var logic 32 7 v_enumed $end $scope module unnamedblk1 $end -$var integer 32 7 b $end +$var integer 32 8 b $end $scope module unnamedblk2 $end -$var integer 32 8 a $end +$var integer 32 9 a $end $upscope $end $upscope $end $scope module p2 $end -$var parameter 32 9 PARAM $end +$var parameter 32 : PARAM $end $upscope $end $scope module p3 $end -$var parameter 32 : PARAM $end +$var parameter 32 ; PARAM $end $upscope $end $upscope $end $scope module $unit $end -$var bit 1 ; global_bit $end +$var bit 1 < global_bit $end $upscope $end $upscope $end $enddefinitions $end @@ -76,12 +77,14 @@ r0 5 b0000000000000000000000000000000000000000000000000000000011111111 6 b00000000000000000000000000000000 7 b00000000000000000000000000000000 8 -b00000000000000000000000000000010 9 -b00000000000000000000000000000011 : -1; +b00000000000000000000000000000000 9 +b00000000000000000000000000000010 : +b00000000000000000000000000000011 ; +1< #10 +b00000000000000000000000000000101 9 b00000000000000000000000000000101 8 -b00000000000000000000000000000101 7 +b00000000000000000000000000000001 7 b0000000000000000000000000000000100000000000000000000000011111110 6 r0.3 5 r0.2 4 @@ -117,14 +120,16 @@ r0.2 3 r0.4 4 r0.6 5 b0000000000000000000000000000001000000000000000000000000011111101 6 -b00000000000000000000000000000101 7 +b00000000000000000000000000000010 7 b00000000000000000000000000000101 8 +b00000000000000000000000000000101 9 #25 0! #30 1! +b00000000000000000000000000000101 9 b00000000000000000000000000000101 8 -b00000000000000000000000000000101 7 +b00000000000000000000000000000011 7 b0000000000000000000000000000001100000000000000000000000011111100 6 r0.8999999999999999 5 r0.6000000000000001 4 @@ -159,12 +164,14 @@ r0.4 3 r0.8 4 r1.2 5 b0000000000000000000000000000010000000000000000000000000011111011 6 -b00000000000000000000000000000101 7 +b00000000000000000000000000000100 7 b00000000000000000000000000000101 8 +b00000000000000000000000000000101 9 #45 0! #50 1! +b00000000000000000000000000000101 9 b00000000000000000000000000000101 8 b00000000000000000000000000000101 7 b0000000000000000000000000000010100000000000000000000000011111010 6 @@ -201,5 +208,6 @@ r0.6 3 r1.2 4 r1.8 5 b0000000000000000000000000000011000000000000000000000000011111001 6 -b00000000000000000000000000000101 7 +b00000000000000000000000000000110 7 b00000000000000000000000000000101 8 +b00000000000000000000000000000101 9 diff --git a/test_regress/t/t_trace_complex_params_lxt2.out b/test_regress/t/t_trace_complex_params_lxt2.out index 552bc58fe..e4a324efb 100644 --- a/test_regress/t/t_trace_complex_params_lxt2.out +++ b/test_regress/t/t_trace_complex_params_lxt2.out @@ -1,5 +1,5 @@ $date - Tue Aug 28 15:09:58 2018 + Fri Oct 5 18:38:02 2018 $end $version lxt2vcd @@ -39,11 +39,12 @@ $var wire 1 3 v_arru_arru(4)(1) $end $var wire 1 4 v_arru_arru(4)(2) $end $var wire 2 5 v_arru_strp(3) [1:0] $end $var wire 2 6 v_arru_strp(4) [1:0] $end -$var real 1 7 v_real $end -$var wire 64 8 v_str32x2 [63:0] $end -$var wire 2 9 v_strp [1:0] $end -$var wire 4 : v_strp_strp [3:0] $end -$var wire 2 ; v_unip_strp [1:0] $end +$var wire 32 7 v_enumed [31:0] $end +$var real 1 8 v_real $end +$var wire 64 9 v_str32x2 [63:0] $end +$var wire 2 : v_strp [1:0] $end +$var wire 4 ; v_strp_strp [3:0] $end +$var wire 2 < v_unip_strp [1:0] $end $var wire 1 " clk $end $upscope $end $upscope $end @@ -72,17 +73,19 @@ b0 0 04 b0 5 b0 6 -r0 7 -b11111111 8 -b0 9 +b0 7 +r0 8 +b11111111 9 b0 : b0 ; +b0 < #10 -b11 ; -b1111 : -b11 9 -b100000000000000000000000011111110 8 -r0.1 7 +b11 < +b1111 ; +b11 : +b100000000000000000000000011111110 9 +r0.1 8 +b1 7 b11 6 b11 5 b11 0 @@ -110,20 +113,22 @@ b0 / b0 0 b0 5 b0 6 -r0.2 7 -b1000000000000000000000000011111101 8 -b0 9 +b10 7 +r0.2 8 +b1000000000000000000000000011111101 9 b0 : b0 ; +b0 < #25 0" #30 1" -b11 ; -b1111 : -b11 9 -b1100000000000000000000000011111100 8 -r0.3 7 +b11 < +b1111 ; +b11 : +b1100000000000000000000000011111100 9 +r0.3 8 +b11 7 b11 6 b11 5 b11 0 @@ -148,20 +153,22 @@ b0 / b0 0 b0 5 b0 6 -r0.4 7 -b10000000000000000000000000011111011 8 -b0 9 +b100 7 +r0.4 8 +b10000000000000000000000000011111011 9 b0 : b0 ; +b0 < #45 0" #50 1" -b11 ; -b1111 : -b11 9 -b10100000000000000000000000011111010 8 -r0.5 7 +b11 < +b1111 ; +b11 : +b10100000000000000000000000011111010 9 +r0.5 8 +b101 7 b11 6 b11 5 b11 0 @@ -186,8 +193,9 @@ b0 / b0 0 b0 5 b0 6 -r0.6 7 -b11000000000000000000000000011111001 8 -b0 9 +b110 7 +r0.6 8 +b11000000000000000000000000011111001 9 b0 : b0 ; +b0 < diff --git a/test_regress/t/t_trace_complex_structs.out b/test_regress/t/t_trace_complex_structs.out index 0940b4eb6..16cfc73cd 100644 --- a/test_regress/t/t_trace_complex_structs.out +++ b/test_regress/t/t_trace_complex_structs.out @@ -1,34 +1,35 @@ $version Generated by VerilatedVcd $end -$date Tue Apr 15 12:58:17 2014 +$date Fri Oct 5 18:38:02 2018 $end -$timescale 1ns $end +$timescale 1ns $end $scope module top $end - $var wire 1 D clk $end + $var wire 1 E clk $end $scope module $unit $end $var wire 1 # global_bit $end $upscope $end $scope module t $end - $var wire 1 D clk $end + $var wire 1 E clk $end $var wire 32 $ cyc [31:0] $end $var real 64 > v_arr_real(0) $end $var real 64 @ v_arr_real(1) $end $var wire 2 / v_arrp [2:1] $end $var wire 2 0 v_arrp_arrp(3) [1:0] $end $var wire 2 1 v_arrp_arrp(4) [1:0] $end - $var wire 1 E v_arru(1) $end - $var wire 1 F v_arru(2) $end + $var wire 1 F v_arru(1) $end + $var wire 1 G v_arru(2) $end $var wire 2 6 v_arru_arrp(3) [2:1] $end $var wire 2 7 v_arru_arrp(4) [2:1] $end - $var wire 1 G v_arru_arru(3)(1) $end - $var wire 1 H v_arru_arru(3)(2) $end - $var wire 1 I v_arru_arru(4)(1) $end - $var wire 1 J v_arru_arru(4)(2) $end + $var wire 1 H v_arru_arru(3)(1) $end + $var wire 1 I v_arru_arru(3)(2) $end + $var wire 1 J v_arru_arru(4)(1) $end + $var wire 1 K v_arru_arru(4)(2) $end + $var wire 32 B v_enumed [31:0] $end $var real 64 < v_real $end $scope module unnamedblk1 $end - $var wire 32 B b [31:0] $end + $var wire 32 C b [31:0] $end $scope module unnamedblk2 $end - $var wire 32 C a [31:0] $end + $var wire 32 D a [31:0] $end $upscope $end $upscope $end $scope module v_arrp_strp(3) $end @@ -113,13 +114,14 @@ r0 > r0 @ b00000000000000000000000000000000 B b00000000000000000000000000000000 C -0D +b00000000000000000000000000000000 D 0E 0F 0G 0H 0I 0J +0K #10 b00000000000000000000000000000001 $ b00000000000000000000000011111110 % @@ -148,11 +150,12 @@ b11 7 r0.1 < r0.2 > r0.3 @ -b00000000000000000000000000000101 B +b00000000000000000000000000000001 B b00000000000000000000000000000101 C -1D +b00000000000000000000000000000101 D +1E #15 -0D +0E #20 b00000000000000000000000000000010 $ b00000000000000000000000011111101 % @@ -181,9 +184,10 @@ b00 7 r0.2 < r0.4 > r0.6 @ -1D +b00000000000000000000000000000010 B +1E #25 -0D +0E #30 b00000000000000000000000000000011 $ b00000000000000000000000011111100 % @@ -212,9 +216,10 @@ b11 7 r0.3 < r0.6000000000000001 > r0.8999999999999999 @ -1D +b00000000000000000000000000000011 B +1E #35 -0D +0E #40 b00000000000000000000000000000100 $ b00000000000000000000000011111011 % @@ -243,9 +248,10 @@ b00 7 r0.4 < r0.8 > r1.2 @ -1D +b00000000000000000000000000000100 B +1E #45 -0D +0E #50 b00000000000000000000000000000101 $ b00000000000000000000000011111010 % @@ -274,9 +280,10 @@ b11 7 r0.5 < r1 > r1.5 @ -1D +b00000000000000000000000000000101 B +1E #55 -0D +0E #60 b00000000000000000000000000000110 $ b00000000000000000000000011111001 % @@ -305,4 +312,5 @@ b00 7 r0.6 < r1.2 > r1.8 @ -1D +b00000000000000000000000000000110 B +1E diff --git a/test_regress/t/t_trace_complex_structs_fst.out b/test_regress/t/t_trace_complex_structs_fst.out index 48e4daafd..b981f0a9d 100644 --- a/test_regress/t/t_trace_complex_structs_fst.out +++ b/test_regress/t/t_trace_complex_structs_fst.out @@ -1,5 +1,5 @@ $date - Thu Oct 4 19:33:40 2018 + Fri Oct 5 18:38:03 2018 $end $version @@ -73,15 +73,16 @@ $upscope $end $scope module v_str32x2(1) $end $var logic 32 B data $end $upscope $end +$var logic 32 C v_enumed $end $scope module unnamedblk1 $end -$var integer 32 C b $end +$var integer 32 D b $end $scope module unnamedblk2 $end -$var integer 32 D a $end +$var integer 32 E a $end $upscope $end $upscope $end $upscope $end $scope module $unit $end -$var bit 1 E global_bit $end +$var bit 1 F global_bit $end $upscope $end $upscope $end $enddefinitions $end @@ -122,10 +123,12 @@ b00000000000000000000000011111111 A b00000000000000000000000000000000 B b00000000000000000000000000000000 C b00000000000000000000000000000000 D -1E +b00000000000000000000000000000000 E +1F #10 +b00000000000000000000000000000101 E b00000000000000000000000000000101 D -b00000000000000000000000000000101 C +b00000000000000000000000000000001 C b00000000000000000000000000000001 B b00000000000000000000000011111110 A r0.3 @ @@ -185,14 +188,16 @@ r0.4 ? r0.6 @ b00000000000000000000000011111101 A b00000000000000000000000000000010 B -b00000000000000000000000000000101 C +b00000000000000000000000000000010 C b00000000000000000000000000000101 D +b00000000000000000000000000000101 E #25 0! #30 1! +b00000000000000000000000000000101 E b00000000000000000000000000000101 D -b00000000000000000000000000000101 C +b00000000000000000000000000000011 C b00000000000000000000000000000011 B b00000000000000000000000011111100 A r0.8999999999999999 @ @@ -251,12 +256,14 @@ r0.8 ? r1.2 @ b00000000000000000000000011111011 A b00000000000000000000000000000100 B -b00000000000000000000000000000101 C +b00000000000000000000000000000100 C b00000000000000000000000000000101 D +b00000000000000000000000000000101 E #45 0! #50 1! +b00000000000000000000000000000101 E b00000000000000000000000000000101 D b00000000000000000000000000000101 C b00000000000000000000000000000101 B @@ -317,5 +324,6 @@ r1.2 ? r1.8 @ b00000000000000000000000011111001 A b00000000000000000000000000000110 B -b00000000000000000000000000000101 C +b00000000000000000000000000000110 C b00000000000000000000000000000101 D +b00000000000000000000000000000101 E diff --git a/test_regress/t/t_trace_complex_structs_lxt2.out b/test_regress/t/t_trace_complex_structs_lxt2.out index 52966de23..9a9964e68 100644 --- a/test_regress/t/t_trace_complex_structs_lxt2.out +++ b/test_regress/t/t_trace_complex_structs_lxt2.out @@ -1,5 +1,5 @@ $date - Tue Aug 28 15:07:10 2018 + Fri Oct 5 18:38:03 2018 $end $version lxt2vcd @@ -47,38 +47,39 @@ $scope module v_arru_strp(4) $end $var wire 1 9 b0 $end $var wire 1 : b1 $end $upscope $end -$var real 1 ; v_real $end +$var wire 32 ; v_enumed [31:0] $end +$var real 1 < v_real $end $scope module v_str32x2(0) $end -$var wire 32 < data [31:0] $end -$upscope $end -$scope module v_str32x2(1) $end $var wire 32 = data [31:0] $end $upscope $end +$scope module v_str32x2(1) $end +$var wire 32 > data [31:0] $end +$upscope $end $scope module v_strp $end -$var wire 1 > b0 $end -$var wire 1 ? b1 $end +$var wire 1 ? b0 $end +$var wire 1 @ b1 $end $upscope $end $scope module v_strp_strp $end $scope module x0 $end -$var wire 1 @ b0 $end -$var wire 1 A b1 $end +$var wire 1 A b0 $end +$var wire 1 B b1 $end $upscope $end $scope module x1 $end -$var wire 1 B b0 $end -$var wire 1 C b1 $end +$var wire 1 C b0 $end +$var wire 1 D b1 $end $upscope $end $upscope $end $scope module v_unip_strp $end $scope module x1 $end -$var wire 1 D b0 $end -$var wire 1 E b1 $end +$var wire 1 E b0 $end +$var wire 1 F b1 $end $upscope $end $upscope $end $var wire 1 " clk $end $scope module v_unip_strp $end $scope module x0 $end -$var wire 1 D b0 $end -$var wire 1 E b1 $end +$var wire 1 E b0 $end +$var wire 1 F b1 $end $upscope $end $upscope $end $upscope $end @@ -112,10 +113,10 @@ b0 2 08 09 0: -r0 ; -b11111111 < -b0 = -0> +b0 ; +r0 < +b11111111 = +b0 > 0? 0@ 0A @@ -123,7 +124,9 @@ b0 = 0C 0D 0E +0F #10 +1F 1E 1D 1C @@ -131,10 +134,10 @@ b0 = 1A 1@ 1? -1> -b1 = -b11111110 < -r0.1 ; +b1 > +b11111110 = +r0.1 < +b1 ; 1: 19 18 @@ -174,10 +177,10 @@ b0 2 08 09 0: -r0.2 ; -b11111101 < -b10 = -0> +b10 ; +r0.2 < +b11111101 = +b10 > 0? 0@ 0A @@ -185,10 +188,12 @@ b10 = 0C 0D 0E +0F #25 0" #30 1" +1F 1E 1D 1C @@ -196,10 +201,10 @@ b10 = 1A 1@ 1? -1> -b11 = -b11111100 < -r0.3 ; +b11 > +b11111100 = +r0.3 < +b11 ; 1: 19 18 @@ -236,10 +241,10 @@ b0 2 08 09 0: -r0.4 ; -b11111011 < -b100 = -0> +b100 ; +r0.4 < +b11111011 = +b100 > 0? 0@ 0A @@ -247,10 +252,12 @@ b100 = 0C 0D 0E +0F #45 0" #50 1" +1F 1E 1D 1C @@ -258,10 +265,10 @@ b100 = 1A 1@ 1? -1> -b101 = -b11111010 < -r0.5 ; +b101 > +b11111010 = +r0.5 < +b101 ; 1: 19 18 @@ -298,10 +305,10 @@ b0 2 08 09 0: -r0.6 ; -b11111001 < -b110 = -0> +b110 ; +r0.6 < +b11111001 = +b110 > 0? 0@ 0A @@ -309,3 +316,4 @@ b110 = 0C 0D 0E +0F