diff --git a/test_regress/t/t_lint_latch_5.pl b/test_regress/t/t_lint_latch_5.pl
new file mode 100755
index 000000000..629a44bbb
--- /dev/null
+++ b/test_regress/t/t_lint_latch_5.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_lint_latch_5.v b/test_regress/t/t_lint_latch_5.v
new file mode 100644
index 000000000..7cf29d05c
--- /dev/null
+++ b/test_regress/t/t_lint_latch_5.v
@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module for Issue#2863
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2021 by Julien Margetts (Originally provided by Thomas Sailer)
+
+module test
+  (input  logic [1:0] a,
+   input  logic       e,
+   output logic [1:0] z);
+
+   always_latch
+     if (e)
+       z[0] <= a[0];
+
+   always_latch
+     if (e)
+       z[1] <= a[1];
+
+endmodule