From 97e9996f0b7e6d71910bc7eda20c6d63022cde8a Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Thu, 8 Aug 2024 22:57:12 +0200
Subject: [PATCH] Fix optimized-out sentrees with `--timing` (#5080) (#5349)

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 src/V3Const.cpp                           |  2 ++
 test_regress/t/t_timing_initial_always.pl | 22 ++++++++++++++++++++
 test_regress/t/t_timing_initial_always.v  | 25 +++++++++++++++++++++++
 3 files changed, 49 insertions(+)
 create mode 100755 test_regress/t/t_timing_initial_always.pl
 create mode 100644 test_regress/t/t_timing_initial_always.v

diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index b5dce4457..54c1d3704 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -2830,6 +2830,8 @@ class ConstVisitor final : public VNVisitor {
     void visit(AstSenItem* nodep) override {
         iterateChildren(nodep);
         if (m_doNConst
+            && !v3Global.opt.timing().isSetTrue()  // If --timing, V3Sched would turn this into an
+                                                   // infinite loop. See #5080
             && (VN_IS(nodep->sensp(), Const) || VN_IS(nodep->sensp(), EnumItemRef)
                 || (nodep->varrefp() && nodep->varrefp()->varp()->isParam()))) {
             // Constants in sensitivity lists may be removed (we'll simplify later)
diff --git a/test_regress/t/t_timing_initial_always.pl b/test_regress/t/t_timing_initial_always.pl
new file mode 100755
index 000000000..929ae897c
--- /dev/null
+++ b/test_regress/t/t_timing_initial_always.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--exe --main --timing"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_timing_initial_always.v b/test_regress/t/t_timing_initial_always.v
new file mode 100644
index 000000000..1acbc71b0
--- /dev/null
+++ b/test_regress/t/t_timing_initial_always.v
@@ -0,0 +1,25 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  wire sig;
+  foo foo(sig);
+
+  initial #1 begin
+    $write("*-* All Finished *-*\n");
+    $finish();
+  end
+endmodule
+
+module foo(inout sig);
+  reg cond = $c(0);
+
+  always @(sig) begin
+    if (cond) begin
+      #1; $c("");
+    end
+  end
+endmodule