From 97561bf0643e8d3f3c818706e174aeb7e123bba3 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 14 Jul 2019 21:42:03 -0400 Subject: [PATCH] When showing an error, show source code. --- Changes | 2 +- src/V3Ast.cpp | 4 + src/V3AstNodes.cpp | 2 +- src/V3Config.cpp | 6 +- src/V3FileLine.cpp | 131 +++++++++- src/V3FileLine.h | 76 ++++-- src/V3ParseImp.cpp | 2 + src/V3ParseImp.h | 5 +- src/V3ParseLex.cpp | 1 + src/V3PreLex.l | 228 ++++++++++-------- src/V3PreProc.cpp | 59 +++-- src/V3String.cpp | 9 + src/V3String.h | 3 + src/verilog.l | 219 +++++++++-------- test_regress/driver.pl | 3 +- test_regress/t/t_array_backw_index_bad.out | 10 + test_regress/t/t_array_list_bad.out | 4 + test_regress/t/t_array_pattern_bad.out | 2 + test_regress/t/t_assert_dup_bad.out | 4 + test_regress/t/t_bitsel_const_bad.out | 2 + test_regress/t/t_bitsel_wire_array_bad.out | 2 + test_regress/t/t_case_default_bad.out | 2 + test_regress/t/t_case_genx_bad.out | 2 + test_regress/t/t_case_x_bad.out | 4 + test_regress/t/t_case_zx_bad.out | 2 + test_regress/t/t_cdc_async_bad.out | 6 + test_regress/t/t_clk_scope_bad.out | 2 + test_regress/t/t_concat_large_bad.out | 2 + test_regress/t/t_const_bad.out | 6 + test_regress/t/t_const_dec_mixed_bad.out | 2 + test_regress/t/t_const_overflow_bad.out | 10 + test_regress/t/t_delay_stmtdly_bad.out | 8 + test_regress/t/t_display_bad.out | 4 + test_regress/t/t_display_esc_bad.out | 2 + test_regress/t/t_dpi_2exp_bad.out | 2 + test_regress/t/t_dpi_dup_bad.out | 4 + test_regress/t/t_dpi_exp_bad.out | 2 + test_regress/t/t_dpi_logic_bad.out | 2 + test_regress/t/t_dpi_name_bad.out | 2 + test_regress/t/t_dpi_openreg_bad.out | 4 + test_regress/t/t_enum_bad_hide.out | 4 + test_regress/t/t_enum_overlap_bad.out | 4 + test_regress/t/t_flag_errorlimit_bad.out | 8 + test_regress/t/t_flag_topmodule_bad.out | 6 + test_regress/t/t_flag_werror_bad1.out | 2 + test_regress/t/t_flag_werror_bad2.out | 2 + test_regress/t/t_flag_wfatal.out | 2 + test_regress/t/t_for_comma_bad.out | 18 ++ test_regress/t/t_func_bad.out | 14 ++ test_regress/t/t_func_bad2.out | 2 + test_regress/t/t_func_bad_width.out | 4 + test_regress/t/t_func_const2_bad.out | 2 + test_regress/t/t_func_const_bad.out | 12 + .../t/t_func_const_packed_array_bad.out | 2 + .../t/t_func_const_packed_struct_bad.out | 2 + .../t/t_func_const_packed_struct_bad2.out | 2 + test_regress/t/t_func_const_struct_bad.out | 2 + test_regress/t/t_func_task_bad.out | 2 + test_regress/t/t_func_tie_bad.out | 2 + test_regress/t/t_func_void_bad.out | 2 + test_regress/t/t_func_wide_out_bad.out | 2 + test_regress/t/t_gen_cond_bitrange_bad.out | 8 + test_regress/t/t_gen_missing_bad.out | 2 + test_regress/t/t_gen_var_bad.out | 2 + test_regress/t/t_hierarchy_identifier_bad.out | 10 + test_regress/t/t_initial_dlyass_bad.out | 4 + test_regress/t/t_inst_array_bad.out | 2 + test_regress/t/t_inst_misarray_bad.out | 2 + test_regress/t/t_inst_missing_bad.out | 6 + test_regress/t/t_inst_overwide_bad.out | 8 + test_regress/t/t_inst_recurse2_bad.out | 2 + test_regress/t/t_inst_recurse_bad.out | 2 + test_regress/t/t_interface_array_bad.out | 4 + .../t/t_interface_array_nocolon_bad.out | 8 + test_regress/t/t_interface_mismodport_bad.out | 2 + test_regress/t/t_interface_missing_bad.out | 6 + test_regress/t/t_interface_modport_bad.out | 2 + .../t/t_interface_param_another_bad.out | 2 + test_regress/t/t_interface_size_bad.out | 4 + test_regress/t/t_interface_top_bad.out | 4 + test_regress/t/t_interface_typo_bad.out | 6 + test_regress/t/t_interface_wrong_bad.out | 2 + test_regress/t/t_lint_always_comb_bad.out | 8 + test_regress/t/t_lint_blksync_bad.out | 4 + test_regress/t/t_lint_bsspace_bad.out | 4 + test_regress/t/t_lint_colonplus_bad.out | 2 + test_regress/t/t_lint_comb_bad.out | 2 + test_regress/t/t_lint_declfilename_bad.out | 2 + test_regress/t/t_lint_defparam_bad.out | 2 + test_regress/t/t_lint_ifdepth_bad.out | 2 + test_regress/t/t_lint_implicit_bad.out | 8 + test_regress/t/t_lint_implicit_def_bad.out | 4 + test_regress/t/t_lint_import_name_bad.out | 2 + test_regress/t/t_lint_importstar_bad.out | 2 + test_regress/t/t_lint_in_inc_bad.out | 6 +- test_regress/t/t_lint_incabspath_bad.out | 2 + test_regress/t/t_lint_infinite.out | 4 + test_regress/t/t_lint_input_eq_bad.out | 2 + test_regress/t/t_lint_latch_bad.out | 2 + test_regress/t/t_lint_literal_bad.out | 2 + test_regress/t/t_lint_mod_paren_bad.out | 2 + test_regress/t/t_lint_modport_dir_bad.out | 2 + test_regress/t/t_lint_multidriven_bad.out | 8 + test_regress/t/t_lint_once_bad.out | 4 + test_regress/t/t_lint_pindup_bad.out | 18 ++ test_regress/t/t_lint_pkg_colon_bad.out | 4 + test_regress/t/t_lint_realcvt_bad.out | 2 + test_regress/t/t_lint_repeat_bad.out | 2 + test_regress/t/t_lint_restore_bad.out | 2 + test_regress/t/t_lint_rsvd_bad.out | 6 + test_regress/t/t_lint_setout_bad.out | 2 + test_regress/t/t_lint_setout_bad_noinl.out | 2 + test_regress/t/t_lint_subout_bad.out | 6 + test_regress/t/t_lint_syncasyncnet_bad.out | 4 + test_regress/t/t_lint_syncasyncnet_bad.v | 2 +- test_regress/t/t_lint_unsized_bad.out | 2 + test_regress/t/t_lint_unused_bad.out | 12 + test_regress/t/t_lint_unused_iface_bad.out | 4 + test_regress/t/t_lint_width_bad.out | 18 ++ test_regress/t/t_math_shift_over_bad.out | 2 + test_regress/t/t_mem_multi_ref_bad.out | 18 ++ test_regress/t/t_mem_packed_bad.out | 2 + test_regress/t/t_mem_slice_bad.out | 14 ++ test_regress/t/t_mem_slice_dtype_bad.out | 2 + test_regress/t/t_metacmt_onoff.out | 4 + test_regress/t/t_mod_dup_bad.out | 8 + test_regress/t/t_multitop_sig_bad.out | 6 + test_regress/t/t_order_clkinst_bad.out | 14 ++ test_regress/t/t_package_export_bad.out | 12 + test_regress/t/t_param_circ_bad.out | 2 + test_regress/t/t_param_concat_bad.out | 6 + test_regress/t/t_param_default_bad.out | 2 + test_regress/t/t_param_default_presv_bad.out | 2 + test_regress/t/t_param_scope_bad.out | 2 + test_regress/t/t_param_sel_range_bad.out | 2 + test_regress/t/t_param_up_bad.out | 2 + test_regress/t/t_past_bad.out | 4 + test_regress/t/t_past_unsup_bad.out | 2 + test_regress/t/t_pp_misdef_bad.out | 4 + test_regress/t/t_pp_underline_bad.out | 4 + test_regress/t/t_preproc_inc_notfound_bad.out | 2 + test_regress/t/t_select_bad_msb.out | 4 + test_regress/t/t_select_bad_range.out | 4 + test_regress/t/t_select_bad_range2.out | 2 + test_regress/t/t_select_bad_range3.out | 2 + test_regress/t/t_select_bad_tri.out | 2 + test_regress/t/t_struct_init_bad.out | 2 + test_regress/t/t_struct_notfound_bad.out | 2 + test_regress/t/t_struct_unpacked_bad.out | 2 + test_regress/t/t_tri_pull2_bad.out | 4 + test_regress/t/t_tri_pull_bad.out | 4 + test_regress/t/t_tri_pullvec_bad.out | 8 + test_regress/t/t_typedef_circ_bad.out | 2 + test_regress/t/t_udp_bad.out | 2 + test_regress/t/t_unopt_combo_bad.out | 2 + test_regress/t/t_unopt_converge_unopt_bad.out | 2 + test_regress/t/t_unoptflat_simple_2_bad.out | 2 + test_regress/t/t_var_bad_hide.out | 8 + test_regress/t/t_var_bad_hide2.out | 4 + test_regress/t/t_var_bad_sameas.out | 20 ++ test_regress/t/t_var_bad_sv.out | 6 + test_regress/t/t_var_const_bad.out | 2 + test_regress/t/t_var_dup2_bad.out | 8 + test_regress/t/t_var_dup_bad.out | 70 ++++++ test_regress/t/t_var_in_assign_bad.out | 4 + test_regress/t/t_var_notfound_bad.out | 12 + test_regress/t/t_var_port2_bad.out | 4 + test_regress/t/t_var_port_bad.out | 2 + test_regress/t/t_var_ref_bad1.out | 2 + test_regress/t/t_var_ref_bad2.out | 4 + test_regress/t/t_var_ref_bad3.out | 2 + test_regress/t/t_var_rsvd_bad.out | 4 + test_regress/t/t_var_suggest_bad.out | 4 + test_regress/t/t_var_types_bad.out | 18 ++ test_regress/t/t_wire_beh_bad.out | 4 + 175 files changed, 1266 insertions(+), 262 deletions(-) diff --git a/Changes b/Changes index 972eff6f1..09f11af2d 100644 --- a/Changes +++ b/Changes @@ -4,7 +4,7 @@ The contributors that suggested a given feature are shown in []. Thanks! * Verilator 4.017 devel -** Offer suggestions on bad identifier errors. +** When showing an error, show source code and offer suggestions of replacements. *** Change MULTITOP to warning to help linting, see manual. diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index e62def7a7..f66d71452 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -1024,8 +1024,12 @@ void AstNode::dumpPtrs(std::ostream& os) const { } void AstNode::dumpTree(std::ostream& os, const string& indent, int maxDepth) { + static int s_debugFileline = v3Global.opt.debugSrcLevel("fileline"); // --debugi-fileline 9 os<8) { os<= 9) { + os<warnContextSecondary(); + } if (maxDepth==1) { if (op1p()||op2p()||op3p()||op4p()) { os<m_backp <<" =editCountLast())?"#>":">") - <<" {"<filenameLetters()<lineno()<<"}"; + <<" {"<filenameLetters()<lastLineno()<<"}"; if (user1p()) str<<" u1="<ascii()<filename())) { @@ -127,7 +127,7 @@ public: m_lastFilename = filelinep->filename(); } // Process all on/offs for lines up to and including the current line - int curlineno = filelinep->lineno(); + int curlineno = filelinep->lastLineno(); for (; m_lastIt != m_lastEnd; ++m_lastIt) { if (m_lastIt->m_lineno > curlineno) break; //UINFO(9," Hit "<<*m_lastIt<lineno(); + m_lastLineno = filelinep->lastLineno(); } } }; diff --git a/src/V3FileLine.cpp b/src/V3FileLine.cpp index 56d865343..cba37efd1 100644 --- a/src/V3FileLine.cpp +++ b/src/V3FileLine.cpp @@ -23,6 +23,7 @@ #include "V3Error.h" #include "V3FileLine.h" +#include "V3String.h" #ifndef _V3ERROR_NO_GLOBAL_ # include "V3Ast.h" # include "V3Global.h" @@ -31,6 +32,7 @@ # include "V3File.h" #endif +#include #include #include VL_INCLUDE_UNORDERED_SET @@ -80,13 +82,73 @@ void FileLineSingleton::fileNameNumMapDumpXml(std::ostream& os) { os<<"\n"; } +//###################################################################### +// VFileContents class functions + +int VFileContent::debug() { + static int level = -1; + if (VL_UNLIKELY(level < 0)) level = v3Global.opt.debugSrcLevel(__FILE__); + return level; +} + +void VFileContent::pushText(const string& text) { + if (m_lines.size() == 0) { + m_lines.push_back(""); // no such thing as line [0] + m_lines.push_back(""); // start with no leftover + } + + // Any leftover text is stored on largest line (might be "") + string leftover = m_lines.back() + text; m_lines.pop_back(); + + // Insert line-by-line + string::size_type pos = 0; + string::size_type line_start = 0; + while (1) { + string::size_type line_end = leftover.find("\n", line_start); + if (line_end != string::npos) { + string oneline (leftover, line_start, line_end-line_start+1); + m_lines.push_back(oneline); // Keeps newline + UINFO(9, "PushStream[ct"<= (int)m_lines.size())) { + if (debug() || v3Global.opt.debugCheck()) { + return ("%Error-internal-contents-bad-ct"+cvtToStr(m_id) + +"-ln"+cvtToStr(lineno)); + } else return ""; + } + string text = m_lines[lineno]; + UINFO(9, "Get Stream[ct"<ascii(); + return os; +} + //###################################################################### // FileLine class functions FileLine::FileLine(FileLine::EmptySecret) { // Sort of a singleton - m_lineno = 0; + m_firstLineno = 0; + m_lastLineno = 0; + m_firstColumn = 0; + m_lastColumn = 0; m_filenameno = singleton().nameToNumber(FileLine::builtInFilename()); + m_contentp = NULL; + m_contentLineno = 0; m_parent = NULL; m_warnOn = 0; @@ -97,13 +159,16 @@ FileLine::FileLine(FileLine::EmptySecret) { } string FileLine::lineDirectiveStrg(int enterExit) const { - char numbuf[20]; sprintf(numbuf, "%d", lineno()); + char numbuf[20]; sprintf(numbuf, "%d", lastLineno()); char levelbuf[20]; sprintf(levelbuf, "%d", enterExit); return (string("`line ")+numbuf+" \""+filename()+"\" "+levelbuf+"\n"); } void FileLine::lineDirective(const char* textp, int& enterExitRef) { // Handle `line directive + // Does not parse streamNumber/streamLineno as the next input token + // will come from the same stream as the previous line. + // Skip `line while (*textp && isspace(*textp)) textp++; while (*textp && !isspace(*textp)) textp++; @@ -134,6 +199,18 @@ void FileLine::lineDirective(const char* textp, int& enterExitRef) { //printf ("PPLINE %d '%s'\n", s_lineno, s_filename.c_str()); } +void FileLine::forwardToken(const char* textp, size_t size, bool trackLines) { + for (const char* sp = textp; size && *sp; ++sp, --size) { + if (*sp == '\n') { + if (trackLines) linenoInc(); + m_lastColumn = 1; + } else if (*sp == '\r') { + } else { // Tabs are considered one column; hence column means number of chars + ++m_lastColumn; + } + } +} + FileLine* FileLine::copyOrSameFileLine() { // When a fileline is "used" to produce a node, calls this function. // Return this, or a copy of this @@ -177,12 +254,19 @@ const string FileLine::profileFuncname() const { != string::npos) { name.replace(pos, 1, "_"); } - name += "__l"+cvtToStr(lineno()); + name += "__l"+cvtToStr(lastLineno()); return name; } +string FileLine::asciiLineCol() const { + return (cvtToStr(firstLineno())+"-"+cvtToStr(lastLineno()) + +":"+cvtToStr(firstColumn())+"-"+cvtToStr(lastColumn()) + +"["+(m_contentp ? m_contentp->ascii() : "ct0") + +"+"+cvtToStr(m_contentLineno)+"]"); +} string FileLine::ascii() const { - return filename()+":"+cvtToStr(lineno()); + // For most errors especially in the parser the lastLineno is more accurate than firstLineno + return filename()+":"+cvtToStr(lastLineno()); } std::ostream& operator<<(std::ostream& os, FileLine* fileline) { os <ascii()<<": "<getLine(m_contentLineno); +} +string FileLine::prettySource() const { + string out = source(); + // Drop ignore trailing newline + string::size_type pos = out.find('\n'); + if (pos != string::npos) out = string(out, 0, pos); + // Column tracking counts tabs = 1, so match that when print source + return VString::spaceUnprintable(out); +} + string FileLine::warnContext(bool secondary) const { V3Error::errorContexted(true); string out = ""; - // TODO: Eventually print the original source code here + if (firstLineno()==lastLineno() && firstColumn()) { + string sourceLine = prettySource(); + // Don't show super-long lines as can fill screen and unlikely to help user + if (!sourceLine.empty() + && sourceLine.length() < SHOW_SOURCE_MAX_LENGTH + && sourceLine.length() >= (lastColumn()-1)) { + out += sourceLine+"\n"; + out += string((firstColumn()-1), ' ')+'^'; + // Can't use UASSERT_OBJ used in warnings already inside the error end handler + UASSERT_STATIC(lastColumn() >= firstColumn(), "Column numbers backwards"); + if (lastColumn() != firstColumn()) { + out += string((lastColumn()-firstColumn()-1), '~'); + } + out += "\n"; + } + } if (!secondary) { // Avoid printing long paths on informational part of error for (FileLine* parentFl = parent(); parentFl; parentFl = parentFl->parent()) { if (parentFl->filenameIsGlobal()) break; diff --git a/src/V3FileLine.h b/src/V3FileLine.h index 4599de798..68a17a81e 100644 --- a/src/V3FileLine.h +++ b/src/V3FileLine.h @@ -54,7 +54,6 @@ class FileLineSingleton { ~FileLineSingleton() { } protected: friend class FileLine; - // METHODS int nameToNumber(const string& filename); const string numberToName(int filenameno) const { return m_names[filenameno]; } const V3LangCode numberToLang(int filenameno) const { return m_languages[filenameno]; } @@ -64,15 +63,40 @@ protected: static const string filenameLetters(int fileno); }; +//! All source lines from a file/stream, to enable errors to show sources +class VFileContent { + // MEMBERS + int m_id; // Content ID number + std::deque m_lines; // Source text lines +public: + VFileContent() { static int s_id = 0; m_id = ++s_id; } + ~VFileContent() { } + // METHODS + void pushText(const string& text); // Add arbitrary text (need not be line-by-line) + string getLine(int lineno) const; + string ascii() const { return "ct"+cvtToStr(m_id); } + static int debug(); +}; +std::ostream& operator<<(std::ostream& os, VFileContent* contentp); + //! File and line number of an object, mostly for error reporting //! This class is instantiated for every source code line (potentially //! millions). To save space, per-file information (e.g. filename, source //! language is held in tables in the FileLineSingleton class. class FileLine { + // CONSTANTS + enum { SHOW_SOURCE_MAX_LENGTH = 400 }; // Don't show source lines > this long + // MEMBERS - int m_lineno; // `line corrected line number + // Columns here means number of chars from beginning (i.e. tabs count as one) + int m_firstLineno; // `line corrected token's first line number + int m_firstColumn; // `line corrected token's first column number + int m_lastLineno; // `line corrected token's last line number + int m_lastColumn; // `line corrected token's last column number int m_filenameno; // `line corrected filename number + int m_contentLineno; // Line number within source stream + VFileContent* m_contentp; // Source text contents line is within FileLine* m_parent; // Parent line that included this line std::bitset m_warnOn; @@ -96,20 +120,22 @@ private: } public: FileLine(const string& filename) { - m_lineno = 0; - m_filenameno = singleton().nameToNumber(filename); - m_parent = NULL; - m_warnOn = defaultFileLine().m_warnOn; - } - FileLine(const string& filename, int lineno) { - m_lineno = lineno; + m_lastLineno = m_firstLineno = 0; + m_lastColumn = m_firstColumn = 0; m_filenameno = singleton().nameToNumber(filename); + m_contentLineno = 0; + m_contentp = NULL; m_parent = NULL; m_warnOn = defaultFileLine().m_warnOn; } explicit FileLine(FileLine* fromp) { - m_lineno = fromp->m_lineno; + m_firstLineno = fromp->m_firstLineno; + m_firstColumn = fromp->m_firstColumn; + m_lastLineno = fromp->m_lastLineno; + m_lastColumn = fromp->m_lastColumn; m_filenameno = fromp->m_filenameno; + m_contentLineno = fromp->m_contentLineno; + m_contentp = fromp->m_contentp; m_parent = fromp->m_parent; m_warnOn = fromp->m_warnOn; } @@ -122,18 +148,33 @@ public: static void* operator new(size_t size); static void operator delete(void* obj, size_t size); #endif + void newContent() { m_contentp = new VFileContent; m_contentLineno = 1; } // METHODS - void lineno(int num) { m_lineno = num; } + void lineno(int num) { m_firstLineno = num; m_lastLineno = num; + m_firstColumn = m_lastColumn = 1; } void language(V3LangCode lang) { singleton().numberToLang(m_filenameno, lang); } void filename(const string& name) { m_filenameno = singleton().nameToNumber(name); } void parent(FileLine* fileline) { m_parent = fileline; } void lineDirective(const char* textp, int& enterExitRef); - void linenoInc() { m_lineno++; } - - int lineno() const { return m_lineno; } + void linenoInc() { m_lastLineno++; m_lastColumn = 1; m_contentLineno++; } + void startToken() { m_firstLineno = m_lastLineno; + m_firstColumn = m_lastColumn; } + // Advance last line/column based on given text + void forwardToken(const char* textp, size_t size, bool trackLines=true); + int firstLineno() const { return m_firstLineno; } + int firstColumn() const { return m_firstColumn; } + int lastLineno() const { return m_lastLineno; } + int lastColumn() const { return m_lastColumn; } + VFileContent* contentp() const { return m_contentp; } + // If not otherwise more specific, use last lineno for errors etc, + // as the parser errors etc generally make more sense pointing at the last parse point + int lineno() const { return m_lastLineno; } + string source() const; + string prettySource() const; // Source, w/stripped unprintables and newlines FileLine* parent() const { return m_parent; } V3LangCode language() const { return singleton().numberToLang(m_filenameno); } string ascii() const; + string asciiLineCol() const; const string filename() const { return singleton().numberToName(m_filenameno); } bool filenameIsGlobal() const { return (filename() == commandLineFilename() || filename() == builtInFilename()); } @@ -141,7 +182,7 @@ public: const string filebasename() const; const string filebasenameNoExt() const; const string profileFuncname() const; - const string xml() const { return "fl=\""+filenameLetters()+cvtToStr(lineno())+"\""; } + const string xml() const { return "fl=\""+filenameLetters()+cvtToStr(lastLineno())+"\""; } string lineDirectiveStrg(int enterExit) const; // Turn on/off warning messages on this line. @@ -199,7 +240,10 @@ public: /// Simplified information vs warnContextPrimary() to make dump clearer string warnContextSecondary() const { return warnContext(true); } bool operator==(FileLine rhs) const { - return (m_lineno == rhs.m_lineno + return (m_firstLineno == rhs.m_firstLineno + && m_firstColumn == rhs.m_firstColumn + && m_lastLineno == rhs.m_lastLineno + && m_lastColumn == rhs.m_lastColumn && m_filenameno == rhs.m_filenameno && m_warnOn == rhs.m_warnOn); } diff --git a/src/V3ParseImp.cpp b/src/V3ParseImp.cpp index 5c97e24d5..1f7d81491 100644 --- a/src/V3ParseImp.cpp +++ b/src/V3ParseImp.cpp @@ -225,7 +225,9 @@ void V3ParseImp::parseFile(FileLine* fileline, const string& modfilename, bool i string modname = V3Os::filenameNonExt(modfilename); UINFO(2,__FUNCTION__<<": "<newContent(); m_inLibrary = inLibrary; // Preprocess into m_ppBuffer diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h index 4078e8293..819517283 100644 --- a/src/V3ParseImp.h +++ b/src/V3ParseImp.h @@ -160,7 +160,10 @@ public: int lastVerilogState() const { return m_lastVerilogState; } static const char* tokenName(int tok); - void ppPushText(const string& text) { m_ppBuffers.push_back(text); } + void ppPushText(const string& text) { + m_ppBuffers.push_back(text); + if (fileline()->contentp()) fileline()->contentp()->pushText(text); + } size_t ppInputToLex(char* buf, size_t max_size); static V3ParseImp* parsep() { return s_parsep; } diff --git a/src/V3ParseLex.cpp b/src/V3ParseLex.cpp index c28133bef..e2f46b9fb 100644 --- a/src/V3ParseLex.cpp +++ b/src/V3ParseLex.cpp @@ -66,6 +66,7 @@ void V3ParseImp::unputString(const char* textp, size_t length) { int V3ParseImp::yylexReadTok() { // Call yylex() remembering last non-whitespace token + parsep()->fileline()->startToken(); int token = parsep()->m_lexerp->yylex(); m_prevLexToken = token; // Save so can find '#' to parse following number return token; diff --git a/src/V3PreLex.l b/src/V3PreLex.l index fe7013e7f..9e6cf51f5 100644 --- a/src/V3PreLex.l +++ b/src/V3PreLex.l @@ -40,6 +40,12 @@ char* yyourtext() { return yytext; } size_t yyourleng() { return yyleng; } void yyourtext(const char* textp, size_t size) { yytext=(char*)textp; yyleng=size; } +// FL_FWD only tracks columns; preproc uses linenoInc() to track lines, so +// insertion of a \n does not mess up line count +#define FL_FWDC { LEXP->curFilelinep()->forwardToken(yytext, yyleng, false); } +// Use this to break between tokens whereever not return'ing a token (e.g. skipping inside lexer) +#define FL_BRK { LEXP->curFilelinep()->startToken(); } + // Prevent conflicts from perl version static void linenoInc() {LEXP->linenoInc();} static bool pedantic() { return LEXP->m_pedantic; } @@ -83,197 +89,210 @@ bom [\357\273\277] %% {bom} { } -^{ws}*"`line"{ws}+.*{crnl} { LEXP->lineDirective(yytext); +^{ws}*"`line"{ws}+.*{crnl} { FL_FWDC; LEXP->lineDirective(yytext); return VP_LINE; } /* Special directives we recognize */ -"`define" { return VP_DEFINE; } -"`else" { return VP_ELSE; } -"`elsif" { return VP_ELSIF; } -"`endif" { return VP_ENDIF; } -"`ifdef" { return VP_IFDEF; } -"`ifndef" { return VP_IFNDEF; } -"`include" { return VP_INCLUDE; } -"`undef" { return VP_UNDEF; } -"`undefineall" { return VP_UNDEFINEALL; } -"`error" { if (!pedantic()) return VP_ERROR; else return VP_DEFREF; } -"`__FILE__" { static string rtnfile; +"`define" { FL_FWDC; return VP_DEFINE; } +"`else" { FL_FWDC; return VP_ELSE; } +"`elsif" { FL_FWDC; return VP_ELSIF; } +"`endif" { FL_FWDC; return VP_ENDIF; } +"`ifdef" { FL_FWDC; return VP_IFDEF; } +"`ifndef" { FL_FWDC; return VP_IFNDEF; } +"`include" { FL_FWDC; return VP_INCLUDE; } +"`undef" { FL_FWDC; return VP_UNDEF; } +"`undefineall" { FL_FWDC; return VP_UNDEFINEALL; } +"`error" { FL_FWDC; if (!pedantic()) return VP_ERROR; else return VP_DEFREF; } +"`__FILE__" { FL_FWDC; + static string rtnfile; rtnfile = '"'; rtnfile += LEXP->curFilelinep()->filename(); rtnfile += '"'; yytext = (char*)rtnfile.c_str(); yyleng = rtnfile.length(); return VP_STRING; } -"`__LINE__" { static char buf[10]; - sprintf(buf, "%d", LEXP->curFilelinep()->lineno()); +"`__LINE__" { FL_FWDC; + static char buf[10]; + sprintf(buf, "%d", LEXP->curFilelinep()->lastLineno()); yytext = buf; yyleng = strlen(yytext); return VP_TEXT; } /* Pass-through strings */ {quote} { yy_push_state(STRMODE); yymore(); } -<> { linenoInc(); yyerrorf("EOF in unterminated string"); yyleng=0; yyterminate(); } -{crnl} { linenoInc(); yyerrorf("Unterminated string"); BEGIN(INITIAL); } +<> { FL_FWDC; linenoInc(); yyerrorf("EOF in unterminated string"); + yyleng=0; yyterminate(); } +{crnl} { FL_FWDC; linenoInc(); yyerrorf("Unterminated string"); + FL_BRK; BEGIN(INITIAL); } {word} { yymore(); } [^\"\\] { yymore(); } [\\]{crnl} { linenoInc(); yymore(); } -[\\]{wsn}+{crnl} { yyless(1); LEXP->warnBackslashSpace(); } +[\\]{wsn}+{crnl} { LEXP->warnBackslashSpace(); yyless(1); } [\\]. { yymore(); } -{quote} { yy_pop_state(); +{quote} { FL_FWDC; yy_pop_state(); if (LEXP->m_parenLevel || LEXP->m_defQuote) { - LEXP->m_defQuote=false; appendDefValue(yytext, yyleng); yyleng=0; + LEXP->m_defQuote=false; appendDefValue(yytext, yyleng); + yyleng=0; FL_BRK; } else return VP_STRING; } /* Stringification */ -{tickquote} { yy_push_state(STRIFY); return VP_STRIFY; } -<> { linenoInc(); yyerrorf("EOF in unterminated '\""); yyleng=0; yyterminate(); } -"`\\`\"" { return VP_BACKQUOTE; } +{tickquote} { FL_FWDC; yy_push_state(STRIFY); return VP_STRIFY; } +<> { FL_FWDC; linenoInc(); yyerrorf("EOF in unterminated '\""); + yyleng=0; yyterminate(); } +"`\\`\"" { FL_FWDC; return VP_BACKQUOTE; } {quote} { yy_push_state(STRMODE); yymore(); } -{tickquote} { yy_pop_state(); return VP_STRIFY; } -{symbdef} { return VP_SYMBOL; } -{symbdef}`` { yyleng-=2; return VP_SYMBOL_JOIN; } -"`"{symbdef} { return VP_DEFREF; } -"`"{symbdef}`` { yyleng-=2; return VP_DEFREF_JOIN; } -`` { yyleng-=2; return VP_JOIN; } -{crnl} { linenoInc(); yytext = (char*)"\n"; yyleng = 1; return VP_WHITE; } -{wsn}+ { return VP_WHITE; } -{drop} { } -[\r] { } -. { return VP_TEXT; } +{tickquote} { FL_FWDC; yy_pop_state(); return VP_STRIFY; } +{symbdef} { FL_FWDC; return VP_SYMBOL; } +{symbdef}`` { FL_FWDC; yyleng-=2; return VP_SYMBOL_JOIN; } +"`"{symbdef} { FL_FWDC; return VP_DEFREF; } +"`"{symbdef}`` { FL_FWDC; yyleng-=2; return VP_DEFREF_JOIN; } +`` { FL_FWDC; yyleng-=2; return VP_JOIN; } +{crnl} { FL_FWDC; linenoInc(); yytext = (char*)"\n"; yyleng = 1; return VP_WHITE; } +{wsn}+ { FL_FWDC; return VP_WHITE; } +{drop} { FL_FWDC; FL_BRK; } +[\r] { FL_FWDC; FL_BRK; } +. { FL_FWDC; return VP_TEXT; } /* Protected blocks */ "`protected" { yy_push_state(PRTMODE); yymore(); } -<> { linenoInc(); yyerrorf("EOF in `protected"); yyleng = 0; yyterminate(); } -{crnl} { linenoInc(); return VP_TEXT; } +<> { FL_FWDC; linenoInc(); yyerrorf("EOF in `protected"); + yyleng = 0; yyterminate(); } +{crnl} { FL_FWDC; linenoInc(); return VP_TEXT; } . { yymore(); } -"`endprotected" { yy_pop_state(); return VP_TEXT; } +"`endprotected" { FL_FWDC; yy_pop_state(); return VP_TEXT; } /* Pass-through include <> filenames */ -<> { linenoInc(); yyerrorf("EOF in unterminated include filename"); yyleng = 0; yyterminate(); } -{crnl} { linenoInc(); yyerrorf("Unterminated include filename"); BEGIN(INITIAL); } +<> { FL_FWDC; linenoInc(); yyerrorf("EOF in unterminated include filename"); + yyleng = 0; yyterminate(); } +{crnl} { FL_FWDC; linenoInc(); yyerrorf("Unterminated include filename"); + FL_BRK; BEGIN(INITIAL); } [^\>\\] { yymore(); } [\\]. { yymore(); } -[\>] { yy_pop_state(); return VP_STRING; } +[\>] { FL_FWDC; yy_pop_state(); return VP_STRING; } /* Reading definition formal parenthesis (or not) to begin formal arguments */ /* Note '(' must IMMEDIATELY follow definition name */ -[(] { appendDefValue("(", 1); LEXP->m_formalLevel=1; BEGIN(DEFFORM); } -{crnl} { yy_pop_state(); unput('\n'); yyleng=0; return VP_DEFFORM; } /* DEFVAL will later grab the return */ -<> { yy_pop_state(); return VP_DEFFORM; } /* empty formals */ -. { yy_pop_state(); unput(yytext[yyleng-1]); yyleng=0; return VP_DEFFORM; } /* empty formals */ +[(] { FL_FWDC; appendDefValue("(", 1); LEXP->m_formalLevel=1; + FL_BRK; BEGIN(DEFFORM); } +{crnl} { FL_FWDC; yy_pop_state(); unput('\n'); yyleng=0; return VP_DEFFORM; } /* DEFVAL will later grab the return */ +<> { FL_FWDC; yy_pop_state(); return VP_DEFFORM; } /* empty formals */ +. { FL_FWDC; yy_pop_state(); unput(yytext[yyleng-1]); yyleng=0; return VP_DEFFORM; } /* empty formals */ /* Reading definition formals (declaration of a define) */ -[(] { appendDefValue(yytext, yyleng); yyleng=0; ++LEXP->m_formalLevel; } -[)] { appendDefValue(yytext, yyleng); yyleng=0; - if ((--LEXP->m_formalLevel)==0) { yy_pop_state(); return VP_DEFFORM; } } +[(] { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; yyleng=0; ++LEXP->m_formalLevel; } +[)] { FL_FWDC; appendDefValue(yytext, yyleng); yyleng=0; + if ((--LEXP->m_formalLevel)==0) { yy_pop_state(); return VP_DEFFORM; } + FL_BRK; } "/*" { yy_push_state(CMTMODE); yymore(); } -"//"[^\n\r]* { return VP_COMMENT;} -{drop} { } -<> { linenoInc(); yy_pop_state(); yyerrorf("Unterminated ( in define formal arguments."); yyleng=0; return VP_DEFFORM; } -{crnl} { linenoInc(); appendDefValue((char*)"\n", 1); } /* Include return so can maintain output line count */ -[\\]{wsn}+{crnl} { yyless(1); LEXP->warnBackslashSpace(); } -[\\]{crnl} { linenoInc(); appendDefValue((char*)"\\\n", 2); } /* Include return so can maintain output line count */ +"//"[^\n\r]* { FL_FWDC; return VP_COMMENT;} +{drop} { FL_FWDC; FL_BRK; } +<> { FL_FWDC; linenoInc(); yy_pop_state(); yyerrorf("Unterminated ( in define formal arguments."); + yyleng=0; return VP_DEFFORM; } +{crnl} { FL_FWDC; linenoInc(); appendDefValue((char*)"\n", 1); FL_BRK; } /* Include return so can maintain output line count */ +[\\]{wsn}+{crnl} { LEXP->warnBackslashSpace(); yyless(1); } +[\\]{crnl} { FL_FWDC; linenoInc(); appendDefValue((char*)"\\\n", 2); FL_BRK; } /* Include return so can maintain output line count */ {quote} { LEXP->m_defQuote=true; yy_push_state(STRMODE); yymore(); } /* Legal only in default values */ -"`\\`\"" { appendDefValue(yytext, yyleng); } /* Maybe illegal, otherwise in default value */ -{tickquote} { appendDefValue(yytext, yyleng); } /* Maybe illegal, otherwise in default value */ -[{\[] { LEXP->m_formalLevel++; appendDefValue(yytext, yyleng); } -[}\]] { LEXP->m_formalLevel--; appendDefValue(yytext, yyleng); } +"`\\`\"" { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; } /* Maybe illegal, otherwise in default value */ +{tickquote} { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; } /* Maybe illegal, otherwise in default value */ +[{\[] { FL_FWDC; LEXP->m_formalLevel++; appendDefValue(yytext, yyleng); FL_BRK; } +[}\]] { FL_FWDC; LEXP->m_formalLevel--; appendDefValue(yytext, yyleng); FL_BRK; } [^\/\*\n\r\\(){}\[\]\"]+ | [\\][^\n\r] | -. { appendDefValue(yytext, yyleng); } +. { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; } /* Reading definition value (declaration of a define's text) */ "/*" { LEXP->m_defCmtSlash=false; yy_push_state(DEFCMT); yymore(); } /* Special comment parser */ -"//"[^\n\r]*[\\]{crnl} { linenoInc(); appendDefValue((char*)"\n", 1); } /* Spec says // not part of define value */ -"//"[^\n\r]* { return VP_COMMENT;} -{drop} { } -<> { linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return VP_DEFVALUE; } /* Technically illegal, but people complained */ -{crnl} { linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return VP_DEFVALUE; } -[\\]{wsn}+{crnl} { yyless(1); LEXP->warnBackslashSpace(); } -[\\]{crnl} { linenoInc(); appendDefValue((char*)"\\\n", 2); } /* Return, AND \ is part of define value */ +"//"[^\n\r]*[\\]{crnl} { FL_FWDC; linenoInc(); appendDefValue((char*)"\n", 1); FL_BRK; } /* Spec says // not part of define value */ +"//"[^\n\r]* { FL_FWDC; return VP_COMMENT;} +{drop} { FL_FWDC; FL_BRK; } +<> { FL_FWDC; linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return VP_DEFVALUE; } /* Technically illegal, but people complained */ +{crnl} { FL_FWDC; linenoInc(); yy_pop_state(); yytext=(char*)"\n"; yyleng=1; return VP_DEFVALUE; } +[\\]{wsn}+{crnl} { LEXP->warnBackslashSpace(); yyless(1); } +[\\]{crnl} { FL_FWDC; linenoInc(); appendDefValue((char*)"\\\n", 2); FL_BRK; } /* Return, AND \ is part of define value */ {quote} { LEXP->m_defQuote = true; yy_push_state(STRMODE); yymore(); } [^\/\*\n\r\\\"]+ | [\\][^\n\r] | -. { appendDefValue(yytext, yyleng); } +. { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; } /* Comments inside define values - if embedded get added to define value per spec */ /* - if no \{crnl} ending then the comment belongs to the next line, as a non-embedded comment */ /* - if all but (say) 3rd line is missing \ then it's indeterminate */ -"*/" { yy_pop_state(); appendDefValue(yytext, yyleng); } -[\\]{wsn}+{crnl} { yyless(1); LEXP->warnBackslashSpace(); } -[\\]{crnl} { linenoInc(); LEXP->m_defCmtSlash=true; - appendDefValue(yytext, yyleng-2); appendDefValue((char*)"\n", 1); } /* Return but not \ */ +"*/" { FL_FWDC; yy_pop_state(); appendDefValue(yytext, yyleng); FL_BRK; } +[\\]{wsn}+{crnl} { LEXP->warnBackslashSpace(); yyless(1); } +[\\]{crnl} { FL_FWDC; linenoInc(); LEXP->m_defCmtSlash=true; + appendDefValue(yytext, yyleng-2); appendDefValue((char*)"\n", 1); /* Return but not \ */ + FL_BRK; } {crnl} { linenoInc(); yymore(); if (LEXP->m_defCmtSlash) yyerrorf("One line of /* ... */ is missing \\ before newline"); BEGIN(CMTMODE); } {word} { yymore(); } . { yymore(); } -<> { yyerrorf("EOF in '/* ... */' block comment\n"); yyleng=0; yyterminate(); } +<> { FL_FWDC; yyerrorf("EOF in '/* ... */' block comment\n"); yyleng=0; yyterminate(); } /* Define arguments (use of a define) */ "/*" { yy_push_state(CMTMODE); yymore(); } -"//"[^\n\r]* { return VP_COMMENT;} -{drop} { } -<> { yyerrorf("EOF in define argument list\n"); yyleng = 0; yyterminate(); } -{crnl} { linenoInc(); yytext=(char*)"\n"; yyleng=1; return VP_WHITE; } +"//"[^\n\r]* { FL_FWDC; return VP_COMMENT; } +{drop} { FL_FWDC; FL_BRK; } +<> { FL_FWDC; yyerrorf("EOF in define argument list\n"); yyleng = 0; yyterminate(); } +{crnl} { FL_FWDC; linenoInc(); yytext=(char*)"\n"; yyleng=1; return VP_WHITE; } {quote} { yy_push_state(STRMODE); yymore(); } -"`\\`\"" { appendDefValue(yytext, yyleng); } /* Literal text */ -{tickquote} { yy_push_state(STRIFY); return VP_STRIFY; } -[{\[] { LEXP->m_parenLevel++; appendDefValue(yytext, yyleng); } -[}\]] { LEXP->m_parenLevel--; appendDefValue(yytext, yyleng); } -[(] { LEXP->m_parenLevel++; +"`\\`\"" { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; } /* Literal text */ +{tickquote} { FL_FWDC; yy_push_state(STRIFY); return VP_STRIFY; } +[{\[] { FL_FWDC; LEXP->m_parenLevel++; appendDefValue(yytext, yyleng); FL_BRK; } +[}\]] { FL_FWDC; LEXP->m_parenLevel--; appendDefValue(yytext, yyleng); FL_BRK; } +[(] { FL_FWDC; LEXP->m_parenLevel++; // Note paren level 0 means before "(" of starting args // Level 1 means "," between arguments // Level 2+ means one inside the () of an argument if (LEXP->m_parenLevel>1) { - appendDefValue(yytext, yyleng); + appendDefValue(yytext, yyleng); FL_BRK; } else { return VP_TEXT; }} -[)] { LEXP->m_parenLevel--; +[)] { FL_FWDC; LEXP->m_parenLevel--; if (LEXP->m_parenLevel>0) { - appendDefValue(yytext, yyleng); + appendDefValue(yytext, yyleng); FL_BRK; } else { yy_pop_state(); return VP_DEFARG; }} -[,] { if (LEXP->m_parenLevel>1) { - appendDefValue(yytext, yyleng); +[,] { FL_FWDC; if (LEXP->m_parenLevel>1) { + appendDefValue(yytext, yyleng); FL_BRK; } else { yy_pop_state(); return VP_DEFARG; }} -"`"{symbdef} { appendDefValue(yytext, yyleng); } /* defref in defref - outer macro expands first */ -"`"{symbdef}`` { appendDefValue(yytext, yyleng); } /* defref in defref - outer macro expands first */ -`` { appendDefValue(yytext, yyleng); } /* defref in defref - outer macro expands first */ +"`"{symbdef} { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; } /* defref in defref - outer macro expands first */ +"`"{symbdef}`` { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; } /* defref in defref - outer macro expands first */ +`` { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; } /* defref in defref - outer macro expands first */ [^\/\*\n\r\\(,){}\[\]\"`]+ | -. { appendDefValue(yytext, yyleng); } +. { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; } /* One line comments. */ -"//"{ws}*{crnl} { linenoInc(); yytext=(char*)"\n"; yyleng=1; return VP_WHITE; } +"//"{ws}*{crnl} { FL_FWDC; linenoInc(); yytext=(char*)"\n"; yyleng=1; return VP_WHITE; } "//" { yy_push_state(CMTONEM); yymore(); } -[^\n\r]* { yy_pop_state(); return VP_COMMENT; } +[^\n\r]* { FL_FWDC; yy_pop_state(); return VP_COMMENT; } /* C-style comments. */ /**** See also DEFCMT */ /* We distinguish between the start of a comment, and later, to look for prefix comments (deprecated) */ "/*" { yy_push_state(CMTMODE); yymore(); } {ws}+ { yymore(); } -"*/" { yy_pop_state(); return VP_COMMENT; } +"*/" { FL_FWDC; yy_pop_state(); return VP_COMMENT; } {crnl} { linenoInc(); yymore(); } -<> { yyerrorf("EOF in '/* ... */' block comment\n"); yyleng=0; yyterminate(); } +<> { FL_FWDC; yyerrorf("EOF in '/* ... */' block comment\n"); yyleng=0; yyterminate(); } {word} { yymore(); } -. { BEGIN CMTMODE; yymore(); } /* beginning in comment */ +. { yymore(); BEGIN CMTMODE; } /* beginning in comment */ . { yymore(); } /* Define calls */ /* symbdef prevents normal lex rules from making `\`"foo a symbol {`"foo} instead of a BACKQUOTE */ -"`"{symbdef} { return VP_DEFREF; } -"`"{symbdef}`` { yyleng-=2; return VP_DEFREF_JOIN; } +"`"{symbdef} { FL_FWDC; return VP_DEFREF; } +"`"{symbdef}`` { FL_FWDC; yyleng-=2; return VP_DEFREF_JOIN; } /* Generics */ -{crnl} { linenoInc(); yytext=(char*)"\n"; yyleng=1; return VP_WHITE; } -<> { yyterminate(); } /* A "normal" EOF */ -{symb} { return VP_SYMBOL; } -{symb}`` { yyleng-=2; return VP_SYMBOL_JOIN; } -`` { yyleng-=2; return VP_JOIN; } -{wsn}+ { return VP_WHITE; } -{drop} { } -[\r] { } -. { return VP_TEXT; } +{crnl} { FL_FWDC; linenoInc(); yytext=(char*)"\n"; yyleng=1; return VP_WHITE; } +<> { FL_FWDC; yyterminate(); } /* A "normal" EOF */ +{symb} { FL_FWDC; return VP_SYMBOL; } +{symb}`` { FL_FWDC; yyleng-=2; return VP_SYMBOL_JOIN; } +`` { FL_FWDC; yyleng-=2; return VP_JOIN; } +{wsn}+ { FL_FWDC; return VP_WHITE; } +{drop} { FL_FWDC; FL_BRK; } +[\r] { FL_FWDC; FL_BRK; } +. { FL_FWDC; return VP_TEXT; } %% void V3PreLex::pushStateDefArg(int level) { @@ -509,6 +528,7 @@ void V3PreLex::lineDirective(const char* textp) { } void V3PreLex::warnBackslashSpace() { + // Make fileline highlight the specific backslash and space curFilelinep()->v3warn(BSSPACE, "Backslash followed by whitespace, perhaps the whitespace is accidental?"); } diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index 863ac9016..118be67c8 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -267,7 +267,8 @@ public: void configure(FileLine* filelinep) { // configure() separate from constructor to avoid calling abstract functions m_preprocp = this; // Silly, but to make code more similar to Verilog-Perl - m_finFilelinep = new FileLine(filelinep->filename(), 1); + m_finFilelinep = new FileLine(filelinep->filename()); + m_finFilelinep->lineno(1); // Create lexer m_lexp = new V3PreLex(this, filelinep); m_lexp->m_keepComments = m_preprocp->keepComments(); @@ -768,8 +769,16 @@ void V3PreProcImp::openFile(FileLine* fl, V3InFilter* filterp, const string& fil addLineComment(0); } + // Save file contents for future error reporting + FileLine* flsp = new FileLine(filename); + flsp->lineno(1); + flsp->newContent(); + for (StrList::iterator it=wholefile.begin(); it!=wholefile.end(); ++it) { + flsp->contentp()->pushText(*it); + } + // Create new stream structure - m_lexp->scanNewFile(new FileLine(filename, 1)); + m_lexp->scanNewFile(flsp); addLineComment(1); // Enter // Filter all DOS CR's en-mass. This avoids bugs with lexing CRs in the wrong places. @@ -868,6 +877,7 @@ int V3PreProcImp::getRawToken() { if (isEof()) return (VP_EOF); // Snarf next token from the file + m_lexp->curFilelinep()->startToken(); int tok = m_lexp->lex(); if (debug()>=5) debugToken(tok, "RAW"); @@ -883,16 +893,22 @@ int V3PreProcImp::getRawToken() { } void V3PreProcImp::debugToken(int tok, const char* cmtp) { - if (debug()>=5) { + static int s_debugFileline = v3Global.opt.debugSrcLevel("fileline"); // --debugi-fileline 9 + if (debug() >= 5) { string buf = string(yyourtext(), yyourleng()); string::size_type pos; while ((pos = buf.find('\n')) != string::npos) { buf.replace(pos, 1, "\\n"); } while ((pos = buf.find('\r')) != string::npos) { buf.replace(pos, 1, "\\r"); } - fprintf(stderr, "%d: %s %s %s(%d) dr%d: <%d>%-10s: %s\n", - m_lexp->m_tokFilelinep->lineno(), cmtp, m_off?"of":"on", + string flcol = m_lexp->m_tokFilelinep->asciiLineCol(); + fprintf(stderr, "%s: %s %s %s(%d) dr%d: <%d>%-10s: %s\n", + flcol.c_str(), + cmtp, (m_off ? "of" : "on"), procStateName(state()), static_cast(m_states.size()), static_cast(m_defRefs.size()), m_lexp->currentStartState(), tokenName(tok), buf.c_str()); + if (s_debugFileline >= 9) { + std::cerr<m_tokFilelinep->warnContextSecondary()<=5) { string bufcln = V3PreLex::cleanDbgStrg(buf); - fprintf(stderr, "%d: FIN: %-10s: %s\n", - m_lexp->m_tokFilelinep->lineno(), tokenName(tok), bufcln.c_str()); + string flcol = m_lexp->m_tokFilelinep->asciiLineCol(); + fprintf(stderr, "%s: FIN: %-10s: %s\n", + flcol.c_str(), + tokenName(tok), bufcln.c_str()); } // Track `line const char* bufp = buf.c_str(); @@ -1462,14 +1480,17 @@ int V3PreProcImp::getFinalToken(string& buf) { else { if (m_finAtBol && !(tok==VP_TEXT && buf=="\n") && m_preprocp->lineDirectives()) { - if (int outBehind = m_lexp->m_tokFilelinep->lineno() - m_finFilelinep->lineno()) { + if (int outBehind = (m_lexp->m_tokFilelinep->lastLineno() + - m_finFilelinep->lastLineno())) { if (debug()>=5) { - fprintf(stderr, "%d: FIN: readjust, fin at %d request at %d\n", - m_lexp->m_tokFilelinep->lineno(), - m_finFilelinep->lineno(), m_lexp->m_tokFilelinep->lineno()); + string flcol = m_lexp->m_tokFilelinep->asciiLineCol(); + fprintf(stderr, "%s: FIN: readjust, fin at %d request at %d\n", + flcol.c_str(), + m_finFilelinep->lastLineno(), + m_lexp->m_tokFilelinep->lastLineno()); } - m_finFilelinep = new FileLine(m_lexp->m_tokFilelinep->filename(), - m_lexp->m_tokFilelinep->lineno()); + m_finFilelinep->filename(m_lexp->m_tokFilelinep->filename()); + m_finFilelinep->lineno(m_lexp->m_tokFilelinep->lastLineno()); if (outBehind > 0 && (outBehind <= static_cast(V3PreProc::NEWLINES_VS_TICKLINE))) { // Output stream is behind, send newlines to get back in sync @@ -1509,8 +1530,10 @@ string V3PreProcImp::getline() { int tok = getFinalToken(buf/*ref*/); if (debug()>=5) { string bufcln = V3PreLex::cleanDbgStrg(buf); - fprintf(stderr, "%d: GETFETC: %-10s: %s\n", - m_lexp->m_tokFilelinep->lineno(), tokenName(tok), bufcln.c_str()); + string flcol = m_lexp->m_tokFilelinep->asciiLineCol(); + fprintf(stderr, "%s: GETFETC: %-10s: %s\n", + flcol.c_str(), + tokenName(tok), bufcln.c_str()); } if (tok==VP_EOF) { // Add a final newline, if the user forgot the final \n. @@ -1530,8 +1553,10 @@ string V3PreProcImp::getline() { m_lineChars = m_lineChars.erase(0, len); // Remove returned characters if (debug()>=4) { string lncln = V3PreLex::cleanDbgStrg(theLine); - fprintf(stderr, "%d: GETLINE: %s\n", - m_lexp->m_tokFilelinep->lineno(), lncln.c_str()); + string flcol = m_lexp->m_tokFilelinep->asciiLineCol(); + fprintf(stderr, "%s: GETLINE: %s\n", + flcol.c_str(), + lncln.c_str()); } return theLine; } diff --git a/src/V3String.cpp b/src/V3String.cpp index 574b8879f..f9a7c6532 100644 --- a/src/V3String.cpp +++ b/src/V3String.cpp @@ -97,6 +97,15 @@ string VString::quotePercent(const string& str) { return out; } +string VString::spaceUnprintable(const string& str) { + string out; + for (string::const_iterator pos = str.begin(); pos != str.end(); ++pos) { + if (isprint(*pos)) out += *pos; + else out += ' '; + } + return out; +} + //###################################################################### // VHashSha1 diff --git a/src/V3String.h b/src/V3String.h index 5212fc0b1..b09a08c0e 100644 --- a/src/V3String.h +++ b/src/V3String.h @@ -41,6 +41,9 @@ public: static string downcase(const string& str); // Replace any %'s with %% static string quotePercent(const string& str); + // Replace any unprintable with space + // This includes removing tabs, so column tracking is correct + static string spaceUnprintable(const string& str); }; //###################################################################### diff --git a/src/verilog.l b/src/verilog.l index a2a10b176..2810fc2bb 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -41,19 +41,22 @@ extern void yyerrorf(const char* format, ...); //====================================================================== -#define NEXTLINE() {PARSEP->linenoInc();} -#define LINECHECKS(textp,len) { const char* cp=textp; for (int n=len; n; --n) if (cp[n]=='\n') NEXTLINE(); } -#define LINECHECK() LINECHECKS(yytext, yyleng) +#define FL_FWD { PARSEP->fileline()->forwardToken(yytext, yyleng, true); } +// Use this to break between tokens whereever not return'ing a token (e.g. skipping inside lexer) +#define FL_BRK { PARSEP->fileline()->startToken(); } + #define CRELINE() (PARSEP->copyOrSameFileLine()) -#define FL { yylval.fl = CRELINE(); } +#define FL { FL_FWD; yylval.fl = CRELINE(); } #define RETURN_BBOX_SYS_OR_MSG(msg,yytext) { \ - if (!v3Global.opt.bboxSys()) yyerrorf(msg, yytext); \ + if (!v3Global.opt.bboxSys()) { yyerrorf(msg, yytext); FL_BRK; } \ return yaD_IGNORE; } #define ERROR_RSVD_WORD(language) \ - yyerrorf("Unsupported: " language " reserved word not implemented: '%s'", yytext) + do { FL_FWD; \ + yyerrorf("Unsupported: " language " reserved word not implemented: '%s'", yytext); \ + FL_BRK; } while(0) // See V3Read.cpp //void V3ParseImp::statePop() { yy_pop_state(); } @@ -129,8 +132,8 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Verilator control files */ { - {ws} { } /* otherwise ignore white-space */ - {crnl} { NEXTLINE(); } /* Count line numbers */ + {ws} { FL_FWD; FL_BRK; } /* otherwise ignore white-space */ + {crnl} { FL_FWD; FL_BRK; } /* Count line numbers */ "coverage_off" { FL; return yVLT_COVERAGE_OFF; } "coverage_on" { FL; return yVLT_COVERAGE_ON; } @@ -147,10 +150,10 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Verilog 1995 */ { - {ws} { } /* otherwise ignore white-space */ - {crnl} { NEXTLINE(); } /* Count line numbers */ + {ws} { FL_FWD; FL_BRK; } /* otherwise ignore white-space */ + {crnl} { FL_FWD; FL_BRK; } /* Count line numbers */ /* Extensions to Verilog set, some specified by PSL */ - "$c"[0-9]* { FL; return yD_C; } /*Verilator only*/ + "$c"[0-9]* { FL; return yD_C; } /*Verilator only*/ /* System Tasks */ "$acos" { FL; return yD_ACOS; } "$acosh" { FL; return yD_ACOSH; } @@ -241,7 +244,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "endmodule" { FL; return yENDMODULE; } "endprimitive" { FL; return yENDPRIMITIVE; } "endspecify" { FL; return yENDSPECIFY; } - "endtable" { yyerrorf("Syntax error: ENDTABLE outside of TABLE"); } + "endtable" { FL_FWD; yyerrorf("Syntax error: ENDTABLE outside of TABLE"); FL_BRK; } "endtask" { FL; return yENDTASK; } "event" { FL; return yEVENT; } "for" { FL; return yFOR; } @@ -298,7 +301,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "strong1" { FL; return ygenSTRENGTH; } "supply0" { FL; return ySUPPLY0; } "supply1" { FL; return ySUPPLY1; } - "table" { yy_push_state(TABLE); FL; return yTABLE; } + "table" { FL; yy_push_state(TABLE); return yTABLE; } "task" { FL; return yTASK; } "time" { FL; return yTIME; } "tran" { FL; return yTRAN; } @@ -359,7 +362,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "design" { ERROR_RSVD_WORD("Verilog 2001-config"); } "endconfig" { ERROR_RSVD_WORD("Verilog 2001-config"); } "incdir" { ERROR_RSVD_WORD("Verilog 2001-config"); } - "include" { yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented; probably you want `include instead: %s", yytext); } + "include" { FL_FWD; yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented; suggest you want `include instead: %s", yytext); FL_BRK; } "instance" { ERROR_RSVD_WORD("Verilog 2001-config"); } "liblist" { ERROR_RSVD_WORD("Verilog 2001-config"); } "library" { ERROR_RSVD_WORD("Verilog 2001-config"); } @@ -649,7 +652,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* Converted from //{cmt}verilator ...{cmt} by preprocessor */ { - "/*verilator"{ws}*"*/" { } /* Ignore empty comments, may be `endif // verilator */ + "/*verilator"{ws}*"*/" { FL_FWD; FL_BRK; } /* Ignore empty comments, may be `endif // verilator */ "/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; } "/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; } "/*verilator full_case*/" { FL; return yVL_FULL_CASE; } @@ -669,18 +672,18 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "/*verilator sc_bv*/" { FL; return yVL_SC_BV; } "/*verilator sformat*/" { FL; return yVL_SFORMAT; } "/*verilator systemc_clock*/" { FL; return yVL_CLOCK; } - "/*verilator tracing_off*/" {PARSEP->fileline()->tracingOn(false); } - "/*verilator tracing_on*/" {PARSEP->fileline()->tracingOn(true); } - "/*verilator coverage_off*/" {PARSEP->fileline()->coverageOn(false); } - "/*verilator coverage_on*/" {PARSEP->fileline()->coverageOn(true); } - "/*verilator lint_off"[^*]*"*/" {PARSEP->verilatorCmtLint(yytext, true); } - "/*verilator lint_on"[^*]*"*/" {PARSEP->verilatorCmtLint(yytext, false); } - "/*verilator lint_restore*/" {PARSEP->verilatorCmtLintRestore(); } - "/*verilator lint_save*/" {PARSEP->verilatorCmtLintSave(); } - "/*verilator tag"[^*]*"*/" {PARSEP->tag(yytext); } + "/*verilator tracing_off*/" { FL_FWD; PARSEP->fileline()->tracingOn(false); FL_BRK; } + "/*verilator tracing_on*/" { FL_FWD; PARSEP->fileline()->tracingOn(true); FL_BRK; } + "/*verilator coverage_off*/" { FL_FWD; PARSEP->fileline()->coverageOn(false); FL_BRK; } + "/*verilator coverage_on*/" { FL_FWD; PARSEP->fileline()->coverageOn(true); FL_BRK; } + "/*verilator lint_off"[^*]*"*/" { FL_FWD; PARSEP->verilatorCmtLint(yytext, true); FL_BRK; } + "/*verilator lint_on"[^*]*"*/" { FL_FWD; PARSEP->verilatorCmtLint(yytext, false); FL_BRK; } + "/*verilator lint_restore*/" { FL_FWD; PARSEP->verilatorCmtLintRestore(); FL_BRK; } + "/*verilator lint_save*/" { FL_FWD; PARSEP->verilatorCmtLintSave(); FL_BRK; } + "/*verilator tag"[^*]*"*/" { FL_FWD; PARSEP->tag(yytext); FL_BRK; } - "/**/" { } - "/*"[^*]+"*/" {PARSEP->verilatorCmtBad(yytext); } + "/**/" { FL_FWD; FL_BRK; } + "/*"[^*]+"*/" { FL_FWD; PARSEP->verilatorCmtBad(yytext); FL_BRK; } } /************************************************************************/ @@ -806,23 +809,22 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} return yaSTRING; } \" { yy_push_state(STRING); yymore(); } - {vnum} { /* "# 1'b0" is a delay value so must lex as "#" "1" "'b0" */ if (PARSEP->prevLexToken()=='#') { int shortlen = 0; while (isdigit(yytext[shortlen])) shortlen++; if (shortlen) { - // Push rest for later parse + // Push rest past numbers for later parse PARSEP->unputString(yytext+shortlen, yyleng-shortlen); - FL; LINECHECKS(yytext, shortlen); // Return is stuff before the tick - yytext[shortlen] = '\0'; - yylval.nump = PARSEP->newNumber(yylval.fl, (char*)yytext); + yyleng = shortlen; + yytext[yyleng] = '\0'; + FL; yylval.nump = PARSEP->newNumber(yylval.fl, (char*)yytext); return yaINTNUM; } } - FL; LINECHECK(); yylval.nump = PARSEP->newNumber(yylval. fl, (char*)yytext); + FL; yylval.nump = PARSEP->newNumber(yylval. fl, (char*)yytext); return yaINTNUM; } [0-9][_0-9]* { @@ -845,9 +847,9 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* STRINGS */ -<> { yyerrorf("EOF in unterminated string"); yyleng = 0; yy_pop_state(); } -{crnl} { yyerrorf("Unterminated string"); NEXTLINE(); } -\\{crnl} { yymore(); NEXTLINE(); } +<> { FL_FWD; yyerrorf("EOF in unterminated string"); yyleng = 0; yy_pop_state(); FL_BRK; } +{crnl} { FL_FWD; yyerrorf("Unterminated string"); FL_BRK; } +\\{crnl} { yymore(); } \\. { yymore(); } \" { yy_pop_state(); FL; yylval.strp = PARSEP->newString(yytext+1, yyleng-2); @@ -857,12 +859,12 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Attributes */ -{crnl} { yymore(); NEXTLINE(); } -"*)" { yy_pop_state(); } +{crnl} { yymore(); } +"*)" { FL_FWD; yy_pop_state(); FL_BRK; } {word} { yymore(); } . { yymore(); } -<> { yyerrorf("EOF in (*"); - yyleng = 0; yy_pop_state(); } +<> { FL_FWD; yyerrorf("EOF in (*"); + yyleng = 0; yy_pop_state(); FL_BRK; } /************************************************************************/ /* Attributes */ @@ -873,12 +875,12 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /************************************************************************/ /* Tables */ -\\{crnl} { yymore(); NEXTLINE(); } -
{crnl} { NEXTLINE(); yymore(); } +
\\{crnl} { yymore(); } +
{crnl} { yymore(); }
";" { FL; yylval.strp = PARSEP->newString(yytext, yyleng); return yaTABLELINE; }
"endtable" { yy_pop_state(); FL; return yENDTABLE; }
. { yymore(); } -
<> { yyerrorf("EOF in TABLE"); yyleng = 0; yy_pop_state(); } +
<> { FL_FWD; yyerrorf("EOF in TABLE"); yyleng = 0; yy_pop_state(); FL_BRK; } /************************************************************************/ /* Preprocessor */ @@ -886,91 +888,94 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} /* OPTIMIZE: we return one per line, make it one for the entire block */ /* If add to this list also add to V3LanguageWords.h */ { - "`accelerate" { } // Verilog-XL compatibility - "`autoexpand_vectornets" { } // Verilog-XL compatibility - "`celldefine" { PARSEP->inCellDefine(true); } - "`default_decay_time"{ws}+[^\n\r]* { } // Verilog spec - delays only - "`default_nettype"{ws}+"wire" { PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true); } - "`default_nettype"{ws}+"none" { PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, false); } - "`default_nettype"{ws}+[a-zA-Z0-9]* { yyerrorf("Unsupported: `default_nettype of other than none or wire: %s", yytext); } - "`default_trireg_strength"{ws}+[^\n\r]* { yyerrorf("Unsupported: Verilog optional directive not implemented: %s", yytext); } - "`delay_mode_distributed" { } // Verilog spec - delays only - "`delay_mode_path" { } // Verilog spec - delays only - "`delay_mode_unit" { } // Verilog spec - delays only - "`delay_mode_zero" { } // Verilog spec - delays only - "`disable_portfaults" { } // Verilog-XL compatibility - "`enable_portfaults" { } // Verilog-XL compatibility - "`endcelldefine" { PARSEP->inCellDefine(false); } - "`endprotect" { } - "`expand_vectornets" { } // Verilog-XL compatibility - "`inline" { } - "`line"{ws}+[^\n\r]*{crnl} { PARSEP->ppline(yytext); } - "`noaccelerate" { } // Verilog-XL compatibility - "`noexpand_vectornets" { } // Verilog-XL compatibility - "`noremove_gatenames" { } // Verilog-XL compatibility - "`noremove_netnames" { } // Verilog-XL compatibility - "`nosuppress_faults" { } // Verilog-XL compatibility - "`nounconnected_drive" { } // Verilog-XL compatibility - "`portcoerce" { } - "`pragma"{ws}+[^\n\r]* { } // Verilog 2005 - "`protect" { } - "`remove_gatenames" { } // Verilog-XL compatibility - "`remove_netnames" { } // Verilog-XL compatibility - "`resetall" { PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true); } // Rest handled by preproc - "`suppress_faults" { } // Verilog-XL compatibility - "`timescale"{ws}+[^\n\r]* { } // Verilog spec - not supported + "`accelerate" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`autoexpand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`celldefine" { FL_FWD; PARSEP->inCellDefine(true); FL_BRK; } + "`default_decay_time"{ws}+[^\n\r]* { FL_FWD; FL_BRK; } // Verilog spec - delays only + "`default_nettype"{ws}+"wire" { FL_FWD; PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true); FL_BRK; } + "`default_nettype"{ws}+"none" { FL_FWD; PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, false); FL_BRK; } + "`default_nettype"{ws}+[a-zA-Z0-9]* { FL_FWD; yyerrorf("Unsupported: `default_nettype of other than none or wire: %s", yytext); FL_BRK; } + "`default_trireg_strength"{ws}+[^\n\r]* { FL_FWD; yyerrorf("Unsupported: Verilog optional directive not implemented: %s", yytext); FL_BRK; } + "`delay_mode_distributed" { FL_FWD; FL_BRK; } // Verilog spec - delays only + "`delay_mode_path" { FL_FWD; FL_BRK; } // Verilog spec - delays only + "`delay_mode_unit" { FL_FWD; FL_BRK; } // Verilog spec - delays only + "`delay_mode_zero" { FL_FWD; FL_BRK; } // Verilog spec - delays only + "`disable_portfaults" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`enable_portfaults" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`endcelldefine" { FL_FWD; PARSEP->inCellDefine(false); FL_BRK; } + "`endprotect" { FL_FWD; FL_BRK; } + "`expand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`inline" { FL_FWD; FL_BRK; } + "`line"{ws}+[^\n\r]*{crnl} { FL_FWD; PARSEP->ppline(yytext); FL_BRK; } + "`noaccelerate" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`noexpand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`noremove_gatenames" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`noremove_netnames" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`nosuppress_faults" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`nounconnected_drive" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`portcoerce" { FL_FWD; FL_BRK; } + "`pragma"{ws}+[^\n\r]* { FL_FWD; FL_BRK; } // Verilog 2005 + "`protect" { FL_FWD; FL_BRK; } + "`remove_gatenames" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`remove_netnames" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`resetall" { FL_FWD; PARSEP->fileline()->warnOn(V3ErrorCode::I_DEF_NETTYPE_WIRE, true); + FL_BRK; } // Rest handled by preproc + "`suppress_faults" { FL_FWD; FL_BRK; } // Verilog-XL compatibility + "`timescale"{ws}+[^\n\r]* { FL_FWD; FL_BRK; } // Verilog spec - not supported /* See also setLanguage below */ - "`begin_keywords"[ \t]*\"1364-1995\" { yy_push_state(V95); PARSEP->pushBeginKeywords(YY_START); } - "`begin_keywords"[ \t]*\"1364-2001\" { yy_push_state(V01); PARSEP->pushBeginKeywords(YY_START); } - "`begin_keywords"[ \t]*\"1364-2001-noconfig\" { yy_push_state(V01); PARSEP->pushBeginKeywords(YY_START); } - "`begin_keywords"[ \t]*\"1364-2005\" { yy_push_state(V05); PARSEP->pushBeginKeywords(YY_START); } - "`begin_keywords"[ \t]*\"VAMS[-0-9.]*\" { yy_push_state(VA5); PARSEP->pushBeginKeywords(YY_START); } - "`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); PARSEP->pushBeginKeywords(YY_START); } - "`begin_keywords"[ \t]*\"1800-2009\" { yy_push_state(S09); PARSEP->pushBeginKeywords(YY_START); } - "`begin_keywords"[ \t]*\"1800-2012\" { yy_push_state(S12); PARSEP->pushBeginKeywords(YY_START); } - "`begin_keywords"[ \t]*\"1800-2017\" { yy_push_state(S17); PARSEP->pushBeginKeywords(YY_START); } - "`begin_keywords"[ \t]*\"1800[+]VAMS\" { yy_push_state(SAX); PARSEP->pushBeginKeywords(YY_START); } /*Latest SV*/ - "`end_keywords" { yy_pop_state(); if (!PARSEP->popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); } + "`begin_keywords"[ \t]*\"1364-1995\" { FL_FWD; yy_push_state(V95); PARSEP->pushBeginKeywords(YY_START); FL_BRK; } + "`begin_keywords"[ \t]*\"1364-2001\" { FL_FWD; yy_push_state(V01); PARSEP->pushBeginKeywords(YY_START); FL_BRK; } + "`begin_keywords"[ \t]*\"1364-2001-noconfig\" { FL_FWD; yy_push_state(V01); PARSEP->pushBeginKeywords(YY_START); FL_BRK; } + "`begin_keywords"[ \t]*\"1364-2005\" { FL_FWD; yy_push_state(V05); PARSEP->pushBeginKeywords(YY_START); FL_BRK; } + "`begin_keywords"[ \t]*\"VAMS[-0-9.]*\" { FL_FWD; yy_push_state(VA5); PARSEP->pushBeginKeywords(YY_START); FL_BRK; } + "`begin_keywords"[ \t]*\"1800-2005\" { FL_FWD; yy_push_state(S05); PARSEP->pushBeginKeywords(YY_START); FL_BRK; } + "`begin_keywords"[ \t]*\"1800-2009\" { FL_FWD; yy_push_state(S09); PARSEP->pushBeginKeywords(YY_START); FL_BRK; } + "`begin_keywords"[ \t]*\"1800-2012\" { FL_FWD; yy_push_state(S12); PARSEP->pushBeginKeywords(YY_START); FL_BRK; } + "`begin_keywords"[ \t]*\"1800-2017\" { FL_FWD; yy_push_state(S17); PARSEP->pushBeginKeywords(YY_START); FL_BRK; } + "`begin_keywords"[ \t]*\"1800[+]VAMS\" { FL_FWD; yy_push_state(SAX); PARSEP->pushBeginKeywords(YY_START); FL_BRK; } /*Latest SV*/ + "`end_keywords" { FL_FWD; yy_pop_state(); + if (!PARSEP->popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); + FL_BRK; } /* Verilator */ - "`systemc_ctor" { BEGIN SYSCCTOR; } - "`systemc_dtor" { BEGIN SYSCDTOR; } - "`systemc_header" { BEGIN SYSCHDR; } - "`systemc_imp_header" { BEGIN SYSCIMPH; } - "`systemc_implementation" { BEGIN SYSCIMP; } - "`systemc_interface" { BEGIN SYSCINT; } - "`verilator_config" { BEGIN VLT; } - "`verilog" { BEGIN PARSEP->lastVerilogState(); } + "`systemc_ctor" { FL_FWD; BEGIN SYSCCTOR; FL_BRK; } + "`systemc_dtor" { FL_FWD; BEGIN SYSCDTOR; FL_BRK; } + "`systemc_header" { FL_FWD; BEGIN SYSCHDR; FL_BRK; } + "`systemc_imp_header" { FL_FWD; BEGIN SYSCIMPH; FL_BRK; } + "`systemc_implementation" { FL_FWD; BEGIN SYSCIMP; FL_BRK; } + "`systemc_interface" { FL_FWD; BEGIN SYSCINT; FL_BRK; } + "`verilator_config" { FL_FWD; BEGIN VLT; FL_BRK; } + "`verilog" { FL_FWD; BEGIN PARSEP->lastVerilogState(); FL_BRK; } /* If add to this list also add to V3LanguageWords.h */ } -[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; NEXTLINE(); yylval.strp = PARSEP->newString(yytext); return yaSCHDR; } -[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; NEXTLINE(); yylval.strp = PARSEP->newString(yytext); return yaSCINT; } -[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; NEXTLINE(); yylval.strp = PARSEP->newString(yytext); return yaSCIMP; } -[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; NEXTLINE(); yylval.strp = PARSEP->newString(yytext); return yaSCIMPH; } -[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; NEXTLINE(); yylval.strp = PARSEP->newString(yytext); return yaSCCTOR; } -[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; NEXTLINE(); yylval.strp = PARSEP->newString(yytext); return yaSCDTOR; } -[ \t]*[^` \t\n\r][^\n\r]*{crnl} { NEXTLINE(); } +[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCHDR; } +[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCINT; } +[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCIMP; } +[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCIMPH; } +[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCCTOR; } +[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL; yylval.strp = PARSEP->newString(yytext); return yaSCDTOR; } +[ \t]*[^` \t\n\r][^\n\r]*{crnl} { FL_FWD; FL_BRK; } /* Pick up text-type data */ { {wsnr}* { yymore(); } - {crnl} { NEXTLINE(); yymore(); } + {crnl} { yymore(); } } /************************************************************************/ /* Default rules - leave last */ { - "`"[a-zA-Z_0-9]+ { FL; PARSEP->errorPreprocDirective(yytext); } - "//"[^\n]* { } /* throw away single line comments */ + "`"[a-zA-Z_0-9]+ { FL_FWD; PARSEP->errorPreprocDirective(yytext); FL_BRK; } + "//"[^\n]* { FL_FWD; FL_BRK; } /* throw away single line comments */ . { FL; return yytext[0]; } /* return single char ops. */ } /* Catch all - absolutely last */ -<*>.|\n { yyerrorf("Missing verilog.l rule: Default rule invoked in state %d: %s", YY_START, yytext); } +<*>.|\n { FL_FWD; yyerrorf("Missing verilog.l rule: Default rule invoked in state %d: %s", YY_START, yytext); FL_BRK; } %% int V3ParseImp::stateVerilogRecent() { return STATE_VERILOG_RECENT; } @@ -1059,8 +1064,8 @@ int V3ParseImp::lexToBison() { m_curBisonVal = yylval; //yylval.scp = NULL; // Symbol table not yet needed - no packages - if (debugFlex()>=6 || debugBison()>=6) { - cout<<" {"<filenameLetters()<lineno() + if (debugFlex()>=6 || debugBison()>=6) { // --debugi-flex and --debugi-bison + cout<<" {"<filenameLetters()<asciiLineCol() <<"} lexToBison TOKEN="< 0, # Force printing @_); my $leftmsg = $::Have_Forker ? $self->{left_cnt} : "NO-FORKER"; - if (!$self->{quiet} || !$self->{left_cnt} || $params{force} + if (!$self->{quiet} || $params{force} + || ($self->{left_cnt} < 5) || time() > ($self->{_next_summary_time} || 0)) { $self->{_next_summary_time} = time() + 15; print STDERR ("==SUMMARY: ".$self->sprint_summary."\n") diff --git a/test_regress/t/t_array_backw_index_bad.out b/test_regress/t/t_array_backw_index_bad.out index eddc7f808..adecd0e5f 100644 --- a/test_regress/t/t_array_backw_index_bad.out +++ b/test_regress/t/t_array_backw_index_bad.out @@ -1,6 +1,16 @@ %Error: t/t_array_backw_index_bad.v:13: Slice selection '[1:3]' has backward indexing versus data type's '[3:0]' + array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; + ^ %Error: t/t_array_backw_index_bad.v:14: Slice selection '[3:1]' has backward indexing versus data type's '[0:3]' + larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; + ^ %Error: t/t_array_backw_index_bad.v:16: Slice selection index '[4:3]' outside data type's '[3:0]' + array_assign[4:3] = '{32'd4, 32'd3}; + ^ %Error: t/t_array_backw_index_bad.v:17: Slice selection index '[1:-1]' outside data type's '[3:0]' + array_assign[1:-1] = '{32'd4, 32'd3}; + ^ %Error: t/t_array_backw_index_bad.v:17: Assignment pattern missed initializing elements: -1 + array_assign[1:-1] = '{32'd4, 32'd3}; + ^~ %Error: Exiting due to diff --git a/test_regress/t/t_array_list_bad.out b/test_regress/t/t_array_list_bad.out index 3c40e735d..62529c0a3 100644 --- a/test_regress/t/t_array_list_bad.out +++ b/test_regress/t/t_array_list_bad.out @@ -1,4 +1,8 @@ %Error: t/t_array_list_bad.v:37: Assignment pattern missed initializing elements: MEMBERDTYPE 't3' + test_out <= '{'0, '0}; + ^~ %Warning-WIDTH: t/t_array_list_bad.v:37: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits. + test_out <= '{'0, '0}; + ^~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_array_pattern_bad.out b/test_regress/t/t_array_pattern_bad.out index 02ac9e880..46f37b4f1 100644 --- a/test_regress/t/t_array_pattern_bad.out +++ b/test_regress/t/t_array_pattern_bad.out @@ -1,2 +1,4 @@ %Error: t/t_array_pattern_bad.v:23: Assignment pattern key 'valids' not found as member + valids: '1}; + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_dup_bad.out b/test_regress/t/t_assert_dup_bad.out index 6faa66cca..366bdec58 100644 --- a/test_regress/t/t_assert_dup_bad.out +++ b/test_regress/t/t_assert_dup_bad.out @@ -1,3 +1,7 @@ %Error: t/t_assert_dup_bad.v:16: Duplicate declaration of block: 'covlabel' + covlabel: + ^~~~~~~~ t/t_assert_dup_bad.v:14: ... Location of original declaration + covlabel: + ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_bitsel_const_bad.out b/test_regress/t/t_bitsel_const_bad.out index 4a088c918..fbaedf383 100644 --- a/test_regress/t/t_bitsel_const_bad.out +++ b/test_regress/t/t_bitsel_const_bad.out @@ -1,2 +1,4 @@ %Error: t/t_bitsel_const_bad.v:20: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic + assign a = b[0]; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_bitsel_wire_array_bad.out b/test_regress/t/t_bitsel_wire_array_bad.out index db50a1e84..a67643ac5 100644 --- a/test_regress/t/t_bitsel_wire_array_bad.out +++ b/test_regress/t/t_bitsel_wire_array_bad.out @@ -1,2 +1,4 @@ %Error: t/t_bitsel_wire_array_bad.v:20: Illegal assignment of constant to unpacked array + assign b = a[0]; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_case_default_bad.out b/test_regress/t/t_case_default_bad.out index a802929e6..50f7838f4 100644 --- a/test_regress/t/t_case_default_bad.out +++ b/test_regress/t/t_case_default_bad.out @@ -1,2 +1,4 @@ %Error: t/t_case_default_bad.v:15: Multiple default statements in case statement. + default: $stop; + ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_case_genx_bad.out b/test_regress/t/t_case_genx_bad.out index 0676c543b..8b8338666 100644 --- a/test_regress/t/t_case_genx_bad.out +++ b/test_regress/t/t_case_genx_bad.out @@ -1,2 +1,4 @@ %Error: t/t_case_genx_bad.v:13: Use of x/? constant in generate case statement, (no such thing as 'generate casez') + 32'b1xxx: initial begin end + ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_case_x_bad.out b/test_regress/t/t_case_x_bad.out index 8f2dcb4a1..29c09348a 100644 --- a/test_regress/t/t_case_x_bad.out +++ b/test_regress/t/t_case_x_bad.out @@ -1,4 +1,8 @@ %Warning-CASEX: t/t_case_x_bad.v:13: Suggest casez (with ?'s) in place of casex (with X's) + casex (value) + ^~~~~ ... Use "/* verilator lint_off CASEX */" and lint_on around source to disable this message. %Warning-CASEWITHX: t/t_case_x_bad.v:18: Use of x/? constant in case statement, (perhaps intended casex/casez) + 4'b1xxx: $stop; + ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_case_zx_bad.out b/test_regress/t/t_case_zx_bad.out index 70fca0f81..81af2999e 100644 --- a/test_regress/t/t_case_zx_bad.out +++ b/test_regress/t/t_case_zx_bad.out @@ -1,3 +1,5 @@ %Warning-CASEWITHX: t/t_case_zx_bad.v:15: Use of x constant in casez statement, (perhaps intended ?/z in constant) + 4'b1xxx: $stop; + ^~~~~~~ ... Use "/* verilator lint_off CASEWITHX */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_cdc_async_bad.out b/test_regress/t/t_cdc_async_bad.out index bc32e79d0..68ee9cdf6 100644 --- a/test_regress/t/t_cdc_async_bad.out +++ b/test_regress/t/t_cdc_async_bad.out @@ -1,6 +1,12 @@ %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:27: Logic in path that feeds async reset, via signal: 't.rst2_bad_n' + wire rst2_bad_n = rst0_n | rst1_n; + ^ ... Use "/* verilator lint_off CDCRSTLOGIC */" and lint_on around source to disable this message. %Warning-CDCRSTLOGIC: See details in obj_vlt/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:52: Logic in path that feeds async reset, via signal: 't.rst6a_bad_n' + wire rst6a_bad_n = rst6_bad_n ^ $c1("0"); + ^ %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:53: Logic in path that feeds async reset, via signal: 't.rst6b_bad_n' + wire rst6b_bad_n = rst6_bad_n ^ $c1("1"); + ^ %Error: Exiting due to diff --git a/test_regress/t/t_clk_scope_bad.out b/test_regress/t/t_clk_scope_bad.out index 4aedb4884..48f29caac 100644 --- a/test_regress/t/t_clk_scope_bad.out +++ b/test_regress/t/t_clk_scope_bad.out @@ -1,3 +1,5 @@ %Warning-CLKDATA: t/t_clk_scope_bad.v:35: Clock used as data (on rhs of assignment) in sequential block 'clk' + q <= d; + ^ ... Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_concat_large_bad.out b/test_regress/t/t_concat_large_bad.out index eb84bb43b..2a55d527d 100644 --- a/test_regress/t/t_concat_large_bad.out +++ b/test_regress/t/t_concat_large_bad.out @@ -1,3 +1,5 @@ %Warning-WIDTHCONCAT: t/t_concat_large_bad.v:8: More than a 8k bit replication is probably wrong: 32768 + wire [32767:0] a = {32768{1'b1}}; + ^ ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_const_bad.out b/test_regress/t/t_const_bad.out index e1d3ea4bd..cb866504f 100644 --- a/test_regress/t/t_const_bad.out +++ b/test_regress/t/t_const_bad.out @@ -1,5 +1,11 @@ %Warning-WIDTH: t/t_const_bad.v:12: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; + ^~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_const_bad.v:13: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz + if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; + ^~~ %Warning-WIDTH: t/t_const_bad.v:14: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz + if (68'h?_????????_???????? !== 'd?) $stop; + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_const_dec_mixed_bad.out b/test_regress/t/t_const_dec_mixed_bad.out index 512f9f447..e7f12a4f9 100644 --- a/test_regress/t/t_const_dec_mixed_bad.out +++ b/test_regress/t/t_const_dec_mixed_bad.out @@ -1,2 +1,4 @@ %Error: t/t_const_dec_mixed_bad.v:8: Mixing X/Z/? with digits not legal in decimal constant: x_1 + parameter [200:0] MIXED = 32'dx_1; + ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_const_overflow_bad.out b/test_regress/t/t_const_overflow_bad.out index 56909e483..81de441e9 100644 --- a/test_regress/t/t_const_overflow_bad.out +++ b/test_regress/t/t_const_overflow_bad.out @@ -1,6 +1,16 @@ %Error: t/t_const_overflow_bad.v:8: Too many digits for 94 bit number: 94'd123456789012345678901234567890 + parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; + ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: t/t_const_overflow_bad.v:10: Too many digits for 8 bit number: 8'habc + parameter [200:0] SMALLH = 8'habc; + ^~~~~~ %Error: t/t_const_overflow_bad.v:11: Too many digits for 6 bit number: 6'o1234 + parameter [200:0] SMALLO = 6'o1234; + ^~~~~~~ %Error: t/t_const_overflow_bad.v:12: Too many digits for 3 bit number: 3'b1111 + parameter [200:0] SMALLB = 3'b1111; + ^~~~~~~ %Error: t/t_const_overflow_bad.v:18: Too many digits for 129 bit number: 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d + parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; + ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_delay_stmtdly_bad.out b/test_regress/t/t_delay_stmtdly_bad.out index 1136df927..12cd1077f 100644 --- a/test_regress/t/t_delay_stmtdly_bad.out +++ b/test_regress/t/t_delay_stmtdly_bad.out @@ -1,6 +1,14 @@ %Warning-ASSIGNDLY: t/t_delay.v:19: Unsupported: Ignoring delay on this assignment/primitive. + assign #(1.2000000000000000) dly1 = dly0 + 32'h1; + ^ ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message. %Warning-ASSIGNDLY: t/t_delay.v:24: Unsupported: Ignoring delay on this assignment/primitive. + dly0 <= #0 32'h11; + ^ %Warning-ASSIGNDLY: t/t_delay.v:27: Unsupported: Ignoring delay on this assignment/primitive. + dly0 <= #0.12 dly0 + 32'h12; + ^ %Warning-STMTDLY: t/t_delay.v:33: Unsupported: Ignoring delay on this delayed statement. + #100 $finish; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_display_bad.out b/test_regress/t/t_display_bad.out index cb354b9cf..61ed03584 100644 --- a/test_regress/t/t_display_bad.out +++ b/test_regress/t/t_display_bad.out @@ -1,3 +1,7 @@ %Error: t/t_display_bad.v:10: Missing arguments for $display-like format + $display("%x"); + ^~~~~~~~ %Error: t/t_display_bad.v:12: Unknown $display-like format code: '%q' + $display("%q"); + ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_display_esc_bad.out b/test_regress/t/t_display_esc_bad.out index 4609a8695..504024a19 100644 --- a/test_regress/t/t_display_esc_bad.out +++ b/test_regress/t/t_display_esc_bad.out @@ -1,2 +1,4 @@ %Error: t/t_display_esc_bad.v:8: Unknown escape sequence: \x + $display("\x\y\z"); + ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_2exp_bad.out b/test_regress/t/t_dpi_2exp_bad.out index 9293f4265..31732bd6b 100644 --- a/test_regress/t/t_dpi_2exp_bad.out +++ b/test_regress/t/t_dpi_2exp_bad.out @@ -1,2 +1,4 @@ %Error: t/t_dpi_2exp_bad.v:11: Function was already DPI Exported, duplicate not allowed: 'dpix_twice' + export "DPI-C" dpix_t_int_renamed = task dpix_twice; + ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_dup_bad.out b/test_regress/t/t_dpi_dup_bad.out index be0cba70e..9b951038f 100644 --- a/test_regress/t/t_dpi_dup_bad.out +++ b/test_regress/t/t_dpi_dup_bad.out @@ -1,4 +1,8 @@ %Error: t/t_dpi_dup_bad.v:12: Duplicate declaration of DPI function with different formal arguments: 't.oth_f_int2' + import "DPI-C" pure dpii_fa_bit = function int oth_f_int2(input int i, input int bad); + ^~~~~~~~~~ : ... New prototype: pure int dpii_fa_bit (int, int) t/t_dpi_dup_bad.v:11: ... Original prototype: int dpii_fa_bit (int) + import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); + ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_exp_bad.out b/test_regress/t/t_dpi_exp_bad.out index 7cd143b4f..f98e051e9 100644 --- a/test_regress/t/t_dpi_exp_bad.out +++ b/test_regress/t/t_dpi_exp_bad.out @@ -1,2 +1,4 @@ %Error: t/t_dpi_exp_bad.v:11: DPI functions cannot return > 32 bits or four-state; use a two-state type or task instead: 'dpix_f_bit48__Vfuncrtn' + function bit [47:0] dpix_f_bit48(bit [47:0] i); dpix_f_bit48 = ~i; endfunction + ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_logic_bad.out b/test_regress/t/t_dpi_logic_bad.out index 1000d5a50..bb5c4444a 100644 --- a/test_regress/t/t_dpi_logic_bad.out +++ b/test_regress/t/t_dpi_logic_bad.out @@ -1,2 +1,4 @@ %Error: t/t_dpi_logic_bad.v:11: DPI function may not return type BASICDTYPE 'logic' (IEEE 2017 35.5.5) + import "DPI-C" dpii_fa_bit = function logic [2:0] oth_f_int1(input time i); + ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_name_bad.out b/test_regress/t/t_dpi_name_bad.out index 3237533b0..ebbef4650 100644 --- a/test_regress/t/t_dpi_name_bad.out +++ b/test_regress/t/t_dpi_name_bad.out @@ -1,2 +1,4 @@ %Error: t/t_dpi_name_bad.v:11: DPI function has illegal characters in C identifier name: 'badly.named' + import "DPI-C" function int \badly.named (int i); + ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_openreg_bad.out b/test_regress/t/t_dpi_openreg_bad.out index e8aed3c4d..c9d178542 100644 --- a/test_regress/t/t_dpi_openreg_bad.out +++ b/test_regress/t/t_dpi_openreg_bad.out @@ -1,3 +1,7 @@ %Error: t/t_dpi_openreg_bad.v:13: Unsized/open arrays ('[]') are only supported in DPI imports + reg a []; + ^ %Error: t/t_dpi_openreg_bad.v:14: Unsized/open arrays ('[]') are only supported in DPI imports + input b []; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_enum_bad_hide.out b/test_regress/t/t_enum_bad_hide.out index 60ad9f046..e9ab63481 100644 --- a/test_regress/t/t_enum_bad_hide.out +++ b/test_regress/t/t_enum_bad_hide.out @@ -1,4 +1,8 @@ %Warning-VARHIDDEN: t/t_enum_bad_hide.v:10: Declaration of enum value hides declaration in upper scope: HIDE_VALUE + typedef enum { HIDE_VALUE = 0 } hide_enum_t; + ^~~~~~~~~~ t/t_enum_bad_hide.v:6: ... Location of original declaration + typedef enum { HIDE_VALUE = 0 } hide_enum_t; + ^~~~~~~~~~ ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_enum_overlap_bad.out b/test_regress/t/t_enum_overlap_bad.out index 38f4253c3..6ce534611 100644 --- a/test_regress/t/t_enum_overlap_bad.out +++ b/test_regress/t/t_enum_overlap_bad.out @@ -1,3 +1,7 @@ %Error: t/t_enum_overlap_bad.v:11: Overlapping enumeration value: 'e1b' + e1b=1 + ^~~ t/t_enum_overlap_bad.v:9: ... Location of original declaration + e1, + ^~ %Error: Exiting due to diff --git a/test_regress/t/t_flag_errorlimit_bad.out b/test_regress/t/t_flag_errorlimit_bad.out index 27f101167..e25846d3d 100644 --- a/test_regress/t/t_flag_errorlimit_bad.out +++ b/test_regress/t/t_flag_errorlimit_bad.out @@ -1,5 +1,13 @@ %Error: t/t_flag_errorlimit_bad.v:9: Duplicate declaration of signal: 'u1' + int u1; + ^~ t/t_flag_errorlimit_bad.v:8: ... Location of original declaration + int u1; + ^~ %Error: t/t_flag_errorlimit_bad.v:10: Duplicate declaration of signal: 'u1' + int u1; + ^~ t/t_flag_errorlimit_bad.v:8: ... Location of original declaration + int u1; + ^~ %Error: Exiting due to diff --git a/test_regress/t/t_flag_topmodule_bad.out b/test_regress/t/t_flag_topmodule_bad.out index cc83a3175..c4aed56b2 100644 --- a/test_regress/t/t_flag_topmodule_bad.out +++ b/test_regress/t/t_flag_topmodule_bad.out @@ -2,6 +2,12 @@ : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'a' +module a; + ^ : ... Top module 'a2' +module a2; + ^~ : ... Top module 'b' +module b; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_flag_werror_bad1.out b/test_regress/t/t_flag_werror_bad1.out index 9d33320ec..2043d6699 100644 --- a/test_regress/t/t_flag_werror_bad1.out +++ b/test_regress/t/t_flag_werror_bad1.out @@ -1,3 +1,5 @@ %Warning-WIDTH: t/t_flag_werror.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. + wire [3:0] foo = 6'h2e; + ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_flag_werror_bad2.out b/test_regress/t/t_flag_werror_bad2.out index 431bbc2a2..a927218ae 100644 --- a/test_regress/t/t_flag_werror_bad2.out +++ b/test_regress/t/t_flag_werror_bad2.out @@ -1,2 +1,4 @@ %Error-WIDTH: t/t_flag_werror.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. + wire [3:0] foo = 6'h2e; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_flag_wfatal.out b/test_regress/t/t_flag_wfatal.out index e5c676d92..15d9f3d35 100644 --- a/test_regress/t/t_flag_wfatal.out +++ b/test_regress/t/t_flag_wfatal.out @@ -1,2 +1,4 @@ %Warning-WIDTH: t/t_flag_wfatal.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. + wire [3:0] foo = 6'h2e; + ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_for_comma_bad.out b/test_regress/t/t_for_comma_bad.out index b3cb3e089..8549edd19 100644 --- a/test_regress/t/t_for_comma_bad.out +++ b/test_regress/t/t_for_comma_bad.out @@ -1,10 +1,28 @@ %Error: t/t_for_comma_bad.v:13: Unsupported: for loop step after the first comma + for (; ; a=a+1, b=b+1) ; + ^ %Error: t/t_for_comma_bad.v:16: Unsupported: for loop step after the first comma + for (; a<1; a=a+1, b=b+1) ; + ^ %Error: t/t_for_comma_bad.v:19: Unsupported: for loop step after the first comma + for (a=0; a<1; a=a+1, b=b+1) ; + ^ %Error: t/t_for_comma_bad.v:22: Unsupported: for loop step after the first comma + for (integer a=0; a<1; a=a+1, b=b+1) ; + ^ %Error: t/t_for_comma_bad.v:25: Unsupported: for loop step after the first comma + for (var integer a=0; a<1; a=a+1, b=b+1) ; + ^ %Error: t/t_for_comma_bad.v:26: Unsupported: for loop initialization after the first comma + for (integer a=0, integer b=0; a<1; ) ; + ^ %Error: t/t_for_comma_bad.v:27: Unsupported: for loop initialization after the first comma + for (integer a=0, integer b=0; a<1; a=a+1) ; + ^ %Error: t/t_for_comma_bad.v:28: Unsupported: for loop initialization after the first comma + for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ; + ^ %Error: t/t_for_comma_bad.v:28: Unsupported: for loop step after the first comma + for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_func_bad.out b/test_regress/t/t_func_bad.out index a0a15d909..5f812421a 100644 --- a/test_regress/t/t_func_bad.out +++ b/test_regress/t/t_func_bad.out @@ -1,8 +1,22 @@ %Error: t/t_func_bad.v:8: Missing argument on non-defaulted argument 'from2' in function call to FUNC 'add' + if (add(3'd1) != 0) $stop; + ^~~ %Error: t/t_func_bad.v:9: Too many arguments in function call to FUNC 'add' + if (add(3'd1, 3'd2, 3'd3) != 0) $stop; + ^~~~ %Error: t/t_func_bad.v:10: Missing argument on non-defaulted argument 'y' in function call to TASK 'x' + x; + ^ %Error: t/t_func_bad.v:10: Unsupported: Function output argument 'y' requires 1 bits, but connection's CONST '?32?h0' generates 32 bits. + x; + ^ %Error: t/t_func_bad.v:13: No such argument 'no_such' in function call to FUNC 'f' + f(.j(1), .no_such(2)); + ^~~~~~~ %Error: t/t_func_bad.v:14: Duplicate argument 'dup' in function call to FUNC 'f' + f(.dup(1), .dup(3)); + ^~~ %Error: t/t_func_bad.v:15: Too many arguments in function call to FUNC 'f' + f(1,2,3); + ^ %Error: Exiting due to diff --git a/test_regress/t/t_func_bad2.out b/test_regress/t/t_func_bad2.out index 09f7e5f84..3a9d6fc18 100644 --- a/test_regress/t/t_func_bad2.out +++ b/test_regress/t/t_func_bad2.out @@ -1,2 +1,4 @@ %Error: t/t_func_bad2.v:7: Unsupported: Recursive function or task call + function recurse; + ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_bad_width.out b/test_regress/t/t_func_bad_width.out index e3778931c..edd56d524 100644 --- a/test_regress/t/t_func_bad_width.out +++ b/test_regress/t/t_func_bad_width.out @@ -1,4 +1,8 @@ %Warning-WIDTH: t/t_func_bad_width.v:12: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits. + out = MUX (in); + ^~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_func_bad_width.v:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits. + out = MUX (in); + ^ %Error: Exiting due to diff --git a/test_regress/t/t_func_const2_bad.out b/test_regress/t/t_func_const2_bad.out index bee54cccd..891de13ea 100644 --- a/test_regress/t/t_func_const2_bad.out +++ b/test_regress/t/t_func_const2_bad.out @@ -9,4 +9,6 @@ a = ?32?sh7 b = ?32?sh8 c = ?32?sh9 + localparam P24 = f_add2(7, 8, 9); + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_const_bad.out b/test_regress/t/t_func_const_bad.out index f43dcb844..d80c86eec 100644 --- a/test_regress/t/t_func_const_bad.out +++ b/test_regress/t/t_func_const_bad.out @@ -1,21 +1,31 @@ %Error: t/t_func_const_bad.v:11: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_output' t/t_func_const_bad.v:12: ... Location of non-constant VAR 'o': Language violation: Outputs/refs not allowed in constant functions + localparam B1 = f_bad_output(1,2); + ^~~~~~~~~~~~ %Error: t/t_func_const_bad.v:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_dotted' t/t_func_const_bad.v:22: ... Location of non-constant VARXREF 'EIGHT': Language violation: Dotted hierarchical references not allowed in constant functions t/t_func_const_bad.v:20: ... Called from f_bad_dotted() with parameters: a = ?32?sh2 + localparam B2 = f_bad_dotted(2); + ^~~~~~~~~~~~ %Error: t/t_func_const_bad.v:27: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_nonparam' t/t_func_const_bad.v:29: ... Location of non-constant VARREF 'modvar': Language violation: reference to non-function-local variable t/t_func_const_bad.v:27: ... Called from f_bad_nonparam() with parameters: a = ?32?sh3 + localparam B3 = f_bad_nonparam(3); + ^~~~~~~~~~~~~~ %Error: t/t_func_const_bad.v:35: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_infinite' t/t_func_const_bad.v:37: ... Location of non-constant WHILE: Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above 1024 t/t_func_const_bad.v:35: ... Called from f_bad_infinite() with parameters: a = ?32?sh3 + localparam B4 = f_bad_infinite(3); + ^~~~~~~~~~~~~~ %Error: t/t_func_const_bad.v:43: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_stop' t/t_func_const_bad.v:45: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_bad.v:43: ... Called from f_bad_stop() with parameters: a = ?32?sh3 + localparam BSTOP = f_bad_stop(3); + ^~~~~~~~~~ -Info: Printing in loop: 0 -Info: Printing in loop: 1 -Info: Printing in loop: 2 @@ -25,4 +35,6 @@ t/t_func_const_bad.v:54: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_func_const_bad.v:49: ... Called from f_bad_fatal() with parameters: a = ?32?sh3 + localparam BFATAL = f_bad_fatal(3); + ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_const_packed_array_bad.out b/test_regress/t/t_func_const_packed_array_bad.out index fd5aed943..51ab866ca 100644 --- a/test_regress/t/t_func_const_packed_array_bad.out +++ b/test_regress/t/t_func_const_packed_array_bad.out @@ -8,4 +8,6 @@ a = ?32?sh7 b = ?32?sh8 c = ?32?sh9 + localparam P24 = f_add2(7, 8, 9); + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_const_packed_struct_bad.out b/test_regress/t/t_func_const_packed_struct_bad.out index 5900de393..8d37641cd 100644 --- a/test_regress/t/t_func_const_packed_struct_bad.out +++ b/test_regress/t/t_func_const_packed_struct_bad.out @@ -8,4 +8,6 @@ a = ?32?sh7 b = ?32?sh8 c = ?32?sh9 + localparam P24 = f_add2(7, 8, 9); + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_const_packed_struct_bad2.out b/test_regress/t/t_func_const_packed_struct_bad2.out index fb9a93bc6..6f4e304a6 100644 --- a/test_regress/t/t_func_const_packed_struct_bad2.out +++ b/test_regress/t/t_func_const_packed_struct_bad2.out @@ -8,4 +8,6 @@ a = ?32?sh7 b = ?32?sh8 c = ?32?sh9 + localparam P24 = f_add2(7, 8, 9); + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_const_struct_bad.out b/test_regress/t/t_func_const_struct_bad.out index 49c3f22cb..53ea3f3d2 100644 --- a/test_regress/t/t_func_const_struct_bad.out +++ b/test_regress/t/t_func_const_struct_bad.out @@ -8,4 +8,6 @@ a = ?32?sh7 b = ?32?sh8 c = ?32?sh9 + localparam P24 = f_add2(7, 8, 9); + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_task_bad.out b/test_regress/t/t_func_task_bad.out index 11b2260f5..a50e09a63 100644 --- a/test_regress/t/t_func_task_bad.out +++ b/test_regress/t/t_func_task_bad.out @@ -1,2 +1,4 @@ %Error: t/t_func_task_bad.v:9: Illegal call of a task as a function: 'task_as_func' + if (task_as_func(1'b0)) $stop; + ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_tie_bad.out b/test_regress/t/t_func_tie_bad.out index 03dbf6985..0a7779940 100644 --- a/test_regress/t/t_func_tie_bad.out +++ b/test_regress/t/t_func_tie_bad.out @@ -1,2 +1,4 @@ %Error: t/t_func_tie_bad.v:10: Function/task output connected to constant instead of variable: 'b' + func(0, 1'b1); + ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_void_bad.out b/test_regress/t/t_func_void_bad.out index bb0542681..ba40b25a7 100644 --- a/test_regress/t/t_func_void_bad.out +++ b/test_regress/t/t_func_void_bad.out @@ -1,3 +1,5 @@ %Warning-IGNOREDRETURN: t/t_func_void_bad.v:25: Ignoring return value of non-void function (IEEE 2017 13.4.1) + f1(20); + ^~ ... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_func_wide_out_bad.out b/test_regress/t/t_func_wide_out_bad.out index 6e1458475..df11f3d81 100644 --- a/test_regress/t/t_func_wide_out_bad.out +++ b/test_regress/t/t_func_wide_out_bad.out @@ -1,2 +1,4 @@ %Error: t/t_func_wide_out_bad.v:16: Unsupported: Function output argument 'data' requires 4352 bits, but connection's VARREF 'msg' generates 4350 bits. + func(msg); + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_gen_cond_bitrange_bad.out b/test_regress/t/t_gen_cond_bitrange_bad.out index e39b20ccf..88188064f 100644 --- a/test_regress/t/t_gen_cond_bitrange_bad.out +++ b/test_regress/t/t_gen_cond_bitrange_bad.out @@ -1,6 +1,14 @@ %Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:58: Selection index out of range: 2:2 outside 1:0 + if ((g < (SIZE + 1)) && MASK[g]) begin + ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:70: Selection index out of range: 2:2 outside 1:0 + if ((g < SIZE) && MASK[g + 1]) begin + ^ %Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:83: Selection index out of range: 2:2 outside 1:0 + if ((g < (SIZE)) & MASK[g]) begin + ^ %Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:96: Selection index out of range: 2:2 outside 1:0 + if (!((g >= SIZE) | ~MASK[g])) begin + ^ %Error: Exiting due to diff --git a/test_regress/t/t_gen_missing_bad.out b/test_regress/t/t_gen_missing_bad.out index b12e952a6..f1a07c9f8 100644 --- a/test_regress/t/t_gen_missing_bad.out +++ b/test_regress/t/t_gen_missing_bad.out @@ -1,4 +1,6 @@ %Error: t/t_gen_missing.v:42: Cannot find file containing module: 'foo_not_needed' + foo_not_needed i_foo(.x(foo[j]), .y(bar[j])); + ^~~~~~~~~~~~~~ ... Looked in: t/foo_not_needed t/foo_not_needed.v diff --git a/test_regress/t/t_gen_var_bad.out b/test_regress/t/t_gen_var_bad.out index ac12a2912..8233ad286 100644 --- a/test_regress/t/t_gen_var_bad.out +++ b/test_regress/t/t_gen_var_bad.out @@ -1,2 +1,4 @@ %Error: t/t_gen_var_bad.v:9: Non-genvar used in generate for: 'i' + for (i=0; i<3; i=i+1) begin + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_hierarchy_identifier_bad.out b/test_regress/t/t_hierarchy_identifier_bad.out index 0664dbe1a..b3a3a702b 100644 --- a/test_regress/t/t_hierarchy_identifier_bad.out +++ b/test_regress/t/t_hierarchy_identifier_bad.out @@ -1,7 +1,17 @@ %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:33: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish' + end : if_cnt_finish_bad + ^~~~~~~~~~~~~~~~~ ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message. %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:39: End label 'generate_for_bad' does not match begin label 'generate_for' + end : generate_for_bad + ^~~~~~~~~~~~~~~~ %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:46: End label 'generate_if_if_bad' does not match begin label 'generate_if_if' + end : generate_if_if_bad + ^~~~~~~~~~~~~~~~~~ %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:50: End label 'generate_if_else_bad' does not match begin label 'generate_if_else' + end : generate_if_else_bad + ^~~~~~~~~~~~~~~~~~~~ %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:53: End label 't_bad' does not match begin label 't' +endmodule : t_bad + ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_initial_dlyass_bad.out b/test_regress/t/t_initial_dlyass_bad.out index c966481ac..ad57dba85 100644 --- a/test_regress/t/t_initial_dlyass_bad.out +++ b/test_regress/t/t_initial_dlyass_bad.out @@ -1,6 +1,10 @@ %Warning-INITIALDLY: t/t_initial_dlyass.v:17: Delayed assignments (<=) in initial or final block : ... Suggest blocking assignments (=) + a <= 22; + ^~ ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message. %Warning-INITIALDLY: t/t_initial_dlyass.v:18: Delayed assignments (<=) in initial or final block : ... Suggest blocking assignments (=) + b <= 33; + ^~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_array_bad.out b/test_regress/t/t_inst_array_bad.out index 95b87a386..116321aa5 100644 --- a/test_regress/t/t_inst_array_bad.out +++ b/test_regress/t/t_inst_array_bad.out @@ -1,2 +1,4 @@ %Error: t/t_inst_array_bad.v:18: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. + sub sub [7:0] (allbits, onebitbad, bitout); + ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_misarray_bad.out b/test_regress/t/t_inst_misarray_bad.out index 7d8e9de28..0932a0795 100644 --- a/test_regress/t/t_inst_misarray_bad.out +++ b/test_regress/t/t_inst_misarray_bad.out @@ -1,2 +1,4 @@ %Error: t/t_inst_misarray_bad.v:16: VARREF 't.foo' is not an unpacked array, but is in an unpacked array context + .foo(foo)); + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_missing_bad.out b/test_regress/t/t_inst_missing_bad.out index 522b1c923..42aa1eade 100644 --- a/test_regress/t/t_inst_missing_bad.out +++ b/test_regress/t/t_inst_missing_bad.out @@ -1,5 +1,11 @@ %Warning-PINNOCONNECT: t/t_inst_missing_bad.v:8: Cell pin is not connected: '__pinNumber2' + sub sub (.ok(ok), , .nc()); + ^ ... Use "/* verilator lint_off PINNOCONNECT */" and lint_on around source to disable this message. %Warning-PINCONNECTEMPTY: t/t_inst_missing_bad.v:8: Cell pin connected by name with empty reference: 'nc' + sub sub (.ok(ok), , .nc()); + ^~ %Warning-PINMISSING: t/t_inst_missing_bad.v:8: Cell has missing pin: 'missing' + sub sub (.ok(ok), , .nc()); + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_overwide_bad.out b/test_regress/t/t_inst_overwide_bad.out index babd4b74b..d1c074319 100644 --- a/test_regress/t/t_inst_overwide_bad.out +++ b/test_regress/t/t_inst_overwide_bad.out @@ -1,6 +1,14 @@ %Warning-WIDTH: t/t_inst_overwide.v:22: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits. + .outy_w92 (outc_w30), + ^~~~~~~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_inst_overwide.v:23: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits. + .outz_w22 (outd_w73), + ^~~~~~~~ %Warning-WIDTH: t/t_inst_overwide.v:26: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits. + .inw_w31 (ina_w1), + ^~~~~~~ %Warning-WIDTH: t/t_inst_overwide.v:27: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits. + .inx_w11 (inb_w61) + ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_recurse2_bad.out b/test_regress/t/t_inst_recurse2_bad.out index 1f755b51b..4773641b7 100644 --- a/test_regress/t/t_inst_recurse2_bad.out +++ b/test_regress/t/t_inst_recurse2_bad.out @@ -1,2 +1,4 @@ %Error: t/t_inst_recurse2_bad.v:17: Unsupported: Identically recursive module (module instantiates itself, without changing parameters): 'looped' +module looped ( ); + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_recurse_bad.out b/test_regress/t/t_inst_recurse_bad.out index 65d8814f2..9d4c8093f 100644 --- a/test_regress/t/t_inst_recurse_bad.out +++ b/test_regress/t/t_inst_recurse_bad.out @@ -1,3 +1,5 @@ %Error: t/t_inst_recurse_bad.v:17: Unsupported: Recursive multiple modules (module instantiates something leading back to itself): 'looped' ... note: self-recursion (module instantiating itself directly) is supported. +module looped ( ); + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_array_bad.out b/test_regress/t/t_interface_array_bad.out index 80d58634f..f2d9702cb 100644 --- a/test_regress/t/t_interface_array_bad.out +++ b/test_regress/t/t_interface_array_bad.out @@ -1,3 +1,7 @@ %Error: t/t_interface_array_bad.v:22: Expecting expression to be constant, but variable isn't const: 'bar' + assign foos[bar].a = 1'b1; + ^~~ %Error: t/t_interface_array_bad.v:22: Could not expand constant selection inside dotted reference: 'bar' + assign foos[bar].a = 1'b1; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_interface_array_nocolon_bad.out b/test_regress/t/t_interface_array_nocolon_bad.out index 316a9663b..39a0896c1 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.out +++ b/test_regress/t/t_interface_array_nocolon_bad.out @@ -1,6 +1,14 @@ %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:25: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2 + foo_intf foos [N] (.x(X)); + ^ ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3 + foo_intf fool [1:3] (.x(X)); + ^ %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:29: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2 + foo_subm subs [N] (.x(X)); + ^ %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3 + foo_subm subl [1:3] (.x(X)); + ^ %Error: Exiting due to diff --git a/test_regress/t/t_interface_mismodport_bad.out b/test_regress/t/t_interface_mismodport_bad.out index 053af0854..d829e3a74 100644 --- a/test_regress/t/t_interface_mismodport_bad.out +++ b/test_regress/t/t_interface_mismodport_bad.out @@ -1,3 +1,5 @@ %Error: t/t_interface_mismodport_bad.v:35: Can't find definition of 'bad' in dotted signal: 'isub.bad' + isub.bad = i_value; + ^~~ ... Known scopes under 'bad': %Error: Exiting due to diff --git a/test_regress/t/t_interface_missing_bad.out b/test_regress/t/t_interface_missing_bad.out index 0aab2aa9e..28c69c288 100644 --- a/test_regress/t/t_interface_missing_bad.out +++ b/test_regress/t/t_interface_missing_bad.out @@ -1,4 +1,10 @@ %Error: t/t_interface_missing_bad.v:13: Cannot find file containing interface: 'foo_intf' + foo_intf foo + ^~~~~~~~ %Error: t/t_interface_missing_bad.v:19: Cannot find file containing interface: 'foo_intf' + foo_intf the_foo (); + ^~~~~~~~ %Error: t/t_interface_missing_bad.v:24: Found definition of 'the_foo' as a CELL but expected a variable + .foo (the_foo) + ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_modport_bad.out b/test_regress/t/t_interface_modport_bad.out index e610d48b8..4491a623a 100644 --- a/test_regress/t/t_interface_modport_bad.out +++ b/test_regress/t/t_interface_modport_bad.out @@ -1,3 +1,5 @@ %Error: t/t_interface_modport_bad.v:22: Modport not found under interface 'ifc': 'oop_modport' : ... Suggested alternative: 'out_modport' + ifc.oop_modport isub, + ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_param_another_bad.out b/test_regress/t/t_interface_param_another_bad.out index 5896e9d9e..037570bfe 100644 --- a/test_regress/t/t_interface_param_another_bad.out +++ b/test_regress/t/t_interface_param_another_bad.out @@ -1,2 +1,4 @@ %Error: t/t_interface_param_another_bad.v:8: Parameter-resolved constants must not use dotted references: 'dummy' + simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple(); + ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_size_bad.out b/test_regress/t/t_interface_size_bad.out index 223198a17..beed09b36 100644 --- a/test_regress/t/t_interface_size_bad.out +++ b/test_regress/t/t_interface_size_bad.out @@ -1,3 +1,7 @@ %Error: t/t_interface_size_bad.v:15: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 4. + baz baz4_inst (.foo(foo4)); + ^~~ %Error: t/t_interface_size_bad.v:16: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 6. + baz baz6_inst (.foo(foo6)); + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_top_bad.out b/test_regress/t/t_interface_top_bad.out index f017ac0b4..adaecff1c 100644 --- a/test_regress/t/t_interface_top_bad.out +++ b/test_regress/t/t_interface_top_bad.out @@ -1,3 +1,7 @@ %Error: t/t_interface_top_bad.v:16: Unsupported: Interfaced port on top level module + ifc.counter_mp c_data + ^~~~~~ %Error: t/t_interface_top_bad.v:16: Parent cell's interface is not found: 'ifc' + ifc.counter_mp c_data + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_typo_bad.out b/test_regress/t/t_interface_typo_bad.out index 07ece3ee1..2785a1329 100644 --- a/test_regress/t/t_interface_typo_bad.out +++ b/test_regress/t/t_interface_typo_bad.out @@ -1,4 +1,10 @@ %Error: t/t_interface_typo_bad.v:13: Parent cell's interface is not found: 'foo_intf' + foo_intf foo + ^~~~~~~~ %Error: t/t_interface_typo_bad.v:21: Cannot find file containing interface: 'fo_intf' + fo_intf the_foo; + ^~~~~~~ %Error: t/t_interface_typo_bad.v:26: Found definition of 'the_foo' as a CELL but expected a variable + .foo (the_foo) + ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_wrong_bad.out b/test_regress/t/t_interface_wrong_bad.out index cc0e3ec0f..f8f82a065 100644 --- a/test_regress/t/t_interface_wrong_bad.out +++ b/test_regress/t/t_interface_wrong_bad.out @@ -1,2 +1,4 @@ %Error: t/t_interface_wrong_bad.v:31: Port 'foo_port' expects 'foo_intf' interface but pin connects 'bar_intf' interface + .foo_port (bar) + ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_always_comb_bad.out b/test_regress/t/t_lint_always_comb_bad.out index 9e3ae8c17..dd1d07ea8 100644 --- a/test_regress/t/t_lint_always_comb_bad.out +++ b/test_regress/t/t_lint_always_comb_bad.out @@ -1,6 +1,14 @@ %Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'temp1' + temp1 = 'h0; + ^~~~~ %Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:30: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'temp1' + temp1 = (temp1_d1r - 'h1); + ^~~~~ %Warning-ALWCOMBORDER: t/t_lint_always_comb_bad.v:31: Always_comb variable driven after use: 'mid' + mid = (temp1_d1r == 'h0); + ^~~ ... Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message. %Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:45: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'temp1_d1r' + temp1_d1r <= temp1; + ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_blksync_bad.out b/test_regress/t/t_lint_blksync_bad.out index d101b971f..2ddeeabfe 100644 --- a/test_regress/t/t_lint_blksync_bad.out +++ b/test_regress/t/t_lint_blksync_bad.out @@ -1,8 +1,12 @@ %Warning-BLKSEQ: t/t_lint_blksync_bad.v:23: Blocking assignments (=) in sequential (flop or latch) block : ... Suggest delayed assignments (<=) + sync_blk = 1'b1; + ^ ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message. %Warning-COMBDLY: t/t_lint_blksync_bad.v:30: Delayed assignments (<=) in non-clocked (non flop or latch) block : ... Suggest blocking assignments (=) + combo_nblk <= 1'b1; + ^~ *** See the manual before disabling this, else you may end up with different sim results. %Error: Exiting due to diff --git a/test_regress/t/t_lint_bsspace_bad.out b/test_regress/t/t_lint_bsspace_bad.out index 76753bce0..2c79ad74b 100644 --- a/test_regress/t/t_lint_bsspace_bad.out +++ b/test_regress/t/t_lint_bsspace_bad.out @@ -1,4 +1,8 @@ %Warning-BSSPACE: t/t_lint_bsspace_bad.v:9: Backslash followed by whitespace, perhaps the whitespace is accidental? +`define FOO blak \ + ^ ... Use "/* verilator lint_off BSSPACE */" and lint_on around source to disable this message. %Error: t/t_lint_bsspace_bad.v:10: syntax error, unexpected IDENTIFIER + blak + ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_colonplus_bad.out b/test_regress/t/t_lint_colonplus_bad.out index 33cffa284..ff1ae2b56 100644 --- a/test_regress/t/t_lint_colonplus_bad.out +++ b/test_regress/t/t_lint_colonplus_bad.out @@ -1,3 +1,5 @@ %Warning-COLONPLUS: t/t_lint_colonplus_bad.v:12: Perhaps instead of ':+' the intent was '+:'? + output [2:1] z = r[2 :+ 1]; + ^~ ... Use "/* verilator lint_off COLONPLUS */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_comb_bad.out b/test_regress/t/t_lint_comb_bad.out index 9dd830c36..34d8bc8de 100644 --- a/test_regress/t/t_lint_comb_bad.out +++ b/test_regress/t/t_lint_comb_bad.out @@ -1,3 +1,5 @@ %Error: t/t_lint_comb_bad.v:13: syntax error, unexpected '@' + always_comb @(*) begin + ^ %Error: Cannot continue %Error: Command Failed diff --git a/test_regress/t/t_lint_declfilename_bad.out b/test_regress/t/t_lint_declfilename_bad.out index 784eea788..32edff12e 100644 --- a/test_regress/t/t_lint_declfilename_bad.out +++ b/test_regress/t/t_lint_declfilename_bad.out @@ -1,3 +1,5 @@ %Warning-DECLFILENAME: t/t_lint_declfilename.v:6: Filename 't_lint_declfilename' does not match MODULE name: 't' +module t; + ^ ... Use "/* verilator lint_off DECLFILENAME */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_defparam_bad.out b/test_regress/t/t_lint_defparam_bad.out index 88fa7c7f0..3b5105e5e 100644 --- a/test_regress/t/t_lint_defparam_bad.out +++ b/test_regress/t/t_lint_defparam_bad.out @@ -1,3 +1,5 @@ %Warning-DEFPARAM: t/t_lint_defparam.v:9: Suggest replace defparam assignment with Verilog 2001 #(.P(...etc...)) + defparam sub.P = 2; + ^ ... Use "/* verilator lint_off DEFPARAM */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_ifdepth_bad.out b/test_regress/t/t_lint_ifdepth_bad.out index 7f79da650..60ff8ee10 100644 --- a/test_regress/t/t_lint_ifdepth_bad.out +++ b/test_regress/t/t_lint_ifdepth_bad.out @@ -1,3 +1,5 @@ %Warning-IFDEPTH: t/t_lint_ifdepth_bad.v:21: Deep 'if' statement; suggest unique/priority to avoid slow logic + else if (value==11) begin end + ^~ ... Use "/* verilator lint_off IFDEPTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_bad.out b/test_regress/t/t_lint_implicit_bad.out index 6ef21f6a2..ac6800b5f 100644 --- a/test_regress/t/t_lint_implicit_bad.out +++ b/test_regress/t/t_lint_implicit_bad.out @@ -1,8 +1,16 @@ %Warning-IMPLICIT: t/t_lint_implicit.v:10: Signal definition not found, creating implicitly: 'b' + assign b = 1'b1; + ^ ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Warning-IMPLICIT: t/t_lint_implicit.v:12: Signal definition not found, creating implicitly: 'nt0' + or OR0 (nt0, a, b); + ^~~ %Warning-IMPLICIT: t/t_lint_implicit.v:15: Signal definition not found, creating implicitly: 'dummy1' : ... Suggested alternative: 'dummy_ip' + assign {dummy1, dummy2} = dummy_ip; + ^~~~~~ %Warning-IMPLICIT: t/t_lint_implicit.v:15: Signal definition not found, creating implicitly: 'dummy2' : ... Suggested alternative: 'dummy1' + assign {dummy1, dummy2} = dummy_ip; + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_def_bad.out b/test_regress/t/t_lint_implicit_def_bad.out index 508be69e4..9d3577db9 100644 --- a/test_regress/t/t_lint_implicit_def_bad.out +++ b/test_regress/t/t_lint_implicit_def_bad.out @@ -1,4 +1,8 @@ %Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:10: Signal definition not found, creating implicitly: 'imp_warn' + assign imp_warn = 1'b1; + ^~~~~~~~ ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: t/t_lint_implicit_def_bad.v:15: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err' + assign imp_err = 1'b1; + ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_import_name_bad.out b/test_regress/t/t_lint_import_name_bad.out index 0d8629847..c790c7bb0 100644 --- a/test_regress/t/t_lint_import_name_bad.out +++ b/test_regress/t/t_lint_import_name_bad.out @@ -1,2 +1,4 @@ %Error: t/t_lint_import_name_bad.v:10: Import object not found: 'defs::sigs' +import defs::sigs; + ^~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_importstar_bad.out b/test_regress/t/t_lint_importstar_bad.out index 08f821b0a..c75019b5b 100644 --- a/test_regress/t/t_lint_importstar_bad.out +++ b/test_regress/t/t_lint_importstar_bad.out @@ -1,3 +1,5 @@ %Warning-IMPORTSTAR: t/t_lint_importstar_bad.v:10: Import::* in $unit scope may pollute global namespace +import defs::*; + ^~ ... Use "/* verilator lint_off IMPORTSTAR */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_in_inc_bad.out b/test_regress/t/t_lint_in_inc_bad.out index cd6904200..ce1771397 100644 --- a/test_regress/t/t_lint_in_inc_bad.out +++ b/test_regress/t/t_lint_in_inc_bad.out @@ -1,4 +1,6 @@ %Error: t/t_lint_in_inc_bad_2.vh:8: syntax error, unexpected if, expecting '(' - t/t_lint_in_inc_bad_1.vh:6: ... note: In file included from t_lint_in_inc_bad_1.vh - t/t_lint_in_inc_bad.v:6: ... note: In file included from t_lint_in_inc_bad.v + if if if; + ^~ + t/t_lint_in_inc_bad_1.vh:7: ... note: In file included from t_lint_in_inc_bad_1.vh + t/t_lint_in_inc_bad.v:7: ... note: In file included from t_lint_in_inc_bad.v %Error: Exiting due to diff --git a/test_regress/t/t_lint_incabspath_bad.out b/test_regress/t/t_lint_incabspath_bad.out index fd0c2c6d8..b2af30de9 100644 --- a/test_regress/t/t_lint_incabspath_bad.out +++ b/test_regress/t/t_lint_incabspath_bad.out @@ -1,3 +1,5 @@ %Warning-INCABSPATH: t/t_lint_incabspath.v:6: Suggest `include with absolute path be made relative, and use +include: /dev/null +`include "/dev/null" + ^~~~~~~~~~~ ... Use "/* verilator lint_off INCABSPATH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_infinite.out b/test_regress/t/t_lint_infinite.out index bfab775ea..227e33c07 100644 --- a/test_regress/t/t_lint_infinite.out +++ b/test_regress/t/t_lint_infinite.out @@ -1,4 +1,8 @@ %Warning-INFINITELOOP: t/t_lint_infinite.v:9: Infinite loop (condition always true) + forever begin end + ^~~~~~~ ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message. %Warning-INFINITELOOP: t/t_lint_infinite.v:11: Infinite loop (condition always true) + for (reg [31:0] i=0; i>=0; i=i+1) begin end + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_input_eq_bad.out b/test_regress/t/t_lint_input_eq_bad.out index 6c19d9840..c45d62534 100644 --- a/test_regress/t/t_lint_input_eq_bad.out +++ b/test_regress/t/t_lint_input_eq_bad.out @@ -1,2 +1,4 @@ %Error: t/t_lint_input_eq_bad.v:9: Unsupported: Default value on module input: 'i2' + input wire i2 = i + ^~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_bad.out b/test_regress/t/t_lint_latch_bad.out index 7c5cf3d40..9334c03d7 100644 --- a/test_regress/t/t_lint_latch_bad.out +++ b/test_regress/t/t_lint_latch_bad.out @@ -1,5 +1,7 @@ %Warning-COMBDLY: t/t_lint_latch_bad.v:24: Delayed assignments (<=) in non-clocked (non flop or latch) block : ... Suggest blocking assignments (=) + bc <= a; + ^~ ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. *** See the manual before disabling this, else you may end up with different sim results. diff --git a/test_regress/t/t_lint_literal_bad.out b/test_regress/t/t_lint_literal_bad.out index c437ad24b..9ed1d4c3e 100644 --- a/test_regress/t/t_lint_literal_bad.out +++ b/test_regress/t/t_lint_literal_bad.out @@ -1,3 +1,5 @@ %Warning-WIDTH: t/t_lint_literal_bad.v:9: Value too large for 8 bit number: 256 + localparam the_localparam = 8'd256; + ^~~~~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_mod_paren_bad.out b/test_regress/t/t_lint_mod_paren_bad.out index d2f556cd9..f7783f03d 100644 --- a/test_regress/t/t_lint_mod_paren_bad.out +++ b/test_regress/t/t_lint_mod_paren_bad.out @@ -1,2 +1,4 @@ %Error: t/t_lint_mod_paren_bad.v:13: syntax error, unexpected '(', expecting ';' + output bar + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_modport_dir_bad.out b/test_regress/t/t_lint_modport_dir_bad.out index 8f76a7a35..f6000fed4 100644 --- a/test_regress/t/t_lint_modport_dir_bad.out +++ b/test_regress/t/t_lint_modport_dir_bad.out @@ -1,2 +1,4 @@ %Error: t/t_lint_modport_dir_bad.v:25: Attempt to drive input-only modport: 'signal' + assign dummy_in.signal = signal_i; + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_multidriven_bad.out b/test_regress/t/t_lint_multidriven_bad.out index 3ffb9d042..4503dc79c 100644 --- a/test_regress/t/t_lint_multidriven_bad.out +++ b/test_regress/t/t_lint_multidriven_bad.out @@ -1,8 +1,16 @@ %Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:20: Signal has multiple driving blocks with different clocking: 't.mem' t/t_lint_multidriven_bad.v:26: ... Location of first driving block + mem[a0] <= d1; + ^~~ t/t_lint_multidriven_bad.v:23: ... Location of other driving block + mem[a0] <= d0; + ^~~ ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. %Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:18: Signal has multiple driving blocks with different clocking: 'out2' t/t_lint_multidriven_bad.v:34: ... Location of first driving block + out2[15:8] <= d0; + ^~~~ t/t_lint_multidriven_bad.v:31: ... Location of other driving block + out2[7:0] <= d0; + ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_once_bad.out b/test_regress/t/t_lint_once_bad.out index 366521f20..910f56dda 100644 --- a/test_regress/t/t_lint_once_bad.out +++ b/test_regress/t/t_lint_once_bad.out @@ -1,4 +1,8 @@ %Warning-UNUSED: t/t_lint_once_bad.v:18: Signal is not driven, nor used: 'unus1' + reg [A:0] unus1; reg [A:0] unus2; + ^~~~~ ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message. %Warning-UNUSED: t/t_lint_once_bad.v:18: Signal is not driven, nor used: 'unus2' + reg [A:0] unus1; reg [A:0] unus2; + ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_pindup_bad.out b/test_regress/t/t_lint_pindup_bad.out index 987229849..3769a5e47 100644 --- a/test_regress/t/t_lint_pindup_bad.out +++ b/test_regress/t/t_lint_pindup_bad.out @@ -1,13 +1,31 @@ %Warning-PINMISSING: t/t_lint_pindup_bad.v:18: Cell has missing pin: 'exists' + sub (.o(o), + ^~~ ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: t/t_lint_pindup_bad.v:20: Duplicate pin connection: 'i' + .i(i2), + ^ t/t_lint_pindup_bad.v:19: ... Location of original pin connection + .i(i), + ^ %Error: t/t_lint_pindup_bad.v:21: Pin not found: 'nexist' : ... Suggested alternative: 'exists' + .nexist(i2) + ^~~~~~ %Error: t/t_lint_pindup_bad.v:15: Parameter pin not found: 'NEXIST' : ... Suggested alternative: 'EXIST' + .NEXIST(1), + ^~~~~~ %Error: t/t_lint_pindup_bad.v:16: Duplicate parameter pin connection: 'P' + .P(2), + ^ t/t_lint_pindup_bad.v:14: ... Location of original parameter pin connection + #(, + ^ %Error: t/t_lint_pindup_bad.v:17: Duplicate parameter pin connection: 'P' + .P(3)) + ^ t/t_lint_pindup_bad.v:14: ... Location of original parameter pin connection + #(, + ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_pkg_colon_bad.out b/test_regress/t/t_lint_pkg_colon_bad.out index 6194138fa..483b9b58b 100644 --- a/test_regress/t/t_lint_pkg_colon_bad.out +++ b/test_regress/t/t_lint_pkg_colon_bad.out @@ -1,4 +1,8 @@ %Error: t/t_lint_pkg_colon_bad.v:6: syntax error, unexpected ::, expecting ')' or ',' +module t (input mispkg::foo_t a); + ^~ : ... Perhaps 'mispkg' is a package which needs to be predeclared? (IEEE 2017 26.3) %Error: t/t_lint_pkg_colon_bad.v:7: syntax error, unexpected ::, expecting ',' or ';' + reg mispkgb::bar_t b; + ^~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_realcvt_bad.out b/test_regress/t/t_lint_realcvt_bad.out index 529830f17..a41da1e6f 100644 --- a/test_regress/t/t_lint_realcvt_bad.out +++ b/test_regress/t/t_lint_realcvt_bad.out @@ -1,3 +1,5 @@ %Warning-REALCVT: t/t_lint_realcvt_bad.v:9: Implicit conversion of real to integer + i = 23.2; + ^~~~ ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_repeat_bad.out b/test_regress/t/t_lint_repeat_bad.out index 728ecb737..8dfc5aa15 100644 --- a/test_regress/t/t_lint_repeat_bad.out +++ b/test_regress/t/t_lint_repeat_bad.out @@ -1,3 +1,5 @@ %Warning-WIDTH: t/t_lint_repeat_bad.v:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits. + wire [0:0] b = a; + ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_restore_bad.out b/test_regress/t/t_lint_restore_bad.out index 4b8d915df..0637ec08f 100644 --- a/test_regress/t/t_lint_restore_bad.out +++ b/test_regress/t/t_lint_restore_bad.out @@ -1,3 +1,5 @@ %Warning-WIDTH: t/t_lint_restore_bad.v:18: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. + initial five = 64'h1; + ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_rsvd_bad.out b/test_regress/t/t_lint_rsvd_bad.out index 3a3eb12c7..8f947efdb 100644 --- a/test_regress/t/t_lint_rsvd_bad.out +++ b/test_regress/t/t_lint_rsvd_bad.out @@ -1,4 +1,10 @@ %Error: t/t_lint_rsvd_bad.v:6: Unsupported: Verilog 2001-config reserved word not implemented: 'config' +config cfgBad; +^~~~~~ %Error: t/t_lint_rsvd_bad.v:6: syntax error, unexpected IDENTIFIER +config cfgBad; + ^~~~~~ %Error: t/t_lint_rsvd_bad.v:7: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig' +endconfig +^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_setout_bad.out b/test_regress/t/t_lint_setout_bad.out index aa43238fb..8cf5e9e1d 100644 --- a/test_regress/t/t_lint_setout_bad.out +++ b/test_regress/t/t_lint_setout_bad.out @@ -1,2 +1,4 @@ %Error-PORTSHORT: t/t_lint_setout_bad.v:16: Output port is connected to a constant pin, electrical short + .cpu_if_timeout(1'b0) + ^~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_setout_bad_noinl.out b/test_regress/t/t_lint_setout_bad_noinl.out index aa43238fb..8cf5e9e1d 100644 --- a/test_regress/t/t_lint_setout_bad_noinl.out +++ b/test_regress/t/t_lint_setout_bad_noinl.out @@ -1,2 +1,4 @@ %Error-PORTSHORT: t/t_lint_setout_bad.v:16: Output port is connected to a constant pin, electrical short + .cpu_if_timeout(1'b0) + ^~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_subout_bad.out b/test_regress/t/t_lint_subout_bad.out index 635de2efc..04e0bee4c 100644 --- a/test_regress/t/t_lint_subout_bad.out +++ b/test_regress/t/t_lint_subout_bad.out @@ -1,4 +1,10 @@ %Error-PORTSHORT: t/t_lint_subout_bad.v:11: Output port is connected to a constant pin, electrical short + sub sub1(.out({32'b0, sig})); + ^~~ %Error-PORTSHORT: t/t_lint_subout_bad.v:12: Output port is connected to a constant pin, electrical short + sub sub2(.out({32'b1, sig})); + ^~~ %Error-PORTSHORT: t/t_lint_subout_bad.v:10: Output port is connected to a constant pin, electrical short + sub sub0(.out(33'b0)); + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_syncasyncnet_bad.out b/test_regress/t/t_lint_syncasyncnet_bad.out index 4bcb609e8..8ca9a32da 100644 --- a/test_regress/t/t_lint_syncasyncnet_bad.out +++ b/test_regress/t/t_lint_syncasyncnet_bad.out @@ -1,5 +1,9 @@ %Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:15: Signal flopped as both synchronous and async: 'rst_both_l' t/t_lint_syncasyncnet_bad.v:90: ... Location of async usage + q2 <= (~rst_both_l) ? 1'b0 : d; + ^~~~~~~~~~ t/t_lint_syncasyncnet_bad.v:58: ... Location of sync usage + q2 <= (rst_both_l) ? d : 1'b0; + ^~~~~~~~~~ ... Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_syncasyncnet_bad.v b/test_regress/t/t_lint_syncasyncnet_bad.v index daba7977e..2335dbcc5 100644 --- a/test_regress/t/t_lint_syncasyncnet_bad.v +++ b/test_regress/t/t_lint_syncasyncnet_bad.v @@ -55,7 +55,7 @@ module sub1 (/*AUTOARG*/ end always @(posedge clk) begin - q2 <= (~rst_both_l) ? 1'b0 : d; + q2 <= (rst_both_l) ? d : 1'b0; if (0 && q1 && q2) ; end diff --git a/test_regress/t/t_lint_unsized_bad.out b/test_regress/t/t_lint_unsized_bad.out index e9ef69463..ce16f29e9 100644 --- a/test_regress/t/t_lint_unsized_bad.out +++ b/test_regress/t/t_lint_unsized_bad.out @@ -1,4 +1,6 @@ %Error: t/t_lint_unsized_bad.v:7: Too many digits for 32 bit number: 'd123456789123456789123456789 ... As that number was unsized ('d...) it is limited to 32 bits (IEEE 2017 5.7.1) ... Suggest adding a size to it. + bit [256:0] num = 'd123456789123456789123456789; + ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_unused_bad.out b/test_regress/t/t_lint_unused_bad.out index bbd0dc99b..2255df3b9 100644 --- a/test_regress/t/t_lint_unused_bad.out +++ b/test_regress/t/t_lint_unused_bad.out @@ -1,8 +1,20 @@ %Warning-UNUSED: t/t_lint_unused_bad.v:16: Bits of signal are not used: 'assunu1'[5:1] + wire [5:0] assunu1 = 0; + ^~~~~~~ ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message. %Warning-UNDRIVEN: t/t_lint_unused_bad.v:20: Bits of signal are not driven: 'udrb2'[14:13,11] + wire [15:10] udrb2; + ^~~~~ %Warning-UNUSED: t/t_lint_unused_bad.v:25: Signal is not driven, nor used: 'unu3' + wire unu3; + ^~~~ %Warning-UNUSED: t/t_lint_unused_bad.v:27: Bits of signal are not driven, nor used: 'mixed'[3] + wire [3:0] mixed; + ^~~~~ %Warning-UNUSED: t/t_lint_unused_bad.v:27: Bits of signal are not used: 'mixed'[2] + wire [3:0] mixed; + ^~~~~ %Warning-UNDRIVEN: t/t_lint_unused_bad.v:27: Bits of signal are not driven: 'mixed'[1] + wire [3:0] mixed; + ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_unused_iface_bad.out b/test_regress/t/t_lint_unused_iface_bad.out index cd38912dd..a981b3daa 100644 --- a/test_regress/t/t_lint_unused_iface_bad.out +++ b/test_regress/t/t_lint_unused_iface_bad.out @@ -1,4 +1,8 @@ %Warning-UNDRIVEN: t/t_lint_unused_iface_bad.v:7: Signal is not driven: 'sig_udrv' + logic sig_udrv; + ^~~~~~~~ ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message. %Warning-UNUSED: t/t_lint_unused_iface_bad.v:8: Signal is not used: 'sig_uusd' + logic sig_uusd; + ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_width_bad.out b/test_regress/t/t_lint_width_bad.out index 778ffb33a..49a92a0d4 100644 --- a/test_regress/t/t_lint_width_bad.out +++ b/test_regress/t/t_lint_width_bad.out @@ -1,8 +1,26 @@ %Warning-WIDTH: t/t_lint_width_bad.v:16: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits. + localparam [3:0] XS = 'hx; + ^~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_lint_width_bad.v:38: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits. + wire [4:0] out = in; + ^ %Warning-WIDTH: t/t_lint_width_bad.v:20: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits. + wire [4:0] d = (1'b1 << 2) + 5'b1; + ^~ %Warning-WIDTH: t/t_lint_width_bad.v:26: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits. + wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); + ^ %Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits. + wire [2:0] cnt = (one + one + one + one); + ^ %Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. + wire [2:0] cnt = (one + one + one + one); + ^ +%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. + wire [2:0] cnt = (one + one + one + one); + ^ +%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. + wire [2:0] cnt = (one + one + one + one); + ^ %Error: Exiting due to diff --git a/test_regress/t/t_math_shift_over_bad.out b/test_regress/t/t_math_shift_over_bad.out index bc87aff04..84450f13b 100644 --- a/test_regress/t/t_math_shift_over_bad.out +++ b/test_regress/t/t_math_shift_over_bad.out @@ -1,2 +1,4 @@ %Error: t/t_math_shift_over_bad.v:18: Value too wide for 32-bits expected in this context 64'h123456789abcdef + assign o = i << 64'h01234567_89abcdef; + ^~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_mem_multi_ref_bad.out b/test_regress/t/t_mem_multi_ref_bad.out index c7fef17f7..b72828aec 100644 --- a/test_regress/t/t_mem_multi_ref_bad.out +++ b/test_regress/t/t_mem_multi_ref_bad.out @@ -1,11 +1,29 @@ %Error: t/t_mem_multi_ref_bad.v:14: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic + dimn[1:0] = 0; + ^ %Error: t/t_mem_multi_ref_bad.v:14: Extracting 2 bits from only 1 bit number + dimn[1:0] = 0; + ^ %Error: t/t_mem_multi_ref_bad.v:15: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic + dim0[1][1] = 0; + ^ %Warning-SELRANGE: t/t_mem_multi_ref_bad.v:15: Selection index out of range: 1:1 outside 0:0 + dim0[1][1] = 0; + ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: t/t_mem_multi_ref_bad.v:16: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic + dim1[1][1][1] = 0; + ^ %Warning-SELRANGE: t/t_mem_multi_ref_bad.v:16: Selection index out of range: 1:1 outside 0:0 + dim1[1][1][1] = 0; + ^ %Error: t/t_mem_multi_ref_bad.v:18: Illegal +: or -: select; type already selected, or bad dimension: type is UNPACKARRAYDTYPE + dim2[0 +: 1][1] = 0; + ^ %Error: t/t_mem_multi_ref_bad.v:22: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic + dim0nv[1][1] = 0; + ^ %Warning-SELRANGE: t/t_mem_multi_ref_bad.v:22: Selection index out of range: 1:1 outside 0:0 + dim0nv[1][1] = 0; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_mem_packed_bad.out b/test_regress/t/t_mem_packed_bad.out index 3a6a8ab72..33d55f0ce 100644 --- a/test_regress/t/t_mem_packed_bad.out +++ b/test_regress/t/t_mem_packed_bad.out @@ -1,2 +1,4 @@ %Error: t/t_mem_packed_bad.v:26: CONST '28'h0' unexpected in assignment to unpacked array + ch04 <= 56'd0; + ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_mem_slice_bad.out b/test_regress/t/t_mem_slice_bad.out index 06a36554f..e3cc34a09 100644 --- a/test_regress/t/t_mem_slice_bad.out +++ b/test_regress/t/t_mem_slice_bad.out @@ -1,5 +1,19 @@ %Error: t/t_mem_slice_bad.v:38: Slice selection index '[2:0]' outside data type's '[1:0]' + assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + ^ %Error: t/t_mem_slice_bad.v:38: Slice selection index '[3:0]' outside data type's '[2:0]' + assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + ^ +%Error: t/t_mem_slice_bad.v:38: Slice selection index '[2:0]' outside data type's '[1:0]' + assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + ^ +%Error: t/t_mem_slice_bad.v:38: Slice selection index '[3:0]' outside data type's '[2:0]' + assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + ^ %Error: t/t_mem_slice_bad.v:38: Slice selection index '[3:0]' outside data type's '[1:0]' + assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + ^ %Error: t/t_mem_slice_bad.v:50: Slice selection index '[8:0]' outside data type's '[7:0]' + active_command4[7:0] <= command_A4[8:0]; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_mem_slice_dtype_bad.out b/test_regress/t/t_mem_slice_dtype_bad.out index ac31ee92a..92c5454e4 100644 --- a/test_regress/t/t_mem_slice_dtype_bad.out +++ b/test_regress/t/t_mem_slice_dtype_bad.out @@ -1,2 +1,4 @@ %Error: t/t_mem_slice_dtype_bad.v:22: ADD unexpected in assignment to unpacked array + completed_cnt[id] <= completed_cnt_dp + 1; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_metacmt_onoff.out b/test_regress/t/t_metacmt_onoff.out index 6cddaf571..e49dc4f6b 100644 --- a/test_regress/t/t_metacmt_onoff.out +++ b/test_regress/t/t_metacmt_onoff.out @@ -1,4 +1,8 @@ %Warning-LITENDIAN: t/t_metacmt_onoff.v:5: Little bit endian vector: MSB < LSB of bit range: 0:1 + reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; + ^ ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. %Warning-LITENDIAN: t/t_metacmt_onoff.v:5: Little bit endian vector: MSB < LSB of bit range: 0:3 + reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_mod_dup_bad.out b/test_regress/t/t_mod_dup_bad.out index 85969d71c..e0a5d6893 100644 --- a/test_regress/t/t_mod_dup_bad.out +++ b/test_regress/t/t_mod_dup_bad.out @@ -1,8 +1,16 @@ %Warning-MODDUP: t/t_mod_dup_bad.v:13: Duplicate declaration of module: 'a' +module a(); + ^ t/t_mod_dup_bad.v:6: ... Location of original declaration +module a(); + ^ ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. %Warning-MULTITOP: t/t_mod_dup_bad.v:16: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. : ... Top module 'test' +module test(); + ^~~~ : ... Top module 'b' +module b(); + ^ %Error: Exiting due to diff --git a/test_regress/t/t_multitop_sig_bad.out b/test_regress/t/t_multitop_sig_bad.out index 67b5e82d3..02a6e508c 100644 --- a/test_regress/t/t_multitop_sig_bad.out +++ b/test_regress/t/t_multitop_sig_bad.out @@ -2,6 +2,12 @@ : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'a' +module a(in, out); + ^ : ... Top module 'b' +module b(in, out); + ^ : ... Top module 'c' +module c(uniq_in, uniq_out); + ^ %Error: Exiting due to diff --git a/test_regress/t/t_order_clkinst_bad.out b/test_regress/t/t_order_clkinst_bad.out index d308a4eff..79330f780 100644 --- a/test_regress/t/t_order_clkinst_bad.out +++ b/test_regress/t/t_order_clkinst_bad.out @@ -1,9 +1,23 @@ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:17: Imperfect scheduling of variable: 't.c1_start' + reg c1_start; initial c1_start = 0; + ^~~~~~~~ ... Use "/* verilator lint_off IMPERFECTSCH */" and lint_on around source to disable this message. %Warning-IMPERFECTSCH: t/t_order_clkinst.v:18: Imperfect scheduling of variable: 't.c1_count' + wire [31:0] c1_count; + ^~~~~~~~ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:22: Imperfect scheduling of variable: 't.s2_count' + wire [31:0] s2_count; + ^~~~~~~~ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:26: Imperfect scheduling of variable: 't.c3_count' + wire [31:0] c3_count; + ^~~~~~~~ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:70: Imperfect scheduling of variable: 't.c1.runner' + reg [31:0] runnerm1, runner; initial runner = 0; + ^~~~~~ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:99: Imperfect scheduling of variable: 't.s2.runner' + reg [31:0] runnerm1, runner; initial runner = 0; + ^~~~~~ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:70: Imperfect scheduling of variable: 't.c3.runner' + reg [31:0] runnerm1, runner; initial runner = 0; + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_package_export_bad.out b/test_regress/t/t_package_export_bad.out index e4b758b99..54980b7c8 100644 --- a/test_regress/t/t_package_export_bad.out +++ b/test_regress/t/t_package_export_bad.out @@ -1,13 +1,25 @@ %Error: t/t_package_export.v:56: Can't find definition of scope/variable: 'PARAM2' : ... Suggested alternative: 'PARAM1' + reg [pkg11::PARAM2 : 0] bus12; + ^~~~~~ %Error: t/t_package_export.v:57: Can't find definition of scope/variable: 'PARAM3' : ... Suggested alternative: 'PARAM1' + reg [pkg11::PARAM3 : 0] bus13; + ^~~~~~ %Error: t/t_package_export.v:60: Can't find definition of scope/variable: 'PARAM2' : ... Suggested alternative: 'PARAM1' + reg [pkg21::PARAM2 : 0] bus22; + ^~~~~~ %Error: t/t_package_export.v:61: Can't find definition of scope/variable: 'PARAM3' : ... Suggested alternative: 'PARAM1' + reg [pkg21::PARAM3 : 0] bus23; + ^~~~~~ %Error: t/t_package_export.v:64: Can't find definition of scope/variable: 'PARAM2' : ... Suggested alternative: 'PARAM1' + reg [pkg31::PARAM2 : 0] bus32; + ^~~~~~ %Error: t/t_package_export.v:65: Can't find definition of scope/variable: 'PARAM3' : ... Suggested alternative: 'PARAM1' + reg [pkg31::PARAM3 : 0] bus33; + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_circ_bad.out b/test_regress/t/t_param_circ_bad.out index ea464ee9a..e9a9edb72 100644 --- a/test_regress/t/t_param_circ_bad.out +++ b/test_regress/t/t_param_circ_bad.out @@ -1,2 +1,4 @@ %Error: t/t_param_circ_bad.v:10: Variable's initial value is circular: 'X' +module sub #(parameter WIDTH=X, parameter X=WIDTH) + ^ %Error: Exiting due to diff --git a/test_regress/t/t_param_concat_bad.out b/test_regress/t/t_param_concat_bad.out index 110baca05..abb8f206c 100644 --- a/test_regress/t/t_param_concat_bad.out +++ b/test_regress/t/t_param_concat_bad.out @@ -1,5 +1,11 @@ %Warning-WIDTHCONCAT: t/t_param_concat.v:18: Unsized numbers/parameters not allowed in concatenations. + if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; + ^~~~~~~ ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Warning-WIDTHCONCAT: t/t_param_concat.v:18: Unsized numbers/parameters not allowed in replications. + if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; + ^ %Warning-WIDTHCONCAT: t/t_param_concat.v:19: Unsized numbers/parameters not allowed in replications. + if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; + ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_default_bad.out b/test_regress/t/t_param_default_bad.out index fedfd02de..4a414573c 100644 --- a/test_regress/t/t_param_default_bad.out +++ b/test_regress/t/t_param_default_bad.out @@ -1,2 +1,4 @@ %Error: t/t_param_default_bad.v:6: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'Foo' +module m #(parameter int Foo); + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_default_presv_bad.out b/test_regress/t/t_param_default_presv_bad.out index 6661a2f71..e7e159d88 100644 --- a/test_regress/t/t_param_default_presv_bad.out +++ b/test_regress/t/t_param_default_presv_bad.out @@ -1,2 +1,4 @@ %Error: t/t_param_default_bad.v:6: Parameter requires default value, or use IEEE 1800-2009 or later. +module m #(parameter int Foo); + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_scope_bad.out b/test_regress/t/t_param_scope_bad.out index 9f397e65e..c42f66b15 100644 --- a/test_regress/t/t_param_scope_bad.out +++ b/test_regress/t/t_param_scope_bad.out @@ -1,3 +1,5 @@ %Warning-CASEOVERLAP: t/t_param_scope_bad.v:27: Case values overlap (example pattern 0x2) + 2'h2: $stop; + ^~~~ ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_param_sel_range_bad.out b/test_regress/t/t_param_sel_range_bad.out index 8eb678a4f..1b53f9c5a 100644 --- a/test_regress/t/t_param_sel_range_bad.out +++ b/test_regress/t/t_param_sel_range_bad.out @@ -1,3 +1,5 @@ %Warning-SELRANGE: t/t_param_sel_range.v:40: Selection index out of range: 7:7 outside 4:0 + r_rst[i] <= r_rst[i-1]; + ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_param_up_bad.out b/test_regress/t/t_param_up_bad.out index 68bb84f68..3ce943df0 100644 --- a/test_regress/t/t_param_up_bad.out +++ b/test_regress/t/t_param_up_bad.out @@ -1,2 +1,4 @@ %Error: t/t_param_up_bad.v:15: Can't find definition of scope/variable: 'bar' + assign a_bad = bar.foo; + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_past_bad.out b/test_regress/t/t_past_bad.out index 9811283d3..6cf4e60bd 100644 --- a/test_regress/t/t_past_bad.out +++ b/test_regress/t/t_past_bad.out @@ -1,4 +1,8 @@ %Error: t/t_past_bad.v:11: $past tick value must be constant (IEEE 2017 16.9.3) + if ($past(d, 0)) $stop; + ^~~~~ %Warning-TICKCOUNT: t/t_past_bad.v:12: $past tick value of 10000 may have a large performance cost + if ($past(d, 10000)) $stop; + ^~~~~ ... Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_past_unsup_bad.out b/test_regress/t/t_past_unsup_bad.out index 2d6b38bed..aaac41288 100644 --- a/test_regress/t/t_past_unsup_bad.out +++ b/test_regress/t/t_past_unsup_bad.out @@ -1,2 +1,4 @@ %Error: t/t_past_unsup_bad.v:12: Unsupported: $past expr2 and clock arguments + if ($past(d, 0, 0, 0)) $stop; + ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_pp_misdef_bad.out b/test_regress/t/t_pp_misdef_bad.out index 20111898f..6cb34ad26 100644 --- a/test_regress/t/t_pp_misdef_bad.out +++ b/test_regress/t/t_pp_misdef_bad.out @@ -1,5 +1,9 @@ %Error: t/t_pp_misdef_bad.v:10: Define or directive not defined: '`NDEFINED' : ... Suggested alternative: '`DEFINED' + `NDEFINED + ^~~~~~~~~ %Error: t/t_pp_misdef_bad.v:13: Define or directive not defined: '`imescale' : ... Suggested alternative: '`timescale' + `imescale + ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_pp_underline_bad.out b/test_regress/t/t_pp_underline_bad.out index 3aaf91f5a..4c83f2957 100644 --- a/test_regress/t/t_pp_underline_bad.out +++ b/test_regress/t/t_pp_underline_bad.out @@ -1,3 +1,7 @@ %Error: t/t_pp_underline_bad.v:7: Extra underscore in meta-comment; use /*verilator {...}*/ not /*verilator_{...}*/ + // verilator_no_inline_module + ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: t/t_pp_underline_bad.v:7: Unknown verilator comment: /*verilator _no_inline_module*/ + /*verilator _no_inline_module*/ + ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_preproc_inc_notfound_bad.out b/test_regress/t/t_preproc_inc_notfound_bad.out index f7ab1fbaa..41a4268eb 100644 --- a/test_regress/t/t_preproc_inc_notfound_bad.out +++ b/test_regress/t/t_preproc_inc_notfound_bad.out @@ -1,4 +1,6 @@ %Error: t/t_preproc_inc_notfound_bad.v:6: Cannot find include file: this_file_is_not_found.vh +`include "this_file_is_not_found.vh" + ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ... Looked in: t/this_file_is_not_found.vh t/this_file_is_not_found.vh.v diff --git a/test_regress/t/t_select_bad_msb.out b/test_regress/t/t_select_bad_msb.out index f2d205eea..27cbe2882 100644 --- a/test_regress/t/t_select_bad_msb.out +++ b/test_regress/t/t_select_bad_msb.out @@ -1,4 +1,8 @@ %Warning-LITENDIAN: t/t_select_bad_msb.v:11: Little bit endian vector: MSB < LSB of bit range: 0:22 + reg [0:22] backwd; + ^ ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. %Error: t/t_select_bad_msb.v:15: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1] + sel2 = mi[1:4]; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range.out b/test_regress/t/t_select_bad_range.out index b63fa0466..e43d34d38 100644 --- a/test_regress/t/t_select_bad_range.out +++ b/test_regress/t/t_select_bad_range.out @@ -1,4 +1,8 @@ %Warning-SELRANGE: t/t_select_bad_range.v:15: Selection index out of range: 44:44 outside 43:0 + sel = mi[44]; + ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_range.v:16: Selection index out of range: 44:41 outside 43:0 + sel2 = mi[44:41]; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range2.out b/test_regress/t/t_select_bad_range2.out index 74866f9d8..a48a04d3b 100644 --- a/test_regress/t/t_select_bad_range2.out +++ b/test_regress/t/t_select_bad_range2.out @@ -1,3 +1,5 @@ %Warning-SELRANGE: t/t_select_bad_range2.v:50: Selection index out of range: 3:2 outside 1:0 + assign out32 = in[3:2]; + ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range3.out b/test_regress/t/t_select_bad_range3.out index 3b8d4b761..1193eeedc 100644 --- a/test_regress/t/t_select_bad_range3.out +++ b/test_regress/t/t_select_bad_range3.out @@ -1,3 +1,5 @@ %Warning-SELRANGE: t/t_select_bad_range3.v:18: Selection index out of range: 13 outside 12:10 + assign outwires[12] = inwires[13]; + ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_tri.out b/test_regress/t/t_select_bad_tri.out index c33b55fae..9082dd1b0 100644 --- a/test_regress/t/t_select_bad_tri.out +++ b/test_regress/t/t_select_bad_tri.out @@ -1,2 +1,4 @@ %Error: t/t_select_bad_tri.v:10: Selection index is constantly unknown or tristated: lsb=7'bxxxxxxx width=32'sh47 + if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_struct_init_bad.out b/test_regress/t/t_struct_init_bad.out index 71597196b..1dc84beb4 100644 --- a/test_regress/t/t_struct_init_bad.out +++ b/test_regress/t/t_struct_init_bad.out @@ -1,2 +1,4 @@ %Error: t/t_struct_init.v:53: Assignment pattern contains duplicate entry: b1 + const b4_t b4_const_c = '{b1: 1'b1, b1: 1'b0, b0:1'b0, b2: 1'b1, b3: 1'b1}; + ^~ %Error: Exiting due to diff --git a/test_regress/t/t_struct_notfound_bad.out b/test_regress/t/t_struct_notfound_bad.out index b823fe88d..c3b8fa292 100644 --- a/test_regress/t/t_struct_notfound_bad.out +++ b/test_regress/t/t_struct_notfound_bad.out @@ -1,2 +1,4 @@ %Error: t/t_struct_notfound_bad.v:12: Member 'nfmember' not found in structure + s.nfmember = 0; + ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_struct_unpacked_bad.out b/test_regress/t/t_struct_unpacked_bad.out index d1c0d5ee2..6f32a647a 100644 --- a/test_regress/t/t_struct_unpacked_bad.out +++ b/test_regress/t/t_struct_unpacked_bad.out @@ -1,3 +1,5 @@ %Warning-UNPACKED: t/t_struct_unpacked_bad.v:8: Unsupported: Unpacked struct/union + typedef struct { + ^~~~~~ ... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_tri_pull2_bad.out b/test_regress/t/t_tri_pull2_bad.out index b6c50583e..cc2f941b4 100644 --- a/test_regress/t/t_tri_pull2_bad.out +++ b/test_regress/t/t_tri_pull2_bad.out @@ -1,3 +1,7 @@ %Error: t/t_tri_pull2_bad.v:9: Unsupported: Conflicting pull directions. + pullup p1(A); + ^~ t/t_tri_pull2_bad.v:19: ... Location of conflicting pull. + pulldown p2(A); + ^~ %Error: Exiting due to diff --git a/test_regress/t/t_tri_pull_bad.out b/test_regress/t/t_tri_pull_bad.out index 463005bf7..fec86f7b4 100644 --- a/test_regress/t/t_tri_pull_bad.out +++ b/test_regress/t/t_tri_pull_bad.out @@ -1,3 +1,7 @@ %Error: t/t_tri_pull_bad.v:10: Unsupported: Conflicting pull directions. + pulldown p2(A); + ^~ t/t_tri_pull_bad.v:9: ... Location of conflicting pull. + pullup p1(A); + ^~ %Error: Exiting due to diff --git a/test_regress/t/t_tri_pullvec_bad.out b/test_regress/t/t_tri_pullvec_bad.out index 4894d17af..d4bb1cb4b 100644 --- a/test_regress/t/t_tri_pullvec_bad.out +++ b/test_regress/t/t_tri_pullvec_bad.out @@ -1,5 +1,13 @@ %Error: t/t_tri_pullvec_bad.v:10: Unsupported: Conflicting pull directions. + pulldown p1 (w[1]); + ^~ t/t_tri_pullvec_bad.v:9: ... Location of conflicting pull. + pullup p0 (w[0]); + ^~ %Error: t/t_tri_pullvec_bad.v:11: Unsupported: Conflicting pull directions. + pulldown p2 (w[2]); + ^~ t/t_tri_pullvec_bad.v:9: ... Location of conflicting pull. + pullup p0 (w[0]); + ^~ %Error: Exiting due to diff --git a/test_regress/t/t_typedef_circ_bad.out b/test_regress/t/t_typedef_circ_bad.out index 09126fefc..33179862f 100644 --- a/test_regress/t/t_typedef_circ_bad.out +++ b/test_regress/t/t_typedef_circ_bad.out @@ -1,2 +1,4 @@ %Error: t/t_typedef_circ_bad.v:5: Typedef's type is circular: a_t +typedef a_t b_t; + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_udp_bad.out b/test_regress/t/t_udp_bad.out index 91d6ab5b9..2ab137bee 100644 --- a/test_regress/t/t_udp_bad.out +++ b/test_regress/t/t_udp_bad.out @@ -1,2 +1,4 @@ %Error: t/t_udp.v:103: Unsupported: Verilog 1995 UDP Tables. Use --bbox-unsup to ignore tables. + table + ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_unopt_combo_bad.out b/test_regress/t/t_unopt_combo_bad.out index 21e687c45..67138f1b5 100644 --- a/test_regress/t/t_unopt_combo_bad.out +++ b/test_regress/t/t_unopt_combo_bad.out @@ -1,4 +1,6 @@ %Warning-UNOPTFLAT: t/t_unopt_combo.v:23: Signal unoptimizable: Feedback to clock or circular logic: 't.c' + wire [31:0] c; + ^ ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_unopt_combo.v:23: Example path: t.c t/t_unopt_combo.v:80: Example path: ALWAYS diff --git a/test_regress/t/t_unopt_converge_unopt_bad.out b/test_regress/t/t_unopt_converge_unopt_bad.out index 0603ce585..9e70e6ee2 100644 --- a/test_regress/t/t_unopt_converge_unopt_bad.out +++ b/test_regress/t/t_unopt_converge_unopt_bad.out @@ -1,4 +1,6 @@ %Warning-UNOPT: t/t_unopt_converge.v:18: Signal unoptimizable: Feedback to public clock or circular logic: 'x' + output x; + ^ ... Use "/* verilator lint_off UNOPT */" and lint_on around source to disable this message. t/t_unopt_converge.v:18: Example path: x t/t_unopt_converge.v:21: Example path: ALWAYS diff --git a/test_regress/t/t_unoptflat_simple_2_bad.out b/test_regress/t/t_unoptflat_simple_2_bad.out index 37d4f84f4..d13984a08 100644 --- a/test_regress/t/t_unoptflat_simple_2_bad.out +++ b/test_regress/t/t_unoptflat_simple_2_bad.out @@ -1,4 +1,6 @@ %Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: Signal unoptimizable: Feedback to clock or circular logic: 't.x' + wire [2:0] x; + ^ ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_unoptflat_simple_2.v:14: Example path: t.x t/t_unoptflat_simple_2.v:16: Example path: ASSIGNW diff --git a/test_regress/t/t_var_bad_hide.out b/test_regress/t/t_var_bad_hide.out index 34e398ba2..865f47ecc 100644 --- a/test_regress/t/t_var_bad_hide.out +++ b/test_regress/t/t_var_bad_hide.out @@ -1,6 +1,14 @@ %Warning-VARHIDDEN: t/t_var_bad_hide.v:15: Declaration of signal hides declaration in upper scope: 'top' + output top; + ^~~ t/t_var_bad_hide.v:12: ... Location of original declaration + integer top; + ^~~ ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Warning-VARHIDDEN: t/t_var_bad_hide.v:21: Declaration of signal hides declaration in upper scope: 'top' + integer top; + ^~~ t/t_var_bad_hide.v:12: ... Location of original declaration + integer top; + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_hide2.out b/test_regress/t/t_var_bad_hide2.out index 796958f41..d92a97678 100644 --- a/test_regress/t/t_var_bad_hide2.out +++ b/test_regress/t/t_var_bad_hide2.out @@ -1,4 +1,8 @@ %Warning-VARHIDDEN: t/t_var_bad_hide2.v:13: Declaration of signal hides declaration in upper scope: 't' + integer t; + ^ t/t_var_bad_hide2.v:6: ... Location of original declaration +module t; + ^ ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_sameas.out b/test_regress/t/t_var_bad_sameas.out index 2759c3470..05cc448ab 100644 --- a/test_regress/t/t_var_bad_sameas.out +++ b/test_regress/t/t_var_bad_sameas.out @@ -1,11 +1,31 @@ %Error: t/t_var_bad_sameas.v:9: Unsupported in C: Cell has the same name as variable: 'varfirst' + sub varfirst (); + ^~~~~~~~ t/t_var_bad_sameas.v:8: ... Location of original declaration + integer varfirst; + ^~~~~~~~ %Error: t/t_var_bad_sameas.v:10: Unsupported in C: Task has the same name as cell: 'varfirst' + task varfirst; begin end endtask + ^~~~~~~~ t/t_var_bad_sameas.v:9: ... Location of original declaration + sub varfirst (); + ^~~~~~~~ %Error: t/t_var_bad_sameas.v:13: Unsupported in C: Variable has same name as cell: 'cellfirst' + integer cellfirst; + ^~~~~~~~~ %Error: t/t_var_bad_sameas.v:14: Unsupported in C: Task has the same name as cell: 'cellfirst' + task cellfirst; begin end endtask + ^~~~~~~~~ t/t_var_bad_sameas.v:12: ... Location of original declaration + sub cellfirst (); + ^~~~~~~~~ %Error: t/t_var_bad_sameas.v:17: Unsupported in C: Variable has same name as task: 'taskfirst' + integer taskfirst; + ^~~~~~~~~ %Error: t/t_var_bad_sameas.v:18: Unsupported in C: Cell has the same name as task: 'taskfirst' + sub taskfirst (); + ^~~~~~~~~ t/t_var_bad_sameas.v:16: ... Location of original declaration + task taskfirst; begin end endtask + ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_sv.out b/test_regress/t/t_var_bad_sv.out index 6e26bc0fa..c97f9325d 100644 --- a/test_regress/t/t_var_bad_sv.out +++ b/test_regress/t/t_var_bad_sv.out @@ -1,5 +1,11 @@ %Error: t/t_var_bad_sv.v:7: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language. + reg do; + ^~ %Error: t/t_var_bad_sv.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. + mod mod (.do(bar)); + ^~ %Error: t/t_var_bad_sv.v:8: syntax error, unexpected '(', expecting ')' + mod mod (.do(bar)); + ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_const_bad.out b/test_regress/t/t_var_const_bad.out index 20b69eea5..6d65a73f1 100644 --- a/test_regress/t/t_var_const_bad.out +++ b/test_regress/t/t_var_const_bad.out @@ -1,2 +1,4 @@ %Error: t/t_var_const_bad.v:16: Assigning to const variable: 'five' + five = 3'd4; + ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_dup2_bad.out b/test_regress/t/t_var_dup2_bad.out index f3e259631..78044c27d 100644 --- a/test_regress/t/t_var_dup2_bad.out +++ b/test_regress/t/t_var_dup2_bad.out @@ -1,6 +1,14 @@ %Error: t/t_var_dup2_bad.v:12: Duplicate declaration of signal: 'bad_o_w' : ... note: ANSI ports must have type declared with the I/O (IEEE 2017 23.2.2.2) + wire bad_o_w; + ^~~~~~~ t/t_var_dup2_bad.v:9: ... Location of original declaration + output bad_o_w, + ^~~~~~~ %Error: t/t_var_dup2_bad.v:13: Duplicate declaration of signal: 'bad_o_r' + reg bad_o_r; + ^~~~~~~ t/t_var_dup2_bad.v:10: ... Location of original declaration + output bad_o_r); + ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_dup_bad.out b/test_regress/t/t_var_dup_bad.out index a1cc32c01..7ecf933e6 100644 --- a/test_regress/t/t_var_dup_bad.out +++ b/test_regress/t/t_var_dup_bad.out @@ -1,39 +1,109 @@ %Error: t/t_var_dup_bad.v:16: Duplicate declaration of signal: 'a' + reg a; + ^ t/t_var_dup_bad.v:15: ... Location of original declaration + reg a; + ^ %Error: t/t_var_dup_bad.v:19: Duplicate declaration of signal: 'l' + integer l; + ^ t/t_var_dup_bad.v:18: ... Location of original declaration + integer l; + ^ %Error: t/t_var_dup_bad.v:22: Duplicate declaration of signal: 'b' + bit b; + ^ t/t_var_dup_bad.v:21: ... Location of original declaration + bit b; + ^ %Error: t/t_var_dup_bad.v:25: Duplicate declaration of signal: 'o' + output o; + ^ t/t_var_dup_bad.v:24: ... Location of original declaration + output o; + ^ %Error: t/t_var_dup_bad.v:28: Duplicate declaration of signal: 'i' + input i; + ^ t/t_var_dup_bad.v:27: ... Location of original declaration + input i; + ^ %Error: t/t_var_dup_bad.v:31: Duplicate declaration of signal: 'oi' + input oi; + ^~ t/t_var_dup_bad.v:30: ... Location of original declaration + output oi; + ^~ %Error: t/t_var_dup_bad.v:38: Duplicate declaration of signal: 'org' + output reg org; + ^~~ t/t_var_dup_bad.v:37: ... Location of original declaration + output reg org; + ^~~ %Error: t/t_var_dup_bad.v:65: Duplicate declaration of signal: 'bad_reout_port' + output bad_reout_port; + ^~~~~~~~~~~~~~ t/t_var_dup_bad.v:63: ... Location of original declaration + output bad_reout_port + ^~~~~~~~~~~~~~ %Error: t/t_var_dup_bad.v:72: Duplicate declaration of signal: 'bad_rewire' + wire bad_rewire; + ^~~~~~~~~~ t/t_var_dup_bad.v:69: ... Location of original declaration + (output wire bad_rewire, + ^~~~~~~~~~ %Error: t/t_var_dup_bad.v:73: Duplicate declaration of signal: 'bad_rereg' + reg bad_rereg; + ^~~~~~~~~ t/t_var_dup_bad.v:70: ... Location of original declaration + output reg bad_rereg + ^~~~~~~~~ %Error: t/t_var_dup_bad.v:12: Duplicate declaration of port: 'oi' + i, oi + ^~ t/t_var_dup_bad.v:30: ... Location of original declaration + output oi; + ^~ %Error: t/t_var_dup_bad.v:49: Duplicate declaration of port: 'bad_duport' + bad_duport + ^~~~~~~~~~ t/t_var_dup_bad.v:51: ... Location of original declaration + output bad_duport; + ^~~~~~~~~~ %Error: t/t_var_dup_bad.v:57: Duplicate declaration of port: 'bad_mixport' + output bad_mixport + ^~~~~~~~~~~ t/t_var_dup_bad.v:57: ... Location of original declaration + output bad_mixport + ^~~~~~~~~~~ %Error: t/t_var_dup_bad.v:40: Can't find definition of variable: 'bad_duport' + sub0 sub0(.*); + ^~~~ %Error: t/t_var_dup_bad.v:40: Duplicate pin connection: 'bad_duport' + sub0 sub0(.*); + ^~~~ t/t_var_dup_bad.v:40: ... Location of original pin connection + sub0 sub0(.*); + ^~~~ %Error: t/t_var_dup_bad.v:41: Can't find definition of variable: 'bad_mixport' : ... Suggested alternative: 'bad_duport' + sub1 sub1(.*); + ^~~~ %Error: t/t_var_dup_bad.v:41: Duplicate pin connection: 'bad_mixport' + sub1 sub1(.*); + ^~~~ t/t_var_dup_bad.v:41: ... Location of original pin connection + sub1 sub1(.*); + ^~~~ %Error: t/t_var_dup_bad.v:42: Can't find definition of variable: 'bad_reout_port' : ... Suggested alternative: 'bad_duport' + sub2 sub2(.*); + ^~~~ %Error: t/t_var_dup_bad.v:43: Can't find definition of variable: 'bad_rewire' + sub3 sub3(.*); + ^~~~ %Error: t/t_var_dup_bad.v:43: Can't find definition of variable: 'bad_rereg' : ... Suggested alternative: 'bad_rewire' + sub3 sub3(.*); + ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_in_assign_bad.out b/test_regress/t/t_var_in_assign_bad.out index 3841eb205..cd6b4a463 100644 --- a/test_regress/t/t_var_in_assign_bad.out +++ b/test_regress/t/t_var_in_assign_bad.out @@ -1,3 +1,7 @@ %Error-ASSIGNIN: t/t_var_in_assign_bad.v:11: Assigning to input/const variable: 'value' + assign value = 4'h0; + ^~~~~ %Error-ASSIGNIN: t/t_var_in_assign_bad.v:20: Assigning to input/const variable: 'valueSub' + assign valueSub = 4'h0; + ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_notfound_bad.out b/test_regress/t/t_var_notfound_bad.out index 0c9a50f97..cad5a6c9f 100644 --- a/test_regress/t/t_var_notfound_bad.out +++ b/test_regress/t/t_var_notfound_bad.out @@ -1,12 +1,24 @@ %Error: t/t_var_notfound_bad.v:17: Can't find definition of variable: 'nf' + nf = 0; + ^~ %Error: t/t_var_notfound_bad.v:18: Can't find definition of 'subsubz' in dotted scope/variable: 'sub.subsubz' + sub.subsubz.inss = 0; + ^~~~~~~ ... Known scopes under 'sub': subsub %Error: t/t_var_notfound_bad.v:19: Can't find definition of task/function: 'nofunc' : ... Suggested alternative: 'notfunc' + i = nofunc(); + ^~~~~~ %Error: t/t_var_notfound_bad.v:20: Can't find definition of 'nofuncs' in dotted task/function: 'sub.nofuncs' : ... Suggested alternative: 'notfuncs' + i = sub.nofuncs(); + ^~~~~~~ ... Known scopes under 'nofuncs': %Error: t/t_var_notfound_bad.v:21: Can't find definition of task/function: 'notask' : ... Suggested alternative: 'nottask' + notask(); + ^~~~~~ %Error: t/t_var_notfound_bad.v:22: Found definition of 'a_var' as a VAR but expected a task/function + a_var(); + ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_port2_bad.out b/test_regress/t/t_var_port2_bad.out index 6ab629b0f..2ca15102a 100644 --- a/test_regress/t/t_var_port2_bad.out +++ b/test_regress/t/t_var_port2_bad.out @@ -1,3 +1,7 @@ %Error: t/t_var_port2_bad.v:6: Input/output/inout declaration not found for port: 'portwithoin' +module t (portwithoin); + ^~~~~~~~~~~ %Error: t/t_var_port2_bad.v:7: Input/output/inout does not appear in port list: 'portwithin' + input portwithin; + ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_port_bad.out b/test_regress/t/t_var_port_bad.out index ca4591430..a0fda600c 100644 --- a/test_regress/t/t_var_port_bad.out +++ b/test_regress/t/t_var_port_bad.out @@ -1,2 +1,4 @@ %Error: t/t_var_port_bad.v:15: Input/output/inout does not appear in port list: 'b' + input a, b; + ^ %Error: Exiting due to diff --git a/test_regress/t/t_var_ref_bad1.out b/test_regress/t/t_var_ref_bad1.out index 3f2605033..58a781819 100644 --- a/test_regress/t/t_var_ref_bad1.out +++ b/test_regress/t/t_var_ref_bad1.out @@ -1,2 +1,4 @@ %Error: t/t_var_ref_bad1.v:13: Ref connection 'bad_sub_ref' requires matching types; ref requires BASICDTYPE 'real' but connection is BASICDTYPE 'bit'. + (.bad_sub_ref(bad_parent)); + ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_ref_bad2.out b/test_regress/t/t_var_ref_bad2.out index d1f363d6d..3262d7f3b 100644 --- a/test_regress/t/t_var_ref_bad2.out +++ b/test_regress/t/t_var_ref_bad2.out @@ -1,3 +1,7 @@ %Error: t/t_var_ref_bad2.v:12: Assigning to const ref variable: 'bad_const_set' + bad_const_set = 32'h4567; + ^~~~~~~~~~~~~ %Error: t/t_var_ref_bad2.v:22: Ref argument requires matching types; port 'int_ref' requires VAR 'int_ref' but connection is VARREF 'bad_non_int'. + checkset2(bad_non_int); + ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_ref_bad3.out b/test_regress/t/t_var_ref_bad3.out index 262bc0189..78118fc6d 100644 --- a/test_regress/t/t_var_ref_bad3.out +++ b/test_regress/t/t_var_ref_bad3.out @@ -1,2 +1,4 @@ %Error: t/t_var_ref_bad3.v:9: Unsupported: ref/const ref as primary input/output: 'bad_primary_ref' +module t(ref int bad_primary_ref + ^~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_rsvd_bad.out b/test_regress/t/t_var_rsvd_bad.out index 0998e311c..5d648c5d7 100644 --- a/test_regress/t/t_var_rsvd_bad.out +++ b/test_regress/t/t_var_rsvd_bad.out @@ -1,4 +1,8 @@ %Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:11: Symbol matches C++ keyword: 'bool' + input bool; + ^~~~ ... Use "/* verilator lint_off SYMRSVDWORD */" and lint_on around source to disable this message. %Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:14: Symbol matches C++ keyword: 'switch' + reg switch /*verilator public*/ ; + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_suggest_bad.out b/test_regress/t/t_var_suggest_bad.out index 8dab22b8c..e861eadd6 100644 --- a/test_regress/t/t_var_suggest_bad.out +++ b/test_regress/t/t_var_suggest_bad.out @@ -1,5 +1,9 @@ %Error: t/t_var_suggest_bad.v:12: Can't find definition of variable: 'foobat' : ... Suggested alternative: 'foobar' + if (foobat) $stop; + ^~~~~~ %Error: t/t_var_suggest_bad.v:13: Can't find definition of task/function: 'boobat' : ... Suggested alternative: 'boobar' + boobat; + ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_types_bad.out b/test_regress/t/t_var_types_bad.out index 86e1dcf87..e47bd8cc2 100644 --- a/test_regress/t/t_var_types_bad.out +++ b/test_regress/t/t_var_types_bad.out @@ -1,11 +1,29 @@ %Error: t/t_var_types_bad.v:38: Illegal bit or array select; type does not have a bit range, or bad dimension: type is bit + d_bitz[0] = 1'b1; + ^ %Error: t/t_var_types_bad.v:39: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic + d_logicz[0] = 1'b1; + ^ %Error: t/t_var_types_bad.v:40: Illegal bit or array select; type does not have a bit range, or bad dimension: type is logic + d_regz[0] = 1'b1; + ^ %Error: t/t_var_types_bad.v:45: Illegal bit or array select; type does not have a bit range, or bad dimension: type is real + d_real[0] = 1'b1; + ^ %Error: t/t_var_types_bad.v:45: Expected integral (non-real) input to SEL + d_real[0] = 1'b1; + ^~~~~~ %Warning-REALCVT: t/t_var_types_bad.v:45: Implicit conversion of real to integer + d_real[0] = 1'b1; + ^~~~~~ ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. %Error: t/t_var_types_bad.v:46: Illegal bit or array select; type does not have a bit range, or bad dimension: type is real + d_realtime[0] = 1'b1; + ^ %Error: t/t_var_types_bad.v:46: Expected integral (non-real) input to SEL + d_realtime[0] = 1'b1; + ^~~~~~~~~~ %Warning-REALCVT: t/t_var_types_bad.v:46: Implicit conversion of real to integer + d_realtime[0] = 1'b1; + ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_wire_beh_bad.out b/test_regress/t/t_wire_beh_bad.out index 7de87d764..2308abe57 100644 --- a/test_regress/t/t_wire_beh_bad.out +++ b/test_regress/t/t_wire_beh_bad.out @@ -1,3 +1,7 @@ %Error-CONTASSREG: t/t_wire_beh_bad.v:11: Continuous assignment to reg, perhaps intended wire (IEEE 2005 6.1; Verilog only, legal in SV): 'r' + assign r = 1'b1; + ^ %Error-PROCASSWIRE: t/t_wire_beh_bad.v:12: Procedural assignment to wire, perhaps intended var (IEEE 2017 6.5): 'w' + always @ (r) w = 1'b0; + ^ %Error: Exiting due to