From 97255dc8355ba73d5930584791ba5d25e9ceb172 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 23 Dec 2020 18:23:47 -0500
Subject: [PATCH] Tests: Test future if condition optimization (#2726)

---
 test_regress/t/t_optm_if_cond.pl | 22 ++++++++++++
 test_regress/t/t_optm_if_cond.v  | 57 ++++++++++++++++++++++++++++++++
 2 files changed, 79 insertions(+)
 create mode 100755 test_regress/t/t_optm_if_cond.pl
 create mode 100644 test_regress/t/t_optm_if_cond.v

diff --git a/test_regress/t/t_optm_if_cond.pl b/test_regress/t/t_optm_if_cond.pl
new file mode 100755
index 000000000..3c5833594
--- /dev/null
+++ b/test_regress/t/t_optm_if_cond.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    verilator_flags2 => ['--stats'],
+    );
+
+if ($Self->{vlt_all}) {
+    file_grep($Self->{stats}, qr/Node count, IF  +\d+ +\d+ +\d+ +\d+ +(\d+)/, 11);
+}
+
+ok(1);
+1;
diff --git a/test_regress/t/t_optm_if_cond.v b/test_regress/t/t_optm_if_cond.v
new file mode 100644
index 000000000..f9509efad
--- /dev/null
+++ b/test_regress/t/t_optm_if_cond.v
@@ -0,0 +1,57 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/
+   // Outputs
+   q0, q1, q2, q3, q4,
+   // Inputs
+   clk, rst, en, i0, i1, i2, i3, i4
+   );
+   input clk;
+
+   input rst;
+   input en;
+   output int q0;   input int i0;
+   output int q1;   input int i1;
+   output int q2;   input int i2;
+   output int q3;   input int i3;
+   output int q4;   input int i4;
+
+   always @ (posedge clk) begin
+      if (rst) begin
+         if (en) q0 <= i0;
+      end
+      else q0 <= 0;
+
+      if (rst) begin
+         if (en) q1 <= i1;
+      end
+      else q1 <= 0;
+
+      if (rst) begin
+         if (en) q2 <= i2;
+      end
+      else q2 <= 0;
+
+      if (rst) begin
+         if (en) q3 <= i3;
+      end
+      else q3 <= 0;
+   end
+
+   always_comb begin
+      q4 = i4;
+      if (q4 == 0) begin
+         // Conflicts with condition
+         q4 = 1;
+      end
+      if (q4 == 0) begin
+         // Conflicts with condition
+         q4 = 2;
+      end
+   end
+
+endmodule