From 96f8bbd023e4bb2510de3693e033d6ca9eaa35af Mon Sep 17 00:00:00 2001 From: Garrett Smith Date: Tue, 3 Dec 2019 18:22:17 -0500 Subject: [PATCH] Support float and shorts, bug1592, bug1619. Signed-off-by: Wilson Snyder --- Changes | 2 ++ docs/CONTRIBUTORS | 1 + include/verilated.cpp | 21 ++++++++++++++++++--- include/verilated_heavy.h | 18 ++++++++++++++++++ test_regress/t/t_sys_plusargs.pl | 2 +- test_regress/t/t_sys_plusargs.v | 31 ++++++++++++++++++++++++++++++- 6 files changed, 70 insertions(+), 5 deletions(-) diff --git a/Changes b/Changes index 9ded95c50..0a716ad72 100644 --- a/Changes +++ b/Changes @@ -20,6 +20,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Add error on redefining preprocessor directives. [Piotr Binkowski] +**** Support $value$plusargs float and shorts, bug1592, bug1619. [Garrett Smith] + **** Fix color assertion on empty if, bug1604. [Andrew Holme] **** Fix for loop missing initializer, bug1605. [Andrew Holme] diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 914039bad..d29ca10dc 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -8,6 +8,7 @@ Ahmed El-Mahmoudy Alex Chadwick Chris Randall Eric Rippey +Garrett Smith Gianfranco Costamagna Howard Su Iztok Jeras diff --git a/include/verilated.cpp b/include/verilated.cpp index 13463c190..904b6cfad 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -1708,9 +1708,24 @@ IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_M _vl_vsss_setbit(rwp, rbits, lsb, 8, dp[posp]); lsb+=8; } break; - case 'e': // FALLTHRU - Unsupported - case 'f': // FALLTHRU - Unsupported - case 'g': // FALLTHRU - Unsupported + case 'e': { + double temp = 0.f; + sscanf(dp, "%le", &temp); + VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); + break; + } + case 'f': { + double temp = 0.f; + sscanf(dp, "%lf", &temp); + VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); + break; + } + case 'g': { + double temp = 0.f; + sscanf(dp, "%lg", &temp); + VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); + break; + } default: // Other simulators simply return 0 in these cases and don't error out return 0; } diff --git a/include/verilated_heavy.h b/include/verilated_heavy.h index 6adda6447..03d1824ca 100644 --- a/include/verilated_heavy.h +++ b/include/verilated_heavy.h @@ -318,6 +318,18 @@ extern void VL_SFORMAT_X(int obits_ignored, std::string& output, const char* formatp, ...) VL_MT_SAFE; extern std::string VL_SFORMATF_NX(const char* formatp, ...) VL_MT_SAFE; extern IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_MT_SAFE; +inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, CData& rdr) VL_MT_SAFE { + WData rwp[2]; // WData must always be at least 2 + IData got = VL_VALUEPLUSARGS_INW(rbits,ld,rwp); + if (got) rdr = rwp[0]; + return got; +} +inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, SData& rdr) VL_MT_SAFE { + WData rwp[2]; // WData must always be at least 2 + IData got = VL_VALUEPLUSARGS_INW(rbits,ld,rwp); + if (got) rdr = rwp[0]; + return got; +} inline IData VL_VALUEPLUSARGS_INI(int rbits, const std::string& ld, IData& rdr) VL_MT_SAFE { WData rwp[2]; // WData must always be at least 2 IData got = VL_VALUEPLUSARGS_INW(rbits, ld, rwp); @@ -330,6 +342,12 @@ inline IData VL_VALUEPLUSARGS_INQ(int rbits, const std::string& ld, QData& rdr) if (got) rdr = VL_SET_QW(rwp); return got; } +inline IData VL_VALUEPLUSARGS_INQ(int rbits, const std::string& ld, double& rdr) VL_MT_SAFE { + WData rwp[2]; + IData got = VL_VALUEPLUSARGS_INW(rbits,ld,rwp); + if (got) rdr = VL_CVT_D_Q(VL_SET_QW(rwp)); + return got; +} extern IData VL_VALUEPLUSARGS_INN(int, const std::string& ld, std::string& rdr) VL_MT_SAFE; #endif // Guard diff --git a/test_regress/t/t_sys_plusargs.pl b/test_regress/t/t_sys_plusargs.pl index 587bd97e3..99b5b07cf 100755 --- a/test_regress/t/t_sys_plusargs.pl +++ b/test_regress/t/t_sys_plusargs.pl @@ -15,7 +15,7 @@ compile( execute( check_finished => 1, - all_run_flags => ['+PLUS +INT=1234 +STRSTR'], + all_run_flags => ['+PLUS +INT=1234 +STRSTR +REAL=1.2345'], ); ok(1); diff --git a/test_regress/t/t_sys_plusargs.v b/test_regress/t/t_sys_plusargs.v index 8de3437ae..470f7929a 100644 --- a/test_regress/t/t_sys_plusargs.v +++ b/test_regress/t/t_sys_plusargs.v @@ -5,7 +5,10 @@ module t; - integer p_i; + integer p_i; // signal type IData + reg [15:0] p_s; // signal type SData + reg [7:0] p_c; // signal type CData + real p_r; // signal type double reg [7*8:1] p_str; string sv_str; reg [7*8:1] p_in; @@ -35,6 +38,32 @@ module t; if (!$value$plusargs("INT=%o", p_i)) $stop; if (p_i !== 32'o1234) $stop; + // Check handling of 'SData' type signals (Issue #1592) + p_s = 0; + if (!$value$plusargs("INT=%d", p_s)) $stop; + if (p_s !== 16'd1234) $stop; + + // Check handling of 'CData' type signals (Issue #1592) + p_c = 0; + if (!$value$plusargs("INT=%d", p_c)) $stop; + if (p_c !== 8'd210) $stop; + + // Check handling of 'double' type signals (Issue #1619) + p_r = 0; + if (!$value$plusargs("REAL=%e", p_r)) $stop; + $display("r='%e'", p_r); + if (p_r !== 1.2345) $stop; + + p_r = 0; + if (!$value$plusargs("REAL=%f", p_r)) $stop; + $display("r='%f'", p_r); + if (p_r !== 1.2345) $stop; + + p_r = 0; + if (!$value$plusargs("REAL=%g", p_r)) $stop; + $display("r='%g'", p_r); + if (p_r !== 1.2345) $stop; + p_str = "none"; if ($value$plusargs("IN%s", p_str)!==1) $stop; $display("str='%s'",p_str);