From 96630cee5ae15d31a7ba9f6efb79a97b406d7601 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 7 Jun 2026 21:55:43 -0400 Subject: [PATCH] Verilog format --- test_regress/t/t_altera_lpm.v | 1 + test_regress/t/t_clk_first_bad.out | 4 +- test_regress/t/t_clk_first_deprecated.v | 3 +- .../t/t_constraint_pure_nonabs_bad.out | 6 +- test_regress/t/t_constraint_pure_nonabs_bad.v | 2 +- test_regress/t/t_dpi_accessors_inc.vh | 45 +- test_regress/t/t_dpi_accessors_macros_inc.vh | 26 +- test_regress/t/t_hier_block_chained.v | 368 +++++++------- test_regress/t/t_initial_inc.vh | 1 + test_regress/t/t_lint_in_inc_bad.out | 6 +- test_regress/t/t_lint_in_inc_bad_2.vh | 4 +- test_regress/t/t_lint_latch_bad_3.out | 6 +- test_regress/t/t_lint_latch_bad_3.v | 129 ++--- test_regress/t/t_lint_warn_incfile2_bad_b.vh | 4 +- test_regress/t/t_math_shift.v | 448 +++++++++--------- test_regress/t/t_mod_topmodule.v | 25 +- test_regress/t/t_preproc_inc_inc_bad.vh | 2 +- .../t/t_property_pexpr_parse_unsup.out | 96 ++-- test_regress/t/t_property_pexpr_unsup.out | 36 +- test_regress/t/t_property_pexpr_unsup.v | 204 ++++---- .../t/t_property_s_eventually_iface.v | 36 +- .../t/t_structu_dataType_assignment.v | 182 +++---- test_regress/t/t_vlt_warn_file_bad_b.vh | 2 +- 23 files changed, 817 insertions(+), 819 deletions(-) diff --git a/test_regress/t/t_altera_lpm.v b/test_regress/t/t_altera_lpm.v index 3b48d349c..967cd1dea 100644 --- a/test_regress/t/t_altera_lpm.v +++ b/test_regress/t/t_altera_lpm.v @@ -48,6 +48,7 @@ //END_MODULE_NAME-------------------------------------------------------------- //See also: https://github.com/twosigma/verilator_support +// verilog_format: off // verilator lint_off COMBDLY,INITIALDLY,LATCH,MULTIDRIVEN,UNSIGNED,WIDTH // BEGINNING OF MODULE diff --git a/test_regress/t/t_clk_first_bad.out b/test_regress/t/t_clk_first_bad.out index 9ce9543db..425d4ec7f 100644 --- a/test_regress/t/t_clk_first_bad.out +++ b/test_regress/t/t_clk_first_bad.out @@ -1,5 +1,5 @@ -%Warning-DEPRECATED: t/t_clk_first_deprecated.v:12:14: sc_clock is ignored - 12 | input clk /*verilator sc_clock*/; +%Warning-DEPRECATED: t/t_clk_first_deprecated.v:11:14: sc_clock is ignored + 11 | input clk /*verilator sc_clock*/; | ^~~~~~~~~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_clk_first_deprecated.v b/test_regress/t/t_clk_first_deprecated.v index 9142eb9ab..915c60a1e 100644 --- a/test_regress/t/t_clk_first_deprecated.v +++ b/test_regress/t/t_clk_first_deprecated.v @@ -4,8 +4,7 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t ( /*AUTOARG*/ - // Inputs +module t ( clk ); diff --git a/test_regress/t/t_constraint_pure_nonabs_bad.out b/test_regress/t/t_constraint_pure_nonabs_bad.out index 3de1a490d..4f97b4013 100644 --- a/test_regress/t/t_constraint_pure_nonabs_bad.out +++ b/test_regress/t/t_constraint_pure_nonabs_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_constraint_pure_nonabs_bad.v:8:20: Illegal to have 'pure constraint' in non-abstract class (IEEE 1800-2023 18.5.2) +%Error: t/t_constraint_pure_nonabs_bad.v:8:19: Illegal to have 'pure constraint' in non-abstract class (IEEE 1800-2023 18.5.2) : ... note: In instance 't' - 8 | pure constraint raintBad; - | ^~~~~~~~ + 8 | pure constraint raintBad; + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_constraint_pure_nonabs_bad.v b/test_regress/t/t_constraint_pure_nonabs_bad.v index 0ecef66a6..f907c9737 100644 --- a/test_regress/t/t_constraint_pure_nonabs_bad.v +++ b/test_regress/t/t_constraint_pure_nonabs_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 class NonAsbstract; - pure constraint raintBad; // Bad: Not in abstract class + pure constraint raintBad; // Bad: Not in abstract class endclass module t; diff --git a/test_regress/t/t_dpi_accessors_inc.vh b/test_regress/t/t_dpi_accessors_inc.vh index 7a2339678..911d4e874 100644 --- a/test_regress/t/t_dpi_accessors_inc.vh +++ b/test_regress/t/t_dpi_accessors_inc.vh @@ -9,29 +9,26 @@ // See t_dpi_accessors.v for details of the test. This file should be included // by the top level module to define all the accessors needed. - // Use the macros to provide the desire access to our data. First simple - // access to the registers, array elements and wires. For consistency with - // simulators, we do not attempt to write wires. - `RW_ACCESS([0:0], a, {t.i_test_sub.a}); - `RW_ACCESS([7:0], b, {t.i_test_sub.b}); - `RW_ACCESS([7:0], mem32, {t.i_test_sub.mem[32]}); - `R_ACCESS ([0:0], c, {t.i_test_sub.c}); - `R_ACCESS ([7:0], d, {t.i_test_sub.d}); - `RW_ACCESS([7:0], e, {t.i_test_sub.e}); - `RW_ACCESS([7:0], f, {t.i_test_sub.f}); +// Use the macros to provide the desire access to our data. First simple +// access to the registers, array elements and wires. For consistency with +// simulators, we do not attempt to write wires. +`RW_ACCESS([0:0], a, {t.i_test_sub.a}); +`RW_ACCESS([7:0], b, {t.i_test_sub.b}); +`RW_ACCESS([7:0], mem32, {t.i_test_sub.mem[32]}); +`R_ACCESS([0:0], c, {t.i_test_sub.c}); +`R_ACCESS([7:0], d, {t.i_test_sub.d}); +`RW_ACCESS([7:0], e, {t.i_test_sub.e}); +`RW_ACCESS([7:0], f, {t.i_test_sub.f}); - // Slices of vectors and array elements. For consistency with simulators, - // we do not attempt to write wire slices. - `RW_ACCESS([3:0], b_slice, {t.i_test_sub.b[3:0]}); - `RW_ACCESS([4:0], mem32_slice, - {t.i_test_sub.mem[32][7:6], t.i_test_sub.mem[32][2:0]}); - `R_ACCESS([5:0], d_slice, {t.i_test_sub.d[6:1]}); +// Slices of vectors and array elements. For consistency with simulators, +// we do not attempt to write wire slices. +`RW_ACCESS([3:0], b_slice, {t.i_test_sub.b[3:0]}); +`RW_ACCESS([4:0], mem32_slice, {t.i_test_sub.mem[32][7:6], t.i_test_sub.mem[32][2:0]}); +`R_ACCESS([5:0], d_slice, {t.i_test_sub.d[6:1]}); - // Complex registers, one with distinct read and write. We avoid use of - // wires for consistency with simulators. - `RW_ACCESS([14:0], l1, {t.i_test_sub.b[3:0], - t.i_test_sub.mem[32][7:6], - t.i_test_sub.e[6:1], - t.i_test_sub.mem[32][2:0]}); - `R_ACCESS([7:0], l2, {t.i_test_sub.e[7:4], t.i_test_sub.f[3:0]}); - `W_ACCESS([7:0], l2, {t.i_test_sub.e[5:2], t.i_test_sub.f[5:2]}); +// Complex registers, one with distinct read and write. We avoid use of +// wires for consistency with simulators. +`RW_ACCESS([14:0], l1, {t.i_test_sub.b[3:0], t.i_test_sub.mem[32][7:6], t.i_test_sub.e[6:1], + t.i_test_sub.mem[32][2:0]}); +`R_ACCESS([7:0], l2, {t.i_test_sub.e[7:4], t.i_test_sub.f[3:0]}); +`W_ACCESS([7:0], l2, {t.i_test_sub.e[5:2], t.i_test_sub.f[5:2]}); diff --git a/test_regress/t/t_dpi_accessors_macros_inc.vh b/test_regress/t/t_dpi_accessors_macros_inc.vh index 90c41f5ce..1a017ec7e 100644 --- a/test_regress/t/t_dpi_accessors_macros_inc.vh +++ b/test_regress/t/t_dpi_accessors_macros_inc.vh @@ -9,20 +9,22 @@ // See t_dpi_accessors.v for details of the test. This file should be included // by the top level module to define the generic accessor macros. +// verilog_format: off + // Accessor macros, to keep stuff concise `define R_ACCESS(type_spec, name, expr) \ - export "DPI-C" function name``_read; \ - function bit type_spec name``_read; \ - name``_read = (expr); \ - endfunction + export "DPI-C" function name``_read; \ + function bit type_spec name``_read; \ + name``_read = (expr); \ + endfunction -`define W_ACCESS(type_spec, name, expr) \ - export "DPI-C" task name``_write; \ - task name``_write; \ - input bit type_spec in; \ - expr = in; \ - endtask +`define W_ACCESS(type_spec, name, expr) \ + export "DPI-C" task name``_write; \ + task name``_write; \ + input bit type_spec in; \ + expr = in; \ + endtask `define RW_ACCESS(type_spec, name, expr) \ - `R_ACCESS (type_spec, name, expr); \ - `W_ACCESS (type_spec, name, expr) + `R_ACCESS (type_spec, name, expr); \ + `W_ACCESS (type_spec, name, expr) diff --git a/test_regress/t/t_hier_block_chained.v b/test_regress/t/t_hier_block_chained.v index 5d3739823..db3fe8a9b 100644 --- a/test_regress/t/t_hier_block_chained.v +++ b/test_regress/t/t_hier_block_chained.v @@ -11,204 +11,204 @@ module t (clk); logic reset; - reg [255:0] v2_0; - reg [255:0] v1_0; - reg [255:0] v1_1; - reg [255:0] v1_2; - reg [255:0] v1_3; - reg [255:0] v1_4; - reg [255:0] v1_5; - reg [255:0] v1_6; - reg [255:0] v1_7; - // verilator lint_off MULTIDRIVEN - reg [255:0] dummy; - // verilator lint_on MULTIDRIVEN + reg [255:0] v2_0; + reg [255:0] v1_0; + reg [255:0] v1_1; + reg [255:0] v1_2; + reg [255:0] v1_3; + reg [255:0] v1_4; + reg [255:0] v1_5; + reg [255:0] v1_6; + reg [255:0] v1_7; + // verilator lint_off MULTIDRIVEN + reg [255:0] dummy; + // verilator lint_on MULTIDRIVEN - Calculate calc0(.clk(clk), .reset(reset), .v1_0(v1_0), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); - Calculate calc1(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(v1_1), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); - Calculate calc2(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(v1_2), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); - Calculate calc3(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(v1_3), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); - Calculate calc4(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(v1_4), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); - Calculate calc5(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(v1_5), .v1_6(dummy), .v1_7(dummy)); - Calculate calc6(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(v1_6), .v1_7(dummy)); - Calculate calc7(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(v1_7)); - always @ (posedge clk) v2_0 <= v1_0 + v1_1 + v1_2 + v1_3 + v1_4 + v1_5 + v1_6 + v1_7; - Check chk(.clk(clk), .reset(reset), .v2_0(v2_0)); + Calculate calc0(.clk(clk), .reset(reset), .v1_0(v1_0), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); + Calculate calc1(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(v1_1), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); + Calculate calc2(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(v1_2), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); + Calculate calc3(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(v1_3), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); + Calculate calc4(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(v1_4), .v1_5(dummy), .v1_6(dummy), .v1_7(dummy)); + Calculate calc5(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(v1_5), .v1_6(dummy), .v1_7(dummy)); + Calculate calc6(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(v1_6), .v1_7(dummy)); + Calculate calc7(.clk(clk), .reset(reset), .v1_0(dummy), .v1_1(dummy), .v1_2(dummy), .v1_3(dummy), .v1_4(dummy), .v1_5(dummy), .v1_6(dummy), .v1_7(v1_7)); + always @ (posedge clk) v2_0 <= v1_0 + v1_1 + v1_2 + v1_3 + v1_4 + v1_5 + v1_6 + v1_7; + Check chk(.clk(clk), .reset(reset), .v2_0(v2_0)); endmodule module Check(input clk, output logic reset, input reg [255:0] v2_0); integer cyc=0; - always @ (posedge clk) begin - cyc <= cyc + 1; + always @ (posedge clk) begin + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $write("[%0t] rst=%0x v0_0=%0x v1_0=%0x result=%0x\n", $time, reset, v0_0, v1_0, v2_0); + $write("[%0t] rst=%0x v0_0=%0x v1_0=%0x result=%0x\n", $time, reset, v0_0, v1_0, v2_0); `endif - if (cyc==0) begin - reset <= 1; - end - else if (cyc==10) begin - reset <= 0; - end + if (cyc==0) begin + reset <= 1; + end + else if (cyc==10) begin + reset <= 0; + end `ifndef SIM_CYCLES `define SIM_CYCLES 99 `endif - else if (cyc==`SIM_CYCLES) begin - if (v2_0 != 256'd2017) $stop; - $write("VARS=64 WIDTH=256 WORKINGSET=2KB\n"); - $write("*-* All Finished *-*\n"); - $finish; - end - end + else if (cyc==`SIM_CYCLES) begin + if (v2_0 != 256'd2017) $stop; + $write("VARS=64 WIDTH=256 WORKINGSET=2KB\n"); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Calculate(input clk, - input reset, - output reg [255:0] v1_0, - output reg [255:0] v1_1, - output reg [255:0] v1_2, - output reg [255:0] v1_3, - output reg [255:0] v1_4, - output reg [255:0] v1_5, - output reg [255:0] v1_6, - output reg [255:0] v1_7 - ); - reg [255:0] v0_0; - reg [255:0] v0_1; - reg [255:0] v0_2; - reg [255:0] v0_3; - reg [255:0] v0_4; - reg [255:0] v0_5; - reg [255:0] v0_6; - reg [255:0] v0_7; - reg [255:0] v0_8; - reg [255:0] v0_9; - reg [255:0] v0_10; - reg [255:0] v0_11; - reg [255:0] v0_12; - reg [255:0] v0_13; - reg [255:0] v0_14; - reg [255:0] v0_15; - reg [255:0] v0_16; - reg [255:0] v0_17; - reg [255:0] v0_18; - reg [255:0] v0_19; - reg [255:0] v0_20; - reg [255:0] v0_21; - reg [255:0] v0_22; - reg [255:0] v0_23; - reg [255:0] v0_24; - reg [255:0] v0_25; - reg [255:0] v0_26; - reg [255:0] v0_27; - reg [255:0] v0_28; - reg [255:0] v0_29; - reg [255:0] v0_30; - reg [255:0] v0_31; - reg [255:0] v0_32; - reg [255:0] v0_33; - reg [255:0] v0_34; - reg [255:0] v0_35; - reg [255:0] v0_36; - reg [255:0] v0_37; - reg [255:0] v0_38; - reg [255:0] v0_39; - reg [255:0] v0_40; - reg [255:0] v0_41; - reg [255:0] v0_42; - reg [255:0] v0_43; - reg [255:0] v0_44; - reg [255:0] v0_45; - reg [255:0] v0_46; - reg [255:0] v0_47; - reg [255:0] v0_48; - reg [255:0] v0_49; - reg [255:0] v0_50; - reg [255:0] v0_51; - reg [255:0] v0_52; - reg [255:0] v0_53; - reg [255:0] v0_54; - reg [255:0] v0_55; - reg [255:0] v0_56; - reg [255:0] v0_57; - reg [255:0] v0_58; - reg [255:0] v0_59; - reg [255:0] v0_60; - reg [255:0] v0_61; - reg [255:0] v0_62; - reg [255:0] v0_63; + input reset, + output reg [255:0] v1_0, + output reg [255:0] v1_1, + output reg [255:0] v1_2, + output reg [255:0] v1_3, + output reg [255:0] v1_4, + output reg [255:0] v1_5, + output reg [255:0] v1_6, + output reg [255:0] v1_7 + ); + reg [255:0] v0_0; + reg [255:0] v0_1; + reg [255:0] v0_2; + reg [255:0] v0_3; + reg [255:0] v0_4; + reg [255:0] v0_5; + reg [255:0] v0_6; + reg [255:0] v0_7; + reg [255:0] v0_8; + reg [255:0] v0_9; + reg [255:0] v0_10; + reg [255:0] v0_11; + reg [255:0] v0_12; + reg [255:0] v0_13; + reg [255:0] v0_14; + reg [255:0] v0_15; + reg [255:0] v0_16; + reg [255:0] v0_17; + reg [255:0] v0_18; + reg [255:0] v0_19; + reg [255:0] v0_20; + reg [255:0] v0_21; + reg [255:0] v0_22; + reg [255:0] v0_23; + reg [255:0] v0_24; + reg [255:0] v0_25; + reg [255:0] v0_26; + reg [255:0] v0_27; + reg [255:0] v0_28; + reg [255:0] v0_29; + reg [255:0] v0_30; + reg [255:0] v0_31; + reg [255:0] v0_32; + reg [255:0] v0_33; + reg [255:0] v0_34; + reg [255:0] v0_35; + reg [255:0] v0_36; + reg [255:0] v0_37; + reg [255:0] v0_38; + reg [255:0] v0_39; + reg [255:0] v0_40; + reg [255:0] v0_41; + reg [255:0] v0_42; + reg [255:0] v0_43; + reg [255:0] v0_44; + reg [255:0] v0_45; + reg [255:0] v0_46; + reg [255:0] v0_47; + reg [255:0] v0_48; + reg [255:0] v0_49; + reg [255:0] v0_50; + reg [255:0] v0_51; + reg [255:0] v0_52; + reg [255:0] v0_53; + reg [255:0] v0_54; + reg [255:0] v0_55; + reg [255:0] v0_56; + reg [255:0] v0_57; + reg [255:0] v0_58; + reg [255:0] v0_59; + reg [255:0] v0_60; + reg [255:0] v0_61; + reg [255:0] v0_62; + reg [255:0] v0_63; - always @ (posedge clk) v0_0 <= reset ? 256'd1 : v0_1; - always @ (posedge clk) v0_1 <= reset ? 256'd1 : v0_2; - always @ (posedge clk) v0_2 <= reset ? 256'd2 : v0_3; - always @ (posedge clk) v0_3 <= reset ? 256'd3 : v0_4; - always @ (posedge clk) v0_4 <= reset ? 256'd4 : v0_5; - always @ (posedge clk) v0_5 <= reset ? 256'd5 : v0_6; - always @ (posedge clk) v0_6 <= reset ? 256'd6 : v0_7; - always @ (posedge clk) v0_7 <= reset ? 256'd7 : v0_0; - always @ (posedge clk) v0_8 <= reset ? 256'd8 : v0_9; - always @ (posedge clk) v0_9 <= reset ? 256'd9 : v0_10; - always @ (posedge clk) v0_10 <= reset ? 256'd10 : v0_11; - always @ (posedge clk) v0_11 <= reset ? 256'd11 : v0_12; - always @ (posedge clk) v0_12 <= reset ? 256'd12 : v0_13; - always @ (posedge clk) v0_13 <= reset ? 256'd13 : v0_14; - always @ (posedge clk) v0_14 <= reset ? 256'd14 : v0_15; - always @ (posedge clk) v0_15 <= reset ? 256'd15 : v0_8; - always @ (posedge clk) v0_16 <= reset ? 256'd16 : v0_17; - always @ (posedge clk) v0_17 <= reset ? 256'd17 : v0_18; - always @ (posedge clk) v0_18 <= reset ? 256'd18 : v0_19; - always @ (posedge clk) v0_19 <= reset ? 256'd19 : v0_20; - always @ (posedge clk) v0_20 <= reset ? 256'd20 : v0_21; - always @ (posedge clk) v0_21 <= reset ? 256'd21 : v0_22; - always @ (posedge clk) v0_22 <= reset ? 256'd22 : v0_23; - always @ (posedge clk) v0_23 <= reset ? 256'd23 : v0_16; - always @ (posedge clk) v0_24 <= reset ? 256'd24 : v0_25; - always @ (posedge clk) v0_25 <= reset ? 256'd25 : v0_26; - always @ (posedge clk) v0_26 <= reset ? 256'd26 : v0_27; - always @ (posedge clk) v0_27 <= reset ? 256'd27 : v0_28; - always @ (posedge clk) v0_28 <= reset ? 256'd28 : v0_29; - always @ (posedge clk) v0_29 <= reset ? 256'd29 : v0_30; - always @ (posedge clk) v0_30 <= reset ? 256'd30 : v0_31; - always @ (posedge clk) v0_31 <= reset ? 256'd31 : v0_24; - always @ (posedge clk) v0_32 <= reset ? 256'd32 : v0_33; - always @ (posedge clk) v0_33 <= reset ? 256'd33 : v0_34; - always @ (posedge clk) v0_34 <= reset ? 256'd34 : v0_35; - always @ (posedge clk) v0_35 <= reset ? 256'd35 : v0_36; - always @ (posedge clk) v0_36 <= reset ? 256'd36 : v0_37; - always @ (posedge clk) v0_37 <= reset ? 256'd37 : v0_38; - always @ (posedge clk) v0_38 <= reset ? 256'd38 : v0_39; - always @ (posedge clk) v0_39 <= reset ? 256'd39 : v0_32; - always @ (posedge clk) v0_40 <= reset ? 256'd40 : v0_41; - always @ (posedge clk) v0_41 <= reset ? 256'd41 : v0_42; - always @ (posedge clk) v0_42 <= reset ? 256'd42 : v0_43; - always @ (posedge clk) v0_43 <= reset ? 256'd43 : v0_44; - always @ (posedge clk) v0_44 <= reset ? 256'd44 : v0_45; - always @ (posedge clk) v0_45 <= reset ? 256'd45 : v0_46; - always @ (posedge clk) v0_46 <= reset ? 256'd46 : v0_47; - always @ (posedge clk) v0_47 <= reset ? 256'd47 : v0_40; - always @ (posedge clk) v0_48 <= reset ? 256'd48 : v0_49; - always @ (posedge clk) v0_49 <= reset ? 256'd49 : v0_50; - always @ (posedge clk) v0_50 <= reset ? 256'd50 : v0_51; - always @ (posedge clk) v0_51 <= reset ? 256'd51 : v0_52; - always @ (posedge clk) v0_52 <= reset ? 256'd52 : v0_53; - always @ (posedge clk) v0_53 <= reset ? 256'd53 : v0_54; - always @ (posedge clk) v0_54 <= reset ? 256'd54 : v0_55; - always @ (posedge clk) v0_55 <= reset ? 256'd55 : v0_48; - always @ (posedge clk) v0_56 <= reset ? 256'd56 : v0_57; - always @ (posedge clk) v0_57 <= reset ? 256'd57 : v0_58; - always @ (posedge clk) v0_58 <= reset ? 256'd58 : v0_59; - always @ (posedge clk) v0_59 <= reset ? 256'd59 : v0_60; - always @ (posedge clk) v0_60 <= reset ? 256'd60 : v0_61; - always @ (posedge clk) v0_61 <= reset ? 256'd61 : v0_62; - always @ (posedge clk) v0_62 <= reset ? 256'd62 : v0_63; - always @ (posedge clk) v0_63 <= reset ? 256'd63 : v0_56; + always @ (posedge clk) v0_0 <= reset ? 256'd1 : v0_1; + always @ (posedge clk) v0_1 <= reset ? 256'd1 : v0_2; + always @ (posedge clk) v0_2 <= reset ? 256'd2 : v0_3; + always @ (posedge clk) v0_3 <= reset ? 256'd3 : v0_4; + always @ (posedge clk) v0_4 <= reset ? 256'd4 : v0_5; + always @ (posedge clk) v0_5 <= reset ? 256'd5 : v0_6; + always @ (posedge clk) v0_6 <= reset ? 256'd6 : v0_7; + always @ (posedge clk) v0_7 <= reset ? 256'd7 : v0_0; + always @ (posedge clk) v0_8 <= reset ? 256'd8 : v0_9; + always @ (posedge clk) v0_9 <= reset ? 256'd9 : v0_10; + always @ (posedge clk) v0_10 <= reset ? 256'd10 : v0_11; + always @ (posedge clk) v0_11 <= reset ? 256'd11 : v0_12; + always @ (posedge clk) v0_12 <= reset ? 256'd12 : v0_13; + always @ (posedge clk) v0_13 <= reset ? 256'd13 : v0_14; + always @ (posedge clk) v0_14 <= reset ? 256'd14 : v0_15; + always @ (posedge clk) v0_15 <= reset ? 256'd15 : v0_8; + always @ (posedge clk) v0_16 <= reset ? 256'd16 : v0_17; + always @ (posedge clk) v0_17 <= reset ? 256'd17 : v0_18; + always @ (posedge clk) v0_18 <= reset ? 256'd18 : v0_19; + always @ (posedge clk) v0_19 <= reset ? 256'd19 : v0_20; + always @ (posedge clk) v0_20 <= reset ? 256'd20 : v0_21; + always @ (posedge clk) v0_21 <= reset ? 256'd21 : v0_22; + always @ (posedge clk) v0_22 <= reset ? 256'd22 : v0_23; + always @ (posedge clk) v0_23 <= reset ? 256'd23 : v0_16; + always @ (posedge clk) v0_24 <= reset ? 256'd24 : v0_25; + always @ (posedge clk) v0_25 <= reset ? 256'd25 : v0_26; + always @ (posedge clk) v0_26 <= reset ? 256'd26 : v0_27; + always @ (posedge clk) v0_27 <= reset ? 256'd27 : v0_28; + always @ (posedge clk) v0_28 <= reset ? 256'd28 : v0_29; + always @ (posedge clk) v0_29 <= reset ? 256'd29 : v0_30; + always @ (posedge clk) v0_30 <= reset ? 256'd30 : v0_31; + always @ (posedge clk) v0_31 <= reset ? 256'd31 : v0_24; + always @ (posedge clk) v0_32 <= reset ? 256'd32 : v0_33; + always @ (posedge clk) v0_33 <= reset ? 256'd33 : v0_34; + always @ (posedge clk) v0_34 <= reset ? 256'd34 : v0_35; + always @ (posedge clk) v0_35 <= reset ? 256'd35 : v0_36; + always @ (posedge clk) v0_36 <= reset ? 256'd36 : v0_37; + always @ (posedge clk) v0_37 <= reset ? 256'd37 : v0_38; + always @ (posedge clk) v0_38 <= reset ? 256'd38 : v0_39; + always @ (posedge clk) v0_39 <= reset ? 256'd39 : v0_32; + always @ (posedge clk) v0_40 <= reset ? 256'd40 : v0_41; + always @ (posedge clk) v0_41 <= reset ? 256'd41 : v0_42; + always @ (posedge clk) v0_42 <= reset ? 256'd42 : v0_43; + always @ (posedge clk) v0_43 <= reset ? 256'd43 : v0_44; + always @ (posedge clk) v0_44 <= reset ? 256'd44 : v0_45; + always @ (posedge clk) v0_45 <= reset ? 256'd45 : v0_46; + always @ (posedge clk) v0_46 <= reset ? 256'd46 : v0_47; + always @ (posedge clk) v0_47 <= reset ? 256'd47 : v0_40; + always @ (posedge clk) v0_48 <= reset ? 256'd48 : v0_49; + always @ (posedge clk) v0_49 <= reset ? 256'd49 : v0_50; + always @ (posedge clk) v0_50 <= reset ? 256'd50 : v0_51; + always @ (posedge clk) v0_51 <= reset ? 256'd51 : v0_52; + always @ (posedge clk) v0_52 <= reset ? 256'd52 : v0_53; + always @ (posedge clk) v0_53 <= reset ? 256'd53 : v0_54; + always @ (posedge clk) v0_54 <= reset ? 256'd54 : v0_55; + always @ (posedge clk) v0_55 <= reset ? 256'd55 : v0_48; + always @ (posedge clk) v0_56 <= reset ? 256'd56 : v0_57; + always @ (posedge clk) v0_57 <= reset ? 256'd57 : v0_58; + always @ (posedge clk) v0_58 <= reset ? 256'd58 : v0_59; + always @ (posedge clk) v0_59 <= reset ? 256'd59 : v0_60; + always @ (posedge clk) v0_60 <= reset ? 256'd60 : v0_61; + always @ (posedge clk) v0_61 <= reset ? 256'd61 : v0_62; + always @ (posedge clk) v0_62 <= reset ? 256'd62 : v0_63; + always @ (posedge clk) v0_63 <= reset ? 256'd63 : v0_56; - always @ (posedge clk) v1_0 <= v0_0 + v0_1 + v0_2 + v0_3 + v0_4 + v0_5 + v0_6 + v0_7; - always @ (posedge clk) v1_1 <= v0_8 + v0_9 + v0_10 + v0_11 + v0_12 + v0_13 + v0_14 + v0_15; - always @ (posedge clk) v1_2 <= v0_16 + v0_17 + v0_18 + v0_19 + v0_20 + v0_21 + v0_22 + v0_23; - always @ (posedge clk) v1_3 <= v0_24 + v0_25 + v0_26 + v0_27 + v0_28 + v0_29 + v0_30 + v0_31; - always @ (posedge clk) v1_4 <= v0_32 + v0_33 + v0_34 + v0_35 + v0_36 + v0_37 + v0_38 + v0_39; - always @ (posedge clk) v1_5 <= v0_40 + v0_41 + v0_42 + v0_43 + v0_44 + v0_45 + v0_46 + v0_47; - always @ (posedge clk) v1_6 <= v0_48 + v0_49 + v0_50 + v0_51 + v0_52 + v0_53 + v0_54 + v0_55; - always @ (posedge clk) v1_7 <= v0_56 + v0_57 + v0_58 + v0_59 + v0_60 + v0_61 + v0_62 + v0_63; + always @ (posedge clk) v1_0 <= v0_0 + v0_1 + v0_2 + v0_3 + v0_4 + v0_5 + v0_6 + v0_7; + always @ (posedge clk) v1_1 <= v0_8 + v0_9 + v0_10 + v0_11 + v0_12 + v0_13 + v0_14 + v0_15; + always @ (posedge clk) v1_2 <= v0_16 + v0_17 + v0_18 + v0_19 + v0_20 + v0_21 + v0_22 + v0_23; + always @ (posedge clk) v1_3 <= v0_24 + v0_25 + v0_26 + v0_27 + v0_28 + v0_29 + v0_30 + v0_31; + always @ (posedge clk) v1_4 <= v0_32 + v0_33 + v0_34 + v0_35 + v0_36 + v0_37 + v0_38 + v0_39; + always @ (posedge clk) v1_5 <= v0_40 + v0_41 + v0_42 + v0_43 + v0_44 + v0_45 + v0_46 + v0_47; + always @ (posedge clk) v1_6 <= v0_48 + v0_49 + v0_50 + v0_51 + v0_52 + v0_53 + v0_54 + v0_55; + always @ (posedge clk) v1_7 <= v0_56 + v0_57 + v0_58 + v0_59 + v0_60 + v0_61 + v0_62 + v0_63; endmodule diff --git a/test_regress/t/t_initial_inc.vh b/test_regress/t/t_initial_inc.vh index 3e52492c1..d6b3bee9f 100644 --- a/test_regress/t/t_initial_inc.vh +++ b/test_regress/t/t_initial_inc.vh @@ -4,6 +4,7 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define foo bar `ifdef foo `ifdef baz `else diff --git a/test_regress/t/t_lint_in_inc_bad.out b/test_regress/t/t_lint_in_inc_bad.out index 99675736e..8044313b5 100644 --- a/test_regress/t/t_lint_in_inc_bad.out +++ b/test_regress/t/t_lint_in_inc_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_lint_in_inc_bad_2.vh:9:7: syntax error, unexpected if, expecting '(' - 9 | if if if; - | ^~ +%Error: t/t_lint_in_inc_bad_2.vh:9:6: syntax error, unexpected if, expecting '(' + 9 | if if if; + | ^~ t/t_lint_in_inc_bad_1.vh:8:1: ... note: In file included from 't_lint_in_inc_bad_1.vh' t/t_lint_in_inc_bad.v:8:1: ... note: In file included from 't_lint_in_inc_bad.v' ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. diff --git a/test_regress/t/t_lint_in_inc_bad_2.vh b/test_regress/t/t_lint_in_inc_bad_2.vh index cfcc5be74..f509db1c1 100644 --- a/test_regress/t/t_lint_in_inc_bad_2.vh +++ b/test_regress/t/t_lint_in_inc_bad_2.vh @@ -5,6 +5,6 @@ // SPDX-License-Identifier: CC0-1.0 module x; - // Syntax error - if if if; + // Syntax error + if if if; endmodule diff --git a/test_regress/t/t_lint_latch_bad_3.out b/test_regress/t/t_lint_latch_bad_3.out index 93a9577b8..137c4bc26 100644 --- a/test_regress/t/t_lint_latch_bad_3.out +++ b/test_regress/t/t_lint_latch_bad_3.out @@ -1,7 +1,7 @@ -%Warning-LATCH: t/t_lint_latch_bad_3.v:19:1: Latch inferred for signal 'o5' (not all control paths of combinational always assign a value) +%Warning-LATCH: t/t_lint_latch_bad_3.v:30:3: Latch inferred for signal 'o5' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches - 19 | always_comb - | ^~~~~~~~~~~ + 30 | always_comb + | ^~~~~~~~~~~ ... For warning description see https://verilator.org/warn/LATCH?v=latest ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_bad_3.v b/test_regress/t/t_lint_latch_bad_3.v index ee459ade6..c37a5749d 100644 --- a/test_regress/t/t_lint_latch_bad_3.v +++ b/test_regress/t/t_lint_latch_bad_3.v @@ -4,72 +4,73 @@ // SPDX-FileCopyrightText: 2020 Julien Margetts // SPDX-License-Identifier: Unlicense -module t (/*AUTOARG*/ reset, a, b, c, en, o1, o2, o3, o4, o5); - input reset; - input a; - input b; - input c; - input en; - output reg o1; // Always assigned - output reg o2; // " - output reg o3; // " - output reg o4; // " - output reg o5; // Latch +module t ( /*AUTOARG*/ + reset, + a, + b, + c, + en, + o1, + o2, + o3, + o4, + o5 +); + input reset; + input a; + input b; + input c; + input en; + output reg o1; // Always assigned + output reg o2; // " + output reg o3; // " + output reg o4; // " + output reg o5; // Latch -always_comb -if (reset) -begin - o1 = 1'b0; - o2 = 1'b0; - o3 = 1'b0; - o4 = 1'b0; - o5 = 1'b0; -end -else -begin - o1 = 1'b1; - if (en) - begin + always_comb + if (reset) begin + o1 = 1'b0; o2 = 1'b0; - - if (a) - begin - o3 = a; - o5 = 1'b1; - end - else - begin - o3 = ~a; - o5 = a; - end - - // o3 is not assigned in either path of this if/else - // but no latch because always assigned above - if (c) - begin - o2 = a ^ b; - o4 = 1'b1; - end - else - o4 = ~a ^ b; - - o2 = 1'b1; - end - else - begin - o2 = 1'b1; - if (b) - begin - o3 = ~a | b; - o5 = ~b; - end - else - begin - o3 = a & ~b; - // No assignment to o5, expect Warning-LATCH - end + o3 = 1'b0; o4 = 1'b0; - end -end + o5 = 1'b0; + end + else begin + o1 = 1'b1; + if (en) begin + o2 = 1'b0; + + if (a) begin + o3 = a; + o5 = 1'b1; + end + else begin + o3 = ~a; + o5 = a; + end + + // o3 is not assigned in either path of this if/else + // but no latch because always assigned above + if (c) begin + o2 = a ^ b; + o4 = 1'b1; + end + else o4 = ~a ^ b; + + o2 = 1'b1; + end + else begin + o2 = 1'b1; + if (b) begin + o3 = ~a | b; + o5 = ~b; + end + else begin + o3 = a & ~b; + // No assignment to o5, expect Warning-LATCH + end + o4 = 1'b0; + end + end endmodule diff --git a/test_regress/t/t_lint_warn_incfile2_bad_b.vh b/test_regress/t/t_lint_warn_incfile2_bad_b.vh index bc6ffde2f..9a9e217dd 100644 --- a/test_regress/t/t_lint_warn_incfile2_bad_b.vh +++ b/test_regress/t/t_lint_warn_incfile2_bad_b.vh @@ -5,6 +5,6 @@ // SPDX-License-Identifier: CC0-1.0 module sub; - // verilator lint_off WIDTHTRUNC - int warn_sub = 64'h1; // Suppressed + // verilator lint_off WIDTHTRUNC + int warn_sub = 64'h1; // Suppressed endmodule diff --git a/test_regress/t/t_math_shift.v b/test_regress/t/t_math_shift.v index c78333832..bd8df1c16 100644 --- a/test_regress/t/t_math_shift.v +++ b/test_regress/t/t_math_shift.v @@ -5,248 +5,248 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Outputs - ign, ign2, ign3, c_wright_32, c_wleft_32, ign4, ign4s, - // Inputs - clk - ); + // Outputs + ign, ign2, ign3, c_wright_32, c_wleft_32, ign4, ign4s, + // Inputs + clk + ); - input clk; - output [31:0] ign; - output [3:0] ign2; - output [11:0] ign3; + input clk; + output [31:0] ign; + output [3:0] ign2; + output [11:0] ign3; - parameter [95:0] P6 = 6; - localparam P64 = (1 << P6); + parameter [95:0] P6 = 6; + localparam P64 = (1 << P6); - // verilator lint_off WIDTH - localparam [4:0] PBIG23 = 1'b1 << ~73'b0; - localparam [3:0] PBIG29 = 4'b1 << 33'h100000000; - // verilator lint_on WIDTH + // verilator lint_off WIDTH + localparam [4:0] PBIG23 = 1'b1 << ~73'b0; + localparam [3:0] PBIG29 = 4'b1 << 33'h100000000; + // verilator lint_on WIDTH - reg [31:0] iright; - reg signed [31:0] irights; - reg [31:0] ileft; - reg [P64-1:0] qright; - reg signed [P64-1:0] qrights; - reg [P64-1:0] qleft; - reg [95:0] wright; - reg signed [95:0] wrights; - reg [95:0] wleft; + reg [31:0] iright; + reg signed [31:0] irights; + reg [31:0] ileft; + reg [P64-1:0] qright; + reg signed [P64-1:0] qrights; + reg [P64-1:0] qleft; + reg [95:0] wright; + reg signed [95:0] wrights; + reg [95:0] wleft; - reg [31:0] q_iright; - reg signed [31:0] q_irights; - reg [31:0] q_ileft; - reg [P64-1:0] q_qright; - reg signed [P64-1:0] q_qrights; - reg [P64-1:0] q_qleft; - reg [95:0] q_wright; - reg signed [95:0] q_wrights; - reg [95:0] q_wleft; + reg [31:0] q_iright; + reg signed [31:0] q_irights; + reg [31:0] q_ileft; + reg [P64-1:0] q_qright; + reg signed [P64-1:0] q_qrights; + reg [P64-1:0] q_qleft; + reg [95:0] q_wright; + reg signed [95:0] q_wrights; + reg [95:0] q_wleft; - reg [31:0] w_iright; - reg signed [31:0] w_irights; - reg [31:0] w_ileft; - reg [P64-1:0] w_qright; - reg signed [P64-1:0] w_qrights; - reg [P64-1:0] w_qleft; - reg [95:0] w_wright; - reg signed [95:0] w_wrights; - reg [95:0] w_wleft; + reg [31:0] w_iright; + reg signed [31:0] w_irights; + reg [31:0] w_ileft; + reg [P64-1:0] w_qright; + reg signed [P64-1:0] w_qrights; + reg [P64-1:0] w_qleft; + reg [95:0] w_wright; + reg signed [95:0] w_wrights; + reg [95:0] w_wleft; - reg [31:0] iamt; - reg [63:0] qamt; - reg [95:0] wamt; + reg [31:0] iamt; + reg [63:0] qamt; + reg [95:0] wamt; - output reg [95:0] c_wright_32; - output reg [95:0] c_wleft_32; + output reg [95:0] c_wright_32; + output reg [95:0] c_wleft_32; - reg [63:0] crc = 64'h5aef0c8d_d70a4497; - wire [95:0] rand_96 = {crc[63:32] | crc[31:0], crc}; + reg [63:0] crc = 64'h5aef0c8d_d70a4497; + wire [95:0] rand_96 = {crc[63:32] | crc[31:0], crc}; - assign ign = {31'h0, clk} >>> 4'bx; // bug760 - assign ign2 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] << (0 <<< iamt[5:2])}; // bug1174 - assign ign3 = {iamt[1:0] >> {22{iamt[5:2]}}, - iamt[1:0] >> {11{iamt[5:2]}}, - $signed(iamt[1:0]) >>> {22{iamt[5:2]}}, - $signed(iamt[1:0]) >>> {11{iamt[5:2]}}, - iamt[1:0] << {22{iamt[5:2]}}, - iamt[1:0] << {11{iamt[5:2]}}}; + assign ign = {31'h0, clk} >>> 4'bx; // bug760 + assign ign2 = {iamt[1:0] >> {22{iamt[5:2]}}, iamt[1:0] << (0 <<< iamt[5:2])}; // bug1174 + assign ign3 = {iamt[1:0] >> {22{iamt[5:2]}}, + iamt[1:0] >> {11{iamt[5:2]}}, + $signed(iamt[1:0]) >>> {22{iamt[5:2]}}, + $signed(iamt[1:0]) >>> {11{iamt[5:2]}}, + iamt[1:0] << {22{iamt[5:2]}}, + iamt[1:0] << {11{iamt[5:2]}}}; - wire [95:0] wamtt = {iamt,iamt,iamt}; - output wire [95:0] ign4; - assign ign4 = wamtt >> {11{iamt[5:2]}}; - output wire signed [95:0] ign4s; - assign ign4s = $signed(wamtt) >>> {11{iamt[5:2]}}; + wire [95:0] wamtt = {iamt,iamt,iamt}; + output wire [95:0] ign4; + assign ign4 = wamtt >> {11{iamt[5:2]}}; + output wire signed [95:0] ign4s; + assign ign4s = $signed(wamtt) >>> {11{iamt[5:2]}}; - always @* begin - iright = 32'h819b018a >> iamt; - irights = 32'sh819b018a >>> signed'(iamt); - ileft = 32'h819b018a << iamt; - qright = 64'hf784bf8f_12734089 >> iamt; - qrights = 64'shf784bf8f_12734089 >>> signed'(iamt); - qleft = 64'hf784bf8f_12734089 << iamt; - wright = 96'hf784bf8f_12734089_190abe48 >> iamt; - wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(iamt); - wleft = 96'hf784bf8f_12734089_190abe48 << iamt; + always @* begin + iright = 32'h819b018a >> iamt; + irights = 32'sh819b018a >>> signed'(iamt); + ileft = 32'h819b018a << iamt; + qright = 64'hf784bf8f_12734089 >> iamt; + qrights = 64'shf784bf8f_12734089 >>> signed'(iamt); + qleft = 64'hf784bf8f_12734089 << iamt; + wright = 96'hf784bf8f_12734089_190abe48 >> iamt; + wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(iamt); + wleft = 96'hf784bf8f_12734089_190abe48 << iamt; - q_iright = 32'h819b018a >> qamt; - q_irights = 32'sh819b018a >>> signed'(qamt); - q_ileft = 32'h819b018a << qamt; - q_qright = 64'hf784bf8f_12734089 >> qamt; - q_qrights = 64'shf784bf8f_12734089 >>> signed'(qamt); - q_qleft = 64'hf784bf8f_12734089 << qamt; - q_wright = 96'hf784bf8f_12734089_190abe48 >> qamt; - q_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(qamt); - q_wleft = 96'hf784bf8f_12734089_190abe48 << qamt; + q_iright = 32'h819b018a >> qamt; + q_irights = 32'sh819b018a >>> signed'(qamt); + q_ileft = 32'h819b018a << qamt; + q_qright = 64'hf784bf8f_12734089 >> qamt; + q_qrights = 64'shf784bf8f_12734089 >>> signed'(qamt); + q_qleft = 64'hf784bf8f_12734089 << qamt; + q_wright = 96'hf784bf8f_12734089_190abe48 >> qamt; + q_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(qamt); + q_wleft = 96'hf784bf8f_12734089_190abe48 << qamt; - w_iright = 32'h819b018a >> wamt; - w_irights = 32'sh819b018a >>> signed'(wamt); - w_ileft = 32'h819b018a << wamt; - w_qright = 64'hf784bf8f_12734089 >> wamt; - w_qrights = 64'shf784bf8f_12734089 >>> signed'(wamt); - w_qleft = 64'hf784bf8f_12734089 << wamt; - w_wright = 96'hf784bf8f_12734089_190abe48 >> wamt; - w_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(wamt); - w_wleft = 96'hf784bf8f_12734089_190abe48 << wamt; + w_iright = 32'h819b018a >> wamt; + w_irights = 32'sh819b018a >>> signed'(wamt); + w_ileft = 32'h819b018a << wamt; + w_qright = 64'hf784bf8f_12734089 >> wamt; + w_qrights = 64'shf784bf8f_12734089 >>> signed'(wamt); + w_qleft = 64'hf784bf8f_12734089 << wamt; + w_wright = 96'hf784bf8f_12734089_190abe48 >> wamt; + w_wrights = 96'shf784bf8f_12734089_190abe48 >>> signed'(wamt); + w_wleft = 96'hf784bf8f_12734089_190abe48 << wamt; - c_wright_32 = rand_96 >> 32; - c_wleft_32 = rand_96 << 32; - end + c_wright_32 = rand_96 >> 32; + c_wleft_32 = rand_96 << 32; + end - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; `ifdef TEST_VERBOSE - $write("%d %x %x %x %x %x %x\n", cyc, ileft, iright, qleft, qright, wleft, wright); + $write("%d %x %x %x %x %x %x\n", cyc, ileft, iright, qleft, qright, wleft, wright); `endif - if (cyc==1) begin - iamt <= 0; - qamt <= 0; - wamt <= 0; - if (P64 != 64) $stop; - if (5'b10110>>2 != 5'b00101) $stop; - if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness - if (5'b10110<<2 != 5'b11000) $stop; - if (5'b10110<<<2 != 5'b11000) $stop; - if (5'sb10110>>2 != 5'sb00101) $stop; - if (5'sb10110>>>2 != 5'sb11101) $stop; - if (5'sb10110<<2 != 5'sb11000) $stop; - if (5'sb10110<<<2 != 5'sb11000) $stop; - // Allow >64 bit shifts if the shift amount is a constant - if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop; - end - if (cyc==2) begin - iamt <= 28; - qamt <= 28; - wamt <= 28; - if (ileft != 32'h819b018a) $stop; - if (iright != 32'h819b018a) $stop; - if (irights != 32'h819b018a) $stop; - if (qleft != 64'hf784bf8f_12734089) $stop; - if (qright != 64'hf784bf8f_12734089) $stop; - if (qrights != 64'hf784bf8f_12734089) $stop; - if (wleft != 96'hf784bf8f12734089190abe48) $stop; - if (wright != 96'hf784bf8f12734089190abe48) $stop; - if (wrights != 96'hf784bf8f12734089190abe48) $stop; - end - if (cyc==3) begin - iamt <= 31; - qamt <= 31; - wamt <= 31; - if (ileft != 32'ha0000000) $stop; - if (iright != 32'h8) $stop; - if (irights != 32'hfffffff8) $stop; - if (qleft != 64'hf127340890000000) $stop; - if (qright != 64'h0000000f784bf8f1) $stop; - if (qrights != 64'hffffffff784bf8f1) $stop; - if (wleft != 96'hf12734089190abe480000000) $stop; - if (wright != 96'h0000000f784bf8f127340891) $stop; - if (wrights != 96'hffffffff784bf8f127340891) $stop; - end - if (cyc==4) begin - iamt <= 32; - qamt <= 32; - wamt <= 32; - if (ileft != 32'h0) $stop; - if (iright != 32'h1) $stop; - if (qleft != 64'h8939a04480000000) $stop; - if (qright != 64'h00000001ef097f1e) $stop; - end - if (cyc==5) begin - iamt <= 33; - qamt <= 33; - wamt <= 33; - if (ileft != 32'h0) $stop; - if (iright != 32'h0) $stop; - if (qleft != 64'h1273408900000000) $stop; - if (qright != 64'h00000000f784bf8f) $stop; - end - if (cyc==6) begin - iamt <= 64; - qamt <= 64; - wamt <= 64; - if (ileft != 32'h0) $stop; - if (iright != 32'h0) $stop; - if (qleft != 64'h24e6811200000000) $stop; - if (qright != 64'h000000007bc25fc7) $stop; - end - if (cyc==7) begin - iamt <= 128; - qamt <= 128; - wamt <= 128; - if (ileft != 32'h0) $stop; - if (iright != 32'h0) $stop; - if (qleft != 64'h0) $stop; - if (qright != 64'h0) $stop; - end - if (cyc==8) begin - iamt <= 100; - qamt <= {32'h10, 32'h0}; - wamt <= {32'h10, 64'h0}; - if (ileft != '0) $stop; - if (iright != '0) $stop; - if (irights != '1) $stop; - if (qleft != '0) $stop; - if (qright != '0) $stop; - if (qrights != '1) $stop; - if (wleft != '0) $stop; - if (wright != '0) $stop; - if (wrights != '1) $stop; - end - if (cyc==19) begin - $write("*-* All Finished *-*\n"); - $finish; - end - - // General rule to test all q's - if (cyc != 0) begin - if (ileft != q_ileft) $stop; - if (iright != q_iright) $stop; - if (irights != q_irights) $stop; - if (qleft != q_qleft) $stop; - if (qright != q_qright) $stop; - if (qrights != q_qrights) $stop; - if (wleft != q_wleft) $stop; - if (wright != q_wright) $stop; - if (wrights != q_wrights) $stop; - - if (ileft != w_ileft) $stop; - if (iright != w_iright) $stop; - if (irights != w_irights) $stop; - if (qleft != w_qleft) $stop; - if (qright != w_qright) $stop; - if (qrights != w_qrights) $stop; - if (wleft != w_wleft) $stop; - if (wright != w_wright) $stop; - if (wrights != w_wrights) $stop; - - if (c_wright_32 << 32 != {rand_96[95:32], 32'd0}) $stop; - if (c_wleft_32 >> 32 != {32'd0, rand_96[63:0]}) $stop; - end + if (cyc==1) begin + iamt <= 0; + qamt <= 0; + wamt <= 0; + if (P64 != 64) $stop; + if (5'b10110>>2 != 5'b00101) $stop; + if (5'b10110>>>2 != 5'b00101) $stop; // Note it cares about sign-ness + if (5'b10110<<2 != 5'b11000) $stop; + if (5'b10110<<<2 != 5'b11000) $stop; + if (5'sb10110>>2 != 5'sb00101) $stop; + if (5'sb10110>>>2 != 5'sb11101) $stop; + if (5'sb10110<<2 != 5'sb11000) $stop; + if (5'sb10110<<<2 != 5'sb11000) $stop; + // Allow >64 bit shifts if the shift amount is a constant + if ((64'sh458c2de282e30f8b >> 68'sh4) !== 64'sh0458c2de282e30f8) $stop; end - end + if (cyc==2) begin + iamt <= 28; + qamt <= 28; + wamt <= 28; + if (ileft != 32'h819b018a) $stop; + if (iright != 32'h819b018a) $stop; + if (irights != 32'h819b018a) $stop; + if (qleft != 64'hf784bf8f_12734089) $stop; + if (qright != 64'hf784bf8f_12734089) $stop; + if (qrights != 64'hf784bf8f_12734089) $stop; + if (wleft != 96'hf784bf8f12734089190abe48) $stop; + if (wright != 96'hf784bf8f12734089190abe48) $stop; + if (wrights != 96'hf784bf8f12734089190abe48) $stop; + end + if (cyc==3) begin + iamt <= 31; + qamt <= 31; + wamt <= 31; + if (ileft != 32'ha0000000) $stop; + if (iright != 32'h8) $stop; + if (irights != 32'hfffffff8) $stop; + if (qleft != 64'hf127340890000000) $stop; + if (qright != 64'h0000000f784bf8f1) $stop; + if (qrights != 64'hffffffff784bf8f1) $stop; + if (wleft != 96'hf12734089190abe480000000) $stop; + if (wright != 96'h0000000f784bf8f127340891) $stop; + if (wrights != 96'hffffffff784bf8f127340891) $stop; + end + if (cyc==4) begin + iamt <= 32; + qamt <= 32; + wamt <= 32; + if (ileft != 32'h0) $stop; + if (iright != 32'h1) $stop; + if (qleft != 64'h8939a04480000000) $stop; + if (qright != 64'h00000001ef097f1e) $stop; + end + if (cyc==5) begin + iamt <= 33; + qamt <= 33; + wamt <= 33; + if (ileft != 32'h0) $stop; + if (iright != 32'h0) $stop; + if (qleft != 64'h1273408900000000) $stop; + if (qright != 64'h00000000f784bf8f) $stop; + end + if (cyc==6) begin + iamt <= 64; + qamt <= 64; + wamt <= 64; + if (ileft != 32'h0) $stop; + if (iright != 32'h0) $stop; + if (qleft != 64'h24e6811200000000) $stop; + if (qright != 64'h000000007bc25fc7) $stop; + end + if (cyc==7) begin + iamt <= 128; + qamt <= 128; + wamt <= 128; + if (ileft != 32'h0) $stop; + if (iright != 32'h0) $stop; + if (qleft != 64'h0) $stop; + if (qright != 64'h0) $stop; + end + if (cyc==8) begin + iamt <= 100; + qamt <= {32'h10, 32'h0}; + wamt <= {32'h10, 64'h0}; + if (ileft != '0) $stop; + if (iright != '0) $stop; + if (irights != '1) $stop; + if (qleft != '0) $stop; + if (qright != '0) $stop; + if (qrights != '1) $stop; + if (wleft != '0) $stop; + if (wright != '0) $stop; + if (wrights != '1) $stop; + end + if (cyc==19) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + // General rule to test all q's + if (cyc != 0) begin + if (ileft != q_ileft) $stop; + if (iright != q_iright) $stop; + if (irights != q_irights) $stop; + if (qleft != q_qleft) $stop; + if (qright != q_qright) $stop; + if (qrights != q_qrights) $stop; + if (wleft != q_wleft) $stop; + if (wright != q_wright) $stop; + if (wrights != q_wrights) $stop; + + if (ileft != w_ileft) $stop; + if (iright != w_iright) $stop; + if (irights != w_irights) $stop; + if (qleft != w_qleft) $stop; + if (qright != w_qright) $stop; + if (qrights != w_qrights) $stop; + if (wleft != w_wleft) $stop; + if (wright != w_wright) $stop; + if (wrights != w_wrights) $stop; + + if (c_wright_32 << 32 != {rand_96[95:32], 32'd0}) $stop; + if (c_wleft_32 >> 32 != {32'd0, rand_96[63:0]}) $stop; + end + end + end endmodule diff --git a/test_regress/t/t_mod_topmodule.v b/test_regress/t/t_mod_topmodule.v index e14726373..235011495 100644 --- a/test_regress/t/t_mod_topmodule.v +++ b/test_regress/t/t_mod_topmodule.v @@ -8,27 +8,24 @@ // SPDX-FileCopyrightText: 2021 Dan Petrisko // SPDX-License-Identifier: CC0-1.0 -module top(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module top ( + input clk +); - always_ff @(posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish(); - end + always_ff @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish(); + end endmodule -module faketop(/*AUTOARG*/ - ); +module faketop; - top top(); + top top (); - // Stop immediately if this module is instantiated + // Stop immediately if this module is instantiated initial begin $stop(); - end + end endmodule diff --git a/test_regress/t/t_preproc_inc_inc_bad.vh b/test_regress/t/t_preproc_inc_inc_bad.vh index e854c817a..0cd401d5e 100644 --- a/test_regress/t/t_preproc_inc_inc_bad.vh +++ b/test_regress/t/t_preproc_inc_inc_bad.vh @@ -6,6 +6,6 @@ module xx; - xx // intentional error + xx // intentional error endmodule diff --git a/test_regress/t/t_property_pexpr_parse_unsup.out b/test_regress/t/t_property_pexpr_parse_unsup.out index 8d3609b07..976b9669f 100644 --- a/test_regress/t/t_property_pexpr_parse_unsup.out +++ b/test_regress/t/t_property_pexpr_parse_unsup.out @@ -1,50 +1,50 @@ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:26:13: Unsupported: strong (in property expression) - 26 | strong(a); - | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:30:11: Unsupported: weak (in property expression) - 30 | weak(a); +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:24:11: Unsupported: strong (in property expression) + 24 | strong(a); | ^ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:58:7: Unsupported: nexttime (in property expression) - 58 | nexttime a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:62:7: Unsupported: nexttime[] (in property expression) - 62 | nexttime [2] a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:66:7: Unsupported: s_nexttime (in property expression) - 66 | s_nexttime a; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:70:7: Unsupported: s_nexttime[] (in property expression) - 70 | s_nexttime [2] a; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:74:7: Unsupported: nexttime (in property expression) - 74 | nexttime always a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:78:7: Unsupported: nexttime[] (in property expression) - 78 | nexttime [2] always a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:82:7: Unsupported: nexttime[] (in property expression) - 82 | nexttime [2] always a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:86:7: Unsupported: nexttime (in property expression) - 86 | nexttime s_eventually a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:90:16: Unsupported: s_eventually[] (in property expression) - 90 | nexttime s_eventually [2:$] always a; - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:90:7: Unsupported: nexttime (in property expression) - 90 | nexttime s_eventually [2:$] always a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:109:27: Unsupported: property argument data type - 109 | property p_arg_propery(property inprop); - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:112:27: Unsupported: sequence argument data type - 112 | property p_arg_seqence(sequence inseq); - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:117:7: Unsupported: property case expression - 117 | case (a) endcase - | ^~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:120:7: Unsupported: property case expression - 120 | case (a) default: b; endcase - | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:28:9: Unsupported: weak (in property expression) + 28 | weak(a); + | ^ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:56:5: Unsupported: nexttime (in property expression) + 56 | nexttime a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:60:5: Unsupported: nexttime[] (in property expression) + 60 | nexttime [2] a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:64:5: Unsupported: s_nexttime (in property expression) + 64 | s_nexttime a; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:68:5: Unsupported: s_nexttime[] (in property expression) + 68 | s_nexttime [2] a; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:72:5: Unsupported: nexttime (in property expression) + 72 | nexttime always a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:76:5: Unsupported: nexttime[] (in property expression) + 76 | nexttime [2] always a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:80:5: Unsupported: nexttime[] (in property expression) + 80 | nexttime [2] always a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:84:5: Unsupported: nexttime (in property expression) + 84 | nexttime s_eventually a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:88:14: Unsupported: s_eventually[] (in property expression) + 88 | nexttime s_eventually [2:$] always a; + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:88:5: Unsupported: nexttime (in property expression) + 88 | nexttime s_eventually [2:$] always a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:107:26: Unsupported: property argument data type + 107 | property p_arg_propery(property inprop); + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:110:26: Unsupported: sequence argument data type + 110 | property p_arg_seqence(sequence inseq); + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:115:5: Unsupported: property case expression + 115 | case (a) endcase + | ^~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:118:5: Unsupported: property case expression + 118 | case (a) default: b; endcase + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_property_pexpr_unsup.out b/test_regress/t/t_property_pexpr_unsup.out index dc3914b8f..c7d9bb601 100644 --- a/test_regress/t/t_property_pexpr_unsup.out +++ b/test_regress/t/t_property_pexpr_unsup.out @@ -1,26 +1,26 @@ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:130:22: Unsupported: Unclocked assertion +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:128:21: Unsupported: Unclocked assertion : ... note: In instance 't' - 130 | assert property ((s_eventually a) implies (s_eventually a)); - | ^~~~~~~~~~~~ + 128 | assert property ((s_eventually a) implies (s_eventually a)); + | ^~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:130:47: Unsupported: Unclocked assertion +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:128:46: Unsupported: Unclocked assertion : ... note: In instance 't' - 130 | assert property ((s_eventually a) implies (s_eventually a)); - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:130:4: Unsupported: Unclocked assertion + 128 | assert property ((s_eventually a) implies (s_eventually a)); + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:128:3: Unsupported: Unclocked assertion : ... note: In instance 't' - 130 | assert property ((s_eventually a) implies (s_eventually a)); - | ^~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:132:22: Unsupported: Unclocked assertion + 128 | assert property ((s_eventually a) implies (s_eventually a)); + | ^~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:130:21: Unsupported: Unclocked assertion : ... note: In instance 't' - 132 | assert property ((s_eventually a) iff (s_eventually a)); - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:132:43: Unsupported: Unclocked assertion + 130 | assert property ((s_eventually a) iff (s_eventually a)); + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:130:42: Unsupported: Unclocked assertion : ... note: In instance 't' - 132 | assert property ((s_eventually a) iff (s_eventually a)); - | ^~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:132:4: Unsupported: Unclocked assertion + 130 | assert property ((s_eventually a) iff (s_eventually a)); + | ^~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_property_pexpr_unsup.v:130:3: Unsupported: Unclocked assertion : ... note: In instance 't' - 132 | assert property ((s_eventually a) iff (s_eventually a)); - | ^~~~~~ + 130 | assert property ((s_eventually a) iff (s_eventually a)); + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_property_pexpr_unsup.v b/test_regress/t/t_property_pexpr_unsup.v index 8b9bb9ade..a582241b7 100644 --- a/test_regress/t/t_property_pexpr_unsup.v +++ b/test_regress/t/t_property_pexpr_unsup.v @@ -4,137 +4,135 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - bit a; - bit b; - bit c; - int cyc = 0; + bit a; + bit b; + bit c; + int cyc = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - end + always @(posedge clk) begin + cyc <= cyc + 1; + end `ifdef PARSING_TIME - // NOTE this grammar hasn't been checked with other simulators, - // is here just to avoid uncovered code lines in the grammar. - property p_strong; - strong(a); - endproperty + // NOTE this grammar hasn't been checked with other simulators, + // is here just to avoid uncovered code lines in the grammar. + property p_strong; + strong(a); + endproperty - property p_weak; - weak(a); - endproperty + property p_weak; + weak(a); + endproperty - property p_until; - a until b; - endproperty + property p_until; + a until b; + endproperty - property p_suntil; - a s_until b; - endproperty + property p_suntil; + a s_until b; + endproperty - property p_untilwith; - a until_with b; - endproperty + property p_untilwith; + a until_with b; + endproperty - property p_suntilwith; - a s_until_with b; - endproperty + property p_suntilwith; + a s_until_with b; + endproperty - property p_poundminuspound1; - a #-# b; - endproperty + property p_poundminuspound1; + a #-# b; + endproperty - property p_poundeqpound; - a #=# b; - endproperty + property p_poundeqpound; + a #=# b; + endproperty - property p_nexttime; - nexttime a; - endproperty + property p_nexttime; + nexttime a; + endproperty - property p_nexttime2; - nexttime [2] a; - endproperty + property p_nexttime2; + nexttime [2] a; + endproperty - property p_snexttime; - s_nexttime a; - endproperty + property p_snexttime; + s_nexttime a; + endproperty - property p_snexttime2; - s_nexttime [2] a; - endproperty + property p_snexttime2; + s_nexttime [2] a; + endproperty - property p_nexttime_always; - nexttime always a; - endproperty + property p_nexttime_always; + nexttime always a; + endproperty - property p_nexttime_always2; - nexttime [2] always a; - endproperty + property p_nexttime_always2; + nexttime [2] always a; + endproperty - property p_nexttime_eventually2; - nexttime [2] always a; - endproperty + property p_nexttime_eventually2; + nexttime [2] always a; + endproperty - property p_nexttime_seventually; - nexttime s_eventually a; - endproperty + property p_nexttime_seventually; + nexttime s_eventually a; + endproperty - property p_nexttime_seventually2; - nexttime s_eventually [2:$] always a; - endproperty + property p_nexttime_seventually2; + nexttime s_eventually [2:$] always a; + endproperty - property p_accepton; - accept_on (a) b; - endproperty + property p_accepton; + accept_on (a) b; + endproperty - property p_syncaccepton; - sync_accept_on (a) b; - endproperty + property p_syncaccepton; + sync_accept_on (a) b; + endproperty - property p_rejecton; - reject_on (a) b; - endproperty + property p_rejecton; + reject_on (a) b; + endproperty - property p_syncrejecton; - sync_reject_on (a) b; - endproperty + property p_syncrejecton; + sync_reject_on (a) b; + endproperty - property p_arg_propery(property inprop); - inprop; - endproperty - property p_arg_seqence(sequence inseq); - inseq; - endproperty + property p_arg_propery(property inprop); + inprop; + endproperty + property p_arg_seqence(sequence inseq); + inseq; + endproperty - property p_case_1; - case (a) endcase - endproperty - property p_case_2; - case (a) default: b; endcase - endproperty - property p_if; - if (a) b - endproperty - property p_ifelse; - if (a) b else c - endproperty + property p_case_1; + case (a) endcase + endproperty + property p_case_2; + case (a) default: b; endcase + endproperty + property p_if; + if (a) b + endproperty + property p_ifelse; + if (a) b else c + endproperty `endif - assert property ((s_eventually a) implies (s_eventually a)); + assert property ((s_eventually a) implies (s_eventually a)); - assert property ((s_eventually a) iff (s_eventually a)); + assert property ((s_eventually a) iff (s_eventually a)); - always @(posedge clk) begin - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_property_s_eventually_iface.v b/test_regress/t/t_property_s_eventually_iface.v index f5df9e5ab..fa79e43cd 100644 --- a/test_regress/t/t_property_s_eventually_iface.v +++ b/test_regress/t/t_property_s_eventually_iface.v @@ -7,27 +7,29 @@ // s_eventually (strong eventually) inside an interface used to trigger an // internal error in V3Scope ("Can't locate varref scope"). -interface my_if(input logic clk); - logic a; - assert property (@(posedge clk) s_eventually a); +interface my_if ( + input logic clk +); + logic a; + assert property (@(posedge clk) s_eventually a); endinterface -module t(/*AUTOARG*/); - bit clk = 0; - initial forever #1 clk = ~clk; +module t ( /*AUTOARG*/); + bit clk = 0; + initial forever #1 clk = ~clk; - integer cyc = 0; + integer cyc = 0; - my_if u_if(.clk(clk)); + my_if u_if (.clk(clk)); - initial u_if.a = 0; + initial u_if.a = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - u_if.a <= (cyc >= 3); - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + u_if.a <= (cyc >= 3); + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_structu_dataType_assignment.v b/test_regress/t/t_structu_dataType_assignment.v index cae4c5c35..667c5f70c 100644 --- a/test_regress/t/t_structu_dataType_assignment.v +++ b/test_regress/t/t_structu_dataType_assignment.v @@ -66,122 +66,122 @@ module top(); HIJ_struct HIJ; initial begin - // struct ab - ab = '{0, 0}; //constant member by position - if (ab.a != 0) $stop; - if (ab.b != 0) $stop; + // struct ab + ab = '{0, 0}; //constant member by position + if (ab.a != 0) $stop; + if (ab.b != 0) $stop; - ab = '{default: 0}; //default value - if (ab.a != 0) $stop; - if (ab.b != 0) $stop; + ab = '{default: 0}; //default value + if (ab.a != 0) $stop; + if (ab.b != 0) $stop; - ab = '{int: 1, shortint: 0}; //data type and default value - if (ab.a != 1) $stop; - if (ab.b != 0) $stop; + ab = '{int: 1, shortint: 0}; //data type and default value + if (ab.a != 1) $stop; + if (ab.b != 0) $stop; - abkey[1:0] = '{'{a:1, b:2}, '{int:2, shortint:3}}; // member: value & data_type: value - if (abkey[1].a != 1) $stop; - if (abkey[1].b != 2) $stop; - if (abkey[0].a != 2) $stop; - if (abkey[0].b != 3) $stop; + abkey[1:0] = '{'{a:1, b:2}, '{int:2, shortint:3}}; // member: value & data_type: value + if (abkey[1].a != 1) $stop; + if (abkey[1].b != 2) $stop; + if (abkey[0].a != 2) $stop; + if (abkey[0].b != 3) $stop; - // struct st - st = '{1, 2+k}; //constant member by position - if (st.x != 1) $stop; - if (st.y != 2+k) $stop; + // struct st + st = '{1, 2+k}; //constant member by position + if (st.x != 1) $stop; + if (st.y != 2+k) $stop; - st = '{x:2, y:3+k}; //member: value - if (st.x != 2) $stop; - if (st.y != 3+k) $stop; + st = '{x:2, y:3+k}; //member: value + if (st.x != 2) $stop; + if (st.y != 3+k) $stop; - st = '{int:2, int:3+k}; //data_type: value override - if (st.x != 3+k) $stop; - if (st.y != 3+k) $stop; + st = '{int:2, int:3+k}; //data_type: value override + if (st.x != 3+k) $stop; + if (st.y != 3+k) $stop; - // struct sa - sa = '{default:'1}; - if (sa.a != '1) $stop; - if (sa.b != '1) $stop; - if (sa.c != '1) $stop; - if (sa.s != '1) $stop; + // struct sa + sa = '{default:'1}; + if (sa.a != '1) $stop; + if (sa.b != '1) $stop; + if (sa.c != '1) $stop; + if (sa.s != '1) $stop; - sa = '{default:'1, int: 5}; - if (sa.a != '1) $stop; - if (sa.b != '1) $stop; - if (sa.c != '1) $stop; - if (sa.s != 5) $stop; + sa = '{default:'1, int: 5}; + if (sa.a != '1) $stop; + if (sa.b != '1) $stop; + if (sa.c != '1) $stop; + if (sa.s != 5) $stop; - sa = '{default:'1, int: 5, b: 0}; - if (sa.a != '1) $stop; - if (sa.b != 0) $stop; - if (sa.c != '1) $stop; - if (sa.s != 5) $stop; + sa = '{default:'1, int: 5, b: 0}; + if (sa.a != '1) $stop; + if (sa.b != 0) $stop; + if (sa.c != '1) $stop; + if (sa.s != 5) $stop; - // struct DEF - DEF = '{A:1, BC1:'{B:2, C:3}, BC2:'{B:4,C:5}}; - if (DEF.A != 1) $stop; - if (DEF.BC1.B != 2) $stop; - if (DEF.BC1.C != 3) $stop; - if (DEF.BC2.B != 4) $stop; - if (DEF.BC2.C != 5) $stop; + // struct DEF + DEF = '{A:1, BC1:'{B:2, C:3}, BC2:'{B:4,C:5}}; + if (DEF.A != 1) $stop; + if (DEF.BC1.B != 2) $stop; + if (DEF.BC1.C != 3) $stop; + if (DEF.BC2.B != 4) $stop; + if (DEF.BC2.C != 5) $stop; - DEF = '{int:0, BC1:'{int:10}, BC2:'{default:5}}; - if (DEF.A != 0) $stop; - if (DEF.BC1.B != 10) $stop; - if (DEF.BC1.C != 10) $stop; - if (DEF.BC2.B != 5) $stop; - if (DEF.BC2.C != 5) $stop; + DEF = '{int:0, BC1:'{int:10}, BC2:'{default:5}}; + if (DEF.A != 0) $stop; + if (DEF.BC1.B != 10) $stop; + if (DEF.BC1.C != 10) $stop; + if (DEF.BC2.B != 5) $stop; + if (DEF.BC2.C != 5) $stop; - DEF = '{default:1, BC1:'{int:10}, BC2:'{default:5}}; - if (DEF.A != 1) $stop; - if (DEF.BC1.B != 10) $stop; - if (DEF.BC1.C != 10) $stop; - if (DEF.BC2.B != 5) $stop; - if (DEF.BC2.C != 5) $stop; + DEF = '{default:1, BC1:'{int:10}, BC2:'{default:5}}; + if (DEF.A != 1) $stop; + if (DEF.BC1.B != 10) $stop; + if (DEF.BC1.C != 10) $stop; + if (DEF.BC2.B != 5) $stop; + if (DEF.BC2.C != 5) $stop; - DEF = '{default:10}; - if (DEF.A != 10) $stop; - if (DEF.BC1.B != 10) $stop; - if (DEF.BC1.C != 10) $stop; - if (DEF.BC2.B != 10) $stop; - if (DEF.BC2.C != 10) $stop; + DEF = '{default:10}; + if (DEF.A != 10) $stop; + if (DEF.BC1.B != 10) $stop; + if (DEF.BC1.C != 10) $stop; + if (DEF.BC2.B != 10) $stop; + if (DEF.BC2.C != 10) $stop; - DEF = '{int:10}; - if (DEF.A != 10) $stop; - if (DEF.BC1.B != 10) $stop; - if (DEF.BC1.C != 10) $stop; - if (DEF.BC2.B != 10) $stop; - if (DEF.BC2.C != 10) $stop; + DEF = '{int:10}; + if (DEF.A != 10) $stop; + if (DEF.BC1.B != 10) $stop; + if (DEF.BC1.C != 10) $stop; + if (DEF.BC2.B != 10) $stop; + if (DEF.BC2.C != 10) $stop; - // struct HIJ - HIJ = '{int:10, default: 5}; - if (HIJ.A != 10) $stop; - if (HIJ.BC1.B != 10) $stop; - if (HIJ.BC1.C != 10) $stop; - if (HIJ.BC1.DE1.D != 10) $stop; - if (HIJ.BC1.DE1.E != 10) $stop; - if (HIJ.BC1.DE1.FG1.F != 10) $stop; - if (HIJ.BC1.DE1.FG1.G != 5) $stop; + // struct HIJ + HIJ = '{int:10, default: 5}; + if (HIJ.A != 10) $stop; + if (HIJ.BC1.B != 10) $stop; + if (HIJ.BC1.C != 10) $stop; + if (HIJ.BC1.DE1.D != 10) $stop; + if (HIJ.BC1.DE1.E != 10) $stop; + if (HIJ.BC1.DE1.FG1.F != 10) $stop; + if (HIJ.BC1.DE1.FG1.G != 5) $stop; - HIJ = '{shortint:10, default: 5}; - if (HIJ.A != 5) $stop; - if (HIJ.BC1.B != 5) $stop; - if (HIJ.BC1.C != 5) $stop; - if (HIJ.BC1.DE1.D != 5) $stop; - if (HIJ.BC1.DE1.E != 5) $stop; - if (HIJ.BC1.DE1.FG1.F != 5) $stop; - if (HIJ.BC1.DE1.FG1.G != 10) $stop; + HIJ = '{shortint:10, default: 5}; + if (HIJ.A != 5) $stop; + if (HIJ.BC1.B != 5) $stop; + if (HIJ.BC1.C != 5) $stop; + if (HIJ.BC1.DE1.D != 5) $stop; + if (HIJ.BC1.DE1.E != 5) $stop; + if (HIJ.BC1.DE1.FG1.F != 5) $stop; + if (HIJ.BC1.DE1.FG1.G != 10) $stop; - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end endmodule diff --git a/test_regress/t/t_vlt_warn_file_bad_b.vh b/test_regress/t/t_vlt_warn_file_bad_b.vh index f97aad506..e20daea9a 100644 --- a/test_regress/t/t_vlt_warn_file_bad_b.vh +++ b/test_regress/t/t_vlt_warn_file_bad_b.vh @@ -5,5 +5,5 @@ // SPDX-License-Identifier: CC0-1.0 module sub; - int warn_sub = 64'h1; + int warn_sub = 64'h1; endmodule