diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS
index 27974bf80..70f80c34a 100644
--- a/docs/CONTRIBUTORS
+++ b/docs/CONTRIBUTORS
@@ -14,6 +14,7 @@ Ameya Vikram Singh
 Andreas Kuster
 Andrei Kostovski
 Andrew Nolte
+Anthony Donlon
 Arkadiusz Kozdra
 Aylon Chaim Porat
 Cameron Kirk
diff --git a/src/verilog.y b/src/verilog.y
index 0b8dd10e5..b83e8ce1f 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -5863,6 +5863,7 @@ property_declarationFront<nodeFTaskp>:  // IEEE: part of property_declaration
 
 property_port_listE<nodep>:  // IEEE: [ ( [ property_port_list ] ) ]
                 /* empty */                       { $$ = nullptr; }
+        |       '(' ')'                           { $$ = nullptr; }
         |       '(' property_port_list ')'        { $$ = $2; }
         ;
 
diff --git a/test_regress/t/t_assert_named_property.v b/test_regress/t/t_assert_named_property.v
index 36e622825..7fed4f620 100644
--- a/test_regress/t/t_assert_named_property.v
+++ b/test_regress/t/t_assert_named_property.v
@@ -60,12 +60,19 @@ module t (/*AUTOARG*/
    logic out = 1;
 
     property prop_a;
-        @(posedge clk) disable iff (cyc <= 10) out;
-    endproperty
+        @(posedge clk) disable iff (cyc <= 1) out;
+    endproperty : prop_a
+
+    property prop_b();
+        @(posedge clk) disable iff (cyc <= 1) out;
+    endproperty : prop_b
 
    assert property(disable iff (cyc < 5) check_if_gt_5(cyc + 1));
    assert property(@(posedge clk) pass_assertion(cyc));
    assert property (prop_a) else $error($sformatf("property check failed :assert: (False)"));
+   assert property (prop_a()) else $error($sformatf("property check failed :assert: (False)"));
+   assert property (prop_b) else $error($sformatf("property check failed :assert: (False)"));
+   assert property (prop_b()) else $error($sformatf("property check failed :assert: (False)"));
 
    always @(posedge clk) begin
       if (expected_fails == 2) begin