From 947683ba2a1f3ee1f40fea6cd193d38764112b08 Mon Sep 17 00:00:00 2001 From: wsxarcher Date: Tue, 24 Mar 2026 23:22:24 +0100 Subject: [PATCH] Add fst/saif test --- .../t/t_trace_dumpvars_level_scope_fst.out | 31 +++++ .../t/t_trace_dumpvars_level_scope_fst.py | 15 +++ .../t/t_trace_dumpvars_level_scope_saif.out | 119 ++++++++++++++++++ .../t/t_trace_dumpvars_level_scope_saif.py | 15 +++ test_regress/t/trace_dumpvars_common.py | 45 +++++-- 5 files changed, 212 insertions(+), 13 deletions(-) create mode 100644 test_regress/t/t_trace_dumpvars_level_scope_fst.out create mode 100644 test_regress/t/t_trace_dumpvars_level_scope_fst.py create mode 100644 test_regress/t/t_trace_dumpvars_level_scope_saif.out create mode 100644 test_regress/t/t_trace_dumpvars_level_scope_saif.py diff --git a/test_regress/t/t_trace_dumpvars_level_scope_fst.out b/test_regress/t/t_trace_dumpvars_level_scope_fst.out new file mode 100644 index 000000000..f74d6bd3e --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level_scope_fst.out @@ -0,0 +1,31 @@ +$date +Tue Mar 24 23:18:44 2026 + +$end +$version +Generated by VerilatedFst +$end +$timescale +1ps +$end + $scope module $rootio $end + $upscope $end + $scope module t $end + $scope module sub_a $end + $var parameter 32 ! ADD [31:0] $end + $var wire 32 " cyc [31:0] $end + $var int 32 # value [31:0] $end + $scope module deep_i $end + $upscope $end + $upscope $end + $scope module sub_b $end + $scope module deep_i $end + $upscope $end + $upscope $end + $upscope $end +$enddefinitions $end +#0 +$dumpvars +b00000000000000000000000000001010 # +b00000000000000000000000000000000 " +b00000000000000000000000000001010 ! diff --git a/test_regress/t/t_trace_dumpvars_level_scope_fst.py b/test_regress/t/t_trace_dumpvars_level_scope_fst.py new file mode 100644 index 000000000..96746adc4 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level_scope_fst.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_dumpvars_common + +test.scenarios('vlt') + +trace_dumpvars_common.run(test) diff --git a/test_regress/t/t_trace_dumpvars_level_scope_saif.out b/test_regress/t/t_trace_dumpvars_level_scope_saif.out new file mode 100644 index 000000000..c7d8c321b --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level_scope_saif.out @@ -0,0 +1,119 @@ +// Generated by verilated_saif +(SAIFILE +(SAIFVERSION "2.0") +(DIRECTION "backward") +(PROGRAM_NAME "Verilator") +(DIVIDER / ) +(TIMESCALE 1ps) +(DURATION 0) + (INSTANCE $rootio + ) + (INSTANCE t + (INSTANCE sub_a + (NET + (ADD\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) + (ADD\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) + (ADD\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (ADD\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (cyc\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[0\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[1\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) + (value\[2\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[3\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 1)) + (value\[4\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[5\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[6\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[7\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[8\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[9\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[10\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[11\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[12\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[13\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[14\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[15\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[16\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[17\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[18\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[19\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[20\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[21\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[22\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[23\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[24\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[25\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[26\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[27\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[28\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[29\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[30\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + (value\[31\] (T0 0) (T1 0) (TZ 0) (TX 0) (TB 0) (TC 0)) + ) + (INSTANCE deep_i + ) + ) + (INSTANCE sub_b + (INSTANCE deep_i + ) + ) + ) +) diff --git a/test_regress/t/t_trace_dumpvars_level_scope_saif.py b/test_regress/t/t_trace_dumpvars_level_scope_saif.py new file mode 100644 index 000000000..96746adc4 --- /dev/null +++ b/test_regress/t/t_trace_dumpvars_level_scope_saif.py @@ -0,0 +1,15 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap +import trace_dumpvars_common + +test.scenarios('vlt') + +trace_dumpvars_common.run(test) diff --git a/test_regress/t/trace_dumpvars_common.py b/test_regress/t/trace_dumpvars_common.py index 6bb3782ad..fe4bf2587 100644 --- a/test_regress/t/trace_dumpvars_common.py +++ b/test_regress/t/trace_dumpvars_common.py @@ -68,6 +68,16 @@ _DEFINE_ALIASES = { "task2_no_inl": "task2", } +_ALT_TRACE_FORMATS = {"fst", "saif"} + + +def _split_format(case): + """Split case into (base_case, trace_format).""" + for fmt in _ALT_TRACE_FORMATS: + if case.endswith("_" + fmt): + return case[:-(len(fmt) + 1)], fmt + return case, "vcd" + def _case_name(test): name = os.path.splitext(os.path.basename(test.py_filename))[0] @@ -85,14 +95,15 @@ def _define_name(case): return f"+define+TRACE_DUMPVARS_CASE_{token}" -def _compile_flags(case): +def _compile_flags(case, fmt="vcd"): + trace_flag = f"--trace-{fmt}" flags = ["--top-module", "t", _define_name(case)] if case == "add_module": - flags = ["--binary", "--timing", "--trace-vcd", *flags] + flags = ["--binary", "--timing", trace_flag, *flags] elif case in _CPPTOP_CASES: - flags = ["--cc", "--exe", "--trace-vcd", *flags, _SHARED_CPPTOP] + flags = ["--cc", "--exe", trace_flag, *flags, _SHARED_CPPTOP] else: - flags = ["--binary", "--trace-vcd", *flags] + flags = ["--binary", trace_flag, *flags] if case in _STRUCT_TRACE_CASES: flags.append("--trace-structs") @@ -107,42 +118,50 @@ def _has_golden_trace(test): def run(test): case = _case_name(test) - if case == "top": + base_case, fmt = _split_format(case) + + if base_case == "top": test.passes() return test.top_filename = _SHARED_TOP - compile_kwargs = {"verilator_flags2": _compile_flags(case)} - if case in _CPPTOP_CASES: + compile_kwargs = {"verilator_flags2": _compile_flags(base_case, fmt)} + if base_case in _CPPTOP_CASES: compile_kwargs["make_main"] = False - if case in _COMPILE_FAIL_CASES: + if base_case in _COMPILE_FAIL_CASES: test.compile(fails=True, expect_filename=test.golden_filename, **compile_kwargs) test.passes() return test.compile(**compile_kwargs) - if case in _EXECUTE_FAIL_CASES: + if base_case in _EXECUTE_FAIL_CASES: test.execute(fails=True, expect_filename=test.golden_filename) test.passes() return execute_kwargs = {} - if case == "nonconst_scope": + if base_case == "nonconst_scope": execute_kwargs["all_run_flags"] = ['+LEVEL=0'] test.execute(**execute_kwargs) - if case == "add_module": + # For format variants, fall back to the base case's golden file + if fmt != "vcd" and not _has_golden_trace(test): + base_golden = os.path.join(test.t_dir, f"t_trace_dumpvars_{base_case}.out") + if os.path.exists(base_golden) and os.path.getsize(base_golden) > 0: + test.golden_filename = base_golden + + if base_case == "add_module": test.vcd_identical(test.obj_dir + "/simx0.vcd", test.t_dir + "/t_trace_dumpvars_add_module_0.out") test.vcd_identical(test.obj_dir + "/simx1.vcd", test.t_dir + "/t_trace_dumpvars_add_module_1.out") elif _has_golden_trace(test): - if case in _FILE_COMPARE_CASES: + if base_case in _FILE_COMPARE_CASES: test.files_identical(test.trace_filename, test.golden_filename) else: - test.vcd_identical(test.trace_filename, test.golden_filename) + test.trace_identical(test.trace_filename, test.golden_filename) test.passes()