From 93790c1dc6d7fc143223e7d67602655d8eefaf4a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 14 Mar 2014 20:36:47 -0400 Subject: [PATCH] Fix tracing of package variables and real arrays. --- Changes | 2 + src/V3EmitC.cpp | 8 +- src/V3TraceDecl.cpp | 6 +- test_regress/t/t_savable.v | 3 + test_regress/t/t_trace_complex.out | 208 +++++++++++-------- test_regress/t/t_trace_complex.v | 11 + test_regress/t/t_trace_complex_params.out | 208 +++++++++++-------- test_regress/t/t_trace_complex_structs.out | 226 ++++++++++++--------- 8 files changed, 388 insertions(+), 284 deletions(-) diff --git a/Changes b/Changes index fea9253c8..42f3f9244 100644 --- a/Changes +++ b/Changes @@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Documentation fixes, bug723. [Glen Gibb] +**** Fix tracing of package variables and real arrays. + * Verilator 3.856 2014-03-11 diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index c4d82341f..a826bffe8 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -2184,7 +2184,7 @@ class EmitCTrace : EmitCStmts { } void emitTraceInitOne(AstTraceDecl* nodep) { - if (nodep->isDouble()) { + if (nodep->dtypep()->basicp()->isDouble()) { puts("vcdp->declDouble"); } else if (nodep->isWide()) { puts("vcdp->declArray"); @@ -2204,7 +2204,7 @@ class EmitCTrace : EmitCStmts { } else { puts(",-1"); } - if (!nodep->isDouble() // When float/double no longer have widths this can go + if (!nodep->dtypep()->basicp()->isDouble() // When float/double no longer have widths this can go && nodep->bitRange().ranged()) { puts(","+cvtToStr(nodep->bitRange().left())+","+cvtToStr(nodep->bitRange().right())); } @@ -2216,7 +2216,7 @@ class EmitCTrace : EmitCStmts { string full = ((m_funcp->funcType() == AstCFuncType::TRACE_FULL || m_funcp->funcType() == AstCFuncType::TRACE_FULL_SUB) ? "full":"chg"); - if (nodep->isDouble()) { + if (nodep->dtypep()->basicp()->isDouble()) { puts("vcdp->"+full+"Double"); } else if (nodep->isWide() || emitTraceIsScBv(nodep) || emitTraceIsScBigUint(nodep)) { puts("vcdp->"+full+"Array"); @@ -2231,7 +2231,7 @@ class EmitCTrace : EmitCStmts { + ((arrayindex<0) ? 0 : (arrayindex*nodep->declp()->widthWords())))); puts(","); emitTraceValue(nodep, arrayindex); - if (!nodep->isDouble() // When float/double no longer have widths this can go + if (!nodep->dtypep()->basicp()->isDouble() // When float/double no longer have widths this can go && (nodep->declp()->bitRange().ranged() || emitTraceIsScBv(nodep) || emitTraceIsScBigUint(nodep))) { puts(","+cvtToStr(nodep->declp()->widthMin())); } diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp index 825705267..37a166280 100644 --- a/src/V3TraceDecl.cpp +++ b/src/V3TraceDecl.cpp @@ -279,7 +279,11 @@ private: } virtual void visit(AstBasicDType* nodep, AstNUser*) { if (m_traVscp) { - addTraceDecl(VNumRange()); + if (nodep->keyword()==AstBasicDTypeKwd::STRING) { + addIgnore("Unsupported: strings"); + } else { + addTraceDecl(VNumRange()); + } } } virtual void visit(AstNodeDType* nodep, AstNUser*) { diff --git a/test_regress/t/t_savable.v b/test_regress/t/t_savable.v index 730842990..4df08d24d 100644 --- a/test_regress/t/t_savable.v +++ b/test_regress/t/t_savable.v @@ -33,11 +33,14 @@ module sub (/*AUTOARG*/ real r; string s,s2; + string si; + // Test loop always @ (posedge clk) begin `ifdef TEST_VERBOSE $write("[%0t] cyc==%0d\n",$time, cyc); `endif + si = "siimmed"; cyc <= cyc + 1; if (cycdone[cyc[7:0]]) $stop; cycdone[cyc[7:0]] <= '1; diff --git a/test_regress/t/t_trace_complex.out b/test_regress/t/t_trace_complex.out index 5d5d4f519..9dde10fbb 100644 --- a/test_regress/t/t_trace_complex.out +++ b/test_regress/t/t_trace_complex.out @@ -1,39 +1,45 @@ $version Generated by VerilatedVcd $end -$date Thu Mar 13 20:06:49 2014 +$date Fri Mar 14 20:31:17 2014 $end $timescale 1ns $end $scope module top $end - $var wire 1 0 clk $end + $var wire 1 7 clk $end + $scope module $unit $end + $var wire 1 # global_bit $end + $upscope $end $scope module v $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 2 ' v_arrp [2:1] $end - $var wire 2 ( v_arrp_arrp [2:1] $end - $var wire 2 ) v_arrp_strp [1:0] $end - $var wire 1 1 v_arru(1) $end - $var wire 1 2 v_arru(2) $end - $var wire 2 * v_arru_arrp(3) [2:1] $end - $var wire 2 + v_arru_arrp(4) [2:1] $end - $var wire 1 3 v_arru_arru(3)(1) $end - $var wire 1 4 v_arru_arru(3)(2) $end - $var wire 1 5 v_arru_arru(4)(1) $end - $var wire 1 6 v_arru_arru(4)(2) $end - $var wire 2 , v_arru_strp(3) [1:0] $end - $var wire 2 - v_arru_strp(4) [1:0] $end - $var wire 2 $ v_strp [1:0] $end - $var wire 4 % v_strp_strp [3:0] $end - $var wire 2 & v_unip_strp [1:0] $end + $var wire 1 7 clk $end + $var wire 32 $ cyc [31:0] $end + $var real 64 1 v_arr_real(0) $end + $var real 64 3 v_arr_real(1) $end + $var wire 2 ( v_arrp [2:1] $end + $var wire 2 ) v_arrp_arrp [2:1] $end + $var wire 2 * v_arrp_strp [1:0] $end + $var wire 1 8 v_arru(1) $end + $var wire 1 9 v_arru(2) $end + $var wire 2 + v_arru_arrp(3) [2:1] $end + $var wire 2 , v_arru_arrp(4) [2:1] $end + $var wire 1 : v_arru_arru(3)(1) $end + $var wire 1 ; v_arru_arru(3)(2) $end + $var wire 1 < v_arru_arru(4)(1) $end + $var wire 1 = v_arru_arru(4)(2) $end + $var wire 2 - v_arru_strp(3) [1:0] $end + $var wire 2 . v_arru_strp(4) [1:0] $end + $var real 64 / v_real $end + $var wire 2 % v_strp [1:0] $end + $var wire 4 & v_strp_strp [3:0] $end + $var wire 2 ' v_unip_strp [1:0] $end $scope module p2 $end - $var wire 32 7 PARAM [31:0] $end + $var wire 32 > PARAM [31:0] $end $upscope $end $scope module p3 $end - $var wire 32 8 PARAM [31:0] $end + $var wire 32 ? PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 . b [31:0] $end + $var wire 32 5 b [31:0] $end $scope module unnamedblk2 $end - $var wire 32 / a [31:0] $end + $var wire 32 6 a [31:0] $end $upscope $end $upscope $end $upscope $end @@ -42,115 +48,137 @@ $enddefinitions $end #0 -b00000000000000000000000000000000 # -b00 $ -b0000 % -b00 & +1# +b00000000000000000000000000000000 $ +b00 % +b0000 & b00 ' -b0000 ( +b00 ( b0000 ) -b00 * +b0000 * b00 + b00 , b00 - -b00000000000000000000000000000000 . -b00000000000000000000000000000000 / -00 -01 -02 -03 -04 -05 -06 -b00000000000000000000000000000010 7 -b00000000000000000000000000000011 8 +b00 . +r0 / +r0 1 +r0 3 +b00000000000000000000000000000000 5 +b00000000000000000000000000000000 6 +07 +08 +09 +0: +0; +0< +0= +b00000000000000000000000000000010 > +b00000000000000000000000000000011 ? #10 -b00000000000000000000000000000001 # -b11 $ -b1111 % -b11 & +b00000000000000000000000000000001 $ +b11 % +b1111 & b11 ' -b1111 ( +b11 ( b1111 ) -b11 * +b1111 * b11 + b11 , b11 - -b00000000000000000000000000000101 . -b00000000000000000000000000000101 / -10 +b11 . +r0.1 / +r0.2 1 +r0.3 3 +b00000000000000000000000000000101 5 +b00000000000000000000000000000101 6 +17 #15 -00 +07 #20 -b00000000000000000000000000000010 # -b00 $ -b0000 % -b00 & +b00000000000000000000000000000010 $ +b00 % +b0000 & b00 ' -b0000 ( +b00 ( b0000 ) -b00 * +b0000 * b00 + b00 , b00 - -10 +b00 . +r0.2 / +r0.4 1 +r0.6 3 +17 #25 -00 +07 #30 -b00000000000000000000000000000011 # -b11 $ -b1111 % -b11 & +b00000000000000000000000000000011 $ +b11 % +b1111 & b11 ' -b1111 ( +b11 ( b1111 ) -b11 * +b1111 * b11 + b11 , b11 - -10 +b11 . +r0.3 / +r0.6000000000000001 1 +r0.8999999999999999 3 +17 #35 -00 +07 #40 -b00000000000000000000000000000100 # -b00 $ -b0000 % -b00 & +b00000000000000000000000000000100 $ +b00 % +b0000 & b00 ' -b0000 ( +b00 ( b0000 ) -b00 * +b0000 * b00 + b00 , b00 - -10 +b00 . +r0.4 / +r0.8 1 +r1.2 3 +17 #45 -00 +07 #50 -b00000000000000000000000000000101 # -b11 $ -b1111 % -b11 & +b00000000000000000000000000000101 $ +b11 % +b1111 & b11 ' -b1111 ( +b11 ( b1111 ) -b11 * +b1111 * b11 + b11 , b11 - -10 +b11 . +r0.5 / +r1 1 +r1.5 3 +17 #55 -00 +07 #60 -b00000000000000000000000000000110 # -b00 $ -b0000 % -b00 & +b00000000000000000000000000000110 $ +b00 % +b0000 & b00 ' -b0000 ( +b00 ( b0000 ) -b00 * +b0000 * b00 + b00 , b00 - -10 +b00 . +r0.6 / +r1.2 1 +r1.8 3 +17 diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v index e00bc9ad7..c57e440a8 100644 --- a/test_regress/t/t_trace_complex.v +++ b/test_regress/t/t_trace_complex.v @@ -3,6 +3,8 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Wilson Snyder. +bit global_bit; + module t (clk); input clk; integer cyc=0; @@ -43,6 +45,10 @@ module t (clk); arru_arrp_t v_arru_arrp; arru_strp_t v_arru_strp; + real v_real; + real v_arr_real [2]; + string v_string; + p #(.PARAM(2)) p2 (); p #(.PARAM(3)) p3 (); @@ -54,6 +60,10 @@ module t (clk); v_arrp_strp <= ~v_arrp_strp; v_arrp <= ~v_arrp; v_arrp_arrp <= ~v_arrp_arrp; + v_real <= v_real + 0.1; + v_string <= "foo"; + v_arr_real[0] <= v_arr_real[0] + 0.2; + v_arr_real[1] <= v_arr_real[1] + 0.3; for (integer b=3; b<=4; b++) begin v_arru[b] <= ~v_arru[b]; v_arru_strp[b] <= ~v_arru_strp[b]; @@ -71,4 +81,5 @@ endmodule module p; parameter PARAM = 1; + initial global_bit = 1; endmodule diff --git a/test_regress/t/t_trace_complex_params.out b/test_regress/t/t_trace_complex_params.out index fda4a88c0..a55094151 100644 --- a/test_regress/t/t_trace_complex_params.out +++ b/test_regress/t/t_trace_complex_params.out @@ -1,39 +1,45 @@ $version Generated by VerilatedVcd $end -$date Thu Mar 13 20:06:34 2014 +$date Fri Mar 14 20:32:05 2014 $end $timescale 1ns $end $scope module top $end - $var wire 1 0 clk $end + $var wire 1 7 clk $end + $scope module $unit $end + $var wire 1 # global_bit $end + $upscope $end $scope module v $end - $var wire 1 0 clk $end - $var wire 32 # cyc [31:0] $end - $var wire 2 ' v_arrp [2:1] $end - $var wire 2 ( v_arrp_arrp [2:1] $end - $var wire 2 ) v_arrp_strp [1:0] $end - $var wire 1 1 v_arru(1) $end - $var wire 1 2 v_arru(2) $end - $var wire 2 * v_arru_arrp(3) [2:1] $end - $var wire 2 + v_arru_arrp(4) [2:1] $end - $var wire 1 3 v_arru_arru(3)(1) $end - $var wire 1 4 v_arru_arru(3)(2) $end - $var wire 1 5 v_arru_arru(4)(1) $end - $var wire 1 6 v_arru_arru(4)(2) $end - $var wire 2 , v_arru_strp(3) [1:0] $end - $var wire 2 - v_arru_strp(4) [1:0] $end - $var wire 2 $ v_strp [1:0] $end - $var wire 4 % v_strp_strp [3:0] $end - $var wire 2 & v_unip_strp [1:0] $end + $var wire 1 7 clk $end + $var wire 32 $ cyc [31:0] $end + $var real 64 1 v_arr_real(0) $end + $var real 64 3 v_arr_real(1) $end + $var wire 2 ( v_arrp [2:1] $end + $var wire 2 ) v_arrp_arrp [2:1] $end + $var wire 2 * v_arrp_strp [1:0] $end + $var wire 1 8 v_arru(1) $end + $var wire 1 9 v_arru(2) $end + $var wire 2 + v_arru_arrp(3) [2:1] $end + $var wire 2 , v_arru_arrp(4) [2:1] $end + $var wire 1 : v_arru_arru(3)(1) $end + $var wire 1 ; v_arru_arru(3)(2) $end + $var wire 1 < v_arru_arru(4)(1) $end + $var wire 1 = v_arru_arru(4)(2) $end + $var wire 2 - v_arru_strp(3) [1:0] $end + $var wire 2 . v_arru_strp(4) [1:0] $end + $var real 64 / v_real $end + $var wire 2 % v_strp [1:0] $end + $var wire 4 & v_strp_strp [3:0] $end + $var wire 2 ' v_unip_strp [1:0] $end $scope module p2 $end - $var wire 32 7 PARAM [31:0] $end + $var wire 32 > PARAM [31:0] $end $upscope $end $scope module p3 $end - $var wire 32 8 PARAM [31:0] $end + $var wire 32 ? PARAM [31:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 . b [31:0] $end + $var wire 32 5 b [31:0] $end $scope module unnamedblk2 $end - $var wire 32 / a [31:0] $end + $var wire 32 6 a [31:0] $end $upscope $end $upscope $end $upscope $end @@ -42,115 +48,137 @@ $enddefinitions $end #0 -b00000000000000000000000000000000 # -b00 $ -b0000 % -b00 & +1# +b00000000000000000000000000000000 $ +b00 % +b0000 & b00 ' -b0000 ( +b00 ( b0000 ) -b00 * +b0000 * b00 + b00 , b00 - -b00000000000000000000000000000000 . -b00000000000000000000000000000000 / -00 -01 -02 -03 -04 -05 -06 -b00000000000000000000000000000010 7 -b00000000000000000000000000000011 8 +b00 . +r0 / +r0 1 +r0 3 +b00000000000000000000000000000000 5 +b00000000000000000000000000000000 6 +07 +08 +09 +0: +0; +0< +0= +b00000000000000000000000000000010 > +b00000000000000000000000000000011 ? #10 -b00000000000000000000000000000001 # -b11 $ -b1111 % -b11 & +b00000000000000000000000000000001 $ +b11 % +b1111 & b11 ' -b1111 ( +b11 ( b1111 ) -b11 * +b1111 * b11 + b11 , b11 - -b00000000000000000000000000000101 . -b00000000000000000000000000000101 / -10 +b11 . +r0.1 / +r0.2 1 +r0.3 3 +b00000000000000000000000000000101 5 +b00000000000000000000000000000101 6 +17 #15 -00 +07 #20 -b00000000000000000000000000000010 # -b00 $ -b0000 % -b00 & +b00000000000000000000000000000010 $ +b00 % +b0000 & b00 ' -b0000 ( +b00 ( b0000 ) -b00 * +b0000 * b00 + b00 , b00 - -10 +b00 . +r0.2 / +r0.4 1 +r0.6 3 +17 #25 -00 +07 #30 -b00000000000000000000000000000011 # -b11 $ -b1111 % -b11 & +b00000000000000000000000000000011 $ +b11 % +b1111 & b11 ' -b1111 ( +b11 ( b1111 ) -b11 * +b1111 * b11 + b11 , b11 - -10 +b11 . +r0.3 / +r0.6000000000000001 1 +r0.8999999999999999 3 +17 #35 -00 +07 #40 -b00000000000000000000000000000100 # -b00 $ -b0000 % -b00 & +b00000000000000000000000000000100 $ +b00 % +b0000 & b00 ' -b0000 ( +b00 ( b0000 ) -b00 * +b0000 * b00 + b00 , b00 - -10 +b00 . +r0.4 / +r0.8 1 +r1.2 3 +17 #45 -00 +07 #50 -b00000000000000000000000000000101 # -b11 $ -b1111 % -b11 & +b00000000000000000000000000000101 $ +b11 % +b1111 & b11 ' -b1111 ( +b11 ( b1111 ) -b11 * +b1111 * b11 + b11 , b11 - -10 +b11 . +r0.5 / +r1 1 +r1.5 3 +17 #55 -00 +07 #60 -b00000000000000000000000000000110 # -b00 $ -b0000 % -b00 & +b00000000000000000000000000000110 $ +b00 % +b0000 & b00 ' -b0000 ( +b00 ( b0000 ) -b00 * +b0000 * b00 + b00 , b00 - -10 +b00 . +r0.6 / +r1.2 1 +r1.8 3 +17 diff --git a/test_regress/t/t_trace_complex_structs.out b/test_regress/t/t_trace_complex_structs.out index cfcb0a5a9..850a29c03 100644 --- a/test_regress/t/t_trace_complex_structs.out +++ b/test_regress/t/t_trace_complex_structs.out @@ -1,68 +1,74 @@ $version Generated by VerilatedVcd $end -$date Thu Mar 13 20:04:29 2014 +$date Fri Mar 14 20:32:11 2014 $end $timescale 1ns $end $scope module top $end - $var wire 1 ; clk $end + $var wire 1 B clk $end + $scope module $unit $end + $var wire 1 # global_bit $end + $upscope $end $scope module v $end - $var wire 1 ; clk $end - $var wire 32 # cyc [31:0] $end - $var wire 2 , v_arrp [2:1] $end - $var wire 2 - v_arrp_arrp(3) [1:0] $end - $var wire 2 . v_arrp_arrp(4) [1:0] $end - $var wire 1 < v_arru(1) $end - $var wire 1 = v_arru(2) $end - $var wire 2 3 v_arru_arrp(3) [2:1] $end - $var wire 2 4 v_arru_arrp(4) [2:1] $end - $var wire 1 > v_arru_arru(3)(1) $end - $var wire 1 ? v_arru_arru(3)(2) $end - $var wire 1 @ v_arru_arru(4)(1) $end - $var wire 1 A v_arru_arru(4)(2) $end + $var wire 1 B clk $end + $var wire 32 $ cyc [31:0] $end + $var real 64 < v_arr_real(0) $end + $var real 64 > v_arr_real(1) $end + $var wire 2 - v_arrp [2:1] $end + $var wire 2 . v_arrp_arrp(3) [1:0] $end + $var wire 2 / v_arrp_arrp(4) [1:0] $end + $var wire 1 C v_arru(1) $end + $var wire 1 D v_arru(2) $end + $var wire 2 4 v_arru_arrp(3) [2:1] $end + $var wire 2 5 v_arru_arrp(4) [2:1] $end + $var wire 1 E v_arru_arru(3)(1) $end + $var wire 1 F v_arru_arru(3)(2) $end + $var wire 1 G v_arru_arru(4)(1) $end + $var wire 1 H v_arru_arru(4)(2) $end + $var real 64 : v_real $end $scope module unnamedblk1 $end - $var wire 32 9 b [31:0] $end + $var wire 32 @ b [31:0] $end $scope module unnamedblk2 $end - $var wire 32 : a [31:0] $end + $var wire 32 A a [31:0] $end $upscope $end $upscope $end $scope module v_arrp_strp(3) $end - $var wire 1 0 b0 $end - $var wire 1 / b1 $end + $var wire 1 1 b0 $end + $var wire 1 0 b1 $end $upscope $end $scope module v_arrp_strp(4) $end - $var wire 1 2 b0 $end - $var wire 1 1 b1 $end + $var wire 1 3 b0 $end + $var wire 1 2 b1 $end $upscope $end $scope module v_arru_strp(3) $end - $var wire 1 6 b0 $end - $var wire 1 5 b1 $end + $var wire 1 7 b0 $end + $var wire 1 6 b1 $end $upscope $end $scope module v_arru_strp(4) $end - $var wire 1 8 b0 $end - $var wire 1 7 b1 $end + $var wire 1 9 b0 $end + $var wire 1 8 b1 $end $upscope $end $scope module v_strp $end - $var wire 1 % b0 $end - $var wire 1 $ b1 $end + $var wire 1 & b0 $end + $var wire 1 % b1 $end $upscope $end $scope module v_strp_strp $end $scope module x0 $end - $var wire 1 ) b0 $end - $var wire 1 ( b1 $end + $var wire 1 * b0 $end + $var wire 1 ) b1 $end $upscope $end $scope module x1 $end - $var wire 1 ' b0 $end - $var wire 1 & b1 $end + $var wire 1 ( b0 $end + $var wire 1 ' b1 $end $upscope $end $upscope $end $scope module v_unip_strp $end $scope module x0 $end - $var wire 1 + b0 $end - $var wire 1 * b1 $end + $var wire 1 , b0 $end + $var wire 1 + b1 $end $upscope $end $scope module x1 $end - $var wire 1 + b0 $end - $var wire 1 * b1 $end + $var wire 1 , b0 $end + $var wire 1 + b1 $end $upscope $end $upscope $end $upscope $end @@ -71,8 +77,8 @@ $enddefinitions $end #0 -b00000000000000000000000000000000 # -0$ +1# +b00000000000000000000000000000000 $ 0% 0& 0' @@ -80,31 +86,34 @@ b00000000000000000000000000000000 # 0) 0* 0+ -b00 , +0, b00 - b00 . -0/ +b00 / 00 01 02 -b00 3 +03 b00 4 -05 +b00 5 06 07 08 -b00000000000000000000000000000000 9 -b00000000000000000000000000000000 : -0; -0< -0= -0> -0? -0@ -0A +09 +r0 : +r0 < +r0 > +b00000000000000000000000000000000 @ +b00000000000000000000000000000000 A +0B +0C +0D +0E +0F +0G +0H #10 -b00000000000000000000000000000001 # -1$ +b00000000000000000000000000000001 $ 1% 1& 1' @@ -112,27 +121,30 @@ b00000000000000000000000000000001 # 1) 1* 1+ -b11 , +1, b11 - b11 . -1/ +b11 / 10 11 12 -b11 3 +13 b11 4 -15 +b11 5 16 17 18 -b00000000000000000000000000000101 9 -b00000000000000000000000000000101 : -1; +19 +r0.1 : +r0.2 < +r0.3 > +b00000000000000000000000000000101 @ +b00000000000000000000000000000101 A +1B #15 -0; +0B #20 -b00000000000000000000000000000010 # -0$ +b00000000000000000000000000000010 $ 0% 0& 0' @@ -140,25 +152,28 @@ b00000000000000000000000000000010 # 0) 0* 0+ -b00 , +0, b00 - b00 . -0/ +b00 / 00 01 02 -b00 3 +03 b00 4 -05 +b00 5 06 07 08 -1; +09 +r0.2 : +r0.4 < +r0.6 > +1B #25 -0; +0B #30 -b00000000000000000000000000000011 # -1$ +b00000000000000000000000000000011 $ 1% 1& 1' @@ -166,25 +181,28 @@ b00000000000000000000000000000011 # 1) 1* 1+ -b11 , +1, b11 - b11 . -1/ +b11 / 10 11 12 -b11 3 +13 b11 4 -15 +b11 5 16 17 18 -1; +19 +r0.3 : +r0.6000000000000001 < +r0.8999999999999999 > +1B #35 -0; +0B #40 -b00000000000000000000000000000100 # -0$ +b00000000000000000000000000000100 $ 0% 0& 0' @@ -192,25 +210,28 @@ b00000000000000000000000000000100 # 0) 0* 0+ -b00 , +0, b00 - b00 . -0/ +b00 / 00 01 02 -b00 3 +03 b00 4 -05 +b00 5 06 07 08 -1; +09 +r0.4 : +r0.8 < +r1.2 > +1B #45 -0; +0B #50 -b00000000000000000000000000000101 # -1$ +b00000000000000000000000000000101 $ 1% 1& 1' @@ -218,25 +239,28 @@ b00000000000000000000000000000101 # 1) 1* 1+ -b11 , +1, b11 - b11 . -1/ +b11 / 10 11 12 -b11 3 +13 b11 4 -15 +b11 5 16 17 18 -1; +19 +r0.5 : +r1 < +r1.5 > +1B #55 -0; +0B #60 -b00000000000000000000000000000110 # -0$ +b00000000000000000000000000000110 $ 0% 0& 0' @@ -244,17 +268,21 @@ b00000000000000000000000000000110 # 0) 0* 0+ -b00 , +0, b00 - b00 . -0/ +b00 / 00 01 02 -b00 3 +03 b00 4 -05 +b00 5 06 07 08 -1; +09 +r0.6 : +r1.2 < +r1.8 > +1B