From 936bb7b1edb47a0f1d4cf69ca8a1c1b54c1245b7 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 5 Feb 2023 14:06:03 -0500
Subject: [PATCH] Add error on size with unsized number

---
 src/V3Number.cpp                       |  6 ++++++
 test_regress/t/t_fuzz_negwidth_bad.out | 12 ++++++++++++
 test_regress/t/t_fuzz_negwidth_bad.v   |  4 ++++
 test_regress/t/t_tri_and_eqcase.out    | 12 ++++++------
 test_regress/t/t_tri_and_eqcase.v      |  2 +-
 5 files changed, 29 insertions(+), 7 deletions(-)

diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index b59dfb899..54342a561 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -138,6 +138,7 @@ void V3Number::create(const char* sourcep) {
         }
     }
 
+    bool userSized = false;
     bool unbased = false;
     char base = '\0';
     if (value_startp != sourcep) {  // Has a '
@@ -161,6 +162,7 @@ void V3Number::create(const char* sourcep) {
         }
         value_startp = cp;
 
+        userSized = widthn.length() != 0;
         if (std::atoi(widthn.c_str())) {
             if (std::atoi(widthn.c_str()) < 0
                 || std::atoi(widthn.c_str()) > v3Global.opt.maxNumWidth()) {
@@ -208,6 +210,10 @@ void V3Number::create(const char* sourcep) {
     if (!*value_startp && !m_data.m_autoExtend) {
         v3error("Number is missing value digits: " << sourcep);
     }
+    if (userSized && m_data.m_autoExtend) {
+        v3error("Syntax error: size cannot be provided with '0/'1/'x/'z: "
+                << sourcep << " (IEEE 1800-2017 5.7.1)");
+    }
 
     int obit = 0;  // Start at LSB
     if (tolower(base) == 'd') {
diff --git a/test_regress/t/t_fuzz_negwidth_bad.out b/test_regress/t/t_fuzz_negwidth_bad.out
index 7d1d69a9f..f6ee9cd4d 100644
--- a/test_regress/t/t_fuzz_negwidth_bad.out
+++ b/test_regress/t/t_fuzz_negwidth_bad.out
@@ -1,4 +1,16 @@
 %Error: t/t_fuzz_negwidth_bad.v:9:9: Unsupported: Width of number exceeds implementation limit: 1231232312312312'd1  (IEEE 1800-2017 6.9.1)
     9 | int c = 1231232312312312'd1;
       |         ^~~~~~~~~~~~~~~~~~~
+%Error: t/t_fuzz_negwidth_bad.v:10:9: Syntax error: size cannot be provided with '0/'1/'x/'z: 12'1 (IEEE 1800-2017 5.7.1)
+   10 | int e = 12'1;
+      |         ^~~~
+%Error: t/t_fuzz_negwidth_bad.v:11:9: Syntax error: size cannot be provided with '0/'1/'x/'z: 12'0 (IEEE 1800-2017 5.7.1)
+   11 | int f = 12'0;
+      |         ^~~~
+%Error: t/t_fuzz_negwidth_bad.v:12:9: Syntax error: size cannot be provided with '0/'1/'x/'z: 12'z (IEEE 1800-2017 5.7.1)
+   12 | int g = 12'z;
+      |         ^~~~
+%Error: t/t_fuzz_negwidth_bad.v:13:9: Syntax error: size cannot be provided with '0/'1/'x/'z: 12'x (IEEE 1800-2017 5.7.1)
+   13 | int h = 12'x;
+      |         ^~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_fuzz_negwidth_bad.v b/test_regress/t/t_fuzz_negwidth_bad.v
index d9c7d3cdb..242f0a64b 100644
--- a/test_regress/t/t_fuzz_negwidth_bad.v
+++ b/test_regress/t/t_fuzz_negwidth_bad.v
@@ -7,3 +7,7 @@
 int a = -12'd1;
 int b = 65536'd1;
 int c = 1231232312312312'd1;
+int e = 12'1;
+int f = 12'0;
+int g = 12'z;
+int h = 12'x;
diff --git a/test_regress/t/t_tri_and_eqcase.out b/test_regress/t/t_tri_and_eqcase.out
index 315a41e1f..d319b4996 100644
--- a/test_regress/t/t_tri_and_eqcase.out
+++ b/test_regress/t/t_tri_and_eqcase.out
@@ -1,8 +1,8 @@
-%Error-UNSUPPORTED: t/t_tri_and_eqcase.v:9:28: Unsupported tristate construct: AND in function getEnExprBasedOnOriginalp
-    9 |    logic b = 1'z === (clk1 & clk2);
-      |                            ^
+%Error-UNSUPPORTED: t/t_tri_and_eqcase.v:9:29: Unsupported tristate construct: AND in function getEnExprBasedOnOriginalp
+    9 |    logic b = 1'bz === (clk1 & clk2);
+      |                             ^
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error: Internal Error: t/t_tri_and_eqcase.v:9:18: ../V3Ast.cpp:#: Null item passed to setOp2p
-    9 |    logic b = 1'z === (clk1 & clk2);
-      |                  ^~~
+%Error: Internal Error: t/t_tri_and_eqcase.v:9:19: ../V3Ast.cpp:#: Null item passed to setOp2p
+    9 |    logic b = 1'bz === (clk1 & clk2);
+      |                   ^~~
                         ... See the manual at https://verilator.org/verilator_doc.html for more assistance.
diff --git a/test_regress/t/t_tri_and_eqcase.v b/test_regress/t/t_tri_and_eqcase.v
index 204aab82d..1c4b09a14 100644
--- a/test_regress/t/t_tri_and_eqcase.v
+++ b/test_regress/t/t_tri_and_eqcase.v
@@ -6,7 +6,7 @@
 
 module t (clk1, clk2);
    input wire clk1, clk2;
-   logic b = 1'z === (clk1 & clk2);
+   logic b = 1'bz === (clk1 & clk2);
 
    always begin
       if (!b) begin