From 929d2ad83a59c0e54b58fb25853c617d626c461d Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 3 Sep 2025 19:45:43 -0400
Subject: [PATCH] Fix package imports not found after parameters applied
 (#6373).

---
 Changes                                  |  1 +
 src/V3LinkDot.cpp                        | 16 ++++++------
 test_regress/t/t_package_import_param.py | 16 ++++++++++++
 test_regress/t/t_package_import_param.v  | 33 ++++++++++++++++++++++++
 4 files changed, 58 insertions(+), 8 deletions(-)
 create mode 100755 test_regress/t/t_package_import_param.py
 create mode 100644 test_regress/t/t_package_import_param.v

diff --git a/Changes b/Changes
index 9baced51a..a0825e403 100644
--- a/Changes
+++ b/Changes
@@ -16,6 +16,7 @@ Verilator 5.041 devel
 * Fix while loop hang on timing-delayed assignment (#6343) (#6354). [Krzysztof Bieganski, Antmicro Ltd.]
 * Fix V3Hash MacOS ambiguity (#6350). [Lan Zongwei]
 * Fix cmake APPLE variable (#6351). [Lan Zongwei]
+* Fix package imports not found after parameters applied (#6373). [Alex Solomatnikov]
 
 
 Verilator 5.040 2025-08-30
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 4afa67720..1bf052536 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -168,8 +168,8 @@ private:
 public:
     // METHODS
 
-    void dumpSelf(const string& nameComment = "linkdot", bool force = false) {
-        if (dumpLevel() >= 6 || force) {
+    void dumpSelf(const string& nameComment, bool force = false) {
+        if (debug() >= 6 || dumpLevel() >= 6 || force) {
             const string filename = v3Global.debugFilename(nameComment) + ".txt";
             const std::unique_ptr<std::ofstream> logp{V3File::new_ofstream(filename)};
             if (logp->fail()) v3fatal("Can't write file: " << filename);
@@ -4880,19 +4880,19 @@ class LinkDotResolveVisitor final : public VNVisitor {
         // No longer needed
         LINKDOT_VISIT_START();
         checkNoDot(nodep);
-        VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
+        if (m_statep->forParamed()) VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
     }
     void visit(AstPackageExport* nodep) override {
         // No longer needed
         LINKDOT_VISIT_START();
         checkNoDot(nodep);
-        VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
+        if (m_statep->forParamed()) VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
     }
     void visit(AstPackageExportStarStar* nodep) override {
         // No longer needed
         LINKDOT_VISIT_START();
         checkNoDot(nodep);
-        VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
+        if (m_statep->forParamed()) VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
     }
     void visit(AstCellRef* nodep) override {
         LINKDOT_VISIT_START();
@@ -5009,13 +5009,13 @@ void V3LinkDot::linkDotGuts(AstNetlist* rootp, VLinkDotStep step) {
     } else {
         v3fatalSrc("Bad case");
     }
-    state.dumpSelf();
+    state.dumpSelf("prelinkdot");
     state.computeIfaceModSyms();
     state.computeIfaceVarSyms();
     state.computeScopeAliases();
-    state.dumpSelf();
+    state.dumpSelf("linkdot-preresolve");
     LinkDotResolveVisitor visitor{rootp, &state};
-    state.dumpSelf();
+    state.dumpSelf("linkdot-done");
 }
 
 void V3LinkDot::linkDotPrimary(AstNetlist* nodep) {
diff --git a/test_regress/t/t_package_import_param.py b/test_regress/t/t_package_import_param.py
new file mode 100755
index 000000000..cca4c9e73
--- /dev/null
+++ b/test_regress/t/t_package_import_param.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.lint()
+
+test.passes()
diff --git a/test_regress/t/t_package_import_param.v b/test_regress/t/t_package_import_param.v
new file mode 100644
index 000000000..9822d0e76
--- /dev/null
+++ b/test_regress/t/t_package_import_param.v
@@ -0,0 +1,33 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+package s_pkg;
+  typedef enum bit [4:0] {MEM_REQ = 5'b00000} P_Type_e;
+endpackage
+
+package pkg;
+  import s_pkg::*;
+
+  virtual class uvm_sequence #(
+      type REQ = int
+  );
+    REQ m_req;
+  endclass
+
+  class cls_txn;
+    P_Type_e m_type;
+  endclass
+
+  class cls_seq extends uvm_sequence #(cls_txn);
+  endclass
+
+  class p_mem_seq extends cls_seq;
+    virtual task body();
+      if (0 == (m_req.randomize() with {m_req.m_type == MEM_REQ;})) begin
+      end
+    endtask
+  endclass
+endpackage