From 9254443cd41509f6c5337c7cccc01813b1da23b2 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 12 Nov 2015 22:29:42 -0500
Subject: [PATCH] Fix  casts under generates, bug999.

---
 Changes                          |  4 ++-
 src/V3Width.cpp                  |  6 ++---
 src/V3WidthCommit.h              |  1 +
 test_regress/t/t_math_signed7.pl | 18 +++++++++++++
 test_regress/t/t_math_signed7.v  | 44 ++++++++++++++++++++++++++++++++
 5 files changed, 68 insertions(+), 5 deletions(-)
 create mode 100755 test_regress/t/t_math_signed7.pl
 create mode 100644 test_regress/t/t_math_signed7.v

diff --git a/Changes b/Changes
index 8a205db0a..6cc11b0c7 100644
--- a/Changes
+++ b/Changes
@@ -5,7 +5,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.879 devel
 
-****  Fix display %u, %v, %p, %z, bug989. [Johan Bjork]
+***   Support display %u, %v, %p, %z, bug989. [Johan Bjork]
 
 ****  Fix real parameters causing bad module names, bug992. [Johan Bjork]
 
@@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix constant function assigned to packed structs, bug997. [Johan Bjork]
 
+****  Fix $signed casts under generates, bug999. [Clifford Wolf]
+
 
 * Verilator 3.878 2015-11-01
 
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 727d025d6..9272d1159 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3544,8 +3544,7 @@ AstNode* V3Width::widthParamsEdit (AstNode* nodep) {
     // We should do it in bottom-up module order, but it works in any order.
     WidthVisitor visitor (true, false);
     nodep = visitor.mainAcceptEdit(nodep);
-    WidthRemoveVisitor rvisitor;
-    nodep = rvisitor.mainAcceptEdit(nodep);
+    // No WidthRemoveVisitor, as don't want to drop $signed etc inside gen blocks
     return nodep;
 }
 
@@ -3564,8 +3563,7 @@ AstNode* V3Width::widthGenerateParamsEdit(
     // We should do it in bottom-up module order, but it works in any order.
     WidthVisitor visitor (true, true);
     nodep = visitor.mainAcceptEdit(nodep);
-    WidthRemoveVisitor rvisitor;
-    nodep = rvisitor.mainAcceptEdit(nodep);
+    // No WidthRemoveVisitor, as don't want to drop $signed etc inside gen blocks
     return nodep;
 }
 
diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h
index b7c73e83b..abb0617c1 100644
--- a/src/V3WidthCommit.h
+++ b/src/V3WidthCommit.h
@@ -32,6 +32,7 @@
 //######################################################################
 
 /// Remove all $signed, $unsigned, we're done with them.
+/// This step is only called on real V3Width, not intermediate e.g. widthParams
 
 class WidthRemoveVisitor : public AstNVisitor {
 private:
diff --git a/test_regress/t/t_math_signed7.pl b/test_regress/t/t_math_signed7.pl
new file mode 100755
index 000000000..f91289753
--- /dev/null
+++ b/test_regress/t/t_math_signed7.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_math_signed7.v b/test_regress/t/t_math_signed7.v
new file mode 100644
index 000000000..421fde7c2
--- /dev/null
+++ b/test_regress/t/t_math_signed7.v
@@ -0,0 +1,44 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2015 by Iztok Jeras.
+
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   reg alu_ltu, alu_lts;
+   logic [3:0] in_op1;
+   logic [3:0] in_op2;
+
+
+   reg aaa_ltu, aaa_lts;
+      always @(posedge clk) begin
+	 in_op1 = 4'sb1110;
+	 in_op2 =  4'b0010;
+	 aaa_ltu = in_op1 < in_op2;
+	 // bug999
+	 aaa_lts = $signed(in_op1) < $signed(in_op2);
+	 `checkh (aaa_ltu, 1'b0);
+	 `checkh (aaa_lts, 1'b1);
+      end
+
+   generate if (1) begin
+      always @(posedge clk) begin
+	 in_op1 = 4'sb1110;
+	 in_op2 =  4'b0010;
+	 alu_ltu = in_op1 < in_op2;
+	 // bug999
+	 alu_lts = $signed(in_op1) < $signed(in_op2);
+	 `checkh (alu_ltu, 1'b0);
+	 `checkh (alu_lts, 1'b1);
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+   endgenerate
+endmodule