diff --git a/test_regress/t/t_gen_index.pl b/test_regress/t/t_gen_index.pl
new file mode 100755
index 000000000..4d9e70f55
--- /dev/null
+++ b/test_regress/t/t_gen_index.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} and $Self->unsupported("Verilator unsupported, bug517");
+
+# Compile time only test
+compile (
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gen_index.v b/test_regress/t/t_gen_index.v
new file mode 100644
index 000000000..cf5644445
--- /dev/null
+++ b/test_regress/t/t_gen_index.v
@@ -0,0 +1,72 @@
+// DESCRIPTION: Verilator: Test generate index usage.
+//
+// The code illustrates a problem in Verilator's handling of constant
+// expressions inside generate indexes.
+//
+// This is a regression test against issue 517.
+//
+// **If you do not wish for your code to be released to the public
+// please note it here, otherwise:**
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Jeremy Bennett.
+
+
+`define START 8
+`define SIZE  4
+`define END   (`START + `SIZE)
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   reg [`END-1:0]   y;
+   wire [`END-1:0]  x;
+
+   foo foo_i (.y   (y),
+	      .x   (x),
+	      .clk (clk));
+
+   always @(posedge clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule // t
+
+
+module foo(output wire [`END-1:0] y,
+	   input wire [`END-1:0] x,
+	   input wire 		 clk);
+
+   function peek_bar;
+      peek_bar = bar_inst[`START].i_bar.r;       // this is ok
+      peek_bar = bar_inst[`START + 1].i_bar.r;   // this fails, should not.
+   endfunction
+
+   genvar g;
+   generate
+      for (g = `START; g < `END; g = g + 1) begin: bar_inst
+         bar i_bar(.x   (x[g]),
+		   .y   (y[g]),
+		   .clk (clk));
+      end
+   endgenerate
+
+endmodule : foo
+
+
+module bar(output wire y,
+	   input wire x,
+	   input wire clk);
+
+   reg r = 0;
+   assign y = r;
+
+   always @(posedge clk) begin
+      r = x ? ~x : y;
+   end
+
+endmodule : bar