From 92300ab675def3cfe7fed8d5896c23fe97152bde Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 14 Aug 2026 18:28:19 -0400
Subject: [PATCH] Commentary: Changes update

---
 Changes                                     | 8 ++++++++
 test_regress/t/t_assocsel_sideeffect.v      | 6 +++---
 test_regress/t/t_constraint_red_arr_unsup.v | 6 ++----
 test_regress/t/t_wildcard_sideeffect.v      | 2 +-
 4 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/Changes b/Changes
index 8ce90518e..80442b213 100644
--- a/Changes
+++ b/Changes
@@ -32,12 +32,14 @@ Verilator 5.051 devel
 * Support `default clocking` (#7984). [Kamil Danecki, Antmicro Ltd.]
 * Support embedded covergroup clocking events (#8028). [Marco Bartoli]
 * Support `weak`/`strong` keywords in property expressions (#8054). [Artur Bieniek, Antmicro Ltd.]
+* Support class handle covergroup arguments (#8071). [Marco Bartoli]
 * Optimize random initialization. [Geza Lore, Testorrent USA, Inc.]
 * Optimize more always blocks in DFG (#7775). [Geza Lore, Testorrent USA, Inc.]
 * Optimize assertion NFAs using bit-vector ring buffers (#7885). [Artur Bieniek, Antmicro Ltd.]
 * Optimize VPI symbol registration and scope construction (#7936). [Nick Brereton]
 * Optimize bounded always properties using ring buffers (#8061) (#8092). [Artur Bieniek, Antmicro Ltd.]
 * Optimize VL_WORDS_I/VL_BYTES_I (#8095). [Geza Lore, Testorrent USA, Inc.]
+* Optimize temporary insertion for single bit replicates in DFG (#8110). [Geza Lore, Testorrent USA, Inc.]
 * Fix $finish continuing event loop (#7267) (#7950). [Artur Bieniek, Antmicro Ltd.]
 * Fix $display accepting streaming concat arguments (#7663) (#7890). [Jaeuk Lee]
 * Fix DFG misoptimizing bound checks (#7755). [Jakub Michalski]
@@ -86,6 +88,7 @@ Verilator 5.051 devel
 * Fix variable scope in unique on dynamic array (#7981). [Kornel Uriasz, Antmicro Ltd.]
 * Fix table optimization causing not contextually convertible to bool error (#7983). [Jakub Michalski]
 * Fix wait fork trigger temporary split across generated functions (#7985) (#7986). [Marco Brambilla]
+* Fix randc cycling in a class that also uses solve...before (#7991 partial) (#8055). [Yilou Wang]
 * Fix randomize() with a user variable named 'item' (#7993) (#7994).
 * Fix UNSATCONSTR reporting constraint indices above 9 (#7995). [Yilou Wang]
 * Fix MULTIDRIVEN/PROC warning suppression via lint_off (#8000). [Gilberto Abram]
@@ -112,9 +115,14 @@ Verilator 5.051 devel
 * Fix untyped datatype error on sampling functions with property arguments (#8060). [Artur Bieniek, Antmicro Ltd.]
 * Fix VPI cbValueChange for 1-bit select (#8063). [Bartłomiej Chmiel, Antmicro Ltd.]
 * Fix skipping non-constrained enum constraining when inside object of other class (#8075). [Kornel Uriasz, Antmicro Ltd.]
+* Fix unintended side-effect insertion on associative array read (#8077). [Adam Kostrzewski, Antmicro Ltd.]
 * Fix undefined symbol solver error (#8080). [Igor Zaworski, Antmicro Ltd.]
 * Fix unpacked array element force with procedural assign (#8084) (#8085). [Nikolai Kumar]
 * Fix hierarchical class scope resolution (#8094). [Artur Bieniek, Antmicro Ltd.]
+* Fix the clang compilation using precompiled headers (#8105). [Demin Han]
+* Fix invalid typedef (#8106). [Adam Kostrzewski, Antmicro Ltd.]
+* Fix R/W references to random builtin function seeds (#8112). [Geza Lore, Testorrent USA, Inc.]
+* Fix COVERIGN on SVA goto repetition (#8118). [Artur Bieniek, Antmicro Ltd.]
 
 
 Verilator 5.050 2026-07-01
diff --git a/test_regress/t/t_assocsel_sideeffect.v b/test_regress/t/t_assocsel_sideeffect.v
index 0afc941a0..72e95fbb4 100644
--- a/test_regress/t/t_assocsel_sideeffect.v
+++ b/test_regress/t/t_assocsel_sideeffect.v
@@ -33,20 +33,20 @@ module t;
   initial begin
     // 1D
     foreach (dict1d[b]) begin
-      $error(b); // should never reach
+      $error(b);  // should never reach
     end
     `checkd(dict1d.size(), 0);
 
     // 2D
     foreach (dict2d[0][b]) begin
-      $error(b); // should never reach
+      $error(b);  // should never reach
     end
     `checkd(dict2d.size(), 0);
 
     // 3D
     foreach (dict3d[0][i]) begin
       foreach (dict3d[0][i][j]) begin
-        $error(i, j); // should never reach
+        $error(i, j);  // should never reach
       end
     end
     `checkd(dict3d.size(), 0);
diff --git a/test_regress/t/t_constraint_red_arr_unsup.v b/test_regress/t/t_constraint_red_arr_unsup.v
index 25ed0e2ec..82a2e74c7 100644
--- a/test_regress/t/t_constraint_red_arr_unsup.v
+++ b/test_regress/t/t_constraint_red_arr_unsup.v
@@ -8,16 +8,14 @@ class ReductionDynSubArr;
   rand int arr[5][];
   rand int a;
 
-  typedef struct {
-    rand int arr[];
-  } Subcls;
+  typedef struct {rand int arr[];} Subcls;
 
   rand Subcls sc;
 
   function new();
     sc.arr = new[5];
     foreach (arr[i]) begin
-      arr[i] = new [5];
+      arr[i] = new[5];
     end
   endfunction
 
diff --git a/test_regress/t/t_wildcard_sideeffect.v b/test_regress/t/t_wildcard_sideeffect.v
index 2ddcf3293..b44bac44f 100644
--- a/test_regress/t/t_wildcard_sideeffect.v
+++ b/test_regress/t/t_wildcard_sideeffect.v
@@ -17,7 +17,7 @@ module t;
     int dict1d[*];
     int dict2d[*][*];
     int dict3d[*][*][*];
-    int dictmix[int][*];
+    int dictmix[int] [*];
 
     `checkd(dict1d[0], 0);
     `checkd(dict1d.size(), 0);