From 91e2d1d2a05db5a22df8b3b552d8016eefe9ca17 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 17 Jan 2013 22:45:35 -0500 Subject: [PATCH] Tests: Make struct test pass. --- test_regress/t/t_array_packed_sysfunct.v | 210 +++++++++++++---------- test_regress/t/t_array_query.v | 8 +- test_regress/t/t_bind2.v | 2 +- test_regress/t/t_bitsel_struct2.v | 2 +- 4 files changed, 123 insertions(+), 99 deletions(-) diff --git a/test_regress/t/t_array_packed_sysfunct.v b/test_regress/t/t_array_packed_sysfunct.v index 28010613c..e54fb0946 100644 --- a/test_regress/t/t_array_packed_sysfunct.v +++ b/test_regress/t/t_array_packed_sysfunct.v @@ -10,22 +10,40 @@ module t (/*AUTOARG*/ input clk; +`define check(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: Line%0d: cnt=0x%0x got=0x%0x exp=0x%0x\n", `__LINE__, cnt, (gotv), (expv)); $stop; end while(0); + // parameters for array sizes localparam WA = 4; localparam WB = 6; localparam WC = 8; // 2D packed arrays - logic [WA-1:0] [WB-1:0] [WC-1:0] array_bg; // big endian array + logic [WA+1:2] [WB+1:2] [WC+1:2] array_bg; // big endian array /* verilator lint_off LITENDIAN */ - logic [0:WA-1] [0:WB-1] [0:WC-1] array_lt; // little endian array + logic [2:WA+1] [2:WB+1] [2:WC+1] array_lt; // little endian array /* verilator lint_on LITENDIAN */ + logic [1:0] array_unpk [3:2][1:0]; + integer cnt = 0; integer slc = 0; // slice type integer dim = 0; // dimension integer wdt = 0; // width + initial begin + `check($dimensions (array_unpk), 3); +`ifndef VCS + `check($unpacked_dimensions (array_unpk), 2); // IEEE 2009 +`endif + `check($bits (array_unpk), 2*2*2); + `check($low (array_unpk), 2); + `check($high (array_unpk), 3); + `check($left (array_unpk), 3); + `check($right(array_unpk), 2); + `check($increment(array_unpk), 1); + `check($size (array_unpk), 2); + end + // event counter always @ (posedge clk) begin cnt <= cnt + 1; @@ -38,104 +56,110 @@ module t (/*AUTOARG*/ $finish; end + integer slc_next; + // calculation of dimention sizes - always @ (posedge clk) - begin - // slicing tipe counter + always @ (posedge clk) begin + // slicing type counter case (cnt[3:2]) - 2'd0 : begin slc <= 0; end // full array - 2'd1 : begin slc <= 1; end // half array - 2'd2 : begin slc <= 2; end // single array element - default: begin slc <= 0; end + 2'd0 : begin slc_next = 0; end // full array + 2'd1 : begin slc_next = 1; end // single array element + 2'd2 : begin slc_next = 2; end // half array + default: begin slc_next = 0; end endcase - // dimmension counter + slc <= slc_next; + // dimension counter case (cnt[1:0]) - 2'd0 : begin dim <= 1; wdt = (slc==1) ? WA/2 : (slc==2) ? 1 : WA; end - 2'd1 : begin dim <= 2; wdt = WB; end - 2'd2 : begin dim <= 3; wdt = WC; end - default: begin dim <= 0; wdt = 0; end + 2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end + 2'd1 : begin dim <= 2; wdt <= WB; end + 2'd2 : begin dim <= 3; wdt <= WC; end + default: begin dim <= 0; wdt <= 0; end endcase end - always @ (posedge clk) - if (cnt[30:4]==1) begin - // big endian - if (cnt[3:2]==0) begin - // full array - if ($dimensions (array_bg) != 3) $stop; - if ($bits (array_bg) != WA*WB*WC) $stop; - if ((dim>=1)&&(dim<=3)) begin - if ($left (array_bg, dim) != wdt-1) $stop; - if ($right (array_bg, dim) != 0 ) $stop; - if ($low (array_bg, dim) != 0 ) $stop; - if ($high (array_bg, dim) != wdt-1) $stop; - if ($increment (array_bg, dim) != 1 ) $stop; - if ($size (array_bg, dim) != wdt ) $stop; - end - end else if (cnt[3:2]==1) begin - // half array - if ($dimensions (array_bg[WA/2-1:0]) != 3) $stop; - if ($bits (array_bg[WA/2-1:0]) != WA/2*WB*WC) $stop; - if ((dim>=1)&&(dim<=3)) begin - if ($left (array_bg[WA/2-1:0], dim) != wdt-1) $stop; - if ($right (array_bg[WA/2-1:0], dim) != 0 ) $stop; - if ($low (array_bg[WA/2-1:0], dim) != 0 ) $stop; - if ($high (array_bg[WA/2-1:0], dim) != wdt-1) $stop; - if ($increment (array_bg[WA/2-1:0], dim) != 1 ) $stop; - if ($size (array_bg[WA/2-1:0], dim) != wdt ) $stop; - end - end else if (cnt[3:2]==2) begin - // single array element - if ($dimensions (array_bg[0]) != 2) $stop; - if ($bits (array_bg[0]) != WB*WC) $stop; - if ((dim>=2)&&(dim<=3)) begin - if ($left (array_bg[0], dim-1) != wdt-1) $stop; - if ($right (array_bg[0], dim-1) != 0 ) $stop; - if ($low (array_bg[0], dim-1) != 0 ) $stop; - if ($high (array_bg[0], dim-1) != wdt-1) $stop; - if ($increment (array_bg[0], dim-1) != 1 ) $stop; - if ($size (array_bg[0], dim-1) != wdt ) $stop; - end - end - end else if (cnt[30:4]==2) begin - // little endian - if (cnt[3:2]==0) begin - // full array - if ($dimensions (array_lt) != 3) $stop; - if ($bits (array_lt) != WA*WB*WC) $stop; - if ((dim>=1)&&(dim<=3)) begin - if ($left (array_lt, dim) != 0 ) $stop; - if ($right (array_lt, dim) != wdt-1) $stop; - if ($low (array_lt, dim) != 0 ) $stop; - if ($high (array_lt, dim) != wdt-1) $stop; - if ($increment (array_lt, dim) != -1 ) $stop; - if ($size (array_lt, dim) != wdt ) $stop; - end - end else if (cnt[3:2]==1) begin - // half array - if ($dimensions (array_lt[0:WA/2-1]) != 3) $stop; - if ($bits (array_lt[0:WA/2-1]) != WA/2*WB*WC) $stop; - if ((dim>=1)&&(dim<=3)) begin - if ($left (array_lt[0:WA/2-1], dim) != 0 ) $stop; - if ($right (array_lt[0:WA/2-1], dim) != wdt-1) $stop; - if ($low (array_lt[0:WA/2-1], dim) != 0 ) $stop; - if ($high (array_lt[0:WA/2-1], dim) != wdt-1) $stop; - if ($increment (array_lt[0:WA/2-1], dim) != -1 ) $stop; - if ($size (array_lt[0:WA/2-1], dim) != wdt ) $stop; - end - end else if (cnt[3:2]==2) begin - // single array element - if ($dimensions (array_lt[0]) != 2) $stop; - if ($bits (array_lt[0]) != WB*WC) $stop; - if ((dim>=2)&&(dim<=3)) begin - if ($left (array_lt[0], dim-1) != 0 ) $stop; - if ($right (array_lt[0], dim-1) != wdt-1) $stop; - if ($low (array_lt[0], dim-1) != 0 ) $stop; - if ($high (array_lt[0], dim-1) != wdt-1) $stop; - if ($increment (array_lt[0], dim-1) != -1 ) $stop; - if ($size (array_lt[0], dim-1) != wdt ) $stop; - end + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt); +`endif + if (cnt[30:4]==1) begin + // big endian + if (slc==0) begin + // full array + `check($dimensions (array_bg), 3); + `check($bits (array_bg), WA*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `check($left (array_bg, dim), wdt+1); + `check($right (array_bg, dim), 2 ); + `check($low (array_bg, dim), 2 ); + `check($high (array_bg, dim), wdt+1); + `check($increment (array_bg, dim), 1 ); + `check($size (array_bg, dim), wdt ); + end + end else if (slc==1) begin + // single array element + `check($dimensions (array_bg[2]), 2); + `check($bits (array_bg[2]), WB*WC); + if ((dim>=2)&&(dim<=3)) begin + `check($left (array_bg[2], dim-1), wdt+1); + `check($right (array_bg[2], dim-1), 2 ); + `check($low (array_bg[2], dim-1), 2 ); + `check($high (array_bg[2], dim-1), wdt+1); + `check($increment (array_bg[2], dim-1), 1 ); + `check($size (array_bg[2], dim-1), wdt ); + end + end else if (slc==2) begin + // half array + `check($dimensions (array_bg[WA/2+1:2]), 3); + `check($bits (array_bg[WA/2+1:2]), WA/2*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `check($left (array_bg[WA/2+1:2], dim), wdt+1); + `check($right (array_bg[WA/2+1:2], dim), 2 ); + `check($low (array_bg[WA/2+1:2], dim), 2 ); + `check($high (array_bg[WA/2+1:2], dim), wdt+1); + `check($increment (array_bg[WA/2+1:2], dim), 1 ); + `check($size (array_bg[WA/2+1:2], dim), wdt); + end + end + end else if (cnt[30:4]==2) begin + // little endian + if (slc==0) begin + // full array + `check($dimensions (array_lt), 3); + `check($bits (array_lt), WA*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `check($left (array_lt, dim), 2 ); + `check($right (array_lt, dim), wdt+1); + `check($low (array_lt, dim), 2 ); + `check($high (array_lt, dim), wdt+1); + `check($increment (array_lt, dim), -1 ); + `check($size (array_lt, dim), wdt ); + end + end else if (slc==1) begin + // single array element + `check($dimensions (array_lt[2]), 2); + `check($bits (array_lt[2]), WB*WC); + if ((dim>=2)&&(dim<=3)) begin + `check($left (array_lt[2], dim-1), 2 ); + `check($right (array_lt[2], dim-1), wdt+1); + `check($low (array_lt[2], dim-1), 2 ); + `check($high (array_lt[2], dim-1), wdt+1); + `check($increment (array_lt[2], dim-1), -1 ); + `check($size (array_lt[2], dim-1), wdt ); + end + end else if (slc==2) begin + // half array + `check($dimensions (array_lt[2:WA/2+1]), 3); + `check($bits (array_lt[2:WA/2+1]), WA/2*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `check($left (array_lt[2:WA/2+1], dim), 2 ); + `check($right (array_lt[2:WA/2+1], dim), wdt+1); + `check($low (array_lt[2:WA/2+1], dim), 2 ); + `check($high (array_lt[2:WA/2+1], dim), wdt+1); + `check($increment (array_lt[2:WA/2+1], dim), -1 ); + `check($size (array_lt[2:WA/2+1], dim), wdt ); + end + end end end - + endmodule diff --git a/test_regress/t/t_array_query.v b/test_regress/t/t_array_query.v index bc72d3fcb..f65bae653 100644 --- a/test_regress/t/t_array_query.v +++ b/test_regress/t/t_array_query.v @@ -39,7 +39,9 @@ module array_test input clk; + // verilator lint_off LITENDIAN reg [7:0] a [LEFT:RIGHT]; + // verilator lint_on LITENDIAN integer l; integer r; @@ -54,10 +56,8 @@ module array_test $write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s); `endif - if ((l == LEFT) && (r == RIGHT) && (s == (RIGHT - LEFT + 1))) begin - $write("*-* All Finished *-*\n"); - end - + if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop; + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_bind2.v b/test_regress/t/t_bind2.v index 07b810e72..3470bf4b4 100644 --- a/test_regress/t/t_bind2.v +++ b/test_regress/t/t_bind2.v @@ -5,7 +5,7 @@ // verilator lint_off WIDTH -`define check(got,expec) do if ((got) != (expec)) begin $display("Line%0d: Got 0x%0x Exp 0x%0x\n", `__LINE__, (got), (expec)); $stop; end while(0); +`define check(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: Line%0d: got=0x%0x exp=0x%0x\n", `__LINE__, (gotv), (expv)); $stop; end while(0); module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_bitsel_struct2.v b/test_regress/t/t_bitsel_struct2.v index 27cb2cf91..a86c0d120 100644 --- a/test_regress/t/t_bitsel_struct2.v +++ b/test_regress/t/t_bitsel_struct2.v @@ -14,7 +14,7 @@ module t (/*AUTOARG*/); c_t [17:16] d; } e_t; -`define check(got,expec) do if ((got) != (expec)) begin $display("Line%0d: Got %b Exp %b\n", `__LINE__, (got), (expec)); $stop; end while(0); +`define check(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: Line%0d: got=0b%b exp=0b%b\n", `__LINE__, (gotv), (expv)); $stop; end while(0); initial begin e_t e;