diff --git a/src/V3AstNodeStmt.h b/src/V3AstNodeStmt.h
index e30a8a596..8fef497de 100644
--- a/src/V3AstNodeStmt.h
+++ b/src/V3AstNodeStmt.h
@@ -795,8 +795,10 @@ class AstLoop final : public AstNodeStmt {
     // @astgen op2 := contsp : List[AstNode] // Empty after LinkJump
     VOptionBool m_unroll;  // Full, none, or default unrolling
 public:
-    explicit AstLoop(FileLine* fl)
-        : ASTGEN_SUPER_Loop(fl) {}
+    explicit AstLoop(FileLine* fl, AstNode* stmtsp = nullptr)
+        : ASTGEN_SUPER_Loop(fl) {
+        addStmtsp(stmtsp);
+    }
     ASTGEN_MEMBERS_AstLoop;
     void dump(std::ostream& str) const override;
     void dumpJson(std::ostream& str) const override;
diff --git a/src/verilog.y b/src/verilog.y
index 19b81dfed..7c3a90de1 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3561,8 +3561,7 @@ statement_item<nodeStmtp>:          // IEEE: statement_item
         //
         // do/for/forever/while loops all modelled as AstLoop
         |       yDO stmt yWHILE '(' expr ')' ';'
-                        { AstLoop* const loopp = new AstLoop{$1};
-                          loopp->addStmtsp($2);
+                        { AstLoop* const loopp = new AstLoop{$1, $2};
                           loopp->addContsp(new AstLoopTest{$<fl>5, loopp, $5});
                           $$ = loopp; }
         |       yFOR  '(' { VARRESET_NONLIST(UNKNOWN); } for_initializationE ';' exprE ';' for_stepE ')' stmt
@@ -3574,8 +3573,7 @@ statement_item<nodeStmtp>:          // IEEE: statement_item
                           blockp->addStmtsp(loopp);
                           $$ = blockp; }
         |       yFOREVER stmt
-                        { AstLoop* const loopp = new AstLoop{$1};
-                          loopp->addStmtsp($2);
+                        { AstLoop* const loopp = new AstLoop{$1, $2};
                           $$ = loopp; }
         |       yWHILE '(' expr ')' stmt
                         { AstLoop* const loopp = new AstLoop{$1};