From 90c61c79d66206ef6ae0c40f90e71c7f2f69db42 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 5 Mar 2022 17:04:52 -0500
Subject: [PATCH] Fix unnamedblk error on foreach (#3321).

---
 Changes                           |  3 ++-
 src/V3LinkDot.cpp                 |  2 +-
 test_regress/t/t_foreach_iface.pl | 21 +++++++++++++++++++++
 test_regress/t/t_foreach_iface.v  | 28 ++++++++++++++++++++++++++++
 4 files changed, 52 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_foreach_iface.pl
 create mode 100644 test_regress/t/t_foreach_iface.v

diff --git a/Changes b/Changes
index bf67ba73d..551867530 100644
--- a/Changes
+++ b/Changes
@@ -21,8 +21,9 @@ Verilator 4.219 devel
 * Fix $readmem file not found to be warning not error (#3310). [Alexander Grobman]
 * Fix class stringification on wide arrays (#3312). [Iru Cai]
 * Fix public function arguments that are arrayed (#3316). [pawel256]
-* Fix compile error with --trace-fst --sc (#3332). [leavinel]
+* Fix unnamedblk error on foreach (#3321). [Aliaksei Chapyzhenka]
 * Fix crash in recursive module inlining (#3324). [Larry Doolittle]
+* Fix compile error with --trace-fst --sc (#3332). [leavinel]
 
 
 Verilator 4.218 2022-01-17
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index d6d29d5bd..d8c03df52 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -942,7 +942,7 @@ class LinkDotFindVisitor final : public VNVisitor {
             // places such as tasks, where "task ...; begin ... end"
             // are common.
             for (AstNode* stmtp = nodep->stmtsp(); stmtp; stmtp = stmtp->nextp()) {
-                if (VN_IS(stmtp, Var)) {
+                if (VN_IS(stmtp, Var) || VN_IS(stmtp, Foreach)) {
                     ++m_modBlockNum;
                     nodep->name("unnamedblk" + cvtToStr(m_modBlockNum));
                     break;
diff --git a/test_regress/t/t_foreach_iface.pl b/test_regress/t/t_foreach_iface.pl
new file mode 100755
index 000000000..1aa73f80a
--- /dev/null
+++ b/test_regress/t/t_foreach_iface.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_foreach_iface.v b/test_regress/t/t_foreach_iface.v
new file mode 100644
index 000000000..0412c6821
--- /dev/null
+++ b/test_regress/t/t_foreach_iface.v
@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Pawel Jewstafjew (Pawel.Jewstafjew@gmail.com).
+// SPDX-License-Identifier: CC0-1.0
+
+interface Iface (input bit [31:0] regs [1]);
+   initial begin
+      string instance_path = $sformatf("%m");
+      $display("Iface path %s\n", instance_path);
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+   bit [0:0] ppp;
+   always_comb begin
+      // Ok:
+      //for (int index = 1 ; index < 2 ; ++index) begin
+      foreach (regs[index]) begin
+         ppp[index] = 1;
+      end
+   end
+
+endinterface
+
+module top (input bit [31:0] regs [1]);
+   Iface t1(.regs(regs));
+endmodule