From 8a3227697e98b7d1e71ca3d01df9b8b9593e45ef Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 4 Nov 2019 22:00:20 -0500 Subject: [PATCH] Fix bad-syntax crashes, bug1579. --- Changes | 2 +- src/V3Width.cpp | 1 + test_regress/t/t_fuzz_triand_bad.out | 9 +++++++++ test_regress/t/t_fuzz_triand_bad.pl | 18 ++++++++++++++++++ test_regress/t/t_fuzz_triand_bad.v | 8 ++++++++ 5 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 test_regress/t/t_fuzz_triand_bad.out create mode 100755 test_regress/t/t_fuzz_triand_bad.pl create mode 100644 test_regress/t/t_fuzz_triand_bad.v diff --git a/Changes b/Changes index 99b8be577..eaeb01a25 100644 --- a/Changes +++ b/Changes @@ -27,7 +27,7 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Fix multithreaded yield behavior when no work. [Patrick Stewart] **** Fix bad-syntax crashes, bug1548, bug1550-1553, bug1557-1560, bug1563, - bug1573-1577, bug1582-1591. [Eric Rippey] + bug1573-1577, bug1579, bug1582-1591. [Eric Rippey] **** Fix false CMPCONST/UNSIGNED warnings on "inside", bug1581. [Mitch Hayenga] diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 94044c01a..a8db61d28 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -1562,6 +1562,7 @@ private: userIterateChildren(nodep, WidthVP(SELF, BOTH).p()); if (debug()>=9) nodep->dumpTree("-mbs-ic: "); // Find the fromp dtype - should be a class + if (!nodep->fromp()->dtypep()) nodep->fromp()->v3fatalSrc("Unlinked data type"); AstNodeDType* fromDtp = nodep->fromp()->dtypep()->skipRefToEnump(); UINFO(9," from dt "< 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_fuzz_triand_bad.v b/test_regress/t/t_fuzz_triand_bad.v new file mode 100644 index 000000000..7f07d18a9 --- /dev/null +++ b/test_regress/t/t_fuzz_triand_bad.v @@ -0,0 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t (); + tri g=g.and.g; +endmodule