From 88a2b0b911799f0b963955236205a6179121183e Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 2 Nov 2011 18:34:17 -0400
Subject: [PATCH] Support constants in sensitivity lists, bug412.

---
 Changes                        |  2 ++
 src/verilog.y                  |  9 +++++++--
 test_regress/t/t_alw_combdly.v | 12 ++++++++++--
 3 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/Changes b/Changes
index e2ac21f46..ff7852b0c 100644
--- a/Changes
+++ b/Changes
@@ -10,6 +10,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Search for user -y paths before default current directory.  [Ruben Diez]
 
+**** Support constants in sensitivity lists, bug412.  [Jeremy Bennett]
+
 **** Indicate 'exiting due to errors' if errors, not warnings. [Ruben Diez]
 
 **** Fix reporting not found modules if generate-off, bug403. [Jeremy Bennett]
diff --git a/src/verilog.y b/src/verilog.y
index 196241e6c..ba46dafe7 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1768,8 +1768,8 @@ event_control<sentreep>:	// ==IEEE: event_control
 
 event_expression<senitemp>:	// IEEE: event_expression - split over several
 		senitem					{ $$ = $1; }
-	|	event_expression yOR senitem		{ $$ = $1;$1->addNext($3); }
-	|	event_expression ',' senitem		{ $$ = $1;$1->addNext($3); }	/* Verilog 2001 */
+	|	event_expression yOR senitem		{ $$ = $1;$1->addNextNull($3); }
+	|	event_expression ',' senitem		{ $$ = $1;$1->addNextNull($3); }	/* Verilog 2001 */
 	;
 
 senitem<senitemp>:		// IEEE: part of event_expression, non-'OR' ',' terms
@@ -1778,6 +1778,11 @@ senitem<senitemp>:		// IEEE: part of event_expression, non-'OR' ',' terms
 	|	'(' senitemVar ')'			{ $$ = $2; }
 	//UNSUP	expr					{ UNSUP }
 	//UNSUP	expr yIFF expr				{ UNSUP }
+	// Since expr is unsupported we allow and ignore constants (removed in V3Const)
+	|	yaINTNUM				{ $$ = NULL; }
+	|	yaFLOATNUM				{ $$ = NULL; }
+	|	'(' yaINTNUM ')'			{ $$ = NULL; }
+	|	'(' yaFLOATNUM ')'			{ $$ = NULL; }
 	;
 
 senitemVar<senitemp>:
diff --git a/test_regress/t/t_alw_combdly.v b/test_regress/t/t_alw_combdly.v
index 08487611c..5e147eea6 100644
--- a/test_regress/t/t_alw_combdly.v
+++ b/test_regress/t/t_alw_combdly.v
@@ -11,7 +11,7 @@ module t (/*AUTOARG*/
    input clk;
    integer cyc; initial cyc=1;
 
-   reg [31:0] a, b, c, d, e;
+   reg [31:0] a, b, c, d, e, f, g;
 
    always @ (*) begin   // Test Verilog 2001 (*)
       // verilator lint_off COMBDLY
@@ -25,6 +25,14 @@ module t (/*AUTOARG*/
    always @ ((d)) begin // always bug 2008/4/18
       e = d;
    end
+
+   parameter CONSTANT = 1;
+   always @ (e, 1'b0, CONSTANT) begin // not technically legal, see bug412
+      f = e;
+   end
+   always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412
+      g = f;
+   end
    //always @ ((posedge b) or (a or b)) begin // note both illegal
 
    always @ (posedge clk) begin
@@ -38,7 +46,7 @@ module t (/*AUTOARG*/
 	    if (c != 32'hfeedface) $stop;
 	 end
 	 if (cyc==3) begin
-	    if (e != 32'hfeedface) $stop;
+	    if (g != 32'hfeedface) $stop;
 	 end
 	 if (cyc==7) begin
 	    $write("*-* All Finished *-*\n");