From 87e4a86fbbb33d9e075041e1f60f887062cd7ac7 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 18 Sep 2020 21:27:36 -0400 Subject: [PATCH] Internal coverage improvements --- include/verilated.cpp | 9 +++-- include/verilated_threads.cpp | 2 +- nodist/code_coverage.dat | 1 + test_regress/input.vc | 2 +- test_regress/t/t_debug_emitv.out | 8 ++++- test_regress/t/t_debug_emitv.v | 5 ++- test_regress/t/t_dpi_export_context2_bad.cpp | 35 ++++++++++++++++++++ test_regress/t/t_dpi_export_context2_bad.out | 2 ++ test_regress/t/t_dpi_export_context2_bad.pl | 24 ++++++++++++++ test_regress/t/t_dpi_export_context2_bad.v | 19 +++++++++++ test_regress/t/t_lint_unused_bad.pl | 3 +- test_regress/t/t_lint_unused_bad.v | 3 ++ test_regress/t/t_runflag_bad.out | 2 ++ test_regress/t/t_runflag_bad.pl | 24 ++++++++++++++ test_regress/t/t_runflag_bad.v | 12 +++++++ test_regress/t/t_sys_file_basic.v | 8 +++++ test_regress/t/t_sys_file_basic_input.dat | 1 + 17 files changed, 152 insertions(+), 8 deletions(-) create mode 100644 test_regress/t/t_dpi_export_context2_bad.cpp create mode 100644 test_regress/t/t_dpi_export_context2_bad.out create mode 100755 test_regress/t/t_dpi_export_context2_bad.pl create mode 100644 test_regress/t/t_dpi_export_context2_bad.v create mode 100644 test_regress/t/t_runflag_bad.out create mode 100755 test_regress/t/t_runflag_bad.pl create mode 100644 test_regress/t/t_runflag_bad.v diff --git a/include/verilated.cpp b/include/verilated.cpp index fe450ab25..00600f7ca 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -913,10 +913,11 @@ void _vl_vsformat(std::string& output, const char* formatp, va_list ap) VL_MT_SA output += "0123456789abcdef"[charval]; } break; - default: + default: { // LCOV_EXCL_START std::string msg = std::string("Unknown _vl_vsformat code: ") + pos[0]; VL_FATAL_MT(__FILE__, __LINE__, "", msg.c_str()); break; + } // LCOV_EXCL_STOP } // switch } } // switch @@ -1182,10 +1183,12 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf } break; } - default: + default: { // LCOV_EXCL_START std::string msg = std::string("Unknown _vl_vsscanf code: ") + pos[0]; VL_FATAL_MT(__FILE__, __LINE__, "", msg.c_str()); break; + } // LCOV_EXCL_STOP + } // switch if (!inIgnore) ++got; @@ -2596,7 +2599,7 @@ vluint32_t VerilatedVarProps::entSize() const { case VLVT_UINT32: size = sizeof(IData); break; case VLVT_UINT64: size = sizeof(QData); break; case VLVT_WDATA: size = VL_WORDS_I(packed().elements()) * sizeof(IData); break; - default: size = 0; break; + default: size = 0; break; // LCOV_EXCL_LINE } return size; } diff --git a/include/verilated_threads.cpp b/include/verilated_threads.cpp index 4edd9db71..1a6d1277e 100644 --- a/include/verilated_threads.cpp +++ b/include/verilated_threads.cpp @@ -139,7 +139,7 @@ void VlThreadPool::profileDump(const char* filenamep, vluint64_t ticksElapsed) { if (VL_UNLIKELY(!fp)) { VL_FATAL_MT(filenamep, 0, "", "+prof+threads+file file not writable"); // cppcheck-suppress resourceLeak // bug, doesn't realize fp is nullptr - return; + return; // LCOV_EXCL_LINE } // TODO Perhaps merge with verilated_coverage output format, so can diff --git a/nodist/code_coverage.dat b/nodist/code_coverage.dat index fc3beb3ee..f4aacd760 100644 --- a/nodist/code_coverage.dat +++ b/nodist/code_coverage.dat @@ -46,6 +46,7 @@ remove_gcda_regexp(qr!test_regress/.*/(Vt_|Vtop_).*\.gcda!); exclude_line_regexp(qr/(\bv3fatalSrc\b |\bfatalSrc\b |\bVL_UNCOVERABLE\b + |\bVL_UNREACHABLE\b |\bVL_FATAL |\bUASSERT |\bNUM_ASSERT diff --git a/test_regress/input.vc b/test_regress/input.vc index 77e6ce27e..b394985f6 100644 --- a/test_regress/input.vc +++ b/test_regress/input.vc @@ -1,5 +1,5 @@ -+librescan +libext+.v ++librescan +notimingchecks +libext+.v -y t +incdir+t +incdir+../include diff --git a/test_regress/t/t_debug_emitv.out b/test_regress/t/t_debug_emitv.out index 1170727af..39df56002 100644 --- a/test_regress/t/t_debug_emitv.out +++ b/test_regress/t/t_debug_emitv.out @@ -5,6 +5,7 @@ module Vt_debug_emitv; logic logic [15:0] t.pubflat; logic logic [15:0] t.pubflat_r; int signed int [31:0] t.fd; + int signed int [31:0] t.i; int signed int [31:0] t.cyc; int signed int [31:0] t.fo; int signed int [31:0] t.sum; @@ -76,7 +77,7 @@ module Vt_debug_emitv; end end t.sum = __Vfunc_t.sub.f__3__Vfuncout; - $display("sum = %~", t.sum); + $display("[%0t] sum = %~", $timet.sum, t.sum); $c(;); $display("%d", $c(0)); $fopen(72'h2f6465762f6e756c6c); @@ -165,6 +166,11 @@ module Vt_debug_emitv; ; $display("str = %@", t.str); $display("[%t] [%^]", $time$realtime, $realtime); + $sscanf(40'h666f6f3d35, "foo=%d", t.i); + ; + if ((32'sh5 != t.i)) begin + $stop; + end end /*verilator public_flat_rw @(posedge clk)@(negedge clk) t.pubflat*/ diff --git a/test_regress/t/t_debug_emitv.v b/test_regress/t/t_debug_emitv.v index 073485457..67aa6bca8 100644 --- a/test_regress/t/t_debug_emitv.v +++ b/test_regress/t/t_debug_emitv.v @@ -37,6 +37,7 @@ module t (/*AUTOARG*/ reg [15:0] pubflat_r; wire [15:0] pubflat_w = pubflat; int fd; + int i; task t; $display("stmt"); @@ -85,7 +86,7 @@ module t (/*AUTOARG*/ fo = cyc; sub.inc(fo, sum); sum = sub.f(sum); - $display("sum = %d", sum); + $display("[%0t] sum = %d", $time, sum); $c(";"); $display("%d", $c("0")); @@ -136,6 +137,8 @@ module t (/*AUTOARG*/ str = $sformatf("cyc=%d", cyc); $display("str = %s", str); $display("[%t] [%t]", $time, $realtime); + $sscanf("foo=5", "foo=%d", i); + if (i != 5) $stop; end endmodule diff --git a/test_regress/t/t_dpi_export_context2_bad.cpp b/test_regress/t/t_dpi_export_context2_bad.cpp new file mode 100644 index 000000000..b71f678d7 --- /dev/null +++ b/test_regress/t/t_dpi_export_context2_bad.cpp @@ -0,0 +1,35 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include +#include VM_PREFIX_INCLUDE + +//====================================================================== + +#include "Vt_dpi_export_context2_bad__Dpi.h" + +//====================================================================== + +unsigned int main_time = 0; + +double sc_time_stamp() { return main_time; } + +VM_PREFIX* topp = nullptr; + +int main(int argc, char* argv[]) { + topp = new VM_PREFIX; + + Verilated::debug(0); + + topp->eval(); + return 1; +} +int dpii_task() { + dpix_task(); + return 0; +} diff --git a/test_regress/t/t_dpi_export_context2_bad.out b/test_regress/t/t_dpi_export_context2_bad.out new file mode 100644 index 000000000..dc2091af3 --- /dev/null +++ b/test_regress/t/t_dpi_export_context2_bad.out @@ -0,0 +1,2 @@ +%Error: unknown:0: Testbench C called 'dpix_task' but scope wasn't set, perhaps due to dpi import call without 'context', or missing svSetScope. See IEEE 1800-2017 35.5.3. +Aborting... diff --git a/test_regress/t/t_dpi_export_context2_bad.pl b/test_regress/t/t_dpi_export_context2_bad.pl new file mode 100755 index 000000000..93b856ef1 --- /dev/null +++ b/test_regress/t/t_dpi_export_context2_bad.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + v_flags2 => ["--exe $Self->{t_dir}/t_dpi_export_context2_bad.cpp"], + make_main => 0, + ); + +execute( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_dpi_export_context2_bad.v b/test_regress/t/t_dpi_export_context2_bad.v new file mode 100644 index 000000000..5002b95e2 --- /dev/null +++ b/test_regress/t/t_dpi_export_context2_bad.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2020 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +module t; + export "DPI-C" task dpix_task; + sub sub (); + task dpix_task(); + $write("Hello in %m\n"); + endtask +endmodule +module sub; + import "DPI-C" task dpii_task; + initial dpii_task; +endmodule diff --git a/test_regress/t/t_lint_unused_bad.pl b/test_regress/t/t_lint_unused_bad.pl index ca7a27539..feee5f9e4 100755 --- a/test_regress/t/t_lint_unused_bad.pl +++ b/test_regress/t/t_lint_unused_bad.pl @@ -11,7 +11,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(linter => 1); lint( - verilator_flags2 => ["--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME"], + verilator_flags2 => ["--lint-only --bbox-sys --bbox-unsup -Wall -Wno-DECLFILENAME", + "--unused-regexp 'cmdln*'"], fails => 1, expect_filename => $Self->{golden_filename}, ); diff --git a/test_regress/t/t_lint_unused_bad.v b/test_regress/t/t_lint_unused_bad.v index 9ee42b607..839527590 100644 --- a/test_regress/t/t_lint_unused_bad.v +++ b/test_regress/t/t_lint_unused_bad.v @@ -29,6 +29,9 @@ module sub; assign mixed[2] = 0; assign mixed[0] = 0; + wire [2:0] cmdln_off; // Suppressed by command line + assign cmdln_off = 0; + localparam THREE = 3; initial begin diff --git a/test_regress/t/t_runflag_bad.out b/test_regress/t/t_runflag_bad.out new file mode 100644 index 000000000..32330deaf --- /dev/null +++ b/test_regress/t/t_runflag_bad.out @@ -0,0 +1,2 @@ +%Warning: Unknown +verilator runtime argument: '+verilator+bad+flag+testing' +*-* All Finished *-* diff --git a/test_regress/t/t_runflag_bad.pl b/test_regress/t/t_runflag_bad.pl new file mode 100755 index 000000000..7f6ecf79f --- /dev/null +++ b/test_regress/t/t_runflag_bad.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt_all => 1); + +compile( + ); + +execute( + all_run_flags => ["+verilator+bad+flag+testing"], + #fails => 1, # doesn't fail just prints + expect_filename => $Self->{golden_filename}, + ); + +ok(1); + +1; diff --git a/test_regress/t/t_runflag_bad.v b/test_regress/t/t_runflag_bad.v new file mode 100644 index 000000000..cfcf3ba54 --- /dev/null +++ b/test_regress/t/t_runflag_bad.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_sys_file_basic.v b/test_regress/t/t_sys_file_basic.v index 9497d3a2a..27dc4c785 100644 --- a/test_regress/t/t_sys_file_basic.v +++ b/test_regress/t/t_sys_file_basic.v @@ -18,6 +18,7 @@ module t; integer chars; reg [1*8:1] letterl; reg [8*8:1] letterq; + reg signed [8*8:1] letterqs; reg [16*8:1] letterw; reg [16*8:1] letterz; real r; @@ -220,6 +221,13 @@ module t; if (chars != 1) $stop; if (letterq != 64'hfffffffffffc65a5) $stop; + if (!sync("\n")) $stop; + if (!sync("*")) $stop; + chars = $fscanf(file, "u=%d", letterqs); + if (`verbose) $write("c=%0d u=%0x\n", chars, letterqs); + if (chars != 1) $stop; + if (letterqs != -236124) $stop; + if (!sync("\n")) $stop; if (!sync("*")) $stop; chars = $fscanf(file, "%c%s", letterl, letterw); diff --git a/test_regress/t/t_sys_file_basic_input.dat b/test_regress/t/t_sys_file_basic_input.dat index 67437584c..0e640b4ed 100644 --- a/test_regress/t/t_sys_file_basic_input.dat +++ b/test_regress/t/t_sys_file_basic_input.dat @@ -5,5 +5,6 @@ widestuff *ba=10 bb=11010010101001010101 note_the_two *oa=23 ob=12563 *d=-236123 +*u=-236124 *fredfishblah 12346789