From 8738a514499c44b070f76ab6dc6a4b447369b39a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 17 Jan 2007 21:19:29 +0000 Subject: [PATCH] Add combo test git-svn-id: file://localhost/svn/verilator/trunk/verilator@870 77ca24e4-aefa-0310-84f0-b9a241c72d87 --- test_regress/driver.pl | 2 +- test_regress/t/t_unopt_combo.pl | 19 +++++ test_regress/t/t_unopt_combo.v | 112 ++++++++++++++++++++++++++++ test_regress/t/t_unopt_combo_bad.pl | 29 +++++++ 4 files changed, 161 insertions(+), 1 deletion(-) create mode 100755 test_regress/t/t_unopt_combo.pl create mode 100644 test_regress/t/t_unopt_combo.v create mode 100755 test_regress/t/t_unopt_combo_bad.pl diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 08b5de2cc..629a22ce6 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -190,7 +190,7 @@ sub new { make_main => 1, # Make __main.cpp # All compilers v_flags => [split(/\s+/,(" -f input.vc --debug-check" - .($opt_verbose ? " +define+TEST_VERBOSE+1":"") + .($opt_verbose ? " +define+TEST_VERBOSE=1":"") ))], v_flags2 => [], # Overridden in some sim files v_other_filenames => [], # After the filename so we can spec multiple files diff --git a/test_regress/t/t_unopt_combo.pl b/test_regress/t/t_unopt_combo.pl new file mode 100755 index 000000000..0583bc033 --- /dev/null +++ b/test_regress/t/t_unopt_combo.pl @@ -0,0 +1,19 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } +# $Id$ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# General Public License or the Perl Artistic License. + +compile ( + v_flags2 => ['-DALLOW_UNOPT'], + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_unopt_combo.v b/test_regress/t/t_unopt_combo.v new file mode 100644 index 000000000..9d59b542a --- /dev/null +++ b/test_regress/t/t_unopt_combo.v @@ -0,0 +1,112 @@ +// $Id$ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2005 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + integer cyc; initial cyc=0; + reg [63:0] crc; + reg [63:0] sum; + +`ifdef ALLOW_UNOPT + /*verilator lint_off UNOPTFLAT*/ +`endif + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [31:0] b; // From file of file.v + wire [31:0] c; // From file of file.v + wire [31:0] d; // From file of file.v + // End of automatics + + file file (/*AUTOINST*/ + // Outputs + .b (b[31:0]), + .c (c[31:0]), + .d (d[31:0]), + // Inputs + .crc (crc[31:0])); + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc=%0d crc=%x sum=%x b=%x d=%x\n",$time,cyc,crc,sum, b, d); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= {b, d} + ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum); + if (crc != 64'hc77bb9b3784ea091) $stop; + if (sum != 64'he281f003f6dd16b2) $stop; + $finish; + end + end + +endmodule + +module file (/*AUTOARG*/ + // Outputs + b, c, d, + // Inputs + crc + ); + + input [31:0] crc; + output reg [31:0] b; + output reg [31:0] c; + output reg [31:0] d; + + always @* begin + // Note that while c and b depend on crc, b doesn't depend on c. + casez (crc[3:0]) + 4'b??01: begin + b = {crc[15:0],crc[31:16]}; + d = c; + end + 4'b??00: begin + b = {crc[15:0],~crc[31:16]}; + d = {crc[15:0],~c[31:16]}; + end + default: begin + b = ~crc; + d = ~c; + end + endcase + end + + always @* begin + // Any complicated equation we can't optimize + casez (crc[3:0]) + 4'b00??: begin + c = {b[29:0],2'b11}; + end + 4'b01??: begin + c = {b[30:1],2'b01}; + end + 4'b10??: begin + c = {b[31:2],2'b10}; + end + 4'b11??: begin + c = {b[31:2],2'b00}; + end + endcase + end + +endmodule diff --git a/test_regress/t/t_unopt_combo_bad.pl b/test_regress/t/t_unopt_combo_bad.pl new file mode 100755 index 000000000..ead03c03c --- /dev/null +++ b/test_regress/t/t_unopt_combo_bad.pl @@ -0,0 +1,29 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } +# $Id$ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# General Public License or the Perl Artistic License. + +top_filename("t/t_unopt_combo.v"); + +compile ( + fails=>$Last_Self->{v3}, + expect=> +'%Warning-UNOPTFLAT: t/t_unopt_combo.v:\d+: Signal unoptimizable: Feedback to clock or circular logic: TOP->v.c +%Warning-UNOPTFLAT: Use "/\* verilator lint_off UNOPTFLAT \*/" and lint_on around source to disable this message. +%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: TOP->v.c +%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: ALWAYS +%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: TOP->v.b +%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: ALWAYS +%Warning-UNOPTFLAT: Example path: t/t_unopt_combo.v:\d+: TOP->v.c +%Error: Exiting due to ' + ); + +execute ( + ) if !$Last_Self->{v3}; + +ok(1); +1;