diff --git a/src/verilog.l b/src/verilog.l index 639a908a4..9e7bfe74d 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -530,7 +530,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "rand" { FL; return yRAND; } "randc" { FL; return yRANDC; } "randcase" { FL; return yRANDCASE; } - "randomize" { ERROR_RSVD_WORD("SystemVerilog 2005"); } + "randomize" { FL; return yRANDOMIZE; } "randsequence" { ERROR_RSVD_WORD("SystemVerilog 2005"); } "ref" { FL; return yREF; } "restrict" { FL; return yRESTRICT; } diff --git a/src/verilog.y b/src/verilog.y index e8a2bc2d6..816664c5e 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -562,6 +562,7 @@ class AstSenTree; %token yRAND "rand" %token yRANDC "randc" %token yRANDCASE "randcase" +%token yRANDOMIZE "randomize" //UNSUP %token yRANDSEQUENCE "randsequence" %token yRCMOS "rcmos" %token yREAL "real" @@ -3363,7 +3364,8 @@ funcRef: // IEEE: part of tf_call // // sequence_instance sequence_identifier sequence_actual_arg // // let_expression let_identifier let_actual_arg // - id '(' list_of_argumentsE ')' { $$ = new AstFuncRef($1, *$1, $3); } + id '(' list_of_argumentsE ')' + { $$ = new AstFuncRef($1, *$1, $3); } | package_scopeIdFollows id '(' list_of_argumentsE ')' { $$ = AstDot::newIfPkg($2, $1, new AstFuncRef($2,*$2,$4)); } | class_scopeIdFollows id '(' list_of_argumentsE ')' @@ -3401,7 +3403,9 @@ function_subroutine_callNoMethod: // IEEE: function_subroutine_call (as f // // IEEE: randomize_call // // We implement randomize as a normal funcRef, since randomize isn't a keyword // // Note yNULL is already part of expressions, so they come for free - //UNSUP funcRef yWITH__CUR constraint_block { } + //UNSUP funcRef yWITH__CUR constraint_block { $$ = $1; BBUNSUP($2, "Unsupported: randomize() 'with'"); } + //UNSUP remove the next line, temporary until have constraint_block (but enough for UVM parsing) + | funcRef yWITH__CUR '{' '}' { $$ = $1; BBUNSUP($2, "Unsupported: randomize() 'with'"); } ; system_t_call: // IEEE: system_tf_call (as task) @@ -4613,12 +4617,14 @@ junkToSemi: id: yaID__ETC { $$ = $1; $$=$1; } + | idRandomize { $$ = $1; $$=$1; } ; idAny: // Any kind of identifier yaID__aPACKAGE { $$ = $1; $$=$1; } | yaID__aTYPE { $$ = $1; $$=$1; } | yaID__ETC { $$ = $1; $$=$1; } + | idRandomize { $$ = $1; $$=$1; } ; idType: // IEEE: class_identifier or other type identifier @@ -4626,6 +4632,10 @@ idType: // IEEE: class_identifier or other type identifier yaID__aTYPE { $$ = $1; $$=$1; } ; +idRandomize: // Keyword as an identifier + yRANDOMIZE { static string s = "randomize"; $$ = &s; $$ = $1; } + ; + idSVKwd: // Warn about non-forward compatible Verilog 2001 code // // yBIT, yBYTE won't work here as causes conflicts yDO { static string s = "do" ; $$ = &s; ERRSVKWD($1,*$$); $$=$1; } diff --git a/test_regress/t/t_flag_wpedantic_bad.out b/test_regress/t/t_flag_wpedantic_bad.out index 4e9ac3f1b..85f687f33 100644 --- a/test_regress/t/t_flag_wpedantic_bad.out +++ b/test_regress/t/t_flag_wpedantic_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_flag_wpedantic_bad.v:8:14: syntax error, unexpected global, expecting IDENTIFIER or '=' or do or final +%Error: t/t_flag_wpedantic_bad.v:8:14: syntax error, unexpected global 8 | reg global; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_preproc_inc_bad.out b/test_regress/t/t_preproc_inc_bad.out index 295d92512..b03e7f868 100644 --- a/test_regress/t/t_preproc_inc_bad.out +++ b/test_regress/t/t_preproc_inc_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_preproc_inc_inc_bad.vh:11:1: syntax error, unexpected endmodule, expecting IDENTIFIER +%Error: t/t_preproc_inc_inc_bad.vh:11:1: syntax error, unexpected endmodule, expecting IDENTIFIER or randomize 11 | endmodule | ^~~~~~~~~ t/t_preproc_inc_bad.v:10:1: ... note: In file included from t_preproc_inc_bad.v diff --git a/test_regress/t/t_randomize.out b/test_regress/t/t_randomize.out new file mode 100644 index 000000000..2a5c996f7 --- /dev/null +++ b/test_regress/t/t_randomize.out @@ -0,0 +1,4 @@ +%Error: t/t_randomize.v:25:25: Unsupported: randomize() 'with' + 25 | v = p.randomize() with {}; + | ^~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_randomize.pl b/test_regress/t/t_randomize.pl new file mode 100755 index 000000000..63947fd00 --- /dev/null +++ b/test_regress/t/t_randomize.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_randomize.v b/test_regress/t/t_randomize.v new file mode 100644 index 000000000..e5842cb22 --- /dev/null +++ b/test_regress/t/t_randomize.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +class Packet; + rand int header; + rand int length; +endclass + +module t (/*AUTOARG*/); + + Packet p; + + initial begin + + int v; + v = p.randomize(); + if (v != 1) $stop; + v = p.randomize(1); + if (v != 1) $stop; + v = p.randomize(1, 2); + if (v != 1) $stop; + v = p.randomize() with {}; + if (v != 1) $stop; + // Not testing other randomize forms as unused in UVM + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_udp_noname.out b/test_regress/t/t_udp_noname.out index c82b2ceaf..e92964be4 100644 --- a/test_regress/t/t_udp_noname.out +++ b/test_regress/t/t_udp_noname.out @@ -1,4 +1,4 @@ -%Error: t/t_udp_noname.v:15:9: syntax error, unexpected '(', expecting IDENTIFIER +%Error: t/t_udp_noname.v:15:9: syntax error, unexpected '(', expecting IDENTIFIER or randomize 15 | udp (o, a); | ^ %Error: Exiting due to diff --git a/test_regress/t/t_vams_kwd_bad.out b/test_regress/t/t_vams_kwd_bad.out index 739550c49..dfbd90b40 100644 --- a/test_regress/t/t_vams_kwd_bad.out +++ b/test_regress/t/t_vams_kwd_bad.out @@ -1,7 +1,7 @@ %Error: t/t_vams_kwd_bad.v:12:8: Unsupported: AMS reserved word not implemented: 'above' 12 | int above; | ^~~~~ -%Error: t/t_vams_kwd_bad.v:12:13: syntax error, unexpected ';', expecting IDENTIFIER +%Error: t/t_vams_kwd_bad.v:12:13: syntax error, unexpected ';', expecting IDENTIFIER or randomize 12 | int above; | ^ %Error: t/t_vams_kwd_bad.v:13:8: Unsupported: AMS reserved word not implemented: 'abs'