diff --git a/Changes b/Changes
index 44758dd21..76f32e894 100644
--- a/Changes
+++ b/Changes
@@ -32,6 +32,7 @@ Verilator 5.039 devel
 * Fix param-dependent class typedef linking (#6171). [Igor Zaworski, Antmicro Ltd.]
 * Fix `--coverage-expr` null pointer dereference (#6181). [Igor Zaworski, Antmicro Ltd.]
 * Fix conflicting function/class name linking error (#6182). [Igor Zaworski, Antmicro Ltd.]
+* Fix structure select causing 'Wide Op' error (#6191). [Danny Oler]
 
 
 Verilator 5.038 2025-07-08
diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index 3307eedfc..c4c460645 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -1110,6 +1110,9 @@ AstNode* AstArraySel::baseFromp(AstNode* nodep, bool overMembers) {
         } else if (overMembers && VN_IS(nodep, MemberSel)) {
             nodep = VN_AS(nodep, MemberSel)->fromp();
             continue;
+        } else if (overMembers && VN_IS(nodep, StructSel)) {
+            nodep = VN_AS(nodep, StructSel)->fromp();
+            continue;
         }
         // AstNodePreSel stashes the associated variable under an ATTROF
         // of VAttrType::VAR_BASE so it isn't constified
diff --git a/test_regress/t/t_unpacked_wide_unknown.py b/test_regress/t/t_unpacked_wide_unknown.py
new file mode 100755
index 000000000..bd059b0f2
--- /dev/null
+++ b/test_regress/t/t_unpacked_wide_unknown.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=['--binary'])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_unpacked_wide_unknown.v b/test_regress/t/t_unpacked_wide_unknown.v
new file mode 100644
index 000000000..208f99481
--- /dev/null
+++ b/test_regress/t/t_unpacked_wide_unknown.v
@@ -0,0 +1,44 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef struct packed {
+  logic [149:0] hdr;
+  logic [1:0]   vc;
+} packet_t;
+
+module t;
+
+  logic clk;
+
+  typedef struct {packet_t [1:0] pkt_i;} dut_if_t;
+
+  dut_if_t dut[2];
+
+  initial begin
+    clk = 0;
+    forever #(0.5) clk = ~clk;
+  end
+
+  task automatic send_req_packets(int module_id, int channel);
+    packet_t packet = '0;
+    dut[module_id].pkt_i[channel] = packet;
+    @(posedge clk);  // If you comment out this line. It will build.
+  endtask
+
+  initial begin
+    for (int m = 0; m < 2; m++) begin
+      for (int i = 0; i < 2; i++) begin
+        automatic int mod = m;
+        automatic int ch = i;
+        send_req_packets(mod, ch);
+      end
+    end
+
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule