diff --git a/Changes b/Changes index 3cec0001a..5e4c7d316 100644 --- a/Changes +++ b/Changes @@ -3,6 +3,10 @@ Revision history for Verilator The contributors that suggested a given feature are shown in []. [by ...] indicates the contributor was also the author of the fix; Thanks! +* Verilator 3.62*** + +**** Fix dotted references inside generated cells. [David Hewson] + * Verilator 3.623 12/05/2006 *** Add --output-split-cfuncs for accelerating GCC compile. [Eugene Weber] diff --git a/bin/verilator b/bin/verilator index a5fe01ce2..670ede256 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1626,6 +1626,12 @@ complex, since Verilator emits standard C++ code, you can simply write your own C++ routines that can access and modify signal values without needing any PLI interface code, and call it with $c("{any_c++_statement}"). +=item How do I make a Verilog module that contain a C++ object? + +You need to add the object to the structure that Verilator creates, then +use $c to call a method inside your object. The +test_regress/t/t_extend_class files show an example of how to do this. + =item How do I get faster build times? Between GCC 3.0 to 3.3, each compiled progressively slower, thus if you can diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index 99d466807..70702976a 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -200,7 +200,7 @@ private: } // Save some time - virtual void visit(AstNodeStmt*, AstNUser*) {} + virtual void visit(AstNodeMath*, AstNUser*) {} //-------------------- // Default: Just iterate virtual void visit(AstNode* nodep, AstNUser*) { diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 7f3975c72..30534f9a0 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -353,8 +353,11 @@ private: } virtual void visit(AstCell* nodep, AstNUser*) { UINFO(5," CELL under "<iterateChildren(*this); // Recurse in, preserving state string oldscope = m_scope; + AstBegin* oldbeginp = m_beginp; LinkDotCellVertex* oldVxp = m_cellVxp; // Where do we add it? LinkDotBaseVertex* aboveVxp = m_cellVxp; @@ -371,9 +374,11 @@ private: m_scope = m_scope+"."+nodep->name(); m_cellVxp = m_statep->insertCell(aboveVxp, m_cellVxp, nodep, m_scope); m_inlineVxp = m_cellVxp; + m_beginp = NULL; if (nodep->modp()) nodep->modp()->accept(*this); } m_scope = oldscope; + m_beginp = oldbeginp; m_cellVxp = oldVxp; m_inlineVxp = m_cellVxp; } @@ -407,6 +412,8 @@ private: && !m_beginp // For now, we don't support xrefs into begin blocks && !nodep->isFuncLocal()) { m_statep->insertSym(m_cellVxp, nodep->name(), nodep); + } else { + UINFO(9," Not allowing dot refs to: "<iterateChildren(*this); } // For speed, don't recurse things that can't have scope + // Note we allow AstNodeStmt's as generates may be under them virtual void visit(AstCell*, AstNUser*) {} virtual void visit(AstVar*, AstNUser*) {} - virtual void visit(AstNodeStmt*, AstNUser*) {} virtual void visit(AstNodeMath*, AstNUser*) {} virtual void visit(AstNode* nodep, AstNUser*) { // Default: Just iterate diff --git a/test_regress/t/t_gen_intdot.pl b/test_regress/t/t_gen_intdot.pl new file mode 100755 index 000000000..7bfdbe852 --- /dev/null +++ b/test_regress/t/t_gen_intdot.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } +# $Id$ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# General Public License or the Perl Artistic License. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_gen_intdot.v b/test_regress/t/t_gen_intdot.v new file mode 100644 index 000000000..f3c684ed9 --- /dev/null +++ b/test_regress/t/t_gen_intdot.v @@ -0,0 +1,93 @@ +// $Id$ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2003-2006 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + integer cyc=0; + + wire out; + reg in; + + Genit g (.clk(clk), .value(in), .result(out)); + + always @ (posedge clk) begin + //$write("[%0t] cyc==%0d %x %x\n",$time, cyc, in, out); + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + in <= 1'b1; + end + else if (cyc==1) begin + in <= 1'b0; + end + else if (cyc==2) begin + if (out != 1'b1) $stop; + end + else if (cyc==3) begin + if (out != 1'b0) $stop; + end + else if (cyc==9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Generate (clk, value, result); + input clk; + input value; + output result; + + reg Internal; + + assign result = Internal ^ clk; + + always @(posedge clk) + Internal <= #1 value; +endmodule + +module Checker (clk, value); + input clk, value; + + always @(posedge clk) begin + $write ("[%0t] value=%h\n", $time, value); + end + +endmodule + +module Test (clk, value, result); + input clk; + input value; + output result; + + Generate gen (clk, value, result); + Checker chk (clk, gen.Internal); + +endmodule + +module Genit (clk, value, result); + input clk; + input value; + output result; + +`define WITH_GENERATE +`ifdef WITH_GENERATE + genvar i; + generate + for (i = 0; i < 1; i = i + 1) + begin : gen + Test t (clk, value, result); + end + endgenerate +`else + Test t (clk, value, result); +`endif +endmodule +