From 851b022c7aeb8d840b87bd1766a163260f08574d Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 5 May 2009 13:39:25 -0400 Subject: [PATCH] Change lexer to more closely match Verilog-Perl. Should be no functional change --- nodist/flexdiff | 61 +++ src/verilog.l | 977 +++++++++++++++++++++++++----------------------- src/verilog.y | 16 +- 3 files changed, 593 insertions(+), 461 deletions(-) create mode 100755 nodist/flexdiff diff --git a/nodist/flexdiff b/nodist/flexdiff new file mode 100755 index 000000000..ee6e0f28a --- /dev/null +++ b/nodist/flexdiff @@ -0,0 +1,61 @@ +#!/usr/bin/perl -w +###################################################################### +# +# Copyright 2007-2009 by Wilson Snyder. This package is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +###################################################################### + +# DESCRIPTION: Diff flex files + +use IO::File; +use strict; + +my $Debug; + +diff($ARGV[0],$ARGV[1]); + +sub diff { + my $a=shift; + my $b=shift; + + my $ta = "/tmp/flexdiff.$$.a"; + my $tb = "/tmp/flexdiff.$$.b"; + + prep($a,$ta); + prep($b,$tb); + + system("diff -u -w $ta $tb"); +} + +sub prep { + my $filename = shift; + my $wfilename = shift; + + my $fh = IO::File->new("<$filename") or die "%Error: $! $filename"; + my $fho = IO::File->new(">$wfilename") or die "%Error: $! writing $wfilename"; + + my %declared; + my %used; + my @lines; + + while (defined(my $line = $fh->getline)) { + # Productions + $line =~ s/[ \t]{[^}]*?}/\t{}/g; + push @lines, $line; + } + + #@lines = sort @lines; + $fho->print(@lines); +} + +# Local Variables: +# compile-command: "./flexdiff $WUP/Verilog/Parser/VParseLex.l ../src/verilog.l" +# End: diff --git a/src/verilog.l b/src/verilog.l index ca486d83b..dd9f9a662 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -6,17 +6,17 @@ * ************************************************************************** * - * Copyright 2003-2009 by Wilson Snyder. Verilator is free software; you - * can redistribute it and/or modify it under the terms of either the GNU - * Lesser General Public License Version 3 or the Perl Artistic License + * Copyright 2003-2009 by Wilson Snyder. Verilator is free software; + * you can redistribute it and/or modify it under the terms of either the + * GNU Lesser General Public License Version 3 or the Perl Artistic License * Version 2.0. * - * Verilator is distributed in the hope that it will be useful, + * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * - **************************************************************************/ + *************************************************************************/ %option interactive c++ stack noyywrap %{ @@ -42,6 +42,8 @@ extern void yyerrorf(const char* format, ...); #define NEXTLINE() {V3Read::incLineno();} #define CRELINE() (V3Read::copyOrSameFileLine()) +#define FL { yylval.fileline = CRELINE(); } + void V3Read::ppline (const char* textp) { // Handle `line directive fileline()->lineDirective(textp); @@ -98,7 +100,7 @@ void V3Read::verilatorCmtBad(const char* textp) { //====================================================================== void yyerror(char* errmsg) { - yyerrorf("%s",errmsg); + V3Read::fileline()->v3error(errmsg); } void yyerrorf(const char* format, ...) { @@ -109,10 +111,10 @@ void yyerrorf(const char* format, ...) { vsprintf(msg,format,ap); va_end(ap); - V3Read::fileline()->v3error(msg); + yyerror(msg); } -//====================================================================== +/**********************************************************************/ %} %e 2000 @@ -123,7 +125,8 @@ void yyerrorf(const char* format, ...) { %o 25000 %s V95 V01 V05 S05 -%s PSL STRING ATTRMODE +%s STRING ATTRMODE +%s PSL %s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR %s IGNORE @@ -140,323 +143,325 @@ escid \\[^ \t\f\r\n]+ /* Verilog 1995 */ { - {ws} ; /* ignore white-space */ - \n {NEXTLINE();} /* Count line numbers */ + {ws} { } /* otherwise ignore white-space */ + \n { NEXTLINE(); } /* Count line numbers */ /* Extensions to Verilog set, some specified by PSL */ - "$c"[0-9]* {yylval.fileline = CRELINE(); return yD_C;} /*Verilator only*/ + "$c"[0-9]* { FL; return yD_C; } /*Verilator only*/ /* System Tasks */ - "$display" {yylval.fileline = CRELINE(); return yD_DISPLAY;} - "$fclose" {yylval.fileline = CRELINE(); return yD_FCLOSE;} - "$fdisplay" {yylval.fileline = CRELINE(); return yD_FDISPLAY;} - "$feof" {yylval.fileline = CRELINE(); return yD_FEOF;} - "$fflush" {yylval.fileline = CRELINE(); return yD_FFLUSH;} - "$fgetc" {yylval.fileline = CRELINE(); return yD_FGETC;} - "$fgets" {yylval.fileline = CRELINE(); return yD_FGETS;} - "$finish" {yylval.fileline = CRELINE(); return yD_FINISH;} - "$fopen" {yylval.fileline = CRELINE(); return yD_FOPEN;} - "$fscanf" {yylval.fileline = CRELINE(); return yD_FSCANF;} - "$fullskew" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "$fwrite" {yylval.fileline = CRELINE(); return yD_FWRITE;} - "$hold" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "$nochange" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "$period" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "$random" {yylval.fileline = CRELINE(); return yD_RANDOM;} - "$readmemb" {yylval.fileline = CRELINE(); return yD_READMEMB;} - "$readmemh" {yylval.fileline = CRELINE(); return yD_READMEMH;} - "$realtime" {yylval.fileline = CRELINE(); return yD_TIME;} - "$recovery" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "$recrem" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "$removal" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "$setup" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "$setuphold" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "$skew" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "$sscanf" {yylval.fileline = CRELINE(); return yD_SSCANF;} - "$stime" {yylval.fileline = CRELINE(); return yD_STIME;} - "$stop" {yylval.fileline = CRELINE(); return yD_STOP;} - "$time" {yylval.fileline = CRELINE(); return yD_TIME;} - "$timeskew" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "$width" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "$write" {yylval.fileline = CRELINE(); return yD_WRITE;} + "$display" { FL; return yD_DISPLAY; } + "$fclose" { FL; return yD_FCLOSE; } + "$fdisplay" { FL; return yD_FDISPLAY; } + "$feof" { FL; return yD_FEOF; } + "$fflush" { FL; return yD_FFLUSH; } + "$fgetc" { FL; return yD_FGETC; } + "$fgets" { FL; return yD_FGETS; } + "$finish" { FL; return yD_FINISH; } + "$fopen" { FL; return yD_FOPEN; } + "$fscanf" { FL; return yD_FSCANF; } + "$fullskew" { FL; return yaTIMINGSPEC; } + "$fwrite" { FL; return yD_FWRITE; } + "$hold" { FL; return yaTIMINGSPEC; } + "$nochange" { FL; return yaTIMINGSPEC; } + "$period" { FL; return yaTIMINGSPEC; } + "$random" { FL; return yD_RANDOM; } + "$readmemb" { FL; return yD_READMEMB; } + "$readmemh" { FL; return yD_READMEMH; } + "$realtime" { FL; return yD_TIME; } + "$recovery" { FL; return yaTIMINGSPEC; } + "$recrem" { FL; return yaTIMINGSPEC; } + "$removal" { FL; return yaTIMINGSPEC; } + "$setup" { FL; return yaTIMINGSPEC; } + "$setuphold" { FL; return yaTIMINGSPEC; } + "$skew" { FL; return yaTIMINGSPEC; } + "$sscanf" { FL; return yD_SSCANF; } + "$stime" { FL; return yD_STIME; } + "$stop" { FL; return yD_STOP; } + "$time" { FL; return yD_TIME; } + "$timeskew" { FL; return yaTIMINGSPEC; } + "$width" { FL; return yaTIMINGSPEC; } + "$write" { FL; return yD_WRITE; } /* Keywords */ - "always" {yylval.fileline = CRELINE(); return yALWAYS;} - "and" {yylval.fileline = CRELINE(); return yAND;} - "assign" {yylval.fileline = CRELINE(); return yASSIGN;} - "begin" {yylval.fileline = CRELINE(); return yBEGIN;} - "buf" {yylval.fileline = CRELINE(); return yBUF;} - "bufif0" {yylval.fileline = CRELINE(); return yBUFIF0;} - "bufif1" {yylval.fileline = CRELINE(); return yBUFIF1;} - "case" {yylval.fileline = CRELINE(); return yCASE;} - "casex" {yylval.fileline = CRELINE(); return yCASEX;} - "casez" {yylval.fileline = CRELINE(); return yCASEZ;} - "default" {yylval.fileline = CRELINE(); return yDEFAULT;} - "defparam" {yylval.fileline = CRELINE(); return yDEFPARAM;} - "disable" {yylval.fileline = CRELINE(); return yDISABLE;} - "edge" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "else" {yylval.fileline = CRELINE(); return yELSE;} - "end" {yylval.fileline = CRELINE(); return yEND;} - "endcase" {yylval.fileline = CRELINE(); return yENDCASE;} - "endfunction" {yylval.fileline = CRELINE(); return yENDFUNCTION;} - "endmodule" {yylval.fileline = CRELINE(); return yENDMODULE;} - "endspecify" {yylval.fileline = CRELINE(); return yENDSPECIFY;} - "endtask" {yylval.fileline = CRELINE(); return yENDTASK;} - "for" {yylval.fileline = CRELINE(); return yFOR;} - "forever" {yylval.fileline = CRELINE(); return yFOREVER;} - "function" {yylval.fileline = CRELINE(); return yFUNCTION;} - "if" {yylval.fileline = CRELINE(); return yIF;} - "initial" {yylval.fileline = CRELINE(); return yINITIAL;} - "inout" {yylval.fileline = CRELINE(); return yINOUT;} - "input" {yylval.fileline = CRELINE(); return yINPUT;} - "integer" {yylval.fileline = CRELINE(); return yINTEGER;} - "macromodule" {yylval.fileline = CRELINE(); return yMODULE;} - "module" {yylval.fileline = CRELINE(); return yMODULE;} - "nand" {yylval.fileline = CRELINE(); return yNAND;} - "negedge" {yylval.fileline = CRELINE(); return yNEGEDGE;} - "nor" {yylval.fileline = CRELINE(); return yNOR;} - "not" {yylval.fileline = CRELINE(); return yNOT;} - "notif0" {yylval.fileline = CRELINE(); return yNOTIF0;} - "notif1" {yylval.fileline = CRELINE(); return yNOTIF1;} - "or" {yylval.fileline = CRELINE(); return yOR;} - "output" {yylval.fileline = CRELINE(); return yOUTPUT;} - "parameter" {yylval.fileline = CRELINE(); return yPARAMETER;} - "posedge" {yylval.fileline = CRELINE(); return yPOSEDGE;} - "pulldown" {yylval.fileline = CRELINE(); return yPULLDOWN;} - "pullup" {yylval.fileline = CRELINE(); return yPULLUP;} - "reg" {yylval.fileline = CRELINE(); return yREG;} - "repeat" {yylval.fileline = CRELINE(); return yREPEAT;} - "scalared" {yylval.fileline = CRELINE(); return ySCALARED;} - "specify" {yylval.fileline = CRELINE(); return ySPECIFY;} - "specparam" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "supply0" {yylval.fileline = CRELINE(); return ySUPPLY0;} - "supply1" {yylval.fileline = CRELINE(); return ySUPPLY1;} - "task" {yylval.fileline = CRELINE(); return yTASK;} - "tri" {yylval.fileline = CRELINE(); return yTRI;} - "vectored" {yylval.fileline = CRELINE(); return yVECTORED;} - "while" {yylval.fileline = CRELINE(); return yWHILE;} - "wire" {yylval.fileline = CRELINE(); return yWIRE;} - "xnor" {yylval.fileline = CRELINE(); return yXNOR;} - "xor" {yylval.fileline = CRELINE(); return yXOR;} + "always" { FL; return yALWAYS; } + "and" { FL; return yAND; } + "assign" { FL; return yASSIGN; } + "begin" { FL; return yBEGIN; } + "buf" { FL; return yBUF; } + "bufif0" { FL; return yBUFIF0; } + "bufif1" { FL; return yBUFIF1; } + "case" { FL; return yCASE; } + "casex" { FL; return yCASEX; } + "casez" { FL; return yCASEZ; } + "default" { FL; return yDEFAULT; } + "defparam" { FL; return yDEFPARAM; } + "disable" { FL; return yDISABLE; } + "edge" { FL; return yaTIMINGSPEC; } + "else" { FL; return yELSE; } + "end" { FL; return yEND; } + "endcase" { FL; return yENDCASE; } + "endfunction" { FL; return yENDFUNCTION; } + "endmodule" { FL; return yENDMODULE; } + "endspecify" { FL; return yENDSPECIFY; } + "endtask" { FL; return yENDTASK; } + "for" { FL; return yFOR; } + "forever" { FL; return yFOREVER; } + "function" { FL; return yFUNCTION; } + "if" { FL; return yIF; } + "initial" { FL; return yINITIAL; } + "inout" { FL; return yINOUT; } + "input" { FL; return yINPUT; } + "integer" { FL; return yINTEGER; } + "macromodule" { FL; return yMODULE; } + "module" { FL; return yMODULE; } + "nand" { FL; return yNAND; } + "negedge" { FL; return yNEGEDGE; } + "nor" { FL; return yNOR; } + "not" { FL; return yNOT; } + "notif0" { FL; return yNOTIF0; } + "notif1" { FL; return yNOTIF1; } + "or" { FL; return yOR; } + "output" { FL; return yOUTPUT; } + "parameter" { FL; return yPARAMETER; } + "posedge" { FL; return yPOSEDGE; } + "pulldown" { FL; return yPULLDOWN; } + "pullup" { FL; return yPULLUP; } + "reg" { FL; return yREG; } + "repeat" { FL; return yREPEAT; } + "scalared" { FL; return ySCALARED; } + "specify" { FL; return ySPECIFY; } + "specparam" { FL; return yaTIMINGSPEC; } + "supply0" { FL; return ySUPPLY0; } + "supply1" { FL; return ySUPPLY1; } + "task" { FL; return yTASK; } + "tri" { FL; return yTRI; } + "vectored" { FL; return yVECTORED; } + "while" { FL; return yWHILE; } + "wire" { FL; return yWIRE; } + "xnor" { FL; return yXNOR; } + "xor" { FL; return yXOR; } /* Special errors */ - "$displayb" {yyerrorf("Unsupported: Use $display with %%b format instead: %s",yytext);} - "$displayh" {yyerrorf("Unsupported: Use $display with %%x format instead: %s",yytext);} - "$displayo" {yyerrorf("Unsupported: Use $display with %%o format instead: %s",yytext);} - "$fdisplayb" {yyerrorf("Unsupported: Use $fdisplay with %%b format instead: %s",yytext);} - "$fdisplayh" {yyerrorf("Unsupported: Use $fdisplay with %%x format instead: %s",yytext);} - "$fdisplayo" {yyerrorf("Unsupported: Use $fdisplay with %%o format instead: %s",yytext);} - "$fwriteb" {yyerrorf("Unsupported: Use $fwrite with %%b format instead: %s",yytext);} - "$fwriteh" {yyerrorf("Unsupported: Use $fwrite with %%x format instead: %s",yytext);} - "$fwriteo" {yyerrorf("Unsupported: Use $fwrite with %%o format instead: %s",yytext);} - "$writeb" {yyerrorf("Unsupported: Use $write with %%b format instead: %s",yytext);} - "$writeh" {yyerrorf("Unsupported: Use $write with %%x format instead: %s",yytext);} - "$writeo" {yyerrorf("Unsupported: Use $write with %%o format instead: %s",yytext);} + "$displayb" { yyerrorf("Unsupported: Use $display with %%b format instead: %s",yytext); } + "$displayh" { yyerrorf("Unsupported: Use $display with %%x format instead: %s",yytext); } + "$displayo" { yyerrorf("Unsupported: Use $display with %%o format instead: %s",yytext); } + "$fdisplayb" { yyerrorf("Unsupported: Use $fdisplay with %%b format instead: %s",yytext); } + "$fdisplayh" { yyerrorf("Unsupported: Use $fdisplay with %%x format instead: %s",yytext); } + "$fdisplayo" { yyerrorf("Unsupported: Use $fdisplay with %%o format instead: %s",yytext); } + "$fwriteb" { yyerrorf("Unsupported: Use $fwrite with %%b format instead: %s",yytext); } + "$fwriteh" { yyerrorf("Unsupported: Use $fwrite with %%x format instead: %s",yytext); } + "$fwriteo" { yyerrorf("Unsupported: Use $fwrite with %%o format instead: %s",yytext); } + "$writeb" { yyerrorf("Unsupported: Use $write with %%b format instead: %s",yytext); } + "$writeh" { yyerrorf("Unsupported: Use $write with %%x format instead: %s",yytext); } + "$writeo" { yyerrorf("Unsupported: Use $write with %%o format instead: %s",yytext); } /* Generic unsupported warnings */ - "cmos" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "deassign" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "endprimitive" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "endtable" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "event" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "force" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "fork" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "highz0" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "highz1" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "join" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "large" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "medium" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "nmos" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "pmos" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "primitive" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "pull0" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "pull1" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "rcmos" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "real" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "realtime" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "release" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "rnmos" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "rpmos" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "rtran" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "rtranif0" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "rtranif1" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "small" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "strong0" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "strong1" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "table" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "time" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "tran" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "tranif0" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "tranif1" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "triand" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "trior" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "trireg" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "tri0" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "tri1" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "wait" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "wand" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "weak0" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "weak1" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} - "wor" {yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext);} + "cmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "deassign" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "endprimitive" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "endtable" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "event" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "force" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "fork" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "highz0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "highz1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "join" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "large" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "medium" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "nmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "pmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "primitive" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "pull0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "pull1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "rcmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "real" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "realtime" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "release" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "rnmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "rpmos" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "rtran" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "rtranif0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "rtranif1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "small" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "strong0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "strong1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "table" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "time" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "tran" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "tranif0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "tranif1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "triand" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "trior" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "trireg" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "tri0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "tri1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "wait" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "wand" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "weak0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "weak1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } + "wor" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); } } /* Verilog 2001 */ { /* System Tasks */ - "$signed" {yylval.fileline = CRELINE(); return yD_SIGNED;} - "$unsigned" {yylval.fileline = CRELINE(); return yD_UNSIGNED;} + "$signed" { FL; return yD_SIGNED; } + "$unsigned" { FL; return yD_UNSIGNED; } /* Keywords */ - "automatic" {yylval.fileline = CRELINE(); return yAUTOMATIC;} - "endgenerate" {yylval.fileline = CRELINE(); return yENDGENERATE;} - "generate" {yylval.fileline = CRELINE(); return yGENERATE;} - "genvar" {yylval.fileline = CRELINE(); return yGENVAR;} - "ifnone" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "localparam" {yylval.fileline = CRELINE(); return yLOCALPARAM;} - "noshowcancelled" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "pulsestyle_ondetect" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "pulsestyle_onevent" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "showcancelled" {yylval.fileline = CRELINE(); return yaTIMINGSPEC;} - "signed" {yylval.fileline = CRELINE(); return ySIGNED;} - "unsigned" {yylval.fileline = CRELINE(); return yUNSIGNED;} - /* Special errors */ - "include" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented; probably you want `include instead: %s",yytext);} - /* Generic unsupported warnings */ - "cell" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} - "config" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} - "design" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} - "endconfig" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} - "incdir" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} - "instance" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} - "liblist" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} - "library" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} - "use" {yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext);} + "automatic" { FL; return yAUTOMATIC; } + "endgenerate" { FL; return yENDGENERATE; } + "generate" { FL; return yGENERATE; } + "genvar" { FL; return yGENVAR; } + "ifnone" { FL; return yaTIMINGSPEC; } + "localparam" { FL; return yLOCALPARAM; } + "noshowcancelled" { FL; return yaTIMINGSPEC; } + "pulsestyle_ondetect" { FL; return yaTIMINGSPEC; } + "pulsestyle_onevent" { FL; return yaTIMINGSPEC; } + "showcancelled" { FL; return yaTIMINGSPEC; } + "signed" { FL; return ySIGNED; } + "unsigned" { FL; return yUNSIGNED; } + /* Generic unsupported keywords */ + "cell" { yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext); } + "config" { yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext); } + "design" { yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext); } + "endconfig" { yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext); } + "incdir" { yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext); } + "include" { yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented; probably you want `include instead: %s",yytext); } + "instance" { yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext); } + "liblist" { yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext); } + "library" { yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext); } + "use" { yyerrorf("Unsupported: Verilog 2001-config reserved word not implemented: %s",yytext); } } /* Verilog 2005 */ { /* Keywords */ - "uwire" {yylval.fileline = CRELINE(); return yWIRE;} + "uwire" { FL; return yWIRE; } } /* System Verilog 2005 */ { /* System Tasks */ - "$bits" {yylval.fileline = CRELINE(); return yD_BITS;} - "$clog2" {yylval.fileline = CRELINE(); return yD_CLOG2;} - "$countones" {yylval.fileline = CRELINE(); return yD_COUNTONES;} - "$error" {yylval.fileline = CRELINE(); return yD_ERROR;} - "$fatal" {yylval.fileline = CRELINE(); return yD_FATAL;} - "$info" {yylval.fileline = CRELINE(); return yD_INFO;} - "$isunknown" {yylval.fileline = CRELINE(); return yD_ISUNKNOWN;} - "$onehot" {yylval.fileline = CRELINE(); return yD_ONEHOT;} - "$onehot0" {yylval.fileline = CRELINE(); return yD_ONEHOT0;} - "$warning" {yylval.fileline = CRELINE(); return yD_WARNING;} + "$bits" { FL; return yD_BITS; } + "$clog2" { FL; return yD_CLOG2; } + "$countones" { FL; return yD_COUNTONES; } + "$error" { FL; return yD_ERROR; } + "$fatal" { FL; return yD_FATAL; } + "$info" { FL; return yD_INFO; } + "$isunknown" { FL; return yD_ISUNKNOWN; } + "$onehot" { FL; return yD_ONEHOT; } + "$onehot0" { FL; return yD_ONEHOT0; } + "$warning" { FL; return yD_WARNING; } /* Keywords */ - "always_comb" {yylval.fileline = CRELINE(); return yALWAYS;} - "always_ff" {yylval.fileline = CRELINE(); return yALWAYS;} - "always_latch" {yylval.fileline = CRELINE(); return yALWAYS;} - "clocking" {yylval.fileline = CRELINE(); return yCLOCKING;} - "do" {yylval.fileline = CRELINE(); return yDO;} - "endclocking" {yylval.fileline = CRELINE(); return yENDCLOCKING;} - "endproperty" {yylval.fileline = CRELINE(); return yENDPROPERTY;} - "final" {yylval.fileline = CRELINE(); return yFINAL;} - "iff" {yylval.fileline = CRELINE(); return yIFF;} - "priority" {yylval.fileline = CRELINE(); return yPRIORITY;} - "static" {yylval.fileline = CRELINE(); return ySTATIC;} - "timeprecision" {yylval.fileline = CRELINE(); return yTIMEPRECISION;} - "timeunit" {yylval.fileline = CRELINE(); return yTIMEUNIT;} - "unique" {yylval.fileline = CRELINE(); return yUNIQUE;} + "always_comb" { FL; return yALWAYS; } + "always_ff" { FL; return yALWAYS; } + "always_latch" { FL; return yALWAYS; } + "clocking" { FL; return yCLOCKING; } + "do" { FL; return yDO; } + "endclocking" { FL; return yENDCLOCKING; } + "endproperty" { FL; return yENDPROPERTY; } + "final" { FL; return yFINAL; } + "iff" { FL; return yIFF; } + "priority" { FL; return yPRIORITY; } + "static" { FL; return ySTATIC; } + "timeprecision" { FL; return yTIMEPRECISION; } + "timeunit" { FL; return yTIMEUNIT; } + "unique" { FL; return yUNIQUE; } /* Generic unsupported warnings */ /* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */ - "alias" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "bind" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "bins" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "binsof" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "bit" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "break" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "byte" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "chandle" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "class" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "constraint" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "context" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "continue" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "covergroup" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "coverpoint" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "cross" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "dist" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "endclass" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "endgroup" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "endinterface" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "endpackage" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "endprogram" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "endsequence" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "enum" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "expect" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "export" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "extends" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "extern" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "first_match" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "foreach" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "forkjoin" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "ignore_bins" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "illegal_bins" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "import" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "inside" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "int" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "interface" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "intersect" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "join_any" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "join_none" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "local" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "logic" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "longint" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "matches" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "modport" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "new" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "null" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "package" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "packed" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "program" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "protected" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "pure" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "rand" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "randc" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "randcase" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "randsequence" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "ref" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "return" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "shortint" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "shortreal" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "solve" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "string" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "struct" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "super" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "tagged" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "this" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "throughout" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "type" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "typedef" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "var" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "virtual" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "void" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "wait_order" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "wildcard" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} - "with" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext);} + "$root" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "$unit" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "alias" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "bind" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "bins" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "binsof" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "bit" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "break" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "byte" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "chandle" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "class" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "constraint" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "context" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "continue" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "covergroup" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "coverpoint" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "cross" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "dist" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "endclass" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "endgroup" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "endinterface" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "endpackage" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "endprogram" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "endsequence" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "enum" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "expect" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "export" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "extends" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "extern" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "first_match" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "foreach" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "forkjoin" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "ignore_bins" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "illegal_bins" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "import" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "inside" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "int" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "interface" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "intersect" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "join_any" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "join_none" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "local" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "logic" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "longint" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "matches" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "modport" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "new" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "null" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "package" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "packed" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "program" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "protected" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "pure" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "rand" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "randc" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "randcase" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "randomize" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "randsequence" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "ref" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "return" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "shortint" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "shortreal" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "solve" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "string" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "struct" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "super" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "tagged" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "this" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "throughout" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "type" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "typedef" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "var" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "virtual" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "void" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "wait_order" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "wildcard" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } + "with" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } } /* SystemVerilog ONLY not PSL; different rules for PSL as specified below */ { /* Keywords */ - "assert" {yylval.fileline = CRELINE(); return yASSERT;} - "cover" {yylval.fileline = CRELINE(); return yCOVER;} - "property" {yylval.fileline = CRELINE(); return yPROPERTY;} + "assert" { FL; return yASSERT; } + "cover" { FL; return yCOVER; } + "property" { FL; return yPROPERTY; } /* Generic unsupported warnings */ - "assume" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);} - "before" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);} - "const" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);} - "sequence" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);} - "union" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);} - "within" {yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext);} + "assume" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext); } + "before" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext); } + "const" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext); } + "sequence" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext); } + "union" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext); } + "within" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented in non-PSL context: %s",yytext); } } /* Default PLI rule */ { - "$"[a-zA-Z_$][a-zA-Z0-9_$]* {yyerrorf("Unsupported or unknown PLI call: %s",yytext);} + "$"[a-zA-Z_$][a-zA-Z0-9_$]* { yyerrorf("Unsupported or unknown PLI call: %s",yytext); } } /************************************************************************/ @@ -464,88 +469,88 @@ escid \\[^ \t\f\r\n]+ /*Entry into PSL; mode change */ { - "psl" { yy_push_state(PSL); yylval.fileline = CRELINE(); return yPSL; } + "psl" { yy_push_state(PSL); FL; return yPSL; } } { /* Special things */ "psl" { ; } // 'psl' may occur in middle of statement, so easier just to suppress /* Keywords */ - "assert" {yylval.fileline = CRELINE(); return yPSL_ASSERT;} - "assume" {yylval.fileline = CRELINE(); return yPSL_ASSERT;} //==assert - "before_!" {yyerrorf("Illegal syntax, use before!_ instead of %s",yytext);} - "clock" {yylval.fileline = CRELINE(); return yPSL_CLOCK;} - "countones" {yylval.fileline = CRELINE(); return yD_COUNTONES;} - "cover" {yylval.fileline = CRELINE(); return yPSL_COVER;} - "isunknown" {yylval.fileline = CRELINE(); return yD_ISUNKNOWN;} - "onehot" {yylval.fileline = CRELINE(); return yD_ONEHOT; } - "onehot0" {yylval.fileline = CRELINE(); return yD_ONEHOT0; } - "until_!" {yyerrorf("Illegal syntax, use until!_ instead of %s",yytext);} - "report" {yylval.fileline = CRELINE(); return yPSL_REPORT; } - "true" {yylval.fileline = CRELINE(); return yTRUE; } + "assert" { FL; return yPSL_ASSERT; } + "assume" { FL; return yPSL_ASSERT; } //==assert + "before_!" { yyerrorf("Illegal syntax, use before!_ instead of %s",yytext); } + "clock" { FL; return yPSL_CLOCK; } + "countones" { FL; return yD_COUNTONES; } + "cover" { FL; return yPSL_COVER; } + "isunknown" { FL; return yD_ISUNKNOWN; } + "onehot" { FL; return yD_ONEHOT; } + "onehot0" { FL; return yD_ONEHOT0; } + "until_!" { yyerrorf("Illegal syntax, use until!_ instead of %s",yytext); } + "report" { FL; return yPSL_REPORT; } + "true" { FL; return yTRUE; } /* Generic unsupported warnings */ - /*"A" {yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */ - /*"AF" {yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */ - /*"AG" {yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */ - /*"AX" {yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */ - /*"E" {yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */ - /*"EF" {yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */ - /*"EG" {yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */ - /*"EX" {yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext);} */ - /*"F" {yylval.fileline = CRELINE(); return yEVENTUALLYB; } */ - /*"G" {yylval.fileline = CRELINE(); return yALWAYS; } */ - /*"U" {yylval.fileline = CRELINE(); return yUNTILB; } */ - /*"W" {yylval.fileline = CRELINE(); return yUNTIL; } */ - /*"X" {yylval.fileline = CRELINE(); return yNEXT; } */ - /*"X!" {yylval.fileline = CRELINE(); return yNEXTB; } */ - "%for" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "%if" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "abort" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "assume_guarantee" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools - "before" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "before!" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "before!_" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "before_" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "boolean" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "const" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "endpoint" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "eventually!" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "fairness" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools - "fell" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "forall" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools - "in" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "inf" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "inherit" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools - "never" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "next" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "next!" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "next_a" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "next_a!" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "next_e" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "next_e!" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "next_event" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "next_event!" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "next_event_a" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "next_event_a!" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "next_event_e" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "next_event_e!" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "prev" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "property" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "restrict" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "restrict_guarantee" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools - "rose" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "sequence" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "stable" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "strong" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools - "union" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "until" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "until!" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "until!_" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "until_" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "vmode" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools - "vprop" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} //Unsup in other tools - "vunit" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} - "within" {yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext);} + /*"A" { yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext); } */ + /*"AF" { yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext); } */ + /*"AG" { yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext); } */ + /*"AX" { yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext); } */ + /*"E" { yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext); } */ + /*"EF" { yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext); } */ + /*"EG" { yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext); } */ + /*"EX" { yyerrorf("Unsupported: PSL branching reserved word not implemented: %s",yytext); } */ + /*"F" { FL; return yEVENTUALLYB; } */ + /*"G" { FL; return yALWAYS; } */ + /*"U" { FL; return yUNTILB; } */ + /*"W" { FL; return yUNTIL; } */ + /*"X" { FL; return yNEXT; } */ + /*"X!" { FL; return yNEXTB; } */ + "%for" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "%if" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "abort" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "assume_guarantee" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } //Unsup in other tools + "before" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "before!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "before!_" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "before_" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "boolean" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "const" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "endpoint" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "eventually!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "fairness" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } //Unsup in other tools + "fell" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "forall" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } //Unsup in other tools + "in" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "inf" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "inherit" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } //Unsup in other tools + "never" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "next" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "next!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "next_a" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "next_a!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "next_e" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "next_e!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "next_event" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "next_event!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "next_event_a" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "next_event_a!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "next_event_e" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "next_event_e!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "prev" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "property" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "restrict" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "restrict_guarantee" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } //Unsup in other tools + "rose" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "sequence" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "stable" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "strong" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } //Unsup in other tools + "union" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "until" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "until!" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "until!_" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "until_" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "vmode" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } //Unsup in other tools + "vprop" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } //Unsup in other tools + "vunit" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } + "within" { yyerrorf("Unsupported: PSL reserved word not implemented: %s",yytext); } } /************************************************************************/ @@ -554,23 +559,23 @@ escid \\[^ \t\f\r\n]+ /* Converted from //{cmt}verilator ...{cmt} by preprocessor */ { "/*verilator"{ws}*"*/" {} /* Ignore empty comments, may be `endif // verilator */ - "/*verilator clock_enable*/" {yylval.fileline = CRELINE(); return yVL_CLOCK_ENABLE;} - "/*verilator coverage_block_off*/" {yylval.fileline = CRELINE(); return yVL_COVERAGE_BLOCK_OFF;} - "/*verilator full_case*/" {yylval.fileline = CRELINE(); return yVL_FULL_CASE;} - "/*verilator inline_module*/" {yylval.fileline = CRELINE(); return yVL_INLINE_MODULE;} - "/*verilator isolate_assignments*/" {yylval.fileline = CRELINE(); return yVL_ISOLATE_ASSIGNMENTS;} - "/*verilator no_inline_module*/" {yylval.fileline = CRELINE(); return yVL_NO_INLINE_MODULE;} - "/*verilator no_inline_task*/" {yylval.fileline = CRELINE(); return yVL_NO_INLINE_TASK;} - "/*verilator parallel_case*/" {yylval.fileline = CRELINE(); return yVL_PARALLEL_CASE;} - "/*verilator public*/" {yylval.fileline = CRELINE(); return yVL_PUBLIC;} - "/*verilator public_flat*/" {yylval.fileline = CRELINE(); return yVL_PUBLIC_FLAT;} - "/*verilator public_module*/" {yylval.fileline = CRELINE(); return yVL_PUBLIC_MODULE;} - "/*verilator sc_clock*/" {yylval.fileline = CRELINE(); return yVL_CLOCK;} - "/*verilator systemc_clock*/" {yylval.fileline = CRELINE(); return yVL_CLOCK;} - "/*verilator tracing_off*/" {V3Read::fileline()->tracingOn(false);} - "/*verilator tracing_on*/" {V3Read::fileline()->tracingOn(true);} - "/*verilator coverage_off*/" {V3Read::fileline()->coverageOn(false);} - "/*verilator coverage_on*/" {V3Read::fileline()->coverageOn(true);} + "/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; } + "/*verilator coverage_block_off*/" { FL; return yVL_COVERAGE_BLOCK_OFF; } + "/*verilator full_case*/" { FL; return yVL_FULL_CASE; } + "/*verilator inline_module*/" { FL; return yVL_INLINE_MODULE; } + "/*verilator isolate_assignments*/" { FL; return yVL_ISOLATE_ASSIGNMENTS; } + "/*verilator no_inline_module*/" { FL; return yVL_NO_INLINE_MODULE; } + "/*verilator no_inline_task*/" { FL; return yVL_NO_INLINE_TASK; } + "/*verilator parallel_case*/" { FL; return yVL_PARALLEL_CASE; } + "/*verilator public*/" { FL; return yVL_PUBLIC; } + "/*verilator public_flat*/" { FL; return yVL_PUBLIC_FLAT; } + "/*verilator public_module*/" { FL; return yVL_PUBLIC_MODULE; } + "/*verilator sc_clock*/" { FL; return yVL_CLOCK; } + "/*verilator systemc_clock*/" { FL; return yVL_CLOCK; } + "/*verilator tracing_off*/" {V3Read::fileline()->tracingOn(false); } + "/*verilator tracing_on*/" {V3Read::fileline()->tracingOn(true); } + "/*verilator coverage_off*/" {V3Read::fileline()->coverageOn(false); } + "/*verilator coverage_on*/" {V3Read::fileline()->coverageOn(true); } "/*verilator lint_off"[^*]*"*/" {V3Read::verilatorCmtLint(yytext, true); } "/*verilator lint_on"[^*]*"*/" {V3Read::verilatorCmtLint(yytext, false); } "/*verilator lint_restore*/" {V3Read::verilatorCmtLintRestore(); } @@ -580,79 +585,122 @@ escid \\[^ \t\f\r\n]+ } /************************************************************************/ - /* Operators */ + + /* Single character operator thingies */ +{ + "{" { FL; return yytext[0]; } + "}" { FL; return yytext[0]; } +} +{ + "!" { FL; return yytext[0]; } + "#" { FL; return yytext[0]; } + "$" { FL; return yytext[0]; } + "%" { FL; return yytext[0]; } + "&" { FL; return yytext[0]; } + "(" { FL; return yytext[0]; } + ")" { FL; return yytext[0]; } + "*" { FL; return yytext[0]; } + "+" { FL; return yytext[0]; } + "," { FL; return yytext[0]; } + "-" { FL; return yytext[0]; } + "." { FL; return yytext[0]; } + "/" { FL; return yytext[0]; } + ":" { FL; return yytext[0]; } + ";" { FL; return yytext[0]; } + "<" { FL; return yytext[0]; } + "=" { FL; return yytext[0]; } + ">" { FL; return yytext[0]; } + "?" { FL; return yytext[0]; } + "@" { FL; return yytext[0]; } + "[" { FL; return yytext[0]; } + "]" { FL; return yytext[0]; } + "^" { FL; return yytext[0]; } + "|" { FL; return yytext[0]; } + "~" { FL; return yytext[0]; } +} + + /************************************************************************/ + /* Operators and multi-character symbols */ /* Verilog 1995 Operators */ { - "&&" {yylval.fileline = CRELINE(); return yP_ANDAND;} - "||" {yylval.fileline = CRELINE(); return yP_OROR;} - "<=" {yylval.fileline = CRELINE(); return yP_LTE;} - ">=" {yylval.fileline = CRELINE(); return yP_GTE;} - "<<" {yylval.fileline = CRELINE(); return yP_SLEFT;} - ">>" {yylval.fileline = CRELINE(); return yP_SRIGHT;} - "==" {yylval.fileline = CRELINE(); return yP_EQUAL;} - "!=" {yylval.fileline = CRELINE(); return yP_NOTEQUAL;} - "===" {yylval.fileline = CRELINE(); return yP_CASEEQUAL;} - "!==" {yylval.fileline = CRELINE(); return yP_CASENOTEQUAL;} - "^~" {yylval.fileline = CRELINE(); return yP_XNOR;} - "~^" {yylval.fileline = CRELINE(); return yP_XNOR;} - "~&" {yylval.fileline = CRELINE(); return yP_NAND;} - "~|" {yylval.fileline = CRELINE(); return yP_NOR;} - "->" {yylval.fileline = CRELINE(); return yP_MINUSGT;} - "=>" {yylval.fileline = CRELINE(); return yP_EQGT; } - "*>" {yylval.fileline = CRELINE(); return yP_ASTGT; } - "&&&" {yylval.fileline = CRELINE(); return yP_ANDANDAND; } + "&&" { FL; return yP_ANDAND; } + "||" { FL; return yP_OROR; } + "<=" { FL; return yP_LTE; } + ">=" { FL; return yP_GTE; } + "<<" { FL; return yP_SLEFT; } + ">>" { FL; return yP_SRIGHT; } + "==" { FL; return yP_EQUAL; } + "!=" { FL; return yP_NOTEQUAL; } + "===" { FL; return yP_CASEEQUAL; } + "!==" { FL; return yP_CASENOTEQUAL; } + "^~" { FL; return yP_XNOR; } + "~^" { FL; return yP_XNOR; } + "~&" { FL; return yP_NAND; } + "~|" { FL; return yP_NOR; } + "->" { FL; return yP_MINUSGT; } + "=>" { FL; return yP_EQGT; } + "*>" { FL; return yP_ASTGT; } + "&&&" { FL; return yP_ANDANDAND; } } /* Verilog 2001 Operators */ { - "<<<" {yylval.fileline = CRELINE(); return yP_SLEFT;} - ">>>" {yylval.fileline = CRELINE(); return yP_SSRIGHT;} - "**" {yylval.fileline = CRELINE(); return yP_POW;} - "+:" {yylval.fileline = CRELINE(); return yP_PLUSCOLON;} - "-:" {yylval.fileline = CRELINE(); return yP_MINUSCOLON;} - ".*" {yylval.fileline = CRELINE(); return yP_DOTSTAR;} + "<<<" { FL; return yP_SLEFT; } + ">>>" { FL; return yP_SSRIGHT; } + "**" { FL; return yP_POW; } + "+:" { FL; return yP_PLUSCOLON; } + "-:" { FL; return yP_MINUSCOLON; } + ".*" { FL; return yP_DOTSTAR; } } /* SystemVerilog Operators */ { - "==?" {yylval.fileline = CRELINE(); return yP_WILDEQUAL;} - "!=?" {yylval.fileline = CRELINE(); return yP_WILDNOTEQUAL;} - "+=" {yylval.fileline = CRELINE(); return yP_PLUSEQ; } - "-=" {yylval.fileline = CRELINE(); return yP_MINUSEQ; } - "*=" {yylval.fileline = CRELINE(); return yP_TIMESEQ; } - "/=" {yylval.fileline = CRELINE(); return yP_DIVEQ; } - "%=" {yylval.fileline = CRELINE(); return yP_MODEQ; } - "&=" {yylval.fileline = CRELINE(); return yP_ANDEQ; } - "|=" {yylval.fileline = CRELINE(); return yP_OREQ; } - "^=" {yylval.fileline = CRELINE(); return yP_XOREQ; } - "<<=" {yylval.fileline = CRELINE(); return yP_SLEFTEQ; } - ">>=" {yylval.fileline = CRELINE(); return yP_SRIGHTEQ; } - "<<<=" {yylval.fileline = CRELINE(); return yP_SLEFTEQ; } - ">>>=" {yylval.fileline = CRELINE(); return yP_SSRIGHTEQ; } - "->>" {yylval.fileline = CRELINE(); return yP_MINUSGTGT; } - "##" {yylval.fileline = CRELINE(); return yP_POUNDPOUND; } - "@@" {yylval.fileline = CRELINE(); return yP_ATAT; } - "::" {yylval.fileline = CRELINE(); return yP_COLONCOLON; } - ":=" {yylval.fileline = CRELINE(); return yP_COLONEQ; } - ":/" {yylval.fileline = CRELINE(); return yP_COLONDIV; } - "|->" {yylval.fileline = CRELINE(); return yP_ORMINUSGT; } - "|=>" {yylval.fileline = CRELINE(); return yP_OREQGT; } + "'" { FL; return yP_TICK; } + "'{" { FL; return yP_TICKBRA; } + "==?" { FL; return yP_WILDEQUAL; } + "!=?" { FL; return yP_WILDNOTEQUAL; } + "++" { FL; return yP_PLUSPLUS; } + "--" { FL; return yP_MINUSMINUS; } + "+=" { FL; return yP_PLUSEQ; } + "-=" { FL; return yP_MINUSEQ; } + "*=" { FL; return yP_TIMESEQ; } + "/=" { FL; return yP_DIVEQ; } + "%=" { FL; return yP_MODEQ; } + "&=" { FL; return yP_ANDEQ; } + "|=" { FL; return yP_OREQ; } + "^=" { FL; return yP_XOREQ; } + "<<=" { FL; return yP_SLEFTEQ; } + ">>=" { FL; return yP_SRIGHTEQ; } + "<<<=" { FL; return yP_SLEFTEQ; } + ">>>=" { FL; return yP_SSRIGHTEQ; } + "->>" { FL; return yP_MINUSGTGT; } + "##" { FL; return yP_POUNDPOUND; } + "@@" { FL; return yP_ATAT; } + "::" { FL; return yP_COLONCOLON; } + ":=" { FL; return yP_COLONEQ; } + ":/"[^\/\*] { FL; return yP_COLONDIV; } /* : then comment is not ":/" */ + "|->" { FL; return yP_ORMINUSGT; } + "|=>" { FL; return yP_OREQGT; } + /* Some simulators allow whitespace here. Grr */ + "["{ws}*"*" { FL; return yP_BRASTAR; } + "["{ws}*"=" { FL; return yP_BRAEQ; } + "["{ws}*"->" { FL; return yP_BRAMINUSGT; } } /* PSL Operators */ { - "{" {yylval.fileline = CRELINE(); return yPSL_BRA;} // Avoid parser hitting concatenate. - "}" {yylval.fileline = CRELINE(); return yPSL_KET;} // Avoid parser hitting concatenate. - "<->" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} //Unsup in other tools - "[*" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_STAR - "[*]" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_STAR_KET - "[+]" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_PLUS_KET - "[->" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_MINUS_GT - "[->]" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_MINUS_GT_KET - "[=" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_BRA_EQ - "|->" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_ORMINUSGT - "|=>" {yyerrorf("Unsupported: PSL operator not implemented: %s",yytext);} // yP_OREQGT + "{" { FL; return yPSL_BRA; } // Avoid parser hitting concatenate. + "}" { FL; return yPSL_KET; } // Avoid parser hitting concatenate. + "<->" { yyerrorf("Unsupported: PSL operator not implemented: %s",yytext); } //Unsup in other tools + "[*" { yyerrorf("Unsupported: PSL operator not implemented: %s",yytext); } // yP_BRA_STAR + "[*]" { yyerrorf("Unsupported: PSL operator not implemented: %s",yytext); } // yP_BRA_STAR_KET + "[+]" { yyerrorf("Unsupported: PSL operator not implemented: %s",yytext); } // yP_BRA_PLUS_KET + "[->" { yyerrorf("Unsupported: PSL operator not implemented: %s",yytext); } // yP_BRA_MINUS_GT + "[->]" { yyerrorf("Unsupported: PSL operator not implemented: %s",yytext); } // yP_BRA_MINUS_GT_KET + "[=" { yyerrorf("Unsupported: PSL operator not implemented: %s",yytext); } // yP_BRA_EQ + "|->" { yyerrorf("Unsupported: PSL operator not implemented: %s",yytext); } // yP_ORMINUSGT + "|=>" { yyerrorf("Unsupported: PSL operator not implemented: %s",yytext); } // yP_OREQGT } /* Identifiers and numbers */ @@ -680,11 +728,21 @@ escid \\[^ \t\f\r\n]+ yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext); return yaINTNUM; } - [0-9][_0-9]*[ \t]*['']s?[bcodhBCODH]?[ \t]*[A-Fa-f0-9xXzZ_?]* { + /* Note below is constructed to not match the ' that begins a '( or '{ */ + [0-9][_0-9]*[ \t]*['']s?[bcodhBCODH]?[ \t]*[A-Fa-f0-9xXzZ_?]+ { yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext); return yaINTNUM; } - [0-9][_0-9]* { yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext); + [0-9][_0-9]*[ \t]*['']s?[bcodhBCODH] { + yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext); + return yaINTNUM; + } + [0-9][_0-9]*[ \t]*['']s { + yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext); + return yaINTNUM; + } + [0-9][_0-9]* { + yylval.nump = V3Read::newNumber(V3Read::fileline(),(char*)yytext); return yaINTNUM; } [0-9][_0-9]*(\.[_0-9]+)([eE][-+]?[_0-9]+)? { @@ -752,6 +810,7 @@ escid \\[^ \t\f\r\n]+ "`nosuppress_faults" { } // Verilog-XL compatibility "`nounconnected_drive" { } // Verilog-XL compatibility "`portcoerce" { } + "`pragma"{ws}+[^\n]*\n { } // Verilog 2005 "`protect" { } "`psl" { if (V3Read::optPsl()) { BEGIN PSL; } else { BEGIN IGNORE; } } "`remove_gatenames" { } // Verilog-XL compatibility @@ -764,29 +823,29 @@ escid \\[^ \t\f\r\n]+ "`systemc_imp_header" { BEGIN SYSCIMPH; } "`systemc_implementation" { BEGIN SYSCIMP; } "`systemc_interface" { BEGIN SYSCINT; } - "`timescale"{ws}+[^\n]* { } // Verilog spec - not supported + "`timescale"{ws}+[^\n]*\n { NEXTLINE(); } // Verilog spec - not supported "`verilog" { BEGIN V3Read::lastVerilogState(); } - "`begin_keywords"[ \t]*\"1364-1995\" { yy_push_state(V95); V3Read::pushBeginKeywords(YY_START);} - "`begin_keywords"[ \t]*\"1364-2001\" { yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);} - "`begin_keywords"[ \t]*\"1364-2001-noconfig\" { yy_push_state(V01); V3Read::pushBeginKeywords(YY_START);} - "`begin_keywords"[ \t]*\"1364-2005\" { yy_push_state(V05); V3Read::pushBeginKeywords(YY_START);} - "`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); V3Read::pushBeginKeywords(YY_START);} + "`begin_keywords"[ \t]*\"1364-1995\" { yy_push_state(V95); V3Read::pushBeginKeywords(YY_START); } + "`begin_keywords"[ \t]*\"1364-2001\" { yy_push_state(V01); V3Read::pushBeginKeywords(YY_START); } + "`begin_keywords"[ \t]*\"1364-2001-noconfig\" { yy_push_state(V01); V3Read::pushBeginKeywords(YY_START); } + "`begin_keywords"[ \t]*\"1364-2005\" { yy_push_state(V05); V3Read::pushBeginKeywords(YY_START); } + "`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); V3Read::pushBeginKeywords(YY_START); } "`end_keywords" { yy_pop_state(); if (!V3Read::popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); } } -[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCHDR;} -[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCINT;} -[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCIMP;} -[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCIMPH;} -[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCCTOR;} -[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCDTOR;} +[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCHDR; } +[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCINT; } +[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCIMP; } +[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCIMPH; } +[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCCTOR; } +[ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); yylval.strp = V3Read::newString(yytext); return yaSCDTOR; } [ \t]*[^` \t\n][^\n]*\n { NEXTLINE(); } /* Pick up text-type data */ { - {wsnr}* { yymore();} - \n { NEXTLINE(); yymore();} + {wsnr}* { yymore(); } + \n { NEXTLINE(); yymore(); } \r ; } @@ -796,7 +855,7 @@ escid \\[^ \t\f\r\n]+ { "`"[a-zA-Z_0-9]+ { yyerrorf("Define or directive not defined: %s",yytext); } "//"[^\n]* { } /* throw away single line comments */ - . {yylval.fileline = CRELINE(); return yytext[0];} /* return single char ops. */ + . { FL; return yytext[0]; } /* return single char ops. */ } /* Catch all - absolutely last */ diff --git a/src/verilog.y b/src/verilog.y index 3dd660ef6..ff1d4974b 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -243,8 +243,8 @@ class AstSenTree; %token yPOSEDGE "posedge" %token yPRIORITY "priority" %token yPROPERTY "property" -%token yPULLDOWN "pulldown" -%token yPULLUP "pullup" +%token yPULLDOWN "pulldown" +%token yPULLUP "pullup" %token yREG "reg" %token yREPEAT "repeat" %token ySCALARED "scalared" @@ -318,6 +318,8 @@ class AstSenTree; %token yVL_PUBLIC_FLAT "/*verilator public_flat*/" %token yVL_PUBLIC_MODULE "/*verilator public_module*/" +%token yP_TICK "'" +%token yP_TICKBRA "'{" %token yP_OROR "||" %token yP_ANDAND "&&" %token yP_NOR "~|" @@ -352,7 +354,12 @@ class AstSenTree; %token yP_COLONDIV ":/" %token yP_ORMINUSGT "|->" %token yP_OREQGT "|=>" +%token yP_BRASTAR "[*" +%token yP_BRAEQ "[=" +%token yP_BRAMINUSGT "[->" +%token yP_PLUSPLUS "++" +%token yP_MINUSMINUS "--" %token yP_PLUSEQ "+=" %token yP_MINUSEQ "-=" %token yP_TIMESEQ "*=" @@ -1747,6 +1754,11 @@ AstText* V3Parse::createTextQuoted(FileLine* fileline, string text) { return new AstText(fileline, newtext); } +//YACC = /kits/sources/bison-2.4.1/src/bison --report=lookahead +// --report=lookahead +// --report=itemset +// --graph +// // Local Variables: // compile-command: "cd obj_dbg ; /usr/bin/bison -y -d -v ../verilog.y ; cat y.output" // End: