Fix constification removing continuous always blocks

git-svn-id: file://localhost/svn/verilator/trunk/verilator@940 77ca24e4-aefa-0310-84f0-b9a241c72d87

include/verilated.cpp

@@ -31,7 +31,7 @@
 //===========================================================================
 // Global variables
 
-int  Verilated::s_randReset = false;
+int  Verilated::s_randReset = 0;
 int  Verilated::s_debug = 1;
 bool Verilated::s_calcUnusedSigs = false;
 bool Verilated::s_gotFinish = false;

src/V3Const.cpp

@@ -802,7 +802,12 @@ private:
 	if (nodep->sensp()->castConst()
 	    || (nodep->varrefp() && nodep->varrefp()->varp()->isParam())) {
 	    // Constants in sensitivity lists may be removed (we'll simplify later)
-	    AstSenItem* newp = new AstSenItem(nodep->fileline(), AstSenItem::Never());
+	    AstSenItem* newp;
+	    if (nodep->isClocked()) {  // A constant can never get a pos/negexge
+		newp = new AstSenItem(nodep->fileline(), AstSenItem::Never());
+	    } else {  // Otherwise it may compute a result that needs to settle out
+		newp = new AstSenItem(nodep->fileline(), AstSenItem::Combo());
+	    }
 	    nodep->replaceWith(newp);
 	    nodep->deleteTree(); nodep=NULL;
 	} else if (nodep->sensp()->castNot()) {

test_regress/driver.pl

@@ -549,6 +549,7 @@ sub _make_main {
 	print $fh "    double sim_time = 1000;\n";
     }
     print $fh "    Verilated::debug(".($self->{verilated_debug}?1:0).");\n";
+    print $fh "    Verilated::randReset(".$self->{verilated_randReset}.");\n" if defined $self->{verilated_randReset};
     print $fh "    topp = new $VM_PREFIX (\"TOP\");\n";
     my $set;
     if ($self->sp) {

test_regress/t/t_func_check.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+$Last_Self->{verilated_randReset} = 1;
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_func_check.v

@@ -0,0 +1,75 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+
+// verilator lint_off WIDTH
+// verilator lint_off VARHIDDEN
+
+module t (
+   clk
+   );
+   input clk;
+   integer 	cyc=0;
+   reg [63:0] 	crc; initial crc = 64'h1;
+
+   chk chk (.clk	(clk),
+	    .rst_l	(1'b1),
+	    .expr	(|crc),
+	    );
+
+   always @ (posedge clk) begin
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      if (cyc==0) begin
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+endmodule
+
+module chk (input clk, input rst_l, input expr);
+
+   integer errors; initial errors = 0;
+
+   task printerr;
+      input [8*64:1] msg;
+      begin
+	 errors = errors + 1;
+	 $write("%%Error: %0s\n", msg);
+	 $stop;
+      end
+   endtask 
+
+   always @(posedge clk) begin
+      if (rst_l) begin
+	 if (expr == 1'b0) begin
+            printerr("expr not asserted");
+	 end
+      end
+   end
+
+   wire noxs = ((expr ^ expr) == 1'b0);
+
+   reg 	  hasx;
+   always @ (noxs) begin
+      if (noxs) begin
+         hasx = 1'b0;
+      end
+      else begin
+         hasx = 1'b1;
+      end
+   end
+
+   always @(posedge clk) begin
+      if (rst_l) begin
+         if (hasx) begin
+            printerr("expr has unknowns");
+         end
+      end
+   end
+
+endmodule