From 0b0b642241f77f4cfbb726493e8c242394aa3af5 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 29 Oct 2022 17:54:12 -0400
Subject: [PATCH 001/156] devel release

---
 Changes      | 7 +++++++
 configure.ac | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/Changes b/Changes
index 7a64aee94..ccadf7afb 100644
--- a/Changes
+++ b/Changes
@@ -8,6 +8,13 @@ The changes in each Verilator version are described below.  The
 contributors that suggested a given feature are shown in []. Thanks!
 
 
+Verilator 5.003 devel
+==========================
+
+**Minor:**
+
+
+
 Verilator 5.002 2022-10-29
 ==========================
 
diff --git a/configure.ac b/configure.ac
index 7994e3554..81000ef74 100644
--- a/configure.ac
+++ b/configure.ac
@@ -10,7 +10,7 @@
 # Then 'make maintainer-dist'
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[5.002 2022-10-29],
+AC_INIT([Verilator],[5.003 devel],
         [https://verilator.org],
         [verilator],[https://verilator.org])
 

From bac98df46b00171025e10544e10a6100b4c20196 Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Tue, 1 Nov 2022 23:53:47 +0100
Subject: [PATCH 002/156] Support named properties (#3667)

---
 src/V3AssertPre.cpp                           |  76 ++++++++++-
 src/V3Ast.h                                   |  16 ++-
 src/V3AstNodeDType.h                          |   1 +
 src/V3AstNodeOther.h                          |  16 ++-
 src/V3LinkInc.cpp                             |   2 +-
 src/V3ParseGrammar.cpp                        |   9 +-
 src/V3Width.cpp                               |  38 +++++-
 src/verilog.l                                 |   2 +-
 src/verilog.y                                 | 123 ++++++++++--------
 test_regress/t/t_assert_clock_event_unsup.out |   5 +
 test_regress/t/t_assert_clock_event_unsup.pl  |  20 +++
 test_regress/t/t_assert_clock_event_unsup.v   |  37 ++++++
 test_regress/t/t_assert_disable_bad.out       |   5 +
 test_regress/t/t_assert_disable_bad.pl        |  20 +++
 test_regress/t/t_assert_disable_bad.v         |  28 ++++
 test_regress/t/t_assert_named_property.pl     |  22 ++++
 test_regress/t/t_assert_named_property.v      |  66 ++++++++++
 test_regress/t/t_assert_property_untyped.pl   |  22 ++++
 test_regress/t/t_assert_property_untyped.v    |  38 ++++++
 .../t/t_assert_property_untyped_unsup.out     |   5 +
 .../t/t_assert_property_untyped_unsup.pl      |  20 +++
 .../t/t_assert_property_untyped_unsup.v       |  33 +++++
 .../t/t_assert_recursive_property_unsup.out   |   6 +
 .../t/t_assert_recursive_property_unsup.pl    |  20 +++
 .../t/t_assert_recursive_property_unsup.v     |  36 +++++
 25 files changed, 594 insertions(+), 72 deletions(-)
 create mode 100644 test_regress/t/t_assert_clock_event_unsup.out
 create mode 100755 test_regress/t/t_assert_clock_event_unsup.pl
 create mode 100644 test_regress/t/t_assert_clock_event_unsup.v
 create mode 100644 test_regress/t/t_assert_disable_bad.out
 create mode 100755 test_regress/t/t_assert_disable_bad.pl
 create mode 100644 test_regress/t/t_assert_disable_bad.v
 create mode 100755 test_regress/t/t_assert_named_property.pl
 create mode 100644 test_regress/t/t_assert_named_property.v
 create mode 100755 test_regress/t/t_assert_property_untyped.pl
 create mode 100644 test_regress/t/t_assert_property_untyped.v
 create mode 100644 test_regress/t/t_assert_property_untyped_unsup.out
 create mode 100755 test_regress/t/t_assert_property_untyped_unsup.pl
 create mode 100644 test_regress/t/t_assert_property_untyped_unsup.v
 create mode 100644 test_regress/t/t_assert_recursive_property_unsup.out
 create mode 100755 test_regress/t/t_assert_recursive_property_unsup.pl
 create mode 100644 test_regress/t/t_assert_recursive_property_unsup.v

diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp
index bb0ae8b27..528efcd96 100644
--- a/src/V3AssertPre.cpp
+++ b/src/V3AssertPre.cpp
@@ -15,6 +15,7 @@
 //*************************************************************************
 //  Pre steps:
 //      Attach clocks to each assertion
+//      Substitute property references by property body (IEEE Std 1800-2012, section 16.12.1).
 //*************************************************************************
 
 #include "config_build.h"
@@ -24,6 +25,7 @@
 
 #include "V3Ast.h"
 #include "V3Global.h"
+#include "V3Task.h"
 
 VL_DEFINE_DEBUG_FUNCTIONS;
 
@@ -67,6 +69,72 @@ private:
         m_senip = nullptr;
         m_disablep = nullptr;
     }
+    AstPropSpec* getPropertyExprp(const AstProperty* const propp) {
+        // The only statements possible in AstProperty are AstPropSpec (body)
+        // and AstVar (arguments).
+        AstNode* propExprp = propp->stmtsp();
+        while (VN_IS(propExprp, Var)) propExprp = propExprp->nextp();
+        return VN_CAST(propExprp, PropSpec);
+    }
+    void replaceVarRefsWithExprRecurse(AstNode* const nodep, const AstVar* varp,
+                                       AstNode* const exprp) {
+        if (!nodep) return;
+        if (const AstVarRef* varrefp = VN_CAST(nodep, VarRef)) {
+            if (varp == varrefp->varp()) nodep->replaceWith(exprp->cloneTree(false));
+        }
+        replaceVarRefsWithExprRecurse(nodep->op1p(), varp, exprp);
+        replaceVarRefsWithExprRecurse(nodep->op2p(), varp, exprp);
+        replaceVarRefsWithExprRecurse(nodep->op3p(), varp, exprp);
+        replaceVarRefsWithExprRecurse(nodep->op4p(), varp, exprp);
+    }
+    AstPropSpec* substitutePropertyCall(AstPropSpec* nodep) {
+        if (AstFuncRef* const funcrefp = VN_CAST(nodep->propp(), FuncRef)) {
+            if (AstProperty* const propp = VN_CAST(funcrefp->taskp(), Property)) {
+                AstPropSpec* propExprp = getPropertyExprp(propp);
+                // Substitute inner property call befory copying in order to not doing the same for
+                // each call of outer property call.
+                propExprp = substitutePropertyCall(propExprp);
+                // Clone subtree after substitution. It is needed, because property might be called
+                // multiple times with different arguments.
+                propExprp = propExprp->cloneTree(false);
+                // Substitute formal arguments with actual arguments
+                const V3TaskConnects tconnects = V3Task::taskConnects(funcrefp, propp->stmtsp());
+                for (const auto& tconnect : tconnects) {
+                    const AstVar* const portp = tconnect.first;
+                    AstArg* const argp = tconnect.second;
+                    AstNode* const pinp = argp->exprp()->unlinkFrBack();
+                    replaceVarRefsWithExprRecurse(propExprp, portp, pinp);
+                }
+                // Handle case with 2 disable iff statement (IEEE 1800-2017 16.12.1)
+                if (nodep->disablep() && propExprp->disablep()) {
+                    nodep->v3error("disable iff expression before property call and in its "
+                                   "body is not legal");
+                }
+                // If disable iff is in outer property, move it to inner
+                if (nodep->disablep()) {
+                    AstNode* const disablep = nodep->disablep()->unlinkFrBack();
+                    propExprp->disablep(disablep);
+                }
+
+                if (nodep->sensesp() && propExprp->sensesp()) {
+                    nodep->v3warn(E_UNSUPPORTED,
+                                  "Unsupported: Clock event before property call and in its body");
+                    pushDeletep(propExprp->sensesp()->unlinkFrBack());
+                }
+                // If clock event is in outer property, move it to inner
+                if (nodep->sensesp()) {
+                    AstSenItem* const sensesp = nodep->sensesp();
+                    sensesp->unlinkFrBack();
+                    propExprp->sensesp(sensesp);
+                }
+
+                // Now substitute property reference with property body
+                nodep->replaceWith(propExprp);
+                return propExprp;
+            }
+        }
+        return nodep;
+    }
 
     // VISITORS
     //========== Statements
@@ -162,7 +230,8 @@ private:
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
     }
 
-    void visit(AstPropClocked* nodep) override {
+    void visit(AstPropSpec* nodep) override {
+        nodep = substitutePropertyCall(nodep);
         // No need to iterate the body, once replace will get iterated
         iterateAndNextNull(nodep->sensesp());
         if (m_senip)
@@ -189,6 +258,11 @@ private:
         // Reset defaults
         m_seniDefaultp = nullptr;
     }
+    void visit(AstProperty* nodep) override {
+        // The body will be visited when will be substituted in place of property reference
+        // (AstFuncRef)
+        VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
+    }
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
diff --git a/src/V3Ast.h b/src/V3Ast.h
index 0253e20fe..c38b73ce2 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -453,6 +453,8 @@ public:
         TIME,
         // Closer to a class type, but limited usage
         STRING,
+        // Property / Sequence argument type
+        UNTYPED,
         // Internal types for mid-steps
         SCOPEPTR,
         CHARPTR,
@@ -485,6 +487,7 @@ public:
                                             "shortint",
                                             "time",
                                             "string",
+                                            "untyped",
                                             "VerilatedScope*",
                                             "char*",
                                             "VlMTaskState",
@@ -501,11 +504,12 @@ public:
     }
     const char* dpiType() const {
         static const char* const names[]
-            = {"%E-unk",        "svBit",         "char",         "void*",           "char",
-               "int",           "%E-integer",    "svLogic",      "long long",       "double",
-               "short",         "%E-time",       "const char*",  "dpiScope",        "const char*",
-               "%E-mtaskstate", "%E-triggervec", "%E-dly-sched", "%E-trig-sched",   "%E-dyn-sched",
-               "%E-fork",       "IData",         "QData",        "%E-logic-implct", " MAX"};
+            = {"%E-unk",       "svBit",         "char",          "void*",        "char",
+               "int",          "%E-integer",    "svLogic",       "long long",    "double",
+               "short",        "%E-time",       "const char*",   "%E-untyped",   "dpiScope",
+               "const char*",  "%E-mtaskstate", "%E-triggervec", "%E-dly-sched", "%E-trig-sched",
+               "%E-dyn-sched", "%E-fork",       "IData",         "QData",        "%E-logic-implct",
+               " MAX"};
         return names[m_e];
     }
     static void selfTest() {
@@ -582,7 +586,7 @@ public:
         return (m_e == EVENT || m_e == STRING || m_e == SCOPEPTR || m_e == CHARPTR
                 || m_e == MTASKSTATE || m_e == TRIGGERVEC || m_e == DELAY_SCHEDULER
                 || m_e == TRIGGER_SCHEDULER || m_e == DYNAMIC_TRIGGER_SCHEDULER || m_e == FORK_SYNC
-                || m_e == DOUBLE);
+                || m_e == DOUBLE || m_e == UNTYPED);
     }
     bool isDouble() const VL_MT_SAFE { return m_e == DOUBLE; }
     bool isEvent() const { return m_e == EVENT; }
diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h
index 010a78d20..a69c0ad8d 100644
--- a/src/V3AstNodeDType.h
+++ b/src/V3AstNodeDType.h
@@ -465,6 +465,7 @@ public:
     int right() const { return littleEndian() ? hi() : lo(); }
     inline bool littleEndian() const;
     bool implicit() const { return keyword() == VBasicDTypeKwd::LOGIC_IMPLICIT; }
+    bool untyped() const { return keyword() == VBasicDTypeKwd::UNTYPED; }
     VNumRange declRange() const { return isRanged() ? VNumRange{left(), right()} : VNumRange{}; }
     void cvtRangeConst();  // Convert to smaller representation
     bool isCompound() const override { return isString(); }
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index a0b3e991f..7343024d4 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -1593,7 +1593,7 @@ public:
         return pragType() == static_cast<const AstPragma*>(samep)->pragType();
     }
 };
-class AstPropClocked final : public AstNode {
+class AstPropSpec final : public AstNode {
     // A clocked property
     // Parents:  ASSERT|COVER (property)
     // Children: SENITEM, Properties
@@ -1601,13 +1601,13 @@ class AstPropClocked final : public AstNode {
     // @astgen op2 := disablep : Optional[AstNode]
     // @astgen op3 := propp : AstNode
 public:
-    AstPropClocked(FileLine* fl, AstSenItem* sensesp, AstNode* disablep, AstNode* propp)
-        : ASTGEN_SUPER_PropClocked(fl) {
+    AstPropSpec(FileLine* fl, AstSenItem* sensesp, AstNode* disablep, AstNode* propp)
+        : ASTGEN_SUPER_PropSpec(fl) {
         this->sensesp(sensesp);
         this->disablep(disablep);
         this->propp(propp);
     }
-    ASTGEN_MEMBERS_AstPropClocked;
+    ASTGEN_MEMBERS_AstPropSpec;
     bool hasDType() const override {
         return true;
     }  // Used under Cover, which expects a bool child
@@ -2433,6 +2433,14 @@ public:
     ASTGEN_MEMBERS_AstFunc;
     bool hasDType() const override { return true; }
 };
+class AstProperty final : public AstNodeFTask {
+    // A property inside a module
+public:
+    AstProperty(FileLine* fl, const string& name, AstNode* stmtp)
+        : ASTGEN_SUPER_Property(fl, name, stmtp) {}
+    ASTGEN_MEMBERS_AstProperty;
+    bool hasDType() const override { return true; }
+};
 class AstTask final : public AstNodeFTask {
     // A task inside a module
 public:
diff --git a/src/V3LinkInc.cpp b/src/V3LinkInc.cpp
index 7c12c4e28..56a7512a8 100644
--- a/src/V3LinkInc.cpp
+++ b/src/V3LinkInc.cpp
@@ -195,7 +195,7 @@ private:
     void visit(AstLogEq* nodep) override { unsupported_visit(nodep); }
     void visit(AstLogIf* nodep) override { unsupported_visit(nodep); }
     void visit(AstNodeCond* nodep) override { unsupported_visit(nodep); }
-    void visit(AstPropClocked* nodep) override { unsupported_visit(nodep); }
+    void visit(AstPropSpec* nodep) override { unsupported_visit(nodep); }
     void prepost_visit(AstNodeTriop* nodep) {
         // Check if we are underneath a statement
         if (!m_insStmtp) {
diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp
index 7781f6eb8..8d495716a 100644
--- a/src/V3ParseGrammar.cpp
+++ b/src/V3ParseGrammar.cpp
@@ -169,7 +169,14 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name,
         dtypep = new AstBasicDType(fileline, VBasicDTypeKwd::DOUBLE);
     }
     if (!dtypep) {  // Created implicitly
-        dtypep = new AstBasicDType(fileline, LOGIC_IMPLICIT);
+        if (m_insideProperty) {
+            if (m_typedPropertyPort) {
+                fileline->v3warn(E_UNSUPPORTED, "Untyped property port following a typed port");
+            }
+            dtypep = new AstBasicDType{fileline, VBasicDTypeKwd::UNTYPED};
+        } else {
+            dtypep = new AstBasicDType{fileline, LOGIC_IMPLICIT};
+        }
     } else {  // May make new variables with same type, so clone
         dtypep = dtypep->cloneTree(false);
     }
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index e5a7050fd..caebfdcd0 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -4027,7 +4027,7 @@ private:
         return times;
     }
 
-    void visit(AstPropClocked* nodep) override {
+    void visit(AstPropSpec* nodep) override {
         if (m_vup->prelim()) {  // First stage evaluation
             iterateCheckBool(nodep, "Property", nodep->propp(), BOTH);
             userIterateAndNext(nodep->sensesp(), nullptr);
@@ -4940,8 +4940,13 @@ private:
             m_funcp = VN_AS(nodep, Func);
             UASSERT_OBJ(m_funcp, nodep, "FTask with function variable, but isn't a function");
             nodep->dtypeFrom(nodep->fvarp());  // Which will get it from fvarp()->dtypep()
+        } else if (VN_IS(nodep, Property)) {
+            nodep->dtypeSetBit();
         }
-        userIterateChildren(nodep, nullptr);
+        WidthVP* vup = nullptr;
+        if (VN_IS(nodep, Property)) vup = WidthVP(SELF, BOTH).p();
+        userIterateChildren(nodep, vup);
+
         nodep->didWidth(true);
         nodep->doingWidth(false);
         m_funcp = nullptr;
@@ -4951,6 +4956,34 @@ private:
                                         // func
         }
     }
+    void visit(AstProperty* nodep) override {
+        if (nodep->didWidth()) return;
+        if (nodep->doingWidth()) {
+            UINFO(5, "Recursive property call: " << nodep);
+            nodep->v3warn(E_UNSUPPORTED,
+                          "Unsupported: Recursive property call: " << nodep->prettyNameQ());
+            nodep->recursive(true);
+            nodep->didWidth(true);
+            return;
+        }
+        nodep->doingWidth(true);
+        m_ftaskp = nodep;
+        // Property call will be replaced by property body in V3AssertPre. Property body has bit
+        // dtype, so set it here too
+        nodep->dtypeSetBit();
+        for (AstNode* propStmtp = nodep->stmtsp(); propStmtp; propStmtp = propStmtp->nextp()) {
+            if (VN_IS(propStmtp, Var)) {
+                userIterate(propStmtp, nullptr);
+            } else if (VN_IS(propStmtp, PropSpec)) {
+                iterateCheckSizedSelf(nodep, "PropSpec", propStmtp, SELF, BOTH);
+            } else {
+                propStmtp->v3fatal("Invalid statement under AstProperty");
+            }
+        }
+        nodep->didWidth(true);
+        nodep->doingWidth(false);
+        m_ftaskp = nullptr;
+    }
     void visit(AstReturn* nodep) override {
         // IEEE: Assignment-like context
         assertAtStatement(nodep);
@@ -5718,6 +5751,7 @@ private:
         UASSERT_OBJ(nodep->dtypep(), nodep,
                     "Under node " << nodep->prettyTypeName()
                                   << " has no dtype?? Missing Visitor func?");
+        if (expDTypep->basicp()->untyped() || nodep->dtypep()->basicp()->untyped()) return false;
         UASSERT_OBJ(nodep->width() != 0, nodep,
                     "Under node " << nodep->prettyTypeName()
                                   << " has no expected width?? Missing Visitor func?");
diff --git a/src/verilog.l b/src/verilog.l
index b2cf6533f..b0a6d01e3 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -598,7 +598,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "unique0"             { FL; return yUNIQUE0; }
   "until"               { ERROR_RSVD_WORD("SystemVerilog 2009"); }
   "until_with"          { ERROR_RSVD_WORD("SystemVerilog 2009"); }
-  "untyped"             { ERROR_RSVD_WORD("SystemVerilog 2009"); }
+  "untyped"             { FL; return yUNTYPED; }
   "weak"                { ERROR_RSVD_WORD("SystemVerilog 2009"); }
 }
 
diff --git a/src/verilog.y b/src/verilog.y
index c73dad6e4..d7668fffe 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -93,6 +93,8 @@ public:
     string m_instModule;  // Name of module referenced for instantiations
     AstPin* m_instParamp = nullptr;  // Parameters for instantiations
     bool m_tracingParse = true;  // Tracing disable for parser
+    bool m_insideProperty = false;  // Is inside property declaration
+    bool m_typedPropertyPort = false;  // True if typed property port occured on port lists
 
     int m_pinNum = -1;  // Pin number currently parsing
     std::stack<int> m_pinStack;  // Queue of pin numbers being parsed
@@ -719,7 +721,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
 %token<fl>              yUNSIGNED       "unsigned"
 //UNSUP %token<fl>      yUNTIL          "until"
 //UNSUP %token<fl>      yUNTIL_WITH     "until_with"
-//UNSUP %token<fl>      yUNTYPED        "untyped"
+%token<fl>              yUNTYPED        "untyped"
 %token<fl>              yVAR            "var"
 %token<fl>              yVECTORED       "vectored"
 %token<fl>              yVIRTUAL__CLASS "virtual-then-class"
@@ -1182,7 +1184,7 @@ package_or_generate_item_declaration<nodep>:    // ==IEEE: package_or_generate_i
         //                      // local_parameter_declaration under parameter_declaration
         |       parameter_declaration ';'               { $$ = $1; }
         //UNSUP covergroup_declaration                  { $$ = $1; }
-        //UNSUP assertion_item_declaration              { $$ = $1; }
+        |       assertion_item_declaration              { $$ = $1; }
         |       ';'                                     { $$ = nullptr; }
         ;
 
@@ -5308,11 +5310,11 @@ clocking_declaration<nodep>:            // IEEE: clocking_declaration  (INCOMPLE
 //************************************************
 // Asserts
 
-//UNSUPassertion_item_declaration:  // ==IEEE: assertion_item_declaration
-//UNSUP         property_declaration                    { $$ = $1; }
+assertion_item_declaration<nodep>:  // ==IEEE: assertion_item_declaration
+                property_declaration                    { $$ = $1; }
 //UNSUP |       sequence_declaration                    { $$ = $1; }
 //UNSUP |       let_declaration                         { $$ = $1; }
-//UNSUP ;
+        ;
 
 assertion_item<nodep>:          // ==IEEE: assertion_item
                 concurrent_assertion_item               { $$ = $1; }
@@ -5411,66 +5413,75 @@ elseStmtBlock<nodep>:   // Part of concurrent_assertion_statement
         |       yELSE stmtBlock                         { $$ = $2; }
         ;
 
-//UNSUPproperty_declaration<nodep>:  // ==IEEE: property_declaration
-//UNSUP         property_declarationFront property_port_listE ';' property_declarationBody
-//UNSUP                 yENDPROPERTY endLabelE
-//UNSUP                 { SYMP->popScope($$); }
-//UNSUP ;
+property_declaration<nodeFTaskp>:  // ==IEEE: property_declaration
+                property_declarationFront property_port_listE ';' property_declarationBody
+                        yENDPROPERTY endLabelE
+                        {   $$ = $1;
+                            $$->addStmtsp($2);
+                            $$->addStmtsp($4);
+                            SYMP->popScope($$);
+                            GRAMMARP->endLabel($<fl>6, $$, $6);
+                            GRAMMARP->m_insideProperty = false;
+                            GRAMMARP->m_typedPropertyPort = false; }
+        ;
 
-//UNSUPproperty_declarationFront<nodep>:  // IEEE: part of property_declaration
-//UNSUP         yPROPERTY idAny/*property_identifier*/
-//UNSUP                 { SYMP->pushNew($$); }
-//UNSUP ;
+property_declarationFront<nodeFTaskp>:  // IEEE: part of property_declaration
+                yPROPERTY idAny/*property_identifier*/
+                        {   $$ = new AstProperty{$1, *$2, nullptr};
+                            GRAMMARP->m_insideProperty = true;
+                            SYMP->pushNewUnderNodeOrCurrent($$, nullptr); }
+        ;
 
-//UNSUPproperty_port_listE<nodep>:  // IEEE: [ ( [ property_port_list ] ) ]
-//UNSUP         /* empty */                             { $$ = nullptr; }
-//UNSUP |       '(' {VARRESET_LIST(""); VARIO("input"); } property_port_list ')'
-//UNSUP                 { VARRESET_NONLIST(""); }
-//UNSUP ;
+property_port_listE<nodep>:  // IEEE: [ ( [ property_port_list ] ) ]
+                /* empty */                       { $$ = nullptr; }
+        |       '(' property_port_list ')'        { $$ = $2; }
+        ;
 
-//UNSUPproperty_port_list<nodep>:  // ==IEEE: property_port_list
-//UNSUP         property_port_item                      { $$ = $1; }
-//UNSUP |       property_port_list ',' property_port_item       { }
-//UNSUP ;
+property_port_list<nodep>:  // ==IEEE: property_port_list
+                property_port_item                              { $$ = $1; }
+        |       property_port_list ',' property_port_item       { $$ = addNextNull($1, $3); }
+        ;
 
-//UNSUPproperty_port_item<nodep>:  // IEEE: property_port_item/sequence_port_item
+property_port_item<nodep>:  // IEEE: property_port_item/sequence_port_item
 //UNSUP //                      // Merged in sequence_port_item
 //UNSUP //                      // IEEE: property_lvar_port_direction ::= yINPUT
 //UNSUP //                      // prop IEEE: [ yLOCAL [ yINPUT ] ] property_formal_type
 //UNSUP //                      //           id {variable_dimension} [ '=' property_actual_arg ]
 //UNSUP //                      // seq IEEE: [ yLOCAL [ sequence_lvar_port_direction ] ] sequence_formal_type
 //UNSUP //                      //           id {variable_dimension} [ '=' sequence_actual_arg ]
-//UNSUP         property_port_itemFront property_port_itemAssignment { }
-//UNSUP ;
+                property_port_itemFront property_port_itemAssignment { $$ = $2; }
+        ;
 
-//UNSUPproperty_port_itemFront: // IEEE: part of property_port_item/sequence_port_item
-//UNSUP         property_port_itemDirE property_formal_typeNoDt         { VARDTYPE($2); }
+property_port_itemFront: // IEEE: part of property_port_item/sequence_port_item
+                property_port_itemDirE property_formal_typeNoDt { VARDTYPE($2); }
 //UNSUP //                      // data_type_or_implicit
-//UNSUP |       property_port_itemDirE data_type                { VARDTYPE($2); }
+        |       property_port_itemDirE data_type
+                        { VARDTYPE($2); GRAMMARP->m_typedPropertyPort = true; }
 //UNSUP |       property_port_itemDirE yVAR data_type           { VARDTYPE($3); }
 //UNSUP |       property_port_itemDirE yVAR implicit_typeE      { VARDTYPE($3); }
 //UNSUP |       property_port_itemDirE signingE rangeList       { VARDTYPE(SPACED($2,$3)); }
-//UNSUP |       property_port_itemDirE /*implicit*/             { /*VARDTYPE-same*/ }
-//UNSUP ;
+        |       property_port_itemDirE implicit_typeE           { VARDTYPE($2); }
+        ;
 
-//UNSUPproperty_port_itemAssignment<nodep>:  // IEEE: part of property_port_item/sequence_port_item/checker_port_direction
-//UNSUP         portSig variable_dimensionListE         { VARDONE($<fl>1, $1, $2, ""); PINNUMINC(); }
+property_port_itemAssignment<nodep>:  // IEEE: part of property_port_item/sequence_port_item/checker_port_direction
+                id variable_dimensionListE         { $$ = VARDONEA($<fl>1, *$1, $2, nullptr); }
 //UNSUP |       portSig variable_dimensionListE '=' property_actual_arg
 //UNSUP                 { VARDONE($<fl>1, $1, $2, $4); PINNUMINC(); }
-//UNSUP ;
+        ;
 
-//UNSUPproperty_port_itemDirE:
-//UNSUP         /* empty */                             { $$ = nullptr; }
-//UNSUP |       yLOCAL__ETC                             { }
-//UNSUP |       yLOCAL__ETC port_direction              { }
-//UNSUP ;
+property_port_itemDirE:
+                /* empty */                             { GRAMMARP->m_pinAnsi = true; VARIO(INPUT); }
+//UNSUP |        yLOCAL__ETC             { GRAMMARP->m_pinAnsi = true; VARIO(INPUT); }
+//UNSUP |        yLOCAL__ETC yINPUT      { GRAMMARP->m_pinAnsi = true; VARIO(INPUT); }
+        ;
 
-//UNSUPproperty_declarationBody<nodep>:  // IEEE: part of property_declaration
+property_declarationBody<nodep>:  // IEEE: part of property_declaration
 //UNSUP         assertion_variable_declarationList property_statement_spec      { }
 //UNSUP //                      // IEEE-2012: Incorectly hasyCOVER ySEQUENCE then property_spec here.
 //UNSUP //                      // Fixed in IEEE 1800-2017
-//UNSUP |       property_statement_spec                 { $$ = $1; }
-//UNSUP ;
+                property_spec                 { $$ = $1; }
+        |       property_spec ';'             { $$ = $1; }
+        ;
 
 //UNSUPassertion_variable_declarationList: // IEEE: part of assertion_variable_declaration
 //UNSUP         assertion_variable_declaration          { $$ = $1; }
@@ -5498,19 +5509,19 @@ elseStmtBlock<nodep>:   // Part of concurrent_assertion_statement
 //UNSUP         property_port_listE                     { $$ = $1; }
 //UNSUP ;
 
-//UNSUPproperty_formal_typeNoDt<nodep>:  // IEEE: property_formal_type (w/o implicit)
-//UNSUP         sequence_formal_typeNoDt                { $$ = $1; }
+property_formal_typeNoDt<nodeDTypep>:  // IEEE: property_formal_type (w/o implicit)
+                sequence_formal_typeNoDt                { $$ = $1; }
 //UNSUP |       yPROPERTY                               { }
-//UNSUP ;
+        ;
 
-//UNSUPsequence_formal_typeNoDt<nodep>:  // ==IEEE: sequence_formal_type (w/o data_type_or_implicit)
-//UNSUP //                      // IEEE: data_type_or_implicit
-//UNSUP //                      // implicit expanded where used
+sequence_formal_typeNoDt<nodeDTypep>:  // ==IEEE: sequence_formal_type (w/o data_type_or_implicit)
+//                      // IEEE: data_type_or_implicit
+//                      // implicit expanded where used
 //UNSUP         ySEQUENCE                               { }
-//UNSUP //                      // IEEE-2009: yEVENT
-//UNSUP //                      // already part of data_type.  Removed in 1800-2012.
-//UNSUP |       yUNTYPED                                { }
-//UNSUP ;
+//                      // IEEE-2009: yEVENT
+//                      // already part of data_type.  Removed in 1800-2012.
+                yUNTYPED                                { $$ = nullptr; GRAMMARP->m_typedPropertyPort = false; }
+        ;
 
 //UNSUPsequence_declarationBody<nodep>:  // IEEE: part of sequence_declaration
 //UNSUP //                      // 1800-2012 makes ';' optional
@@ -5524,11 +5535,11 @@ property_spec<nodep>:                   // IEEE: property_spec
         //UNSUP: This rule has been super-specialized to what is supported now
         //UNSUP remove below
                 '@' '(' senitemEdge ')' yDISABLE yIFF '(' expr ')' pexpr
-                        { $$ = new AstPropClocked($1, $3, $8, $10); }
-        |       '@' '(' senitemEdge ')' pexpr           { $$ = new AstPropClocked($1, $3, nullptr, $5); }
+                        { $$ = new AstPropSpec{$1, $3, $8, $10}; }
+        |       '@' '(' senitemEdge ')' pexpr           { $$ = new AstPropSpec{$1, $3, nullptr, $5}; }
         //UNSUP remove above
-        |       yDISABLE yIFF '(' expr ')' pexpr        { $$ = new AstPropClocked($4->fileline(), nullptr, $4, $6); }
-        |       pexpr                                   { $$ = new AstPropClocked($1->fileline(), nullptr, nullptr, $1); }
+        |       yDISABLE yIFF '(' expr ')' pexpr        { $$ = new AstPropSpec{$4->fileline(), nullptr, $4, $6}; }
+        |       pexpr                                   { $$ = new AstPropSpec{$1->fileline(), nullptr, nullptr, $1}; }
         ;
 
 //UNSUPproperty_statement_spec<nodep>:  // ==IEEE: property_statement_spec
diff --git a/test_regress/t/t_assert_clock_event_unsup.out b/test_regress/t/t_assert_clock_event_unsup.out
new file mode 100644
index 000000000..56484ebb6
--- /dev/null
+++ b/test_regress/t/t_assert_clock_event_unsup.out
@@ -0,0 +1,5 @@
+%Error-UNSUPPORTED: t/t_assert_clock_event_unsup.v:26:7: Unsupported: Clock event before property call and in its body
+   26 |       @(negedge clk)
+      |       ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to
diff --git a/test_regress/t/t_assert_clock_event_unsup.pl b/test_regress/t/t_assert_clock_event_unsup.pl
new file mode 100755
index 000000000..f201521f0
--- /dev/null
+++ b/test_regress/t/t_assert_clock_event_unsup.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    expect_filename=>$Self->{golden_filename},
+    verilator_flags2=> ['--assert'],
+    fails => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_assert_clock_event_unsup.v b/test_regress/t/t_assert_clock_event_unsup.v
new file mode 100644
index 000000000..6737ff316
--- /dev/null
+++ b/test_regress/t/t_assert_clock_event_unsup.v
@@ -0,0 +1,37 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+   int cyc = 0;
+   logic val = 0;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      val = ~val;
+   end
+
+   property check(int cyc_mod_2, logic expected);
+      @(posedge clk)
+        cyc % 2 == cyc_mod_2 |=> val == expected;
+   endproperty
+
+   property check_if_1(int cyc_mod_2);
+      @(negedge clk)
+        check(cyc_mod_2, 1);
+   endproperty
+
+   assert property(check_if_1(1))
+     else begin
+        // Assertion should fail
+        $write("*-* All Finished *-*\n");
+        $finish;
+     end
+
+endmodule
diff --git a/test_regress/t/t_assert_disable_bad.out b/test_regress/t/t_assert_disable_bad.out
new file mode 100644
index 000000000..a53fbe9d1
--- /dev/null
+++ b/test_regress/t/t_assert_disable_bad.out
@@ -0,0 +1,5 @@
+%Error: t/t_assert_disable_bad.v:27:38: disable iff expression before property call and in its body is not legal
+                                      : ... In instance t
+   27 |    assert property (disable iff (val == 0) check(1, 1));
+      |                                      ^~
+%Error: Exiting due to
diff --git a/test_regress/t/t_assert_disable_bad.pl b/test_regress/t/t_assert_disable_bad.pl
new file mode 100755
index 000000000..f201521f0
--- /dev/null
+++ b/test_regress/t/t_assert_disable_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    expect_filename=>$Self->{golden_filename},
+    verilator_flags2=> ['--assert'],
+    fails => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_assert_disable_bad.v b/test_regress/t/t_assert_disable_bad.v
new file mode 100644
index 000000000..cb0f84b7d
--- /dev/null
+++ b/test_regress/t/t_assert_disable_bad.v
@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+   int cyc = 0;
+   logic val = 0;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      val = ~val;
+   end
+
+   property check(int cyc_mod_2, logic expected);
+      @(posedge clk)
+        disable iff (cyc == 0) cyc % 2 == cyc_mod_2 |=> val == expected;
+   endproperty
+
+   // Test should fail due to duplicated disable iff statements
+   // (IEEE Std 1800-2012, section 16.12.1).
+   assert property (disable iff (val == 0) check(1, 1));
+endmodule
diff --git a/test_regress/t/t_assert_named_property.pl b/test_regress/t/t_assert_named_property.pl
new file mode 100755
index 000000000..c505d6263
--- /dev/null
+++ b/test_regress/t/t_assert_named_property.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['--assert'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_assert_named_property.v b/test_regress/t/t_assert_named_property.v
new file mode 100644
index 000000000..63e4f6a33
--- /dev/null
+++ b/test_regress/t/t_assert_named_property.v
@@ -0,0 +1,66 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+   int cyc = 0;
+   logic val = 0;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      val = ~val;
+   end
+
+   property check(int cyc_mod_2, logic expected);
+      @(posedge clk)
+        cyc % 2 == cyc_mod_2 |=> val == expected;
+   endproperty
+
+   property check_if_1(int cyc_mod_2);
+      check(cyc_mod_2, 1);
+   endproperty
+
+   property check_if_gt_5(int cyc);
+      @(posedge clk)
+        cyc > 5;
+   endproperty
+
+   property pass_assertion(int cyc);
+      disable iff (cyc <= 10)
+      cyc > 10;
+   endproperty
+
+   int expected_fails = 0;
+
+   assert property(check(0, 1))
+     else begin
+        // Assertion should pass
+        $display("Assert failed, but shouldn't");
+        $stop;
+     end
+   assert property(check(1, 1))
+     else begin
+        // Assertion should fail
+        expected_fails += 1;
+     end
+   assert property(check_if_1(1))
+     else begin
+        // Assertion should fail
+        expected_fails += 1;
+     end
+   assert property(disable iff (cyc < 5) check_if_gt_5(cyc + 1));
+   assert property(@(posedge clk) pass_assertion(cyc));
+
+   always @(posedge clk) begin
+      if (expected_fails == 2) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule
diff --git a/test_regress/t/t_assert_property_untyped.pl b/test_regress/t/t_assert_property_untyped.pl
new file mode 100755
index 000000000..c505d6263
--- /dev/null
+++ b/test_regress/t/t_assert_property_untyped.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['--assert'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_assert_property_untyped.v b/test_regress/t/t_assert_property_untyped.v
new file mode 100644
index 000000000..29fbd99c2
--- /dev/null
+++ b/test_regress/t/t_assert_property_untyped.v
@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+   int cyc = 0;
+   logic [4:0] val = 0;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      val = ~val;
+   end
+
+   property check(cyc_mod_2, untyped expected);
+      @(posedge clk)
+        cyc % 2 == cyc_mod_2 |=> val == expected;
+   endproperty
+
+   assert property(check(0, 5'b11111))
+     else begin
+        // Assertion should pass
+        $display("Assert failed, but shouldn't");
+        $stop;
+     end
+
+   always @(posedge clk) begin
+      if (cyc == 10) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule
diff --git a/test_regress/t/t_assert_property_untyped_unsup.out b/test_regress/t/t_assert_property_untyped_unsup.out
new file mode 100644
index 000000000..e9985890c
--- /dev/null
+++ b/test_regress/t/t_assert_property_untyped_unsup.out
@@ -0,0 +1,5 @@
+%Error-UNSUPPORTED: t/t_assert_property_untyped_unsup.v:20:52: Untyped property port following a typed port
+   20 |    property check(cyc_mod_2, logic [4:0] expected, arg3, untyped arg4, arg5);
+      |                                                    ^~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to
diff --git a/test_regress/t/t_assert_property_untyped_unsup.pl b/test_regress/t/t_assert_property_untyped_unsup.pl
new file mode 100755
index 000000000..f201521f0
--- /dev/null
+++ b/test_regress/t/t_assert_property_untyped_unsup.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    expect_filename=>$Self->{golden_filename},
+    verilator_flags2=> ['--assert'],
+    fails => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_assert_property_untyped_unsup.v b/test_regress/t/t_assert_property_untyped_unsup.v
new file mode 100644
index 000000000..9784c48fc
--- /dev/null
+++ b/test_regress/t/t_assert_property_untyped_unsup.v
@@ -0,0 +1,33 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+   int cyc = 0;
+   logic [4:0] val = 0;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      val = ~val;
+   end
+
+   property check(cyc_mod_2, logic [4:0] expected, arg3, untyped arg4, arg5);
+      @(posedge clk)
+        cyc % 2 == cyc_mod_2 |=> val == expected;
+   endproperty
+
+   assert property(check(0, 5'b11111, 100, 25, 17));
+
+   always @(posedge clk) begin
+      if (cyc == 10) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+endmodule
diff --git a/test_regress/t/t_assert_recursive_property_unsup.out b/test_regress/t/t_assert_recursive_property_unsup.out
new file mode 100644
index 000000000..fbca8fd7c
--- /dev/null
+++ b/test_regress/t/t_assert_recursive_property_unsup.out
@@ -0,0 +1,6 @@
+%Error-UNSUPPORTED: t/t_assert_recursive_property_unsup.v:20:4: Unsupported: Recursive property call: 'check'
+                                                              : ... In instance t
+   20 |    property check(int n);
+      |    ^~~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Exiting due to
diff --git a/test_regress/t/t_assert_recursive_property_unsup.pl b/test_regress/t/t_assert_recursive_property_unsup.pl
new file mode 100755
index 000000000..f201521f0
--- /dev/null
+++ b/test_regress/t/t_assert_recursive_property_unsup.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    expect_filename=>$Self->{golden_filename},
+    verilator_flags2=> ['--assert'],
+    fails => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_assert_recursive_property_unsup.v b/test_regress/t/t_assert_recursive_property_unsup.v
new file mode 100644
index 000000000..b6d91ad47
--- /dev/null
+++ b/test_regress/t/t_assert_recursive_property_unsup.v
@@ -0,0 +1,36 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+   int cyc = 0;
+   logic val = 0;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      val = ~val;
+   end
+
+   property check(int n);
+      disable iff (n == 0)
+        check(n - 1);
+   endproperty
+
+   assert property(@(posedge clk) check(1))
+     else begin
+        // Assertion should pass
+        $write("*-* Assertion failed *-*\n");
+        $stop;
+     end
+
+   always @(posedge clk) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

From cf4c00e3b41fb015f497469cddc3132eccd660c9 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 2 Nov 2022 20:11:25 -0400
Subject: [PATCH 003/156] Internals: if assertion should be VL_UNLIKELY

---
 src/V3Sched.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp
index 36a23771f..50f8f12ea 100644
--- a/src/V3Sched.cpp
+++ b/src/V3Sched.cpp
@@ -574,6 +574,7 @@ std::pair<AstVarScope*, AstNode*> makeEvalLoop(AstNetlist* netlistp, const strin
                 constp->num().setLong(limit);
                 AstNodeMath* const condp = new AstGt{flp, refp, constp};
                 AstIf* const failp = new AstIf{flp, condp};
+                failp->branchPred(VBranchPred::BP_UNLIKELY);
                 ifp->addThensp(failp);
                 AstTextBlock* const blockp = new AstTextBlock{flp};
                 failp->addThensp(blockp);

From 65e08f4dbfe119bb4de87e83c95bbfc2aedeb9e5 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Wed, 12 Oct 2022 10:19:21 +0100
Subject: [PATCH 004/156] Make all expressions derive from AstNodeExpr (#3721).

Apart from the representational changes below, this patch renames
AstNodeMath to AstNodeExpr, and AstCMath to AstCExpr.

Now every expression (i.e.: those AstNodes that represent a [possibly
void] value, with value being interpreted in a very general sense) has
AstNodeExpr as a super class. This necessitates the introduction of an
AstStmtExpr, which represents an expression in statement position, e.g :
'foo();' would be represented as AstStmtExpr(AstCCall(foo)). In exchange
we can get rid of isStatement() in AstNodeStmt, which now really always
represent a statement

Peak memory consumption and verilation speed are not measurably changed.

Partial step towards #3420
---
 docs/internals.rst                       |   11 +-
 include/verilated.cpp                    |    2 +-
 include/verilated_funcs.h                |    4 +-
 src/Makefile_obj.in                      |    4 +-
 src/V3ActiveTop.cpp                      |    2 +-
 src/V3Assert.cpp                         |    2 +-
 src/V3Ast.h                              |    8 +-
 src/V3AstInlines.h                       |    6 +-
 src/{V3AstNodeMath.h => V3AstNodeExpr.h} |  753 ++++++++--
 src/V3AstNodeOther.h                     |  552 +------
 src/V3AstNodes.cpp                       |   38 +-
 src/V3CCtors.cpp                         |    3 +-
 src/V3Cast.cpp                           |    7 +-
 src/V3Cdc.cpp                            |    4 +-
 src/V3Class.cpp                          |    2 +-
 src/V3Clean.cpp                          |    4 +-
 src/V3Combine.cpp                        |    4 +-
 src/V3Common.cpp                         |    6 +-
 src/V3Const.cpp                          |   12 +-
 src/V3CoverageJoin.cpp                   |    2 +-
 src/V3Delayed.cpp                        |    6 +-
 src/V3Depth.cpp                          |   10 +-
 src/V3DepthBlock.cpp                     |   20 +-
 src/V3Descope.cpp                        |   13 +-
 src/V3Dfg.h                              |    2 +-
 src/V3DfgAstToDfg.cpp                    |    4 +-
 src/V3DfgDfgToAst.cpp                    |   66 +-
 src/V3DfgOptimizer.cpp                   |   12 +-
 src/V3EmitCFunc.cpp                      |    9 +-
 src/V3EmitCFunc.h                        |   21 +-
 src/V3EmitMk.cpp                         |    4 +-
 src/V3EmitV.cpp                          |   12 +-
 src/V3EmitXml.cpp                        |    4 +-
 src/V3Expand.cpp                         |    4 -
 src/V3Force.cpp                          |    2 +-
 src/V3Gate.cpp                           |    6 +-
 src/V3Hasher.cpp                         |    4 +-
 src/V3HierBlock.cpp                      |    2 +-
 src/V3Inline.cpp                         |    2 +-
 src/V3Inst.cpp                           |    6 +-
 src/V3Life.cpp                           |    4 +-
 src/V3LinkDot.cpp                        |    1 +
 src/V3LinkInc.cpp                        |    4 -
 src/V3LinkResolve.cpp                    |    2 +-
 src/V3Order.cpp                          |    3 +-
 src/V3Partition.cpp                      |    3 +-
 src/V3Premit.cpp                         |   15 +-
 src/V3Randomize.cpp                      |    2 +-
 src/V3Reloop.cpp                         |    2 +-
 src/V3Sched.cpp                          |  107 +-
 src/V3SchedTiming.cpp                    |   37 +-
 src/V3SenExprBuilder.h                   |    8 +-
 src/V3SplitAs.cpp                        |    7 +-
 src/V3SplitVar.cpp                       |   71 +-
 src/V3Task.cpp                           |   44 +-
 src/V3Timing.cpp                         |   59 +-
 src/V3Trace.cpp                          |   43 +-
 src/V3TraceDecl.cpp                      |    6 +-
 src/V3Width.cpp                          |   96 +-
 src/Verilator.cpp                        |    2 +-
 src/astgen                               |    2 +-
 src/verilog.y                            |   97 +-
 test_regress/t/t_debug_emitv.out         |    6 +-
 test_regress/t/t_func_tasknsvar_bad.out  |    2 +-
 test_regress/t/t_xml_debugcheck.out      | 1684 +++++++++++-----------
 test_regress/t/t_xml_tag.out             |   31 +-
 66 files changed, 2005 insertions(+), 1968 deletions(-)
 rename src/{V3AstNodeMath.h => V3AstNodeExpr.h} (87%)

diff --git a/docs/internals.rst b/docs/internals.rst
index a3f70ea36..3c4a2404b 100644
--- a/docs/internals.rst
+++ b/docs/internals.rst
@@ -114,6 +114,13 @@ you are at the top of the tree.
 By convention, each function/method uses the variable ``nodep`` as a
 pointer to the ``AstNode`` currently being processed.
 
+There are notable sub-hierarchies of the ``AstNode`` sub-types, namely:
+
+1. All AST nodes representing data types derive from ``AstNodeDType``.
+
+2. All AST nodes representing expressions (i.e.: anything that stands for,
+   or evaluates to a value) derive from ``AstNodeExpr``.
+
 
 ``VNVisitor``
 ^^^^^^^^^^^^^^^
@@ -205,7 +212,7 @@ writing DFG passes easier.
 
 The ``DfgGraph`` represents combinational logic equations as a graph of
 ``DfgVertex`` vertices. Each sub-class of ``DfgVertex`` corresponds to an
-expression (a sub-class of ``AstNodeMath``), a constanat, or a variable
+expression (a sub-class of ``AstNodeExpr``), a constanat, or a variable
 reference. LValues and RValues referencing the same storage location are
 represented by the same ``DfgVertex``. Consumers of such vertices read as the
 LValue, writers of such vertices write the RValue. The bulk of the final
@@ -1117,7 +1124,7 @@ will be used as the base name of the generated operand accessors, and
 
 
 An example of the full syntax of the directive is
-``@astgen op1 := lhsp : AstNodeMath``.
+``@astgen op1 := lhsp : AstNodeExpr``.
 
 ``astnode`` generates accessors for the child nodes based on these directives.
 For non-list children, the names of the getter and setter both are that of the
diff --git a/include/verilated.cpp b/include/verilated.cpp
index 6428c4ee5..0d0d1a5c8 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -395,7 +395,7 @@ void _vl_debug_print_w(int lbits, const WDataInP iwp) VL_MT_SAFE {
 }
 
 //===========================================================================
-// Slow math
+// Slow expressions
 
 WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WDataInP rwp,
                        bool is_modulus) VL_MT_SAFE {
diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h
index 8f5027f96..1733d33d4 100644
--- a/include/verilated_funcs.h
+++ b/include/verilated_funcs.h
@@ -929,7 +929,7 @@ static inline int _vl_cmps_w(int lbits, WDataInP const lwp, WDataInP const rwp)
 }
 
 //=========================================================================
-// Math
+// Expressions
 
 // Output NOT clean
 static inline WDataOutP VL_NEGATE_W(int words, WDataOutP owp, WDataInP const lwp) VL_MT_SAFE {
@@ -1917,7 +1917,7 @@ static inline WDataOutP VL_SEL_WWII(int obits, int lbits, WDataOutP owp, WDataIn
 }
 
 //======================================================================
-// Math needing insert/select
+// Expressions needing insert/select
 
 // Return QData from double (numeric)
 // EMIT_RULE: VL_RTOIROUND_Q_D:  oclean=dirty; lclean==clean/real
diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in
index bcde753fc..616b9c43e 100644
--- a/src/Makefile_obj.in
+++ b/src/Makefile_obj.in
@@ -288,14 +288,14 @@ VLCOV_OBJS = \
 NON_STANDALONE_HEADERS = \
 	V3AstInlines.h  \
 	V3AstNodeDType.h  \
-	V3AstNodeMath.h  \
+	V3AstNodeExpr.h  \
 	V3AstNodeOther.h  \
 	V3DfgVertices.h  \
 	V3WidthCommit.h  \
 
 AST_DEFS := \
   V3AstNodeDType.h \
-  V3AstNodeMath.h \
+  V3AstNodeExpr.h \
   V3AstNodeOther.h \
 
 DFG_DEFS := \
diff --git a/src/V3ActiveTop.cpp b/src/V3ActiveTop.cpp
index 2be352c17..47f183122 100644
--- a/src/V3ActiveTop.cpp
+++ b/src/V3ActiveTop.cpp
@@ -129,7 +129,7 @@ class ActiveTopVisitor final : public VNVisitor {
         nodep->v3fatalSrc("Node should have been under ACTIVE");
     }
     //--------------------
-    void visit(AstNodeMath*) override {}  // Accelerate
+    void visit(AstNodeExpr*) override {}  // Accelerate
     void visit(AstVarScope*) override {}  // Accelerate
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp
index 40d9f609f..62976a59a 100644
--- a/src/V3Assert.cpp
+++ b/src/V3Assert.cpp
@@ -105,7 +105,7 @@ private:
                  // This allows syntax errors and such to be detected normally.
                  (v3Global.opt.assertOn()
                       ? static_cast<AstNode*>(
-                          new AstCMath{fl, "vlSymsp->_vm_contextp__->assertOn()", 1})
+                          new AstCExpr{fl, "vlSymsp->_vm_contextp__->assertOn()", 1})
                       : static_cast<AstNode*>(new AstConst{fl, AstConst::BitFalse{}}))),
             nodep};
         newp->isBoundsCheck(true);  // To avoid LATCH warning
diff --git a/src/V3Ast.h b/src/V3Ast.h
index c38b73ce2..0e8f277a7 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -2218,11 +2218,11 @@ void AstNode::addPrev(AstNode* newp) {
 // Specializations of AstNode::mayBeUnder
 template <>
 inline bool AstNode::mayBeUnder<AstCell>(const AstNode* nodep) {
-    return !VN_IS(nodep, NodeStmt) && !VN_IS(nodep, NodeMath);
+    return !VN_IS(nodep, NodeStmt) && !VN_IS(nodep, NodeExpr);
 }
 template <>
 inline bool AstNode::mayBeUnder<AstNodeAssign>(const AstNode* nodep) {
-    return !VN_IS(nodep, NodeMath);
+    return !VN_IS(nodep, NodeExpr);
 }
 template <>
 inline bool AstNode::mayBeUnder<AstVarScope>(const AstNode* nodep) {
@@ -2230,7 +2230,7 @@ inline bool AstNode::mayBeUnder<AstVarScope>(const AstNode* nodep) {
     if (VN_IS(nodep, Var)) return false;
     if (VN_IS(nodep, Active)) return false;
     if (VN_IS(nodep, NodeStmt)) return false;
-    if (VN_IS(nodep, NodeMath)) return false;
+    if (VN_IS(nodep, NodeExpr)) return false;
     return true;
 }
 template <>
@@ -2512,7 +2512,7 @@ AstNode* VNVisitor::iterateSubtreeReturnEdits(AstNode* nodep) {
 
 // AstNode subclasses
 #include "V3AstNodeDType.h"
-#include "V3AstNodeMath.h"
+#include "V3AstNodeExpr.h"
 #include "V3AstNodeOther.h"
 
 // Inline function definitions need to go last
diff --git a/src/V3AstInlines.h b/src/V3AstInlines.h
index 144419d05..3793225c0 100644
--- a/src/V3AstInlines.h
+++ b/src/V3AstInlines.h
@@ -141,8 +141,8 @@ AstCStmt::AstCStmt(FileLine* fl, const string& textStmt)
     addExprsp(new AstText{fl, textStmt, true});
 }
 
-AstCMath::AstCMath(FileLine* fl, const string& textStmt, int setwidth, bool cleanOut)
-    : ASTGEN_SUPER_CMath(fl)
+AstCExpr::AstCExpr(FileLine* fl, const string& textStmt, int setwidth, bool cleanOut)
+    : ASTGEN_SUPER_CExpr(fl)
     , m_cleanOut{cleanOut}
     , m_pure{true} {
     addExprsp(new AstText{fl, textStmt, true});
@@ -180,4 +180,6 @@ AstVarXRef::AstVarXRef(FileLine* fl, AstVar* varp, const string& dotted, const V
     dtypeFrom(varp);
 }
 
+AstStmtExpr* AstNodeExpr::makeStmt() { return new AstStmtExpr{fileline(), this}; }
+
 #endif  // Guard
diff --git a/src/V3AstNodeMath.h b/src/V3AstNodeExpr.h
similarity index 87%
rename from src/V3AstNodeMath.h
rename to src/V3AstNodeExpr.h
index ef635a14a..305ac78b8 100644
--- a/src/V3AstNodeMath.h
+++ b/src/V3AstNodeExpr.h
@@ -14,20 +14,14 @@
 //
 //*************************************************************************
 //
-// This files contains all 'AstNode' sub-types that representing expressions,
-// i.e.: those constructs that evaluate to [a possible void/unit] value.  The
-// root of the hierarchy is 'AstNodeMath', which could also be called
-// 'AstNodeExpr'.
-//
-// Warning: Although the above is what we are aiming for, currently there are
-// some 'AstNode' sub-types defined elsewhere, that represent expressions but
-// are not part of the `AstNodeMath` hierarchy (e.g.: 'AstNodeCall' and its
-// sub-types). These should eventually be fixed and moved under 'AstNodeMath'.
+// This files contains all 'AstNode' sub-types that represent expressions,
+// i.e.: those constructs that represent, or evaluate to [a possible void]
+// value. The root of the hierarchy is 'AstNodeExpr'.
 //
 //*************************************************************************
 
-#ifndef VERILATOR_V3ASTNODEMATH_H_
-#define VERILATOR_V3ASTNODEMATH_H_
+#ifndef VERILATOR_V3ASTNODEEXPR_H_
+#define VERILATOR_V3ASTNODEEXPR_H_
 
 #ifndef VERILATOR_V3AST_H_
 #error "Use V3Ast.h as the include"
@@ -37,34 +31,37 @@
 
 // === Abstract base node types (AstNode*) =====================================
 
-class AstNodeMath VL_NOT_FINAL : public AstNode {
-    // Math -- anything that's part of an expression tree
+class AstNodeExpr VL_NOT_FINAL : public AstNode {
+    // An expression tree node
 protected:
-    AstNodeMath(VNType t, FileLine* fl)
+    AstNodeExpr(VNType t, FileLine* fl)
         : AstNode{t, fl} {}
 
 public:
-    ASTGEN_MEMBERS_AstNodeMath;
+    ASTGEN_MEMBERS_AstNodeExpr;
     // METHODS
     void dump(std::ostream& str) const override;
-    bool hasDType() const override { return true; }
+    bool hasDType() const final override { return true; }
     virtual string emitVerilog() = 0;  /// Format string for verilog writing; see V3EmitV
     // For documentation on emitC format see EmitCFunc::emitOpName
     virtual string emitC() = 0;
     virtual string emitSimpleOperator() { return ""; }  // "" means not ok to use
     virtual bool emitCheckMaxWords() { return false; }  // Check VL_MULS_MAX_WORDS
     virtual bool cleanOut() const = 0;  // True if output has extra upper bits zero
-    // Someday we will generically support data types on every math node
+    // Someday we will generically support data types on every expr node
     // Until then isOpaque indicates we shouldn't constant optimize this node type
     bool isOpaque() const { return VN_IS(this, CvtPackString); }
+
+    // Wrap This expression into an AstStmtExpr to denote it occurs in statement position
+    inline AstStmtExpr* makeStmt();
 };
-class AstNodeBiop VL_NOT_FINAL : public AstNodeMath {
+class AstNodeBiop VL_NOT_FINAL : public AstNodeExpr {
     // Binary expression
     // @astgen op1 := lhsp : AstNode
     // @astgen op2 := rhsp : AstNode
 protected:
     AstNodeBiop(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp)
-        : AstNodeMath{t, fl} {
+        : AstNodeExpr{t, fl} {
         this->lhsp(lhsp);
         this->rhsp(rhsp);
     }
@@ -88,7 +85,7 @@ public:
     bool same(const AstNode*) const override { return true; }
 };
 class AstNodeBiCom VL_NOT_FINAL : public AstNodeBiop {
-    // Binary math with commutative properties
+    // Binary expr with commutative properties
 protected:
     AstNodeBiCom(VNType t, FileLine* fl, AstNode* lhs, AstNode* rhs)
         : AstNodeBiop{t, fl, lhs, rhs} {}
@@ -97,7 +94,7 @@ public:
     ASTGEN_MEMBERS_AstNodeBiCom;
 };
 class AstNodeBiComAsv VL_NOT_FINAL : public AstNodeBiCom {
-    // Binary math with commutative & associative properties
+    // Binary expr with commutative & associative properties
 protected:
     AstNodeBiComAsv(VNType t, FileLine* fl, AstNode* lhs, AstNode* rhs)
         : AstNodeBiCom{t, fl, lhs, rhs} {}
@@ -116,7 +113,6 @@ protected:
 public:
     ASTGEN_MEMBERS_AstNodeSel;
     int bitConst() const;
-    bool hasDType() const override { return true; }
 };
 class AstNodeStream VL_NOT_FINAL : public AstNodeBiop {
     // Verilog {rhs{lhs}} - Note rhsp() is the slice size, not the lhsp()
@@ -144,7 +140,113 @@ public:
     int instrCount() const override { return INSTR_COUNT_DBL_TRIG; }
     bool doubleFlavor() const override { return true; }
 };
-class AstNodeQuadop VL_NOT_FINAL : public AstNodeMath {
+class AstNodeCCall VL_NOT_FINAL : public AstNodeExpr {
+    // A call of a C++ function, perhaps a AstCFunc or perhaps globally named
+    // @astgen op2 := argsp : List[AstNode] // Note: op1 used by some sub-types only
+    AstCFunc* m_funcp;
+    string m_argTypes;
+
+protected:
+    AstNodeCCall(VNType t, FileLine* fl, AstCFunc* funcp, AstNode* argsp = nullptr)
+        : AstNodeExpr{t, fl}
+        , m_funcp{funcp} {
+        addArgsp(argsp);
+    }
+
+public:
+    ASTGEN_MEMBERS_AstNodeCCall;
+    void dump(std::ostream& str = std::cout) const override;
+    void cloneRelink() override;
+    const char* broken() const override;
+    int instrCount() const override { return INSTR_COUNT_CALL; }
+    bool same(const AstNode* samep) const override {
+        const AstNodeCCall* const asamep = static_cast<const AstNodeCCall*>(samep);
+        return (funcp() == asamep->funcp() && argTypes() == asamep->argTypes());
+    }
+    bool isGateOptimizable() const override { return false; }
+    bool isPredictOptimizable() const override { return false; }
+    bool isPure() const override;
+    bool isOutputter() const override { return !isPure(); }
+    AstCFunc* funcp() const { return m_funcp; }
+    void funcp(AstCFunc* funcp) { m_funcp = funcp; }
+    void argTypes(const string& str) { m_argTypes = str; }
+    string argTypes() const { return m_argTypes; }
+
+    string emitVerilog() final override { V3ERROR_NA_RETURN(""); }
+    string emitC() final override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const final override { return true; }
+};
+class AstNodeFTaskRef VL_NOT_FINAL : public AstNodeExpr {
+    // A reference to a task (or function)
+    // @astgen op1 := namep : Optional[AstNode]
+    // op2 used by some sub-types only
+    // @astgen op3 := pinsp : List[AstNode]
+    // @astgen op4 := scopeNamep : Optional[AstScopeName]
+    AstNodeFTask* m_taskp = nullptr;  // [AfterLink] Pointer to task referenced
+    AstNodeModule* m_classOrPackagep = nullptr;  // Package hierarchy
+    string m_name;  // Name of variable
+    string m_dotted;  // Dotted part of scope the name()ed task/func is under or ""
+    string m_inlinedDots;  // Dotted hierarchy flattened out
+    bool m_pli = false;  // Pli system call ($name)
+protected:
+    AstNodeFTaskRef(VNType t, FileLine* fl, AstNode* namep, AstNode* pinsp)
+        : AstNodeExpr{t, fl} {
+        this->namep(namep);
+        this->addPinsp(pinsp);
+    }
+    AstNodeFTaskRef(VNType t, FileLine* fl, const string& name, AstNode* pinsp)
+        : AstNodeExpr{t, fl}
+        , m_name{name} {
+        this->addPinsp(pinsp);
+    }
+
+public:
+    ASTGEN_MEMBERS_AstNodeFTaskRef;
+    const char* broken() const override;
+    void cloneRelink() override;
+    void dump(std::ostream& str = std::cout) const override;
+    string name() const override { return m_name; }  // * = Var name
+    bool isGateOptimizable() const override;
+    string dotted() const { return m_dotted; }  // * = Scope name or ""
+    string inlinedDots() const { return m_inlinedDots; }
+    void inlinedDots(const string& flag) { m_inlinedDots = flag; }
+    AstNodeFTask* taskp() const { return m_taskp; }  // [After Link] Pointer to variable
+    void taskp(AstNodeFTask* taskp) { m_taskp = taskp; }
+    void name(const string& name) override { m_name = name; }
+    void dotted(const string& name) { m_dotted = name; }
+    AstNodeModule* classOrPackagep() const { return m_classOrPackagep; }
+    void classOrPackagep(AstNodeModule* nodep) { m_classOrPackagep = nodep; }
+    bool pli() const { return m_pli; }
+    void pli(bool flag) { m_pli = flag; }
+
+    string emitVerilog() final override { V3ERROR_NA_RETURN(""); }
+    string emitC() final override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const final override { V3ERROR_NA_RETURN(true); }
+};
+class AstNodePreSel VL_NOT_FINAL : public AstNodeExpr {
+    // Something that becomes an AstSel
+    // @astgen op1 := fromp : AstNode
+    // @astgen op2 := rhsp : AstNode
+    // @astgen op3 := thsp : Optional[AstNode]
+    // @astgen op4 := attrp : Optional[AstAttrOf]
+protected:
+    AstNodePreSel(VNType t, FileLine* fl, AstNode* fromp, AstNode* rhsp, AstNode* thsp)
+        : AstNodeExpr{t, fl} {
+        this->fromp(fromp);
+        this->rhsp(rhsp);
+        this->thsp(thsp);
+    }
+
+public:
+    ASTGEN_MEMBERS_AstNodePreSel;
+    // METHODS
+    bool same(const AstNode*) const override { return true; }
+
+    string emitVerilog() final override { V3ERROR_NA_RETURN(""); }
+    string emitC() final override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const final override { V3ERROR_NA_RETURN(true); }
+};
+class AstNodeQuadop VL_NOT_FINAL : public AstNodeExpr {
     // 4-ary expression
     // @astgen op1 := lhsp : AstNode
     // @astgen op2 := rhsp : AstNode
@@ -153,7 +255,7 @@ class AstNodeQuadop VL_NOT_FINAL : public AstNodeMath {
 protected:
     AstNodeQuadop(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* thsp,
                   AstNode* fhsp)
-        : AstNodeMath{t, fl} {
+        : AstNodeExpr{t, fl} {
         this->lhsp(lhsp);
         this->rhsp(rhsp);
         this->thsp(thsp);
@@ -178,11 +280,11 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode*) const override { return true; }
 };
-class AstNodeTermop VL_NOT_FINAL : public AstNodeMath {
+class AstNodeTermop VL_NOT_FINAL : public AstNodeExpr {
     // Terminal operator -- a operator with no "inputs"
 protected:
     AstNodeTermop(VNType t, FileLine* fl)
-        : AstNodeMath{t, fl} {}
+        : AstNodeExpr{t, fl} {}
 
 public:
     ASTGEN_MEMBERS_AstNodeTermop;
@@ -191,14 +293,14 @@ public:
     void iterateChildren(VNVisitor& v) {}
     void dump(std::ostream& str) const override;
 };
-class AstNodeTriop VL_NOT_FINAL : public AstNodeMath {
+class AstNodeTriop VL_NOT_FINAL : public AstNodeExpr {
     // Ternary expression
     // @astgen op1 := lhsp : AstNode
     // @astgen op2 := rhsp : AstNode
     // @astgen op3 := thsp : AstNode
 protected:
     AstNodeTriop(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* thsp)
-        : AstNodeMath{t, fl} {
+        : AstNodeExpr{t, fl} {
         this->lhsp(lhsp);
         this->rhsp(rhsp);
         this->thsp(thsp);
@@ -251,12 +353,12 @@ public:
     int instrCount() const override { return INSTR_COUNT_BRANCH; }
     virtual AstNode* cloneType(AstNode* condp, AstNode* thenp, AstNode* elsep) = 0;
 };
-class AstNodeUniop VL_NOT_FINAL : public AstNodeMath {
+class AstNodeUniop VL_NOT_FINAL : public AstNodeExpr {
     // Unary expression
     // @astgen op1 := lhsp : AstNode
 protected:
     AstNodeUniop(VNType t, FileLine* fl, AstNode* lhsp)
-        : AstNodeMath{t, fl} {
+        : AstNodeExpr{t, fl} {
         dtypeFrom(lhsp);
         this->lhsp(lhsp);
     }
@@ -289,9 +391,8 @@ public:
     int instrCount() const override { return INSTR_COUNT_DBL_TRIG; }
     bool doubleFlavor() const override { return true; }
 };
-class AstNodeVarRef VL_NOT_FINAL : public AstNodeMath {
+class AstNodeVarRef VL_NOT_FINAL : public AstNodeExpr {
     // An AstVarRef or AstVarXRef
-private:
     VAccess m_access;  // Left hand side assignment
     AstVar* m_varp;  // [AfterLink] Pointer to variable itself
     AstVarScope* m_varScopep = nullptr;  // Varscope for hierarchy
@@ -301,13 +402,13 @@ private:
 
 protected:
     AstNodeVarRef(VNType t, FileLine* fl, const string& name, const VAccess& access)
-        : AstNodeMath{t, fl}
+        : AstNodeExpr{t, fl}
         , m_access{access}
         , m_name{name} {
         varp(nullptr);
     }
     AstNodeVarRef(VNType t, FileLine* fl, const string& name, AstVar* varp, const VAccess& access)
-        : AstNodeMath{t, fl}
+        : AstNodeExpr{t, fl}
         , m_access{access}
         , m_name{name} {
         // May have varp==nullptr
@@ -317,7 +418,6 @@ protected:
 public:
     ASTGEN_MEMBERS_AstNodeVarRef;
     void dump(std::ostream& str) const override;
-    bool hasDType() const override { return true; }
     const char* broken() const override;
     int instrCount() const override { return widthInstrs(); }
     void cloneRelink() override;
@@ -344,10 +444,9 @@ public:
 
 // === Concrete node types =====================================================
 
-// === AstNodeMath ===
-class AstAddrOfCFunc final : public AstNodeMath {
+// === AstNodeExpr ===
+class AstAddrOfCFunc final : public AstNodeExpr {
     // Get address of CFunc
-private:
     AstCFunc* m_funcp;  // Pointer to function itself
 
 public:
@@ -366,22 +465,41 @@ public:
     bool cleanOut() const override { return true; }
     AstCFunc* funcp() const { return m_funcp; }
 };
-class AstCMath final : public AstNodeMath {
+class AstAttrOf final : public AstNodeExpr {
+    // Return a value of a attribute, for example a LSB or array LSB of a signal
+    // @astgen op1 := fromp : Optional[AstNode]
+    // @astgen op2 := dimp : Optional[AstNode]
+    VAttrType m_attrType;  // What sort of extraction
+public:
+    AstAttrOf(FileLine* fl, VAttrType attrtype, AstNode* fromp = nullptr, AstNode* dimp = nullptr)
+        : ASTGEN_SUPER_AttrOf(fl) {
+        this->fromp(fromp);
+        this->dimp(dimp);
+        m_attrType = attrtype;
+    }
+    ASTGEN_MEMBERS_AstAttrOf;
+    VAttrType attrType() const { return m_attrType; }
+    void dump(std::ostream& str = std::cout) const override;
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
+class AstCExpr final : public AstNodeExpr {
     // @astgen op1 := exprsp : List[AstNode] // Expressions to print
-private:
     const bool m_cleanOut;
     bool m_pure;  // Pure optimizable
 public:
-    // Emit C textual math function (like AstUCFunc)
-    AstCMath(FileLine* fl, AstNode* exprsp)
-        : ASTGEN_SUPER_CMath(fl)
+    // Emit C textual expr function (like AstUCFunc)
+    AstCExpr(FileLine* fl, AstNode* exprsp)
+        : ASTGEN_SUPER_CExpr(fl)
         , m_cleanOut{true}
         , m_pure{false} {
         addExprsp(exprsp);
         dtypeFrom(exprsp);
     }
-    inline AstCMath(FileLine* fl, const string& textStmt, int setwidth, bool cleanOut = true);
-    ASTGEN_MEMBERS_AstCMath;
+    inline AstCExpr(FileLine* fl, const string& textStmt, int setwidth, bool cleanOut = true);
+    ASTGEN_MEMBERS_AstCExpr;
     bool isGateOptimizable() const override { return m_pure; }
     bool isPredictOptimizable() const override { return m_pure; }
     bool cleanOut() const override { return m_cleanOut; }
@@ -391,7 +509,82 @@ public:
     bool pure() const { return m_pure; }
     void pure(bool flag) { m_pure = flag; }
 };
-class AstConsAssoc final : public AstNodeMath {
+class AstCMethodHard final : public AstNodeExpr {
+    // A reference to a "C" hardcoded member task (or function)
+    // PARENTS: stmt/expr
+    // @astgen op1 := fromp : AstNode // Subject of method call
+    // @astgen op2 := pinsp : List[AstNode] // Arguments
+    string m_name;  // Name of method
+    bool m_pure = false;  // Pure optimizable
+public:
+    AstCMethodHard(FileLine* fl, AstNode* fromp, VFlagChildDType, const string& name,
+                   AstNode* pinsp = nullptr)
+        : ASTGEN_SUPER_CMethodHard(fl)
+        , m_name{name} {
+        // TODO: this constructor is exactly the same as the other, bar the ignored tag argument
+        this->fromp(fromp);
+        this->addPinsp(pinsp);
+        dtypep(nullptr);  // V3Width will resolve
+    }
+    AstCMethodHard(FileLine* fl, AstNode* fromp, const string& name, AstNode* pinsp = nullptr)
+        : ASTGEN_SUPER_CMethodHard(fl)
+        , m_name{name} {
+        this->fromp(fromp);
+        this->addPinsp(pinsp);
+    }
+    ASTGEN_MEMBERS_AstCMethodHard;
+    string name() const override { return m_name; }  // * = Var name
+    void name(const string& name) override { m_name = name; }
+    bool same(const AstNode* samep) const override {
+        const AstCMethodHard* asamep = static_cast<const AstCMethodHard*>(samep);
+        return (m_name == asamep->m_name);
+    }
+    bool isPure() const override { return m_pure; }
+    void pure(bool flag) { m_pure = flag; }
+    int instrCount() const override;
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { return true; }
+};
+class AstCast final : public AstNodeExpr {
+    // Cast to appropriate data type
+    // @astgen op1 := fromp : AstNode
+    // @astgen op2 := childDTypep : Optional[AstNodeDType]
+public:
+    AstCast(FileLine* fl, AstNode* fromp, VFlagChildDType, AstNodeDType* dtp)
+        : ASTGEN_SUPER_Cast(fl) {
+        this->fromp(fromp);
+        this->childDTypep(dtp);
+        dtypeFrom(dtp);
+    }
+    AstCast(FileLine* fl, AstNode* fromp, AstNodeDType* dtp)
+        : ASTGEN_SUPER_Cast(fl) {
+        this->fromp(fromp);
+        dtypeFrom(dtp);
+    }
+    ASTGEN_MEMBERS_AstCast;
+    string emitVerilog() override { return "((%d)'(%l))"; }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+    AstNodeDType* getChildDTypep() const override { return childDTypep(); }
+    AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
+};
+class AstCastParse final : public AstNodeExpr {
+    // Cast to appropriate type, where we haven't determined yet what the data type is
+    // @astgen op1 := lhsp : AstNode
+    // @astgen op2 := dtp : AstNode
+public:
+    AstCastParse(FileLine* fl, AstNode* lhsp, AstNode* dtp)
+        : ASTGEN_SUPER_CastParse(fl) {
+        this->lhsp(lhsp);
+        this->dtp(dtp);
+    }
+    ASTGEN_MEMBERS_AstCastParse;
+    string emitVerilog() override { return "((%d)'(%l))"; }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
+class AstConsAssoc final : public AstNodeExpr {
     // Construct an assoc array and return object, '{}
     // @astgen op1 := defaultp : Optional[AstNode]
 public:
@@ -407,7 +600,7 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstConsDynArray final : public AstNodeMath {
+class AstConsDynArray final : public AstNodeExpr {
     // Construct a queue and return object, '{}. '{lhs}, '{lhs. rhs}
     // @astgen op1 := lhsp : Optional[AstNode]
     // @astgen op2 := rhsp : Optional[AstNode]
@@ -425,7 +618,7 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstConsQueue final : public AstNodeMath {
+class AstConsQueue final : public AstNodeExpr {
     // Construct a queue and return object, '{}. '{lhs}, '{lhs. rhs}
     // @astgen op1 := lhsp : Optional[AstNode]
     // @astgen op2 := rhsp : Optional[AstNode]
@@ -443,7 +636,7 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstConsWildcard final : public AstNodeMath {
+class AstConsWildcard final : public AstNodeExpr {
     // Construct a wildcard assoc array and return object, '{}
     // @astgen op1 := defaultp : Optional[AstNode]
 public:
@@ -459,9 +652,8 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstConst final : public AstNodeMath {
+class AstConst final : public AstNodeExpr {
     // A constant
-private:
     V3Number m_num;  // Constant value
     void initWithNumber() {
         if (m_num.isDouble()) {
@@ -593,7 +785,33 @@ public:
     // May return nullptr on parse failure.
     static AstConst* parseParamLiteral(FileLine* fl, const string& literal);
 };
-class AstEmptyQueue final : public AstNodeMath {
+class AstDot final : public AstNodeExpr {
+    // A dot separating paths in an AstVarXRef, AstFuncRef or AstTaskRef
+    // These are eliminated in the link stage
+    // @astgen op1 := lhsp : AstNode
+    // @astgen op2 := rhsp : AstNode
+    const bool m_colon;  // Is a "::" instead of a "." (lhs must be package/class)
+public:
+    AstDot(FileLine* fl, bool colon, AstNode* lhsp, AstNode* rhsp)
+        : ASTGEN_SUPER_Dot(fl)
+        , m_colon{colon} {
+        this->lhsp(lhsp);
+        this->rhsp(rhsp);
+    }
+    ASTGEN_MEMBERS_AstDot;
+    // For parser, make only if non-null package
+    static AstNodeExpr* newIfPkg(FileLine* fl, AstNode* packageOrClassp, AstNodeExpr* rhsp) {
+        if (!packageOrClassp) return rhsp;
+        return new AstDot(fl, true, packageOrClassp, rhsp);
+    }
+    void dump(std::ostream& str) const override;
+    bool colon() const { return m_colon; }
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
+class AstEmptyQueue final : public AstNodeExpr {
 public:
     explicit AstEmptyQueue(FileLine* fl)
         : ASTGEN_SUPER_EmptyQueue(fl) {}
@@ -603,8 +821,7 @@ public:
     bool same(const AstNode* /*samep*/) const override { return true; }
     bool cleanOut() const override { return true; }
 };
-class AstEnumItemRef final : public AstNodeMath {
-private:
+class AstEnumItemRef final : public AstNodeExpr {
     AstEnumItem* m_itemp;  // [AfterLink] Pointer to item
     AstNodeModule* m_classOrPackagep;  // Package hierarchy
 public:
@@ -633,8 +850,8 @@ public:
     AstNodeModule* classOrPackagep() const { return m_classOrPackagep; }
     void classOrPackagep(AstNodeModule* nodep) { m_classOrPackagep = nodep; }
 };
-class AstExprStmt final : public AstNodeMath {
-    // Perform a statement, often assignment inside an expression/math node,
+class AstExprStmt final : public AstNodeExpr {
+    // Perform a statement, often assignment inside an expression node,
     // the parent gets passed the 'resultp()'.
     // resultp is evaluated AFTER the statement(s).
     // @astgen op1 := stmtsp : List[AstNode]
@@ -653,7 +870,7 @@ public:
     bool cleanOut() const override { return false; }
     bool same(const AstNode*) const override { return true; }
 };
-class AstFError final : public AstNodeMath {
+class AstFError final : public AstNodeExpr {
     // @astgen op1 := filep : AstNode
     // @astgen op2 := strp : AstNode
 public:
@@ -666,13 +883,11 @@ public:
     string emitVerilog() override { return "%f$ferror(%l, %r)"; }
     string emitC() override { V3ERROR_NA_RETURN(""); }
     bool cleanOut() const override { return true; }
-    virtual bool cleanLhs() const { return true; }
-    virtual bool sizeMattersLhs() const { return false; }
     int instrCount() const override { return widthInstrs() * 64; }
     bool isPure() const override { return false; }  // SPECIAL: $display has 'visual' ordering
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstFRead final : public AstNodeMath {
+class AstFRead final : public AstNodeExpr {
     // @astgen op1 := memp : AstNode // VarRef for result
     // @astgen op2 := filep : AstNode // file (must be a VarRef)
     // @astgen op3 := startp : Optional[AstNode] // Offset
@@ -696,8 +911,7 @@ public:
     bool cleanOut() const override { return false; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstFRewind final : public AstNodeMath {
-    // Parents: stmtlist
+class AstFRewind final : public AstNodeExpr {
     // @astgen op1 := filep : Optional[AstNode]
 public:
     AstFRewind(FileLine* fl, AstNode* filep)
@@ -716,10 +930,9 @@ public:
     bool cleanOut() const override { return false; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstFScanF final : public AstNodeMath {
+class AstFScanF final : public AstNodeExpr {
     // @astgen op1 := exprsp : List[AstNode] // VarRefs for results
     // @astgen op2 := filep : Optional[AstNode] // file (must be a VarRef)
-private:
     string m_text;
 
 public:
@@ -745,7 +958,7 @@ public:
     string text() const { return m_text; }  // * = Text to display
     void text(const string& text) { m_text = text; }
 };
-class AstFSeek final : public AstNodeMath {
+class AstFSeek final : public AstNodeExpr {
     // @astgen op1 := filep : AstNode // file (must be a VarRef)
     // @astgen op2 := offset : Optional[AstNode]
     // @astgen op3 := operation : Optional[AstNode]
@@ -767,8 +980,7 @@ public:
     bool cleanOut() const override { return false; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstFTell final : public AstNodeMath {
-    // Parents: stmtlist
+class AstFTell final : public AstNodeExpr {
     // @astgen op1 := filep : AstNode // file (must be a VarRef)
 public:
     AstFTell(FileLine* fl, AstNode* filep)
@@ -787,7 +999,7 @@ public:
     bool cleanOut() const override { return false; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstFell final : public AstNodeMath {
+class AstFell final : public AstNodeExpr {
     // Verilog $fell
     // @astgen op1 := exprp : AstNode
     // @astgen op2 := sentreep : Optional[AstSenTree]
@@ -804,7 +1016,7 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstGatePin final : public AstNodeMath {
+class AstGatePin final : public AstNodeExpr {
     // Possibly expand a gate primitive input pin value to match the range of the gate primitive
     // @astgen op1 := exprp : AstNode // Pin expression
     // @astgen op2 := rangep : AstRange // Range of pin
@@ -819,7 +1031,7 @@ public:
     string emitC() override { V3ERROR_NA_RETURN(""); }
     bool cleanOut() const override { return true; }
 };
-class AstImplication final : public AstNodeMath {
+class AstImplication final : public AstNodeExpr {
     // Verilog |-> |=>
     // @astgen op1 := lhsp : AstNode
     // @astgen op2 := rhsp : AstNode
@@ -838,7 +1050,7 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstInside final : public AstNodeMath {
+class AstInside final : public AstNodeExpr {
     // @astgen op1 := exprp : AstNode
     // @astgen op2 := itemsp : List[AstNode]
 public:
@@ -853,7 +1065,7 @@ public:
     string emitC() override { V3ERROR_NA_RETURN(""); }
     bool cleanOut() const override { return false; }  // NA
 };
-class AstInsideRange final : public AstNodeMath {
+class AstInsideRange final : public AstNodeExpr {
     // @astgen op1 := lhsp : AstNode
     // @astgen op2 := rhsp : AstNode
 public:
@@ -869,11 +1081,10 @@ public:
     // Create AstAnd(AstGte(...), AstLte(...))
     AstNode* newAndFromInside(AstNode* exprp, AstNode* lhsp, AstNode* rhsp);
 };
-class AstLambdaArgRef final : public AstNodeMath {
+class AstLambdaArgRef final : public AstNodeExpr {
     // Lambda argument usage
     // These are not AstVarRefs because we need to be able to delete/clone lambdas during
     // optimizations and AstVar's are painful to remove.
-private:
     string m_name;  // Name of variable
     bool m_index;  // Index, not value
 
@@ -887,16 +1098,13 @@ public:
     string emitVerilog() override { return name(); }
     string emitC() override { V3ERROR_NA_RETURN(""); }
     bool cleanOut() const override { return true; }
-    bool hasDType() const override { return true; }
     int instrCount() const override { return widthInstrs(); }
     string name() const override { return m_name; }  // * = Var name
     void name(const string& name) override { m_name = name; }
     bool index() const { return m_index; }
 };
-class AstMemberSel final : public AstNodeMath {
-    // Parents: math|stmt
+class AstMemberSel final : public AstNodeExpr {
     // @astgen op1 := fromp : AstNode
-private:
     // Don't need the class we are extracting from, as the "fromp()"'s datatype can get us to it
     string m_name;
     AstVar* m_varp = nullptr;  // Post link, variable within class that is target of selection
@@ -926,9 +1134,8 @@ public:
     AstVar* varp() const { return m_varp; }
     void varp(AstVar* nodep) { m_varp = nodep; }
 };
-class AstNewCopy final : public AstNodeMath {
+class AstNewCopy final : public AstNodeExpr {
     // New as shallow copy
-    // Parents: math|stmt
     // @astgen op1 := rhsp : AstNode
 public:
     AstNewCopy(FileLine* fl, AstNode* rhsp)
@@ -943,9 +1150,8 @@ public:
     bool same(const AstNode* /*samep*/) const override { return true; }
     int instrCount() const override { return widthInstrs(); }
 };
-class AstNewDynamic final : public AstNodeMath {
+class AstNewDynamic final : public AstNodeExpr {
     // New for dynamic array
-    // Parents: math|stmt
     // @astgen op1 := sizep : AstNode
     // @astgen op2 := rhsp : Optional[AstNode]
 public:
@@ -962,7 +1168,41 @@ public:
     bool same(const AstNode* /*samep*/) const override { return true; }
     int instrCount() const override { return widthInstrs(); }
 };
-class AstPast final : public AstNodeMath {
+class AstParseRef final : public AstNodeExpr {
+    // A reference to a variable, function or task
+    // We don't know which at parse time due to bison constraints
+    // The link stages will replace this with AstVarRef, or AstTaskRef, etc.
+    // @astgen op1 := lhsp : Optional[AstNode]
+    // @astgen op2 := ftaskrefp : Optional[AstNodeFTaskRef]
+
+    VParseRefExp m_expect;  // Type we think it should resolve to
+    string m_name;
+
+public:
+    AstParseRef(FileLine* fl, VParseRefExp expect, const string& name, AstNode* lhsp = nullptr,
+                AstNodeFTaskRef* ftaskrefp = nullptr)
+        : ASTGEN_SUPER_ParseRef(fl)
+        , m_expect{expect}
+        , m_name{name} {
+        this->lhsp(lhsp);
+        this->ftaskrefp(ftaskrefp);
+    }
+    ASTGEN_MEMBERS_AstParseRef;
+    void dump(std::ostream& str) const override;
+    string name() const override { return m_name; }  // * = Var name
+    bool same(const AstNode* samep) const override {
+        const AstParseRef* const asamep = static_cast<const AstParseRef*>(samep);
+        return (expect() == asamep->expect() && m_name == asamep->m_name);
+    }
+    void name(const string& name) override { m_name = name; }
+    VParseRefExp expect() const { return m_expect; }
+    void expect(VParseRefExp exp) { m_expect = exp; }
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
+class AstPast final : public AstNodeExpr {
     // Verilog $past
     // @astgen op1 := exprp : AstNode
     // @astgen op2 := ticksp : Optional[AstNode]
@@ -981,7 +1221,7 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstPatMember final : public AstNodeMath {
+class AstPatMember final : public AstNodeExpr {
     // Verilog '{a} or '{a{b}}
     // Parents: AstPattern
     // Children: expression, AstPattern, replication count
@@ -989,7 +1229,6 @@ class AstPatMember final : public AstNodeMath {
     // @astgen op1 := lhssp : List[AstNode]
     // @astgen op2 := keyp : Optional[AstNode]
     // @astgen op3 := repp : Optional[AstNode]  // replication count, or nullptr for count 1
-private:
     bool m_default = false;
 
 public:
@@ -1009,7 +1248,7 @@ public:
     bool isDefault() const { return m_default; }
     void isDefault(bool flag) { m_default = flag; }
 };
-class AstPattern final : public AstNodeMath {
+class AstPattern final : public AstNodeExpr {
     // Verilog '{a,b,c,d...}
     // Parents: AstNodeAssign, AstPattern, ...
     // Children: expression, AstPattern, AstPatReplicate
@@ -1027,13 +1266,12 @@ public:
     bool cleanOut() const override { V3ERROR_NA_RETURN(""); }
     int instrCount() const override { return widthInstrs(); }
     AstNodeDType* getChildDTypep() const override { return childDTypep(); }
-    virtual AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
+    AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
 };
-class AstRand final : public AstNodeMath {
+class AstRand final : public AstNodeExpr {
     // $random/$random(seed) or $urandom/$urandom(seed)
     // Return a random number, based upon width()
     // @astgen op1 := seedp : Optional[AstNode]
-private:
     const bool m_urandom = false;  // $urandom vs $random
     const bool m_reset = false;  // Random reset, versus always random
 public:
@@ -1072,7 +1310,7 @@ public:
     bool reset() const { return m_reset; }
     bool urandom() const { return m_urandom; }
 };
-class AstRose final : public AstNodeMath {
+class AstRose final : public AstNodeExpr {
     // Verilog $rose
     // @astgen op1 := exprp : AstNode
     // @astgen op2 := sentreep : Optional[AstSenTree]
@@ -1089,10 +1327,64 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstSScanF final : public AstNodeMath {
+class AstSFormatF final : public AstNodeExpr {
+    // Convert format to string, generally under an AstDisplay or AstSFormat
+    // Also used as "real" function for /*verilator sformat*/ functions
+    // @astgen op1 := exprsp : List[AstNode]
+    // @astgen op2 := scopeNamep : Optional[AstScopeName]
+    string m_text;
+    const bool m_hidden;  // Under display, etc
+    bool m_hasFormat;  // Has format code
+    const char m_missingArgChar;  // Format code when argument without format, 'h'/'o'/'b'
+    VTimescale m_timeunit;  // Parent module time unit
+public:
+    class NoFormat {};
+    AstSFormatF(FileLine* fl, const string& text, bool hidden, AstNode* exprsp,
+                char missingArgChar = 'd')
+        : ASTGEN_SUPER_SFormatF(fl)
+        , m_text{text}
+        , m_hidden{hidden}
+        , m_hasFormat{true}
+        , m_missingArgChar{missingArgChar} {
+        dtypeSetString();
+        addExprsp(exprsp);
+    }
+    AstSFormatF(FileLine* fl, NoFormat, AstNode* exprsp, char missingArgChar = 'd',
+                bool hidden = true)
+        : ASTGEN_SUPER_SFormatF(fl)
+        , m_text{""}
+        , m_hidden{hidden}
+        , m_hasFormat{false}
+        , m_missingArgChar{missingArgChar} {
+        dtypeSetString();
+        addExprsp(exprsp);
+    }
+    ASTGEN_MEMBERS_AstSFormatF;
+    string name() const override { return m_text; }
+    int instrCount() const override { return INSTR_COUNT_PLI; }
+    bool same(const AstNode* samep) const override {
+        return text() == static_cast<const AstSFormatF*>(samep)->text();
+    }
+    string verilogKwd() const override { return "$sformatf"; }
+    string text() const { return m_text; }  // * = Text to display
+    void text(const string& text) { m_text = text; }
+    bool formatScopeTracking() const {  // Track scopeNamep();  Ok if false positive
+        return (name().find("%m") != string::npos || name().find("%M") != string::npos);
+    }
+    bool hidden() const { return m_hidden; }
+    void hasFormat(bool flag) { m_hasFormat = flag; }
+    bool hasFormat() const { return m_hasFormat; }
+    char missingArgChar() const { return m_missingArgChar; }
+    void timeunit(const VTimescale& flag) { m_timeunit = flag; }
+    VTimescale timeunit() const { return m_timeunit; }
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
+class AstSScanF final : public AstNodeExpr {
     // @astgen op1 := exprsp : List[AstNode] // VarRefs for results
     // @astgen op2 := fromp : AstNode
-private:
     string m_text;
 
 public:
@@ -1118,7 +1410,7 @@ public:
     string text() const { return m_text; }  // * = Text to display
     void text(const string& text) { m_text = text; }
 };
-class AstSampled final : public AstNodeMath {
+class AstSampled final : public AstNodeExpr {
     // Verilog $sampled
     // @astgen op1 := exprp : AstNode
 public:
@@ -1134,12 +1426,11 @@ public:
     int instrCount() const override { return 0; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstScopeName final : public AstNodeMath {
+class AstScopeName final : public AstNodeExpr {
     // For display %m and DPI context imports
     // Parents:  DISPLAY
     // @astgen op1 := scopeAttrp : List[AstText]
     // @astgen op2 := scopeEntrp : List[AstText]
-private:
     bool m_dpiExport = false;  // Is for dpiExport
     const bool m_forFormat = false;  // Is for a format %m
     string scopeNameFormatter(AstText* scopeTextp) const;
@@ -1177,9 +1468,8 @@ public:
     void dpiExport(bool flag) { m_dpiExport = flag; }
     bool forFormat() const { return m_forFormat; }
 };
-class AstSetAssoc final : public AstNodeMath {
+class AstSetAssoc final : public AstNodeExpr {
     // Set an assoc array element and return object, '{}
-    // Parents: math
     // @astgen op1 := lhsp : AstNode
     // @astgen op2 := keyp : Optional[AstNode]
     // @astgen op3 := valuep : AstNode
@@ -1198,9 +1488,8 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstSetWildcard final : public AstNodeMath {
+class AstSetWildcard final : public AstNodeExpr {
     // Set a wildcard assoc array element and return object, '{}
-    // Parents: math
     // @astgen op1 := lhsp : AstNode
     // @astgen op2 := keyp : Optional[AstNode]
     // @astgen op3 := valuep : AstNode
@@ -1219,7 +1508,7 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstStable final : public AstNodeMath {
+class AstStable final : public AstNodeExpr {
     // Verilog $stable
     // @astgen op1 := exprp : AstNode
     // @astgen op2 := sentreep : Optional[AstSenTree]
@@ -1236,7 +1525,26 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstSystemF final : public AstNodeMath {
+class AstSysIgnore final : public AstNodeExpr {
+    // @astgen op1 := exprsp : List[AstNode] // Expressions to output (???)
+public:
+    AstSysIgnore(FileLine* fl, AstNode* exprsp)
+        : ASTGEN_SUPER_SysIgnore(fl) {
+        this->addExprsp(exprsp);
+    }
+    ASTGEN_MEMBERS_AstSysIgnore;
+    string verilogKwd() const override { return "$ignored"; }
+    bool isGateOptimizable() const override { return false; }  // Though deleted before opt
+    bool isPredictOptimizable() const override { return false; }  // Though deleted before opt
+    bool isPure() const override { return false; }  // Though deleted before opt
+    bool isOutputter() const override { return true; }  // Though deleted before opt
+    int instrCount() const override { return INSTR_COUNT_PLI; }
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
+class AstSystemF final : public AstNodeExpr {
     // $system used as function
     // @astgen op1 := lhsp : AstNode
 public:
@@ -1256,7 +1564,7 @@ public:
     bool cleanOut() const override { return true; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstTestPlusArgs final : public AstNodeMath {
+class AstTestPlusArgs final : public AstNodeExpr {
     // Search expression. If nullptr then this is a $test$plusargs instead of $value$plusargs.
     // @astgen op1 := searchp : Optional[AstNode]
 public:
@@ -1273,7 +1581,7 @@ public:
     bool cleanOut() const override { return true; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstThisRef final : public AstNodeMath {
+class AstThisRef final : public AstNodeExpr {
     // Reference to 'this'.
     // @astgen op1 := childDTypep : Optional[AstClassRefDType] // dtype of the node
 public:
@@ -1287,9 +1595,9 @@ public:
     bool same(const AstNode* /*samep*/) const override { return true; }
     bool cleanOut() const override { return true; }
     AstNodeDType* getChildDTypep() const override { return childDTypep(); }
-    virtual AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
+    AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
 };
-class AstUCFunc final : public AstNodeMath {
+class AstUCFunc final : public AstNodeExpr {
     // User's $c function
     // Perhaps this should be an AstNodeListop; but there's only one list math right now
     // @astgen op1 := exprsp : List[AstNode] // Expressions to print
@@ -1310,7 +1618,7 @@ public:
     int instrCount() const override { return INSTR_COUNT_PLI; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstUnbounded final : public AstNodeMath {
+class AstUnbounded final : public AstNodeExpr {
     // A $ in the parser, used for unbounded and queues
     // Due to where is used, treated as Signed32
 public:
@@ -1323,7 +1631,26 @@ public:
     string emitC() override { V3ERROR_NA_RETURN(""); }
     bool cleanOut() const override { return true; }
 };
-class AstValuePlusArgs final : public AstNodeMath {
+class AstUnlinkedRef final : public AstNodeExpr {
+    // As-of-yet unlinkable Ref
+    // @astgen op1 := refp : AstNode
+    // @astgen op2 := cellrefp : AstNode
+
+    string m_name;  // Var name // TODO: There is no way to access this, fix or remove
+public:
+    AstUnlinkedRef(FileLine* fl, AstNode* refp, const string& name, AstNode* cellrefp)
+        : ASTGEN_SUPER_UnlinkedRef(fl)
+        , m_name{name} {
+        this->refp(refp);
+        this->cellrefp(cellrefp);
+    }
+    ASTGEN_MEMBERS_AstUnlinkedRef;
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
+class AstValuePlusArgs final : public AstNodeExpr {
     // Search expression. If nullptr then this is a $test$plusargs instead of $value$plusargs.
     // @astgen op1 := searchp : Optional[AstNode]
     // @astgen op2 := outp : AstNode // VarRef for result
@@ -1343,6 +1670,26 @@ public:
     bool cleanOut() const override { return true; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
+class AstWithParse final : public AstNodeExpr {
+    // In early parse, FUNC(index) WITH equation-using-index
+    // Replaced with AstWith
+    // Parents: expr|stmt
+    // Children: funcref, expr
+    // @astgen op1 := funcrefp : AstNode
+    // @astgen op2 := exprp : Optional[AstNode]
+public:
+    AstWithParse(FileLine* fl, AstNode* funcrefp, AstNode* exprp)
+        : ASTGEN_SUPER_WithParse(fl) {
+        this->funcrefp(funcrefp);
+        this->exprp(exprp);
+    }
+    ASTGEN_MEMBERS_AstWithParse;
+    bool same(const AstNode* /*samep*/) const override { return true; }
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
 
 // === AstNodeBiop ===
 class AstBufIf1 final : public AstNodeBiop {
@@ -1373,8 +1720,6 @@ public:
 class AstCastDynamic final : public AstNodeBiop {
     // Verilog $cast used as a function
     // Task usage of $cast is converted during parse to assert($cast(...))
-    // Parents: MATH
-    // Children: MATH
     // lhsp() is value (we are converting FROM) to match AstCCast etc, this
     // is opposite of $cast's order, because the first access is to the
     // value reading from.  Suggest use fromp()/top() instead of lhsp/rhsp().
@@ -1402,7 +1747,6 @@ public:
 };
 class AstCompareNN final : public AstNodeBiop {
     // Verilog str.compare() and str.icompare()
-private:
     const bool m_ignoreCase;  // True for str.icompare()
 public:
     AstCompareNN(FileLine* fl, AstNode* lhsp, AstNode* rhsp, bool ignoreCase)
@@ -2917,9 +3261,6 @@ public:
 
 // === AstNodeSel ===
 class AstArraySel final : public AstNodeSel {
-    // Parents: math|stmt
-    // Children: varref|arraysel, math
-private:
     void init(AstNode* fromp) {
         if (fromp && VN_IS(fromp->dtypep()->skipRefp(), NodeArrayDType)) {
             // Strip off array to find what array references
@@ -2959,9 +3300,6 @@ public:
     static AstNode* baseFromp(AstNode* nodep, bool overMembers);
 };
 class AstAssocSel final : public AstNodeSel {
-    // Parents: math|stmt
-    // Children: varref|arraysel, math
-private:
     void init(AstNode* fromp) {
         if (fromp && VN_IS(fromp->dtypep()->skipRefp(), AssocArrayDType)) {
             // Strip off array to find what array references
@@ -2994,9 +3332,6 @@ public:
     int instrCount() const override { return widthInstrs(); }
 };
 class AstWildcardSel final : public AstNodeSel {
-    // Parents: math|stmt
-    // Children: varref|arraysel, math
-private:
     void init(AstNode* fromp) {
         if (fromp && VN_IS(fromp->dtypep()->skipRefp(), WildcardArrayDType)) {
             // Strip off array to find what array references
@@ -3128,6 +3463,144 @@ public:
     string emitC() override { return "hypot(%li,%ri)"; }
 };
 
+// === AstNodeCCall ===
+class AstCCall final : public AstNodeCCall {
+    // C++ function call
+    string m_selfPointer;  // Output code object pointer (e.g.: 'this')
+
+public:
+    AstCCall(FileLine* fl, AstCFunc* funcp, AstNode* argsp = nullptr)
+        : ASTGEN_SUPER_CCall(fl, funcp, argsp) {}
+    ASTGEN_MEMBERS_AstCCall;
+
+    string selfPointer() const { return m_selfPointer; }
+    void selfPointer(const string& value) { m_selfPointer = value; }
+    string selfPointerProtect(bool useSelfForThis) const;
+};
+class AstCMethodCall final : public AstNodeCCall {
+    // C++ method call
+    // @astgen op1 := fromp : AstNode
+public:
+    AstCMethodCall(FileLine* fl, AstNode* fromp, AstCFunc* funcp, AstNode* argsp = nullptr)
+        : ASTGEN_SUPER_CMethodCall(fl, funcp, argsp) {
+        this->fromp(fromp);
+    }
+    ASTGEN_MEMBERS_AstCMethodCall;
+    const char* broken() const override {
+        BROKEN_BASE_RTN(AstNodeCCall::broken());
+        BROKEN_RTN(!fromp());
+        return nullptr;
+    }
+};
+class AstCNew final : public AstNodeCCall {
+    // C++ new() call
+public:
+    AstCNew(FileLine* fl, AstCFunc* funcp, AstNode* argsp = nullptr)
+        : ASTGEN_SUPER_CNew(fl, funcp, argsp) {}
+    ASTGEN_MEMBERS_AstCNew;
+};
+
+// === AstNodeFTaskRef ===
+class AstFuncRef final : public AstNodeFTaskRef {
+    // A reference to a function
+public:
+    AstFuncRef(FileLine* fl, AstParseRef* namep, AstNode* pinsp)
+        : ASTGEN_SUPER_FuncRef(fl, (AstNode*)namep, pinsp) {}
+    AstFuncRef(FileLine* fl, const string& name, AstNode* pinsp)
+        : ASTGEN_SUPER_FuncRef(fl, name, pinsp) {}
+    ASTGEN_MEMBERS_AstFuncRef;
+};
+class AstMethodCall final : public AstNodeFTaskRef {
+    // A reference to a member task (or function)
+    // Don't need the class we are extracting from, as the "fromp()"'s datatype can get us to it
+    // @astgen op2 := fromp : AstNode
+    //
+public:
+    AstMethodCall(FileLine* fl, AstNode* fromp, VFlagChildDType, const string& name,
+                  AstNode* pinsp)
+        : ASTGEN_SUPER_MethodCall(fl, name, pinsp) {
+        this->fromp(fromp);
+        dtypep(nullptr);  // V3Width will resolve
+    }
+    AstMethodCall(FileLine* fl, AstNode* fromp, const string& name, AstNode* pinsp)
+        : ASTGEN_SUPER_MethodCall(fl, name, pinsp) {
+        this->fromp(fromp);
+    }
+    ASTGEN_MEMBERS_AstMethodCall;
+    const char* broken() const override {
+        BROKEN_BASE_RTN(AstNodeFTaskRef::broken());
+        BROKEN_RTN(!fromp());
+        return nullptr;
+    }
+    void dump(std::ostream& str) const override;
+};
+class AstNew final : public AstNodeFTaskRef {
+    // New as constructor
+    // Don't need the class we are extracting from, as the "fromp()"'s datatype can get us to it
+public:
+    AstNew(FileLine* fl, AstNode* pinsp)
+        : ASTGEN_SUPER_New(fl, "new", pinsp) {}
+    ASTGEN_MEMBERS_AstNew;
+    bool same(const AstNode* /*samep*/) const override { return true; }
+    int instrCount() const override { return widthInstrs(); }
+};
+class AstTaskRef final : public AstNodeFTaskRef {
+    // A reference to a task
+public:
+    AstTaskRef(FileLine* fl, AstParseRef* namep, AstNode* pinsp)
+        : ASTGEN_SUPER_TaskRef(fl, (AstNode*)namep, pinsp) {
+        dtypeSetVoid();
+    }
+    AstTaskRef(FileLine* fl, const string& name, AstNode* pinsp)
+        : ASTGEN_SUPER_TaskRef(fl, name, pinsp) {
+        dtypeSetVoid();
+    }
+    ASTGEN_MEMBERS_AstTaskRef;
+};
+
+// === AstNodePreSel ===
+class AstSelBit final : public AstNodePreSel {
+    // Single bit range extraction, perhaps with non-constant selection or array selection
+    // Gets replaced during link with AstArraySel or AstSel
+public:
+    AstSelBit(FileLine* fl, AstNode* fromp, AstNode* bitp)
+        : ASTGEN_SUPER_SelBit(fl, fromp, bitp, nullptr) {
+        UASSERT_OBJ(!v3Global.assertDTypesResolved(), this,
+                    "not coded to create after dtypes resolved");
+    }
+    ASTGEN_MEMBERS_AstSelBit;
+    AstNode* bitp() const { return rhsp(); }
+};
+class AstSelExtract final : public AstNodePreSel {
+    // Range extraction, gets replaced with AstSel
+public:
+    AstSelExtract(FileLine* fl, AstNode* fromp, AstNode* msbp, AstNode* lsbp)
+        : ASTGEN_SUPER_SelExtract(fl, fromp, msbp, lsbp) {}
+    ASTGEN_MEMBERS_AstSelExtract;
+    AstNode* leftp() const { return rhsp(); }
+    AstNode* rightp() const { return thsp(); }
+};
+class AstSelMinus final : public AstNodePreSel {
+    // -: range extraction, perhaps with non-constant selection
+    // Gets replaced during link with AstSel
+public:
+    AstSelMinus(FileLine* fl, AstNode* fromp, AstNode* bitp, AstNode* widthp)
+        : ASTGEN_SUPER_SelMinus(fl, fromp, bitp, widthp) {}
+    ASTGEN_MEMBERS_AstSelMinus;
+    AstNode* bitp() const { return rhsp(); }
+    AstNode* widthp() const { return thsp(); }
+};
+class AstSelPlus final : public AstNodePreSel {
+    // +: range extraction, perhaps with non-constant selection
+    // Gets replaced during link with AstSel
+public:
+    AstSelPlus(FileLine* fl, AstNode* fromp, AstNode* bitp, AstNode* widthp)
+        : ASTGEN_SUPER_SelPlus(fl, fromp, bitp, widthp) {}
+    ASTGEN_MEMBERS_AstSelPlus;
+    AstNode* bitp() const { return rhsp(); }
+    AstNode* widthp() const { return thsp(); }
+};
+
 // === AstNodeQuadop ===
 class AstCountBits final : public AstNodeQuadop {
     // Number of bits set in vector
@@ -3203,7 +3676,6 @@ public:
 // === AstNodeTriop ===
 class AstPostAdd final : public AstNodeTriop {
     // Post-increment/add
-    // Parents:  MATH
     // Children: lhsp: AstConst (1) as currently support only ++ not +=
     // Children: rhsp: tree with AstVarRef that is value to read before operation
     // Children: thsp: tree with AstVarRef LValue that is stored after operation
@@ -3228,7 +3700,6 @@ public:
 };
 class AstPostSub final : public AstNodeTriop {
     // Post-decrement/subtract
-    // Parents:  MATH
     // Children: lhsp: AstConst (1) as currently support only -- not -=
     // Children: rhsp: tree with AstVarRef that is value to read before operation
     // Children: thsp: tree with AstVarRef LValue that is stored after operation
@@ -3253,7 +3724,6 @@ public:
 };
 class AstPreAdd final : public AstNodeTriop {
     // Pre-increment/add
-    // Parents:  MATH
     // Children: lhsp: AstConst (1) as currently support only ++ not +=
     // Children: rhsp: tree with AstVarRef that is value to read before operation
     // Children: thsp: tree with AstVarRef LValue that is stored after operation
@@ -3278,7 +3748,6 @@ public:
 };
 class AstPreSub final : public AstNodeTriop {
     // Pre-decrement/subtract
-    // Parents:  MATH
     // Children: lhsp: AstConst (1) as currently support only -- not -=
     // Children: rhsp: tree with AstVarRef that is value to read before operation
     // Children: thsp: tree with AstVarRef LValue that is stored after operation
@@ -3327,12 +3796,9 @@ public:
 };
 class AstSel final : public AstNodeTriop {
     // Multiple bit range extraction
-    // Parents: math|stmt
-    // Children: varref|arraysel, math, constant math
     // @astgen alias op1 := fromp
     // @astgen alias op2 := lsbp
     // @astgen alias op3 := widthp
-private:
     VNumRange m_declRange;  // Range of the 'from' array if isRanged() is set, else invalid
     int m_declElWidth;  // If a packed array, the number of bits per element
 public:
@@ -3380,9 +3846,7 @@ public:
 };
 class AstSliceSel final : public AstNodeTriop {
     // Multiple array element extraction
-    // Parents: math|stmt
     // @astgen alias op1 := fromp
-private:
     VNumRange m_declRange;  // Range of the 'from' array if isRanged() is set, else invalid
 public:
     AstSliceSel(FileLine* fl, AstNode* fromp, const VNumRange& declRange)
@@ -3438,9 +3902,7 @@ public:
 
 // === AstNodeCond ===
 class AstCond final : public AstNodeCond {
-    // Conditional ?: statement
-    // Parents:  MATH
-    // Children: MATH
+    // Conditional ?: expressoin
 public:
     AstCond(FileLine* fl, AstNode* condp, AstNode* thenp, AstNode* elsep)
         : ASTGEN_SUPER_Cond(fl, condp, thenp, elsep) {}
@@ -3450,9 +3912,7 @@ public:
     }
 };
 class AstCondBound final : public AstNodeCond {
-    // Conditional ?: statement, specially made for safety checking of array bounds
-    // Parents:  MATH
-    // Children: MATH
+    // Conditional ?: expression, specially made for safety checking of array bounds
 public:
     AstCondBound(FileLine* fl, AstNode* condp, AstNode* thenp, AstNode* elsep)
         : ASTGEN_SUPER_CondBound(fl, condp, thenp, elsep) {}
@@ -3519,9 +3979,30 @@ public:
     bool sizeMattersLhs() const override { return false; }  // Eliminated before matters
     int instrCount() const override { return INSTR_COUNT_DBL; }
 };
+class AstCAwait final : public AstNodeUniop {
+    // Emit C++'s co_await expression
+    // @astgen alias op1 := exprp
+    AstSenTree* m_sensesp;  // Sentree related to this await
+public:
+    AstCAwait(FileLine* fl, AstNode* exprp, AstSenTree* sensesp = nullptr)
+        : ASTGEN_SUPER_CAwait(fl, exprp)
+        , m_sensesp{sensesp} {}
+    ASTGEN_MEMBERS_AstCAwait;
+    bool isTimingControl() const override { return true; }
+    const char* broken() const override;
+    void cloneRelink() override;
+    void dump(std::ostream& str) const override;
+    AstSenTree* sensesp() const { return m_sensesp; }
+    void clearSensesp() { m_sensesp = nullptr; }
+    void numberOperate(V3Number& out, const V3Number& lhs) override { V3ERROR_NA; }
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { return true; }
+    bool cleanLhs() const override { return true; }
+    bool sizeMattersLhs() const override { return false; }
+};
 class AstCCast final : public AstNodeUniop {
     // Cast to C-based data type
-private:
     int m_size;
 
 public:
@@ -3817,7 +4298,6 @@ public:
 };
 class AstNullCheck final : public AstNodeUniop {
     // Return LHS after checking that LHS is non-null
-    // Children: VarRef or something returning pointer
 public:
     AstNullCheck(FileLine* fl, AstNode* lhsp)
         : ASTGEN_SUPER_NullCheck(fl, lhsp) {
@@ -4273,7 +4753,6 @@ public:
 class AstVarXRef final : public AstNodeVarRef {
     // A VarRef to something in another module before AstScope.
     // Includes pin on a cell, as part of a ASSIGN statement to connect I/Os until AstScope
-private:
     string m_dotted;  // Dotted part of scope the name()'ed reference is under or ""
     string m_inlinedDots;  // Dotted hierarchy flattened out
 public:
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index 7343024d4..cbafbfc8b 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -264,25 +264,6 @@ public:
     void unconnectedDrive(const VOptionBool flag) { m_unconnectedDrive = flag; }
     VOptionBool unconnectedDrive() const { return m_unconnectedDrive; }
 };
-class AstNodePreSel VL_NOT_FINAL : public AstNode {
-    // Something that becomes an AstSel
-    // @astgen op1 := fromp : AstNode
-    // @astgen op2 := rhsp : AstNode
-    // @astgen op3 := thsp : Optional[AstNode]
-    // @astgen op4 := attrp : Optional[AstAttrOf]
-protected:
-    AstNodePreSel(VNType t, FileLine* fl, AstNode* fromp, AstNode* rhsp, AstNode* thsp)
-        : AstNode{t, fl} {
-        this->fromp(fromp);
-        this->rhsp(rhsp);
-        this->thsp(thsp);
-    }
-
-public:
-    ASTGEN_MEMBERS_AstNodePreSel;
-    // METHODS
-    bool same(const AstNode*) const override { return true; }
-};
 class AstNodeProcedure VL_NOT_FINAL : public AstNode {
     // IEEE procedure: initial, final, always
     // @astgen op2 := stmtsp : List[AstNode] // Note: op1 is used in some sub-types only
@@ -312,18 +293,14 @@ public:
     void dump(std::ostream& str) const override;
 };
 class AstNodeStmt VL_NOT_FINAL : public AstNode {
-    // Statement -- anything that's directly under a function
-    bool m_statement;  // Really a statement (e.g. not a function with return)
+    // Procedural statement
 protected:
-    AstNodeStmt(VNType t, FileLine* fl, bool statement = true)
-        : AstNode{t, fl}
-        , m_statement{statement} {}
+    AstNodeStmt(VNType t, FileLine* fl)
+        : AstNode{t, fl} {}
 
 public:
     ASTGEN_MEMBERS_AstNodeStmt;
     // METHODS
-    bool isStatement() const { return m_statement; }  // Really a statement
-    void statement(bool flag) { m_statement = flag; }
     void addNextStmt(AstNode* newp,
                      AstNode* belowp) override;  // Stop statement searchback here
     void addBeforeStmt(AstNode* newp,
@@ -357,40 +334,6 @@ public:
     bool isTimingControl() const override { return timingControlp(); }
     virtual bool brokeLhsMustBeLvalue() const = 0;
 };
-class AstNodeCCall VL_NOT_FINAL : public AstNodeStmt {
-    // A call of a C++ function, perhaps a AstCFunc or perhaps globally named
-    // @astgen op2 := argsp : List[AstNode] // Note: op1 used by some sub-types only
-    //
-    // Functions are not statements, while tasks are. AstNodeStmt needs isStatement() to deal.
-    AstCFunc* m_funcp;
-    string m_argTypes;
-
-protected:
-    AstNodeCCall(VNType t, FileLine* fl, AstCFunc* funcp, AstNode* argsp = nullptr)
-        : AstNodeStmt{t, fl, true}
-        , m_funcp{funcp} {
-        addArgsp(argsp);
-    }
-
-public:
-    ASTGEN_MEMBERS_AstNodeCCall;
-    void dump(std::ostream& str = std::cout) const override;
-    void cloneRelink() override;
-    const char* broken() const override;
-    int instrCount() const override { return INSTR_COUNT_CALL; }
-    bool same(const AstNode* samep) const override {
-        const AstNodeCCall* const asamep = static_cast<const AstNodeCCall*>(samep);
-        return (funcp() == asamep->funcp() && argTypes() == asamep->argTypes());
-    }
-    bool isGateOptimizable() const override { return false; }
-    bool isPredictOptimizable() const override { return false; }
-    bool isPure() const override;
-    bool isOutputter() const override { return !isPure(); }
-    AstCFunc* funcp() const { return m_funcp; }
-    void funcp(AstCFunc* funcp) { m_funcp = funcp; }
-    void argTypes(const string& str) { m_argTypes = str; }
-    string argTypes() const { return m_argTypes; }
-};
 class AstNodeCase VL_NOT_FINAL : public AstNodeStmt {
     // @astgen op1 := exprp : AstNode // Condition (scurtinee) expression
     // @astgen op2 := itemsp : List[AstCaseItem]
@@ -431,52 +374,6 @@ public:
     void dump(std::ostream& str = std::cout) const override;
     bool immediate() const { return m_immediate; }
 };
-class AstNodeFTaskRef VL_NOT_FINAL : public AstNodeStmt {
-    // A reference to a task (or function)
-    // @astgen op1 := namep : Optional[AstNode]
-    // op2 used by some sub-types only
-    // @astgen op3 := pinsp : List[AstNode]
-    // @astgen op4 := scopeNamep : Optional[AstScopeName]
-    //
-    // Functions are not statements, while tasks are. AstNodeStmt needs isStatement() to deal.
-private:
-    AstNodeFTask* m_taskp = nullptr;  // [AfterLink] Pointer to task referenced
-    AstNodeModule* m_classOrPackagep = nullptr;  // Package hierarchy
-    string m_name;  // Name of variable
-    string m_dotted;  // Dotted part of scope the name()ed task/func is under or ""
-    string m_inlinedDots;  // Dotted hierarchy flattened out
-    bool m_pli = false;  // Pli system call ($name)
-protected:
-    AstNodeFTaskRef(VNType t, FileLine* fl, bool statement, AstNode* namep, AstNode* pinsp)
-        : AstNodeStmt{t, fl, statement} {
-        this->namep(namep);
-        this->addPinsp(pinsp);
-    }
-    AstNodeFTaskRef(VNType t, FileLine* fl, bool statement, const string& name, AstNode* pinsp)
-        : AstNodeStmt{t, fl, statement}
-        , m_name{name} {
-        this->addPinsp(pinsp);
-    }
-
-public:
-    ASTGEN_MEMBERS_AstNodeFTaskRef;
-    const char* broken() const override;
-    void cloneRelink() override;
-    void dump(std::ostream& str = std::cout) const override;
-    string name() const override { return m_name; }  // * = Var name
-    bool isGateOptimizable() const override { return m_taskp && m_taskp->isGateOptimizable(); }
-    string dotted() const { return m_dotted; }  // * = Scope name or ""
-    string inlinedDots() const { return m_inlinedDots; }
-    void inlinedDots(const string& flag) { m_inlinedDots = flag; }
-    AstNodeFTask* taskp() const { return m_taskp; }  // [After Link] Pointer to variable
-    void taskp(AstNodeFTask* taskp) { m_taskp = taskp; }
-    void name(const string& name) override { m_name = name; }
-    void dotted(const string& name) { m_dotted = name; }
-    AstNodeModule* classOrPackagep() const { return m_classOrPackagep; }
-    void classOrPackagep(AstNodeModule* nodep) { m_classOrPackagep = nodep; }
-    bool pli() const { return m_pli; }
-    void pli(bool flag) { m_pli = flag; }
-};
 class AstNodeFor VL_NOT_FINAL : public AstNodeStmt {
     // @astgen op1 := initsp : List[AstNode]
     // @astgen op2 := condp : AstNode
@@ -635,22 +532,6 @@ public:
     void name(const string& name) override { m_name = name; }
     bool emptyConnectNoNext() const { return !exprp() && name() == "" && !nextp(); }
 };
-class AstAttrOf final : public AstNode {
-    // Return a value of a attribute, for example a LSB or array LSB of a signal
-    // @astgen op1 := fromp : Optional[AstNode]
-    // @astgen op2 := dimp : Optional[AstNode]
-    VAttrType m_attrType;  // What sort of extraction
-public:
-    AstAttrOf(FileLine* fl, VAttrType attrtype, AstNode* fromp = nullptr, AstNode* dimp = nullptr)
-        : ASTGEN_SUPER_AttrOf(fl) {
-        this->fromp(fromp);
-        this->dimp(dimp);
-        m_attrType = attrtype;
-    }
-    ASTGEN_MEMBERS_AstAttrOf;
-    VAttrType attrType() const { return m_attrType; }
-    void dump(std::ostream& str = std::cout) const override;
-};
 class AstBind final : public AstNode {
     // Parents: MODULE
     // Children: CELL
@@ -849,48 +730,6 @@ public:
     bool isDefault() const { return condsp() == nullptr; }
     bool isFirstInMyListOfStatements(AstNode* n) const override { return n == stmtsp(); }
 };
-class AstCast final : public AstNode {
-    // Cast to appropriate data type
-    // @astgen op1 := fromp : AstNode
-    // @astgen op2 := childDTypep : Optional[AstNodeDType]
-public:
-    AstCast(FileLine* fl, AstNode* fromp, VFlagChildDType, AstNodeDType* dtp)
-        : ASTGEN_SUPER_Cast(fl) {
-        this->fromp(fromp);
-        this->childDTypep(dtp);
-        dtypeFrom(dtp);
-    }
-    AstCast(FileLine* fl, AstNode* fromp, AstNodeDType* dtp)
-        : ASTGEN_SUPER_Cast(fl) {
-        this->fromp(fromp);
-        dtypeFrom(dtp);
-    }
-    ASTGEN_MEMBERS_AstCast;
-    bool hasDType() const override { return true; }
-    virtual string emitVerilog() { return "((%d)'(%l))"; }
-    virtual bool cleanOut() const { V3ERROR_NA_RETURN(true); }
-    virtual bool cleanLhs() const { return true; }
-    virtual bool sizeMattersLhs() const { return false; }
-    AstNodeDType* getChildDTypep() const override { return childDTypep(); }
-    virtual AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
-};
-class AstCastParse final : public AstNode {
-    // Cast to appropriate type, where we haven't determined yet what the data type is
-    // @astgen op1 := lhsp : AstNode
-    // @astgen op2 := dtp : AstNode
-public:
-    AstCastParse(FileLine* fl, AstNode* lhsp, AstNode* dtp)
-        : ASTGEN_SUPER_CastParse(fl) {
-        this->lhsp(lhsp);
-        this->dtp(dtp);
-    }
-    ASTGEN_MEMBERS_AstCastParse;
-    virtual string emitVerilog() { return "((%d)'(%l))"; }
-    virtual string emitC() { V3ERROR_NA_RETURN(""); }
-    virtual bool cleanOut() const { V3ERROR_NA_RETURN(true); }
-    virtual bool cleanLhs() const { return true; }
-    virtual bool sizeMattersLhs() const { return false; }
-};
 class AstCastSize final : public AstNode {
     // Cast to specific size; signed/twostate inherited from lower element per IEEE
     // @astgen op1 := lhsp : AstNode
@@ -1135,28 +974,6 @@ public:
     bool same(const AstNode*) const override { return true; }
     string path() const { return m_path; }
 };
-class AstDot final : public AstNode {
-    // A dot separating paths in an AstVarXRef, AstFuncRef or AstTaskRef
-    // These are eliminated in the link stage
-    // @astgen op1 := lhsp : AstNode
-    // @astgen op2 := rhsp : AstNode
-    const bool m_colon;  // Is a "::" instead of a "." (lhs must be package/class)
-public:
-    AstDot(FileLine* fl, bool colon, AstNode* lhsp, AstNode* rhsp)
-        : ASTGEN_SUPER_Dot(fl)
-        , m_colon{colon} {
-        this->lhsp(lhsp);
-        this->rhsp(rhsp);
-    }
-    ASTGEN_MEMBERS_AstDot;
-    // For parser, make only if non-null package
-    static AstNode* newIfPkg(FileLine* fl, AstNode* packageOrClassp, AstNode* rhsp) {
-        if (!packageOrClassp) return rhsp;
-        return new AstDot(fl, true, packageOrClassp, rhsp);
-    }
-    void dump(std::ostream& str) const override;
-    bool colon() const { return m_colon; }
-};
 class AstDpiExport final : public AstNode {
     // We could put an AstNodeFTaskRef instead of the verilog function name,
     // however we're not *calling* it, so that seems somehow wrong.
@@ -1497,37 +1314,6 @@ public:
     AstPackage* packagep() const { return m_packagep; }
     void packagep(AstPackage* nodep) { m_packagep = nodep; }
 };
-class AstParseRef final : public AstNode {
-    // A reference to a variable, function or task
-    // We don't know which at parse time due to bison constraints
-    // The link stages will replace this with AstVarRef, or AstTaskRef, etc.
-    // Parents: math|stmt
-    // @astgen op1 := lhsp : Optional[AstNode]
-    // @astgen op2 := ftaskrefp : Optional[AstNodeFTaskRef]
-
-    VParseRefExp m_expect;  // Type we think it should resolve to
-    string m_name;
-
-public:
-    AstParseRef(FileLine* fl, VParseRefExp expect, const string& name, AstNode* lhsp = nullptr,
-                AstNodeFTaskRef* ftaskrefp = nullptr)
-        : ASTGEN_SUPER_ParseRef(fl)
-        , m_expect{expect}
-        , m_name{name} {
-        this->lhsp(lhsp);
-        this->ftaskrefp(ftaskrefp);
-    }
-    ASTGEN_MEMBERS_AstParseRef;
-    void dump(std::ostream& str) const override;
-    string name() const override { return m_name; }  // * = Var name
-    bool same(const AstNode* samep) const override {
-        const AstParseRef* const asamep = static_cast<const AstParseRef*>(samep);
-        return (expect() == asamep->expect() && m_name == asamep->m_name);
-    }
-    void name(const string& name) override { m_name = name; }
-    VParseRefExp expect() const { return m_expect; }
-    void expect(VParseRefExp exp) { m_expect = exp; }
-};
 class AstPin final : public AstNode {
     // A port or parameter assignment on an instantiaton
     // @astgen op1 := exprp : Optional[AstNode] // Expression connected (nullptr if unconnected)
@@ -1629,58 +1415,6 @@ public:
     }
     uint32_t direction() const { return (uint32_t)m_direction; }
 };
-class AstSFormatF final : public AstNode {
-    // Convert format to string, generally under an AstDisplay or AstSFormat
-    // Also used as "real" function for /*verilator sformat*/ functions
-    // @astgen op1 := exprsp : List[AstNode]
-    // @astgen op2 := scopeNamep : Optional[AstScopeName]
-    string m_text;
-    const bool m_hidden;  // Under display, etc
-    bool m_hasFormat;  // Has format code
-    const char m_missingArgChar;  // Format code when argument without format, 'h'/'o'/'b'
-    VTimescale m_timeunit;  // Parent module time unit
-public:
-    class NoFormat {};
-    AstSFormatF(FileLine* fl, const string& text, bool hidden, AstNode* exprsp,
-                char missingArgChar = 'd')
-        : ASTGEN_SUPER_SFormatF(fl)
-        , m_text{text}
-        , m_hidden{hidden}
-        , m_hasFormat{true}
-        , m_missingArgChar{missingArgChar} {
-        dtypeSetString();
-        addExprsp(exprsp);
-    }
-    AstSFormatF(FileLine* fl, NoFormat, AstNode* exprsp, char missingArgChar = 'd',
-                bool hidden = true)
-        : ASTGEN_SUPER_SFormatF(fl)
-        , m_text{""}
-        , m_hidden{hidden}
-        , m_hasFormat{false}
-        , m_missingArgChar{missingArgChar} {
-        dtypeSetString();
-        addExprsp(exprsp);
-    }
-    ASTGEN_MEMBERS_AstSFormatF;
-    string name() const override { return m_text; }
-    int instrCount() const override { return INSTR_COUNT_PLI; }
-    bool hasDType() const override { return true; }
-    bool same(const AstNode* samep) const override {
-        return text() == static_cast<const AstSFormatF*>(samep)->text();
-    }
-    string verilogKwd() const override { return "$sformatf"; }
-    string text() const { return m_text; }  // * = Text to display
-    void text(const string& text) { m_text = text; }
-    bool formatScopeTracking() const {  // Track scopeNamep();  Ok if false positive
-        return (name().find("%m") != string::npos || name().find("%M") != string::npos);
-    }
-    bool hidden() const { return m_hidden; }
-    void hasFormat(bool flag) { m_hasFormat = flag; }
-    bool hasFormat() const { return m_hasFormat; }
-    char missingArgChar() const { return m_missingArgChar; }
-    void timeunit(const VTimescale& flag) { m_timeunit = flag; }
-    VTimescale timeunit() const { return m_timeunit; }
-};
 class AstScope final : public AstNode {
     // A particular usage of a cell
     // Parents: MODULE
@@ -1952,21 +1686,6 @@ public:
     string name() const override { return m_text; }
     string text() const { return m_text; }
 };
-class AstUnlinkedRef final : public AstNode {
-    // As-of-yet unlinkable Ref
-    // @astgen op1 := refp : AstNode
-    // @astgen op2 := cellrefp : AstNode
-
-    string m_name;  // Var name // TODO: There is no way to access this, fix or remove
-public:
-    AstUnlinkedRef(FileLine* fl, AstNode* refp, const string& name, AstNode* cellrefp)
-        : ASTGEN_SUPER_UnlinkedRef(fl)
-        , m_name{name} {
-        this->refp(refp);
-        this->cellrefp(cellrefp);
-    }
-    ASTGEN_MEMBERS_AstUnlinkedRef;
-};
 class AstVar final : public AstNode {
     // A variable (in/out/wire/reg/param) inside a module
     //
@@ -2593,49 +2312,6 @@ public:
     bool timescaleMatters() const override { return false; }
 };
 
-// === AstNodePreSel ===
-class AstSelBit final : public AstNodePreSel {
-    // Single bit range extraction, perhaps with non-constant selection or array selection
-    // Gets replaced during link with AstArraySel or AstSel
-public:
-    AstSelBit(FileLine* fl, AstNode* fromp, AstNode* bitp)
-        : ASTGEN_SUPER_SelBit(fl, fromp, bitp, nullptr) {
-        UASSERT_OBJ(!v3Global.assertDTypesResolved(), this,
-                    "not coded to create after dtypes resolved");
-    }
-    ASTGEN_MEMBERS_AstSelBit;
-    AstNode* bitp() const { return rhsp(); }
-};
-class AstSelExtract final : public AstNodePreSel {
-    // Range extraction, gets replaced with AstSel
-public:
-    AstSelExtract(FileLine* fl, AstNode* fromp, AstNode* msbp, AstNode* lsbp)
-        : ASTGEN_SUPER_SelExtract(fl, fromp, msbp, lsbp) {}
-    ASTGEN_MEMBERS_AstSelExtract;
-    AstNode* leftp() const { return rhsp(); }
-    AstNode* rightp() const { return thsp(); }
-};
-class AstSelMinus final : public AstNodePreSel {
-    // -: range extraction, perhaps with non-constant selection
-    // Gets replaced during link with AstSel
-public:
-    AstSelMinus(FileLine* fl, AstNode* fromp, AstNode* bitp, AstNode* widthp)
-        : ASTGEN_SUPER_SelMinus(fl, fromp, bitp, widthp) {}
-    ASTGEN_MEMBERS_AstSelMinus;
-    AstNode* bitp() const { return rhsp(); }
-    AstNode* widthp() const { return thsp(); }
-};
-class AstSelPlus final : public AstNodePreSel {
-    // +: range extraction, perhaps with non-constant selection
-    // Gets replaced during link with AstSel
-public:
-    AstSelPlus(FileLine* fl, AstNode* fromp, AstNode* bitp, AstNode* widthp)
-        : ASTGEN_SUPER_SelPlus(fl, fromp, bitp, widthp) {}
-    ASTGEN_MEMBERS_AstSelPlus;
-    AstNode* bitp() const { return rhsp(); }
-    AstNode* widthp() const { return thsp(); }
-};
-
 // === AstNodeProcedure ===
 class AstAlways final : public AstNodeProcedure {
     // @astgen op1 := sensesp : Optional[AstSenTree] // Sensitivity list iff clocked
@@ -2797,70 +2473,6 @@ public:
         return true;  // SPECIAL: We don't process code after breaks
     }
 };
-class AstCAwait final : public AstNodeStmt {
-    // Emit C++'s co_await statement
-    // @astgen op1 := exprp : AstNode
-    AstSenTree* m_sensesp;  // Sentree related to this await
-public:
-    AstCAwait(FileLine* fl, AstNode* exprp, AstSenTree* sensesp = nullptr)
-        : ASTGEN_SUPER_CAwait(fl)
-        , m_sensesp{sensesp} {
-        this->exprp(exprp);
-    }
-    ASTGEN_MEMBERS_AstCAwait;
-    bool isTimingControl() const override { return true; }
-    const char* broken() const override {
-        BROKEN_RTN(m_sensesp && !m_sensesp->brokeExists());
-        return nullptr;
-    }
-    void cloneRelink() override {
-        if (m_sensesp && m_sensesp->clonep()) m_sensesp = m_sensesp->clonep();
-    }
-    void dump(std::ostream& str) const override;
-    AstSenTree* sensesp() const { return m_sensesp; }
-    void clearSensesp() { m_sensesp = nullptr; }
-};
-class AstCMethodHard final : public AstNodeStmt {
-    // A reference to a "C" hardcoded member task (or function)
-    // PARENTS: stmt/math
-    // Not all calls are statments vs math.  AstNodeStmt needs isStatement() to deal.
-    // @astgen op1 := fromp : AstNode // Subject of method call
-    // @astgen op2 := pinsp : List[AstNode] // Arguments
-private:
-    string m_name;  // Name of method
-    bool m_pure = false;  // Pure optimizable
-public:
-    AstCMethodHard(FileLine* fl, AstNode* fromp, VFlagChildDType, const string& name,
-                   AstNode* pinsp = nullptr)
-        : ASTGEN_SUPER_CMethodHard(fl, false)
-        , m_name{name} {
-        // TODO: this constructor is exactly the same as the other, bar the ignored tag argument
-        this->fromp(fromp);
-        this->addPinsp(pinsp);
-        dtypep(nullptr);  // V3Width will resolve
-    }
-    AstCMethodHard(FileLine* fl, AstNode* fromp, const string& name, AstNode* pinsp = nullptr)
-        : ASTGEN_SUPER_CMethodHard(fl, false)
-        , m_name{name} {
-        this->fromp(fromp);
-        this->addPinsp(pinsp);
-    }
-    ASTGEN_MEMBERS_AstCMethodHard;
-    string name() const override { return m_name; }  // * = Var name
-    bool hasDType() const override { return true; }
-    void name(const string& name) override { m_name = name; }
-    bool same(const AstNode* samep) const override {
-        const AstCMethodHard* asamep = static_cast<const AstCMethodHard*>(samep);
-        return (m_name == asamep->m_name);
-    }
-    bool isPure() const override { return m_pure; }
-    void pure(bool flag) { m_pure = flag; }
-    void makeStatement() {
-        statement(true);
-        dtypeSetVoid();
-    }
-    int instrCount() const override;
-};
 class AstCReset final : public AstNodeStmt {
     // Reset variable at startup
     // @astgen op1 := varrefp : AstVarRef
@@ -3448,6 +3060,16 @@ public:
     int instrCount() const override { return INSTR_COUNT_PLI; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
+class AstStmtExpr final : public AstNodeStmt {
+    // Expression in statement position
+    // @astgen op1 := exprp : AstNodeExpr
+public:
+    AstStmtExpr(FileLine* fl, AstNodeExpr* exprp)
+        : ASTGEN_SUPER_StmtExpr(fl) {
+        this->exprp(exprp);
+    }
+    ASTGEN_MEMBERS_AstStmtExpr;
+};
 class AstStop final : public AstNodeStmt {
 public:
     AstStop(FileLine* fl, bool maybe)
@@ -3478,21 +3100,6 @@ public:
     int instrCount() const override { return 0; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstSysIgnore final : public AstNodeStmt {
-    // @astgen op1 := exprsp : List[AstNode] // Expressions to output (???)
-public:
-    AstSysIgnore(FileLine* fl, AstNode* exprsp)
-        : ASTGEN_SUPER_SysIgnore(fl) {
-        this->addExprsp(exprsp);
-    }
-    ASTGEN_MEMBERS_AstSysIgnore;
-    string verilogKwd() const override { return "$ignored"; }
-    bool isGateOptimizable() const override { return false; }  // Though deleted before opt
-    bool isPredictOptimizable() const override { return false; }  // Though deleted before opt
-    bool isPure() const override { return false; }  // Though deleted before opt
-    bool isOutputter() const override { return true; }  // Though deleted before opt
-    int instrCount() const override { return INSTR_COUNT_PLI; }
-};
 class AstSystemT final : public AstNodeStmt {
     // $system used as task
     // @astgen op1 := lhsp : AstNode
@@ -3708,7 +3315,7 @@ class AstWith final : public AstNodeStmt {
     // Parents: funcref (similar to AstArg)
     // Children: LambdaArgRef that declares the item variable
     // Children: LambdaArgRef that declares the item.index variable
-    // Children: math (equation establishing the with)
+    // Children: expression (equation establishing the with)
     // @astgen op1 := indexArgRefp : AstLambdaArgRef
     // @astgen op2 := valueArgRefp : AstLambdaArgRef
     // @astgen op3 := exprp : AstNode
@@ -3729,23 +3336,6 @@ public:
         return nullptr;
     }
 };
-class AstWithParse final : public AstNodeStmt {
-    // In early parse, FUNC(index) WITH equation-using-index
-    // Replaced with AstWith
-    // Parents: math|stmt
-    // Children: funcref, math
-    // @astgen op1 := funcrefp : AstNode
-    // @astgen op2 := exprp : Optional[AstNode]
-public:
-    AstWithParse(FileLine* fl, bool stmt, AstNode* funcrefp, AstNode* exprp)
-        : ASTGEN_SUPER_WithParse(fl) {
-        statement(stmt);
-        this->funcrefp(funcrefp);
-        this->exprp(exprp);
-    }
-    ASTGEN_MEMBERS_AstWithParse;
-    bool same(const AstNode* /*samep*/) const override { return true; }
-};
 
 // === AstNodeAssign ===
 class AstAssign final : public AstNodeAssign {
@@ -3850,52 +3440,6 @@ public:
     AstAlways* convertToAlways();
 };
 
-// === AstNodeCCall ===
-class AstCCall final : public AstNodeCCall {
-    // C++ function call
-    // Parents:  Anything above a statement
-    // Children: Args to the function
-
-    string m_selfPointer;  // Output code object pointer (e.g.: 'this')
-
-public:
-    AstCCall(FileLine* fl, AstCFunc* funcp, AstNode* argsp = nullptr)
-        : ASTGEN_SUPER_CCall(fl, funcp, argsp) {}
-    ASTGEN_MEMBERS_AstCCall;
-
-    string selfPointer() const { return m_selfPointer; }
-    void selfPointer(const string& value) { m_selfPointer = value; }
-    string selfPointerProtect(bool useSelfForThis) const;
-};
-class AstCMethodCall final : public AstNodeCCall {
-    // C++ method call
-    // Parents:  Anything above a statement
-    // @astgen op1 := fromp : AstNode
-public:
-    AstCMethodCall(FileLine* fl, AstNode* fromp, AstCFunc* funcp, AstNode* argsp = nullptr)
-        : ASTGEN_SUPER_CMethodCall(fl, funcp, argsp) {
-        this->fromp(fromp);
-    }
-    ASTGEN_MEMBERS_AstCMethodCall;
-    const char* broken() const override {
-        BROKEN_BASE_RTN(AstNodeCCall::broken());
-        BROKEN_RTN(!fromp());
-        return nullptr;
-    }
-};
-class AstCNew final : public AstNodeCCall {
-    // C++ new() call
-    // Parents:  Anything above an expression
-    // Children: Args to the function
-public:
-    AstCNew(FileLine* fl, AstCFunc* funcp, AstNode* argsp = nullptr)
-        : ASTGEN_SUPER_CNew(fl, funcp, argsp) {
-        statement(false);
-    }
-    bool hasDType() const override { return true; }
-    ASTGEN_MEMBERS_AstCNew;
-};
-
 // === AstNodeCase ===
 class AstCase final : public AstNodeCase {
     // Case statement
@@ -3979,74 +3523,6 @@ public:
         : ASTGEN_SUPER_Restrict(fl, propp, nullptr, false, "") {}
 };
 
-// === AstNodeFTaskRef ===
-class AstFuncRef final : public AstNodeFTaskRef {
-    // A reference to a function
-public:
-    AstFuncRef(FileLine* fl, AstParseRef* namep, AstNode* pinsp)
-        : ASTGEN_SUPER_FuncRef(fl, false, namep, pinsp) {}
-    AstFuncRef(FileLine* fl, const string& name, AstNode* pinsp)
-        : ASTGEN_SUPER_FuncRef(fl, false, name, pinsp) {}
-    ASTGEN_MEMBERS_AstFuncRef;
-    bool hasDType() const override { return true; }
-};
-class AstMethodCall final : public AstNodeFTaskRef {
-    // A reference to a member task (or function)
-    // PARENTS: stmt/math
-    // Not all calls are statments vs math.  AstNodeStmt needs isStatement() to deal.
-    // Don't need the class we are extracting from, as the "fromp()"'s datatype can get us to it
-    // @astgen op2 := fromp : AstNode
-    //
-public:
-    AstMethodCall(FileLine* fl, AstNode* fromp, VFlagChildDType, const string& name,
-                  AstNode* pinsp)
-        : ASTGEN_SUPER_MethodCall(fl, false, name, pinsp) {
-        this->fromp(fromp);
-        dtypep(nullptr);  // V3Width will resolve
-    }
-    AstMethodCall(FileLine* fl, AstNode* fromp, const string& name, AstNode* pinsp)
-        : ASTGEN_SUPER_MethodCall(fl, false, name, pinsp) {
-        this->fromp(fromp);
-    }
-    ASTGEN_MEMBERS_AstMethodCall;
-    const char* broken() const override {
-        BROKEN_BASE_RTN(AstNodeFTaskRef::broken());
-        BROKEN_RTN(!fromp());
-        return nullptr;
-    }
-    void dump(std::ostream& str) const override;
-    bool hasDType() const override { return true; }
-    void makeStatement() {
-        statement(true);
-        dtypeSetVoid();
-    }
-};
-class AstNew final : public AstNodeFTaskRef {
-    // New as constructor
-    // Don't need the class we are extracting from, as the "fromp()"'s datatype can get us to it
-    // Parents: math|stmt
-    // Children: varref|arraysel, math
-public:
-    AstNew(FileLine* fl, AstNode* pinsp)
-        : ASTGEN_SUPER_New(fl, false, "new", pinsp) {}
-    ASTGEN_MEMBERS_AstNew;
-    virtual bool cleanOut() const { return true; }
-    bool same(const AstNode* /*samep*/) const override { return true; }
-    bool hasDType() const override { return true; }
-    int instrCount() const override { return widthInstrs(); }
-};
-class AstTaskRef final : public AstNodeFTaskRef {
-    // A reference to a task
-public:
-    AstTaskRef(FileLine* fl, AstParseRef* namep, AstNode* pinsp)
-        : ASTGEN_SUPER_TaskRef(fl, true, namep, pinsp) {
-        statement(true);
-    }
-    AstTaskRef(FileLine* fl, const string& name, AstNode* pinsp)
-        : ASTGEN_SUPER_TaskRef(fl, true, name, pinsp) {}
-    ASTGEN_MEMBERS_AstTaskRef;
-};
-
 // === AstNodeFor ===
 class AstGenFor final : public AstNodeFor {
 public:
diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index 3487e1814..9f6dde5b0 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -60,6 +60,8 @@ void AstNodeFTaskRef::cloneRelink() {
     }
 }
 
+bool AstNodeFTaskRef::isGateOptimizable() const { return m_taskp && m_taskp->isGateOptimizable(); }
+
 const char* AstNodeVarRef::broken() const {
     BROKEN_RTN(m_varp && !m_varp->brokeExists());
     BROKEN_RTN(m_varScopep && !m_varScopep->brokeExists());
@@ -123,7 +125,7 @@ const char* AstNodeUOrStructDType::broken() const {
 void AstNodeStmt::dump(std::ostream& str) const { this->AstNode::dump(str); }
 
 void AstNodeCCall::dump(std::ostream& str) const {
-    this->AstNodeStmt::dump(str);
+    this->AstNodeExpr::dump(str);
     if (funcp()) {
         str << " " << funcp()->name() << " => ";
         funcp()->dump(str);
@@ -1376,8 +1378,8 @@ string AstBasicDType::prettyDTypeName() const {
     return os.str();
 }
 
-void AstNodeMath::dump(std::ostream& str) const { this->AstNode::dump(str); }
-void AstNodeUniop::dump(std::ostream& str) const { this->AstNodeMath::dump(str); }
+void AstNodeExpr::dump(std::ostream& str) const { this->AstNode::dump(str); }
+void AstNodeUniop::dump(std::ostream& str) const { this->AstNodeExpr::dump(str); }
 
 void AstCCast::dump(std::ostream& str) const {
     this->AstNodeUniop::dump(str);
@@ -1504,7 +1506,7 @@ void AstDisplay::dump(std::ostream& str) const {
     // str << " " << displayType().ascii();
 }
 void AstEnumItemRef::dump(std::ostream& str) const {
-    this->AstNodeMath::dump(str);
+    this->AstNodeExpr::dump(str);
     str << " -> ";
     if (itemp()) {
         itemp()->dump(str);
@@ -1615,11 +1617,11 @@ void AstJumpLabel::dump(std::ostream& str) const {
     }
 }
 void AstLogOr::dump(std::ostream& str) const {
-    this->AstNodeMath::dump(str);
+    this->AstNodeExpr::dump(str);
     if (sideEffect()) str << " [SIDE]";
 }
 void AstMemberSel::dump(std::ostream& str) const {
-    this->AstNodeMath::dump(str);
+    this->AstNodeExpr::dump(str);
     str << " -> ";
     if (varp()) {
         varp()->dump(str);
@@ -1636,7 +1638,6 @@ const char* AstMemberSel::broken() const {
 }
 void AstMethodCall::dump(std::ostream& str) const {
     this->AstNodeFTaskRef::dump(str);
-    if (isStatement()) str << " [STMT]";
     str << " -> ";
     if (taskp()) {
         taskp()->dump(str);
@@ -1705,7 +1706,7 @@ void AstPrintTimeScale::dump(std::ostream& str) const {
     str << " " << timeunit();
 }
 
-void AstNodeTermop::dump(std::ostream& str) const { this->AstNodeMath::dump(str); }
+void AstNodeTermop::dump(std::ostream& str) const { this->AstNodeExpr::dump(str); }
 void AstTime::dump(std::ostream& str) const {
     this->AstNodeTermop::dump(str);
     str << " " << timeunit();
@@ -1908,10 +1909,10 @@ void AstPackageImport::cloneRelink() {
     if (m_packagep && m_packagep->clonep()) m_packagep = m_packagep->clonep();
 }
 void AstPatMember::dump(std::ostream& str) const {
-    this->AstNodeMath::dump(str);
+    this->AstNodeExpr::dump(str);
     if (isDefault()) str << " [DEFAULT]";
 }
-void AstNodeTriop::dump(std::ostream& str) const { this->AstNodeMath::dump(str); }
+void AstNodeTriop::dump(std::ostream& str) const { this->AstNodeExpr::dump(str); }
 void AstSel::dump(std::ostream& str) const {
     this->AstNodeTriop::dump(str);
     if (declRange().ranged()) {
@@ -2018,7 +2019,7 @@ void AstVarScope::dump(std::ostream& str) const {
     }
 }
 void AstNodeVarRef::dump(std::ostream& str) const {
-    this->AstNodeMath::dump(str);
+    this->AstNodeExpr::dump(str);
     if (classOrPackagep()) str << " pkg=" << nodeAddr(classOrPackagep());
     str << " " << access().arrow() << " ";
 }
@@ -2086,7 +2087,7 @@ void AstScope::dump(std::ostream& str) const {
     str << " [modp=" << reinterpret_cast<const void*>(modp()) << "]";
 }
 void AstScopeName::dump(std::ostream& str) const {
-    this->AstNodeMath::dump(str);
+    this->AstNodeExpr::dump(str);
     if (dpiExport()) str << " [DPIEX]";
     if (forFormat()) str << " [FMT]";
 }
@@ -2145,7 +2146,7 @@ void AstActive::cloneRelink() {
     if (m_sensesp->clonep()) m_sensesp = m_sensesp->clonep();
 }
 void AstNodeFTaskRef::dump(std::ostream& str) const {
-    this->AstNodeStmt::dump(str);
+    this->AstNodeExpr::dump(str);
     if (classOrPackagep()) str << " pkg=" << nodeAddr(classOrPackagep());
     str << " -> ";
     if (dotted() != "") str << ".=" << dotted() << " ";
@@ -2248,8 +2249,15 @@ void AstCFunc::dump(std::ostream& str) const {
     if (isVirtual()) str << " [VIRT]";
     if (isCoroutine()) str << " [CORO]";
 }
+const char* AstCAwait::broken() const {
+    BROKEN_RTN(m_sensesp && !m_sensesp->brokeExists());
+    return nullptr;
+}
+void AstCAwait::cloneRelink() {
+    if (m_sensesp && m_sensesp->clonep()) m_sensesp = m_sensesp->clonep();
+}
 void AstCAwait::dump(std::ostream& str) const {
-    this->AstNodeStmt::dump(str);
+    this->AstNodeUniop::dump(str);
     if (sensesp()) {
         str << " => ";
         sensesp()->dump(str);
@@ -2265,7 +2273,7 @@ int AstCMethodHard::instrCount() const {
             return INSTR_COUNT_LD;
         }
     }
-    return AstNodeStmt::instrCount();
+    return 0;
 }
 const char* AstCFunc::broken() const {
     BROKEN_RTN((m_scopep && !m_scopep->brokeExists()));
diff --git a/src/V3CCtors.cpp b/src/V3CCtors.cpp
index 2dbc74121..f1e5b1bca 100644
--- a/src/V3CCtors.cpp
+++ b/src/V3CCtors.cpp
@@ -112,13 +112,14 @@ public:
             rootFuncp->name(m_basename);
             for (AstCFunc* const funcp : m_newFunctions) {
                 AstCCall* const callp = new AstCCall{m_modp->fileline(), funcp};
+                callp->dtypeSetVoid();
                 if (m_type.isClass()) {
                     callp->argTypes("vlSymsp");
                 } else {
                     if (m_type.isCoverage()) callp->argTypes("first");
                     callp->selfPointer("this");
                 }
-                rootFuncp->addStmtsp(callp);
+                rootFuncp->addStmtsp(callp->makeStmt());
             }
         }
     }
diff --git a/src/V3Cast.cpp b/src/V3Cast.cpp
index 8f7c303e3..0db4e7578 100644
--- a/src/V3Cast.cpp
+++ b/src/V3Cast.cpp
@@ -16,9 +16,9 @@
 // V3Cast's Transformations:
 //
 // Each module:
-//      For each math operator, if above operator requires 32 bits,
+//      For each expression, if above expression requires 32 bits,
 //      and this isn't, cast to 32 bits.
-//      Likewise for 64 bit operators.
+//      Likewise for 64 bit expressions.
 //
 // C++ rules:
 //      Integral promotions allow conversion to larger int.  Unsigned is only
@@ -158,7 +158,8 @@ private:
     }
     void visit(AstVarRef* nodep) override {
         const AstNode* const backp = nodep->backp();
-        if (nodep->access().isReadOnly() && !VN_IS(backp, CCast) && VN_IS(backp, NodeMath)
+        if (nodep->access().isReadOnly() && VN_IS(backp, NodeExpr) && !VN_IS(backp, CCast)
+            && !VN_IS(backp, NodeCCall) && !VN_IS(backp, CMethodHard) && !VN_IS(backp, SFormatF)
             && !VN_IS(backp, ArraySel) && !VN_IS(backp, RedXor)
             && (nodep->varp()->basicp() && !nodep->varp()->basicp()->isTriggerVec()
                 && !nodep->varp()->basicp()->isForkSync())
diff --git a/src/V3Cdc.cpp b/src/V3Cdc.cpp
index 163a34002..0bd371111 100644
--- a/src/V3Cdc.cpp
+++ b/src/V3Cdc.cpp
@@ -697,7 +697,7 @@ private:
     void visit(AstAssignAlias* nodep) override { iterateNewStmt(nodep); }
     void visit(AstAssignW* nodep) override { iterateNewStmt(nodep); }
 
-    // Math that shouldn't cause us to clear hazard
+    // Expressions that shouldn't cause us to clear hazard
     void visit(AstConst*) override {}
     void visit(AstReplicate* nodep) override { iterateChildren(nodep); }
     void visit(AstConcat* nodep) override { iterateChildren(nodep); }
@@ -721,7 +721,7 @@ private:
 
     //--------------------
     // Default
-    void visit(AstNodeMath* nodep) override {
+    void visit(AstNodeExpr* nodep) override {
         setNodeHazard(nodep);
         iterateChildren(nodep);
     }
diff --git a/src/V3Class.cpp b/src/V3Class.cpp
index 810fe95d7..88cae1fc9 100644
--- a/src/V3Class.cpp
+++ b/src/V3Class.cpp
@@ -166,7 +166,7 @@ private:
         }
     }
 
-    void visit(AstNodeMath* nodep) override {}  // Short circuit
+    void visit(AstNodeExpr* nodep) override {}  // Short circuit
     void visit(AstNodeStmt* nodep) override {}  // Short circuit
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
diff --git a/src/V3Clean.cpp b/src/V3Clean.cpp
index cd9c96d7d..db31e87fb 100644
--- a/src/V3Clean.cpp
+++ b/src/V3Clean.cpp
@@ -16,7 +16,7 @@
 // V3Clean's Transformations:
 //
 // Each module:
-//      For each math operator, if it requires a clean operand,
+//      For each expression, if it requires a clean operand,
 //      and the operand is dirty, insert a CLEAN node.
 //      Resize operands to C++ 32/64/wide types.
 //      Copy all width() values to widthMin() so RANGE, etc can still see orig widths
@@ -207,7 +207,7 @@ private:
         operandQuadop(nodep);
         setClean(nodep, nodep->cleanOut());
     }
-    void visit(AstNodeMath* nodep) override {
+    void visit(AstNodeExpr* nodep) override {
         iterateChildren(nodep);
         computeCppWidth(nodep);
         setClean(nodep, nodep->cleanOut());
diff --git a/src/V3Combine.cpp b/src/V3Combine.cpp
index 7d61aae35..ee19f0eef 100644
--- a/src/V3Combine.cpp
+++ b/src/V3Combine.cpp
@@ -69,7 +69,9 @@ class CombineVisitor final : VNVisitor {
             if (funcp->emptyBody()) {
                 // Delete call sites
                 for (AstCCall* const callp : m_callSites(funcp)) {
-                    VL_DO_DANGLING(callp->unlinkFrBack()->deleteTree(), callp);
+                    UASSERT_OBJ(VN_IS(callp->backp(), StmtExpr), callp,
+                                "Deleting non-statement call");
+                    VL_DO_DANGLING(callp->backp()->unlinkFrBack()->deleteTree(), callp);
                 }
                 m_callSites(funcp).clear();
                 // Remove from list
diff --git a/src/V3Common.cpp b/src/V3Common.cpp
index 907c5a33d..9df1abc8a 100644
--- a/src/V3Common.cpp
+++ b/src/V3Common.cpp
@@ -42,7 +42,7 @@ static void makeVlToString(AstClass* nodep) {
     funcp->isConst(false);
     funcp->isStatic(false);
     funcp->protect(false);
-    AstNode* const exprp = new AstCMath{nodep->fileline(), "obj ? obj->to_string() : \"null\"", 0};
+    AstNode* const exprp = new AstCExpr{nodep->fileline(), "obj ? obj->to_string() : \"null\"", 0};
     exprp->dtypeSetString();
     funcp->addStmtsp(new AstCReturn{nodep->fileline(), exprp});
     nodep->addStmtsp(funcp);
@@ -55,7 +55,7 @@ static void makeVlToString(AstIface* nodep) {
     funcp->isConst(false);
     funcp->isStatic(false);
     funcp->protect(false);
-    AstNode* const exprp = new AstCMath{nodep->fileline(), "obj ? obj->name() : \"null\"", 0};
+    AstNode* const exprp = new AstCExpr{nodep->fileline(), "obj ? obj->name() : \"null\"", 0};
     exprp->dtypeSetString();
     funcp->addStmtsp(new AstCReturn{nodep->fileline(), exprp});
     nodep->addStmtsp(funcp);
@@ -66,7 +66,7 @@ static void makeToString(AstClass* nodep) {
     funcp->isStatic(false);
     funcp->protect(false);
     AstNode* const exprp
-        = new AstCMath{nodep->fileline(), R"(std::string{"'{"} + to_string_middle() + "}")", 0};
+        = new AstCExpr{nodep->fileline(), R"(std::string{"'{"} + to_string_middle() + "}")", 0};
     exprp->dtypeSetString();
     funcp->addStmtsp(new AstCReturn{nodep->fileline(), exprp});
     nodep->addStmtsp(funcp);
diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 9d1b7f7f8..3f75f93ae 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -2602,6 +2602,10 @@ private:
         }
         m_selp = nullptr;
     }
+    void visit(AstCAwait* nodep) override {
+        m_hasJumpDelay = true;
+        iterateChildren(nodep);
+    }
     void visit(AstNodeVarRef* nodep) override {
         iterateChildren(nodep);
         UASSERT_OBJ(nodep->varp(), nodep, "Not linked");
@@ -2682,7 +2686,7 @@ private:
     }
 
     //  void visit(AstCvtPackString* nodep) override {
-    // Not constant propagated (for today) because AstNodeMath::isOpaque is set
+    // Not constant propagated (for today) because AstNodeExpr::isOpaque is set
     // Someday if lower is constant, convert to quoted "string".
 
     bool onlySenItemInSenTree(AstSenItem* nodep) {
@@ -3166,6 +3170,11 @@ private:
         if (m_doNConst) VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
     }
 
+    void visit(AstStmtExpr* nodep) override {
+        iterateChildren(nodep);
+        if (!nodep->exprp()) VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
+    }
+
     // Simplify
     void visit(AstBasicDType* nodep) override {
         iterateChildren(nodep);
@@ -3232,6 +3241,7 @@ private:
     //-----
     // clang-format off
     TREE_SKIP_VISIT("ArraySel");
+    TREE_SKIP_VISIT("CAwait");
 
     //-----
     //  "AstNODETYPE {             # bracket not paren
diff --git a/src/V3CoverageJoin.cpp b/src/V3CoverageJoin.cpp
index d5571a7a7..8e1b6cc6d 100644
--- a/src/V3CoverageJoin.cpp
+++ b/src/V3CoverageJoin.cpp
@@ -100,7 +100,7 @@ private:
         iterateChildren(nodep);
     }
     //--------------------
-    void visit(AstNodeMath*) override {}  // Accelerate
+    void visit(AstNodeExpr*) override {}  // Accelerate
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp
index c7012c72b..56f67b57d 100644
--- a/src/V3Delayed.cpp
+++ b/src/V3Delayed.cpp
@@ -485,9 +485,8 @@ private:
                 AstIf* const ifp = new AstIf{flp, dlyRef(VAccess::READ)};
                 postp->addStmtsp(ifp);
                 AstCMethodHard* const callp = new AstCMethodHard{flp, vrefp, "fire"};
-                callp->statement(true);
                 callp->dtypeSetVoid();
-                ifp->addThensp(callp);
+                ifp->addThensp(callp->makeStmt());
             }
 
             AstActive* const activep = createActive(nodep);
@@ -501,8 +500,7 @@ private:
             AstCMethodHard* const callp
                 = new AstCMethodHard{flp, nodep->operandp()->unlinkFrBack(), "fire"};
             callp->dtypeSetVoid();
-            callp->statement(true);
-            nodep->replaceWith(callp);
+            nodep->replaceWith(callp->makeStmt());
         }
         nodep->deleteTree();
     }
diff --git a/src/V3Depth.cpp b/src/V3Depth.cpp
index 489d36b7d..fa1c31ea5 100644
--- a/src/V3Depth.cpp
+++ b/src/V3Depth.cpp
@@ -107,16 +107,10 @@ private:
             iterateChildren(nodep);
         }
     }
-    void visit(AstNodeStmt* nodep) override {
-        if (!nodep->isStatement()) {
-            iterateChildren(nodep);
-        } else {
-            visitStmt(nodep);
-        }
-    }
+    void visit(AstNodeStmt* nodep) override { visitStmt(nodep); }
     // Operators
     void visit(AstNodeTermop* nodep) override {}
-    void visit(AstNodeMath* nodep) override {
+    void visit(AstNodeExpr* nodep) override {
         // We have some operator defines that use 2 parens, so += 2.
         {
             VL_RESTORER(m_depth);
diff --git a/src/V3DepthBlock.cpp b/src/V3DepthBlock.cpp
index 9399e78e0..69497def3 100644
--- a/src/V3DepthBlock.cpp
+++ b/src/V3DepthBlock.cpp
@@ -47,7 +47,7 @@ private:
 
     // METHODS
 
-    AstCFunc* createDeepFunc(AstNode* nodep) {
+    AstCFunc* createDeepFunc(AstNodeStmt* nodep) {
         VNRelinker relinkHandle;
         nodep->unlinkFrBack(&relinkHandle);
         // Create sub function
@@ -61,12 +61,13 @@ private:
         scopep->addBlocksp(funcp);
         // Call sub function at the point where the body was removed from
         AstCCall* const callp = new AstCCall(nodep->fileline(), funcp);
+        callp->dtypeSetVoid();
         if (VN_IS(m_modp, Class)) {
             funcp->argTypes(EmitCBaseVisitor::symClassVar());
             callp->argTypes("vlSymsp");
         }
         UINFO(6, "      New " << callp << endl);
-        relinkHandle.relink(callp);
+        relinkHandle.relink(callp->makeStmt());
         // Done
         return funcp;
     }
@@ -91,10 +92,10 @@ private:
             iterateChildren(nodep);
         }
     }
-    void visitStmt(AstNodeStmt* nodep) {
+    void visit(AstStmtExpr* nodep) override {}  // Stop recursion after introducing new function
+    void visit(AstNodeStmt* nodep) override {
         m_depth++;
-        if (m_depth > v3Global.opt.compLimitBlocks()
-            && !VN_IS(nodep, NodeCCall)) {  // Already done
+        if (m_depth > v3Global.opt.compLimitBlocks()) {  // Already done
             UINFO(4, "DeepBlocks " << m_depth << " " << nodep << endl);
             const AstNode* const backp = nodep->backp();  // Only for debug
             if (debug() >= 9) backp->dumpTree(cout, "-   pre : ");
@@ -107,15 +108,8 @@ private:
         }
         m_depth--;
     }
-    void visit(AstNodeStmt* nodep) override {
-        if (!nodep->isStatement()) {
-            iterateChildren(nodep);
-        } else {
-            visitStmt(nodep);
-        }
-    }
 
-    void visit(AstNodeMath*) override {}  // Accelerate
+    void visit(AstNodeExpr*) override {}  // Accelerate
     //--------------------
     void visit(AstVar*) override {}  // Don't hit varrefs under vars
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
diff --git a/src/V3Descope.cpp b/src/V3Descope.cpp
index 10ab9b2ff..07f985362 100644
--- a/src/V3Descope.cpp
+++ b/src/V3Descope.cpp
@@ -152,15 +152,20 @@ private:
                         }
                     }
 
-                    AstNode* const returnp = new AstCReturn(
-                        funcp->fileline(), new AstCCall(funcp->fileline(), funcp, argsp));
+                    AstCCall* const callp = new AstCCall{funcp->fileline(), funcp, argsp};
+                    if (AstNodeDType* const dtypep = funcp->dtypep()) {
+                        callp->dtypep(dtypep);
+                    } else {
+                        callp->dtypeSetVoid();
+                    }
+                    AstNode* const returnp = new AstCReturn{funcp->fileline(), callp};
 
                     if (moreOfSame) {
                         AstIf* const ifp = new AstIf(
                             funcp->fileline(),
                             new AstEq(
-                                funcp->fileline(), new AstCMath(funcp->fileline(), "this", 64),
-                                new AstCMath(funcp->fileline(),
+                                funcp->fileline(), new AstCExpr(funcp->fileline(), "this", 64),
+                                new AstCExpr(funcp->fileline(),
                                              string("&(") + funcp->scopep()->nameVlSym() + ")",
                                              64)),
                             returnp);
diff --git a/src/V3Dfg.h b/src/V3Dfg.h
index a81f0cea5..f49110296 100644
--- a/src/V3Dfg.h
+++ b/src/V3Dfg.h
@@ -870,7 +870,7 @@ public:
 // DfgVertex subclasses
 #include "V3DfgVertices.h"
 
-// The rest of the DfgVertex subclasses are generated by 'astgen' from AstNodeMath nodes
+// The rest of the DfgVertex subclasses are generated by 'astgen' from AstNodeExpr nodes
 #include "V3Dfg__gen_auto_classes.h"
 
 DfgVertexVar* DfgGraph::varVerticesBeginp() const {
diff --git a/src/V3DfgAstToDfg.cpp b/src/V3DfgAstToDfg.cpp
index b494c81dc..d81ecbfb3 100644
--- a/src/V3DfgAstToDfg.cpp
+++ b/src/V3DfgAstToDfg.cpp
@@ -39,7 +39,7 @@ VL_DEFINE_DEBUG_FUNCTIONS;
 
 namespace {
 
-// Create a DfgVertex out of a AstNodeMath. For most AstNodeMath subtypes, this can be done
+// Create a DfgVertex out of a AstNodeExpr. For most AstNodeExpr subtypes, this can be done
 // automatically. For the few special cases, we provide specializations below
 template <typename Vertex, typename Node>
 Vertex* makeVertex(const Node* nodep, DfgGraph& dfg) {
@@ -132,7 +132,7 @@ class AstToDfgVisitor final : public VNVisitor {
     }
 
     // Returns true if the expression cannot (or should not) be represented by DFG
-    bool unhandled(AstNodeMath* nodep) {
+    bool unhandled(AstNodeExpr* nodep) {
         // Short-circuiting if something was already unhandled
         if (!m_foundUnhandled) {
             // Impure nodes cannot be represented
diff --git a/src/V3DfgDfgToAst.cpp b/src/V3DfgDfgToAst.cpp
index 1ac43d319..f87c443c8 100644
--- a/src/V3DfgDfgToAst.cpp
+++ b/src/V3DfgDfgToAst.cpp
@@ -14,7 +14,7 @@
 //
 //*************************************************************************
 //
-// Convert DfgGraph back to AstModule. We recursively construct AstNodeMath expressions for each
+// Convert DfgGraph back to AstModule. We recursively construct AstNodeExpr expressions for each
 // DfgVertex which represents a storage location (e.g.: DfgVarPacked), or has multiple sinks
 // without driving a storage location (and hence needs a temporary variable to duplication). The
 // recursion stops when we reach a DfgVertex representing a storage location (e.g.: DfgVarPacked),
@@ -40,7 +40,7 @@ VL_DEFINE_DEBUG_FUNCTIONS;
 
 namespace {
 
-// Create an AstNodeMath out of a DfgVertex. For most AstNodeMath subtypes, this can be done
+// Create an AstNodeExpr out of a DfgVertex. For most AstNodeExpr subtypes, this can be done
 // automatically. For the few special cases, we provide specializations below
 template <typename Node, typename Vertex, typename... Ops>
 Node* makeNode(const Vertex* vtxp, Ops... ops) {
@@ -55,8 +55,8 @@ Node* makeNode(const Vertex* vtxp, Ops... ops) {
 // Vertices needing special conversion
 
 template <>
-AstCountOnes* makeNode<AstCountOnes, DfgCountOnes, AstNodeMath*>(  //
-    const DfgCountOnes* vtxp, AstNodeMath* op1) {
+AstCountOnes* makeNode<AstCountOnes, DfgCountOnes, AstNodeExpr*>(  //
+    const DfgCountOnes* vtxp, AstNodeExpr* op1) {
     AstCountOnes* const nodep = new AstCountOnes{vtxp->fileline(), op1};
     // Set dtype same as V3Width
     const int selwidth = V3Number::log2b(nodep->lhsp()->width()) + 1;
@@ -65,32 +65,32 @@ AstCountOnes* makeNode<AstCountOnes, DfgCountOnes, AstNodeMath*>(  //
 }
 
 template <>
-AstExtend* makeNode<AstExtend, DfgExtend, AstNodeMath*>(  //
-    const DfgExtend* vtxp, AstNodeMath* op1) {
+AstExtend* makeNode<AstExtend, DfgExtend, AstNodeExpr*>(  //
+    const DfgExtend* vtxp, AstNodeExpr* op1) {
     return new AstExtend{vtxp->fileline(), op1, static_cast<int>(vtxp->width())};
 }
 
 template <>
-AstExtendS* makeNode<AstExtendS, DfgExtendS, AstNodeMath*>(  //
-    const DfgExtendS* vtxp, AstNodeMath* op1) {
+AstExtendS* makeNode<AstExtendS, DfgExtendS, AstNodeExpr*>(  //
+    const DfgExtendS* vtxp, AstNodeExpr* op1) {
     return new AstExtendS{vtxp->fileline(), op1, static_cast<int>(vtxp->width())};
 }
 
 template <>
-AstShiftL* makeNode<AstShiftL, DfgShiftL, AstNodeMath*, AstNodeMath*>(  //
-    const DfgShiftL* vtxp, AstNodeMath* op1, AstNodeMath* op2) {
+AstShiftL* makeNode<AstShiftL, DfgShiftL, AstNodeExpr*, AstNodeExpr*>(  //
+    const DfgShiftL* vtxp, AstNodeExpr* op1, AstNodeExpr* op2) {
     return new AstShiftL{vtxp->fileline(), op1, op2, static_cast<int>(vtxp->width())};
 }
 
 template <>
-AstShiftR* makeNode<AstShiftR, DfgShiftR, AstNodeMath*, AstNodeMath*>(  //
-    const DfgShiftR* vtxp, AstNodeMath* op1, AstNodeMath* op2) {
+AstShiftR* makeNode<AstShiftR, DfgShiftR, AstNodeExpr*, AstNodeExpr*>(  //
+    const DfgShiftR* vtxp, AstNodeExpr* op1, AstNodeExpr* op2) {
     return new AstShiftR{vtxp->fileline(), op1, op2, static_cast<int>(vtxp->width())};
 }
 
 template <>
-AstShiftRS* makeNode<AstShiftRS, DfgShiftRS, AstNodeMath*, AstNodeMath*>(  //
-    const DfgShiftRS* vtxp, AstNodeMath* op1, AstNodeMath* op2) {
+AstShiftRS* makeNode<AstShiftRS, DfgShiftRS, AstNodeExpr*, AstNodeExpr*>(  //
+    const DfgShiftRS* vtxp, AstNodeExpr* op1, AstNodeExpr* op2) {
     return new AstShiftRS{vtxp->fileline(), op1, op2, static_cast<int>(vtxp->width())};
 }
 
@@ -98,22 +98,22 @@ AstShiftRS* makeNode<AstShiftRS, DfgShiftRS, AstNodeMath*, AstNodeMath*>(  //
 // Currently unhandled nodes - see corresponding AstToDfg functions
 // LCOV_EXCL_START
 template <>
-AstCCast* makeNode<AstCCast, DfgCCast, AstNodeMath*>(const DfgCCast* vtxp, AstNodeMath*) {
+AstCCast* makeNode<AstCCast, DfgCCast, AstNodeExpr*>(const DfgCCast* vtxp, AstNodeExpr*) {
     vtxp->v3fatalSrc("not implemented");
 }
 template <>
-AstAtoN* makeNode<AstAtoN, DfgAtoN, AstNodeMath*>(const DfgAtoN* vtxp, AstNodeMath*) {
+AstAtoN* makeNode<AstAtoN, DfgAtoN, AstNodeExpr*>(const DfgAtoN* vtxp, AstNodeExpr*) {
     vtxp->v3fatalSrc("not implemented");
 }
 template <>
 AstCompareNN*
-makeNode<AstCompareNN, DfgCompareNN, AstNodeMath*, AstNodeMath*>(const DfgCompareNN* vtxp,
-                                                                 AstNodeMath*, AstNodeMath*) {
+makeNode<AstCompareNN, DfgCompareNN, AstNodeExpr*, AstNodeExpr*>(const DfgCompareNN* vtxp,
+                                                                 AstNodeExpr*, AstNodeExpr*) {
     vtxp->v3fatalSrc("not implemented");
 }
 template <>
-AstSliceSel* makeNode<AstSliceSel, DfgSliceSel, AstNodeMath*, AstNodeMath*, AstNodeMath*>(
-    const DfgSliceSel* vtxp, AstNodeMath*, AstNodeMath*, AstNodeMath*) {
+AstSliceSel* makeNode<AstSliceSel, DfgSliceSel, AstNodeExpr*, AstNodeExpr*, AstNodeExpr*>(
+    const DfgSliceSel* vtxp, AstNodeExpr*, AstNodeExpr*, AstNodeExpr*) {
     vtxp->v3fatalSrc("not implemented");
 }
 // LCOV_EXCL_STOP
@@ -130,7 +130,7 @@ class DfgToAstVisitor final : DfgVisitor {
 
     AstModule* const m_modp;  // The parent/result module
     V3DfgOptimizationContext& m_ctx;  // The optimization context for stats
-    AstNodeMath* m_resultp = nullptr;  // The result node of the current traversal
+    AstNodeExpr* m_resultp = nullptr;  // The result node of the current traversal
     // Map from DfgVertex to the AstVar holding the value of that DfgVertex after conversion
     std::unordered_map<const DfgVertex*, AstVar*> m_resultVars;
     // Map from an AstVar, to the canonical AstVar that can be substituted for that AstVar
@@ -212,11 +212,11 @@ class DfgToAstVisitor final : DfgVisitor {
         return varp;
     }
 
-    AstNodeMath* convertDfgVertexToAstNodeMath(DfgVertex* vtxp) {
+    AstNodeExpr* convertDfgVertexToAstNodeExpr(DfgVertex* vtxp) {
         UASSERT_OBJ(!m_resultp, vtxp, "Result already computed");
         iterate(vtxp);
         UASSERT_OBJ(m_resultp, vtxp, "Missing result");
-        AstNodeMath* const resultp = m_resultp;
+        AstNodeExpr* const resultp = m_resultp;
         m_resultp = nullptr;
         return resultp;
     }
@@ -232,11 +232,11 @@ class DfgToAstVisitor final : DfgVisitor {
         return false;
     }
 
-    AstNodeMath* convertSource(DfgVertex* vtxp) {
+    AstNodeExpr* convertSource(DfgVertex* vtxp) {
         if (inlineVertex(*vtxp)) {
             // Inlined vertices are simply recursively converted
             UASSERT_OBJ(vtxp->hasSinks(), vtxp, "Must have one sink: " << vtxp->typeName());
-            return convertDfgVertexToAstNodeMath(vtxp);
+            return convertDfgVertexToAstNodeExpr(vtxp);
         } else {
             // Vertices that are not inlined need a variable, just return a reference
             return new AstVarRef{vtxp->fileline(), getResultVar(vtxp), VAccess::READ};
@@ -249,14 +249,14 @@ class DfgToAstVisitor final : DfgVisitor {
         };
         if (dfgVarp->isDrivenFullyByDfg()) {
             // Whole variable is driven. Render driver and assign directly to whole variable.
-            AstNodeMath* const rhsp = convertDfgVertexToAstNodeMath(dfgVarp->source(0));
+            AstNodeExpr* const rhsp = convertDfgVertexToAstNodeExpr(dfgVarp->source(0));
             addResultEquation(dfgVarp->driverFileLine(0), wRef(), rhsp);
         } else {
             // Variable is driven partially. Render each driver as a separate assignment.
             dfgVarp->forEachSourceEdge([&](const DfgEdge& edge, size_t idx) {
                 UASSERT_OBJ(edge.sourcep(), dfgVarp, "Should have removed undriven sources");
                 // Render the rhs expression
-                AstNodeMath* const rhsp = convertDfgVertexToAstNodeMath(edge.sourcep());
+                AstNodeExpr* const rhsp = convertDfgVertexToAstNodeExpr(edge.sourcep());
                 // Create select LValue
                 FileLine* const flp = dfgVarp->driverFileLine(idx);
                 AstConst* const lsbp = new AstConst{flp, dfgVarp->driverLsb(idx)};
@@ -299,7 +299,7 @@ class DfgToAstVisitor final : DfgVisitor {
         dfgVarp->forEachSourceEdge([&](const DfgEdge& edge, size_t idx) {
             UASSERT_OBJ(edge.sourcep(), dfgVarp, "Should have removed undriven sources");
             // Render the rhs expression
-            AstNodeMath* const rhsp = convertDfgVertexToAstNodeMath(edge.sourcep());
+            AstNodeExpr* const rhsp = convertDfgVertexToAstNodeExpr(edge.sourcep());
             // Create select LValue
             FileLine* const flp = dfgVarp->driverFileLine(idx);
             AstVarRef* const refp = new AstVarRef{flp, dfgVarp->varp(), VAccess::WRITE};
@@ -334,7 +334,7 @@ class DfgToAstVisitor final : DfgVisitor {
 
     void visit(DfgSel* vtxp) override {
         FileLine* const flp = vtxp->fileline();
-        AstNodeMath* const fromp = convertSource(vtxp->fromp());
+        AstNodeExpr* const fromp = convertSource(vtxp->fromp());
         AstConst* const lsbp = new AstConst{flp, vtxp->lsb()};
         AstConst* const widthp = new AstConst{flp, vtxp->width()};
         m_resultp = new AstSel{flp, fromp, lsbp, widthp};
@@ -342,8 +342,8 @@ class DfgToAstVisitor final : DfgVisitor {
 
     void visit(DfgMux* vtxp) override {
         FileLine* const flp = vtxp->fileline();
-        AstNodeMath* const fromp = convertSource(vtxp->fromp());
-        AstNodeMath* const lsbp = convertSource(vtxp->lsbp());
+        AstNodeExpr* const fromp = convertSource(vtxp->fromp());
+        AstNodeExpr* const lsbp = convertSource(vtxp->lsbp());
         AstConst* const widthp = new AstConst{flp, vtxp->width()};
         m_resultp = new AstSel{flp, fromp, lsbp, widthp};
     }
@@ -415,9 +415,9 @@ class DfgToAstVisitor final : DfgVisitor {
                 ++m_ctx.m_intermediateVars;
                 FileLine* const flp = vtxp->fileline();
                 // Just render the logic
-                AstNodeMath* const rhsp = convertDfgVertexToAstNodeMath(vtxp);
+                AstNodeExpr* const rhsp = convertDfgVertexToAstNodeExpr(vtxp);
                 // The lhs is the temporary
-                AstNodeMath* const lhsp = new AstVarRef{flp, resultVarp, VAccess::WRITE};
+                AstNodeExpr* const lhsp = new AstVarRef{flp, resultVarp, VAccess::WRITE};
                 // Add assignment of the value to the variable
                 addResultEquation(flp, lhsp, rhsp);
             }
diff --git a/src/V3DfgOptimizer.cpp b/src/V3DfgOptimizer.cpp
index b162f6819..f093b453d 100644
--- a/src/V3DfgOptimizer.cpp
+++ b/src/V3DfgOptimizer.cpp
@@ -47,7 +47,7 @@ class DataflowExtractVisitor final : public VNVisitor {
 
     // Expressions considered for extraction as separate assignment to gain more opportunities for
     // optimization, together with the list of variables they read.
-    using Candidates = std::vector<std::pair<AstNodeMath*, std::vector<const AstVar*>>>;
+    using Candidates = std::vector<std::pair<AstNodeExpr*, std::vector<const AstVar*>>>;
 
     // Expressions considered for extraction. All the candidates are pure expressions.
     AstUser4Allocator<AstNodeModule, Candidates> m_extractionCandidates;
@@ -65,7 +65,7 @@ class DataflowExtractVisitor final : public VNVisitor {
 
     // Node considered for extraction as a combinational equation. Trace variable usage/purity.
     void iterateExtractionCandidate(AstNode* nodep) {
-        UASSERT_OBJ(!VN_IS(nodep->backp(), NodeMath), nodep,
+        UASSERT_OBJ(!VN_IS(nodep->backp(), NodeExpr), nodep,
                     "Should not try to extract nested expressions (only root expressions)");
 
         // Simple VarRefs should not be extracted, as they only yield trivial assignments.
@@ -93,7 +93,7 @@ class DataflowExtractVisitor final : public VNVisitor {
         if (m_readVars.empty()) return;
 
         // Add to candidate list
-        m_candidatesp->emplace_back(VN_AS(nodep, NodeMath), std::move(m_readVars));
+        m_candidatesp->emplace_back(VN_AS(nodep, NodeExpr), std::move(m_readVars));
     }
 
     // VISIT methods
@@ -110,7 +110,7 @@ class DataflowExtractVisitor final : public VNVisitor {
             if (!VN_IS(modp, Module)) continue;
 
             for (const auto& pair : m_extractionCandidates(modp)) {
-                AstNodeMath* const nodep = pair.first;
+                AstNodeExpr* const nodep = pair.first;
 
                 // Do not extract expressions without any variable references
                 if (pair.second.empty()) continue;
@@ -204,7 +204,7 @@ class DataflowExtractVisitor final : public VNVisitor {
         m_inForceReleaseLhs = false;
     }
 
-    void visit(AstNodeMath* nodep) override { iterateChildrenConst(nodep); }
+    void visit(AstNodeExpr* nodep) override { iterateChildrenConst(nodep); }
 
     void visit(AstNodeVarRef* nodep) override {
         if (nodep->access().isWriteOrRW()) {
@@ -220,7 +220,7 @@ class DataflowExtractVisitor final : public VNVisitor {
 
     void visit(AstNode* nodep) override {
         // Conservatively assume unhandled nodes are impure. This covers all AstNodeFTaskRef
-        // as AstNodeFTaskRef are sadly not AstNodeMath.
+        // as AstNodeFTaskRef are sadly not AstNodeExpr.
         m_impure = true;
         // Still need to gather all references/force/release, etc.
         iterateChildrenConst(nodep);
diff --git a/src/V3EmitCFunc.cpp b/src/V3EmitCFunc.cpp
index f81998976..059e64c65 100644
--- a/src/V3EmitCFunc.cpp
+++ b/src/V3EmitCFunc.cpp
@@ -32,7 +32,7 @@ constexpr int VL_VALUE_STRING_MAX_WIDTH = 8192;
 //######################################################################
 // EmitCFunc
 
-bool EmitCFunc::emitSimpleOk(AstNodeMath* nodep) {
+bool EmitCFunc::emitSimpleOk(AstNodeExpr* nodep) {
     // Can we put out a simple (A + B) instead of VL_ADD_III(A,B)?
     if (nodep->emitSimpleOperator() == "") return false;
     if (nodep->isWide()) return false;
@@ -433,12 +433,7 @@ void EmitCFunc::emitCCallArgs(const AstNodeCCall* nodep, const string& selfPoint
         iterate(subnodep);
         comma = true;
     }
-    if (VN_IS(nodep->backp(), NodeMath) || VN_IS(nodep->backp(), CReturn)) {
-        // We should have a separate CCall for math and statement usage, but...
-        puts(")");
-    } else {
-        puts(");\n");
-    }
+    puts(")");
 }
 
 void EmitCFunc::emitDereference(const string& pointer) {
diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h
index c91ef4174..45f863d21 100644
--- a/src/V3EmitCFunc.h
+++ b/src/V3EmitCFunc.h
@@ -110,15 +110,15 @@ public:
     void reset() { m_emitted.clear(); }
 };
 
-//######################################################################
-// Emit statements and math operators
+// ######################################################################
+//  Emit statements and expressions
 
 class EmitCFunc VL_NOT_FINAL : public EmitCConstInit {
 private:
     AstVarRef* m_wideTempRefp = nullptr;  // Variable that _WW macros should be setting
     int m_labelNum = 0;  // Next label number
     int m_splitSize = 0;  // # of cfunc nodes placed into output file
-    bool m_inUC = false;  // Inside an AstUCStmt or AstUCMath
+    bool m_inUC = false;  // Inside an AstUCStmt or AstUCExpr
     bool m_emitConstInit = false;  // Emitting constant initializer
 
     // State associated with processing $display style string formatting
@@ -167,7 +167,7 @@ public:
     void displayArg(AstNode* dispp, AstNode** elistp, bool isScan, const string& vfmt, bool ignore,
                     char fmtLetter);
 
-    bool emitSimpleOk(AstNodeMath* nodep);
+    bool emitSimpleOk(AstNodeExpr* nodep);
     void emitIQW(AstNode* nodep) {
         // Other abbrevs: "C"har, "S"hort, "F"loat, "D"ouble, stri"N"g
         puts(nodep->dtypep()->charIQWN());
@@ -330,7 +330,7 @@ public:
             iterateAndNextNull(nodep->lhsp());
             puts(", ");
         } else if (nodep->isWide() && VN_IS(nodep->lhsp(), VarRef)  //
-                   && !VN_IS(nodep->rhsp(), CMath)  //
+                   && !VN_IS(nodep->rhsp(), CExpr)  //
                    && !VN_IS(nodep->rhsp(), CMethodHard)  //
                    && !VN_IS(nodep->rhsp(), VarRef)  //
                    && !VN_IS(nodep->rhsp(), AssocSel)  //
@@ -415,7 +415,6 @@ public:
     void visit(AstCAwait* nodep) override {
         puts("co_await ");
         iterate(nodep->exprp());
-        if (nodep->isStatement()) puts(";\n");
     }
     void visit(AstCNew* nodep) override {
         bool comma = false;
@@ -446,10 +445,6 @@ public:
             comma = true;
         }
         puts(")");
-        // Some are statements some are math.
-        if (nodep->isStatement()) puts(";\n");
-        UASSERT_OBJ(!nodep->isStatement() || VN_IS(nodep->dtypep(), VoidDType), nodep,
-                    "Statement of non-void data type");
     }
     void visit(AstLambdaArgRef* nodep) override { putbs(nodep->nameProtect()); }
     void visit(AstWith* nodep) override {
@@ -804,6 +799,10 @@ public:
         iterateAndNextNull(nodep->lhsp());
         puts(")");
     }
+    void visit(AstStmtExpr* node) override {
+        iterate(node->exprp());
+        puts(";\n");
+    }
     void visit(AstJumpBlock* nodep) override {
         nodep->labelNum(++m_labelNum);
         puts("{\n");  // Make it visually obvious label jumps outside these
@@ -931,7 +930,7 @@ public:
         putbs("");
         iterateAndNextNull(nodep->exprsp());
     }
-    void visit(AstCMath* nodep) override {
+    void visit(AstCExpr* nodep) override {
         putbs("");
         iterateAndNextNull(nodep->exprsp());
     }
diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp
index 2d00e01a9..163e408ba 100644
--- a/src/V3EmitMk.cpp
+++ b/src/V3EmitMk.cpp
@@ -26,8 +26,8 @@
 
 VL_DEFINE_DEBUG_FUNCTIONS;
 
-//######################################################################
-// Emit statements and math operators
+// ######################################################################
+//  Emit statements and expressions
 
 class EmitMk final {
 public:
diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp
index 3b2d6a3fd..02f658334 100644
--- a/src/V3EmitV.cpp
+++ b/src/V3EmitV.cpp
@@ -28,8 +28,8 @@
 
 VL_DEFINE_DEBUG_FUNCTIONS;
 
-//######################################################################
-// Emit statements and math operators
+// ######################################################################
+//  Emit statements and expressions
 
 class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor {
     // MEMBERS
@@ -381,6 +381,10 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor {
     }
     void visit(AstStop* nodep) override { putfs(nodep, "$stop;\n"); }
     void visit(AstFinish* nodep) override { putfs(nodep, "$finish;\n"); }
+    void visit(AstStmtExpr* nodep) override {
+        iterate(nodep->exprp());
+        puts(";\n");
+    }
     void visit(AstNodeSimpleText* nodep) override {
         if (nodep->tracking() || m_trackText) {
             puts(nodep->text());
@@ -405,8 +409,8 @@ class EmitVBaseVisitor VL_NOT_FINAL : public EmitCBaseVisitor {
         iterateAndNextConstNull(nodep->exprsp());
         puts(");\n");
     }
-    void visit(AstCMath* nodep) override {
-        putfs(nodep, "$_CMATH(");
+    void visit(AstCExpr* nodep) override {
+        putfs(nodep, "$_CEXPR(");
         iterateAndNextConstNull(nodep->exprsp());
         puts(");\n");
     }
diff --git a/src/V3EmitXml.cpp b/src/V3EmitXml.cpp
index 7d1df2878..17a35a426 100644
--- a/src/V3EmitXml.cpp
+++ b/src/V3EmitXml.cpp
@@ -28,8 +28,8 @@
 
 VL_DEFINE_DEBUG_FUNCTIONS;
 
-//######################################################################
-// Emit statements and math operators
+// ######################################################################
+//  Emit statements and expressions
 
 class EmitXmlFileVisitor final : public VNVisitor {
     // NODE STATE
diff --git a/src/V3Expand.cpp b/src/V3Expand.cpp
index 7bba5f825..d7d957654 100644
--- a/src/V3Expand.cpp
+++ b/src/V3Expand.cpp
@@ -828,10 +828,6 @@ private:
 
     void visit(AstNodeStmt* nodep) override {
         if (nodep->user1SetOnce()) return;  // Process once
-        if (!nodep->isStatement()) {
-            iterateChildren(nodep);
-            return;
-        }
         m_stmtp = nodep;
         iterateChildren(nodep);
         m_stmtp = nullptr;
diff --git a/src/V3Force.cpp b/src/V3Force.cpp
index a1c136f6b..3c3b1c5de 100644
--- a/src/V3Force.cpp
+++ b/src/V3Force.cpp
@@ -104,7 +104,7 @@ class ForceConvertVisitor final : public VNVisitor {
                 AstVarRef* const lhsp = new AstVarRef{flp, m_enVscp, VAccess::WRITE};
                 V3Number zero{m_enVscp, m_enVscp->width()};
                 zero.setAllBits0();
-                AstNodeMath* const rhsp = new AstConst{flp, zero};
+                AstNodeExpr* const rhsp = new AstConst{flp, zero};
                 AstAssign* const assignp = new AstAssign{flp, lhsp, rhsp};
                 AstActive* const activep = new AstActive{
                     flp, "force-init",
diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp
index cb5a1f498..628465602 100644
--- a/src/V3Gate.cpp
+++ b/src/V3Gate.cpp
@@ -185,8 +185,8 @@ public:
     }
 };
 
-//######################################################################
-// Is this a simple math expression with a single input and single output?
+// ######################################################################
+//  Is this a simple expression with a single input and single output?
 
 class GateOkVisitor final : public VNVisitor {
 private:
@@ -801,7 +801,7 @@ private:
         // comparing AstActive nodes, which are very likely not to compare equals (and for the
         // purposes of V3Gate, we probably only care about them either being identical instances,
         // or having the same sensitivities anyway, so if this becomes a problem, it can be
-        // improved which should also speed things up), and AstNodeMath for if conditions, which
+        // improved which should also speed things up), and AstNodeExpr for if conditions, which
         // are hopefully small, and to be safe they should probably be only considered same when
         // identical instances (otherwise if writing the condition between 2 ifs don't really
         // merge).
diff --git a/src/V3Hasher.cpp b/src/V3Hasher.cpp
index 681c68c92..2916d70cf 100644
--- a/src/V3Hasher.cpp
+++ b/src/V3Hasher.cpp
@@ -183,8 +183,8 @@ private:
     }
 
     //------------------------------------------------------------
-    // AstNodeMath
-    void visit(AstNodeMath* nodep) override {
+    // AstNodeExpr
+    void visit(AstNodeExpr* nodep) override {
         m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {});
     }
     void visit(AstConst* nodep) override {
diff --git a/src/V3HierBlock.cpp b/src/V3HierBlock.cpp
index a5f2fa38a..5f4754925 100644
--- a/src/V3HierBlock.cpp
+++ b/src/V3HierBlock.cpp
@@ -296,7 +296,7 @@ class HierBlockUsageCollectVisitor final : public VNVisitor {
         if (nodep->isGParam() && nodep->overriddenParam()) m_gparams.push_back(nodep);
     }
 
-    void visit(AstNodeMath*) override {}  // Accelerate
+    void visit(AstNodeExpr*) override {}  // Accelerate
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp
index 3b0214adb..8d0eb3b6d 100644
--- a/src/V3Inline.cpp
+++ b/src/V3Inline.cpp
@@ -691,7 +691,7 @@ private:
         cellp->addIntfRefsp(new AstIntfRef(varlp->fileline(), alias));
     }
     //--------------------
-    void visit(AstNodeMath*) override {}  // Accelerate
+    void visit(AstNodeExpr*) override {}  // Accelerate
     void visit(AstNodeStmt*) override {}  // Accelerate
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp
index 328318dc5..2de50c0b6 100644
--- a/src/V3Inst.cpp
+++ b/src/V3Inst.cpp
@@ -124,7 +124,7 @@ private:
     }
 
     // Save some time
-    void visit(AstNodeMath*) override {}
+    void visit(AstNodeExpr*) override {}
     void visit(AstNodeAssign*) override {}
     void visit(AstAlways*) override {}
 
@@ -153,7 +153,7 @@ private:
         }
         iterateChildren(nodep);
     }
-    void visit(AstNodeMath*) override {}  // Accelerate
+    void visit(AstNodeExpr*) override {}  // Accelerate
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
@@ -473,7 +473,7 @@ private:
     }
 
     //--------------------
-    void visit(AstNodeMath*) override {}  // Accelerate
+    void visit(AstNodeExpr*) override {}  // Accelerate
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
diff --git a/src/V3Life.cpp b/src/V3Life.cpp
index 1c4bea7df..d1a3ff617 100644
--- a/src/V3Life.cpp
+++ b/src/V3Life.cpp
@@ -441,7 +441,7 @@ private:
         m_sideEffect = true;  // If appears on assign RHS, don't ever delete the assignment
         iterateChildren(nodep);
     }
-    void visit(AstCMath* nodep) override {
+    void visit(AstCExpr* nodep) override {
         m_sideEffect = true;  // If appears on assign RHS, don't ever delete the assignment
         iterateChildren(nodep);
     }
@@ -494,7 +494,7 @@ private:
     }
     void visit(AstVar*) override {}  // Accelerate
     void visit(AstNodeStmt*) override {}  // Accelerate
-    void visit(AstNodeMath*) override {}  // Accelerate
+    void visit(AstNodeExpr*) override {}  // Accelerate
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 3ed4bd599..6659a4662 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -2915,6 +2915,7 @@ private:
                                     outp = AstNode::addNext(outp, addp);
                                 }
                                 newp = new AstSysIgnore(nodep->fileline(), outp);
+                                newp->dtypep(nodep->dtypep());
                             }
                             nodep->replaceWith(newp);
                             VL_DO_DANGLING(nodep->deleteTree(), nodep);
diff --git a/src/V3LinkInc.cpp b/src/V3LinkInc.cpp
index 56a7512a8..6f1fe68f0 100644
--- a/src/V3LinkInc.cpp
+++ b/src/V3LinkInc.cpp
@@ -175,10 +175,6 @@ private:
         m_insStmtp = nullptr;
     }
     void visit(AstNodeStmt* nodep) override {
-        if (!nodep->isStatement()) {
-            iterateChildren(nodep);
-            return;
-        }
         m_insMode = IM_BEFORE;
         m_insStmtp = nodep;
         iterateChildren(nodep);
diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp
index 03cb0abf0..fdcfb1f80 100644
--- a/src/V3LinkResolve.cpp
+++ b/src/V3LinkResolve.cpp
@@ -499,7 +499,7 @@ private:
         if (nodep->modp()->modPublic()) m_modp->modPublic(true);
         //** No iteration for speed
     }
-    void visit(AstNodeMath*) override {}  // Accelerate
+    void visit(AstNodeExpr*) override {}  // Accelerate
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
diff --git a/src/V3Order.cpp b/src/V3Order.cpp
index 88283587b..450ecd583 100644
--- a/src/V3Order.cpp
+++ b/src/V3Order.cpp
@@ -1242,9 +1242,10 @@ AstActive* OrderProcess::processMoveOneLogic(const OrderLogicVertex* lvertexp,
             scopep->addBlocksp(newFuncpr);
             // Create top call to it
             AstCCall* const callp = new AstCCall{nodep->fileline(), newFuncpr};
+            callp->dtypeSetVoid();
             // Where will we be adding the call?
             AstActive* const newActivep = new AstActive{nodep->fileline(), name, domainp};
-            newActivep->addStmtsp(callp);
+            newActivep->addStmtsp(callp->makeStmt());
             if (!activep) {
                 activep = newActivep;
             } else {
diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp
index a9106d549..18744fffc 100644
--- a/src/V3Partition.cpp
+++ b/src/V3Partition.cpp
@@ -3186,8 +3186,9 @@ static void addThreadStartToExecGraph(AstExecGraph* const execGraphp,
         } else {
             // The last will run on the main thread.
             AstCCall* const callp = new AstCCall(fl, funcp);
+            callp->dtypeSetVoid();
             callp->argTypes("vlSelf, vlSymsp->__Vm_even_cycle__" + tag);
-            execGraphp->addStmtsp(callp);
+            execGraphp->addStmtsp(callp->makeStmt());
             addStrStmt("Verilated::mtaskId(0);\n");
         }
     }
diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp
index 5411dbf07..d38eff5e3 100644
--- a/src/V3Premit.cpp
+++ b/src/V3Premit.cpp
@@ -46,7 +46,7 @@ constexpr int STATIC_CONST_MIN_WIDTH = 256;  // Minimum size to extract to stati
 class PremitVisitor final : public VNVisitor {
 private:
     // NODE STATE
-    //  AstNodeMath::user()     -> bool.  True if iterated already
+    //  AstNodeExpr::user()     -> bool.  True if iterated already
     //  AstShiftL::user2()      -> bool.  True if converted to conditional
     //  AstShiftR::user2()      -> bool.  True if converted to conditional
     //  *::user3()              -> Used when visiting AstNodeAssign
@@ -56,6 +56,7 @@ private:
     // STATE
     AstCFunc* m_cfuncp = nullptr;  // Current block
     AstNode* m_stmtp = nullptr;  // Current statement
+    AstCCall* m_callp = nullptr;  // Current AstCCall
     AstWhile* m_inWhilep = nullptr;  // Inside while loop, special statement additions
     AstTraceInc* m_inTracep = nullptr;  // Inside while loop, special statement additions
     bool m_assignLhs = false;  // Inside assignment lhs, don't breakup extracts
@@ -89,8 +90,7 @@ private:
                            && VN_AS(nodep->backp(), Sel)->widthp() == nodep) {
                     // AstSel::width must remain a constant
                 } else if ((nodep->firstAbovep() && VN_IS(nodep->firstAbovep(), ArraySel))
-                           || ((VN_IS(m_stmtp, CCall) || VN_IS(m_stmtp, CStmt))
-                               && VN_IS(nodep, ArraySel))) {
+                           || ((m_callp || VN_IS(m_stmtp, CStmt)) && VN_IS(nodep, ArraySel))) {
                     // ArraySel's are pointer refs, ignore
                 } else {
                     UINFO(4, "Cre Temp: " << nodep << endl);
@@ -208,10 +208,6 @@ private:
         m_stmtp = nullptr;
     }
     void visit(AstNodeStmt* nodep) override {
-        if (!nodep->isStatement()) {
-            iterateChildren(nodep);
-            return;
-        }
         UINFO(4, "  STMT  " << nodep << endl);
         startStatement(nodep);
         iterateChildren(nodep);
@@ -337,6 +333,11 @@ private:
         }
         checkNode(nodep);
     }
+    void visit(AstCCall* nodep) override {
+        VL_RESTORER(m_callp);
+        m_callp = nodep;
+        iterateChildren(nodep);
+    }
 
     // Autoflush
     void visit(AstDisplay* nodep) override {
diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index 3677a1071..385d50b3e 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -172,7 +172,7 @@ private:
             }
             return stmtsp;
         } else {
-            AstNodeMath* valp;
+            AstNodeExpr* valp;
             if (auto* const enumDtp = VN_CAST(memberp ? memberp->subDTypep()->subDTypep()
                                                       : varrefp->dtypep()->subDTypep(),
                                               EnumDType)) {
diff --git a/src/V3Reloop.cpp b/src/V3Reloop.cpp
index db48e6b2e..00d3bfc68 100644
--- a/src/V3Reloop.cpp
+++ b/src/V3Reloop.cpp
@@ -252,7 +252,7 @@ private:
     }
     //--------------------
     void visit(AstVar*) override {}  // Accelerate
-    void visit(AstNodeMath*) override {}  // Accelerate
+    void visit(AstNodeExpr*) override {}  // Accelerate
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp
index 50f8f12ea..52b7adce5 100644
--- a/src/V3Sched.cpp
+++ b/src/V3Sched.cpp
@@ -146,7 +146,8 @@ void splitCheck(AstCFunc* ofuncp) {
             ofuncp->scopep()->addBlocksp(funcp);
             //
             AstCCall* const callp = new AstCCall{funcp->fileline(), funcp};
-            ofuncp->addStmtsp(callp);
+            callp->dtypeSetVoid();
+            ofuncp->addStmtsp(callp->makeStmt());
             func_stmts = 0;
         }
         funcp->addStmtsp(itemp);
@@ -215,7 +216,9 @@ void orderSequentially(AstCFunc* funcp, const LogicByScope& lbs) {
         subFuncp->slow(funcp->slow());
         scopep->addBlocksp(subFuncp);
         // Call it from the top function
-        funcp->addStmtsp(new AstCCall{scopep->fileline(), subFuncp});
+        AstCCall* const callp = new AstCCall{scopep->fileline(), subFuncp};
+        callp->dtypeSetVoid();
+        funcp->addStmtsp(callp->makeStmt());
         return subFuncp;
     };
     const VNUser1InUse user1InUse;  // AstScope -> AstCFunc: the sub-function for the scope
@@ -506,7 +509,9 @@ const TriggerKit createTriggers(AstNetlist* netlistp, AstCFunc* const initFuncp,
         const auto add = [&](const string& text) { blockp->addText(flp, text, true); };
         add("#ifdef VL_DEBUG\n");
         add("if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {\n");
-        blockp->addNodesp(new AstCCall{flp, dumpp});
+        AstCCall* const callp = new AstCCall{flp, dumpp};
+        callp->dtypeSetVoid();
+        blockp->addNodesp(callp->makeStmt());
         add("}\n");
         add("#endif\n");
     }
@@ -520,8 +525,8 @@ const TriggerKit createTriggers(AstNetlist* netlistp, AstCFunc* const initFuncp,
 //============================================================================
 // Helpers to construct an evaluation loop.
 
-AstNode* buildLoop(AstNetlist* netlistp, const string& name,
-                   const std::function<void(AstVarScope*, AstWhile*)>& build)  //
+AstNodeStmt* buildLoop(AstNetlist* netlistp, const string& name,
+                       const std::function<void(AstVarScope*, AstWhile*)>& build)  //
 {
     AstTopScope* const topScopep = netlistp->topScopep();
     AstScope* const scopeTopp = topScopep->scopep();
@@ -529,7 +534,7 @@ AstNode* buildLoop(AstNetlist* netlistp, const string& name,
     // Create the loop condition variable
     AstVarScope* const condp = scopeTopp->createTemp("__V" + name + "Continue", 1);
     // Initialize the loop condition variable to true
-    AstNode* const resp = setVar(condp, 1);
+    AstNodeStmt* const resp = setVar(condp, 1);
     // Add the loop
     AstWhile* const loopp = new AstWhile{flp, new AstVarRef{flp, condp, VAccess::READ}};
     resp->addNext(loopp);
@@ -541,11 +546,11 @@ AstNode* buildLoop(AstNetlist* netlistp, const string& name,
     return resp;
 };
 
-std::pair<AstVarScope*, AstNode*> makeEvalLoop(AstNetlist* netlistp, const string& tag,
-                                               const string& name, AstVarScope* trigVscp,
-                                               AstCFunc* trigDumpp,
-                                               std::function<AstNode*()> computeTriggers,
-                                               std::function<AstNode*()> makeBody) {
+std::pair<AstVarScope*, AstNodeStmt*> makeEvalLoop(AstNetlist* netlistp, const string& tag,
+                                                   const string& name, AstVarScope* trigVscp,
+                                                   AstCFunc* trigDumpp,
+                                                   std::function<AstNodeStmt*()> computeTriggers,
+                                                   std::function<AstNodeStmt*()> makeBody) {
     UASSERT_OBJ(trigVscp->dtypep()->basicp()->isTriggerVec(), trigVscp, "Not TRIGGERVEC");
     AstTopScope* const topScopep = netlistp->topScopep();
     AstScope* const scopeTopp = topScopep->scopep();
@@ -553,7 +558,7 @@ std::pair<AstVarScope*, AstNode*> makeEvalLoop(AstNetlist* netlistp, const strin
 
     AstVarScope* const counterp = scopeTopp->createTemp("__V" + tag + "IterCount", 32);
 
-    AstNode* nodep = setVar(counterp, 0);
+    AstNodeStmt* nodep = setVar(counterp, 0);
     nodep->addNext(buildLoop(netlistp, tag, [&](AstVarScope* continuep, AstWhile* loopp) {
         // Compute triggers
         loopp->addStmtsp(computeTriggers());
@@ -572,7 +577,7 @@ std::pair<AstVarScope*, AstNode*> makeEvalLoop(AstNetlist* netlistp, const strin
                 AstVarRef* const refp = new AstVarRef{flp, counterp, VAccess::READ};
                 AstConst* const constp = new AstConst{flp, AstConst::DTyped{}, counterp->dtypep()};
                 constp->num().setLong(limit);
-                AstNodeMath* const condp = new AstGt{flp, refp, constp};
+                AstNodeExpr* const condp = new AstGt{flp, refp, constp};
                 AstIf* const failp = new AstIf{flp, condp};
                 failp->branchPred(VBranchPred::BP_UNLIKELY);
                 ifp->addThensp(failp);
@@ -583,7 +588,9 @@ std::pair<AstVarScope*, AstNode*> makeEvalLoop(AstNetlist* netlistp, const strin
                 const string& line = cvtToStr(locp->lineno());
                 const auto add = [&](const string& text) { blockp->addText(flp, text, true); };
                 add("#ifdef VL_DEBUG\n");
-                blockp->addNodesp(new AstCCall{flp, trigDumpp});
+                AstCCall* const callp = new AstCCall{flp, trigDumpp};
+                callp->dtypeSetVoid();
+                blockp->addNodesp(callp->makeStmt());
                 add("#endif\n");
                 add("VL_FATAL_MT(\"" + file + "\", " + line + ", \"\", ");
                 add("\"" + name + " region did not converge.\");\n");
@@ -651,10 +658,14 @@ void createSettle(AstNetlist* netlistp, AstCFunc* const initFuncp, SenExprBuilde
     const auto& pair = makeEvalLoop(
         netlistp, "stl", "Settle", trig.m_vscp, trig.m_dumpp,
         [&]() {  // Trigger
-            return new AstCCall{stlFuncp->fileline(), trig.m_funcp};
+            AstCCall* const callp = new AstCCall{stlFuncp->fileline(), trig.m_funcp};
+            callp->dtypeSetVoid();
+            return callp->makeStmt();
         },
         [&]() {  // Body
-            return new AstCCall{stlFuncp->fileline(), stlFuncp};
+            AstCCall* const callp = new AstCCall{stlFuncp->fileline(), stlFuncp};
+            callp->dtypeSetVoid();
+            return callp->makeStmt();
         });
 
     // Add the first iteration trigger to the trigger computation function
@@ -735,10 +746,14 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp,
     const auto& pair = makeEvalLoop(
         netlistp, "ico", "Input combinational", trig.m_vscp, trig.m_dumpp,
         [&]() {  // Trigger
-            return new AstCCall{icoFuncp->fileline(), trig.m_funcp};
+            AstCCall* const callp = new AstCCall{icoFuncp->fileline(), trig.m_funcp};
+            callp->dtypeSetVoid();
+            return callp->makeStmt();
         },
         [&]() {  // Body
-            return new AstCCall{icoFuncp->fileline(), icoFuncp};
+            AstCCall* const callp = new AstCCall{icoFuncp->fileline(), icoFuncp};
+            callp->dtypeSetVoid();
+            return callp->makeStmt();
         });
 
     // Add the first iteration trigger to the trigger computation function
@@ -785,19 +800,28 @@ void createEval(AstNetlist* netlistp,  //
     });
 
     // Create the active eval loop
-    AstNode* const activeEvalLoopp
+    AstNodeStmt* const activeEvalLoopp
         = makeEvalLoop(
               netlistp, "act", "Active", actTrig.m_vscp, actTrig.m_dumpp,
               [&]() {  // Trigger
-                  AstNode* const resultp = new AstCCall{flp, actTrig.m_funcp};
-                  // Commit trigger awaits from the previous iteration
-                  if (AstNode* const commitp = timingKit.createCommit(netlistp)) {
-                      resultp->addNext(commitp);
+                  AstNodeStmt* resultp = nullptr;
+
+                  // Compute the current triggers
+                  {
+                      AstCCall* const trigsp = new AstCCall{flp, actTrig.m_funcp};
+                      trigsp->dtypeSetVoid();
+                      resultp = AstNode::addNext(resultp, trigsp->makeStmt());
                   }
+
+                  // Commit trigger awaits from the previous iteration
+                  if (AstCCall* const commitp = timingKit.createCommit(netlistp)) {
+                      resultp = AstNode::addNext(resultp, commitp->makeStmt());
+                  }
+
                   return resultp;
               },
               [&]() {  // Body
-                  AstNode* resultp = nullptr;
+                  AstNodeStmt* resultp = nullptr;
 
                   // Compute the pre triggers
                   {
@@ -806,9 +830,8 @@ void createEval(AstNetlist* netlistp,  //
                       AstVarRef* const opbp = new AstVarRef{flp, nbaTrigsp, VAccess::READ};
                       opap->addNext(opbp);
                       AstCMethodHard* const callp = new AstCMethodHard{flp, lhsp, "andNot", opap};
-                      callp->statement(true);
                       callp->dtypeSetVoid();
-                      resultp = AstNode::addNext(resultp, callp);
+                      resultp = AstNode::addNext(resultp, callp->makeStmt());
                   }
 
                   // Latch the active trigger flags under the NBA trigger flags
@@ -816,42 +839,48 @@ void createEval(AstNetlist* netlistp,  //
                       AstVarRef* const lhsp = new AstVarRef{flp, nbaTrigsp, VAccess::WRITE};
                       AstVarRef* const argp = new AstVarRef{flp, actTrig.m_vscp, VAccess::READ};
                       AstCMethodHard* const callp = new AstCMethodHard{flp, lhsp, "set", argp};
-                      callp->statement(true);
                       callp->dtypeSetVoid();
-                      resultp = AstNode::addNext(resultp, callp);
+                      resultp = AstNode::addNext(resultp, callp->makeStmt());
                   }
 
                   // Resume triggered timing schedulers
-                  if (AstNode* const resumep = timingKit.createResume(netlistp)) {
-                      resultp = AstNode::addNext(resultp, resumep);
+                  if (AstCCall* const resumep = timingKit.createResume(netlistp)) {
+                      resultp = AstNode::addNext(resultp, resumep->makeStmt());
                   }
 
                   // Invoke body function
-                  return AstNode::addNext(resultp, new AstCCall{flp, actFuncp});
+                  {
+                      AstCCall* const callp = new AstCCall{flp, actFuncp};
+                      callp->dtypeSetVoid();
+                      return AstNode::addNext(resultp, callp->makeStmt());
+                  }
+
+                  return resultp;
               })
               .second;
 
     // Create the NBA eval loop. This uses the Active eval loop in the trigger section.
-    AstNode* const nbaEvalLoopp
+    AstNodeStmt* const nbaEvalLoopp
         = makeEvalLoop(
               netlistp, "nba", "NBA", nbaTrigsp, nbaDumpp,
               [&]() {  // Trigger
-                  AstNode* resultp = nullptr;
+                  AstNodeStmt* resultp = nullptr;
 
                   // Reset NBA triggers
                   {
                       AstVarRef* const refp = new AstVarRef{flp, nbaTrigsp, VAccess::WRITE};
                       AstCMethodHard* const callp = new AstCMethodHard{flp, refp, "clear"};
-                      callp->statement(true);
                       callp->dtypeSetVoid();
-                      resultp = AstNode::addNext(resultp, callp);
+                      resultp = AstNode::addNext(resultp, callp->makeStmt());
                   }
 
                   // Run the Active eval loop
                   return AstNode::addNext(resultp, activeEvalLoopp);
               },
               [&]() {  // Body
-                  return new AstCCall{flp, nbaFuncp};
+                  AstCCall* const callp = new AstCCall{flp, nbaFuncp};
+                  callp->dtypeSetVoid();
+                  return callp->makeStmt();
               })
               .second;
 
@@ -859,7 +888,11 @@ void createEval(AstNetlist* netlistp,  //
     funcp->addStmtsp(nbaEvalLoopp);
 
     // Add the Postponed eval call
-    if (postponedFuncp) funcp->addStmtsp(new AstCCall{flp, postponedFuncp});
+    if (postponedFuncp) {
+        AstCCall* const callp = new AstCCall{flp, postponedFuncp};
+        callp->dtypeSetVoid();
+        funcp->addStmtsp(callp->makeStmt());
+    }
 }
 
 }  // namespace
diff --git a/src/V3SchedTiming.cpp b/src/V3SchedTiming.cpp
index de8845b43..4bf3de0c7 100644
--- a/src/V3SchedTiming.cpp
+++ b/src/V3SchedTiming.cpp
@@ -75,7 +75,9 @@ AstCCall* TimingKit::createResume(AstNetlist* const netlistp) {
             m_resumeFuncp->addStmtsp(activep);
         }
     }
-    return new AstCCall{m_resumeFuncp->fileline(), m_resumeFuncp};
+    AstCCall* const callp = new AstCCall{m_resumeFuncp->fileline(), m_resumeFuncp};
+    callp->dtypeSetVoid();
+    return callp;
 }
 
 //============================================================================
@@ -85,7 +87,7 @@ AstCCall* TimingKit::createCommit(AstNetlist* const netlistp) {
     if (!m_commitFuncp) {
         for (auto& p : m_lbs) {
             AstActive* const activep = p.second;
-            auto* const resumep = VN_AS(activep->stmtsp(), CMethodHard);
+            auto* const resumep = VN_AS(VN_AS(activep->stmtsp(), StmtExpr)->exprp(), CMethodHard);
             UASSERT_OBJ(!resumep->nextp(), resumep, "Should be the only statement here");
             AstVarScope* const schedulerp = VN_AS(resumep->fromp(), VarRef)->varScopep();
             UASSERT_OBJ(schedulerp->dtypep()->basicp()->isDelayScheduler()
@@ -117,15 +119,16 @@ AstCCall* TimingKit::createCommit(AstNetlist* const netlistp) {
             auto* const commitp = new AstCMethodHard{
                 flp, new AstVarRef{flp, schedulerp, VAccess::READWRITE}, "commit"};
             if (resumep->pinsp()) commitp->addPinsp(resumep->pinsp()->cloneTree(false));
-            commitp->statement(true);
             commitp->dtypeSetVoid();
-            newactp->addStmtsp(commitp);
+            newactp->addStmtsp(commitp->makeStmt());
             m_commitFuncp->addStmtsp(newactp);
         }
         // We still haven't created a commit function (no trigger schedulers), return null
         if (!m_commitFuncp) return nullptr;
     }
-    return new AstCCall{m_commitFuncp->fileline(), m_commitFuncp};
+    AstCCall* const callp = new AstCCall{m_commitFuncp->fileline(), m_commitFuncp};
+    callp->dtypeSetVoid();
+    return callp;
 }
 
 //============================================================================
@@ -161,18 +164,17 @@ TimingKit prepareTiming(AstNetlist* const netlistp) {
             // Create a resume() call on the timing scheduler
             auto* const resumep = new AstCMethodHard{
                 flp, new AstVarRef{flp, schedulerp, VAccess::READWRITE}, "resume"};
-            resumep->statement(true);
             resumep->dtypeSetVoid();
             if (schedulerp->dtypep()->basicp()->isTriggerScheduler()) {
                 if (methodp->pinsp()) resumep->addPinsp(methodp->pinsp()->cloneTree(false));
             } else if (schedulerp->dtypep()->basicp()->isDynamicTriggerScheduler()) {
                 auto* const postp = resumep->cloneTree(false);
                 postp->name("doPostUpdates");
-                m_postUpdatesr = AstNode::addNext(m_postUpdatesr, postp);
+                m_postUpdatesr = AstNode::addNext(m_postUpdatesr, postp->makeStmt());
             }
             // Put it in an active and put that in the global resume function
             auto* const activep = new AstActive{flp, "_timing", sensesp};
-            activep->addStmtsp(resumep);
+            activep->addStmtsp(resumep->makeStmt());
             m_lbs.emplace_back(m_scopeTopp, activep);
         }
 
@@ -216,7 +218,7 @@ TimingKit prepareTiming(AstNetlist* const netlistp) {
         }
 
         //--------------------
-        void visit(AstNodeMath*) override {}  // Accelerate
+        void visit(AstNodeExpr*) override {}  // Accelerate
         void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
     public:
@@ -278,10 +280,12 @@ void transformForks(AstNetlist* const netlistp) {
                     // If it's fork..join, we can refer to variables from the parent process
                     if (!m_funcp->user1SetOnce()) {  // Only do this once per function
                         // Move all locals to the heap before the fork
-                        auto* const awaitp = new AstCAwait{
-                            m_forkp->fileline(), new AstCStmt{m_forkp->fileline(), "VlNow{}"}};
-                        awaitp->statement(true);
-                        m_forkp->addHereThisAsNext(awaitp);
+                        AstCExpr* const nowp
+                            = new AstCExpr{m_forkp->fileline(), "VlNow{}", 0, true};
+                        nowp->dtypeSetVoid();  // TODO: this is sloppy but harmless
+                        AstCAwait* const awaitp = new AstCAwait{m_forkp->fileline(), nowp};
+                        awaitp->dtypeSetVoid();
+                        m_forkp->addHereThisAsNext(awaitp->makeStmt());
                     }
                 } else {
                     refp->v3warn(E_UNSUPPORTED, "Unsupported: variable local to a forking process "
@@ -353,8 +357,9 @@ void transformForks(AstNetlist* const netlistp) {
                 newfuncp->isConst(m_funcp->isConst());
                 newfuncp->declPrivate(true);
                 // Replace the begin with a call to the newly created function
-                auto* const callp = new AstCCall{flp, newfuncp};
-                nodep->replaceWith(callp);
+                AstCCall* const callp = new AstCCall{flp, newfuncp};
+                callp->dtypeSetVoid();
+                nodep->replaceWith(callp->makeStmt());
                 // If we're in a class, add a vlSymsp arg
                 if (m_inClass) {
                     newfuncp->addInitsp(new AstCStmt{nodep->fileline(), "VL_KEEP_THIS;\n"});
@@ -376,7 +381,7 @@ void transformForks(AstNetlist* const netlistp) {
         }
 
         //--------------------
-        void visit(AstNodeMath*) override {}  // Accelerate
+        void visit(AstNodeExpr*) override {}  // Accelerate
         void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
     public:
diff --git a/src/V3SenExprBuilder.h b/src/V3SenExprBuilder.h
index 97b31e5b2..81e189d83 100644
--- a/src/V3SenExprBuilder.h
+++ b/src/V3SenExprBuilder.h
@@ -141,8 +141,7 @@ class SenExprBuilder final {
             if (AstUnpackArrayDType* const dtypep = VN_CAST(exprp->dtypep(), UnpackArrayDType)) {
                 AstCMethodHard* const cmhp = new AstCMethodHard{flp, wrPrev(), "assign", rdCurr()};
                 cmhp->dtypeSetVoid();
-                cmhp->statement(true);
-                m_postUpdates.push_back(cmhp);
+                m_postUpdates.push_back(cmhp->makeStmt());
             } else {
                 m_postUpdates.push_back(new AstAssign{flp, wrPrev(), rdCurr()});
             }
@@ -157,7 +156,7 @@ class SenExprBuilder final {
 
         const auto currp = [=]() { return getCurr(senp); };
         const auto prevp = [=]() { return new AstVarRef{flp, getPrev(senp), VAccess::READ}; };
-        const auto lsb = [=](AstNodeMath* opp) { return new AstSel{flp, opp, 0, 1}; };
+        const auto lsb = [=](AstNodeExpr* opp) { return new AstSel{flp, opp, 0, 1}; };
 
         // All event signals should be 1-bit at this point
         switch (senItemp->edgeType()) {
@@ -188,9 +187,8 @@ class SenExprBuilder final {
 
                 // Clear 'fired' state when done
                 AstCMethodHard* const clearp = new AstCMethodHard{flp, currp(), "clearFired"};
-                ifp->addThensp(clearp);
                 clearp->dtypeSetVoid();
-                clearp->statement(true);
+                ifp->addThensp(clearp->makeStmt());
 
                 // Enqueue for clearing 'triggered' state on next eval
                 AstTextBlock* const blockp = new AstTextBlock{flp};
diff --git a/src/V3SplitAs.cpp b/src/V3SplitAs.cpp
index 1d7b4d86d..52810f33c 100644
--- a/src/V3SplitAs.cpp
+++ b/src/V3SplitAs.cpp
@@ -86,10 +86,6 @@ private:
         }
     }
     void visit(AstNodeStmt* nodep) override {
-        if (!nodep->isStatement()) {
-            iterateChildren(nodep);
-            return;
-        }
         UINFO(6, "     CL STMT " << nodep << endl);
         const bool oldKeep = m_keepStmt;
         {
@@ -179,8 +175,7 @@ private:
         }
     }
 
-    // Speedup; no always under math
-    void visit(AstNodeMath*) override {}
+    void visit(AstNodeExpr*) override {}  // Accelerate
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp
index 7b82c3f46..1b90d3384 100644
--- a/src/V3SplitVar.cpp
+++ b/src/V3SplitVar.cpp
@@ -405,7 +405,7 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
     VarSet m_foundTargetVar;
     UnpackRefMap m_refs;
     AstNodeModule* m_modp = nullptr;
-    // AstNodeStmt, AstCell, AstNodeFTaskRef, or AstAlways(Public) for sensitivity
+    // AstNodeStmt, AstCell, or AstAlways(Public) for sensitivity
     AstNode* m_contextp = nullptr;
     const AstNodeFTask* m_inFTask = nullptr;
     size_t m_numSplit = 0;
@@ -492,38 +492,34 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
         }
     }
     void visit(AstNodeFTaskRef* nodep) override {
-        VL_RESTORER(m_contextp);
-        {
-            m_contextp = nodep;
-            const AstNodeFTask* const ftaskp = nodep->taskp();
-            UASSERT_OBJ(ftaskp, nodep, "Unlinked");
-            // Iterate arguments of a function/task.
-            for (AstNode *argp = nodep->pinsp(), *paramp = ftaskp->stmtsp(); argp;
-                 argp = argp->nextp(), paramp = paramp ? paramp->nextp() : nullptr) {
-                const char* reason = nullptr;
-                const AstVar* vparamp = nullptr;
-                while (paramp) {
-                    vparamp = VN_CAST(paramp, Var);
-                    if (vparamp && vparamp->isIO()) {
-                        reason = cannotSplitVarDirectionReason(vparamp->direction());
-                        break;
-                    }
-                    paramp = paramp->nextp();
-                    vparamp = nullptr;
+        const AstNodeFTask* const ftaskp = nodep->taskp();
+        UASSERT_OBJ(ftaskp, nodep, "Unlinked");
+        // Iterate arguments of a function/task.
+        for (AstNode *argp = nodep->pinsp(), *paramp = ftaskp->stmtsp(); argp;
+             argp = argp->nextp(), paramp = paramp ? paramp->nextp() : nullptr) {
+            const char* reason = nullptr;
+            const AstVar* vparamp = nullptr;
+            while (paramp) {
+                vparamp = VN_CAST(paramp, Var);
+                if (vparamp && vparamp->isIO()) {
+                    reason = cannotSplitVarDirectionReason(vparamp->direction());
+                    break;
                 }
-                if (!reason && !vparamp) {
-                    reason = "the number of argument to the task/function mismatches";
-                }
-                m_foundTargetVar.clear();
-                iterate(argp);
-                if (reason) {
-                    for (AstVar* const varp : m_foundTargetVar) {
-                        warnNoSplit(varp, argp, reason);
-                        m_refs.remove(varp);
-                    }
-                }
-                m_foundTargetVar.clear();
+                paramp = paramp->nextp();
+                vparamp = nullptr;
             }
+            if (!reason && !vparamp) {
+                reason = "the number of argument to the task/function mismatches";
+            }
+            m_foundTargetVar.clear();
+            iterate(argp);
+            if (reason) {
+                for (AstVar* const varp : m_foundTargetVar) {
+                    warnNoSplit(varp, argp, reason);
+                    m_refs.remove(varp);
+                }
+            }
+            m_foundTargetVar.clear();
         }
     }
     void visit(AstPin* nodep) override {
@@ -605,12 +601,6 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
             iterateChildren(nodep);
         }
     }
-    AstNode* toInsertPoint(AstNode* insertp) {
-        if (const AstNodeStmt* const stmtp = VN_CAST(insertp, NodeStmt)) {
-            if (!stmtp->isStatement()) insertp = stmtp->backp();
-        }
-        return insertp;
-    }
     AstVarRef* createTempVar(AstNode* context, AstNode* nodep, AstUnpackArrayDType* dtypep,
                              const std::string& name_prefix, std::vector<AstVar*>& vars,
                              int start_idx, bool lvalue, bool /*ftask*/) {
@@ -640,7 +630,7 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
             if (!lvalue) std::swap(lhsp, rhsp);
             AstNode* newassignp;
             if (use_simple_assign) {
-                AstNode* const insertp = toInsertPoint(context);
+                AstNode* const insertp = context;
                 newassignp = new AstAssign{fl, lhsp, rhsp};
                 if (lvalue) {
                     // If varp is LHS, this assignment must appear after the original
@@ -662,7 +652,6 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
     }
     void connectPort(AstVar* varp, std::vector<AstVar*>& vars, AstNode* insertp) {
         UASSERT_OBJ(varp->isIO(), varp, "must be port");
-        insertp = insertp ? toInsertPoint(insertp) : nullptr;
         const bool lvalue = varp->direction().isWritable();
         FileLine* const fl = varp->fileline();
         for (size_t i = 0; i < vars.size(); ++i) {
@@ -1055,9 +1044,7 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
     static void connectPortAndVar(const std::vector<SplitNewVar>& vars, AstVar* portp,
                                   AstNode* insertp) {
         for (; insertp; insertp = insertp->backp()) {
-            if (const AstNodeStmt* const stmtp = VN_CAST(insertp, NodeStmt)) {
-                if (stmtp->isStatement()) break;
-            }
+            if (VN_IS(insertp, NodeStmt)) break;
         }
         const bool in = portp->isReadOnly();
         FileLine* const fl = portp->fileline();
diff --git a/src/V3Task.cpp b/src/V3Task.cpp
index 0d1eb2c22..fea8d97c1 100644
--- a/src/V3Task.cpp
+++ b/src/V3Task.cpp
@@ -552,10 +552,12 @@ private:
             cnewpr = cnewp;
         } else if (const AstMethodCall* const mrefp = VN_CAST(refp, MethodCall)) {
             ccallp = new AstCMethodCall(refp->fileline(), mrefp->fromp()->unlinkFrBack(), cfuncp);
-            beginp->addNext(ccallp);
+            ccallp->dtypeSetVoid();
+            beginp->addNext(ccallp->makeStmt());
         } else {
             ccallp = new AstCCall(refp->fileline(), cfuncp);
-            beginp->addNext(ccallp);
+            ccallp->dtypeSetVoid();
+            beginp->addNext(ccallp->makeStmt());
         }
 
         // Convert complicated outputs to temp signals
@@ -617,7 +619,7 @@ private:
             UASSERT_OBJ(snp, refp, "Missing scoping context");
             ccallp->addArgsp(snp);
             // __Vfilenamep
-            ccallp->addArgsp(new AstCMath(refp->fileline(),
+            ccallp->addArgsp(new AstCExpr(refp->fileline(),
                                           "\"" + refp->fileline()->filename() + "\"", 64, true));
             // __Vlineno
             ccallp->addArgsp(new AstConst(refp->fileline(), refp->fileline()->lineno()));
@@ -701,7 +703,7 @@ private:
         string frstmt;
         string ket;
         const bool useSetWSvlv = TaskDpiUtils::dpiToInternalFrStmt(portp, frName, frstmt, ket);
-        // Use a AstCMath, as we want V3Clean to mask off bits that don't make sense.
+        // Use a AstCExpr, as we want V3Clean to mask off bits that don't make sense.
         int cwidth = VL_IDATASIZE;
         if (!useSetWSvlv && portp->basicp()) {
             if (portp->basicp()->keyword().isBitLogic()) {
@@ -743,7 +745,7 @@ private:
                 }
                 from += ket;
                 AstNode* const rhsp = new AstSel(
-                    portp->fileline(), new AstCMath(portp->fileline(), from, cwidth, false), 0,
+                    portp->fileline(), new AstCExpr(portp->fileline(), from, cwidth, false), 0,
                     portp->width());
                 stmtp = new AstAssign(portp->fileline(), srcp, rhsp);
             }
@@ -1039,8 +1041,9 @@ private:
                 cfuncp->addStmtsp(new AstText(nodep->fileline(), stmt, /* tracking: */ true));
             }
             AstCCall* const callp = new AstCCall(nodep->fileline(), dpiFuncp);
+            callp->dtypeSetVoid();
             callp->argTypes(args);
-            cfuncp->addStmtsp(callp);
+            cfuncp->addStmtsp(callp->makeStmt());
         }
 
         // Convert output/inout arguments back to internal type
@@ -1401,30 +1404,26 @@ private:
             beginp = createInlinedFTask(nodep, namePrefix, outvscp);
         }
         // Replace the ref
-        AstNode* visitp = nullptr;
+        AstNode* const visitp = insertBeforeStmt(nodep, beginp);
+
         if (VN_IS(nodep, New)) {
-            UASSERT_OBJ(!nodep->isStatement(), nodep, "new is non-stmt");
             UASSERT_OBJ(cnewp, nodep, "didn't create cnew for new");
             nodep->replaceWith(cnewp);
-            visitp = insertBeforeStmt(nodep, beginp);
-        } else if (!nodep->isStatement()) {
+            VL_DO_DANGLING(nodep->deleteTree(), nodep);
+        } else if (!VN_IS(nodep->backp(), StmtExpr)) {
             UASSERT_OBJ(nodep->taskp()->isFunction(), nodep, "func reference to non-function");
             AstVarRef* const outrefp = new AstVarRef(nodep->fileline(), outvscp, VAccess::READ);
             nodep->replaceWith(outrefp);
-            // Insert new statements
-            visitp = insertBeforeStmt(nodep, beginp);
+            VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else {
             if (nodep->taskp()->isFunction()) {
                 nodep->v3warn(
                     IGNOREDRETURN,
                     "Ignoring return value of non-void function (IEEE 1800-2017 13.4.1)");
             }
-            // outvscp maybe non-nullptr if calling a function in a taskref,
-            // but if so we want to ignore the function result
-            nodep->replaceWith(beginp);
+            nodep->unlinkFrBack();
+            VL_DO_DANGLING(nodep->deleteTree(), nodep);
         }
-        // Cleanup
-        VL_DO_DANGLING(nodep->deleteTree(), nodep);
         UINFO(4, "  FTask REF Done.\n");
         // Visit nodes that normal iteration won't find
         if (visitp) iterateAndNextNull(visitp);
@@ -1519,15 +1518,18 @@ private:
             "For statements should have been converted to while statements in V3Begin.cpp");
     }
     void visit(AstNodeStmt* nodep) override {
-        if (!nodep->isStatement()) {
-            iterateChildren(nodep);
-            return;
-        }
         m_insMode = IM_BEFORE;
         m_insStmtp = nodep;
         iterateChildren(nodep);
         m_insStmtp = nullptr;  // Next thing should be new statement
     }
+    void visit(AstStmtExpr* nodep) override {
+        m_insMode = IM_BEFORE;
+        m_insStmtp = nodep;
+        iterateChildren(nodep);
+        if (!nodep->exprp()) VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
+        m_insStmtp = nullptr;  // Next thing should be new statement
+    }
     void visit(AstSenItem* nodep) override {
         UASSERT_OBJ(!m_inSensesp, nodep, "Senitem under senitem?");
         VL_RESTORER(m_inSensesp);
diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp
index 8f657e0b0..85549de04 100644
--- a/src/V3Timing.cpp
+++ b/src/V3Timing.cpp
@@ -341,9 +341,8 @@ private:
         auto* const donep = new AstCMethodHard{
             beginp->fileline(), new AstVarRef{flp, forkVscp, VAccess::WRITE}, "done"};
         donep->dtypeSetVoid();
-        donep->statement(true);
         addDebugInfo(donep);
-        beginp->addStmtsp(donep);
+        beginp->addStmtsp(donep->makeStmt());
     }
     // Handle the 'join' part of a fork..join
     void makeForkJoin(AstFork* const forkp) {
@@ -364,16 +363,15 @@ private:
         auto* const initp = new AstCMethodHard{flp, new AstVarRef{flp, forkVscp, VAccess::WRITE},
                                                "init", new AstConst{flp, joinCount}};
         initp->dtypeSetVoid();
-        initp->statement(true);
-        forkp->addHereThisAsNext(initp);
+        forkp->addHereThisAsNext(initp->makeStmt());
         // Await the join at the end
         auto* const joinp
             = new AstCMethodHard{flp, new AstVarRef{flp, forkVscp, VAccess::WRITE}, "join"};
         joinp->dtypeSetVoid();
         addDebugInfo(joinp);
-        auto* const awaitp = new AstCAwait{flp, joinp};
-        awaitp->statement(true);
-        forkp->addNextHere(awaitp);
+        AstCAwait* const awaitp = new AstCAwait{flp, joinp};
+        awaitp->dtypeSetVoid();
+        forkp->addNextHere(awaitp->makeStmt());
     }
 
     // VISITORS
@@ -476,7 +474,9 @@ private:
         if (nodep->funcp()->user2()) {  // If suspendable
             VNRelinker relinker;
             nodep->unlinkFrBack(&relinker);
-            relinker.relink(new AstCAwait{nodep->fileline(), nodep});
+            AstCAwait* const awaitp = new AstCAwait{nodep->fileline(), nodep};
+            awaitp->dtypeSetVoid();
+            relinker.relink(awaitp);
         } else {
             // Add our process/func as the CFunc's dependency as we might have to put an await here
             DependencyVertex* const procVxp = getDependencyVertex(m_procp);
@@ -515,13 +515,15 @@ private:
         delayMethodp->dtypeSetVoid();
         addDebugInfo(delayMethodp);
         // Create the co_await
-        auto* const awaitp = new AstCAwait{flp, delayMethodp, getCreateDelaySenTree()};
-        awaitp->statement(true);
+        AstCAwait* const awaitp = new AstCAwait{flp, delayMethodp, getCreateDelaySenTree()};
+        awaitp->dtypeSetVoid();
+        AstStmtExpr* const awaitStmtp = awaitp->makeStmt();
         // Relink child statements after the co_await
         if (nodep->stmtsp()) {
-            AstNode::addNext<AstNode, AstNode>(awaitp, nodep->stmtsp()->unlinkFrBackWithNext());
+            AstNode::addNext<AstNode, AstNode>(awaitStmtp,
+                                               nodep->stmtsp()->unlinkFrBackWithNext());
         }
-        nodep->replaceWith(awaitp);
+        nodep->replaceWith(awaitStmtp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
     void visit(AstEventControl* nodep) override {
@@ -552,9 +554,9 @@ private:
             auto* const sensesp = nodep->sensesp();
             addEventDebugInfo(evalMethodp, sensesp);
             // Create the co_await
-            auto* const awaitEvalp
+            AstCAwait* const awaitEvalp
                 = new AstCAwait{flp, evalMethodp, getCreateDynamicTriggerSenTree()};
-            awaitEvalp->statement(true);
+            awaitEvalp->dtypeSetVoid();
             // Construct the sen expression for this sentree
             SenExprBuilder senExprBuilder{m_scopep};
             auto* const assignp = new AstAssign{flp, new AstVarRef{flp, trigvscp, VAccess::WRITE},
@@ -568,8 +570,9 @@ private:
             }
             // Create the trigger eval loop, which will await the evaluation step and check the
             // trigger
-            auto* const loopp = new AstWhile{
-                flp, new AstLogNot{flp, new AstVarRef{flp, trigvscp, VAccess::READ}}, awaitEvalp};
+            AstWhile* const loopp = new AstWhile{
+                flp, new AstLogNot{flp, new AstVarRef{flp, trigvscp, VAccess::READ}},
+                awaitEvalp->makeStmt()};
             // Put pre updates before the trigger check and assignment
             for (AstNodeStmt* const stmtp : senExprBuilder.getAndClearPreUpdates()) {
                 loopp->addStmtsp(stmtp);
@@ -579,18 +582,18 @@ private:
             // If the post update is destructive (e.g. event vars are cleared), create an await for
             // the post update step
             if (destructivePostUpdate(sensesp)) {
-                auto* const awaitPostUpdatep = awaitEvalp->cloneTree(false);
+                AstCAwait* const awaitPostUpdatep = awaitEvalp->cloneTree(false);
                 VN_AS(awaitPostUpdatep->exprp(), CMethodHard)->name("postUpdate");
-                loopp->addStmtsp(awaitPostUpdatep);
+                loopp->addStmtsp(awaitPostUpdatep->makeStmt());
             }
             // Put the post updates at the end of the loop
             for (AstNodeStmt* const stmtp : senExprBuilder.getAndClearPostUpdates()) {
                 loopp->addStmtsp(stmtp);
             }
             // Finally, await the resumption step in 'act'
-            auto* const awaitResumep = awaitEvalp->cloneTree(false);
+            AstCAwait* const awaitResumep = awaitEvalp->cloneTree(false);
             VN_AS(awaitResumep->exprp(), CMethodHard)->name("resumption");
-            AstNode::addNext<AstNode, AstNode>(loopp, awaitResumep);
+            AstNode::addNext<AstNodeStmt, AstNodeStmt>(loopp, awaitResumep->makeStmt());
             // Replace the event control with the loop
             nodep->replaceWith(loopp);
         } else {
@@ -605,9 +608,9 @@ private:
             triggerMethodp->dtypeSetVoid();
             addEventDebugInfo(triggerMethodp, sensesp);
             // Create the co_await
-            auto* const awaitp = new AstCAwait{flp, triggerMethodp, sensesp};
-            awaitp->statement(true);
-            nodep->replaceWith(awaitp);
+            AstCAwait* const awaitp = new AstCAwait{flp, triggerMethodp, sensesp};
+            awaitp->dtypeSetVoid();
+            nodep->replaceWith(awaitp->makeStmt());
         }
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
@@ -700,9 +703,11 @@ private:
             if (constp->isZero()) {
                 // We have to await forever instead of simply returning in case we're deep in a
                 // callstack
-                auto* const awaitp = new AstCAwait{flp, new AstCStmt{flp, "VlForever{}"}};
-                awaitp->statement(true);
-                nodep->replaceWith(awaitp);
+                AstCExpr* const foreverp = new AstCExpr{flp, "VlForever{}", 0, true};
+                foreverp->dtypeSetVoid();  // TODO: this is sloppy but harmless
+                AstCAwait* const awaitp = new AstCAwait{flp, foreverp};
+                awaitp->dtypeSetVoid();
+                nodep->replaceWith(awaitp->makeStmt());
                 if (stmtsp) VL_DO_DANGLING(stmtsp->deleteTree(), stmtsp);
             } else if (stmtsp) {
                 // Just put the statements there
@@ -760,7 +765,7 @@ private:
     }
 
     //--------------------
-    void visit(AstNodeMath*) override {}  // Accelerate
+    void visit(AstNodeExpr*) override {}  // Accelerate
     void visit(AstVar*) override {}
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp
index 89703a67f..aaf13244a 100644
--- a/src/V3Trace.cpp
+++ b/src/V3Trace.cpp
@@ -163,7 +163,7 @@ private:
     //  AstCFunc::user1()               // V3GraphVertex* for this node
     //  AstTraceDecl::user1()           // V3GraphVertex* for this node
     //  AstVarScope::user1()            // V3GraphVertex* for this node
-    //  AstCCall::user2()               // bool; walked next list for other ccalls
+    //  AstStmtExpr::user2()            // bool; walked next list for other ccalls
     //  Ast*::user3()                   // TraceActivityVertex* for this node
     const VNUser1InUse m_inuser1;
     const VNUser2InUse m_inuser2;
@@ -429,13 +429,15 @@ private:
         FileLine* const fl = insertp->fileline();
         AstAssign* const setterp = new AstAssign(fl, selectActivity(fl, code, VAccess::WRITE),
                                                  new AstConst(fl, AstConst::BitTrue()));
-        if (AstCCall* const callp = VN_CAST(insertp, CCall)) {
-            callp->addNextHere(setterp);
+        if (AstStmtExpr* const stmtp = VN_CAST(insertp, StmtExpr)) {
+            stmtp->addNextHere(setterp);
         } else if (AstCFunc* const funcp = VN_CAST(insertp, CFunc)) {
             // If there are awaits, insert the setter after each await
             if (funcp->isCoroutine() && funcp->stmtsp()) {
                 funcp->stmtsp()->foreachAndNext([&](AstCAwait* awaitp) {
-                    if (awaitp->nextp()) awaitp->addNextHere(setterp->cloneTree(false));
+                    AstNode* stmtp = awaitp->backp();
+                    while (VN_IS(stmtp, NodeExpr)) stmtp = stmtp->backp();
+                    if (stmtp->nextp()) stmtp->addNextHere(setterp->cloneTree(false));
                 });
             }
             funcp->addStmtsp(setterp);
@@ -550,8 +552,9 @@ private:
             }
             // Add call to top function
             AstCCall* const callp = new AstCCall(funcp->fileline(), funcp);
+            callp->dtypeSetVoid();
             callp->argTypes("bufp");
-            topFuncp->addStmtsp(callp);
+            topFuncp->addStmtsp(callp->makeStmt());
         }
         // Done
         UINFO(5, "  newCFunc " << funcp << endl);
@@ -822,20 +825,24 @@ private:
         if (nodep->isTop()) m_topModp = nodep;
         iterateChildren(nodep);
     }
-    void visit(AstCCall* nodep) override {
-        UINFO(8, "   CCALL " << nodep << endl);
+    void visit(AstStmtExpr* nodep) override {
         if (!m_finding && !nodep->user2()) {
-            // See if there are other calls in same statement list;
-            // If so, all funcs might share the same activity code
-            TraceActivityVertex* const activityVtxp
-                = getActivityVertexp(nodep, nodep->funcp()->slow());
-            for (AstNode* nextp = nodep; nextp; nextp = nextp->nextp()) {
-                if (AstCCall* const ccallp = VN_CAST(nextp, CCall)) {
-                    ccallp->user2(true);  // Processed
-                    UINFO(8, "     SubCCALL " << ccallp << endl);
-                    V3GraphVertex* const ccallFuncVtxp = getCFuncVertexp(ccallp->funcp());
-                    activityVtxp->slow(ccallp->funcp()->slow());
-                    new V3GraphEdge(&m_graph, activityVtxp, ccallFuncVtxp, 1);
+            if (AstCCall* const callp = VN_CAST(nodep->exprp(), CCall)) {
+                UINFO(8, "   CCALL " << callp << endl);
+                // See if there are other calls in same statement list;
+                // If so, all funcs might share the same activity code
+                TraceActivityVertex* const activityVtxp
+                    = getActivityVertexp(nodep, callp->funcp()->slow());
+                for (AstNode* nextp = nodep; nextp; nextp = nextp->nextp()) {
+                    if (AstStmtExpr* const stmtp = VN_CAST(nextp, StmtExpr)) {
+                        if (AstCCall* const ccallp = VN_CAST(stmtp->exprp(), CCall)) {
+                            stmtp->user2(true);  // Processed
+                            UINFO(8, "     SubCCALL " << ccallp << endl);
+                            V3GraphVertex* const ccallFuncVtxp = getCFuncVertexp(ccallp->funcp());
+                            activityVtxp->slow(ccallp->funcp()->slow());
+                            new V3GraphEdge(&m_graph, activityVtxp, ccallFuncVtxp, 1);
+                        }
+                    }
                 }
             }
         }
diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp
index 41db6e5ab..aab284fc3 100644
--- a/src/V3TraceDecl.cpp
+++ b/src/V3TraceDecl.cpp
@@ -489,8 +489,9 @@ public:
             // Call all sub functions for this path
             for (AstCFunc* const subFuncp : item.second) {
                 AstCCall* const callp = new AstCCall{flp, subFuncp};
+                callp->dtypeSetVoid();
                 callp->argTypes("tracep");
-                addToTopFunc(callp);
+                addToTopFunc(callp->makeStmt());
             }
         }
         pathAdjustor.unwind();
@@ -503,8 +504,9 @@ public:
             AstCFunc* const topFuncp = newCFunc(flp, "");
             for (AstCFunc* funcp : m_topFuncps) {
                 AstCCall* const callp = new AstCCall{flp, funcp};
+                callp->dtypeSetVoid();
                 callp->argTypes("tracep");
-                topFuncp->addStmtsp(callp);
+                topFuncp->addStmtsp(callp->makeStmt());
             }
             m_topFuncps.clear();
             m_topFuncps.push_back(topFuncp);
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index caebfdcd0..a2a966a90 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -308,11 +308,11 @@ private:
     // Widths: out width = lhs width = rhs width
     // Signed: Output signed iff LHS & RHS signed.
     // Real: Not allowed
-    void visit(AstAnd* nodep) override { visit_boolmath_and_or(nodep); }
-    void visit(AstOr* nodep) override { visit_boolmath_and_or(nodep); }
-    void visit(AstXor* nodep) override { visit_boolmath_and_or(nodep); }
+    void visit(AstAnd* nodep) override { visit_boolexpr_and_or(nodep); }
+    void visit(AstOr* nodep) override { visit_boolexpr_and_or(nodep); }
+    void visit(AstXor* nodep) override { visit_boolexpr_and_or(nodep); }
     void visit(AstBufIf1* nodep) override {
-        visit_boolmath_and_or(nodep);
+        visit_boolexpr_and_or(nodep);
     }  // Signed behavior changing in 3.814
     // Width: Max(Lhs,Rhs) sort of.
     // Real: If either side real
@@ -2856,12 +2856,12 @@ private:
             if (!nodep->pinsp()) {
                 newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                           "clear"};
-                newp->makeStatement();
+                newp->dtypeSetVoid();
             } else {
                 AstNode* const index_exprp = methodCallWildcardIndexExpr(nodep, adtypep);
                 newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                           "erase", index_exprp->unlinkFrBack()};
-                newp->makeStatement();
+                newp->dtypeSetVoid();
             }
         } else if (nodep->name() == "sort" || nodep->name() == "rsort"
                    || nodep->name() == "reverse" || nodep->name() == "shuffle") {
@@ -2878,14 +2878,14 @@ private:
             newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       "r_" + nodep->name(), withp};
             newp->dtypeFrom(withp ? withp->dtypep() : adtypep->subDTypep());
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "min" || nodep->name() == "max" || nodep->name() == "unique") {
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
             newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name()};
             newp->dtypeFrom(adtypep);
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "find" || nodep->name() == "find_first"
                    || nodep->name() == "find_last") {
             AstWith* const withp
@@ -2896,7 +2896,7 @@ private:
             newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name(), withp};
             newp->dtypeFrom(adtypep);
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else {
             nodep->v3error("Unknown wildcard associative array method " << nodep->prettyNameQ());
             nodep->dtypeFrom(adtypep->subDTypep());  // Best guess
@@ -2926,7 +2926,7 @@ private:
                                       nodep->name(),  // first/last/next/prev
                                       index_exprp->unlinkFrBack());
             newp->dtypeSetSigned32();
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "exists") {  // function int exists(input index)
             // IEEE really should have made this a "bit" return
             methodOkArguments(nodep, 1, 1);
@@ -2941,12 +2941,12 @@ private:
             if (!nodep->pinsp()) {
                 newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                           "clear");
-                newp->makeStatement();
+                newp->dtypeSetVoid();
             } else {
                 AstNode* const index_exprp = methodCallAssocIndexExpr(nodep, adtypep);
                 newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                           "erase", index_exprp->unlinkFrBack());
-                newp->makeStatement();
+                newp->dtypeSetVoid();
             }
         } else if (nodep->name() == "sort" || nodep->name() == "rsort"
                    || nodep->name() == "reverse" || nodep->name() == "shuffle") {
@@ -2962,7 +2962,7 @@ private:
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       "r_" + nodep->name(), withp);
             newp->dtypeFrom(withp ? withp->dtypep() : adtypep->subDTypep());
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "min" || nodep->name() == "max" || nodep->name() == "unique"
                    || nodep->name() == "unique_index") {
             methodOkArguments(nodep, 0, 0);
@@ -2974,7 +2974,7 @@ private:
             } else {
                 newp->dtypeFrom(adtypep);
             }
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "find" || nodep->name() == "find_first"
                    || nodep->name() == "find_last") {
             AstWith* const withp = methodWithArgument(nodep, true, false, nodep->findBitDType(),
@@ -2984,7 +2984,7 @@ private:
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name(), withp);
             newp->dtypeFrom(adtypep);
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "find_index" || nodep->name() == "find_first_index"
                    || nodep->name() == "find_last_index") {
             AstWith* const withp = methodWithArgument(nodep, true, false, nodep->findBitDType(),
@@ -2994,7 +2994,7 @@ private:
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name(), withp);
             newp->dtypep(queueDTypeIndexedBy(adtypep->keyDTypep()));
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else {
             nodep->v3error("Unknown built-in associative array method " << nodep->prettyNameQ());
             nodep->dtypeFrom(adtypep->subDTypep());  // Best guess
@@ -3048,7 +3048,7 @@ private:
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "clear");
-            newp->makeStatement();
+            newp->dtypeSetVoid();
         } else if (nodep->name() == "and" || nodep->name() == "or" || nodep->name() == "xor"
                    || nodep->name() == "sum" || nodep->name() == "product") {
             // All value return
@@ -3060,7 +3060,7 @@ private:
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       "r_" + nodep->name(), withp);
             newp->dtypeFrom(adtypep->subDTypep());
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "reverse" || nodep->name() == "shuffle"
                    || nodep->name() == "sort" || nodep->name() == "rsort") {
             AstWith* withp = nullptr;
@@ -3072,7 +3072,7 @@ private:
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name(), withp);
-            newp->makeStatement();
+            newp->dtypeSetVoid();
         } else if (nodep->name() == "min" || nodep->name() == "max" || nodep->name() == "unique"
                    || nodep->name() == "unique_index") {
             methodOkArguments(nodep, 0, 0);
@@ -3084,7 +3084,7 @@ private:
             } else {
                 newp->dtypeFrom(adtypep);
             }
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "find" || nodep->name() == "find_first"
                    || nodep->name() == "find_last" || nodep->name() == "find_index") {
             AstWith* const withp
@@ -3095,7 +3095,7 @@ private:
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name(), withp);
             newp->dtypeFrom(adtypep);
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "find_index" || nodep->name() == "find_first_index"
                    || nodep->name() == "find_last_index") {
             AstWith* const withp
@@ -3106,7 +3106,7 @@ private:
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name(), withp);
             newp->dtypep(newp->findQueueIndexDType());
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else {
             nodep->v3warn(E_UNSUPPORTED, "Unsupported/unknown built-in dynamic array method "
                                              << nodep->prettyNameQ());
@@ -3137,18 +3137,18 @@ private:
             if (!nodep->pinsp()) {
                 newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                           "clear");
-                newp->makeStatement();
+                newp->dtypeSetVoid();
             } else {
                 AstNode* const index_exprp = methodCallQueueIndexExpr(nodep);
                 if (index_exprp->isZero()) {  // delete(0) is a pop_front
                     newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                               "pop_front");
                     newp->dtypeFrom(adtypep->subDTypep());
-                    newp->makeStatement();
+                    newp->dtypeSetVoid();
                 } else {
                     newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                               "erase", index_exprp->unlinkFrBack());
-                    newp->makeStatement();
+                    newp->dtypeSetVoid();
                 }
             }
         } else if (nodep->name() == "insert") {
@@ -3160,12 +3160,12 @@ private:
             if (index_exprp->isZero()) {  // insert(0, ...) is a push_front
                 newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                           "push_front", argp->exprp()->unlinkFrBack());
-                newp->makeStatement();
+                newp->dtypeSetVoid();
             } else {
                 newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                           nodep->name(), index_exprp->unlinkFrBack());
                 newp->addPinsp(argp->exprp()->unlinkFrBack());
-                newp->makeStatement();
+                newp->dtypeSetVoid();
             }
         } else if (nodep->name() == "pop_front" || nodep->name() == "pop_back") {
             methodOkArguments(nodep, 0, 0);
@@ -3174,9 +3174,7 @@ private:
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name());
             newp->dtypeFrom(adtypep->subDTypep());
-            // Because queue methods pop_front() or pop_back() can be void cast,
-            // they use makeStatement to check if they need the c++ ";" added.
-            if (nodep->isStandaloneBodyStmt()) newp->makeStatement();
+            if (nodep->isStandaloneBodyStmt()) newp->dtypeSetVoid();
         } else if (nodep->name() == "push_back" || nodep->name() == "push_front") {
             methodOkArguments(nodep, 1, 1);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
@@ -3184,7 +3182,7 @@ private:
             iterateCheckTyped(nodep, "push value", argp->exprp(), adtypep->subDTypep(), BOTH);
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name(), argp->exprp()->unlinkFrBack());
-            newp->makeStatement();
+            newp->dtypeSetVoid();
         } else if (nodep->name() == "and" || nodep->name() == "or" || nodep->name() == "xor"
                    || nodep->name() == "sum" || nodep->name() == "product") {
             AstWith* const withp
@@ -3195,7 +3193,7 @@ private:
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       "r_" + nodep->name(), withp);
             newp->dtypeFrom(withp ? withp->dtypep() : adtypep->subDTypep());
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "reverse" || nodep->name() == "shuffle"
                    || nodep->name() == "sort" || nodep->name() == "rsort") {
             AstWith* withp = nullptr;
@@ -3207,7 +3205,7 @@ private:
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name(), withp);
-            newp->makeStatement();
+            newp->dtypeSetVoid();
         } else if (nodep->name() == "min" || nodep->name() == "max" || nodep->name() == "unique"
                    || nodep->name() == "unique_index") {
             methodOkArguments(nodep, 0, 0);
@@ -3219,7 +3217,7 @@ private:
             } else {
                 newp->dtypeFrom(adtypep);
             }
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "find" || nodep->name() == "find_first"
                    || nodep->name() == "find_last") {
             AstWith* const withp
@@ -3230,7 +3228,7 @@ private:
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name(), withp);
             newp->dtypeFrom(adtypep);
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "find_index" || nodep->name() == "find_first_index"
                    || nodep->name() == "find_last_index") {
             AstWith* const withp
@@ -3241,7 +3239,7 @@ private:
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name(), withp);
             newp->dtypep(newp->findQueueIndexDType());
-            if (!nodep->firstAbovep()) newp->makeStatement();
+            if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else {
             nodep->v3warn(E_UNSUPPORTED,
                           "Unsupported/unknown built-in queue method " << nodep->prettyNameQ());
@@ -3289,7 +3287,7 @@ private:
                     nodep->taskp(ftaskp);
                     nodep->dtypeFrom(ftaskp);
                     nodep->classOrPackagep(classp);
-                    if (VN_IS(ftaskp, Task)) nodep->makeStatement();
+                    if (VN_IS(ftaskp, Task)) nodep->dtypeSetVoid();
                     processFTaskRefArgs(nodep);
                 }
                 return;
@@ -3432,8 +3430,8 @@ private:
             AstNode* const newp = new AstAssign(
                 nodep->fileline(), fromp, new AstPutcN(nodep->fileline(), varrefp, rhsp, thsp));
             fromp->access(VAccess::WRITE);
-            nodep->replaceWith(newp);
-            VL_DO_DANGLING(nodep->deleteTree(), nodep);
+            pushDeletep(nodep->backp());
+            VL_DO_DANGLING(nodep->backp()->replaceWith(newp), nodep);
         } else if (nodep->name() == "getc") {
             methodOkArguments(nodep, 1, 1);
             AstArg* const arg0p = VN_AS(nodep->pinsp(), Arg);
@@ -4351,8 +4349,8 @@ private:
             }
             AstMethodCall* const newp = new AstMethodCall{
                 nodep->fileline(), nodep->lhsp()->unlinkFrBack(), "delete", nullptr};
-            newp->makeStatement();
-            nodep->replaceWith(newp);
+            newp->dtypeSetVoid();
+            nodep->replaceWith(newp->makeStmt());
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
             // Need to now convert it
             visit(newp);
@@ -4371,8 +4369,8 @@ private:
             }
             newp->didWidth(true);
             newp->protect(false);
-            newp->makeStatement();
-            nodep->replaceWith(newp);
+            newp->dtypeSetVoid();
+            nodep->replaceWith(newp->makeStmt());
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
             // return;
         }
@@ -4440,8 +4438,8 @@ private:
                         newFormat += "%@";
                         VNRelinker handle;
                         argp->unlinkFrBack(&handle);
-                        AstCMath* const newp
-                            = new AstCMath(nodep->fileline(), "VL_TO_STRING(", 0, true);
+                        AstCExpr* const newp
+                            = new AstCExpr(nodep->fileline(), "VL_TO_STRING(", 0, true);
                         newp->addExprsp(argp);
                         newp->addExprsp(new AstText(nodep->fileline(), ")", true));
                         newp->dtypeSetString();
@@ -5274,7 +5272,7 @@ private:
 
     //--------------------
     // Default
-    void visit(AstNodeMath* nodep) override {
+    void visit(AstNodeExpr* nodep) override {
         if (!nodep->didWidth()) {
             nodep->v3fatalSrc(
                 "Visit function missing? Widthed function missing for math node: " << nodep);
@@ -5623,7 +5621,7 @@ private:
         return nodep;  // May edit
     }
 
-    void visit_boolmath_and_or(AstNodeBiop* nodep) {
+    void visit_boolexpr_and_or(AstNodeBiop* nodep) {
         // CALLER: And, Or, Xor, ...
         // Lint widths: out width = lhs width = rhs width
         // Signed: if lhs & rhs signed
@@ -6452,8 +6450,8 @@ private:
             nodep->fileline(), fromp,
             new AstSFormatF(nodep->fileline(), format, false, argp->exprp()->unlinkFrBack()));
         fromp->access(VAccess::WRITE);
-        nodep->replaceWith(newp);
-        VL_DO_DANGLING(pushDeletep(nodep), nodep);
+        pushDeletep(nodep->backp());
+        VL_DO_DANGLING(nodep->backp()->replaceWith(newp), newp);
     }
 
     //----------------------------------------------------------------------
diff --git a/src/Verilator.cpp b/src/Verilator.cpp
index 9604eb151..536c523da 100644
--- a/src/Verilator.cpp
+++ b/src/Verilator.cpp
@@ -463,7 +463,7 @@ static void process() {
         // Bits between widthMin() and width() are irrelevant, but may be non zero.
         v3Global.widthMinUsage(VWidthMinUsage::VERILOG_WIDTH);
 
-        // Make all math operations either 8, 16, 32 or 64 bits
+        // Make all expressions either 8, 16, 32 or 64 bits
         V3Clean::cleanAll(v3Global.rootp());
 
         // Move wide constants to BLOCK temps / ConstPool.
diff --git a/src/astgen b/src/astgen
index 2c7f847aa..acbb4575e 100755
--- a/src/astgen
+++ b/src/astgen
@@ -1196,7 +1196,7 @@ def write_dfg_dfg_to_ast(filename):
                 "void visit(Dfg{t}* vtxp) override {{\n".format(t=node.name))
             for i in range(node.arity):
                 fh.write(
-                    "    AstNodeMath* const op{j}p = convertSource(vtxp->source<{i}>());\n"
+                    "    AstNodeExpr* const op{j}p = convertSource(vtxp->source<{i}>());\n"
                     .format(i=i, j=i + 1))
             fh.write(
                 "    m_resultp = makeNode<Ast{t}>(vtxp".format(t=node.name))
diff --git a/src/verilog.y b/src/verilog.y
index d7668fffe..28f453728 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1085,6 +1085,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
 //  Blank lines for type insertion
 //  Blank lines for type insertion
 //  Blank lines for type insertion
+//  Blank lines for type insertion
 
 %start source_text
 
@@ -2689,7 +2690,7 @@ genvar_iteration<nodep>:        // ==IEEE: genvar_iteration
         |       varRefBase yP_SRIGHTEQ  expr            { $$ = new AstAssign($2,$1,new AstShiftR ($2,$1->cloneTree(true),$3)); }
         |       varRefBase yP_SSRIGHTEQ expr            { $$ = new AstAssign($2,$1,new AstShiftRS($2,$1->cloneTree(true),$3)); }
         //                      // inc_or_dec_operator
-        // When support ++ as a real AST type, maybe AstWhile::precondsp() becomes generic AstNodeMathStmt?
+        // When support ++ as a real AST type, maybe AstWhile::precondsp() becomes generic AstNodeExprStmt?
         |       yP_PLUSPLUS   varRefBase
                         { $$ = new AstAssign{$1, $2, new AstAdd{$1, $2->cloneTree(true),
                                                                 new AstConst{$1, AstConst::StringToParse{}, "'b1"}}}; }
@@ -3284,23 +3285,27 @@ statement_item<nodep>:          // IEEE: statement_item
                         { $$ = $4;
                           FileLine* const newfl = new FileLine{$$->fileline()};
                           newfl->warnOff(V3ErrorCode::IGNOREDRETURN, true);
-                          $$->fileline(newfl); }
+                          $$->fileline(newfl);
+                          if (AstNodeExpr* const exprp = VN_CAST($$, NodeExpr)) $$ = exprp->makeStmt(); }
         |       yVOID yP_TICK '(' expr '.' task_subroutine_callNoMethod ')' ';'
                         { $$ = new AstDot{$5, false, $4, $6};
                           FileLine* const newfl = new FileLine{$6->fileline()};
                           newfl->warnOff(V3ErrorCode::IGNOREDRETURN, true);
-                          $6->fileline(newfl); }
+                          $6->fileline(newfl);
+                          if (AstNodeExpr* const exprp = VN_CAST($$, NodeExpr)) $$ = exprp->makeStmt(); }
         //                      // Expr included here to resolve our not knowing what is a method call
         //                      // Expr here must result in a subroutine_call
-        |       task_subroutine_callNoMethod ';'        { $$ = $1; }
+        |       task_subroutine_callNoMethod ';'
+                        { $$ = $1;
+                          if (AstNodeExpr* const exprp = VN_CAST($$, NodeExpr)) $$ = exprp->makeStmt(); }
         //UNSUP fexpr '.' array_methodNoRoot ';'        { UNSUP }
-        |       fexpr '.' task_subroutine_callNoMethod ';'      { $$ = new AstDot($<fl>2, false, $1, $3); }
+        |       fexpr '.' task_subroutine_callNoMethod ';'      { $$ = (new AstDot{$<fl>2, false, $1, $3})->makeStmt(); }
         //UNSUP fexprScope ';'                          { UNSUP }
         //                      // Not here in IEEE; from class_constructor_declaration
         //                      // Because we've joined class_constructor_declaration into generic functions
         //                      // Way over-permissive;
         //                      // IEEE: [ ySUPER '.' yNEW [ '(' list_of_arguments ')' ] ';' ]
-        |       fexpr '.' class_new ';'                 { $$ = new AstDot($<fl>2, false, $1, $3); }
+        |       fexpr '.' class_new ';'                 { $$ = (new AstDot{$<fl>2, false, $1, $3})->makeStmt(); }
         //
         |       statementVerilatorPragmas               { $$ = $1; }
         //
@@ -3426,7 +3431,7 @@ foperator_assignment<nodep>:    // IEEE: operator_assignment (for first part of
         //UNSUP BISONPRE_COPY(operator_assignment,{s/~f~/f/g})  // {copied}
         ;
 
-inc_or_dec_expression<nodep>:   // ==IEEE: inc_or_dec_expression
+inc_or_dec_expression<nodeExprp>:   // ==IEEE: inc_or_dec_expression
         //                      // Need fexprScope instead of variable_lvalue to prevent conflict
                 ~l~exprScope yP_PLUSPLUS
                         { $<fl>$ = $<fl>1; $$ = new AstPostAdd{$2, new AstConst{$2, AstConst::StringToParse(), "'b1"}, $1, $1->cloneTree(true)}; }
@@ -3439,7 +3444,7 @@ inc_or_dec_expression<nodep>:   // ==IEEE: inc_or_dec_expression
                         { $<fl>$ = $<fl>1; $$ = new AstPreSub{$1, new AstConst{$1, AstConst::StringToParse(), "'b1"}, $2, $2->cloneTree(true)}; }
         ;
 
-finc_or_dec_expression<nodep>:  // ==IEEE: inc_or_dec_expression
+finc_or_dec_expression<nodeExprp>:  // ==IEEE: inc_or_dec_expression
                 BISONPRE_COPY(inc_or_dec_expression,{s/~l~/f/g})        // {copied}
         ;
 
@@ -3684,14 +3689,14 @@ loop_variables<nodep>:          // IEEE: loop_variables
 //************************************************
 // Functions/tasks
 
-taskRef<nodep>:                 // IEEE: part of tf_call
+taskRef<nodeExprp>:            // IEEE: part of tf_call
                 id                              { $$ = new AstTaskRef($<fl>1,*$1,nullptr); }
         |       id '(' list_of_argumentsE ')'   { $$ = new AstTaskRef($<fl>1,*$1,$3); }
         |       packageClassScope id '(' list_of_argumentsE ')'
                         { $$ = AstDot::newIfPkg($<fl>2, $1, new AstTaskRef($<fl>2, *$2, $4)); }
         ;
 
-funcRef<nodep>:                 // IEEE: part of tf_call
+funcRef<nodeExprp>:             // IEEE: part of tf_call
         //                      // package_scope/hierarchical_... is part of expr, so just need ID
         //                      //      making-a                id-is-a
         //                      //      -----------------       ------------------
@@ -3713,9 +3718,9 @@ task_subroutine_callNoMethod<nodep>:    // function_subroutine_callNoMethod (as
         //                      // IEEE: tf_call
                 taskRef                                 { $$ = $1; }
         //                      // funcref below not task ref to avoid conflict, must later handle either
-        |       funcRef yWITH__PAREN '(' expr ')'       { $$ = new AstWithParse($2, true, $1, $4); }
+        |       funcRef yWITH__PAREN '(' expr ')'       { $$ = new AstWithParse{$2, $1, $4}; }
         //                      // can call as method and yWITH without parenthesis
-        |       id yWITH__PAREN '(' expr ')'            { $$ = new AstWithParse($2, true, new AstFuncRef($<fl>1, *$1, nullptr), $4); }
+        |       id yWITH__PAREN '(' expr ')'            { $$ = new AstWithParse{$2, new AstFuncRef{$<fl>1, *$1, nullptr}, $4}; }
         |       system_t_call                           { $$ = $1; }
         //                      // IEEE: method_call requires a "." so is in expr
         //                      // IEEE: ['std::'] not needed, as normal std package resolution will find it
@@ -3725,12 +3730,12 @@ task_subroutine_callNoMethod<nodep>:    // function_subroutine_callNoMethod (as
         //UNSUP funcRef yWITH__CUR constraint_block     { }
         ;
 
-function_subroutine_callNoMethod<nodep>:        // IEEE: function_subroutine_call (as function)
+function_subroutine_callNoMethod<nodeExprp>:        // IEEE: function_subroutine_call (as function)
         //                      // IEEE: tf_call
                 funcRef                                 { $$ = $1; }
-        |       funcRef yWITH__PAREN '(' expr ')'       { $$ = new AstWithParse($2, false, $1, $4); }
+        |       funcRef yWITH__PAREN '(' expr ')'       { $$ = new AstWithParse{$2, $1, $4}; }
         //                      // can call as method and yWITH without parenthesis
-        |       id yWITH__PAREN '(' expr ')'            { $$ = new AstWithParse($2, false, new AstFuncRef($<fl>1, *$1, nullptr), $4); }
+        |       id yWITH__PAREN '(' expr ')'            { $$ = new AstWithParse{$2, new AstFuncRef{$<fl>1, *$1, nullptr}, $4}; }
         |       system_f_call                           { $$ = $1; }
         //                      // IEEE: method_call requires a "." so is in expr
         //                      // IEEE: ['std::'] not needed, as normal std package resolution will find it
@@ -3739,7 +3744,7 @@ function_subroutine_callNoMethod<nodep>:        // IEEE: function_subroutine_cal
         //                      // Note yNULL is already part of expressions, so they come for free
         |       funcRef yWITH__CUR constraint_block
                         { $$ = $1; BBUNSUP($2, "Unsupported: randomize() 'with' constraint"); }
-        |       funcRef yWITH__CUR '{' '}'              { $$ = new AstWithParse($2, false, $1, nullptr); }
+        |       funcRef yWITH__CUR '{' '}'              { $$ = new AstWithParse{$2, $1, nullptr}; }
         ;
 
 system_t_call<nodep>:           // IEEE: system_tf_call (as task)
@@ -3872,7 +3877,7 @@ system_t_call<nodep>:           // IEEE: system_tf_call (as task)
         |       system_f_call_or_t                      { $$ = new AstSysFuncAsTask($<fl>1, $1); }
         ;
 
-system_f_call<nodep>:           // IEEE: system_tf_call (as func)
+system_f_call<nodeExprp>:           // IEEE: system_tf_call (as func)
                 yaD_PLI systemDpiArgsE                  { $$ = new AstFuncRef($<fl>1, *$1, $2); VN_CAST($$, FuncRef)->pli(true); }
         //
         |       yD_C '(' cStrList ')'                   { $$ = (v3Global.opt.ignc() ? nullptr : new AstUCFunc($1,$3)); }
@@ -3887,7 +3892,7 @@ systemDpiArgsE<nodep>:          // IEEE: part of system_if_call for aruments of
         |       '(' exprList ')'                        { $$ = GRAMMARP->argWrapList($2); }
         ;
 
-system_f_call_or_t<nodep>:      // IEEE: part of system_tf_call (can be task or func)
+system_f_call_or_t<nodeExprp>:      // IEEE: part of system_tf_call (can be task or func)
                 yD_ACOS '(' expr ')'                    { $$ = new AstAcosD($1,$3); }
         |       yD_ACOSH '(' expr ')'                   { $$ = new AstAcoshD($1,$3); }
         |       yD_ASIN '(' expr ')'                    { $$ = new AstAsinD($1,$3); }
@@ -4276,9 +4281,9 @@ array_methodNoRoot<nodeFTaskRefp>:
 array_methodWith<nodep>:
                 array_methodNoRoot parenE               { $$ = $1; }
         |       array_methodNoRoot parenE yWITH__PAREN '(' expr ')'
-                        { $$ = new AstWithParse($3, false, $1, $5); }
+                        { $$ = new AstWithParse{$3, $1, $5}; }
         |       array_methodNoRoot '(' expr ')' yWITH__PAREN '(' expr ')'
-                        { $$ = new AstWithParse($5, false, $1, $7); $1->addPinsp(new AstArg($<fl>3, "", $3)); }
+                        { $$ = new AstWithParse{$5, $1, $7}; $1->addPinsp(new AstArg($<fl>3, "", $3)); }
         ;
 
 dpi_import_export<nodep>:       // ==IEEE: dpi_import_export
@@ -4350,11 +4355,11 @@ exprOrDataTypeEqE<nodep>:       // IEEE: optional '=' expression (part of param_
         |       '=' exprOrDataType                      { $$ = $2; }
         ;
 
-constExpr<nodep>:
+constExpr<nodeExprp>:
                 expr                                    { $$ = $1; }
         ;
 
-expr<nodep>:                    // IEEE: part of expression/constant_expression/primary
+expr<nodeExprp>:                // IEEE: part of expression/constant_expression/primary
         // *SEE BELOW*          // IEEE: primary/constant_primary
         //
         //                      // IEEE: unary_operator primary
@@ -4522,7 +4527,7 @@ expr<nodep>:                    // IEEE: part of expression/constant_expression/
         |       ~l~expr yDIST '{' dist_list '}'         { $$ = $1; BBUNSUP($2, "Unsupported: dist"); }
         ;
 
-fexpr<nodep>:                   // For use as first part of statement (disambiguates <=)
+fexpr<nodeExprp>:                   // For use as first part of statement (disambiguates <=)
                 BISONPRE_COPY(expr,{s/~l~/f/g; s/~r~/f/g; s/~f__IGNORE~/__IGNORE/g;})   // {copied}
         ;
 
@@ -4555,11 +4560,11 @@ fexpr<nodep>:                   // For use as first part of statement (disambigu
 //UNSUP |       '(' event_expression ':' expr ':' expr ')'      { $<fl>$ = $<fl>1; $$ = "(...)"; }
 //UNSUP ;
 
-exprNoStr<nodep>:               // expression with string removed
+exprNoStr<nodeExprp>:               // expression with string removed
                 BISONPRE_COPY(expr,{s/~noStr__IGNORE~/Ignore/g;})       // {copied}
         ;
 
-exprOkLvalue<nodep>:            // expression that's also OK to use as a variable_lvalue
+exprOkLvalue<nodeExprp>:            // expression that's also OK to use as a variable_lvalue
                 ~l~exprScope                            { $$ = $1; }
         //                      // IEEE: concatenation/constant_concatenation
         //                      // Replicate(1) required as otherwise "{a}" would not be self-determined
@@ -4581,7 +4586,7 @@ exprOkLvalue<nodep>:            // expression that's also OK to use as a variabl
         |       streaming_concatenation                 { $$ = $1; }
         ;
 
-fexprOkLvalue<nodep>:           // exprOkLValue, For use as first part of statement (disambiguates <=)
+fexprOkLvalue<nodeExprp>:           // exprOkLValue, For use as first part of statement (disambiguates <=)
                 BISONPRE_COPY(exprOkLvalue,{s/~l~/f/g}) // {copied}
         ;
 
@@ -4601,11 +4606,11 @@ fexprOkLvalue<nodep>:           // exprOkLValue, For use as first part of statem
 //UNSUP         BISONPRE_COPY(exprOkLvalue,{s/~l~/pev_/g})      // {copied}
 //UNSUP ;
 
-fexprLvalue<nodep>:             // For use as first part of statement (disambiguates <=)
+fexprLvalue<nodeExprp>:             // For use as first part of statement (disambiguates <=)
                 fexprOkLvalue                           { $<fl>$ = $<fl>1; $$ = $1; }
         ;
 
-exprScope<nodep>:               // scope and variable for use to inside an expression
+exprScope<nodeExprp>:               // scope and variable for use to inside an expression
         //                      // Here we've split method_call_root | implicit_class_handle | class_scope | package_scope
         //                      // from the object being called and let expr's "." deal with resolving it.
         //                      // (note method_call_root was simplified to require a primary in 1800-2009)
@@ -4624,7 +4629,7 @@ exprScope<nodep>:               // scope and variable for use to inside an expre
         |       ySUPER                                  { $$ = new AstParseRef($<fl>1, VParseRefExp::PX_ROOT, "super"); }
         ;
 
-fexprScope<nodep>:              // exprScope, For use as first part of statement (disambiguates <=)
+fexprScope<nodeExprp>:              // exprScope, For use as first part of statement (disambiguates <=)
                 BISONPRE_COPY(exprScope,{s/~l~/f/g})    // {copied}
         ;
 
@@ -4656,23 +4661,23 @@ cStrList<nodep>:
         |       exprStrText ',' cStrList                { $$ = $1->addNext($3); }
         ;
 
-cateList<nodep>:
+cateList<nodeExprp>:
         //                      // Not just 'expr' to prevent conflict via stream_concOrExprOrType
                 stream_expression                       { $$ = $1; }
         |       cateList ',' stream_expression          { $$ = new AstConcat($2,$1,$3); }
         ;
 
-exprListE<nodep>:
+exprListE<nodeExprp>:
                 /* empty */                             { $$ = nullptr; }
         |       exprList                                { $$ = $1; }
         ;
 
-exprList<nodep>:
+exprList<nodeExprp>:
                 expr                                    { $$ = $1; }
         |       exprList ',' expr                       { $$ = $1->addNext($3); }
         ;
 
-exprDispList<nodep>:            // exprList for within $display
+exprDispList<nodeExprp>:            // exprList for within $display
                 expr                                    { $$ = $1; }
         |       exprDispList ',' expr                   { $$ = $1->addNext($3); }
         //                      // ,, creates a space in $display
@@ -4735,7 +4740,7 @@ argsDotted<nodep>:              // IEEE: part of list_of_arguments
 //UNSUP |       '.' idAny '(' pev_expr ')'              { $$ = new AstArg($<fl>2, *$2, $4); }
 //UNSUP ;
 
-streaming_concatenation<nodep>: // ==IEEE: streaming_concatenation
+streaming_concatenation<nodeExprp>: // ==IEEE: streaming_concatenation
         //                      // Need to disambiguate {<< expr-{ ... expr-} stream_concat }
         //                      // From                 {<< stream-{ ... stream-} }
         //                      // Likewise simple_type's idScoped from constExpr's idScope
@@ -4758,7 +4763,7 @@ stream_concatenation<nodep>:    // ==IEEE: stream_concatenation
                 '{' cateList '}'                        { $$ = $2; }
         ;
 
-stream_expression<nodep>:       // ==IEEE: stream_expression
+stream_expression<nodeExprp>:   // ==IEEE: stream_expression
         //                      // IEEE: array_range_expression expanded below
                 expr                                    { $$ = $1; }
         //UNSUP expr yWITH__BRA '[' expr ']'            { UNSUP }
@@ -5077,7 +5082,7 @@ idSVKwd<strp>:                  // Warn about non-forward compatible Verilog 200
                         { static string s = "final"; $$ = &s; ERRSVKWD($1,*$$); $<fl>$ = $<fl>1; }
         ;
 
-variable_lvalue<nodep>:         // IEEE: variable_lvalue or net_lvalue
+variable_lvalue<nodeExprp>:         // IEEE: variable_lvalue or net_lvalue
         //                      // Note many variable_lvalue's must use exprOkLvalue when arbitrary expressions may also exist
                 idClassSel                              { $$ = $1; }
         |       '{' variable_lvalueConcList '}'         { $$ = $2; }
@@ -5089,7 +5094,7 @@ variable_lvalue<nodep>:         // IEEE: variable_lvalue or net_lvalue
         |       streaming_concatenation                 { $$ = $1; }
         ;
 
-variable_lvalueConcList<nodep>: // IEEE: part of variable_lvalue: '{' variable_lvalue { ',' variable_lvalue } '}'
+variable_lvalueConcList<nodeExprp>: // IEEE: part of variable_lvalue: '{' variable_lvalue { ',' variable_lvalue } '}'
                 variable_lvalue                                 { $$ = $1; }
         |       variable_lvalueConcList ',' variable_lvalue     { $$ = new AstConcat($2,$1,$3); }
         ;
@@ -5100,7 +5105,7 @@ variable_lvalueConcList<nodep>: // IEEE: part of variable_lvalue: '{' variable_l
 //UNSUP ;
 
 // VarRef to dotted, and/or arrayed, and/or bit-ranged variable
-idClassSel<nodep>:                      // Misc Ref to dotted, and/or arrayed, and/or bit-ranged variable
+idClassSel<nodeExprp>:                      // Misc Ref to dotted, and/or arrayed, and/or bit-ranged variable
                 idDotted                                { $$ = $1; }
         //                      // IEEE: [ implicit_class_handle . | package_scope ] hierarchical_variable_identifier select
         |       yTHIS '.' idDotted
@@ -5124,7 +5129,7 @@ idClassSelForeach<nodep>:
         |       packageClassScope idDottedForeach       { $$ = new AstDot($<fl>2, true, $1, $2); }
         ;
 
-idDotted<nodep>:
+idDotted<nodeExprp>:
                 yD_ROOT '.' idDottedMore
                         { $$ = new AstDot($2, false, new AstParseRef($<fl>1, VParseRefExp::PX_ROOT, "$root"), $3); }
         |       idDottedMore                            { $$ = $1; }
@@ -5136,7 +5141,7 @@ idDottedForeach<nodep>:
         |       idDottedMoreForeach                     { $$ = $1; }
         ;
 
-idDottedMore<nodep>:
+idDottedMore<nodeExprp>:
                 idArrayed                               { $$ = $1; }
         |       idDottedMore '.' idArrayed              { $$ = new AstDot($2, false, $1, $3); }
         ;
@@ -5151,7 +5156,7 @@ idDottedMoreForeach<nodep>:
 // we'll assume so and cleanup later.
 // id below includes:
 //       enum_identifier
-idArrayed<nodep>:               // IEEE: id + select
+idArrayed<nodeExprp>:               // IEEE: id + select
                 id
                         { $$ = new AstParseRef($<fl>1, VParseRefExp::PX_TEXT, *$1, nullptr, nullptr); }
         //                      // IEEE: id + part_select_range/constant_part_select_range
@@ -5174,9 +5179,9 @@ idArrayedForeach<nodep>:        // IEEE: id + select (under foreach expression)
         //                      // IEEE: loop_variables (under foreach expression)
         //                      // To avoid conflicts we allow expr as first element, must post-check
         |       idArrayed '[' expr ',' loop_variables ']'
-                        { $3 = addNextNull($3, $5); $$ = new AstSelLoopVars($2, $1, $3); }
+                        { $$ = new AstSelLoopVars{$2, $1, addNextNull(static_cast<AstNode*>($3), $5)}; }
         |       idArrayed '[' ',' loop_variables ']'
-                        { $4 = addNextNull(static_cast<AstNode*>(new AstEmpty{$3}), $4); $$ = new AstSelLoopVars($2, $1, $4); }
+                        { $$ = new AstSelLoopVars{$2, $1, addNextNull(static_cast<AstNode*>(new AstEmpty{$3}), $4)}; }
         ;
 
 // VarRef without any dots or vectorizaion
@@ -5195,7 +5200,7 @@ str<strp>:                      // yaSTRING but with \{escapes} need decoded
                 yaSTRING                                { $$ = PARSEP->newString(GRAMMARP->deQuote($<fl>1,*$1)); }
         ;
 
-strAsInt<nodep>:
+strAsInt<nodeExprp>:
                 yaSTRING
                         { if ($1->empty()) {
                               // else "" is not representable as number as is width 0
@@ -5208,7 +5213,7 @@ strAsInt<nodep>:
                         }
         ;
 
-strAsIntIgnore<nodep>:          // strAsInt, but never matches for when expr shouldn't parse strings
+strAsIntIgnore<nodeExprp>:          // strAsInt, but never matches for when expr shouldn't parse strings
                 yaSTRING__IGNORE                        { $$ = nullptr; yyerror("Impossible token"); }
         ;
 
@@ -6563,7 +6568,7 @@ constraintStaticE<cbool>:  // IEEE: part of extern_constraint_declaration
 //**********************************************************************
 // Constants
 
-timeNumAdjusted<nodep>:         // Time constant, adjusted to module's time units/precision
+timeNumAdjusted<nodeExprp>:         // Time constant, adjusted to module's time units/precision
                 yaTIMENUM
                         { $$ = new AstTimeImport($<fl>1, new AstConst($<fl>1, AstConst::RealDouble(), $1)); }
         ;
diff --git a/test_regress/t/t_debug_emitv.out b/test_regress/t/t_debug_emitv.out
index 749f294de..ac753a612 100644
--- a/test_regress/t/t_debug_emitv.out
+++ b/test_regress/t/t_debug_emitv.out
@@ -148,7 +148,8 @@ module Vt_debug_emitv_t;
                             other = f(i);
                             $display("stmt %~ %~", 
                                      iother, other);
-                            t()end
+                            t();
+                        end
                         i = (i + 'h1);
                     end
                 end
@@ -189,7 +190,8 @@ module Vt_debug_emitv_t;
             cyc <= (cyc + 'sh1);
             r <= (r + 0.01);
             fo = cyc;
-            sub.inc(fosum)sum = sub.f(sum);
+            sub.inc(fosum);
+            sum = sub.f(sum);
             $display("[%0t] sum = %~", $timesum, sum);
             $display("a?= %d", ($c('sh1) ? $c('sh14)
                                  : $c('sh1e)));
diff --git a/test_regress/t/t_func_tasknsvar_bad.out b/test_regress/t/t_func_tasknsvar_bad.out
index 241d8b71a..230364bae 100644
--- a/test_regress/t/t_func_tasknsvar_bad.out
+++ b/test_regress/t/t_func_tasknsvar_bad.out
@@ -2,7 +2,7 @@
    16 |       foo(bus_we_select_from[2]);   
       |                             ^
                   ... For error description see https://verilator.org/warn/TASKNSVAR?v=latest
-%Error: Internal Error: t/t_func_tasknsvar_bad.v:10:7: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): 'm_varp && !m_varp->brokeExists()' @ ../V3AstNodes.cpp:64
+%Error: Internal Error: t/t_func_tasknsvar_bad.v:10:7: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): 'm_varp && !m_varp->brokeExists()' @ ../V3AstNodes.cpp:66
    10 |       sig = '1;
       |       ^~~
                         ... See the manual at https://verilator.org/verilator_doc.html for more assistance.
diff --git a/test_regress/t/t_xml_debugcheck.out b/test_regress/t/t_xml_debugcheck.out
index 35a4d21a9..dbadeec0d 100644
--- a/test_regress/t/t_xml_debugcheck.out
+++ b/test_regress/t/t_xml_debugcheck.out
@@ -33,51 +33,55 @@
         <scope loc="d,10,8,10,9" name="TOP"/>
       </topscope>
       <cfunc loc="a,0,0,0,0" name="_eval_static">
-        <ccall loc="d,10,8,10,9" func="_eval_static__TOP"/>
+        <stmtexpr loc="d,10,8,10,9">
+          <ccall loc="d,10,8,10,9" dtype_id="7" func="_eval_static__TOP"/>
+        </stmtexpr>
       </cfunc>
       <cfunc loc="d,10,8,10,9" name="_eval_static__TOP">
         <assign loc="d,22,23,22,24" dtype_id="4">
-          <const loc="d,22,23,22,24" name="32&apos;sh0" dtype_id="7"/>
+          <const loc="d,22,23,22,24" name="32&apos;sh0" dtype_id="8"/>
           <varref loc="d,22,23,22,24" name="t.cyc" dtype_id="4"/>
         </assign>
       </cfunc>
       <cfunc loc="a,0,0,0,0" name="_eval_initial">
-        <ccall loc="d,10,8,10,9" func="_eval_initial__TOP"/>
-        <assign loc="d,60,22,60,25" dtype_id="8">
-          <varref loc="d,60,22,60,25" name="clk" dtype_id="8"/>
-          <varref loc="d,60,22,60,25" name="__Vtrigrprev__TOP__clk" dtype_id="8"/>
+        <stmtexpr loc="d,10,8,10,9">
+          <ccall loc="d,10,8,10,9" dtype_id="7" func="_eval_initial__TOP"/>
+        </stmtexpr>
+        <assign loc="d,60,22,60,25" dtype_id="9">
+          <varref loc="d,60,22,60,25" name="clk" dtype_id="9"/>
+          <varref loc="d,60,22,60,25" name="__Vtrigrprev__TOP__clk" dtype_id="9"/>
         </assign>
       </cfunc>
       <cfunc loc="d,10,8,10,9" name="_eval_initial__TOP">
-        <var loc="d,27,11,27,14" name="t.all" dtype_id="9" vartype="string" origName="t__DOT__all"/>
+        <var loc="d,27,11,27,14" name="t.all" dtype_id="10" vartype="string" origName="t__DOT__all"/>
         <var loc="d,51,17,51,18" name="t.unnamedblk1.e" dtype_id="2" vartype="my_t" origName="t__DOT__unnamedblk1__DOT__e"/>
-        <var loc="d,48,123,48,127" name="__Vtemp_h########__0" dtype_id="9" vartype="string" origName="__Vtemp_h########__0"/>
-        <assign loc="d,31,9,31,10" dtype_id="10">
-          <const loc="d,31,11,31,14" name="4&apos;h3" dtype_id="10"/>
-          <varref loc="d,31,7,31,8" name="t.e" dtype_id="10"/>
+        <var loc="d,48,123,48,127" name="__Vtemp_h########__0" dtype_id="10" vartype="string" origName="__Vtemp_h########__0"/>
+        <assign loc="d,31,9,31,10" dtype_id="11">
+          <const loc="d,31,11,31,14" name="4&apos;h3" dtype_id="11"/>
+          <varref loc="d,31,7,31,8" name="t.e" dtype_id="11"/>
         </assign>
         <if loc="d,37,10,37,12">
-          <neq loc="d,37,26,37,29" dtype_id="8">
-            <const loc="d,37,31,37,34" name="4&apos;h4" dtype_id="10"/>
-            <arraysel loc="d,37,17,37,21" dtype_id="10">
-              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-              <and loc="d,37,17,37,21" dtype_id="12">
-                <const loc="d,37,17,37,21" name="32&apos;h7" dtype_id="13"/>
-                <ccast loc="d,37,15,37,16" dtype_id="12">
-                  <varref loc="d,37,15,37,16" name="t.e" dtype_id="12"/>
+          <neq loc="d,37,26,37,29" dtype_id="9">
+            <const loc="d,37,31,37,34" name="4&apos;h4" dtype_id="11"/>
+            <arraysel loc="d,37,17,37,21" dtype_id="11">
+              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+              <and loc="d,37,17,37,21" dtype_id="13">
+                <const loc="d,37,17,37,21" name="32&apos;h7" dtype_id="14"/>
+                <ccast loc="d,37,15,37,16" dtype_id="13">
+                  <varref loc="d,37,15,37,16" name="t.e" dtype_id="13"/>
                 </ccast>
               </and>
             </arraysel>
           </neq>
           <begin>
             <display loc="d,37,43,37,49" displaytype="$write">
-              <sformatf loc="d,37,43,37,49" name="%%Error: t/t_enum_type_methods.v:37:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
-                <arraysel loc="d,37,124,37,128" dtype_id="10">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                  <and loc="d,37,124,37,128" dtype_id="12">
-                    <const loc="d,37,124,37,128" name="32&apos;h7" dtype_id="13"/>
-                    <ccast loc="d,37,122,37,123" dtype_id="12">
-                      <varref loc="d,37,122,37,123" name="t.e" dtype_id="12"/>
+              <sformatf loc="d,37,43,37,49" name="%%Error: t/t_enum_type_methods.v:37:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="10">
+                <arraysel loc="d,37,124,37,128" dtype_id="11">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                  <and loc="d,37,124,37,128" dtype_id="13">
+                    <const loc="d,37,124,37,128" name="32&apos;h7" dtype_id="14"/>
+                    <ccast loc="d,37,122,37,123" dtype_id="13">
+                      <varref loc="d,37,122,37,123" name="t.e" dtype_id="13"/>
                     </ccast>
                   </and>
                 </arraysel>
@@ -87,18 +91,18 @@
           </begin>
         </if>
         <if loc="d,38,10,38,12">
-          <neq loc="d,38,34,38,37" dtype_id="8">
-            <const loc="d,38,39,38,42" name="4&apos;h1" dtype_id="10"/>
-            <arraysel loc="d,38,25,38,29" dtype_id="10">
-              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-              <and loc="d,38,25,38,29" dtype_id="12">
-                <const loc="d,38,25,38,29" name="32&apos;h7" dtype_id="13"/>
-                <arraysel loc="d,38,17,38,21" dtype_id="12">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                  <and loc="d,38,17,38,21" dtype_id="12">
-                    <const loc="d,38,17,38,21" name="32&apos;h7" dtype_id="13"/>
-                    <ccast loc="d,38,15,38,16" dtype_id="12">
-                      <varref loc="d,38,15,38,16" name="t.e" dtype_id="12"/>
+          <neq loc="d,38,34,38,37" dtype_id="9">
+            <const loc="d,38,39,38,42" name="4&apos;h1" dtype_id="11"/>
+            <arraysel loc="d,38,25,38,29" dtype_id="11">
+              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+              <and loc="d,38,25,38,29" dtype_id="13">
+                <const loc="d,38,25,38,29" name="32&apos;h7" dtype_id="14"/>
+                <arraysel loc="d,38,17,38,21" dtype_id="13">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                  <and loc="d,38,17,38,21" dtype_id="13">
+                    <const loc="d,38,17,38,21" name="32&apos;h7" dtype_id="14"/>
+                    <ccast loc="d,38,15,38,16" dtype_id="13">
+                      <varref loc="d,38,15,38,16" name="t.e" dtype_id="13"/>
                     </ccast>
                   </and>
                 </arraysel>
@@ -107,17 +111,17 @@
           </neq>
           <begin>
             <display loc="d,38,51,38,57" displaytype="$write">
-              <sformatf loc="d,38,51,38,57" name="%%Error: t/t_enum_type_methods.v:38:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
-                <arraysel loc="d,38,140,38,144" dtype_id="10">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                  <and loc="d,38,140,38,144" dtype_id="12">
-                    <const loc="d,38,140,38,144" name="32&apos;h7" dtype_id="13"/>
-                    <arraysel loc="d,38,132,38,136" dtype_id="12">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                      <and loc="d,38,132,38,136" dtype_id="12">
-                        <const loc="d,38,132,38,136" name="32&apos;h7" dtype_id="13"/>
-                        <ccast loc="d,38,130,38,131" dtype_id="12">
-                          <varref loc="d,38,130,38,131" name="t.e" dtype_id="12"/>
+              <sformatf loc="d,38,51,38,57" name="%%Error: t/t_enum_type_methods.v:38:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="10">
+                <arraysel loc="d,38,140,38,144" dtype_id="11">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                  <and loc="d,38,140,38,144" dtype_id="13">
+                    <const loc="d,38,140,38,144" name="32&apos;h7" dtype_id="14"/>
+                    <arraysel loc="d,38,132,38,136" dtype_id="13">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                      <and loc="d,38,132,38,136" dtype_id="13">
+                        <const loc="d,38,132,38,136" name="32&apos;h7" dtype_id="14"/>
+                        <ccast loc="d,38,130,38,131" dtype_id="13">
+                          <varref loc="d,38,130,38,131" name="t.e" dtype_id="13"/>
                         </ccast>
                       </and>
                     </arraysel>
@@ -129,18 +133,18 @@
           </begin>
         </if>
         <if loc="d,39,10,39,12">
-          <neq loc="d,39,26,39,29" dtype_id="8">
-            <const loc="d,39,31,39,34" name="4&apos;h1" dtype_id="10"/>
-            <arraysel loc="d,39,17,39,21" dtype_id="10">
-              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-              <and loc="d,39,17,39,21" dtype_id="12">
-                <const loc="d,39,17,39,21" name="32&apos;h7" dtype_id="13"/>
-                <arraysel loc="d,39,17,39,21" dtype_id="12">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                  <and loc="d,39,17,39,21" dtype_id="12">
-                    <const loc="d,39,17,39,21" name="32&apos;h7" dtype_id="13"/>
-                    <ccast loc="d,39,15,39,16" dtype_id="12">
-                      <varref loc="d,39,15,39,16" name="t.e" dtype_id="12"/>
+          <neq loc="d,39,26,39,29" dtype_id="9">
+            <const loc="d,39,31,39,34" name="4&apos;h1" dtype_id="11"/>
+            <arraysel loc="d,39,17,39,21" dtype_id="11">
+              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+              <and loc="d,39,17,39,21" dtype_id="13">
+                <const loc="d,39,17,39,21" name="32&apos;h7" dtype_id="14"/>
+                <arraysel loc="d,39,17,39,21" dtype_id="13">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                  <and loc="d,39,17,39,21" dtype_id="13">
+                    <const loc="d,39,17,39,21" name="32&apos;h7" dtype_id="14"/>
+                    <ccast loc="d,39,15,39,16" dtype_id="13">
+                      <varref loc="d,39,15,39,16" name="t.e" dtype_id="13"/>
                     </ccast>
                   </and>
                 </arraysel>
@@ -149,17 +153,17 @@
           </neq>
           <begin>
             <display loc="d,39,43,39,49" displaytype="$write">
-              <sformatf loc="d,39,43,39,49" name="%%Error: t/t_enum_type_methods.v:39:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
-                <arraysel loc="d,39,124,39,128" dtype_id="10">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                  <and loc="d,39,124,39,128" dtype_id="12">
-                    <const loc="d,39,124,39,128" name="32&apos;h7" dtype_id="13"/>
-                    <arraysel loc="d,39,124,39,128" dtype_id="12">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                      <and loc="d,39,124,39,128" dtype_id="12">
-                        <const loc="d,39,124,39,128" name="32&apos;h7" dtype_id="13"/>
-                        <ccast loc="d,39,122,39,123" dtype_id="12">
-                          <varref loc="d,39,122,39,123" name="t.e" dtype_id="12"/>
+              <sformatf loc="d,39,43,39,49" name="%%Error: t/t_enum_type_methods.v:39:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="10">
+                <arraysel loc="d,39,124,39,128" dtype_id="11">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                  <and loc="d,39,124,39,128" dtype_id="13">
+                    <const loc="d,39,124,39,128" name="32&apos;h7" dtype_id="14"/>
+                    <arraysel loc="d,39,124,39,128" dtype_id="13">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                      <and loc="d,39,124,39,128" dtype_id="13">
+                        <const loc="d,39,124,39,128" name="32&apos;h7" dtype_id="14"/>
+                        <ccast loc="d,39,122,39,123" dtype_id="13">
+                          <varref loc="d,39,122,39,123" name="t.e" dtype_id="13"/>
                         </ccast>
                       </and>
                     </arraysel>
@@ -171,22 +175,22 @@
           </begin>
         </if>
         <if loc="d,40,10,40,12">
-          <neq loc="d,40,42,40,45" dtype_id="8">
-            <const loc="d,40,47,40,50" name="4&apos;h3" dtype_id="10"/>
-            <arraysel loc="d,40,33,40,37" dtype_id="10">
-              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-              <and loc="d,40,33,40,37" dtype_id="12">
-                <const loc="d,40,33,40,37" name="32&apos;h7" dtype_id="13"/>
-                <arraysel loc="d,40,25,40,29" dtype_id="12">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                  <and loc="d,40,25,40,29" dtype_id="12">
-                    <const loc="d,40,25,40,29" name="32&apos;h7" dtype_id="13"/>
-                    <arraysel loc="d,40,17,40,21" dtype_id="12">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                      <and loc="d,40,17,40,21" dtype_id="12">
-                        <const loc="d,40,17,40,21" name="32&apos;h7" dtype_id="13"/>
-                        <ccast loc="d,40,15,40,16" dtype_id="12">
-                          <varref loc="d,40,15,40,16" name="t.e" dtype_id="12"/>
+          <neq loc="d,40,42,40,45" dtype_id="9">
+            <const loc="d,40,47,40,50" name="4&apos;h3" dtype_id="11"/>
+            <arraysel loc="d,40,33,40,37" dtype_id="11">
+              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+              <and loc="d,40,33,40,37" dtype_id="13">
+                <const loc="d,40,33,40,37" name="32&apos;h7" dtype_id="14"/>
+                <arraysel loc="d,40,25,40,29" dtype_id="13">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                  <and loc="d,40,25,40,29" dtype_id="13">
+                    <const loc="d,40,25,40,29" name="32&apos;h7" dtype_id="14"/>
+                    <arraysel loc="d,40,17,40,21" dtype_id="13">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                      <and loc="d,40,17,40,21" dtype_id="13">
+                        <const loc="d,40,17,40,21" name="32&apos;h7" dtype_id="14"/>
+                        <ccast loc="d,40,15,40,16" dtype_id="13">
+                          <varref loc="d,40,15,40,16" name="t.e" dtype_id="13"/>
                         </ccast>
                       </and>
                     </arraysel>
@@ -197,21 +201,21 @@
           </neq>
           <begin>
             <display loc="d,40,59,40,65" displaytype="$write">
-              <sformatf loc="d,40,59,40,65" name="%%Error: t/t_enum_type_methods.v:40:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
-                <arraysel loc="d,40,156,40,160" dtype_id="10">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                  <and loc="d,40,156,40,160" dtype_id="12">
-                    <const loc="d,40,156,40,160" name="32&apos;h7" dtype_id="13"/>
-                    <arraysel loc="d,40,148,40,152" dtype_id="12">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                      <and loc="d,40,148,40,152" dtype_id="12">
-                        <const loc="d,40,148,40,152" name="32&apos;h7" dtype_id="13"/>
-                        <arraysel loc="d,40,140,40,144" dtype_id="12">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                          <and loc="d,40,140,40,144" dtype_id="12">
-                            <const loc="d,40,140,40,144" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,40,138,40,139" dtype_id="12">
-                              <varref loc="d,40,138,40,139" name="t.e" dtype_id="12"/>
+              <sformatf loc="d,40,59,40,65" name="%%Error: t/t_enum_type_methods.v:40:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="10">
+                <arraysel loc="d,40,156,40,160" dtype_id="11">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                  <and loc="d,40,156,40,160" dtype_id="13">
+                    <const loc="d,40,156,40,160" name="32&apos;h7" dtype_id="14"/>
+                    <arraysel loc="d,40,148,40,152" dtype_id="13">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                      <and loc="d,40,148,40,152" dtype_id="13">
+                        <const loc="d,40,148,40,152" name="32&apos;h7" dtype_id="14"/>
+                        <arraysel loc="d,40,140,40,144" dtype_id="13">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                          <and loc="d,40,140,40,144" dtype_id="13">
+                            <const loc="d,40,140,40,144" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,40,138,40,139" dtype_id="13">
+                              <varref loc="d,40,138,40,139" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
@@ -225,22 +229,22 @@
           </begin>
         </if>
         <if loc="d,41,10,41,12">
-          <neq loc="d,41,34,41,37" dtype_id="8">
-            <const loc="d,41,39,41,42" name="4&apos;h3" dtype_id="10"/>
-            <arraysel loc="d,41,25,41,29" dtype_id="10">
-              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-              <and loc="d,41,25,41,29" dtype_id="12">
-                <const loc="d,41,25,41,29" name="32&apos;h7" dtype_id="13"/>
-                <arraysel loc="d,41,25,41,29" dtype_id="12">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                  <and loc="d,41,25,41,29" dtype_id="12">
-                    <const loc="d,41,25,41,29" name="32&apos;h7" dtype_id="13"/>
-                    <arraysel loc="d,41,17,41,21" dtype_id="12">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                      <and loc="d,41,17,41,21" dtype_id="12">
-                        <const loc="d,41,17,41,21" name="32&apos;h7" dtype_id="13"/>
-                        <ccast loc="d,41,15,41,16" dtype_id="12">
-                          <varref loc="d,41,15,41,16" name="t.e" dtype_id="12"/>
+          <neq loc="d,41,34,41,37" dtype_id="9">
+            <const loc="d,41,39,41,42" name="4&apos;h3" dtype_id="11"/>
+            <arraysel loc="d,41,25,41,29" dtype_id="11">
+              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+              <and loc="d,41,25,41,29" dtype_id="13">
+                <const loc="d,41,25,41,29" name="32&apos;h7" dtype_id="14"/>
+                <arraysel loc="d,41,25,41,29" dtype_id="13">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                  <and loc="d,41,25,41,29" dtype_id="13">
+                    <const loc="d,41,25,41,29" name="32&apos;h7" dtype_id="14"/>
+                    <arraysel loc="d,41,17,41,21" dtype_id="13">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                      <and loc="d,41,17,41,21" dtype_id="13">
+                        <const loc="d,41,17,41,21" name="32&apos;h7" dtype_id="14"/>
+                        <ccast loc="d,41,15,41,16" dtype_id="13">
+                          <varref loc="d,41,15,41,16" name="t.e" dtype_id="13"/>
                         </ccast>
                       </and>
                     </arraysel>
@@ -251,21 +255,21 @@
           </neq>
           <begin>
             <display loc="d,41,51,41,57" displaytype="$write">
-              <sformatf loc="d,41,51,41,57" name="%%Error: t/t_enum_type_methods.v:41:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
-                <arraysel loc="d,41,140,41,144" dtype_id="10">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                  <and loc="d,41,140,41,144" dtype_id="12">
-                    <const loc="d,41,140,41,144" name="32&apos;h7" dtype_id="13"/>
-                    <arraysel loc="d,41,140,41,144" dtype_id="12">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                      <and loc="d,41,140,41,144" dtype_id="12">
-                        <const loc="d,41,140,41,144" name="32&apos;h7" dtype_id="13"/>
-                        <arraysel loc="d,41,132,41,136" dtype_id="12">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                          <and loc="d,41,132,41,136" dtype_id="12">
-                            <const loc="d,41,132,41,136" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,41,130,41,131" dtype_id="12">
-                              <varref loc="d,41,130,41,131" name="t.e" dtype_id="12"/>
+              <sformatf loc="d,41,51,41,57" name="%%Error: t/t_enum_type_methods.v:41:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="10">
+                <arraysel loc="d,41,140,41,144" dtype_id="11">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                  <and loc="d,41,140,41,144" dtype_id="13">
+                    <const loc="d,41,140,41,144" name="32&apos;h7" dtype_id="14"/>
+                    <arraysel loc="d,41,140,41,144" dtype_id="13">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                      <and loc="d,41,140,41,144" dtype_id="13">
+                        <const loc="d,41,140,41,144" name="32&apos;h7" dtype_id="14"/>
+                        <arraysel loc="d,41,132,41,136" dtype_id="13">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                          <and loc="d,41,132,41,136" dtype_id="13">
+                            <const loc="d,41,132,41,136" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,41,130,41,131" dtype_id="13">
+                              <varref loc="d,41,130,41,131" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
@@ -279,22 +283,22 @@
           </begin>
         </if>
         <if loc="d,42,10,42,12">
-          <neq loc="d,42,26,42,29" dtype_id="8">
-            <const loc="d,42,31,42,34" name="4&apos;h3" dtype_id="10"/>
-            <arraysel loc="d,42,17,42,21" dtype_id="10">
-              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-              <and loc="d,42,17,42,21" dtype_id="12">
-                <const loc="d,42,17,42,21" name="32&apos;h7" dtype_id="13"/>
-                <arraysel loc="d,42,17,42,21" dtype_id="12">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                  <and loc="d,42,17,42,21" dtype_id="12">
-                    <const loc="d,42,17,42,21" name="32&apos;h7" dtype_id="13"/>
-                    <arraysel loc="d,42,17,42,21" dtype_id="12">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                      <and loc="d,42,17,42,21" dtype_id="12">
-                        <const loc="d,42,17,42,21" name="32&apos;h7" dtype_id="13"/>
-                        <ccast loc="d,42,15,42,16" dtype_id="12">
-                          <varref loc="d,42,15,42,16" name="t.e" dtype_id="12"/>
+          <neq loc="d,42,26,42,29" dtype_id="9">
+            <const loc="d,42,31,42,34" name="4&apos;h3" dtype_id="11"/>
+            <arraysel loc="d,42,17,42,21" dtype_id="11">
+              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+              <and loc="d,42,17,42,21" dtype_id="13">
+                <const loc="d,42,17,42,21" name="32&apos;h7" dtype_id="14"/>
+                <arraysel loc="d,42,17,42,21" dtype_id="13">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                  <and loc="d,42,17,42,21" dtype_id="13">
+                    <const loc="d,42,17,42,21" name="32&apos;h7" dtype_id="14"/>
+                    <arraysel loc="d,42,17,42,21" dtype_id="13">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                      <and loc="d,42,17,42,21" dtype_id="13">
+                        <const loc="d,42,17,42,21" name="32&apos;h7" dtype_id="14"/>
+                        <ccast loc="d,42,15,42,16" dtype_id="13">
+                          <varref loc="d,42,15,42,16" name="t.e" dtype_id="13"/>
                         </ccast>
                       </and>
                     </arraysel>
@@ -305,21 +309,21 @@
           </neq>
           <begin>
             <display loc="d,42,43,42,49" displaytype="$write">
-              <sformatf loc="d,42,43,42,49" name="%%Error: t/t_enum_type_methods.v:42:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
-                <arraysel loc="d,42,124,42,128" dtype_id="10">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                  <and loc="d,42,124,42,128" dtype_id="12">
-                    <const loc="d,42,124,42,128" name="32&apos;h7" dtype_id="13"/>
-                    <arraysel loc="d,42,124,42,128" dtype_id="12">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                      <and loc="d,42,124,42,128" dtype_id="12">
-                        <const loc="d,42,124,42,128" name="32&apos;h7" dtype_id="13"/>
-                        <arraysel loc="d,42,124,42,128" dtype_id="12">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                          <and loc="d,42,124,42,128" dtype_id="12">
-                            <const loc="d,42,124,42,128" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,42,122,42,123" dtype_id="12">
-                              <varref loc="d,42,122,42,123" name="t.e" dtype_id="12"/>
+              <sformatf loc="d,42,43,42,49" name="%%Error: t/t_enum_type_methods.v:42:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="10">
+                <arraysel loc="d,42,124,42,128" dtype_id="11">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                  <and loc="d,42,124,42,128" dtype_id="13">
+                    <const loc="d,42,124,42,128" name="32&apos;h7" dtype_id="14"/>
+                    <arraysel loc="d,42,124,42,128" dtype_id="13">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                      <and loc="d,42,124,42,128" dtype_id="13">
+                        <const loc="d,42,124,42,128" name="32&apos;h7" dtype_id="14"/>
+                        <arraysel loc="d,42,124,42,128" dtype_id="13">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                          <and loc="d,42,124,42,128" dtype_id="13">
+                            <const loc="d,42,124,42,128" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,42,122,42,123" dtype_id="13">
+                              <varref loc="d,42,122,42,123" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
@@ -333,27 +337,27 @@
           </begin>
         </if>
         <if loc="d,43,10,43,12">
-          <neq loc="d,43,23,43,26" dtype_id="8">
-            <const loc="d,43,28,43,31" name="4&apos;h1" dtype_id="10"/>
-            <arraysel loc="d,43,17,43,21" dtype_id="10">
-              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-              <and loc="d,43,17,43,21" dtype_id="12">
-                <const loc="d,43,17,43,21" name="32&apos;h7" dtype_id="13"/>
-                <ccast loc="d,43,15,43,16" dtype_id="12">
-                  <varref loc="d,43,15,43,16" name="t.e" dtype_id="12"/>
+          <neq loc="d,43,23,43,26" dtype_id="9">
+            <const loc="d,43,28,43,31" name="4&apos;h1" dtype_id="11"/>
+            <arraysel loc="d,43,17,43,21" dtype_id="11">
+              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+              <and loc="d,43,17,43,21" dtype_id="13">
+                <const loc="d,43,17,43,21" name="32&apos;h7" dtype_id="14"/>
+                <ccast loc="d,43,15,43,16" dtype_id="13">
+                  <varref loc="d,43,15,43,16" name="t.e" dtype_id="13"/>
                 </ccast>
               </and>
             </arraysel>
           </neq>
           <begin>
             <display loc="d,43,40,43,46" displaytype="$write">
-              <sformatf loc="d,43,40,43,46" name="%%Error: t/t_enum_type_methods.v:43:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
-                <arraysel loc="d,43,121,43,125" dtype_id="10">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                  <and loc="d,43,121,43,125" dtype_id="12">
-                    <const loc="d,43,121,43,125" name="32&apos;h7" dtype_id="13"/>
-                    <ccast loc="d,43,119,43,120" dtype_id="12">
-                      <varref loc="d,43,119,43,120" name="t.e" dtype_id="12"/>
+              <sformatf loc="d,43,40,43,46" name="%%Error: t/t_enum_type_methods.v:43:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="10">
+                <arraysel loc="d,43,121,43,125" dtype_id="11">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                  <and loc="d,43,121,43,125" dtype_id="13">
+                    <const loc="d,43,121,43,125" name="32&apos;h7" dtype_id="14"/>
+                    <ccast loc="d,43,119,43,120" dtype_id="13">
+                      <varref loc="d,43,119,43,120" name="t.e" dtype_id="13"/>
                     </ccast>
                   </and>
                 </arraysel>
@@ -363,27 +367,27 @@
           </begin>
         </if>
         <if loc="d,44,10,44,12">
-          <neq loc="d,44,26,44,29" dtype_id="8">
-            <const loc="d,44,31,44,34" name="4&apos;h1" dtype_id="10"/>
-            <arraysel loc="d,44,17,44,21" dtype_id="10">
-              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-              <and loc="d,44,17,44,21" dtype_id="12">
-                <const loc="d,44,17,44,21" name="32&apos;h7" dtype_id="13"/>
-                <ccast loc="d,44,15,44,16" dtype_id="12">
-                  <varref loc="d,44,15,44,16" name="t.e" dtype_id="12"/>
+          <neq loc="d,44,26,44,29" dtype_id="9">
+            <const loc="d,44,31,44,34" name="4&apos;h1" dtype_id="11"/>
+            <arraysel loc="d,44,17,44,21" dtype_id="11">
+              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+              <and loc="d,44,17,44,21" dtype_id="13">
+                <const loc="d,44,17,44,21" name="32&apos;h7" dtype_id="14"/>
+                <ccast loc="d,44,15,44,16" dtype_id="13">
+                  <varref loc="d,44,15,44,16" name="t.e" dtype_id="13"/>
                 </ccast>
               </and>
             </arraysel>
           </neq>
           <begin>
             <display loc="d,44,43,44,49" displaytype="$write">
-              <sformatf loc="d,44,43,44,49" name="%%Error: t/t_enum_type_methods.v:44:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
-                <arraysel loc="d,44,124,44,128" dtype_id="10">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                  <and loc="d,44,124,44,128" dtype_id="12">
-                    <const loc="d,44,124,44,128" name="32&apos;h7" dtype_id="13"/>
-                    <ccast loc="d,44,122,44,123" dtype_id="12">
-                      <varref loc="d,44,122,44,123" name="t.e" dtype_id="12"/>
+              <sformatf loc="d,44,43,44,49" name="%%Error: t/t_enum_type_methods.v:44:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="10">
+                <arraysel loc="d,44,124,44,128" dtype_id="11">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                  <and loc="d,44,124,44,128" dtype_id="13">
+                    <const loc="d,44,124,44,128" name="32&apos;h7" dtype_id="14"/>
+                    <ccast loc="d,44,122,44,123" dtype_id="13">
+                      <varref loc="d,44,122,44,123" name="t.e" dtype_id="13"/>
                     </ccast>
                   </and>
                 </arraysel>
@@ -393,18 +397,18 @@
           </begin>
         </if>
         <if loc="d,45,10,45,12">
-          <neq loc="d,45,34,45,37" dtype_id="8">
-            <const loc="d,45,39,45,42" name="4&apos;h4" dtype_id="10"/>
-            <arraysel loc="d,45,25,45,29" dtype_id="10">
-              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-              <and loc="d,45,25,45,29" dtype_id="12">
-                <const loc="d,45,25,45,29" name="32&apos;h7" dtype_id="13"/>
-                <arraysel loc="d,45,17,45,21" dtype_id="12">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                  <and loc="d,45,17,45,21" dtype_id="12">
-                    <const loc="d,45,17,45,21" name="32&apos;h7" dtype_id="13"/>
-                    <ccast loc="d,45,15,45,16" dtype_id="12">
-                      <varref loc="d,45,15,45,16" name="t.e" dtype_id="12"/>
+          <neq loc="d,45,34,45,37" dtype_id="9">
+            <const loc="d,45,39,45,42" name="4&apos;h4" dtype_id="11"/>
+            <arraysel loc="d,45,25,45,29" dtype_id="11">
+              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+              <and loc="d,45,25,45,29" dtype_id="13">
+                <const loc="d,45,25,45,29" name="32&apos;h7" dtype_id="14"/>
+                <arraysel loc="d,45,17,45,21" dtype_id="13">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                  <and loc="d,45,17,45,21" dtype_id="13">
+                    <const loc="d,45,17,45,21" name="32&apos;h7" dtype_id="14"/>
+                    <ccast loc="d,45,15,45,16" dtype_id="13">
+                      <varref loc="d,45,15,45,16" name="t.e" dtype_id="13"/>
                     </ccast>
                   </and>
                 </arraysel>
@@ -413,17 +417,17 @@
           </neq>
           <begin>
             <display loc="d,45,51,45,57" displaytype="$write">
-              <sformatf loc="d,45,51,45,57" name="%%Error: t/t_enum_type_methods.v:45:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
-                <arraysel loc="d,45,140,45,144" dtype_id="10">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                  <and loc="d,45,140,45,144" dtype_id="12">
-                    <const loc="d,45,140,45,144" name="32&apos;h7" dtype_id="13"/>
-                    <arraysel loc="d,45,132,45,136" dtype_id="12">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                      <and loc="d,45,132,45,136" dtype_id="12">
-                        <const loc="d,45,132,45,136" name="32&apos;h7" dtype_id="13"/>
-                        <ccast loc="d,45,130,45,131" dtype_id="12">
-                          <varref loc="d,45,130,45,131" name="t.e" dtype_id="12"/>
+              <sformatf loc="d,45,51,45,57" name="%%Error: t/t_enum_type_methods.v:45:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="10">
+                <arraysel loc="d,45,140,45,144" dtype_id="11">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                  <and loc="d,45,140,45,144" dtype_id="13">
+                    <const loc="d,45,140,45,144" name="32&apos;h7" dtype_id="14"/>
+                    <arraysel loc="d,45,132,45,136" dtype_id="13">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                      <and loc="d,45,132,45,136" dtype_id="13">
+                        <const loc="d,45,132,45,136" name="32&apos;h7" dtype_id="14"/>
+                        <ccast loc="d,45,130,45,131" dtype_id="13">
+                          <varref loc="d,45,130,45,131" name="t.e" dtype_id="13"/>
                         </ccast>
                       </and>
                     </arraysel>
@@ -435,18 +439,18 @@
           </begin>
         </if>
         <if loc="d,46,10,46,12">
-          <neq loc="d,46,26,46,29" dtype_id="8">
-            <const loc="d,46,31,46,34" name="4&apos;h4" dtype_id="10"/>
-            <arraysel loc="d,46,17,46,21" dtype_id="10">
-              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-              <and loc="d,46,17,46,21" dtype_id="12">
-                <const loc="d,46,17,46,21" name="32&apos;h7" dtype_id="13"/>
-                <arraysel loc="d,46,17,46,21" dtype_id="12">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                  <and loc="d,46,17,46,21" dtype_id="12">
-                    <const loc="d,46,17,46,21" name="32&apos;h7" dtype_id="13"/>
-                    <ccast loc="d,46,15,46,16" dtype_id="12">
-                      <varref loc="d,46,15,46,16" name="t.e" dtype_id="12"/>
+          <neq loc="d,46,26,46,29" dtype_id="9">
+            <const loc="d,46,31,46,34" name="4&apos;h4" dtype_id="11"/>
+            <arraysel loc="d,46,17,46,21" dtype_id="11">
+              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+              <and loc="d,46,17,46,21" dtype_id="13">
+                <const loc="d,46,17,46,21" name="32&apos;h7" dtype_id="14"/>
+                <arraysel loc="d,46,17,46,21" dtype_id="13">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                  <and loc="d,46,17,46,21" dtype_id="13">
+                    <const loc="d,46,17,46,21" name="32&apos;h7" dtype_id="14"/>
+                    <ccast loc="d,46,15,46,16" dtype_id="13">
+                      <varref loc="d,46,15,46,16" name="t.e" dtype_id="13"/>
                     </ccast>
                   </and>
                 </arraysel>
@@ -455,17 +459,17 @@
           </neq>
           <begin>
             <display loc="d,46,43,46,49" displaytype="$write">
-              <sformatf loc="d,46,43,46,49" name="%%Error: t/t_enum_type_methods.v:46:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
-                <arraysel loc="d,46,124,46,128" dtype_id="10">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                  <and loc="d,46,124,46,128" dtype_id="12">
-                    <const loc="d,46,124,46,128" name="32&apos;h7" dtype_id="13"/>
-                    <arraysel loc="d,46,124,46,128" dtype_id="12">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                      <and loc="d,46,124,46,128" dtype_id="12">
-                        <const loc="d,46,124,46,128" name="32&apos;h7" dtype_id="13"/>
-                        <ccast loc="d,46,122,46,123" dtype_id="12">
-                          <varref loc="d,46,122,46,123" name="t.e" dtype_id="12"/>
+              <sformatf loc="d,46,43,46,49" name="%%Error: t/t_enum_type_methods.v:46:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="10">
+                <arraysel loc="d,46,124,46,128" dtype_id="11">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                  <and loc="d,46,124,46,128" dtype_id="13">
+                    <const loc="d,46,124,46,128" name="32&apos;h7" dtype_id="14"/>
+                    <arraysel loc="d,46,124,46,128" dtype_id="13">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                      <and loc="d,46,124,46,128" dtype_id="13">
+                        <const loc="d,46,124,46,128" name="32&apos;h7" dtype_id="14"/>
+                        <ccast loc="d,46,122,46,123" dtype_id="13">
+                          <varref loc="d,46,122,46,123" name="t.e" dtype_id="13"/>
                         </ccast>
                       </and>
                     </arraysel>
@@ -477,110 +481,110 @@
           </begin>
         </if>
         <if loc="d,48,10,48,12">
-          <neqn loc="d,48,23,48,26" dtype_id="8">
-            <const loc="d,48,28,48,33" name="&quot;E03&quot;" dtype_id="9"/>
-            <arraysel loc="d,48,17,48,21" dtype_id="9">
-              <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="15"/>
-              <and loc="d,48,17,48,21" dtype_id="12">
-                <const loc="d,48,17,48,21" name="32&apos;h7" dtype_id="13"/>
-                <ccast loc="d,48,15,48,16" dtype_id="12">
-                  <varref loc="d,48,15,48,16" name="t.e" dtype_id="12"/>
+          <neqn loc="d,48,23,48,26" dtype_id="9">
+            <const loc="d,48,28,48,33" name="&quot;E03&quot;" dtype_id="10"/>
+            <arraysel loc="d,48,17,48,21" dtype_id="10">
+              <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16"/>
+              <and loc="d,48,17,48,21" dtype_id="13">
+                <const loc="d,48,17,48,21" name="32&apos;h7" dtype_id="14"/>
+                <ccast loc="d,48,15,48,16" dtype_id="13">
+                  <varref loc="d,48,15,48,16" name="t.e" dtype_id="13"/>
                 </ccast>
               </and>
             </arraysel>
           </neqn>
           <begin>
-            <assign loc="d,48,123,48,127" dtype_id="9">
-              <arraysel loc="d,48,123,48,127" dtype_id="9">
-                <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="15"/>
-                <and loc="d,48,123,48,127" dtype_id="12">
-                  <const loc="d,48,123,48,127" name="32&apos;h7" dtype_id="13"/>
-                  <ccast loc="d,48,121,48,122" dtype_id="12">
-                    <varref loc="d,48,121,48,122" name="t.e" dtype_id="12"/>
+            <assign loc="d,48,123,48,127" dtype_id="10">
+              <arraysel loc="d,48,123,48,127" dtype_id="10">
+                <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16"/>
+                <and loc="d,48,123,48,127" dtype_id="13">
+                  <const loc="d,48,123,48,127" name="32&apos;h7" dtype_id="14"/>
+                  <ccast loc="d,48,121,48,122" dtype_id="13">
+                    <varref loc="d,48,121,48,122" name="t.e" dtype_id="13"/>
                   </ccast>
                 </and>
               </arraysel>
-              <varref loc="d,48,123,48,127" name="__Vtemp_h########__0" dtype_id="9"/>
+              <varref loc="d,48,123,48,127" name="__Vtemp_h########__0" dtype_id="10"/>
             </assign>
             <display loc="d,48,42,48,48" displaytype="$write">
-              <sformatf loc="d,48,42,48,48" name="%%Error: t/t_enum_type_methods.v:48:  got=&apos;%@&apos; exp=&apos;E03&apos;&#10;" dtype_id="9">
-                <varref loc="d,48,123,48,127" name="__Vtemp_h########__0" dtype_id="9"/>
+              <sformatf loc="d,48,42,48,48" name="%%Error: t/t_enum_type_methods.v:48:  got=&apos;%@&apos; exp=&apos;E03&apos;&#10;" dtype_id="10">
+                <varref loc="d,48,123,48,127" name="__Vtemp_h########__0" dtype_id="10"/>
               </sformatf>
             </display>
             <stop loc="d,48,140,48,145"/>
           </begin>
         </if>
-        <assign loc="d,50,11,50,12" dtype_id="9">
-          <const loc="d,50,13,50,15" name="&quot;&quot;" dtype_id="9"/>
-          <varref loc="d,50,7,50,10" name="t.all" dtype_id="9"/>
+        <assign loc="d,50,11,50,12" dtype_id="10">
+          <const loc="d,50,13,50,15" name="&quot;&quot;" dtype_id="10"/>
+          <varref loc="d,50,7,50,10" name="t.all" dtype_id="10"/>
         </assign>
-        <assign loc="d,51,19,51,20" dtype_id="10">
-          <const loc="d,51,23,51,28" name="4&apos;h1" dtype_id="10"/>
-          <varref loc="d,51,17,51,18" name="t.unnamedblk1.e" dtype_id="10"/>
+        <assign loc="d,51,19,51,20" dtype_id="11">
+          <const loc="d,51,23,51,28" name="4&apos;h1" dtype_id="11"/>
+          <varref loc="d,51,17,51,18" name="t.unnamedblk1.e" dtype_id="11"/>
         </assign>
         <while loc="d,51,7,51,10">
           <begin>
           </begin>
           <begin>
-            <neq loc="d,51,32,51,34" dtype_id="8">
-              <const loc="d,51,37,51,41" name="4&apos;h4" dtype_id="10"/>
-              <ccast loc="d,51,30,51,31" dtype_id="10">
-                <varref loc="d,51,30,51,31" name="t.unnamedblk1.e" dtype_id="10"/>
+            <neq loc="d,51,32,51,34" dtype_id="9">
+              <const loc="d,51,37,51,41" name="4&apos;h4" dtype_id="11"/>
+              <ccast loc="d,51,30,51,31" dtype_id="11">
+                <varref loc="d,51,30,51,31" name="t.unnamedblk1.e" dtype_id="11"/>
               </ccast>
             </neq>
           </begin>
           <begin>
-            <assign loc="d,52,14,52,15" dtype_id="9">
-              <concatn loc="d,52,20,52,21" dtype_id="9">
-                <varref loc="d,52,17,52,20" name="t.all" dtype_id="9"/>
-                <arraysel loc="d,52,24,52,28" dtype_id="9">
-                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="15"/>
-                  <and loc="d,52,24,52,28" dtype_id="12">
-                    <const loc="d,52,24,52,28" name="32&apos;h7" dtype_id="13"/>
-                    <ccast loc="d,52,22,52,23" dtype_id="12">
-                      <varref loc="d,52,22,52,23" name="t.unnamedblk1.e" dtype_id="12"/>
+            <assign loc="d,52,14,52,15" dtype_id="10">
+              <concatn loc="d,52,20,52,21" dtype_id="10">
+                <varref loc="d,52,17,52,20" name="t.all" dtype_id="10"/>
+                <arraysel loc="d,52,24,52,28" dtype_id="10">
+                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16"/>
+                  <and loc="d,52,24,52,28" dtype_id="13">
+                    <const loc="d,52,24,52,28" name="32&apos;h7" dtype_id="14"/>
+                    <ccast loc="d,52,22,52,23" dtype_id="13">
+                      <varref loc="d,52,22,52,23" name="t.unnamedblk1.e" dtype_id="13"/>
                     </ccast>
                   </and>
                 </arraysel>
               </concatn>
-              <varref loc="d,52,10,52,13" name="t.all" dtype_id="9"/>
+              <varref loc="d,52,10,52,13" name="t.all" dtype_id="10"/>
             </assign>
           </begin>
           <begin>
-            <assign loc="d,51,45,51,46" dtype_id="10">
-              <arraysel loc="d,51,49,51,53" dtype_id="10">
-                <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                <and loc="d,51,49,51,53" dtype_id="12">
-                  <const loc="d,51,49,51,53" name="32&apos;h7" dtype_id="13"/>
-                  <ccast loc="d,51,47,51,48" dtype_id="12">
-                    <varref loc="d,51,47,51,48" name="t.unnamedblk1.e" dtype_id="12"/>
+            <assign loc="d,51,45,51,46" dtype_id="11">
+              <arraysel loc="d,51,49,51,53" dtype_id="11">
+                <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                <and loc="d,51,49,51,53" dtype_id="13">
+                  <const loc="d,51,49,51,53" name="32&apos;h7" dtype_id="14"/>
+                  <ccast loc="d,51,47,51,48" dtype_id="13">
+                    <varref loc="d,51,47,51,48" name="t.unnamedblk1.e" dtype_id="13"/>
                   </ccast>
                 </and>
               </arraysel>
-              <varref loc="d,51,43,51,44" name="t.unnamedblk1.e" dtype_id="10"/>
+              <varref loc="d,51,43,51,44" name="t.unnamedblk1.e" dtype_id="11"/>
             </assign>
           </begin>
         </while>
-        <assign loc="d,54,9,54,10" dtype_id="10">
-          <const loc="d,54,13,54,17" name="4&apos;h4" dtype_id="10"/>
-          <varref loc="d,54,7,54,8" name="t.e" dtype_id="10"/>
+        <assign loc="d,54,9,54,10" dtype_id="11">
+          <const loc="d,54,13,54,17" name="4&apos;h4" dtype_id="11"/>
+          <varref loc="d,54,7,54,8" name="t.e" dtype_id="11"/>
         </assign>
-        <assign loc="d,55,11,55,12" dtype_id="9">
-          <concatn loc="d,55,17,55,18" dtype_id="9">
-            <varref loc="d,55,14,55,17" name="t.all" dtype_id="9"/>
-            <const loc="d,16,12,16,16" name="&quot;E04&quot;" dtype_id="9"/>
+        <assign loc="d,55,11,55,12" dtype_id="10">
+          <concatn loc="d,55,17,55,18" dtype_id="10">
+            <varref loc="d,55,14,55,17" name="t.all" dtype_id="10"/>
+            <const loc="d,16,12,16,16" name="&quot;E04&quot;" dtype_id="10"/>
           </concatn>
-          <varref loc="d,55,7,55,10" name="t.all" dtype_id="9"/>
+          <varref loc="d,55,7,55,10" name="t.all" dtype_id="10"/>
         </assign>
         <if loc="d,56,10,56,12">
-          <neqn loc="d,56,20,56,23" dtype_id="8">
-            <const loc="d,56,25,56,36" name="&quot;E01E03E04&quot;" dtype_id="9"/>
-            <varref loc="d,56,15,56,18" name="t.all" dtype_id="9"/>
+          <neqn loc="d,56,20,56,23" dtype_id="9">
+            <const loc="d,56,25,56,36" name="&quot;E01E03E04&quot;" dtype_id="10"/>
+            <varref loc="d,56,15,56,18" name="t.all" dtype_id="10"/>
           </neqn>
           <begin>
             <display loc="d,56,45,56,51" displaytype="$write">
-              <sformatf loc="d,56,45,56,51" name="%%Error: t/t_enum_type_methods.v:56:  got=&apos;%@&apos; exp=&apos;E01E03E04&apos;&#10;" dtype_id="9">
-                <varref loc="d,56,124,56,127" name="t.all" dtype_id="9"/>
+              <sformatf loc="d,56,45,56,51" name="%%Error: t/t_enum_type_methods.v:56:  got=&apos;%@&apos; exp=&apos;E01E03E04&apos;&#10;" dtype_id="10">
+                <varref loc="d,56,124,56,127" name="t.all" dtype_id="10"/>
               </sformatf>
             </display>
             <stop loc="d,56,146,56,151"/>
@@ -590,42 +594,44 @@
       <cfunc loc="a,0,0,0,0" name="_eval_final"/>
       <cfunc loc="a,0,0,0,0" name="_eval_settle"/>
       <cfunc loc="a,0,0,0,0" name="_eval_triggers__act">
-        <assign loc="d,10,8,10,9" dtype_id="8">
-          <and loc="d,60,14,60,21" dtype_id="8">
-            <ccast loc="d,60,22,60,25" dtype_id="8">
-              <varref loc="d,60,22,60,25" name="clk" dtype_id="8"/>
+        <assign loc="d,10,8,10,9" dtype_id="9">
+          <and loc="d,60,14,60,21" dtype_id="9">
+            <ccast loc="d,60,22,60,25" dtype_id="9">
+              <varref loc="d,60,22,60,25" name="clk" dtype_id="9"/>
             </ccast>
-            <not loc="d,60,14,60,21" dtype_id="8">
-              <ccast loc="d,60,14,60,21" dtype_id="8">
-                <varref loc="d,60,14,60,21" name="__Vtrigrprev__TOP__clk" dtype_id="8"/>
+            <not loc="d,60,14,60,21" dtype_id="9">
+              <ccast loc="d,60,14,60,21" dtype_id="9">
+                <varref loc="d,60,14,60,21" name="__Vtrigrprev__TOP__clk" dtype_id="9"/>
               </ccast>
             </not>
           </and>
-          <cmethodhard loc="d,10,8,10,9" name="at" dtype_id="8">
-            <varref loc="d,10,8,10,9" name="__VactTriggered" dtype_id="8"/>
-            <const loc="d,10,8,10,9" name="32&apos;h0" dtype_id="13"/>
+          <cmethodhard loc="d,10,8,10,9" name="at" dtype_id="9">
+            <varref loc="d,10,8,10,9" name="__VactTriggered" dtype_id="9"/>
+            <const loc="d,10,8,10,9" name="32&apos;h0" dtype_id="14"/>
           </cmethodhard>
         </assign>
-        <assign loc="d,60,22,60,25" dtype_id="8">
-          <varref loc="d,60,22,60,25" name="clk" dtype_id="8"/>
-          <varref loc="d,60,22,60,25" name="__Vtrigrprev__TOP__clk" dtype_id="8"/>
+        <assign loc="d,60,22,60,25" dtype_id="9">
+          <varref loc="d,60,22,60,25" name="clk" dtype_id="9"/>
+          <varref loc="d,60,22,60,25" name="__Vtrigrprev__TOP__clk" dtype_id="9"/>
         </assign>
         <textblock loc="d,10,8,10,9">
           <text loc="d,10,8,10,9"/>
           <text loc="d,10,8,10,9"/>
-          <ccall loc="d,10,8,10,9" func="_dump_triggers__act"/>
+          <stmtexpr loc="d,10,8,10,9">
+            <ccall loc="d,10,8,10,9" dtype_id="7" func="_dump_triggers__act"/>
+          </stmtexpr>
           <text loc="d,10,8,10,9"/>
           <text loc="d,10,8,10,9"/>
         </textblock>
       </cfunc>
       <cfunc loc="a,0,0,0,0" name="_dump_triggers__act">
         <if loc="d,10,8,10,9">
-          <and loc="d,10,8,10,9" dtype_id="8">
-            <const loc="d,10,8,10,9" name="32&apos;h1" dtype_id="13"/>
-            <not loc="d,10,8,10,9" dtype_id="8">
-              <ccast loc="d,10,8,10,9" dtype_id="8">
-                <cmethodhard loc="d,10,8,10,9" name="any" dtype_id="8">
-                  <varref loc="d,10,8,10,9" name="__VactTriggered" dtype_id="8"/>
+          <and loc="d,10,8,10,9" dtype_id="9">
+            <const loc="d,10,8,10,9" name="32&apos;h1" dtype_id="14"/>
+            <not loc="d,10,8,10,9" dtype_id="9">
+              <ccast loc="d,10,8,10,9" dtype_id="9">
+                <cmethodhard loc="d,10,8,10,9" name="any" dtype_id="9">
+                  <varref loc="d,10,8,10,9" name="__VactTriggered" dtype_id="9"/>
                 </cmethodhard>
               </ccast>
             </not>
@@ -635,9 +641,9 @@
           </begin>
         </if>
         <if loc="d,10,8,10,9">
-          <cmethodhard loc="d,10,8,10,9" name="at" dtype_id="8">
-            <varref loc="d,10,8,10,9" name="__VactTriggered" dtype_id="8"/>
-            <const loc="d,10,8,10,9" name="32&apos;h0" dtype_id="13"/>
+          <cmethodhard loc="d,10,8,10,9" name="at" dtype_id="9">
+            <varref loc="d,10,8,10,9" name="__VactTriggered" dtype_id="9"/>
+            <const loc="d,10,8,10,9" name="32&apos;h0" dtype_id="14"/>
           </cmethodhard>
           <begin>
             <text loc="d,10,8,10,9"/>
@@ -646,12 +652,12 @@
       </cfunc>
       <cfunc loc="a,0,0,0,0" name="_dump_triggers__nba">
         <if loc="d,10,8,10,9">
-          <and loc="d,10,8,10,9" dtype_id="8">
-            <const loc="d,10,8,10,9" name="32&apos;h1" dtype_id="13"/>
-            <not loc="d,10,8,10,9" dtype_id="8">
-              <ccast loc="d,10,8,10,9" dtype_id="8">
-                <cmethodhard loc="d,10,8,10,9" name="any" dtype_id="8">
-                  <varref loc="d,10,8,10,9" name="__VnbaTriggered" dtype_id="8"/>
+          <and loc="d,10,8,10,9" dtype_id="9">
+            <const loc="d,10,8,10,9" name="32&apos;h1" dtype_id="14"/>
+            <not loc="d,10,8,10,9" dtype_id="9">
+              <ccast loc="d,10,8,10,9" dtype_id="9">
+                <cmethodhard loc="d,10,8,10,9" name="any" dtype_id="9">
+                  <varref loc="d,10,8,10,9" name="__VnbaTriggered" dtype_id="9"/>
                 </cmethodhard>
               </ccast>
             </not>
@@ -661,9 +667,9 @@
           </begin>
         </if>
         <if loc="d,10,8,10,9">
-          <cmethodhard loc="d,10,8,10,9" name="at" dtype_id="8">
-            <varref loc="d,10,8,10,9" name="__VnbaTriggered" dtype_id="8"/>
-            <const loc="d,10,8,10,9" name="32&apos;h0" dtype_id="13"/>
+          <cmethodhard loc="d,10,8,10,9" name="at" dtype_id="9">
+            <varref loc="d,10,8,10,9" name="__VnbaTriggered" dtype_id="9"/>
+            <const loc="d,10,8,10,9" name="32&apos;h0" dtype_id="14"/>
           </cmethodhard>
           <begin>
             <text loc="d,10,8,10,9"/>
@@ -674,12 +680,12 @@
       <cfunc loc="d,64,10,64,11" name="_nba_sequent__TOP__0">
         <var loc="d,22,17,22,20" name="__Vdly__t.cyc" dtype_id="4" vartype="integer" origName="__Vdly__t__DOT__cyc"/>
         <var loc="d,23,9,23,10" name="__Vdly__t.e" dtype_id="2" vartype="my_t" origName="__Vdly__t__DOT__e"/>
-        <var loc="d,67,126,67,130" name="__Vtemp_h########__0" dtype_id="9" vartype="string" origName="__Vtemp_h########__0"/>
-        <var loc="d,77,126,77,130" name="__Vtemp_h########__1" dtype_id="9" vartype="string" origName="__Vtemp_h########__1"/>
-        <var loc="d,87,126,87,130" name="__Vtemp_h########__2" dtype_id="9" vartype="string" origName="__Vtemp_h########__2"/>
-        <assignpre loc="d,64,10,64,11" dtype_id="10">
-          <varref loc="d,64,10,64,11" name="t.e" dtype_id="10"/>
-          <varref loc="d,64,10,64,11" name="__Vdly__t.e" dtype_id="10"/>
+        <var loc="d,67,126,67,130" name="__Vtemp_h########__0" dtype_id="10" vartype="string" origName="__Vtemp_h########__0"/>
+        <var loc="d,77,126,77,130" name="__Vtemp_h########__1" dtype_id="10" vartype="string" origName="__Vtemp_h########__1"/>
+        <var loc="d,87,126,87,130" name="__Vtemp_h########__2" dtype_id="10" vartype="string" origName="__Vtemp_h########__2"/>
+        <assignpre loc="d,64,10,64,11" dtype_id="11">
+          <varref loc="d,64,10,64,11" name="t.e" dtype_id="11"/>
+          <varref loc="d,64,10,64,11" name="__Vdly__t.e" dtype_id="11"/>
         </assignpre>
         <assignpre loc="d,61,7,61,10" dtype_id="4">
           <varref loc="d,61,7,61,10" name="t.cyc" dtype_id="4"/>
@@ -687,87 +693,87 @@
         </assignpre>
         <assigndly loc="d,61,11,61,13" dtype_id="4">
           <add loc="d,61,18,61,19" dtype_id="4">
-            <ccast loc="d,61,20,61,21" dtype_id="13">
-              <const loc="d,61,20,61,21" name="32&apos;sh1" dtype_id="7"/>
+            <ccast loc="d,61,20,61,21" dtype_id="14">
+              <const loc="d,61,20,61,21" name="32&apos;sh1" dtype_id="8"/>
             </ccast>
             <varref loc="d,61,14,61,17" name="t.cyc" dtype_id="4"/>
           </add>
           <varref loc="d,61,7,61,10" name="__Vdly__t.cyc" dtype_id="4"/>
         </assigndly>
         <if loc="d,62,7,62,9">
-          <eq loc="d,62,14,62,16" dtype_id="8">
-            <const loc="d,62,16,62,17" name="32&apos;sh0" dtype_id="7"/>
+          <eq loc="d,62,14,62,16" dtype_id="9">
+            <const loc="d,62,16,62,17" name="32&apos;sh0" dtype_id="8"/>
             <varref loc="d,62,11,62,14" name="t.cyc" dtype_id="4"/>
           </eq>
           <begin>
-            <assigndly loc="d,64,12,64,14" dtype_id="10">
-              <const loc="d,64,15,64,18" name="4&apos;h1" dtype_id="10"/>
-              <varref loc="d,64,10,64,11" name="__Vdly__t.e" dtype_id="10"/>
+            <assigndly loc="d,64,12,64,14" dtype_id="11">
+              <const loc="d,64,15,64,18" name="4&apos;h1" dtype_id="11"/>
+              <varref loc="d,64,10,64,11" name="__Vdly__t.e" dtype_id="11"/>
             </assigndly>
           </begin>
           <begin>
             <if loc="d,66,12,66,14">
-              <eq loc="d,66,19,66,21" dtype_id="8">
-                <const loc="d,66,21,66,22" name="32&apos;sh1" dtype_id="7"/>
+              <eq loc="d,66,19,66,21" dtype_id="9">
+                <const loc="d,66,21,66,22" name="32&apos;sh1" dtype_id="8"/>
                 <varref loc="d,66,16,66,19" name="t.cyc" dtype_id="4"/>
               </eq>
               <begin>
                 <if loc="d,67,13,67,15">
-                  <neqn loc="d,67,26,67,29" dtype_id="8">
-                    <const loc="d,67,31,67,36" name="&quot;E01&quot;" dtype_id="9"/>
-                    <arraysel loc="d,67,20,67,24" dtype_id="9">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="15"/>
-                      <and loc="d,67,20,67,24" dtype_id="12">
-                        <const loc="d,67,20,67,24" name="32&apos;h7" dtype_id="13"/>
-                        <ccast loc="d,67,18,67,19" dtype_id="12">
-                          <varref loc="d,67,18,67,19" name="t.e" dtype_id="12"/>
+                  <neqn loc="d,67,26,67,29" dtype_id="9">
+                    <const loc="d,67,31,67,36" name="&quot;E01&quot;" dtype_id="10"/>
+                    <arraysel loc="d,67,20,67,24" dtype_id="10">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16"/>
+                      <and loc="d,67,20,67,24" dtype_id="13">
+                        <const loc="d,67,20,67,24" name="32&apos;h7" dtype_id="14"/>
+                        <ccast loc="d,67,18,67,19" dtype_id="13">
+                          <varref loc="d,67,18,67,19" name="t.e" dtype_id="13"/>
                         </ccast>
                       </and>
                     </arraysel>
                   </neqn>
                   <begin>
-                    <assign loc="d,67,126,67,130" dtype_id="9">
-                      <arraysel loc="d,67,126,67,130" dtype_id="9">
-                        <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="15"/>
-                        <and loc="d,67,126,67,130" dtype_id="12">
-                          <const loc="d,67,126,67,130" name="32&apos;h7" dtype_id="13"/>
-                          <ccast loc="d,67,124,67,125" dtype_id="12">
-                            <varref loc="d,67,124,67,125" name="t.e" dtype_id="12"/>
+                    <assign loc="d,67,126,67,130" dtype_id="10">
+                      <arraysel loc="d,67,126,67,130" dtype_id="10">
+                        <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16"/>
+                        <and loc="d,67,126,67,130" dtype_id="13">
+                          <const loc="d,67,126,67,130" name="32&apos;h7" dtype_id="14"/>
+                          <ccast loc="d,67,124,67,125" dtype_id="13">
+                            <varref loc="d,67,124,67,125" name="t.e" dtype_id="13"/>
                           </ccast>
                         </and>
                       </arraysel>
-                      <varref loc="d,67,126,67,130" name="__Vtemp_h########__0" dtype_id="9"/>
+                      <varref loc="d,67,126,67,130" name="__Vtemp_h########__0" dtype_id="10"/>
                     </assign>
                     <display loc="d,67,45,67,51" displaytype="$write">
-                      <sformatf loc="d,67,45,67,51" name="%%Error: t/t_enum_type_methods.v:67:  got=&apos;%@&apos; exp=&apos;E01&apos;&#10;" dtype_id="9">
-                        <varref loc="d,67,126,67,130" name="__Vtemp_h########__0" dtype_id="9"/>
+                      <sformatf loc="d,67,45,67,51" name="%%Error: t/t_enum_type_methods.v:67:  got=&apos;%@&apos; exp=&apos;E01&apos;&#10;" dtype_id="10">
+                        <varref loc="d,67,126,67,130" name="__Vtemp_h########__0" dtype_id="10"/>
                       </sformatf>
                     </display>
                     <stop loc="d,67,143,67,148"/>
                   </begin>
                 </if>
                 <if loc="d,68,13,68,15">
-                  <neq loc="d,68,26,68,29" dtype_id="8">
-                    <const loc="d,68,31,68,34" name="4&apos;h3" dtype_id="10"/>
-                    <arraysel loc="d,68,20,68,24" dtype_id="10">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                      <and loc="d,68,20,68,24" dtype_id="12">
-                        <const loc="d,68,20,68,24" name="32&apos;h7" dtype_id="13"/>
-                        <ccast loc="d,68,18,68,19" dtype_id="12">
-                          <varref loc="d,68,18,68,19" name="t.e" dtype_id="12"/>
+                  <neq loc="d,68,26,68,29" dtype_id="9">
+                    <const loc="d,68,31,68,34" name="4&apos;h3" dtype_id="11"/>
+                    <arraysel loc="d,68,20,68,24" dtype_id="11">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                      <and loc="d,68,20,68,24" dtype_id="13">
+                        <const loc="d,68,20,68,24" name="32&apos;h7" dtype_id="14"/>
+                        <ccast loc="d,68,18,68,19" dtype_id="13">
+                          <varref loc="d,68,18,68,19" name="t.e" dtype_id="13"/>
                         </ccast>
                       </and>
                     </arraysel>
                   </neq>
                   <begin>
                     <display loc="d,68,43,68,49" displaytype="$write">
-                      <sformatf loc="d,68,43,68,49" name="%%Error: t/t_enum_type_methods.v:68:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
-                        <arraysel loc="d,68,124,68,128" dtype_id="10">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                          <and loc="d,68,124,68,128" dtype_id="12">
-                            <const loc="d,68,124,68,128" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,68,122,68,123" dtype_id="12">
-                              <varref loc="d,68,122,68,123" name="t.e" dtype_id="12"/>
+                      <sformatf loc="d,68,43,68,49" name="%%Error: t/t_enum_type_methods.v:68:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="10">
+                        <arraysel loc="d,68,124,68,128" dtype_id="11">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                          <and loc="d,68,124,68,128" dtype_id="13">
+                            <const loc="d,68,124,68,128" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,68,122,68,123" dtype_id="13">
+                              <varref loc="d,68,122,68,123" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
@@ -777,27 +783,27 @@
                   </begin>
                 </if>
                 <if loc="d,69,13,69,15">
-                  <neq loc="d,69,29,69,32" dtype_id="8">
-                    <const loc="d,69,34,69,37" name="4&apos;h3" dtype_id="10"/>
-                    <arraysel loc="d,69,20,69,24" dtype_id="10">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                      <and loc="d,69,20,69,24" dtype_id="12">
-                        <const loc="d,69,20,69,24" name="32&apos;h7" dtype_id="13"/>
-                        <ccast loc="d,69,18,69,19" dtype_id="12">
-                          <varref loc="d,69,18,69,19" name="t.e" dtype_id="12"/>
+                  <neq loc="d,69,29,69,32" dtype_id="9">
+                    <const loc="d,69,34,69,37" name="4&apos;h3" dtype_id="11"/>
+                    <arraysel loc="d,69,20,69,24" dtype_id="11">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                      <and loc="d,69,20,69,24" dtype_id="13">
+                        <const loc="d,69,20,69,24" name="32&apos;h7" dtype_id="14"/>
+                        <ccast loc="d,69,18,69,19" dtype_id="13">
+                          <varref loc="d,69,18,69,19" name="t.e" dtype_id="13"/>
                         </ccast>
                       </and>
                     </arraysel>
                   </neq>
                   <begin>
                     <display loc="d,69,46,69,52" displaytype="$write">
-                      <sformatf loc="d,69,46,69,52" name="%%Error: t/t_enum_type_methods.v:69:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
-                        <arraysel loc="d,69,127,69,131" dtype_id="10">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                          <and loc="d,69,127,69,131" dtype_id="12">
-                            <const loc="d,69,127,69,131" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,69,125,69,126" dtype_id="12">
-                              <varref loc="d,69,125,69,126" name="t.e" dtype_id="12"/>
+                      <sformatf loc="d,69,46,69,52" name="%%Error: t/t_enum_type_methods.v:69:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="10">
+                        <arraysel loc="d,69,127,69,131" dtype_id="11">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                          <and loc="d,69,127,69,131" dtype_id="13">
+                            <const loc="d,69,127,69,131" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,69,125,69,126" dtype_id="13">
+                              <varref loc="d,69,125,69,126" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
@@ -807,18 +813,18 @@
                   </begin>
                 </if>
                 <if loc="d,70,13,70,15">
-                  <neq loc="d,70,29,70,32" dtype_id="8">
-                    <const loc="d,70,34,70,37" name="4&apos;h4" dtype_id="10"/>
-                    <arraysel loc="d,70,20,70,24" dtype_id="10">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                      <and loc="d,70,20,70,24" dtype_id="12">
-                        <const loc="d,70,20,70,24" name="32&apos;h7" dtype_id="13"/>
-                        <arraysel loc="d,70,20,70,24" dtype_id="12">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                          <and loc="d,70,20,70,24" dtype_id="12">
-                            <const loc="d,70,20,70,24" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,70,18,70,19" dtype_id="12">
-                              <varref loc="d,70,18,70,19" name="t.e" dtype_id="12"/>
+                  <neq loc="d,70,29,70,32" dtype_id="9">
+                    <const loc="d,70,34,70,37" name="4&apos;h4" dtype_id="11"/>
+                    <arraysel loc="d,70,20,70,24" dtype_id="11">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                      <and loc="d,70,20,70,24" dtype_id="13">
+                        <const loc="d,70,20,70,24" name="32&apos;h7" dtype_id="14"/>
+                        <arraysel loc="d,70,20,70,24" dtype_id="13">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                          <and loc="d,70,20,70,24" dtype_id="13">
+                            <const loc="d,70,20,70,24" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,70,18,70,19" dtype_id="13">
+                              <varref loc="d,70,18,70,19" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
@@ -827,17 +833,17 @@
                   </neq>
                   <begin>
                     <display loc="d,70,46,70,52" displaytype="$write">
-                      <sformatf loc="d,70,46,70,52" name="%%Error: t/t_enum_type_methods.v:70:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
-                        <arraysel loc="d,70,127,70,131" dtype_id="10">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                          <and loc="d,70,127,70,131" dtype_id="12">
-                            <const loc="d,70,127,70,131" name="32&apos;h7" dtype_id="13"/>
-                            <arraysel loc="d,70,127,70,131" dtype_id="12">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                              <and loc="d,70,127,70,131" dtype_id="12">
-                                <const loc="d,70,127,70,131" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,70,125,70,126" dtype_id="12">
-                                  <varref loc="d,70,125,70,126" name="t.e" dtype_id="12"/>
+                      <sformatf loc="d,70,46,70,52" name="%%Error: t/t_enum_type_methods.v:70:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="10">
+                        <arraysel loc="d,70,127,70,131" dtype_id="11">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                          <and loc="d,70,127,70,131" dtype_id="13">
+                            <const loc="d,70,127,70,131" name="32&apos;h7" dtype_id="14"/>
+                            <arraysel loc="d,70,127,70,131" dtype_id="13">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                              <and loc="d,70,127,70,131" dtype_id="13">
+                                <const loc="d,70,127,70,131" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,70,125,70,126" dtype_id="13">
+                                  <varref loc="d,70,125,70,126" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
@@ -849,27 +855,27 @@
                   </begin>
                 </if>
                 <if loc="d,71,13,71,15">
-                  <neq loc="d,71,26,71,29" dtype_id="8">
-                    <const loc="d,71,31,71,34" name="4&apos;h4" dtype_id="10"/>
-                    <arraysel loc="d,71,20,71,24" dtype_id="10">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                      <and loc="d,71,20,71,24" dtype_id="12">
-                        <const loc="d,71,20,71,24" name="32&apos;h7" dtype_id="13"/>
-                        <ccast loc="d,71,18,71,19" dtype_id="12">
-                          <varref loc="d,71,18,71,19" name="t.e" dtype_id="12"/>
+                  <neq loc="d,71,26,71,29" dtype_id="9">
+                    <const loc="d,71,31,71,34" name="4&apos;h4" dtype_id="11"/>
+                    <arraysel loc="d,71,20,71,24" dtype_id="11">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                      <and loc="d,71,20,71,24" dtype_id="13">
+                        <const loc="d,71,20,71,24" name="32&apos;h7" dtype_id="14"/>
+                        <ccast loc="d,71,18,71,19" dtype_id="13">
+                          <varref loc="d,71,18,71,19" name="t.e" dtype_id="13"/>
                         </ccast>
                       </and>
                     </arraysel>
                   </neq>
                   <begin>
                     <display loc="d,71,43,71,49" displaytype="$write">
-                      <sformatf loc="d,71,43,71,49" name="%%Error: t/t_enum_type_methods.v:71:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
-                        <arraysel loc="d,71,124,71,128" dtype_id="10">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                          <and loc="d,71,124,71,128" dtype_id="12">
-                            <const loc="d,71,124,71,128" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,71,122,71,123" dtype_id="12">
-                              <varref loc="d,71,122,71,123" name="t.e" dtype_id="12"/>
+                      <sformatf loc="d,71,43,71,49" name="%%Error: t/t_enum_type_methods.v:71:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="10">
+                        <arraysel loc="d,71,124,71,128" dtype_id="11">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                          <and loc="d,71,124,71,128" dtype_id="13">
+                            <const loc="d,71,124,71,128" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,71,122,71,123" dtype_id="13">
+                              <varref loc="d,71,122,71,123" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
@@ -879,27 +885,27 @@
                   </begin>
                 </if>
                 <if loc="d,72,13,72,15">
-                  <neq loc="d,72,29,72,32" dtype_id="8">
-                    <const loc="d,72,34,72,37" name="4&apos;h4" dtype_id="10"/>
-                    <arraysel loc="d,72,20,72,24" dtype_id="10">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                      <and loc="d,72,20,72,24" dtype_id="12">
-                        <const loc="d,72,20,72,24" name="32&apos;h7" dtype_id="13"/>
-                        <ccast loc="d,72,18,72,19" dtype_id="12">
-                          <varref loc="d,72,18,72,19" name="t.e" dtype_id="12"/>
+                  <neq loc="d,72,29,72,32" dtype_id="9">
+                    <const loc="d,72,34,72,37" name="4&apos;h4" dtype_id="11"/>
+                    <arraysel loc="d,72,20,72,24" dtype_id="11">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                      <and loc="d,72,20,72,24" dtype_id="13">
+                        <const loc="d,72,20,72,24" name="32&apos;h7" dtype_id="14"/>
+                        <ccast loc="d,72,18,72,19" dtype_id="13">
+                          <varref loc="d,72,18,72,19" name="t.e" dtype_id="13"/>
                         </ccast>
                       </and>
                     </arraysel>
                   </neq>
                   <begin>
                     <display loc="d,72,46,72,52" displaytype="$write">
-                      <sformatf loc="d,72,46,72,52" name="%%Error: t/t_enum_type_methods.v:72:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
-                        <arraysel loc="d,72,127,72,131" dtype_id="10">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                          <and loc="d,72,127,72,131" dtype_id="12">
-                            <const loc="d,72,127,72,131" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,72,125,72,126" dtype_id="12">
-                              <varref loc="d,72,125,72,126" name="t.e" dtype_id="12"/>
+                      <sformatf loc="d,72,46,72,52" name="%%Error: t/t_enum_type_methods.v:72:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="10">
+                        <arraysel loc="d,72,127,72,131" dtype_id="11">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                          <and loc="d,72,127,72,131" dtype_id="13">
+                            <const loc="d,72,127,72,131" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,72,125,72,126" dtype_id="13">
+                              <varref loc="d,72,125,72,126" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
@@ -909,18 +915,18 @@
                   </begin>
                 </if>
                 <if loc="d,73,13,73,15">
-                  <neq loc="d,73,29,73,32" dtype_id="8">
-                    <const loc="d,73,34,73,37" name="4&apos;h3" dtype_id="10"/>
-                    <arraysel loc="d,73,20,73,24" dtype_id="10">
-                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                      <and loc="d,73,20,73,24" dtype_id="12">
-                        <const loc="d,73,20,73,24" name="32&apos;h7" dtype_id="13"/>
-                        <arraysel loc="d,73,20,73,24" dtype_id="12">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                          <and loc="d,73,20,73,24" dtype_id="12">
-                            <const loc="d,73,20,73,24" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,73,18,73,19" dtype_id="12">
-                              <varref loc="d,73,18,73,19" name="t.e" dtype_id="12"/>
+                  <neq loc="d,73,29,73,32" dtype_id="9">
+                    <const loc="d,73,34,73,37" name="4&apos;h3" dtype_id="11"/>
+                    <arraysel loc="d,73,20,73,24" dtype_id="11">
+                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                      <and loc="d,73,20,73,24" dtype_id="13">
+                        <const loc="d,73,20,73,24" name="32&apos;h7" dtype_id="14"/>
+                        <arraysel loc="d,73,20,73,24" dtype_id="13">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                          <and loc="d,73,20,73,24" dtype_id="13">
+                            <const loc="d,73,20,73,24" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,73,18,73,19" dtype_id="13">
+                              <varref loc="d,73,18,73,19" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
@@ -929,17 +935,17 @@
                   </neq>
                   <begin>
                     <display loc="d,73,46,73,52" displaytype="$write">
-                      <sformatf loc="d,73,46,73,52" name="%%Error: t/t_enum_type_methods.v:73:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
-                        <arraysel loc="d,73,127,73,131" dtype_id="10">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                          <and loc="d,73,127,73,131" dtype_id="12">
-                            <const loc="d,73,127,73,131" name="32&apos;h7" dtype_id="13"/>
-                            <arraysel loc="d,73,127,73,131" dtype_id="12">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                              <and loc="d,73,127,73,131" dtype_id="12">
-                                <const loc="d,73,127,73,131" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,73,125,73,126" dtype_id="12">
-                                  <varref loc="d,73,125,73,126" name="t.e" dtype_id="12"/>
+                      <sformatf loc="d,73,46,73,52" name="%%Error: t/t_enum_type_methods.v:73:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="10">
+                        <arraysel loc="d,73,127,73,131" dtype_id="11">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                          <and loc="d,73,127,73,131" dtype_id="13">
+                            <const loc="d,73,127,73,131" name="32&apos;h7" dtype_id="14"/>
+                            <arraysel loc="d,73,127,73,131" dtype_id="13">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                              <and loc="d,73,127,73,131" dtype_id="13">
+                                <const loc="d,73,127,73,131" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,73,125,73,126" dtype_id="13">
+                                  <varref loc="d,73,125,73,126" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
@@ -950,74 +956,74 @@
                     <stop loc="d,73,145,73,150"/>
                   </begin>
                 </if>
-                <assigndly loc="d,74,12,74,14" dtype_id="10">
-                  <const loc="d,74,15,74,18" name="4&apos;h3" dtype_id="10"/>
-                  <varref loc="d,74,10,74,11" name="__Vdly__t.e" dtype_id="10"/>
+                <assigndly loc="d,74,12,74,14" dtype_id="11">
+                  <const loc="d,74,15,74,18" name="4&apos;h3" dtype_id="11"/>
+                  <varref loc="d,74,10,74,11" name="__Vdly__t.e" dtype_id="11"/>
                 </assigndly>
               </begin>
               <begin>
                 <if loc="d,76,12,76,14">
-                  <eq loc="d,76,19,76,21" dtype_id="8">
-                    <const loc="d,76,21,76,22" name="32&apos;sh2" dtype_id="7"/>
+                  <eq loc="d,76,19,76,21" dtype_id="9">
+                    <const loc="d,76,21,76,22" name="32&apos;sh2" dtype_id="8"/>
                     <varref loc="d,76,16,76,19" name="t.cyc" dtype_id="4"/>
                   </eq>
                   <begin>
                     <if loc="d,77,13,77,15">
-                      <neqn loc="d,77,26,77,29" dtype_id="8">
-                        <const loc="d,77,31,77,36" name="&quot;E03&quot;" dtype_id="9"/>
-                        <arraysel loc="d,77,20,77,24" dtype_id="9">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="15"/>
-                          <and loc="d,77,20,77,24" dtype_id="12">
-                            <const loc="d,77,20,77,24" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,77,18,77,19" dtype_id="12">
-                              <varref loc="d,77,18,77,19" name="t.e" dtype_id="12"/>
+                      <neqn loc="d,77,26,77,29" dtype_id="9">
+                        <const loc="d,77,31,77,36" name="&quot;E03&quot;" dtype_id="10"/>
+                        <arraysel loc="d,77,20,77,24" dtype_id="10">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16"/>
+                          <and loc="d,77,20,77,24" dtype_id="13">
+                            <const loc="d,77,20,77,24" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,77,18,77,19" dtype_id="13">
+                              <varref loc="d,77,18,77,19" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
                       </neqn>
                       <begin>
-                        <assign loc="d,77,126,77,130" dtype_id="9">
-                          <arraysel loc="d,77,126,77,130" dtype_id="9">
-                            <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="15"/>
-                            <and loc="d,77,126,77,130" dtype_id="12">
-                              <const loc="d,77,126,77,130" name="32&apos;h7" dtype_id="13"/>
-                              <ccast loc="d,77,124,77,125" dtype_id="12">
-                                <varref loc="d,77,124,77,125" name="t.e" dtype_id="12"/>
+                        <assign loc="d,77,126,77,130" dtype_id="10">
+                          <arraysel loc="d,77,126,77,130" dtype_id="10">
+                            <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16"/>
+                            <and loc="d,77,126,77,130" dtype_id="13">
+                              <const loc="d,77,126,77,130" name="32&apos;h7" dtype_id="14"/>
+                              <ccast loc="d,77,124,77,125" dtype_id="13">
+                                <varref loc="d,77,124,77,125" name="t.e" dtype_id="13"/>
                               </ccast>
                             </and>
                           </arraysel>
-                          <varref loc="d,77,126,77,130" name="__Vtemp_h########__1" dtype_id="9"/>
+                          <varref loc="d,77,126,77,130" name="__Vtemp_h########__1" dtype_id="10"/>
                         </assign>
                         <display loc="d,77,45,77,51" displaytype="$write">
-                          <sformatf loc="d,77,45,77,51" name="%%Error: t/t_enum_type_methods.v:77:  got=&apos;%@&apos; exp=&apos;E03&apos;&#10;" dtype_id="9">
-                            <varref loc="d,77,126,77,130" name="__Vtemp_h########__1" dtype_id="9"/>
+                          <sformatf loc="d,77,45,77,51" name="%%Error: t/t_enum_type_methods.v:77:  got=&apos;%@&apos; exp=&apos;E03&apos;&#10;" dtype_id="10">
+                            <varref loc="d,77,126,77,130" name="__Vtemp_h########__1" dtype_id="10"/>
                           </sformatf>
                         </display>
                         <stop loc="d,77,143,77,148"/>
                       </begin>
                     </if>
                     <if loc="d,78,13,78,15">
-                      <neq loc="d,78,26,78,29" dtype_id="8">
-                        <const loc="d,78,31,78,34" name="4&apos;h4" dtype_id="10"/>
-                        <arraysel loc="d,78,20,78,24" dtype_id="10">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                          <and loc="d,78,20,78,24" dtype_id="12">
-                            <const loc="d,78,20,78,24" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,78,18,78,19" dtype_id="12">
-                              <varref loc="d,78,18,78,19" name="t.e" dtype_id="12"/>
+                      <neq loc="d,78,26,78,29" dtype_id="9">
+                        <const loc="d,78,31,78,34" name="4&apos;h4" dtype_id="11"/>
+                        <arraysel loc="d,78,20,78,24" dtype_id="11">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                          <and loc="d,78,20,78,24" dtype_id="13">
+                            <const loc="d,78,20,78,24" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,78,18,78,19" dtype_id="13">
+                              <varref loc="d,78,18,78,19" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
                       </neq>
                       <begin>
                         <display loc="d,78,43,78,49" displaytype="$write">
-                          <sformatf loc="d,78,43,78,49" name="%%Error: t/t_enum_type_methods.v:78:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
-                            <arraysel loc="d,78,124,78,128" dtype_id="10">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                              <and loc="d,78,124,78,128" dtype_id="12">
-                                <const loc="d,78,124,78,128" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,78,122,78,123" dtype_id="12">
-                                  <varref loc="d,78,122,78,123" name="t.e" dtype_id="12"/>
+                          <sformatf loc="d,78,43,78,49" name="%%Error: t/t_enum_type_methods.v:78:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="10">
+                            <arraysel loc="d,78,124,78,128" dtype_id="11">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                              <and loc="d,78,124,78,128" dtype_id="13">
+                                <const loc="d,78,124,78,128" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,78,122,78,123" dtype_id="13">
+                                  <varref loc="d,78,122,78,123" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
@@ -1027,27 +1033,27 @@
                       </begin>
                     </if>
                     <if loc="d,79,13,79,15">
-                      <neq loc="d,79,29,79,32" dtype_id="8">
-                        <const loc="d,79,34,79,37" name="4&apos;h4" dtype_id="10"/>
-                        <arraysel loc="d,79,20,79,24" dtype_id="10">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                          <and loc="d,79,20,79,24" dtype_id="12">
-                            <const loc="d,79,20,79,24" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,79,18,79,19" dtype_id="12">
-                              <varref loc="d,79,18,79,19" name="t.e" dtype_id="12"/>
+                      <neq loc="d,79,29,79,32" dtype_id="9">
+                        <const loc="d,79,34,79,37" name="4&apos;h4" dtype_id="11"/>
+                        <arraysel loc="d,79,20,79,24" dtype_id="11">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                          <and loc="d,79,20,79,24" dtype_id="13">
+                            <const loc="d,79,20,79,24" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,79,18,79,19" dtype_id="13">
+                              <varref loc="d,79,18,79,19" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
                       </neq>
                       <begin>
                         <display loc="d,79,46,79,52" displaytype="$write">
-                          <sformatf loc="d,79,46,79,52" name="%%Error: t/t_enum_type_methods.v:79:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
-                            <arraysel loc="d,79,127,79,131" dtype_id="10">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                              <and loc="d,79,127,79,131" dtype_id="12">
-                                <const loc="d,79,127,79,131" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,79,125,79,126" dtype_id="12">
-                                  <varref loc="d,79,125,79,126" name="t.e" dtype_id="12"/>
+                          <sformatf loc="d,79,46,79,52" name="%%Error: t/t_enum_type_methods.v:79:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="10">
+                            <arraysel loc="d,79,127,79,131" dtype_id="11">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                              <and loc="d,79,127,79,131" dtype_id="13">
+                                <const loc="d,79,127,79,131" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,79,125,79,126" dtype_id="13">
+                                  <varref loc="d,79,125,79,126" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
@@ -1057,18 +1063,18 @@
                       </begin>
                     </if>
                     <if loc="d,80,13,80,15">
-                      <neq loc="d,80,29,80,32" dtype_id="8">
-                        <const loc="d,80,34,80,37" name="4&apos;h1" dtype_id="10"/>
-                        <arraysel loc="d,80,20,80,24" dtype_id="10">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                          <and loc="d,80,20,80,24" dtype_id="12">
-                            <const loc="d,80,20,80,24" name="32&apos;h7" dtype_id="13"/>
-                            <arraysel loc="d,80,20,80,24" dtype_id="12">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                              <and loc="d,80,20,80,24" dtype_id="12">
-                                <const loc="d,80,20,80,24" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,80,18,80,19" dtype_id="12">
-                                  <varref loc="d,80,18,80,19" name="t.e" dtype_id="12"/>
+                      <neq loc="d,80,29,80,32" dtype_id="9">
+                        <const loc="d,80,34,80,37" name="4&apos;h1" dtype_id="11"/>
+                        <arraysel loc="d,80,20,80,24" dtype_id="11">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                          <and loc="d,80,20,80,24" dtype_id="13">
+                            <const loc="d,80,20,80,24" name="32&apos;h7" dtype_id="14"/>
+                            <arraysel loc="d,80,20,80,24" dtype_id="13">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                              <and loc="d,80,20,80,24" dtype_id="13">
+                                <const loc="d,80,20,80,24" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,80,18,80,19" dtype_id="13">
+                                  <varref loc="d,80,18,80,19" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
@@ -1077,17 +1083,17 @@
                       </neq>
                       <begin>
                         <display loc="d,80,46,80,52" displaytype="$write">
-                          <sformatf loc="d,80,46,80,52" name="%%Error: t/t_enum_type_methods.v:80:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
-                            <arraysel loc="d,80,127,80,131" dtype_id="10">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                              <and loc="d,80,127,80,131" dtype_id="12">
-                                <const loc="d,80,127,80,131" name="32&apos;h7" dtype_id="13"/>
-                                <arraysel loc="d,80,127,80,131" dtype_id="12">
-                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                                  <and loc="d,80,127,80,131" dtype_id="12">
-                                    <const loc="d,80,127,80,131" name="32&apos;h7" dtype_id="13"/>
-                                    <ccast loc="d,80,125,80,126" dtype_id="12">
-                                      <varref loc="d,80,125,80,126" name="t.e" dtype_id="12"/>
+                          <sformatf loc="d,80,46,80,52" name="%%Error: t/t_enum_type_methods.v:80:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="10">
+                            <arraysel loc="d,80,127,80,131" dtype_id="11">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                              <and loc="d,80,127,80,131" dtype_id="13">
+                                <const loc="d,80,127,80,131" name="32&apos;h7" dtype_id="14"/>
+                                <arraysel loc="d,80,127,80,131" dtype_id="13">
+                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                                  <and loc="d,80,127,80,131" dtype_id="13">
+                                    <const loc="d,80,127,80,131" name="32&apos;h7" dtype_id="14"/>
+                                    <ccast loc="d,80,125,80,126" dtype_id="13">
+                                      <varref loc="d,80,125,80,126" name="t.e" dtype_id="13"/>
                                     </ccast>
                                   </and>
                                 </arraysel>
@@ -1099,27 +1105,27 @@
                       </begin>
                     </if>
                     <if loc="d,81,13,81,15">
-                      <neq loc="d,81,26,81,29" dtype_id="8">
-                        <const loc="d,81,31,81,34" name="4&apos;h1" dtype_id="10"/>
-                        <arraysel loc="d,81,20,81,24" dtype_id="10">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                          <and loc="d,81,20,81,24" dtype_id="12">
-                            <const loc="d,81,20,81,24" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,81,18,81,19" dtype_id="12">
-                              <varref loc="d,81,18,81,19" name="t.e" dtype_id="12"/>
+                      <neq loc="d,81,26,81,29" dtype_id="9">
+                        <const loc="d,81,31,81,34" name="4&apos;h1" dtype_id="11"/>
+                        <arraysel loc="d,81,20,81,24" dtype_id="11">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                          <and loc="d,81,20,81,24" dtype_id="13">
+                            <const loc="d,81,20,81,24" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,81,18,81,19" dtype_id="13">
+                              <varref loc="d,81,18,81,19" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
                       </neq>
                       <begin>
                         <display loc="d,81,43,81,49" displaytype="$write">
-                          <sformatf loc="d,81,43,81,49" name="%%Error: t/t_enum_type_methods.v:81:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
-                            <arraysel loc="d,81,124,81,128" dtype_id="10">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                              <and loc="d,81,124,81,128" dtype_id="12">
-                                <const loc="d,81,124,81,128" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,81,122,81,123" dtype_id="12">
-                                  <varref loc="d,81,122,81,123" name="t.e" dtype_id="12"/>
+                          <sformatf loc="d,81,43,81,49" name="%%Error: t/t_enum_type_methods.v:81:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="10">
+                            <arraysel loc="d,81,124,81,128" dtype_id="11">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                              <and loc="d,81,124,81,128" dtype_id="13">
+                                <const loc="d,81,124,81,128" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,81,122,81,123" dtype_id="13">
+                                  <varref loc="d,81,122,81,123" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
@@ -1129,27 +1135,27 @@
                       </begin>
                     </if>
                     <if loc="d,82,13,82,15">
-                      <neq loc="d,82,29,82,32" dtype_id="8">
-                        <const loc="d,82,34,82,37" name="4&apos;h1" dtype_id="10"/>
-                        <arraysel loc="d,82,20,82,24" dtype_id="10">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                          <and loc="d,82,20,82,24" dtype_id="12">
-                            <const loc="d,82,20,82,24" name="32&apos;h7" dtype_id="13"/>
-                            <ccast loc="d,82,18,82,19" dtype_id="12">
-                              <varref loc="d,82,18,82,19" name="t.e" dtype_id="12"/>
+                      <neq loc="d,82,29,82,32" dtype_id="9">
+                        <const loc="d,82,34,82,37" name="4&apos;h1" dtype_id="11"/>
+                        <arraysel loc="d,82,20,82,24" dtype_id="11">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                          <and loc="d,82,20,82,24" dtype_id="13">
+                            <const loc="d,82,20,82,24" name="32&apos;h7" dtype_id="14"/>
+                            <ccast loc="d,82,18,82,19" dtype_id="13">
+                              <varref loc="d,82,18,82,19" name="t.e" dtype_id="13"/>
                             </ccast>
                           </and>
                         </arraysel>
                       </neq>
                       <begin>
                         <display loc="d,82,46,82,52" displaytype="$write">
-                          <sformatf loc="d,82,46,82,52" name="%%Error: t/t_enum_type_methods.v:82:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
-                            <arraysel loc="d,82,127,82,131" dtype_id="10">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                              <and loc="d,82,127,82,131" dtype_id="12">
-                                <const loc="d,82,127,82,131" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,82,125,82,126" dtype_id="12">
-                                  <varref loc="d,82,125,82,126" name="t.e" dtype_id="12"/>
+                          <sformatf loc="d,82,46,82,52" name="%%Error: t/t_enum_type_methods.v:82:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="10">
+                            <arraysel loc="d,82,127,82,131" dtype_id="11">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                              <and loc="d,82,127,82,131" dtype_id="13">
+                                <const loc="d,82,127,82,131" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,82,125,82,126" dtype_id="13">
+                                  <varref loc="d,82,125,82,126" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
@@ -1159,18 +1165,18 @@
                       </begin>
                     </if>
                     <if loc="d,83,13,83,15">
-                      <neq loc="d,83,29,83,32" dtype_id="8">
-                        <const loc="d,83,34,83,37" name="4&apos;h4" dtype_id="10"/>
-                        <arraysel loc="d,83,20,83,24" dtype_id="10">
-                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                          <and loc="d,83,20,83,24" dtype_id="12">
-                            <const loc="d,83,20,83,24" name="32&apos;h7" dtype_id="13"/>
-                            <arraysel loc="d,83,20,83,24" dtype_id="12">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                              <and loc="d,83,20,83,24" dtype_id="12">
-                                <const loc="d,83,20,83,24" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,83,18,83,19" dtype_id="12">
-                                  <varref loc="d,83,18,83,19" name="t.e" dtype_id="12"/>
+                      <neq loc="d,83,29,83,32" dtype_id="9">
+                        <const loc="d,83,34,83,37" name="4&apos;h4" dtype_id="11"/>
+                        <arraysel loc="d,83,20,83,24" dtype_id="11">
+                          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                          <and loc="d,83,20,83,24" dtype_id="13">
+                            <const loc="d,83,20,83,24" name="32&apos;h7" dtype_id="14"/>
+                            <arraysel loc="d,83,20,83,24" dtype_id="13">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                              <and loc="d,83,20,83,24" dtype_id="13">
+                                <const loc="d,83,20,83,24" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,83,18,83,19" dtype_id="13">
+                                  <varref loc="d,83,18,83,19" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
@@ -1179,17 +1185,17 @@
                       </neq>
                       <begin>
                         <display loc="d,83,46,83,52" displaytype="$write">
-                          <sformatf loc="d,83,46,83,52" name="%%Error: t/t_enum_type_methods.v:83:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="9">
-                            <arraysel loc="d,83,127,83,131" dtype_id="10">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                              <and loc="d,83,127,83,131" dtype_id="12">
-                                <const loc="d,83,127,83,131" name="32&apos;h7" dtype_id="13"/>
-                                <arraysel loc="d,83,127,83,131" dtype_id="12">
-                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                                  <and loc="d,83,127,83,131" dtype_id="12">
-                                    <const loc="d,83,127,83,131" name="32&apos;h7" dtype_id="13"/>
-                                    <ccast loc="d,83,125,83,126" dtype_id="12">
-                                      <varref loc="d,83,125,83,126" name="t.e" dtype_id="12"/>
+                          <sformatf loc="d,83,46,83,52" name="%%Error: t/t_enum_type_methods.v:83:  got=&apos;h%x exp=&apos;h4&#10;" dtype_id="10">
+                            <arraysel loc="d,83,127,83,131" dtype_id="11">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                              <and loc="d,83,127,83,131" dtype_id="13">
+                                <const loc="d,83,127,83,131" name="32&apos;h7" dtype_id="14"/>
+                                <arraysel loc="d,83,127,83,131" dtype_id="13">
+                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                                  <and loc="d,83,127,83,131" dtype_id="13">
+                                    <const loc="d,83,127,83,131" name="32&apos;h7" dtype_id="14"/>
+                                    <ccast loc="d,83,125,83,126" dtype_id="13">
+                                      <varref loc="d,83,125,83,126" name="t.e" dtype_id="13"/>
                                     </ccast>
                                   </and>
                                 </arraysel>
@@ -1200,74 +1206,74 @@
                         <stop loc="d,83,145,83,150"/>
                       </begin>
                     </if>
-                    <assigndly loc="d,84,12,84,14" dtype_id="10">
-                      <const loc="d,84,15,84,18" name="4&apos;h4" dtype_id="10"/>
-                      <varref loc="d,84,10,84,11" name="__Vdly__t.e" dtype_id="10"/>
+                    <assigndly loc="d,84,12,84,14" dtype_id="11">
+                      <const loc="d,84,15,84,18" name="4&apos;h4" dtype_id="11"/>
+                      <varref loc="d,84,10,84,11" name="__Vdly__t.e" dtype_id="11"/>
                     </assigndly>
                   </begin>
                   <begin>
                     <if loc="d,86,12,86,14">
-                      <eq loc="d,86,19,86,21" dtype_id="8">
-                        <const loc="d,86,21,86,22" name="32&apos;sh3" dtype_id="7"/>
+                      <eq loc="d,86,19,86,21" dtype_id="9">
+                        <const loc="d,86,21,86,22" name="32&apos;sh3" dtype_id="8"/>
                         <varref loc="d,86,16,86,19" name="t.cyc" dtype_id="4"/>
                       </eq>
                       <begin>
                         <if loc="d,87,13,87,15">
-                          <neqn loc="d,87,26,87,29" dtype_id="8">
-                            <const loc="d,87,31,87,36" name="&quot;E04&quot;" dtype_id="9"/>
-                            <arraysel loc="d,87,20,87,24" dtype_id="9">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="15"/>
-                              <and loc="d,87,20,87,24" dtype_id="12">
-                                <const loc="d,87,20,87,24" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,87,18,87,19" dtype_id="12">
-                                  <varref loc="d,87,18,87,19" name="t.e" dtype_id="12"/>
+                          <neqn loc="d,87,26,87,29" dtype_id="9">
+                            <const loc="d,87,31,87,36" name="&quot;E04&quot;" dtype_id="10"/>
+                            <arraysel loc="d,87,20,87,24" dtype_id="10">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16"/>
+                              <and loc="d,87,20,87,24" dtype_id="13">
+                                <const loc="d,87,20,87,24" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,87,18,87,19" dtype_id="13">
+                                  <varref loc="d,87,18,87,19" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
                           </neqn>
                           <begin>
-                            <assign loc="d,87,126,87,130" dtype_id="9">
-                              <arraysel loc="d,87,126,87,130" dtype_id="9">
-                                <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="15"/>
-                                <and loc="d,87,126,87,130" dtype_id="12">
-                                  <const loc="d,87,126,87,130" name="32&apos;h7" dtype_id="13"/>
-                                  <ccast loc="d,87,124,87,125" dtype_id="12">
-                                    <varref loc="d,87,124,87,125" name="t.e" dtype_id="12"/>
+                            <assign loc="d,87,126,87,130" dtype_id="10">
+                              <arraysel loc="d,87,126,87,130" dtype_id="10">
+                                <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16"/>
+                                <and loc="d,87,126,87,130" dtype_id="13">
+                                  <const loc="d,87,126,87,130" name="32&apos;h7" dtype_id="14"/>
+                                  <ccast loc="d,87,124,87,125" dtype_id="13">
+                                    <varref loc="d,87,124,87,125" name="t.e" dtype_id="13"/>
                                   </ccast>
                                 </and>
                               </arraysel>
-                              <varref loc="d,87,126,87,130" name="__Vtemp_h########__2" dtype_id="9"/>
+                              <varref loc="d,87,126,87,130" name="__Vtemp_h########__2" dtype_id="10"/>
                             </assign>
                             <display loc="d,87,45,87,51" displaytype="$write">
-                              <sformatf loc="d,87,45,87,51" name="%%Error: t/t_enum_type_methods.v:87:  got=&apos;%@&apos; exp=&apos;E04&apos;&#10;" dtype_id="9">
-                                <varref loc="d,87,126,87,130" name="__Vtemp_h########__2" dtype_id="9"/>
+                              <sformatf loc="d,87,45,87,51" name="%%Error: t/t_enum_type_methods.v:87:  got=&apos;%@&apos; exp=&apos;E04&apos;&#10;" dtype_id="10">
+                                <varref loc="d,87,126,87,130" name="__Vtemp_h########__2" dtype_id="10"/>
                               </sformatf>
                             </display>
                             <stop loc="d,87,143,87,148"/>
                           </begin>
                         </if>
                         <if loc="d,88,13,88,15">
-                          <neq loc="d,88,26,88,29" dtype_id="8">
-                            <const loc="d,88,31,88,34" name="4&apos;h1" dtype_id="10"/>
-                            <arraysel loc="d,88,20,88,24" dtype_id="10">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                              <and loc="d,88,20,88,24" dtype_id="12">
-                                <const loc="d,88,20,88,24" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,88,18,88,19" dtype_id="12">
-                                  <varref loc="d,88,18,88,19" name="t.e" dtype_id="12"/>
+                          <neq loc="d,88,26,88,29" dtype_id="9">
+                            <const loc="d,88,31,88,34" name="4&apos;h1" dtype_id="11"/>
+                            <arraysel loc="d,88,20,88,24" dtype_id="11">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                              <and loc="d,88,20,88,24" dtype_id="13">
+                                <const loc="d,88,20,88,24" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,88,18,88,19" dtype_id="13">
+                                  <varref loc="d,88,18,88,19" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
                           </neq>
                           <begin>
                             <display loc="d,88,43,88,49" displaytype="$write">
-                              <sformatf loc="d,88,43,88,49" name="%%Error: t/t_enum_type_methods.v:88:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
-                                <arraysel loc="d,88,124,88,128" dtype_id="10">
-                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                                  <and loc="d,88,124,88,128" dtype_id="12">
-                                    <const loc="d,88,124,88,128" name="32&apos;h7" dtype_id="13"/>
-                                    <ccast loc="d,88,122,88,123" dtype_id="12">
-                                      <varref loc="d,88,122,88,123" name="t.e" dtype_id="12"/>
+                              <sformatf loc="d,88,43,88,49" name="%%Error: t/t_enum_type_methods.v:88:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="10">
+                                <arraysel loc="d,88,124,88,128" dtype_id="11">
+                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                                  <and loc="d,88,124,88,128" dtype_id="13">
+                                    <const loc="d,88,124,88,128" name="32&apos;h7" dtype_id="14"/>
+                                    <ccast loc="d,88,122,88,123" dtype_id="13">
+                                      <varref loc="d,88,122,88,123" name="t.e" dtype_id="13"/>
                                     </ccast>
                                   </and>
                                 </arraysel>
@@ -1277,27 +1283,27 @@
                           </begin>
                         </if>
                         <if loc="d,89,13,89,15">
-                          <neq loc="d,89,29,89,32" dtype_id="8">
-                            <const loc="d,89,34,89,37" name="4&apos;h1" dtype_id="10"/>
-                            <arraysel loc="d,89,20,89,24" dtype_id="10">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                              <and loc="d,89,20,89,24" dtype_id="12">
-                                <const loc="d,89,20,89,24" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,89,18,89,19" dtype_id="12">
-                                  <varref loc="d,89,18,89,19" name="t.e" dtype_id="12"/>
+                          <neq loc="d,89,29,89,32" dtype_id="9">
+                            <const loc="d,89,34,89,37" name="4&apos;h1" dtype_id="11"/>
+                            <arraysel loc="d,89,20,89,24" dtype_id="11">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                              <and loc="d,89,20,89,24" dtype_id="13">
+                                <const loc="d,89,20,89,24" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,89,18,89,19" dtype_id="13">
+                                  <varref loc="d,89,18,89,19" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
                           </neq>
                           <begin>
                             <display loc="d,89,46,89,52" displaytype="$write">
-                              <sformatf loc="d,89,46,89,52" name="%%Error: t/t_enum_type_methods.v:89:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
-                                <arraysel loc="d,89,127,89,131" dtype_id="10">
-                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                                  <and loc="d,89,127,89,131" dtype_id="12">
-                                    <const loc="d,89,127,89,131" name="32&apos;h7" dtype_id="13"/>
-                                    <ccast loc="d,89,125,89,126" dtype_id="12">
-                                      <varref loc="d,89,125,89,126" name="t.e" dtype_id="12"/>
+                              <sformatf loc="d,89,46,89,52" name="%%Error: t/t_enum_type_methods.v:89:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="10">
+                                <arraysel loc="d,89,127,89,131" dtype_id="11">
+                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                                  <and loc="d,89,127,89,131" dtype_id="13">
+                                    <const loc="d,89,127,89,131" name="32&apos;h7" dtype_id="14"/>
+                                    <ccast loc="d,89,125,89,126" dtype_id="13">
+                                      <varref loc="d,89,125,89,126" name="t.e" dtype_id="13"/>
                                     </ccast>
                                   </and>
                                 </arraysel>
@@ -1307,18 +1313,18 @@
                           </begin>
                         </if>
                         <if loc="d,90,13,90,15">
-                          <neq loc="d,90,29,90,32" dtype_id="8">
-                            <const loc="d,90,34,90,37" name="4&apos;h3" dtype_id="10"/>
-                            <arraysel loc="d,90,20,90,24" dtype_id="10">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                              <and loc="d,90,20,90,24" dtype_id="12">
-                                <const loc="d,90,20,90,24" name="32&apos;h7" dtype_id="13"/>
-                                <arraysel loc="d,90,20,90,24" dtype_id="12">
-                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                                  <and loc="d,90,20,90,24" dtype_id="12">
-                                    <const loc="d,90,20,90,24" name="32&apos;h7" dtype_id="13"/>
-                                    <ccast loc="d,90,18,90,19" dtype_id="12">
-                                      <varref loc="d,90,18,90,19" name="t.e" dtype_id="12"/>
+                          <neq loc="d,90,29,90,32" dtype_id="9">
+                            <const loc="d,90,34,90,37" name="4&apos;h3" dtype_id="11"/>
+                            <arraysel loc="d,90,20,90,24" dtype_id="11">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                              <and loc="d,90,20,90,24" dtype_id="13">
+                                <const loc="d,90,20,90,24" name="32&apos;h7" dtype_id="14"/>
+                                <arraysel loc="d,90,20,90,24" dtype_id="13">
+                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                                  <and loc="d,90,20,90,24" dtype_id="13">
+                                    <const loc="d,90,20,90,24" name="32&apos;h7" dtype_id="14"/>
+                                    <ccast loc="d,90,18,90,19" dtype_id="13">
+                                      <varref loc="d,90,18,90,19" name="t.e" dtype_id="13"/>
                                     </ccast>
                                   </and>
                                 </arraysel>
@@ -1327,17 +1333,17 @@
                           </neq>
                           <begin>
                             <display loc="d,90,46,90,52" displaytype="$write">
-                              <sformatf loc="d,90,46,90,52" name="%%Error: t/t_enum_type_methods.v:90:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
-                                <arraysel loc="d,90,127,90,131" dtype_id="10">
-                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                                  <and loc="d,90,127,90,131" dtype_id="12">
-                                    <const loc="d,90,127,90,131" name="32&apos;h7" dtype_id="13"/>
-                                    <arraysel loc="d,90,127,90,131" dtype_id="12">
-                                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
-                                      <and loc="d,90,127,90,131" dtype_id="12">
-                                        <const loc="d,90,127,90,131" name="32&apos;h7" dtype_id="13"/>
-                                        <ccast loc="d,90,125,90,126" dtype_id="12">
-                                          <varref loc="d,90,125,90,126" name="t.e" dtype_id="12"/>
+                              <sformatf loc="d,90,46,90,52" name="%%Error: t/t_enum_type_methods.v:90:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="10">
+                                <arraysel loc="d,90,127,90,131" dtype_id="11">
+                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                                  <and loc="d,90,127,90,131" dtype_id="13">
+                                    <const loc="d,90,127,90,131" name="32&apos;h7" dtype_id="14"/>
+                                    <arraysel loc="d,90,127,90,131" dtype_id="13">
+                                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
+                                      <and loc="d,90,127,90,131" dtype_id="13">
+                                        <const loc="d,90,127,90,131" name="32&apos;h7" dtype_id="14"/>
+                                        <ccast loc="d,90,125,90,126" dtype_id="13">
+                                          <varref loc="d,90,125,90,126" name="t.e" dtype_id="13"/>
                                         </ccast>
                                       </and>
                                     </arraysel>
@@ -1349,27 +1355,27 @@
                           </begin>
                         </if>
                         <if loc="d,91,13,91,15">
-                          <neq loc="d,91,26,91,29" dtype_id="8">
-                            <const loc="d,91,31,91,34" name="4&apos;h3" dtype_id="10"/>
-                            <arraysel loc="d,91,20,91,24" dtype_id="10">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                              <and loc="d,91,20,91,24" dtype_id="12">
-                                <const loc="d,91,20,91,24" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,91,18,91,19" dtype_id="12">
-                                  <varref loc="d,91,18,91,19" name="t.e" dtype_id="12"/>
+                          <neq loc="d,91,26,91,29" dtype_id="9">
+                            <const loc="d,91,31,91,34" name="4&apos;h3" dtype_id="11"/>
+                            <arraysel loc="d,91,20,91,24" dtype_id="11">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                              <and loc="d,91,20,91,24" dtype_id="13">
+                                <const loc="d,91,20,91,24" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,91,18,91,19" dtype_id="13">
+                                  <varref loc="d,91,18,91,19" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
                           </neq>
                           <begin>
                             <display loc="d,91,43,91,49" displaytype="$write">
-                              <sformatf loc="d,91,43,91,49" name="%%Error: t/t_enum_type_methods.v:91:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
-                                <arraysel loc="d,91,124,91,128" dtype_id="10">
-                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                                  <and loc="d,91,124,91,128" dtype_id="12">
-                                    <const loc="d,91,124,91,128" name="32&apos;h7" dtype_id="13"/>
-                                    <ccast loc="d,91,122,91,123" dtype_id="12">
-                                      <varref loc="d,91,122,91,123" name="t.e" dtype_id="12"/>
+                              <sformatf loc="d,91,43,91,49" name="%%Error: t/t_enum_type_methods.v:91:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="10">
+                                <arraysel loc="d,91,124,91,128" dtype_id="11">
+                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                                  <and loc="d,91,124,91,128" dtype_id="13">
+                                    <const loc="d,91,124,91,128" name="32&apos;h7" dtype_id="14"/>
+                                    <ccast loc="d,91,122,91,123" dtype_id="13">
+                                      <varref loc="d,91,122,91,123" name="t.e" dtype_id="13"/>
                                     </ccast>
                                   </and>
                                 </arraysel>
@@ -1379,27 +1385,27 @@
                           </begin>
                         </if>
                         <if loc="d,92,13,92,15">
-                          <neq loc="d,92,29,92,32" dtype_id="8">
-                            <const loc="d,92,34,92,37" name="4&apos;h3" dtype_id="10"/>
-                            <arraysel loc="d,92,20,92,24" dtype_id="10">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                              <and loc="d,92,20,92,24" dtype_id="12">
-                                <const loc="d,92,20,92,24" name="32&apos;h7" dtype_id="13"/>
-                                <ccast loc="d,92,18,92,19" dtype_id="12">
-                                  <varref loc="d,92,18,92,19" name="t.e" dtype_id="12"/>
+                          <neq loc="d,92,29,92,32" dtype_id="9">
+                            <const loc="d,92,34,92,37" name="4&apos;h3" dtype_id="11"/>
+                            <arraysel loc="d,92,20,92,24" dtype_id="11">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                              <and loc="d,92,20,92,24" dtype_id="13">
+                                <const loc="d,92,20,92,24" name="32&apos;h7" dtype_id="14"/>
+                                <ccast loc="d,92,18,92,19" dtype_id="13">
+                                  <varref loc="d,92,18,92,19" name="t.e" dtype_id="13"/>
                                 </ccast>
                               </and>
                             </arraysel>
                           </neq>
                           <begin>
                             <display loc="d,92,46,92,52" displaytype="$write">
-                              <sformatf loc="d,92,46,92,52" name="%%Error: t/t_enum_type_methods.v:92:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="9">
-                                <arraysel loc="d,92,127,92,131" dtype_id="10">
-                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                                  <and loc="d,92,127,92,131" dtype_id="12">
-                                    <const loc="d,92,127,92,131" name="32&apos;h7" dtype_id="13"/>
-                                    <ccast loc="d,92,125,92,126" dtype_id="12">
-                                      <varref loc="d,92,125,92,126" name="t.e" dtype_id="12"/>
+                              <sformatf loc="d,92,46,92,52" name="%%Error: t/t_enum_type_methods.v:92:  got=&apos;h%x exp=&apos;h3&#10;" dtype_id="10">
+                                <arraysel loc="d,92,127,92,131" dtype_id="11">
+                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                                  <and loc="d,92,127,92,131" dtype_id="13">
+                                    <const loc="d,92,127,92,131" name="32&apos;h7" dtype_id="14"/>
+                                    <ccast loc="d,92,125,92,126" dtype_id="13">
+                                      <varref loc="d,92,125,92,126" name="t.e" dtype_id="13"/>
                                     </ccast>
                                   </and>
                                 </arraysel>
@@ -1409,18 +1415,18 @@
                           </begin>
                         </if>
                         <if loc="d,93,13,93,15">
-                          <neq loc="d,93,29,93,32" dtype_id="8">
-                            <const loc="d,93,34,93,37" name="4&apos;h1" dtype_id="10"/>
-                            <arraysel loc="d,93,20,93,24" dtype_id="10">
-                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                              <and loc="d,93,20,93,24" dtype_id="12">
-                                <const loc="d,93,20,93,24" name="32&apos;h7" dtype_id="13"/>
-                                <arraysel loc="d,93,20,93,24" dtype_id="12">
-                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                                  <and loc="d,93,20,93,24" dtype_id="12">
-                                    <const loc="d,93,20,93,24" name="32&apos;h7" dtype_id="13"/>
-                                    <ccast loc="d,93,18,93,19" dtype_id="12">
-                                      <varref loc="d,93,18,93,19" name="t.e" dtype_id="12"/>
+                          <neq loc="d,93,29,93,32" dtype_id="9">
+                            <const loc="d,93,34,93,37" name="4&apos;h1" dtype_id="11"/>
+                            <arraysel loc="d,93,20,93,24" dtype_id="11">
+                              <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                              <and loc="d,93,20,93,24" dtype_id="13">
+                                <const loc="d,93,20,93,24" name="32&apos;h7" dtype_id="14"/>
+                                <arraysel loc="d,93,20,93,24" dtype_id="13">
+                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                                  <and loc="d,93,20,93,24" dtype_id="13">
+                                    <const loc="d,93,20,93,24" name="32&apos;h7" dtype_id="14"/>
+                                    <ccast loc="d,93,18,93,19" dtype_id="13">
+                                      <varref loc="d,93,18,93,19" name="t.e" dtype_id="13"/>
                                     </ccast>
                                   </and>
                                 </arraysel>
@@ -1429,17 +1435,17 @@
                           </neq>
                           <begin>
                             <display loc="d,93,46,93,52" displaytype="$write">
-                              <sformatf loc="d,93,46,93,52" name="%%Error: t/t_enum_type_methods.v:93:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="9">
-                                <arraysel loc="d,93,127,93,131" dtype_id="10">
-                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                                  <and loc="d,93,127,93,131" dtype_id="12">
-                                    <const loc="d,93,127,93,131" name="32&apos;h7" dtype_id="13"/>
-                                    <arraysel loc="d,93,127,93,131" dtype_id="12">
-                                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
-                                      <and loc="d,93,127,93,131" dtype_id="12">
-                                        <const loc="d,93,127,93,131" name="32&apos;h7" dtype_id="13"/>
-                                        <ccast loc="d,93,125,93,126" dtype_id="12">
-                                          <varref loc="d,93,125,93,126" name="t.e" dtype_id="12"/>
+                              <sformatf loc="d,93,46,93,52" name="%%Error: t/t_enum_type_methods.v:93:  got=&apos;h%x exp=&apos;h1&#10;" dtype_id="10">
+                                <arraysel loc="d,93,127,93,131" dtype_id="11">
+                                  <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                                  <and loc="d,93,127,93,131" dtype_id="13">
+                                    <const loc="d,93,127,93,131" name="32&apos;h7" dtype_id="14"/>
+                                    <arraysel loc="d,93,127,93,131" dtype_id="13">
+                                      <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
+                                      <and loc="d,93,127,93,131" dtype_id="13">
+                                        <const loc="d,93,127,93,131" name="32&apos;h7" dtype_id="14"/>
+                                        <ccast loc="d,93,125,93,126" dtype_id="13">
+                                          <varref loc="d,93,125,93,126" name="t.e" dtype_id="13"/>
                                         </ccast>
                                       </and>
                                     </arraysel>
@@ -1450,20 +1456,20 @@
                             <stop loc="d,93,145,93,150"/>
                           </begin>
                         </if>
-                        <assigndly loc="d,94,12,94,14" dtype_id="10">
-                          <const loc="d,94,15,94,18" name="4&apos;h1" dtype_id="10"/>
-                          <varref loc="d,94,10,94,11" name="__Vdly__t.e" dtype_id="10"/>
+                        <assigndly loc="d,94,12,94,14" dtype_id="11">
+                          <const loc="d,94,15,94,18" name="4&apos;h1" dtype_id="11"/>
+                          <varref loc="d,94,10,94,11" name="__Vdly__t.e" dtype_id="11"/>
                         </assigndly>
                       </begin>
                       <begin>
                         <if loc="d,96,12,96,14">
-                          <eq loc="d,96,19,96,21" dtype_id="8">
-                            <const loc="d,96,21,96,23" name="32&apos;sh63" dtype_id="7"/>
+                          <eq loc="d,96,19,96,21" dtype_id="9">
+                            <const loc="d,96,21,96,23" name="32&apos;sh63" dtype_id="8"/>
                             <varref loc="d,96,16,96,19" name="t.cyc" dtype_id="4"/>
                           </eq>
                           <begin>
                             <display loc="d,97,10,97,16" displaytype="$write">
-                              <sformatf loc="d,97,10,97,16" name="*-* All Finished *-*&#10;" dtype_id="9"/>
+                              <sformatf loc="d,97,10,97,16" name="*-* All Finished *-*&#10;" dtype_id="10"/>
                             </display>
                             <finish loc="d,98,10,98,17"/>
                           </begin>
@@ -1480,19 +1486,21 @@
           <varref loc="d,61,7,61,10" name="__Vdly__t.cyc" dtype_id="4"/>
           <varref loc="d,61,7,61,10" name="t.cyc" dtype_id="4"/>
         </assignpost>
-        <assignpost loc="d,64,10,64,11" dtype_id="10">
-          <varref loc="d,64,10,64,11" name="__Vdly__t.e" dtype_id="10"/>
-          <varref loc="d,64,10,64,11" name="t.e" dtype_id="10"/>
+        <assignpost loc="d,64,10,64,11" dtype_id="11">
+          <varref loc="d,64,10,64,11" name="__Vdly__t.e" dtype_id="11"/>
+          <varref loc="d,64,10,64,11" name="t.e" dtype_id="11"/>
         </assignpost>
       </cfunc>
       <cfunc loc="a,0,0,0,0" name="_eval_nba">
         <if loc="d,10,8,10,9">
-          <cmethodhard loc="d,10,8,10,9" name="at" dtype_id="8">
-            <varref loc="d,10,8,10,9" name="__VnbaTriggered" dtype_id="8"/>
-            <const loc="d,10,8,10,9" name="32&apos;h0" dtype_id="13"/>
+          <cmethodhard loc="d,10,8,10,9" name="at" dtype_id="9">
+            <varref loc="d,10,8,10,9" name="__VnbaTriggered" dtype_id="9"/>
+            <const loc="d,10,8,10,9" name="32&apos;h0" dtype_id="14"/>
           </cmethodhard>
           <begin>
-            <ccall loc="d,64,10,64,11" func="_nba_sequent__TOP__0"/>
+            <stmtexpr loc="d,64,10,64,11">
+              <ccall loc="d,64,10,64,11" dtype_id="7" func="_nba_sequent__TOP__0"/>
+            </stmtexpr>
           </begin>
         </if>
       </cfunc>
@@ -1501,65 +1509,71 @@
         <var loc="d,10,8,10,9" name="__VnbaIterCount" dtype_id="5" vartype="bit" origName="__VnbaIterCount"/>
         <var loc="d,10,8,10,9" name="__VnbaContinue" dtype_id="3" vartype="bit" origName="__VnbaContinue"/>
         <assign loc="d,10,8,10,9" dtype_id="5">
-          <const loc="d,10,8,10,9" name="32&apos;h0" dtype_id="13"/>
+          <const loc="d,10,8,10,9" name="32&apos;h0" dtype_id="14"/>
           <varref loc="d,10,8,10,9" name="__VnbaIterCount" dtype_id="5"/>
         </assign>
-        <assign loc="d,10,8,10,9" dtype_id="8">
-          <const loc="d,10,8,10,9" name="1&apos;h1" dtype_id="8"/>
-          <varref loc="d,10,8,10,9" name="__VnbaContinue" dtype_id="8"/>
+        <assign loc="d,10,8,10,9" dtype_id="9">
+          <const loc="d,10,8,10,9" name="1&apos;h1" dtype_id="9"/>
+          <varref loc="d,10,8,10,9" name="__VnbaContinue" dtype_id="9"/>
         </assign>
         <while loc="d,10,8,10,9">
           <begin>
           </begin>
           <begin>
-            <varref loc="d,10,8,10,9" name="__VnbaContinue" dtype_id="8"/>
+            <varref loc="d,10,8,10,9" name="__VnbaContinue" dtype_id="9"/>
           </begin>
           <begin>
-            <assign loc="d,10,8,10,9" dtype_id="8">
-              <const loc="d,10,8,10,9" name="1&apos;h0" dtype_id="8"/>
-              <varref loc="d,10,8,10,9" name="__VnbaContinue" dtype_id="8"/>
+            <assign loc="d,10,8,10,9" dtype_id="9">
+              <const loc="d,10,8,10,9" name="1&apos;h0" dtype_id="9"/>
+              <varref loc="d,10,8,10,9" name="__VnbaContinue" dtype_id="9"/>
             </assign>
-            <cmethodhard loc="a,0,0,0,0" name="clear" dtype_id="16">
-              <varref loc="a,0,0,0,0" name="__VnbaTriggered" dtype_id="8"/>
-            </cmethodhard>
+            <stmtexpr loc="a,0,0,0,0">
+              <cmethodhard loc="a,0,0,0,0" name="clear" dtype_id="7">
+                <varref loc="a,0,0,0,0" name="__VnbaTriggered" dtype_id="9"/>
+              </cmethodhard>
+            </stmtexpr>
             <assign loc="d,10,8,10,9" dtype_id="5">
-              <const loc="d,10,8,10,9" name="32&apos;h0" dtype_id="13"/>
+              <const loc="d,10,8,10,9" name="32&apos;h0" dtype_id="14"/>
               <varref loc="d,10,8,10,9" name="__VactIterCount" dtype_id="5"/>
             </assign>
-            <assign loc="d,10,8,10,9" dtype_id="8">
-              <const loc="d,10,8,10,9" name="1&apos;h1" dtype_id="8"/>
-              <varref loc="d,10,8,10,9" name="__VactContinue" dtype_id="8"/>
+            <assign loc="d,10,8,10,9" dtype_id="9">
+              <const loc="d,10,8,10,9" name="1&apos;h1" dtype_id="9"/>
+              <varref loc="d,10,8,10,9" name="__VactContinue" dtype_id="9"/>
             </assign>
             <while loc="d,10,8,10,9">
               <begin>
               </begin>
               <begin>
-                <varref loc="d,10,8,10,9" name="__VactContinue" dtype_id="8"/>
+                <varref loc="d,10,8,10,9" name="__VactContinue" dtype_id="9"/>
               </begin>
               <begin>
-                <assign loc="d,10,8,10,9" dtype_id="8">
-                  <const loc="d,10,8,10,9" name="1&apos;h0" dtype_id="8"/>
-                  <varref loc="d,10,8,10,9" name="__VactContinue" dtype_id="8"/>
+                <assign loc="d,10,8,10,9" dtype_id="9">
+                  <const loc="d,10,8,10,9" name="1&apos;h0" dtype_id="9"/>
+                  <varref loc="d,10,8,10,9" name="__VactContinue" dtype_id="9"/>
                 </assign>
-                <ccall loc="a,0,0,0,0" func="_eval_triggers__act"/>
+                <stmtexpr loc="a,0,0,0,0">
+                  <ccall loc="a,0,0,0,0" dtype_id="7" func="_eval_triggers__act"/>
+                </stmtexpr>
                 <if loc="d,10,8,10,9">
-                  <cmethodhard loc="d,10,8,10,9" name="any" dtype_id="8">
-                    <varref loc="d,10,8,10,9" name="__VactTriggered" dtype_id="8"/>
+                  <cmethodhard loc="d,10,8,10,9" name="any" dtype_id="9">
+                    <varref loc="d,10,8,10,9" name="__VactTriggered" dtype_id="9"/>
                   </cmethodhard>
                   <begin>
-                    <assign loc="d,10,8,10,9" dtype_id="8">
-                      <const loc="d,10,8,10,9" name="1&apos;h1" dtype_id="8"/>
-                      <varref loc="d,10,8,10,9" name="__VactContinue" dtype_id="8"/>
+                    <assign loc="d,10,8,10,9" dtype_id="9">
+                      <const loc="d,10,8,10,9" name="1&apos;h1" dtype_id="9"/>
+                      <varref loc="d,10,8,10,9" name="__VactContinue" dtype_id="9"/>
                     </assign>
                     <if loc="d,10,8,10,9">
-                      <lt loc="d,10,8,10,9" dtype_id="8">
-                        <const loc="d,10,8,10,9" name="32&apos;h64" dtype_id="13"/>
+                      <lt loc="d,10,8,10,9" dtype_id="9">
+                        <const loc="d,10,8,10,9" name="32&apos;h64" dtype_id="14"/>
                         <varref loc="d,10,8,10,9" name="__VactIterCount" dtype_id="5"/>
                       </lt>
                       <begin>
                         <textblock loc="d,10,8,10,9">
                           <text loc="d,10,8,10,9"/>
-                          <ccall loc="d,10,8,10,9" func="_dump_triggers__act"/>
+                          <stmtexpr loc="d,10,8,10,9">
+                            <ccall loc="d,10,8,10,9" dtype_id="7" func="_dump_triggers__act"/>
+                          </stmtexpr>
                           <text loc="d,10,8,10,9"/>
                           <text loc="d,10,8,10,9"/>
                           <text loc="d,10,8,10,9"/>
@@ -1568,45 +1582,53 @@
                     </if>
                     <assign loc="d,10,8,10,9" dtype_id="5">
                       <add loc="d,10,8,10,9" dtype_id="5">
-                        <ccast loc="d,10,8,10,9" dtype_id="13">
-                          <const loc="d,10,8,10,9" name="32&apos;h1" dtype_id="13"/>
+                        <ccast loc="d,10,8,10,9" dtype_id="14">
+                          <const loc="d,10,8,10,9" name="32&apos;h1" dtype_id="14"/>
                         </ccast>
                         <varref loc="d,10,8,10,9" name="__VactIterCount" dtype_id="5"/>
                       </add>
                       <varref loc="d,10,8,10,9" name="__VactIterCount" dtype_id="5"/>
                     </assign>
-                    <cmethodhard loc="a,0,0,0,0" name="andNot" dtype_id="16">
-                      <varref loc="a,0,0,0,0" name="__VpreTriggered" dtype_id="8"/>
-                      <varref loc="a,0,0,0,0" name="__VactTriggered" dtype_id="8"/>
-                      <varref loc="a,0,0,0,0" name="__VnbaTriggered" dtype_id="8"/>
-                    </cmethodhard>
-                    <cmethodhard loc="a,0,0,0,0" name="set" dtype_id="16">
-                      <varref loc="a,0,0,0,0" name="__VnbaTriggered" dtype_id="8"/>
-                      <varref loc="a,0,0,0,0" name="__VactTriggered" dtype_id="8"/>
-                    </cmethodhard>
-                    <ccall loc="a,0,0,0,0" func="_eval_act"/>
+                    <stmtexpr loc="a,0,0,0,0">
+                      <cmethodhard loc="a,0,0,0,0" name="andNot" dtype_id="7">
+                        <varref loc="a,0,0,0,0" name="__VpreTriggered" dtype_id="9"/>
+                        <varref loc="a,0,0,0,0" name="__VactTriggered" dtype_id="9"/>
+                        <varref loc="a,0,0,0,0" name="__VnbaTriggered" dtype_id="9"/>
+                      </cmethodhard>
+                    </stmtexpr>
+                    <stmtexpr loc="a,0,0,0,0">
+                      <cmethodhard loc="a,0,0,0,0" name="set" dtype_id="7">
+                        <varref loc="a,0,0,0,0" name="__VnbaTriggered" dtype_id="9"/>
+                        <varref loc="a,0,0,0,0" name="__VactTriggered" dtype_id="9"/>
+                      </cmethodhard>
+                    </stmtexpr>
+                    <stmtexpr loc="a,0,0,0,0">
+                      <ccall loc="a,0,0,0,0" dtype_id="7" func="_eval_act"/>
+                    </stmtexpr>
                   </begin>
                 </if>
               </begin>
             </while>
             <if loc="d,10,8,10,9">
-              <cmethodhard loc="d,10,8,10,9" name="any" dtype_id="8">
-                <varref loc="d,10,8,10,9" name="__VnbaTriggered" dtype_id="8"/>
+              <cmethodhard loc="d,10,8,10,9" name="any" dtype_id="9">
+                <varref loc="d,10,8,10,9" name="__VnbaTriggered" dtype_id="9"/>
               </cmethodhard>
               <begin>
-                <assign loc="d,10,8,10,9" dtype_id="8">
-                  <const loc="d,10,8,10,9" name="1&apos;h1" dtype_id="8"/>
-                  <varref loc="d,10,8,10,9" name="__VnbaContinue" dtype_id="8"/>
+                <assign loc="d,10,8,10,9" dtype_id="9">
+                  <const loc="d,10,8,10,9" name="1&apos;h1" dtype_id="9"/>
+                  <varref loc="d,10,8,10,9" name="__VnbaContinue" dtype_id="9"/>
                 </assign>
                 <if loc="d,10,8,10,9">
-                  <lt loc="d,10,8,10,9" dtype_id="8">
-                    <const loc="d,10,8,10,9" name="32&apos;h64" dtype_id="13"/>
+                  <lt loc="d,10,8,10,9" dtype_id="9">
+                    <const loc="d,10,8,10,9" name="32&apos;h64" dtype_id="14"/>
                     <varref loc="d,10,8,10,9" name="__VnbaIterCount" dtype_id="5"/>
                   </lt>
                   <begin>
                     <textblock loc="d,10,8,10,9">
                       <text loc="d,10,8,10,9"/>
-                      <ccall loc="d,10,8,10,9" func="_dump_triggers__nba"/>
+                      <stmtexpr loc="d,10,8,10,9">
+                        <ccall loc="d,10,8,10,9" dtype_id="7" func="_dump_triggers__nba"/>
+                      </stmtexpr>
                       <text loc="d,10,8,10,9"/>
                       <text loc="d,10,8,10,9"/>
                       <text loc="d,10,8,10,9"/>
@@ -1615,14 +1637,16 @@
                 </if>
                 <assign loc="d,10,8,10,9" dtype_id="5">
                   <add loc="d,10,8,10,9" dtype_id="5">
-                    <ccast loc="d,10,8,10,9" dtype_id="13">
-                      <const loc="d,10,8,10,9" name="32&apos;h1" dtype_id="13"/>
+                    <ccast loc="d,10,8,10,9" dtype_id="14">
+                      <const loc="d,10,8,10,9" name="32&apos;h1" dtype_id="14"/>
                     </ccast>
                     <varref loc="d,10,8,10,9" name="__VnbaIterCount" dtype_id="5"/>
                   </add>
                   <varref loc="d,10,8,10,9" name="__VnbaIterCount" dtype_id="5"/>
                 </assign>
-                <ccall loc="a,0,0,0,0" func="_eval_nba"/>
+                <stmtexpr loc="a,0,0,0,0">
+                  <ccall loc="a,0,0,0,0" dtype_id="7" func="_eval_nba"/>
+                </stmtexpr>
               </begin>
             </if>
           </begin>
@@ -1664,55 +1688,55 @@
       <cuse loc="a,0,0,0,0" name="$unit"/>
     </module>
     <package loc="a,0,0,0,0" name="$unit" origName="__024unit">
-      <var loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11" vartype="" origName="__Venumtab_enum_next0">
+      <var loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12" vartype="" origName="__Venumtab_enum_next0">
         <initarray>
           <inititem index="1">
-            <const loc="d,18,30,18,31" name="4&apos;h3" dtype_id="10"/>
+            <const loc="d,18,30,18,31" name="4&apos;h3" dtype_id="11"/>
           </inititem>
           <inititem index="3">
-            <const loc="d,19,30,19,31" name="4&apos;h4" dtype_id="10"/>
+            <const loc="d,19,30,19,31" name="4&apos;h4" dtype_id="11"/>
           </inititem>
           <inititem index="4">
-            <const loc="d,17,30,17,31" name="4&apos;h1" dtype_id="10"/>
+            <const loc="d,17,30,17,31" name="4&apos;h1" dtype_id="11"/>
           </inititem>
         </initarray>
       </var>
-      <var loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14" vartype="" origName="__Venumtab_enum_prev1">
+      <var loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15" vartype="" origName="__Venumtab_enum_prev1">
         <initarray>
           <inititem index="1">
-            <const loc="d,19,30,19,31" name="4&apos;h4" dtype_id="10"/>
+            <const loc="d,19,30,19,31" name="4&apos;h4" dtype_id="11"/>
           </inititem>
           <inititem index="3">
-            <const loc="d,17,30,17,31" name="4&apos;h1" dtype_id="10"/>
+            <const loc="d,17,30,17,31" name="4&apos;h1" dtype_id="11"/>
           </inititem>
           <inititem index="4">
-            <const loc="d,18,30,18,31" name="4&apos;h3" dtype_id="10"/>
+            <const loc="d,18,30,18,31" name="4&apos;h3" dtype_id="11"/>
           </inititem>
         </initarray>
       </var>
-      <var loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="15" vartype="" origName="__Venumtab_enum_name2">
+      <var loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16" vartype="" origName="__Venumtab_enum_name2">
         <initarray>
           <inititem index="1">
-            <const loc="d,16,12,16,16" name="&quot;E01&quot;" dtype_id="9"/>
+            <const loc="d,16,12,16,16" name="&quot;E01&quot;" dtype_id="10"/>
           </inititem>
           <inititem index="3">
-            <const loc="d,16,12,16,16" name="&quot;E03&quot;" dtype_id="9"/>
+            <const loc="d,16,12,16,16" name="&quot;E03&quot;" dtype_id="10"/>
           </inititem>
           <inititem index="4">
-            <const loc="d,16,12,16,16" name="&quot;E04&quot;" dtype_id="9"/>
+            <const loc="d,16,12,16,16" name="&quot;E04&quot;" dtype_id="10"/>
           </inititem>
         </initarray>
       </var>
       <scope loc="a,0,0,0,0" name="$unit"/>
       <cfunc loc="a,0,0,0,0" name="_ctor_var_reset">
         <creset loc="d,16,12,16,16">
-          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="11"/>
+          <varref loc="d,16,12,16,16" name="__Venumtab_enum_next0" dtype_id="12"/>
         </creset>
         <creset loc="d,16,12,16,16">
-          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="14"/>
+          <varref loc="d,16,12,16,16" name="__Venumtab_enum_prev1" dtype_id="15"/>
         </creset>
         <creset loc="d,16,12,16,16">
-          <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="15"/>
+          <varref loc="d,16,12,16,16" name="__Venumtab_enum_name2" dtype_id="16"/>
         </creset>
       </cfunc>
     </package>
@@ -1731,49 +1755,49 @@
     <cfile loc="a,0,0,0,0" name="obj_vlt/t_xml_debugcheck/Vt_xml_debugcheck_$unit__DepSet_h########__0__Slow.cpp"/>
     <typetable loc="a,0,0,0,0">
       <basicdtype loc="d,32,24,32,27" id="1" name="logic"/>
-      <basicdtype loc="d,52,16,52,17" id="13" name="logic" left="31" right="0"/>
+      <basicdtype loc="d,52,16,52,17" id="14" name="logic" left="31" right="0"/>
       <basicdtype loc="d,16,17,16,18" id="2" name="logic" left="3" right="0"/>
       <enumdtype loc="d,16,12,16,16" id="18" name="t.my_t" sub_dtype_id="2">
-        <enumitem loc="d,17,24,17,27" name="E01" dtype_id="10">
-          <const loc="d,17,30,17,31" name="4&apos;h1" dtype_id="10"/>
+        <enumitem loc="d,17,24,17,27" name="E01" dtype_id="11">
+          <const loc="d,17,30,17,31" name="4&apos;h1" dtype_id="11"/>
         </enumitem>
-        <enumitem loc="d,18,24,18,27" name="E03" dtype_id="10">
-          <const loc="d,18,30,18,31" name="4&apos;h3" dtype_id="10"/>
+        <enumitem loc="d,18,24,18,27" name="E03" dtype_id="11">
+          <const loc="d,18,30,18,31" name="4&apos;h3" dtype_id="11"/>
         </enumitem>
-        <enumitem loc="d,19,24,19,27" name="E04" dtype_id="10">
-          <const loc="d,19,30,19,31" name="4&apos;h4" dtype_id="10"/>
+        <enumitem loc="d,19,24,19,27" name="E04" dtype_id="11">
+          <const loc="d,19,30,19,31" name="4&apos;h4" dtype_id="11"/>
         </enumitem>
       </enumdtype>
       <basicdtype loc="d,22,4,22,11" id="4" name="integer" left="31" right="0" signed="true"/>
       <refdtype loc="d,23,4,23,8" id="19" name="my_t" sub_dtype_id="2"/>
-      <basicdtype loc="d,27,4,27,10" id="9" name="string"/>
-      <unpackarraydtype loc="d,16,12,16,16" id="11" sub_dtype_id="2">
+      <basicdtype loc="d,27,4,27,10" id="10" name="string"/>
+      <unpackarraydtype loc="d,16,12,16,16" id="12" sub_dtype_id="2">
         <range loc="d,16,12,16,16">
-          <const loc="d,16,12,16,16" name="32&apos;h7" dtype_id="13"/>
-          <const loc="d,16,12,16,16" name="32&apos;h0" dtype_id="13"/>
+          <const loc="d,16,12,16,16" name="32&apos;h7" dtype_id="14"/>
+          <const loc="d,16,12,16,16" name="32&apos;h0" dtype_id="14"/>
         </range>
       </unpackarraydtype>
-      <unpackarraydtype loc="d,16,12,16,16" id="14" sub_dtype_id="2">
+      <unpackarraydtype loc="d,16,12,16,16" id="15" sub_dtype_id="2">
         <range loc="d,16,12,16,16">
-          <const loc="d,16,12,16,16" name="32&apos;h7" dtype_id="13"/>
-          <const loc="d,16,12,16,16" name="32&apos;h0" dtype_id="13"/>
+          <const loc="d,16,12,16,16" name="32&apos;h7" dtype_id="14"/>
+          <const loc="d,16,12,16,16" name="32&apos;h0" dtype_id="14"/>
         </range>
       </unpackarraydtype>
-      <unpackarraydtype loc="d,16,12,16,16" id="15" sub_dtype_id="9">
+      <unpackarraydtype loc="d,16,12,16,16" id="16" sub_dtype_id="10">
         <range loc="d,16,12,16,16">
-          <const loc="d,16,12,16,16" name="32&apos;h7" dtype_id="13"/>
-          <const loc="d,16,12,16,16" name="32&apos;h0" dtype_id="13"/>
+          <const loc="d,16,12,16,16" name="32&apos;h7" dtype_id="14"/>
+          <const loc="d,16,12,16,16" name="32&apos;h0" dtype_id="14"/>
         </range>
       </unpackarraydtype>
       <refdtype loc="d,51,12,51,16" id="20" name="my_t" sub_dtype_id="2"/>
-      <basicdtype loc="d,22,23,22,24" id="7" name="logic" left="31" right="0" signed="true"/>
+      <basicdtype loc="d,22,23,22,24" id="8" name="logic" left="31" right="0" signed="true"/>
+      <voiddtype loc="d,10,8,10,9" id="7"/>
       <basicdtype loc="d,10,8,10,9" id="6" name="VlTriggerVec"/>
       <basicdtype loc="d,10,8,10,9" id="5" name="bit" left="31" right="0"/>
       <basicdtype loc="d,10,8,10,9" id="3" name="bit"/>
-      <voiddtype loc="a,0,0,0,0" id="16"/>
-      <basicdtype loc="d,60,22,60,25" id="8" name="logic" left="31" right="0"/>
-      <basicdtype loc="d,31,11,31,14" id="10" name="logic" left="31" right="0"/>
-      <basicdtype loc="d,37,17,37,21" id="12" name="logic" left="31" right="0"/>
+      <basicdtype loc="d,60,22,60,25" id="9" name="logic" left="31" right="0"/>
+      <basicdtype loc="d,31,11,31,14" id="11" name="logic" left="31" right="0"/>
+      <basicdtype loc="d,37,17,37,21" id="13" name="logic" left="31" right="0"/>
       <basicdtype loc="d,14,10,14,13" id="17" name="logic" left="7" right="0"/>
     </typetable>
     <constpool>
diff --git a/test_regress/t/t_xml_tag.out b/test_regress/t/t_xml_tag.out
index e2d426fd9..fecebf1ba 100644
--- a/test_regress/t/t_xml_tag.out
+++ b/test_regress/t/t_xml_tag.out
@@ -40,11 +40,13 @@
       </func>
       <initial loc="d,39,4,39,11">
         <begin loc="d,39,12,39,17">
-          <taskref loc="d,41,7,41,8" name="f">
-            <arg loc="d,41,9,41,736">
-              <const loc="d,41,9,41,736" name="&quot;&#1;&#2;&#3;&#4;&#5;&#6;&#7;&#8;&#9;&#10;&#11;&#12;&#13;&#14;&#15;&#16;&#17;&#18;&#19;&#20;&#21;&#22;&#23;&#24;&#25;&#26;&#27;&#28;&#29;&#30;&#31; !&quot;#$%&amp;&apos;()*+,-./0123456789:;&lt;=&gt;?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~&#127;&#128;&#129;&#130;&#131;&#132;&#133;&#134;&#135;&#136;&#137;&#138;&#139;&#140;&#141;&#142;&#143;&#144;&#145;&#146;&#147;&#148;&#149;&#150;&#151;&#152;&#153;&#154;&#155;&#156;&#157;&#158;&#159;&#160;&#161;&#162;&#163;&#164;&#165;&#166;&#167;&#168;&#169;&#170;&#171;&#172;&#173;&#174;&#175;&#176;&#177;&#178;&#179;&#180;&#181;&#182;&#183;&#184;&#185;&#186;&#187;&#188;&#189;&#190;&#191;&#192;&#193;&#194;&#195;&#196;&#197;&#198;&#199;&#200;&#201;&#202;&#203;&#204;&#205;&#206;&#207;&#208;&#209;&#210;&#211;&#212;&#213;&#214;&#215;&#216;&#217;&#218;&#219;&#220;&#221;&#222;&#223;&#224;&#225;&#226;&#227;&#228;&#229;&#230;&#231;&#232;&#233;&#234;&#235;&#236;&#237;&#238;&#239;&#240;&#241;&#242;&#243;&#244;&#245;&#246;&#247;&#248;&#249;&#250;&#251;&#252;&#253;&#254;&#255;&quot;" dtype_id="7"/>
-            </arg>
-          </taskref>
+          <stmtexpr loc="d,41,7,41,8">
+            <taskref loc="d,41,7,41,8" name="f" dtype_id="8">
+              <arg loc="d,41,9,41,736">
+                <const loc="d,41,9,41,736" name="&quot;&#1;&#2;&#3;&#4;&#5;&#6;&#7;&#8;&#9;&#10;&#11;&#12;&#13;&#14;&#15;&#16;&#17;&#18;&#19;&#20;&#21;&#22;&#23;&#24;&#25;&#26;&#27;&#28;&#29;&#30;&#31; !&quot;#$%&amp;&apos;()*+,-./0123456789:;&lt;=&gt;?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~&#127;&#128;&#129;&#130;&#131;&#132;&#133;&#134;&#135;&#136;&#137;&#138;&#139;&#140;&#141;&#142;&#143;&#144;&#145;&#146;&#147;&#148;&#149;&#150;&#151;&#152;&#153;&#154;&#155;&#156;&#157;&#158;&#159;&#160;&#161;&#162;&#163;&#164;&#165;&#166;&#167;&#168;&#169;&#170;&#171;&#172;&#173;&#174;&#175;&#176;&#177;&#178;&#179;&#180;&#181;&#182;&#183;&#184;&#185;&#186;&#187;&#188;&#189;&#190;&#191;&#192;&#193;&#194;&#195;&#196;&#197;&#198;&#199;&#200;&#201;&#202;&#203;&#204;&#205;&#206;&#207;&#208;&#209;&#210;&#211;&#212;&#213;&#214;&#215;&#216;&#217;&#218;&#219;&#220;&#221;&#222;&#223;&#224;&#225;&#226;&#227;&#228;&#229;&#230;&#231;&#232;&#233;&#234;&#235;&#236;&#237;&#238;&#239;&#240;&#241;&#242;&#243;&#244;&#245;&#246;&#247;&#248;&#249;&#250;&#251;&#252;&#253;&#254;&#255;&quot;" dtype_id="7"/>
+              </arg>
+            </taskref>
+          </stmtexpr>
         </begin>
       </initial>
     </module>
@@ -55,21 +57,22 @@
       </modport>
     </iface>
     <typetable loc="a,0,0,0,0">
+      <voiddtype loc="d,41,7,41,8" id="8"/>
       <basicdtype loc="d,8,4,8,11" id="6" name="integer" left="31" right="0" signed="true"/>
       <basicdtype loc="d,14,11,14,17" id="1" name="logic"/>
-      <basicdtype loc="d,21,7,21,12" id="8" name="logic"/>
-      <basicdtype loc="d,22,7,22,12" id="9" name="logic"/>
-      <basicdtype loc="d,23,7,23,12" id="10" name="logic"/>
-      <basicdtype loc="d,24,7,24,12" id="11" name="logic"/>
+      <basicdtype loc="d,21,7,21,12" id="9" name="logic"/>
+      <basicdtype loc="d,22,7,22,12" id="10" name="logic"/>
+      <basicdtype loc="d,23,7,23,12" id="11" name="logic"/>
+      <basicdtype loc="d,24,7,24,12" id="12" name="logic"/>
       <structdtype loc="d,20,12,20,18" id="2" name="m.my_struct">
-        <memberdtype loc="d,21,19,21,22" id="12" name="clk" tag="this is clk" sub_dtype_id="8"/>
-        <memberdtype loc="d,22,19,22,20" id="13" name="k" sub_dtype_id="9"/>
-        <memberdtype loc="d,23,19,23,25" id="14" name="enable" tag="enable" sub_dtype_id="10"/>
-        <memberdtype loc="d,24,19,24,23" id="15" name="data" tag="data" sub_dtype_id="11"/>
+        <memberdtype loc="d,21,19,21,22" id="13" name="clk" tag="this is clk" sub_dtype_id="9"/>
+        <memberdtype loc="d,22,19,22,20" id="14" name="k" sub_dtype_id="10"/>
+        <memberdtype loc="d,23,19,23,25" id="15" name="enable" tag="enable" sub_dtype_id="11"/>
+        <memberdtype loc="d,24,19,24,23" id="16" name="data" tag="data" sub_dtype_id="12"/>
       </structdtype>
       <ifacerefdtype loc="d,29,8,29,12" id="3" modportname=""/>
       <basicdtype loc="d,31,27,31,28" id="5" name="logic" left="31" right="0"/>
-      <refdtype loc="d,31,4,31,13" id="16" name="my_struct" sub_dtype_id="2"/>
+      <refdtype loc="d,31,4,31,13" id="17" name="my_struct" sub_dtype_id="2"/>
       <unpackarraydtype loc="d,31,26,31,27" id="4" sub_dtype_id="2">
         <range loc="d,31,26,31,27">
           <const loc="d,31,27,31,28" name="32&apos;h0" dtype_id="5"/>

From 8d61cea366057f0a8537d09168a3377f095784ab Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Fri, 4 Nov 2022 13:58:17 +0100
Subject: [PATCH 005/156] Fix return type of $countbits functions to int
 (#3725)

---
 src/V3Width.cpp                   | 14 +++++-----
 test_regress/t/t_math_countbits.v | 26 +++++++++---------
 test_regress/t/t_math_svl.v       | 44 +++++++++++++++----------------
 3 files changed, 41 insertions(+), 43 deletions(-)

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index a2a966a90..8136142e2 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1337,19 +1337,17 @@ private:
             iterateCheckSizedSelf(nodep, "RHS", nodep->rhsp(), SELF, BOTH);
             iterateCheckSizedSelf(nodep, "THS", nodep->thsp(), SELF, BOTH);
             iterateCheckSizedSelf(nodep, "FHS", nodep->fhsp(), SELF, BOTH);
-            // If it's a 32 bit number, we need a 6 bit number as we need to return '32'.
-            const int selwidth = V3Number::log2b(nodep->lhsp()->width()) + 1;
-            nodep->dtypeSetLogicSized(selwidth,
-                                      VSigning::UNSIGNED);  // Spec doesn't indicate if an integer
+            // For widthMin, if a 32 bit number, we need a 6 bit number as we need to return '32'.
+            const int widthMin = V3Number::log2b(nodep->lhsp()->width()) + 1;
+            nodep->dtypeSetLogicUnsized(32, widthMin, VSigning::SIGNED);
         }
     }
     void visit(AstCountOnes* nodep) override {
         if (m_vup->prelim()) {
             iterateCheckSizedSelf(nodep, "LHS", nodep->lhsp(), SELF, BOTH);
-            // If it's a 32 bit number, we need a 6 bit number as we need to return '32'.
-            const int selwidth = V3Number::log2b(nodep->lhsp()->width()) + 1;
-            nodep->dtypeSetLogicSized(selwidth,
-                                      VSigning::UNSIGNED);  // Spec doesn't indicate if an integer
+            // For widthMin, if a 32 bit number, we need a 6 bit number as we need to return '32'.
+            const int widthMin = V3Number::log2b(nodep->lhsp()->width()) + 1;
+            nodep->dtypeSetLogicUnsized(32, widthMin, VSigning::SIGNED);
         }
     }
     void visit(AstCvtPackString* nodep) override {
diff --git a/test_regress/t/t_math_countbits.v b/test_regress/t/t_math_countbits.v
index 33890f07a..04e7a512f 100644
--- a/test_regress/t/t_math_countbits.v
+++ b/test_regress/t/t_math_countbits.v
@@ -23,19 +23,19 @@ module t(/*AUTOARG*/
    reg [31:0] ctrl1;
    reg [31:0] ctrl2;
 
-   reg [4:0] result_16_1;
-   reg [4:0] result_16_2;
-   reg [4:0] result_16_3;
-   reg [5:0] result_32_1;
-   reg [5:0] result_32_2;
-   reg [5:0] result_32_3;
-   reg [6:0] result_64_1;
-   reg [6:0] result_64_2;
-   reg [6:0] result_64_3;
-   reg [3:0] result_10_3;
-   reg [4:0] result_21_3;
-   reg [5:0] result_59_3;
-   reg [6:0] result_70_3;
+   int result_16_1;
+   int result_16_2;
+   int result_16_3;
+   int result_32_1;
+   int result_32_2;
+   int result_32_3;
+   int result_64_1;
+   int result_64_2;
+   int result_64_3;
+   int result_10_3;
+   int result_21_3;
+   int result_59_3;
+   int result_70_3;
 
    initial begin
       if ($countbits(32'b111100000000, '1) != 4) $stop;
diff --git a/test_regress/t/t_math_svl.v b/test_regress/t/t_math_svl.v
index 04d808141..260e46a3e 100644
--- a/test_regress/t/t_math_svl.v
+++ b/test_regress/t/t_math_svl.v
@@ -14,13 +14,13 @@ module t (/*AUTOARG*/
    reg [15:0] l;
    reg [49:0] q;
    reg [79:0] w;
-   reg [4:0]  lc;
+   int        lc;
    reg        lo;
    reg        l0;
-   reg [5:0]  qc;
+   int        qc;
    reg        qo;
    reg        q0;
-   reg [6:0]  wc;
+   int        wc;
    reg        wo;
    reg        w0;
 
@@ -55,7 +55,7 @@ module t (/*AUTOARG*/
       if ($isunknown(32'b11101011111) != 0) $stop;
       if ($isunknown(32'b10zzzzzzzzz) != 1) $stop;
       if ($bits(0) != 32'd32) $stop;
-      if ($bits(lc) != 5) $stop;
+      if ($bits(lc) != 32) $stop;
       if ($onehot(32'b00000001000000) != 1'b1) $stop;
       if ($onehot(32'b00001001000000) != 1'b0) $stop;
       if ($onehot(32'b0) != 1'b0) $stop;
@@ -81,51 +81,51 @@ module t (/*AUTOARG*/
             q <= ~50'h0;
             w <= ~80'h0;
             //
-            if ({lc,lo,l0} != {5'd0,1'b0,1'b1}) $stop;
-            if ({qc,qo,q0} != {6'd0,1'b0,1'b1}) $stop;
-            if ({wc,wo,w0} != {7'd0,1'b0,1'b1}) $stop;
+            if ({lc,lo,l0} != {32'd0,1'b0,1'b1}) $stop;
+            if ({qc,qo,q0} != {32'd0,1'b0,1'b1}) $stop;
+            if ({wc,wo,w0} != {32'd0,1'b0,1'b1}) $stop;
          end
          if (cyc==3) begin
             l <= 16'b0010110010110111;
             q <= 50'h01_1111_0001;
             w <= 80'h0100_0000_0f00_00f0_0000;
             //
-            if ({lc,lo,l0} != {5'd16,1'b0,1'b0}) $stop;
-            if ({qc,qo,q0} != {6'd50,1'b0,1'b0}) $stop;
-            if ({wc,wo,w0} != {7'd80,1'b0,1'b0}) $stop;
+            if ({lc,lo,l0} != {32'd16,1'b0,1'b0}) $stop;
+            if ({qc,qo,q0} != {32'd50,1'b0,1'b0}) $stop;
+            if ({wc,wo,w0} != {32'd80,1'b0,1'b0}) $stop;
          end
          if (cyc==4) begin
             l <= 16'b0000010000000000;
             q <= 50'h1_0000_0000;
             w <= 80'h010_00000000_00000000;
             //
-            if ({lc,lo,l0} != {5'd9,1'b0,1'b0}) $stop;
-            if ({qc,qo,q0} != {6'd6,1'b0,1'b0}) $stop;
-            if ({wc,wo,w0} != {7'd9,1'b0,1'b0}) $stop;
+            if ({lc,lo,l0} != {32'd9,1'b0,1'b0}) $stop;
+            if ({qc,qo,q0} != {32'd6,1'b0,1'b0}) $stop;
+            if ({wc,wo,w0} != {32'd9,1'b0,1'b0}) $stop;
          end
          if (cyc==5) begin
             l <= 16'b0000000100000000;
             q <= 50'h8000_0000_0000;
             w <= 80'h10_00000000_00000000;
             //
-            if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
-            if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
-            if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
+            if ({lc,lo,l0} != {32'd1,1'b1,1'b1}) $stop;
+            if ({qc,qo,q0} != {32'd1,1'b1,1'b1}) $stop;
+            if ({wc,wo,w0} != {32'd1,1'b1,1'b1}) $stop;
          end
          if (cyc==6) begin
             l <= 16'b0000100100000000;
             q <= 50'h01_00000100;
             w <= 80'h01_00000100_00000000;
             //
-            if ({lc,lo,l0} != {5'd1,1'b1,1'b1}) $stop;
-            if ({qc,qo,q0} != {6'd1,1'b1,1'b1}) $stop;
-            if ({wc,wo,w0} != {7'd1,1'b1,1'b1}) $stop;
+            if ({lc,lo,l0} != {32'd1,1'b1,1'b1}) $stop;
+            if ({qc,qo,q0} != {32'd1,1'b1,1'b1}) $stop;
+            if ({wc,wo,w0} != {32'd1,1'b1,1'b1}) $stop;
          end
          if (cyc==7) begin
             //
-            if ({lc,lo,l0} != {5'd2,1'b0,1'b0}) $stop;
-            if ({qc,qo,q0} != {6'd2,1'b0,1'b0}) $stop;
-            if ({wc,wo,w0} != {7'd2,1'b0,1'b0}) $stop;
+            if ({lc,lo,l0} != {32'd2,1'b0,1'b0}) $stop;
+            if ({qc,qo,q0} != {32'd2,1'b0,1'b0}) $stop;
+            if ({wc,wo,w0} != {32'd2,1'b0,1'b0}) $stop;
          end
          if (cyc==8) begin
          end

From d6126c4b3289d76573c3c9f5b69a371a80b593fb Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Sat, 5 Nov 2022 13:47:34 +0100
Subject: [PATCH 006/156] Remove --no-threads; require --threads 1 for single
 threaded (#3703).

---
 Makefile.in                                 |   4 +-
 docs/guide/exe_verilator.rst                |  13 ++-
 docs/guide/verilating.rst                   |  12 ---
 docs/verilated.dox                          |   1 -
 include/verilated.cpp                       | 102 +++++---------------
 include/verilated.h                         |  52 ++--------
 include/verilated.mk.in                     |  27 +-----
 include/verilated_fst_c.cpp                 |  10 +-
 include/verilated_funcs.h                   |   4 -
 include/verilated_imp.h                     |  10 +-
 include/verilated_profiler.cpp              |   8 +-
 include/verilated_profiler.h                |   2 +-
 include/verilated_threads.h                 |   9 --
 include/verilated_trace.h                   |  23 +----
 include/verilated_trace_imp.h               |  38 +-------
 include/verilated_types.h                   |   4 +-
 include/verilated_vcd_c.cpp                 |  12 ---
 include/verilated_vcd_c.h                   |   4 -
 include/verilated_vpi.cpp                   |  16 +--
 include/verilatedos.h                       |  63 +++++-------
 src/V3EmitCBase.cpp                         |   2 +-
 src/V3EmitCMake.cpp                         |   2 +-
 src/V3EmitMk.cpp                            |   4 -
 src/V3Options.cpp                           |   9 +-
 src/V3Options.h                             |   2 +-
 test_regress/driver.pl                      |   2 +-
 test_regress/t/t_embed1.pl                  |   2 +-
 test_regress/t/t_flag_values_deprecated.out |   5 +
 test_regress/t/t_flag_values_deprecated.pl  |  21 ++++
 test_regress/t/t_gantt.pl                   |   2 +-
 test_regress/t/t_gantt_two.cpp              |   5 +-
 test_regress/t/t_gantt_two.pl               |   6 +-
 test_regress/t/t_hier_block.pl              |   2 +-
 test_regress/t/t_hier_block_cmake.pl        |   6 +-
 test_regress/t/t_hier_block_cmake/main.cpp  |   5 +-
 test_regress/t/t_hier_block_nohier.pl       |   2 +-
 test_regress/t/t_hier_block_sc.pl           |   2 +-
 test_regress/t/t_hier_block_sc_trace_fst.pl |   2 +-
 test_regress/t/t_hier_block_sc_trace_vcd.pl |   2 +-
 test_regress/t/t_hier_block_trace_fst.pl    |   2 +-
 test_regress/t/t_hier_block_trace_vcd.pl    |   2 +-
 test_regress/t/t_hier_block_vlt.pl          |   2 +-
 test_regress/t/t_inst_tree_inl0_pub1.pl     |   2 +-
 test_regress/t/t_lib_prot_shared.pl         |   2 +-
 test_regress/t/t_split_var_0.pl             |   2 +-
 test_regress/t/t_split_var_2_trace.pl       |   2 +-
 test_regress/t/t_threads_counter_0.pl       |   2 +-
 test_regress/t/t_threads_crazy_context.pl   |   4 +-
 test_regress/t/t_timing_debug1.out          |  90 +++++++++++++++++
 test_regress/t/t_timing_debug2.out          |  26 +++++
 test_regress/t/t_trace_litendian.pl         |   2 +-
 test_regress/t/t_trace_litendian_fst.pl     |   2 +-
 test_regress/t/t_trace_litendian_fst_sc.pl  |   2 +-
 test_regress/t/t_verilated_debug.out        |   4 +
 verilator-config.cmake.in                   |  18 +---
 55 files changed, 283 insertions(+), 378 deletions(-)
 create mode 100644 test_regress/t/t_flag_values_deprecated.out
 create mode 100755 test_regress/t/t_flag_values_deprecated.pl

diff --git a/Makefile.in b/Makefile.in
index a8dd0a7fa..63d040be4 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -322,7 +322,7 @@ CPPCHECK_INC = -I$(srcdir)/include -I$(srcdir)/src/obj_dbg -I$(srcdir)/src
 
 cppcheck: $(CPPCHECK_DEP)
 %.cppcheck: %.cpp
-	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 -DVL_THREADED=1 $(CPPCHECK_INC) $<
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $<
 
 CLANGTIDY = clang-tidy
 CLANGTIDY_FLAGS = -config='' \
@@ -330,7 +330,7 @@ CLANGTIDY_FLAGS = -config='' \
 	-checks='-fuchsia-*,-cppcoreguidelines-avoid-c-arrays,-cppcoreguidelines-init-variables,-cppcoreguidelines-avoid-goto,-modernize-avoid-c-arrays,-readability-magic-numbers,-readability-simplify-boolean-expr,-cppcoreguidelines-macro-usage' \
 
 CLANGTIDY_DEP = $(subst .cpp,.cpp.tidy,$(CPPCHECK_CPP))
-CLANGTIDY_DEFS = -DVL_DEBUG=1 -DVL_THREADED=1 -DVL_CPPCHECK=1
+CLANGTIDY_DEFS = -DVL_DEBUG=1 -DVL_CPPCHECK=1
 
 clang-tidy: $(CLANGTIDY_DEP)
 %.cpp.tidy: %.cpp
diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst
index bae014be9..35b589351 100644
--- a/docs/guide/exe_verilator.rst
+++ b/docs/guide/exe_verilator.rst
@@ -1213,15 +1213,18 @@ Summary:
 
 .. option:: --threads <threads>
 
-.. option:: --no-threads
-
-   With "--threads 0" or "--no-threads", the default, the generated model
-   is not thread safe. With "--threads 1", the generated model is single
-   threaded but may run in a multithreaded environment. With "--threads N",
+   With "--threads 1", the default, the generated model is single threaded
+   but may run in a multithreaded environment. With "--threads N",
    where N >= 2, the model is generated to run multithreaded on up to N
    threads. See :ref:`Multithreading`. This option also applies to
    :vlopt:`--trace` (but not :vlopt:`--trace-fst`).
 
+.. option:: --no-threads
+
+   Deprecated and has no effect (ignored).
+
+   In versions prior to 5.004, created a model which was not thread safe.
+
 .. option:: --threads-dpi all
 
 .. option:: --threads-dpi none
diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst
index 3921a1964..f041097d2 100644
--- a/docs/guide/verilating.rst
+++ b/docs/guide/verilating.rst
@@ -183,11 +183,6 @@ Multithreading
 
 Verilator supports multithreaded simulation models.
 
-With :vlopt:`--no-threads`, the default, the model is not thread safe, and
-any use of more than one thread calling into one or even different
-Verilated models may result in unpredictable behavior. This gives the
-highest single thread performance.
-
 With :vlopt:`--threads 1 <--threads>`, the generated model is single
 threaded, however the support libraries are multithread safe. This allows
 different instantiations of model(s) to potentially each be run under a
@@ -203,13 +198,6 @@ oversubscription, the Verilated model should not livelock nor deadlock,
 however, you can expect performance to be far worse than it would be with
 proper ratio of threads and CPU cores.
 
-The remainder of this section describe behavior with :vlopt:`--threads 1
-<--threads>` or :vlopt:`--threads {N} <--threads>` (not
-:vlopt:`--no-threads`).
-
-:code:`VL_THREADED` is defined in the C++ code when compiling a threaded
-Verilated module, causing the Verilated support classes become threadsafe.
-
 The thread used for constructing a model must be the same thread that calls
 :code:`eval()` into the model, this is called the "eval thread". The thread
 used to perform certain global operations such as saving and tracing must
diff --git a/docs/verilated.dox b/docs/verilated.dox
index 5af927ba6..67841f4b1 100644
--- a/docs/verilated.dox
+++ b/docs/verilated.dox
@@ -37,5 +37,4 @@ PREDEFINED             = \
                          "VL_NOT_FINAL=" \
                          "VL_PURE=" \
                          "VL_REQUIRES()=" \
-                         "VL_THREAD_LOCAL=" \
                          "__restrict=" \
diff --git a/include/verilated.cpp b/include/verilated.cpp
index 0d0d1a5c8..148c5b459 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -27,7 +27,7 @@
 //
 // verilated.o may exist both in --lib-create (incrementally linked .a/.so)
 // and the main module.  Both refer the same instance of static
-// variables/VL_THREAD_LOCAL in verilated.o such as Verilated, or
+// variables/thread_local in verilated.o such as Verilated, or
 // VerilatedImpData.  This is important to share that state, but the
 // sharing may cause a double-free error when shutting down because the
 // loader will insert a constructor/destructor at each reference to
@@ -68,9 +68,7 @@
 # include <direct.h>  // mkdir
 #endif
 
-#ifdef VL_THREADED
-# include "verilated_threads.h"
-#endif
+#include "verilated_threads.h"
 // clang-format on
 
 #include "verilated_trace.h"
@@ -96,7 +94,7 @@ VerilatedContext* Verilated::s_lastContextp = nullptr;
 
 // Keep below together in one cache line
 // Internal note: Globals may multi-construct, see verilated.cpp top.
-VL_THREAD_LOCAL Verilated::ThreadLocal Verilated::t_s;
+thread_local Verilated::ThreadLocal Verilated::t_s;
 
 //===========================================================================
 // User definable functions
@@ -193,43 +191,27 @@ void vl_warn(const char* filename, int linenum, const char* hier, const char* ms
 // Wrapper to call certain functions via messages when multithreaded
 
 void VL_FINISH_MT(const char* filename, int linenum, const char* hier) VL_MT_SAFE {
-#ifdef VL_THREADED
     VerilatedThreadMsgQueue::post(VerilatedMsg{[=]() {  //
         vl_finish(filename, linenum, hier);
     }});
-#else
-    vl_finish(filename, linenum, hier);
-#endif
 }
 
 void VL_STOP_MT(const char* filename, int linenum, const char* hier, bool maybe) VL_MT_SAFE {
-#ifdef VL_THREADED
     VerilatedThreadMsgQueue::post(VerilatedMsg{[=]() {  //
         vl_stop_maybe(filename, linenum, hier, maybe);
     }});
-#else
-    vl_stop_maybe(filename, linenum, hier, maybe);
-#endif
 }
 
 void VL_FATAL_MT(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_SAFE {
-#ifdef VL_THREADED
     VerilatedThreadMsgQueue::post(VerilatedMsg{[=]() {  //
         vl_fatal(filename, linenum, hier, msg);
     }});
-#else
-    vl_fatal(filename, linenum, hier, msg);
-#endif
 }
 
 void VL_WARN_MT(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_SAFE {
-#ifdef VL_THREADED
     VerilatedThreadMsgQueue::post(VerilatedMsg{[=]() {  //
         vl_warn(filename, linenum, hier, msg);
     }});
-#else
-    vl_warn(filename, linenum, hier, msg);
-#endif
 }
 
 //===========================================================================
@@ -252,24 +234,16 @@ std::string _vl_string_vprintf(const char* formatp, va_list ap) VL_MT_SAFE {
 }
 
 uint64_t _vl_dbg_sequence_number() VL_MT_SAFE {
-#ifdef VL_THREADED
     static std::atomic<uint64_t> sequence;
-#else
-    static uint64_t sequence = 0;
-#endif
     return ++sequence;
 }
 
 uint32_t VL_THREAD_ID() VL_MT_SAFE {
-#ifdef VL_THREADED
     // Alternative is to use std::this_thread::get_id, but that returns a
     // hard-to-read number and is very slow
     static std::atomic<uint32_t> s_nextId(0);
-    static VL_THREAD_LOCAL uint32_t t_myId = ++s_nextId;
+    static thread_local uint32_t t_myId = ++s_nextId;
     return t_myId;
-#else
-    return 0;
-#endif
 }
 
 void VL_DBG_MSGF(const char* formatp, ...) VL_MT_SAFE {
@@ -288,7 +262,6 @@ void VL_DBG_MSGF(const char* formatp, ...) VL_MT_SAFE {
     VL_PRINTF("-V{t%u,%" PRIu64 "}%s", VL_THREAD_ID(), _vl_dbg_sequence_number(), out.c_str());
 }
 
-#ifdef VL_THREADED
 void VL_PRINTF_MT(const char* formatp, ...) VL_MT_SAFE {
     va_list ap;
     va_start(ap, formatp);
@@ -298,7 +271,6 @@ void VL_PRINTF_MT(const char* formatp, ...) VL_MT_SAFE {
         VL_PRINTF("%s", out.c_str());
     }});
 }
-#endif
 
 //===========================================================================
 // Random -- Mostly called at init time, so not inline.
@@ -317,8 +289,8 @@ static uint32_t vl_sys_rand32() VL_MT_UNSAFE {
 }
 
 uint64_t vl_rand64() VL_MT_SAFE {
-    static VL_THREAD_LOCAL uint64_t t_state[2];
-    static VL_THREAD_LOCAL uint32_t t_seedEpoch = 0;
+    static thread_local uint64_t t_state[2];
+    static thread_local uint32_t t_seedEpoch = 0;
     // For speed, we use a thread-local epoch number to know when to reseed
     // A thread always belongs to a single context, so this works out ok
     if (VL_UNLIKELY(t_seedEpoch != VerilatedContextImp::randSeedEpoch())) {
@@ -762,7 +734,7 @@ void _vl_vsformat(std::string& output, const char* formatp, va_list ap) VL_MT_SA
     // Note uses a single buffer internally; presumes only one usage per printf
     // Note also assumes variables < 64 are not wide, this assumption is
     // sometimes not true in low-level routines written here in verilated.cpp
-    static VL_THREAD_LOCAL char t_tmp[VL_VALUE_STRING_MAX_WIDTH];
+    static thread_local char t_tmp[VL_VALUE_STRING_MAX_WIDTH];
     const char* pctp = nullptr;  // Most recent %##.##g format
     bool inPct = false;
     bool widthSet = false;
@@ -1160,7 +1132,7 @@ IData _vl_vsscanf(FILE* fp,  // If a fscanf
     // Read a Verilog $sscanf/$fscanf style format into the output list
     // The format must be pre-processed (and lower cased) by Verilator
     // Arguments are in "width, arg-value (or WDataIn* if wide)" form
-    static VL_THREAD_LOCAL char t_tmp[VL_VALUE_STRING_MAX_WIDTH];
+    static thread_local char t_tmp[VL_VALUE_STRING_MAX_WIDTH];
     int floc = fbits - 1;
     IData got = 0;
     bool inPct = false;
@@ -1453,7 +1425,7 @@ void VL_FCLOSE_I(IData fdi) VL_MT_SAFE {
 }
 
 void VL_SFORMAT_X(int obits, CData& destr, const char* formatp, ...) VL_MT_SAFE {
-    static VL_THREAD_LOCAL std::string t_output;  // static only for speed
+    static thread_local std::string t_output;  // static only for speed
     t_output = "";
     va_list ap;
     va_start(ap, formatp);
@@ -1464,7 +1436,7 @@ void VL_SFORMAT_X(int obits, CData& destr, const char* formatp, ...) VL_MT_SAFE
 }
 
 void VL_SFORMAT_X(int obits, SData& destr, const char* formatp, ...) VL_MT_SAFE {
-    static VL_THREAD_LOCAL std::string t_output;  // static only for speed
+    static thread_local std::string t_output;  // static only for speed
     t_output = "";
     va_list ap;
     va_start(ap, formatp);
@@ -1475,7 +1447,7 @@ void VL_SFORMAT_X(int obits, SData& destr, const char* formatp, ...) VL_MT_SAFE
 }
 
 void VL_SFORMAT_X(int obits, IData& destr, const char* formatp, ...) VL_MT_SAFE {
-    static VL_THREAD_LOCAL std::string t_output;  // static only for speed
+    static thread_local std::string t_output;  // static only for speed
     t_output = "";
     va_list ap;
     va_start(ap, formatp);
@@ -1486,7 +1458,7 @@ void VL_SFORMAT_X(int obits, IData& destr, const char* formatp, ...) VL_MT_SAFE
 }
 
 void VL_SFORMAT_X(int obits, QData& destr, const char* formatp, ...) VL_MT_SAFE {
-    static VL_THREAD_LOCAL std::string t_output;  // static only for speed
+    static thread_local std::string t_output;  // static only for speed
     t_output = "";
     va_list ap;
     va_start(ap, formatp);
@@ -1497,7 +1469,7 @@ void VL_SFORMAT_X(int obits, QData& destr, const char* formatp, ...) VL_MT_SAFE
 }
 
 void VL_SFORMAT_X(int obits, void* destp, const char* formatp, ...) VL_MT_SAFE {
-    static VL_THREAD_LOCAL std::string t_output;  // static only for speed
+    static thread_local std::string t_output;  // static only for speed
     t_output = "";
     va_list ap;
     va_start(ap, formatp);
@@ -1518,7 +1490,7 @@ void VL_SFORMAT_X(int obits_ignored, std::string& output, const char* formatp, .
 }
 
 std::string VL_SFORMATF_NX(const char* formatp, ...) VL_MT_SAFE {
-    static VL_THREAD_LOCAL std::string t_output;  // static only for speed
+    static thread_local std::string t_output;  // static only for speed
     t_output = "";
     va_list ap;
     va_start(ap, formatp);
@@ -1529,7 +1501,7 @@ std::string VL_SFORMATF_NX(const char* formatp, ...) VL_MT_SAFE {
 }
 
 void VL_WRITEF(const char* formatp, ...) VL_MT_SAFE {
-    static VL_THREAD_LOCAL std::string t_output;  // static only for speed
+    static thread_local std::string t_output;  // static only for speed
     t_output = "";
     va_list ap;
     va_start(ap, formatp);
@@ -1541,7 +1513,7 @@ void VL_WRITEF(const char* formatp, ...) VL_MT_SAFE {
 
 void VL_FWRITEF(IData fpi, const char* formatp, ...) VL_MT_SAFE {
     // While threadsafe, each thread can only access different file handles
-    static VL_THREAD_LOCAL std::string t_output;  // static only for speed
+    static thread_local std::string t_output;  // static only for speed
     t_output = "";
 
     va_list ap;
@@ -1771,7 +1743,7 @@ IData VL_VALUEPLUSARGS_INN(int, const std::string& ld, std::string& rdr) VL_MT_S
 
 const char* vl_mc_scan_plusargs(const char* prefixp) VL_MT_SAFE {
     const std::string& match = Verilated::threadContextp()->impp()->argPlusMatch(prefixp);
-    static VL_THREAD_LOCAL char t_outstr[VL_VALUE_STRING_MAX_WIDTH];
+    static thread_local char t_outstr[VL_VALUE_STRING_MAX_WIDTH];
     if (match.empty()) return nullptr;
     char* dp = t_outstr;
     for (const char* sp = match.c_str() + std::strlen(prefixp) + 1;  // +1 to skip the "+"
@@ -1865,7 +1837,7 @@ IData VL_ATOI_N(const std::string& str, int base) VL_PURE {
 static const char* memhFormat(int nBits) {
     assert((nBits >= 1) && (nBits <= 32));
 
-    static VL_THREAD_LOCAL char t_buf[32];
+    static thread_local char t_buf[32];
     switch ((nBits - 1) / 4) {
     case 0: VL_SNPRINTF(t_buf, 32, "%%01x"); break;
     case 1: VL_SNPRINTF(t_buf, 32, "%%02x"); break;
@@ -1883,7 +1855,7 @@ static const char* memhFormat(int nBits) {
 static const char* formatBinary(int nBits, uint32_t bits) {
     assert((nBits >= 1) && (nBits <= 32));
 
-    static VL_THREAD_LOCAL char t_buf[64];
+    static thread_local char t_buf[64];
     for (int i = 0; i < nBits; i++) {
         const bool isOne = bits & (1 << (nBits - 1 - i));
         t_buf[i] = (isOne ? '1' : '0');
@@ -2474,7 +2446,6 @@ void VerilatedContext::threads(unsigned n) {
             "%Error: Cannot set simulation threads after the thread pool has been created.");
     }
 
-#if VL_THREADED
     if (m_threads == n) return;  // To avoid unnecessary warnings
     m_threads = n;
     const unsigned hardwareThreadsAvailable = std::thread::hardware_concurrency();
@@ -2483,13 +2454,6 @@ void VerilatedContext::threads(unsigned n) {
                      "to %u. This will likely cause significant slowdown.\n",
                      hardwareThreadsAvailable, m_threads);
     }
-#else
-    if (n > 1) {
-        VL_PRINTF_MT("%%Warning: Verilator run-time library built without VL_THREADS. Ignoring "
-                     "call to 'VerilatedContext::threads' with argument %u.\n",
-                     n);
-    }
-#endif
 }
 
 void VerilatedContext::commandArgs(int argc, const char** argv) VL_MT_SAFE_EXCLUDES(m_argMutex) {
@@ -2505,7 +2469,7 @@ void VerilatedContext::commandArgsAdd(int argc, const char** argv)
 const char* VerilatedContext::commandArgsPlusMatch(const char* prefixp)
     VL_MT_SAFE_EXCLUDES(m_argMutex) {
     const std::string& match = impp()->argPlusMatch(prefixp);
-    static VL_THREAD_LOCAL char t_outstr[VL_VALUE_STRING_MAX_WIDTH];
+    static thread_local char t_outstr[VL_VALUE_STRING_MAX_WIDTH];
     if (match.empty()) return "";
     char* dp = t_outstr;
     for (const char* sp = match.c_str(); *sp && (dp - t_outstr) < (VL_VALUE_STRING_MAX_WIDTH - 2);)
@@ -2537,9 +2501,7 @@ void VerilatedContext::addModel(VerilatedModel* modelp) {
 
 VerilatedVirtualBase* VerilatedContext::threadPoolp() {
     if (m_threads == 1) return nullptr;
-#if VL_THREADED
     if (!m_threadPool) m_threadPool.reset(new VlThreadPool{this, m_threads - 1});
-#endif
     return m_threadPool.get();
 }
 
@@ -2701,9 +2663,7 @@ void VerilatedContext::randSeed(int val) VL_MT_SAFE {
     m_s.m_randSeed = val;
     const uint64_t newEpoch = VerilatedContextImp::s().s_randSeedEpoch + 1;
     // Obververs must see new epoch AFTER seed updated
-#ifdef VL_THREADED
     std::atomic_signal_fence(std::memory_order_release);
-#endif
     VerilatedContextImp::s().s_randSeedEpoch = newEpoch;
 }
 uint64_t VerilatedContextImp::randSeedDefault64() const VL_MT_SAFE {
@@ -2760,16 +2720,12 @@ VerilatedSyms::VerilatedSyms(VerilatedContext* contextp)
     : _vm_contextp__(contextp ? contextp : Verilated::threadContextp()) {
     VerilatedContext::checkMagic(_vm_contextp__);
     Verilated::threadContextp(_vm_contextp__);
-#ifdef VL_THREADED
     __Vm_evalMsgQp = new VerilatedEvalMsgQueue;
-#endif
 }
 
 VerilatedSyms::~VerilatedSyms() {
     VerilatedContext::checkMagic(_vm_contextp__);
-#ifdef VL_THREADED
     delete __Vm_evalMsgQp;
-#endif
 }
 
 //===========================================================================
@@ -2791,8 +2747,8 @@ void Verilated::debug(int level) VL_MT_SAFE {
 
 const char* Verilated::catName(const char* n1, const char* n2, const char* delimiter) VL_MT_SAFE {
     // Used by symbol table creation to make module names
-    static VL_THREAD_LOCAL char* t_strp = nullptr;
-    static VL_THREAD_LOCAL size_t t_len = 0;
+    static thread_local char* t_strp = nullptr;
+    static thread_local size_t t_len = 0;
     const size_t newlen = std::strlen(n1) + std::strlen(n2) + std::strlen(delimiter) + 1;
     if (VL_UNLIKELY(!t_strp || newlen > t_len)) {
         if (t_strp) delete[] t_strp;
@@ -2843,11 +2799,7 @@ void Verilated::removeFlushCb(VoidPCb cb, void* datap) VL_MT_SAFE {
 }
 void Verilated::runFlushCallbacks() VL_MT_SAFE {
     // Flush routines may call flush, so avoid mutex deadlock
-#ifdef VL_THREADED
     static std::atomic<int> s_recursing;
-#else
-    static int s_recursing = 0;
-#endif
     if (!s_recursing++) {
         const VerilatedLockGuard lock{VlCbStatic.s_flushMutex};
         runCallbacks(VlCbStatic.s_flushCbs);
@@ -2870,11 +2822,7 @@ void Verilated::removeExitCb(VoidPCb cb, void* datap) VL_MT_SAFE {
     removeCb(cb, datap, VlCbStatic.s_exitCbs);
 }
 void Verilated::runExitCallbacks() VL_MT_SAFE {
-#ifdef VL_THREADED
     static std::atomic<int> s_recursing;
-#else
-    static int s_recursing = 0;
-#endif
     if (!s_recursing++) {
         const VerilatedLockGuard lock{VlCbStatic.s_exitMutex};
         runCallbacks(VlCbStatic.s_exitCbs);
@@ -2908,17 +2856,14 @@ void Verilated::mkdir(const char* dirname) VL_MT_UNSAFE {
 }
 
 void Verilated::quiesce() VL_MT_SAFE {
-#ifdef VL_THREADED
     // Wait until all threads under this evaluation are quiet
     // THREADED-TODO
-#endif
 }
 
 int Verilated::exportFuncNum(const char* namep) VL_MT_SAFE {
     return VerilatedImp::exportFind(namep);
 }
 
-#ifdef VL_THREADED
 void Verilated::endOfThreadMTaskGuts(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE {
     VL_DEBUG_IF(VL_DBG_MSGF("End of thread mtask\n"););
     VerilatedThreadMsgQueue::flush(evalMsgQp);
@@ -2932,7 +2877,6 @@ void Verilated::endOfEval(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE {
     VL_DEBUG_IF(VL_DBG_MSGF("End-of-eval cleanup\n"););
     evalMsgQp->process();
 }
-#endif
 
 //===========================================================================
 // VerilatedImp:: Methods
@@ -3138,7 +3082,7 @@ void VerilatedHierarchy::remove(VerilatedScope* fromp, VerilatedScope* top) {
 //===========================================================================
 // VerilatedOneThreaded:: Methods
 
-#if defined(VL_THREADED) && defined(VL_DEBUG)
+#ifdef VL_DEBUG
 void VerilatedAssertOneThread::fatal_different() VL_MT_SAFE {
     VL_FATAL_MT(__FILE__, __LINE__, "",
                 "Routine called that is single threaded, but called from"
diff --git a/include/verilated.h b/include/verilated.h
index 66ae6017b..e07c8f878 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -54,11 +54,9 @@
 #include <unordered_set>
 #include <vector>
 // <iostream> avoided to reduce compile time
-#ifdef VL_THREADED
-# include <atomic>
-# include <mutex>
-# include <thread>
-#endif
+#include <atomic>
+#include <mutex>
+#include <thread>
 
 // Allow user to specify their own include file
 #ifdef VL_VERILATED_INCLUDE
@@ -149,8 +147,6 @@ enum VerilatedVarFlags {
 // Return current thread ID (or 0), not super fast, cache if needed
 extern uint32_t VL_THREAD_ID() VL_MT_SAFE;
 
-#if VL_THREADED
-
 #define VL_LOCK_SPINS 50000  /// Number of times to spin for a mutex before yielding
 
 /// Mutex, wrapped to allow -fthread_safety checks
@@ -202,34 +198,12 @@ public:
     void unlock() VL_RELEASE() VL_MT_SAFE { m_mutexr.unlock(); }
 };
 
-#else  // !VL_THREADED
-
-// Empty non-threaded mutex to avoid #ifdefs in consuming code
-class VerilatedMutex final {
-public:
-    void lock() {}  // LCOV_EXCL_LINE
-    void unlock() {}  // LCOV_EXCL_LINE
-};
-
-// Empty non-threaded lock guard to avoid #ifdefs in consuming code
-class VerilatedLockGuard final {
-    VL_UNCOPYABLE(VerilatedLockGuard);
-
-public:
-    explicit VerilatedLockGuard(VerilatedMutex&) {}
-    ~VerilatedLockGuard() = default;
-    void lock() {}  // LCOV_EXCL_LINE
-    void unlock() {}  // LCOV_EXCL_LINE
-};
-
-#endif  // VL_THREADED
-
 // Internals: Remember the calling thread at construction time, and make
 // sure later calls use same thread
 
 class VerilatedAssertOneThread final {
     // MEMBERS
-#if defined(VL_THREADED) && defined(VL_DEBUG)
+#ifdef VL_DEBUG
     uint32_t m_threadid;  // Thread that is legal
 public:
     // CONSTRUCTORS
@@ -250,7 +224,7 @@ public:
         }
     }
     static void fatal_different() VL_MT_SAFE;
-#else  // !VL_THREADED || !VL_DEBUG
+#else  // !VL_DEBUG
 public:
     void check() {}
 #endif
@@ -343,7 +317,7 @@ class VerilatedContext VL_NOT_FINAL {
 protected:
     // MEMBERS
     // Slow path variables
-    mutable VerilatedMutex m_mutex;  // Mutex for most s_s/s_ns members, when VL_THREADED
+    mutable VerilatedMutex m_mutex;  // Mutex for most s_s/s_ns members
 
     struct Serialized {  // All these members serialized/deserialized
         // No std::strings or pointers or will serialize badly!
@@ -397,11 +371,7 @@ protected:
     // Implementation details
     const std::unique_ptr<VerilatedContextImpData> m_impdatap;
     // Number of threads to use for simulation (size of m_threadPool + 1 for main thread)
-#ifdef VL_THREADED
     unsigned m_threads = std::thread::hardware_concurrency();
-#else
-    const unsigned m_threads = 1;
-#endif
     // The thread pool shared by all models added to this context
     std::unique_ptr<VerilatedVirtualBase> m_threadPool;
     // The execution profiler shared by all models added to this context
@@ -611,9 +581,7 @@ public:  // But for internal use only
     // MEMBERS
     // Keep first so is at zero offset for fastest code
     VerilatedContext* const _vm_contextp__;  // Context for current model
-#ifdef VL_THREADED
     VerilatedEvalMsgQueue* __Vm_evalMsgQp;
-#endif
     explicit VerilatedSyms(VerilatedContext* contextp);  // Pass null for default context
     ~VerilatedSyms();
 };
@@ -694,17 +662,15 @@ class Verilated final {
     static VerilatedContext* s_lastContextp;  // Last context constructed/attached
 
     // Not covered by mutex, as per-thread
-    static VL_THREAD_LOCAL struct ThreadLocal {
+    static thread_local struct ThreadLocal {
         // No non-POD objects here due to this:
         // Internal note: Globals may multi-construct, see verilated.cpp top.
 
         // Fast path
         VerilatedContext* t_contextp = nullptr;  // Thread's context
-#ifdef VL_THREADED
         uint32_t t_mtaskId = 0;  // mtask# executing on this thread
         // Messages maybe pending on thread, needs end-of-eval calls
         uint32_t t_endOfEvalReqd = 0;
-#endif
         const VerilatedScope* t_dpiScopep = nullptr;  // DPI context scope
         const char* t_dpiFilename = nullptr;  // DPI context filename
         int t_dpiLineno = 0;  // DPI context line number
@@ -911,7 +877,6 @@ public:
     static int dpiLineno() VL_MT_SAFE { return t_s.t_dpiLineno; }
     static int exportFuncNum(const char* namep) VL_MT_SAFE;
 
-#ifdef VL_THREADED
     // Internal: Set the mtaskId, called when an mtask starts
     // Per thread, so no need to be in VerilatedContext
     static void mtaskId(uint32_t id) VL_MT_SAFE { t_s.t_mtaskId = id; }
@@ -925,12 +890,9 @@ public:
     }
     // Internal: Called at end of eval loop
     static void endOfEval(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE;
-#endif
 
 private:
-#ifdef VL_THREADED
     static void endOfThreadMTaskGuts(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE;
-#endif
 };
 
 void VerilatedContext::debug(int val) VL_MT_SAFE { Verilated::debug(val); }
diff --git a/include/verilated.mk.in b/include/verilated.mk.in
index b01799dfb..9dcff5121 100644
--- a/include/verilated.mk.in
+++ b/include/verilated.mk.in
@@ -130,19 +130,8 @@ endif
 #######################################################################
 ##### Threaded builds
 
-ifneq ($(VM_C11),0)
- ifneq ($(VM_C11),)
-  VK_C11=1
- endif
-endif
-
-ifneq ($(VM_THREADS),0)
- ifneq ($(VM_THREADS),)
-  CPPFLAGS += -DVL_THREADED
-  VK_C11=1
-  VK_LIBS_THREADED=1
- endif
-endif
+CPPFLAGS += $(CFG_CXXFLAGS_STD_NEWEST)
+LDLIBS += $(CFG_LDLIBS_THREADS)
 
 ifneq ($(VM_TIMING),0)
  ifneq ($(VM_TIMING),)
@@ -150,18 +139,6 @@ ifneq ($(VM_TIMING),0)
  endif
 endif
 
-ifneq ($(VK_C11),0)
- ifneq ($(VK_C11),)
-  # Need C++11 at least, so always default to newest
-  CPPFLAGS += $(CFG_CXXFLAGS_STD_NEWEST)
- endif
-endif
-
-ifneq ($(VK_LIBS_THREADED),0)
- ifneq ($(VK_LIBS_THREADED),)
-  LDLIBS += $(CFG_LDLIBS_THREADS)
- endif
-endif
 
 #######################################################################
 ### Aggregates
diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp
index ad3de6c26..1247b46ed 100644
--- a/include/verilated_fst_c.cpp
+++ b/include/verilated_fst_c.cpp
@@ -28,10 +28,8 @@
 #include "verilated_fst_c.h"
 
 // GTKWave configuration
-#ifdef VL_THREADED
-# define HAVE_LIBPTHREAD
-# define FST_WRITER_PARALLEL
-#endif
+#define HAVE_LIBPTHREAD
+#define FST_WRITER_PARALLEL
 
 // Include the GTKWave implementation directly
 #define FST_CONFIG_INCLUDE "fst_config.h"
@@ -248,14 +246,11 @@ void VerilatedFst::declDouble(uint32_t code, const char* name, int dtypenum, fst
 // Get/commit trace buffer
 
 VerilatedFst::Buffer* VerilatedFst::getTraceBuffer() {
-#ifdef VL_THREADED
     if (offload()) return new OffloadBuffer{*this};
-#endif
     return new Buffer{*this};
 }
 
 void VerilatedFst::commitTraceBuffer(VerilatedFst::Buffer* bufp) {
-#ifdef VL_THREADED
     if (offload()) {
         OffloadBuffer* const offloadBufferp = static_cast<OffloadBuffer*>(bufp);
         if (offloadBufferp->m_offloadBufferWritep) {
@@ -263,7 +258,6 @@ void VerilatedFst::commitTraceBuffer(VerilatedFst::Buffer* bufp) {
             return;  // Buffer will be deleted by the offload thread
         }
     }
-#endif
     delete bufp;
 }
 
diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h
index 1733d33d4..c226426d8 100644
--- a/include/verilated_funcs.h
+++ b/include/verilated_funcs.h
@@ -73,11 +73,7 @@ extern void VL_WARN_MT(const char* filename, int linenum, const char* hier,
 
 // clang-format off
 /// Print a string, multithread safe. Eventually VL_PRINTF will get called.
-#ifdef VL_THREADED
 extern void VL_PRINTF_MT(const char* formatp, ...) VL_ATTR_PRINTF(1) VL_MT_SAFE;
-#else
-# define VL_PRINTF_MT VL_PRINTF  // The following parens will take care of themselves
-#endif
 // clang-format on
 
 /// Print a debug message from internals with standard prefix, with printf style format
diff --git a/include/verilated_imp.h b/include/verilated_imp.h
index cc1971d04..afc3d01c8 100644
--- a/include/verilated_imp.h
+++ b/include/verilated_imp.h
@@ -41,10 +41,8 @@
 #include <string>
 #include <utility>
 #include <vector>
-#ifdef VL_THREADED
-# include <functional>
-# include <queue>
-#endif
+#include <functional>
+#include <queue>
 // clang-format on
 
 class VerilatedScope;
@@ -52,7 +50,6 @@ class VerilatedScope;
 //======================================================================
 // Threaded message passing
 
-#ifdef VL_THREADED
 // Message, enqueued on an mtask, and consumed on the main eval thread
 class VerilatedMsg final {
 public:
@@ -152,7 +149,7 @@ private:
     VL_UNCOPYABLE(VerilatedThreadMsgQueue);
     // METHODS
     static VerilatedThreadMsgQueue& threadton() {
-        static VL_THREAD_LOCAL VerilatedThreadMsgQueue t_s;
+        static thread_local VerilatedThreadMsgQueue t_s;
         return t_s;
     }
 
@@ -178,7 +175,6 @@ public:
         }
     }
 };
-#endif  // VL_THREADED
 
 // FILE* list constructed from a file-descriptor
 class VerilatedFpList final {
diff --git a/include/verilated_profiler.cpp b/include/verilated_profiler.cpp
index b04cc34e3..85d76352b 100644
--- a/include/verilated_profiler.cpp
+++ b/include/verilated_profiler.cpp
@@ -20,9 +20,7 @@
 
 #include "verilated_profiler.h"
 
-#if VL_THREADED
 #include "verilated_threads.h"
-#endif
 
 #include <fstream>
 #include <string>
@@ -32,7 +30,7 @@
 
 // Internal note: Globals may multi-construct, see verilated.cpp top.
 
-VL_THREAD_LOCAL VlExecutionProfiler::ExecutionTrace VlExecutionProfiler::t_trace;
+thread_local VlExecutionProfiler::ExecutionTrace VlExecutionProfiler::t_trace;
 
 constexpr const char* const VlExecutionRecord::s_ascii[];
 
@@ -105,7 +103,6 @@ void VlExecutionProfiler::configure() {
 
 VerilatedVirtualBase* VlExecutionProfiler::construct(VerilatedContext& context) {
     VlExecutionProfiler* const selfp = new VlExecutionProfiler{context};
-#if VL_THREADED
     if (VlThreadPool* const threadPoolp = static_cast<VlThreadPool*>(context.threadPoolp())) {
         for (int i = 0; i < threadPoolp->numThreads(); ++i) {
             // Data to pass to worker thread initialization
@@ -126,7 +123,6 @@ VerilatedVirtualBase* VlExecutionProfiler::construct(VerilatedContext& context)
             threadPoolp->workerp(i)->wait();
         }
     }
-#endif
     return selfp;
 }
 
@@ -172,9 +168,7 @@ void VlExecutionProfiler::dump(const char* filenamep, uint64_t tickEnd)
             Verilated::threadContextp()->profExecWindow());
     const unsigned threads = static_cast<unsigned>(m_traceps.size());
     fprintf(fp, "VLPROF stat threads %u\n", threads);
-#ifdef VL_THREADED
     fprintf(fp, "VLPROF stat yields %" PRIu64 "\n", VlMTaskVertex::yields());
-#endif
 
     // Copy /proc/cpuinfo into this output so verilator_gantt can be run on
     // a different machine
diff --git a/include/verilated_profiler.h b/include/verilated_profiler.h
index 5ddf3b0d9..5ca1271ff 100644
--- a/include/verilated_profiler.h
+++ b/include/verilated_profiler.h
@@ -151,7 +151,7 @@ class VlExecutionProfiler final : public VerilatedVirtualBase {
 
     // STATE
     VerilatedContext& m_context;  // The context this profiler is under
-    static VL_THREAD_LOCAL ExecutionTrace t_trace;  // thread-local trace buffers
+    static thread_local ExecutionTrace t_trace;  // thread-local trace buffers
     mutable VerilatedMutex m_mutex;
     // Map from thread id to &t_trace of given thread
     std::map<uint32_t, ExecutionTrace*> m_traceps VL_GUARDED_BY(m_mutex);
diff --git a/include/verilated_threads.h b/include/verilated_threads.h
index b595c1bca..6100ac057 100644
--- a/include/verilated_threads.h
+++ b/include/verilated_threads.h
@@ -27,15 +27,6 @@
 
 #include "verilated.h"  // for VerilatedMutex and clang annotations
 
-#ifndef VL_THREADED
-// Hitting this likely means verilated_threads.cpp is being compiled when
-// 'verilator --threads' was not used.  'verilator --threads' sets
-// VL_THREADED.
-// Alternatively it is always safe but may harm performance to always
-// define VL_THREADED for all compiles.
-#error "verilated_threads.h/cpp expected VL_THREADED (from verilator --threads)"
-#endif
-
 #include <atomic>
 #include <condition_variable>
 #include <set>
diff --git a/include/verilated_trace.h b/include/verilated_trace.h
index 151d2c9f2..2d75ea0ab 100644
--- a/include/verilated_trace.h
+++ b/include/verilated_trace.h
@@ -35,10 +35,8 @@
 #include <unordered_set>
 #include <vector>
 
-#ifdef VL_THREADED
-# include <deque>
-# include <thread>
-#endif
+#include <deque>
+#include <thread>
 
 // clang-format on
 
@@ -48,7 +46,6 @@ class VerilatedTraceBuffer;
 template <class T_Buffer>
 class VerilatedTraceOffloadBuffer;
 
-#ifdef VL_THREADED
 //=============================================================================
 // Offloaded tracing
 
@@ -117,7 +114,6 @@ public:
         SHUTDOWN = 0xf  // Shutdown worker thread, also marks end of buffer
     };
 };
-#endif
 
 //=============================================================================
 // VerilatedTraceConfig
@@ -186,10 +182,9 @@ private:
             , m_userp{userp} {}
     };
 
-    bool m_offload = false;  // Use the offload thread (ignored if !VL_THREADED)
-    bool m_parallel = false;  // Use parallel tracing (ignored if !VL_THREADED)
+    bool m_offload = false;  // Use the offload thread
+    bool m_parallel = false;  // Use parallel tracing
 
-#ifdef VL_THREADED
     struct ParallelWorkerData {
         const dumpCb_t m_cb;  // The callback
         void* const m_userp;  // The use pointer to pass to the callback
@@ -209,7 +204,6 @@ private:
 
     // Passed a ParallelWorkerData*, second argument is ignored
     static void parallelWorkerTask(void*, bool);
-#endif
 
 protected:
     uint32_t* m_sigs_oldvalp = nullptr;  // Previous value store
@@ -251,7 +245,6 @@ private:
     // Close the file on termination
     static void onExit(void* selfp) VL_MT_UNSAFE_ONE;
 
-#ifdef VL_THREADED
     // Number of total offload buffers that have been allocated
     uint32_t m_numOffloadBuffers = 0;
     // Size of offload buffers
@@ -282,7 +275,6 @@ private:
 
     // Shut down and join worker, if it's running, otherwise do nothing
     void shutdownOffloadWorker();
-#endif
 
     // CONSTRUCTORS
     VL_UNCOPYABLE(VerilatedTrace);
@@ -317,13 +309,8 @@ protected:
     void closeBase();
     void flushBase();
 
-#ifdef VL_THREADED
     bool offload() const { return m_offload; }
     bool parallel() const { return m_parallel; }
-#else
-    static constexpr bool offload() { return false; }
-    static constexpr bool parallel() { return false; }
-#endif
 
     //=========================================================================
     // Virtual functions to be provided by the format specific implementation
@@ -475,7 +462,6 @@ public:
     }
 };
 
-#ifdef VL_THREADED
 //=============================================================================
 // VerilatedTraceOffloadBuffer
 
@@ -548,6 +534,5 @@ public:
         VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp););
     }
 };
-#endif
 
 #endif  // guard
diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h
index 21756dc77..7718ded13 100644
--- a/include/verilated_trace_imp.h
+++ b/include/verilated_trace_imp.h
@@ -26,10 +26,8 @@
 
 #include "verilated_intrinsics.h"
 #include "verilated_trace.h"
-#ifdef VL_THREADED
-# include "verilated_threads.h"
-# include <list>
-#endif
+#include "verilated_threads.h"
+#include <list>
 
 #if 0
 # include <iostream>
@@ -78,7 +76,6 @@ static std::string doubleToTimescale(double value) {
     return valuestr;  // Gets converted to string, so no ref to stack
 }
 
-#ifdef VL_THREADED
 //=========================================================================
 // Buffer management
 
@@ -250,14 +247,11 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::shutdownOffloadWorker() {
     m_workerThread.reset(nullptr);
 }
 
-#endif
-
 //=============================================================================
 // Life cycle
 
 template <>
 void VerilatedTrace<VL_SUB_T, VL_BUF_T>::closeBase() {
-#ifdef VL_THREADED
     if (offload()) {
         shutdownOffloadWorker();
         while (m_numOffloadBuffers) {
@@ -265,12 +259,10 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::closeBase() {
             --m_numOffloadBuffers;
         }
     }
-#endif
 }
 
 template <>
 void VerilatedTrace<VL_SUB_T, VL_BUF_T>::flushBase() {
-#ifdef VL_THREADED
     if (offload()) {
         // Hand an empty buffer to the worker thread
         uint32_t* const bufferp = getOffloadBuffer();
@@ -280,7 +272,6 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::flushBase() {
         // this ensures all previous buffers have been processed.
         waitForOffloadBuffer(bufferp);
     }
-#endif
 }
 
 //=============================================================================
@@ -368,7 +359,6 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::traceInit() VL_MT_UNSAFE {
     Verilated::addFlushCb(VerilatedTrace<VL_SUB_T, VL_BUF_T>::onFlush, this);
     Verilated::addExitCb(VerilatedTrace<VL_SUB_T, VL_BUF_T>::onExit, this);
 
-#ifdef VL_THREADED
     if (offload()) {
         // Compute offload buffer size. we need to be able to store a new value for
         // each signal, which is 'nextCode()' entries after the init callbacks
@@ -381,7 +371,6 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::traceInit() VL_MT_UNSAFE {
         m_workerThread.reset(
             new std::thread{&VerilatedTrace<VL_SUB_T, VL_BUF_T>::offloadWorkerThreadMain, this});
     }
-#endif
 }
 
 template <>
@@ -468,7 +457,6 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::dumpvars(int level, const std::string&
     }
 }
 
-#ifdef VL_THREADED
 template <>
 void VerilatedTrace<VL_SUB_T, VL_BUF_T>::parallelWorkerTask(void* datap, bool) {
     ParallelWorkerData* const wdp = reinterpret_cast<ParallelWorkerData*>(datap);
@@ -493,11 +481,9 @@ VL_ATTR_NOINLINE void VerilatedTrace<VL_SUB_T, VL_BUF_T>::ParallelWorkerData::wa
     m_cv.wait(lock, [this] { return m_ready.load(std::memory_order_relaxed); });
     m_waiting = false;
 }
-#endif
 
 template <>
 void VerilatedTrace<VL_SUB_T, VL_BUF_T>::runCallbacks(const std::vector<CallbackRecord>& cbVec) {
-#ifdef VL_THREADED
     if (parallel()) {
         // If tracing in parallel, dispatch to the thread pool
         VlThreadPool* threadPoolp = static_cast<VlThreadPool*>(m_contextp->threadPoolp());
@@ -538,7 +524,6 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::runCallbacks(const std::vector<Callback
         // Done
         return;
     }
-#endif
     // Fall back on sequential execution
     for (const CallbackRecord& cbr : cbVec) {
         Buffer* const traceBufferp = getTraceBuffer();
@@ -551,15 +536,11 @@ template <>
 void VerilatedTrace<VL_SUB_T, VL_BUF_T>::runOffloadedCallbacks(
     const std::vector<CallbackRecord>& cbVec) {
     // Fall back on sequential execution
-#ifdef VL_THREADED
     for (const CallbackRecord& cbr : cbVec) {
         Buffer* traceBufferp = getTraceBuffer();
         cbr.m_dumpOffloadCb(cbr.m_userp, static_cast<OffloadBuffer*>(traceBufferp));
         commitTraceBuffer(traceBufferp);
     }
-#else
-    if (!cbVec.empty()) VL_FATAL_MT(__FILE__, __LINE__, "", "Unreachable");
-#endif
 }
 
 template <>
@@ -586,11 +567,8 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::dump(uint64_t timeui) VL_MT_SAFE_EXCLUD
         if (!preChangeDump()) return;
     }
 
-#ifdef VL_THREADED
     uint32_t* bufferp = nullptr;
-#endif
     if (offload()) {
-#ifdef VL_THREADED
         // Currently only incremental dumps run on the worker thread
         if (VL_LIKELY(!m_fullDump)) {
             // Get the offload buffer we are about to fill
@@ -607,9 +585,6 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::dump(uint64_t timeui) VL_MT_SAFE_EXCLUD
             flushBase();
             emitTimeChange(timeui);
         }
-#else
-        VL_FATAL_MT(__FILE__, __LINE__, "", "Unreachable");
-#endif
     } else {
         // Update time point
         emitTimeChange(timeui);
@@ -636,7 +611,6 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::dump(uint64_t timeui) VL_MT_SAFE_EXCLUD
         cbr.m_cleanupCb(cbr.m_userp, self());
     }
 
-#ifdef VL_THREADED
     if (offload() && VL_LIKELY(bufferp)) {
         // Mark end of the offload buffer we just filled
         *m_offloadBufferWritep++ = VerilatedTraceOffloadCommand::END;
@@ -651,7 +625,6 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::dump(uint64_t timeui) VL_MT_SAFE_EXCLUD
         // Pass it to the worker thread
         m_offloadBuffersToWorker.put(bufferp);
     }
-#endif
 }
 
 //=============================================================================
@@ -685,11 +658,6 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::addModel(VerilatedModel* modelp)
 
     // Get the desired trace config from the model
     const std::unique_ptr<VerilatedTraceConfig> configp = modelp->traceConfig();
-#ifndef VL_THREADED
-    if (configp->m_useOffloading) {
-        VL_FATAL_MT(__FILE__, __LINE__, "", "Cannot use trace offloading without VL_THREADED");
-    }
-#endif
 
     // Configure trace base class
     if (!firstModel) {
@@ -915,7 +883,6 @@ void VerilatedTraceBuffer<VL_BUF_T>::fullDouble(uint32_t* oldp, double newval) {
     emitDouble(code, newval);
 }
 
-#ifdef VL_THREADED
 //=========================================================================
 // VerilatedTraceOffloadBuffer
 
@@ -934,6 +901,5 @@ VerilatedTraceOffloadBuffer<VL_BUF_T>::VerilatedTraceOffloadBuffer(VL_SUB_T& own
         m_offloadBufferWritep += 2;
     }
 }
-#endif
 
 #endif  // VL_CPPCHECK
diff --git a/include/verilated_types.h b/include/verilated_types.h
index dba797b74..0aae11ea1 100644
--- a/include/verilated_types.h
+++ b/include/verilated_types.h
@@ -367,7 +367,7 @@ public:
     // Can't just overload operator[] or provide a "at" reference to set,
     // because we need to be able to insert only when the value is set
     T_Value& at(int32_t index) {
-        static VL_THREAD_LOCAL T_Value s_throwAway;
+        static thread_local T_Value s_throwAway;
         // Needs to work for dynamic arrays, so does not use T_MaxSize
         if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) {
             s_throwAway = atDefault();
@@ -378,7 +378,7 @@ public:
     }
     // Accessing. Verilog: v = assoc[index]
     const T_Value& at(int32_t index) const {
-        static VL_THREAD_LOCAL T_Value s_throwAway;
+        static thread_local T_Value s_throwAway;
         // Needs to work for dynamic arrays, so does not use T_MaxSize
         if (VL_UNLIKELY(index < 0 || index >= m_deque.size())) {
             return atDefault();
diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp
index 2d0cc57f0..a0145b2af 100644
--- a/include/verilated_vcd_c.cpp
+++ b/include/verilated_vcd_c.cpp
@@ -230,12 +230,10 @@ VerilatedVcd::~VerilatedVcd() {
     if (m_wrBufp) VL_DO_CLEAR(delete[] m_wrBufp, m_wrBufp = nullptr);
     deleteNameMap();
     if (m_filep && m_fileNewed) VL_DO_CLEAR(delete m_filep, m_filep = nullptr);
-#ifdef VL_THREADED
     if (parallel()) {
         assert(m_numBuffers == m_freeBuffers.size());
         for (auto& pair : m_freeBuffers) VL_DO_CLEAR(delete[] pair.first, pair.first = nullptr);
     }
-#endif
 }
 
 void VerilatedVcd::closePrev() {
@@ -574,7 +572,6 @@ void VerilatedVcd::declDouble(uint32_t code, const char* name, bool array, int a
 
 VerilatedVcd::Buffer* VerilatedVcd::getTraceBuffer() {
     VerilatedVcd::Buffer* const bufp = new Buffer{*this};
-#ifdef VL_THREADED
     if (parallel()) {
         // Note: This is called from VeriltedVcd::dump, which already holds the lock
         // If no buffer available, allocate a new one
@@ -593,14 +590,12 @@ VerilatedVcd::Buffer* VerilatedVcd::getTraceBuffer() {
         bufp->m_size = pair.second;
         bufp->adjustGrowp();
     }
-#endif
     // Return the buffer
     return bufp;
 }
 
 void VerilatedVcd::commitTraceBuffer(VerilatedVcd::Buffer* bufp) {
     if (parallel()) {
-#if VL_THREADED
         // Note: This is called from VeriltedVcd::dump, which already holds the lock
         // Resize output buffer. Note, we use the full size of the trace buffer, as
         // this is a lot more stable than the actual occupancy of the trace buffer.
@@ -616,9 +611,6 @@ void VerilatedVcd::commitTraceBuffer(VerilatedVcd::Buffer* bufp) {
         bufferCheck();
         // Put buffer back on free list
         m_freeBuffers.emplace_back(bufp->m_bufp, bufp->m_size);
-#else
-        VL_FATAL_MT(__FILE__, __LINE__, "", "Unreachable");
-#endif
     } else {
         // Needs adjusting for emitTimeChange
         m_writep = bufp->m_writep;
@@ -665,7 +657,6 @@ void VerilatedVcdBuffer::finishLine(uint32_t code, char* writep) {
     m_writep = writep + suffixp[VL_TRACE_SUFFIX_ENTRY_SIZE - 1];
 
     if (m_owner.parallel()) {
-#ifdef VL_THREADED
         // Double the size of the buffer if necessary
         if (VL_UNLIKELY(m_writep >= m_growp)) {
             // Compute occupied size of current buffer
@@ -685,9 +676,6 @@ void VerilatedVcdBuffer::finishLine(uint32_t code, char* writep) {
             // Adjust resize limit
             adjustGrowp();
         }
-#else
-        VL_FATAL_MT(__FILE__, __LINE__, "", "Unreachable");
-#endif
     } else {
         // Flush the write buffer if there's not enough space left for new information
         // We only call this once per vector, so we need enough slop for a very wide "b###" line
diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h
index 2967225b1..166a48322 100644
--- a/include/verilated_vcd_c.h
+++ b/include/verilated_vcd_c.h
@@ -65,11 +65,9 @@ private:
     using NameMap = std::map<const std::string, const std::string>;
     NameMap* m_namemapp = nullptr;  // List of names for the header
 
-#ifdef VL_THREADED
     // Vector of free trace buffers as (pointer, size) pairs.
     std::vector<std::pair<char*, size_t>> m_freeBuffers;
     size_t m_numBuffers = 0;  // Number of trace buffers allocated
-#endif
 
     void bufferResize(size_t minsize);
     void bufferFlush() VL_MT_UNSAFE_ONE;
@@ -187,7 +185,6 @@ class VerilatedVcdBuffer VL_NOT_FINAL {
     // The maximum number of bytes a single signal can emit
     const size_t m_maxSignalBytes = m_owner.m_maxSignalBytes;
 
-#ifdef VL_THREADED
     // Additional data for parallel tracing only
     char* m_bufp = nullptr;  // The beginning of the trace buffer
     size_t m_size = 0;  // The size of the buffer at m_bufp
@@ -197,7 +194,6 @@ class VerilatedVcdBuffer VL_NOT_FINAL {
         m_growp = (m_bufp + m_size) - (2 * m_maxSignalBytes);
         assert(m_growp >= m_bufp + m_maxSignalBytes);
     }
-#endif
 
     void finishLine(uint32_t code, char* writep);
 
diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp
index 56f7d5e42..023c6683d 100644
--- a/include/verilated_vpi.cpp
+++ b/include/verilated_vpi.cpp
@@ -71,7 +71,7 @@ class VerilatedVpio VL_NOT_FINAL {
 
     // MEM MANGLEMENT
     // Internal note: Globals may multi-construct, see verilated.cpp top.
-    static VL_THREAD_LOCAL uint8_t* t_freeHead;
+    static thread_local uint8_t* t_freeHead;
 
 public:
     // CONSTRUCTORS
@@ -205,7 +205,7 @@ public:
     const VerilatedRange* rangep() const override { return &get_range(); }
     const char* name() const override { return m_varp->name(); }
     const char* fullname() const override {
-        static VL_THREAD_LOCAL std::string t_out;
+        static thread_local std::string t_out;
         t_out = std::string{m_scopep->name()} + "." + name();
         return t_out.c_str();
     }
@@ -348,7 +348,7 @@ public:
     uint32_t size() const override { return varp()->packed().elements(); }
     const VerilatedRange* rangep() const override { return &(varp()->packed()); }
     const char* fullname() const override {
-        static VL_THREAD_LOCAL std::string t_out;
+        static thread_local std::string t_out;
         constexpr size_t LEN_MAX_INDEX = 25;
         char num[LEN_MAX_INDEX];
         VL_SNPRINTF(num, LEN_MAX_INDEX, "%d", m_index);
@@ -666,7 +666,7 @@ public:
 // Statics
 // Internal note: Globals may multi-construct, see verilated.cpp top.
 
-VL_THREAD_LOCAL uint8_t* VerilatedVpio::t_freeHead = nullptr;
+thread_local uint8_t* VerilatedVpio::t_freeHead = nullptr;
 
 //======================================================================
 // VerilatedVpiError
@@ -708,7 +708,7 @@ public:
     }
     void setMessage(const std::string& file, PLI_INT32 line, const char* message, ...) {
         // message cannot be a const string& as va_start cannot use a reference
-        static VL_THREAD_LOCAL std::string t_filehold;
+        static thread_local std::string t_filehold;
         va_list args;
         va_start(args, message);
         VL_VSNPRINTF(m_buff, sizeof(m_buff), message, args);
@@ -1701,15 +1701,15 @@ void vl_get_value(const VerilatedVar* varp, void* varDatap, p_vpi_value valuep,
                   const char* fullname) {
     if (!vl_check_format(varp, valuep, fullname, true)) return;
     // Maximum required size is for binary string, one byte per bit plus null termination
-    static VL_THREAD_LOCAL char t_outStr[VL_VALUE_STRING_MAX_WORDS * VL_EDATASIZE + 1];
+    static thread_local char t_outStr[VL_VALUE_STRING_MAX_WORDS * VL_EDATASIZE + 1];
     // cppcheck-suppress variableScope
-    static const VL_THREAD_LOCAL int t_outStrSz = sizeof(t_outStr) - 1;
+    static const thread_local int t_outStrSz = sizeof(t_outStr) - 1;
     // We used to presume vpiValue.format = vpiIntVal or if single bit vpiScalarVal
     // This may cause backward compatibility issues with older code.
     if (valuep->format == vpiVectorVal) {
         // Vector pointer must come from our memory pool
         // It only needs to persist until the next vpi_get_value
-        static VL_THREAD_LOCAL t_vpi_vecval t_out[VL_VALUE_STRING_MAX_WORDS * 2];
+        static thread_local t_vpi_vecval t_out[VL_VALUE_STRING_MAX_WORDS * 2];
         valuep->value.vector = t_out;
         if (varp->vltype() == VLVT_UINT8) {
             t_out[0].aval = *(reinterpret_cast<CData*>(varDatap));
diff --git a/include/verilatedos.h b/include/verilatedos.h
index de89e822e..41e74684a 100644
--- a/include/verilatedos.h
+++ b/include/verilatedos.h
@@ -56,7 +56,7 @@
 # if !defined(_WIN32) && !defined(__MINGW32__)
 #  define VL_ATTR_WEAK __attribute__((weak))
 # endif
-# if defined(__clang__) && defined(VL_THREADED)
+# if defined(__clang__)
 #  define VL_ACQUIRE(...) __attribute__((acquire_capability(__VA_ARGS__)))
 #  define VL_ACQUIRE_SHARED(...) __attribute__((acquire_shared_capability(__VA_ARGS__)))
 #  define VL_RELEASE(...) __attribute__((release_capability(__VA_ARGS__)))
@@ -139,47 +139,34 @@
 # define VL_PREFETCH_RW(p)  ///< Prefetch pointer argument with read/write intent
 #endif
 
-#if defined(VL_THREADED) && !defined(VL_CPPCHECK)
-# if defined(_MSC_VER) && _MSC_VER >= 1900
-#  define VL_THREAD_LOCAL thread_local
-# elif defined(__GNUC__)
-#  if (__cplusplus < 201103L)
-#   error "VL_THREADED/--threads support requires C++-11 or newer only; use newer compiler"
-#  endif
-# else
-#  error "Unsupported compiler for VL_THREADED: No thread-local declarator"
-# endif
-# define VL_THREAD_LOCAL thread_local  // "thread_local" when supported
-#else
-# define VL_THREAD_LOCAL  // "thread_local" when supported
-#endif
 
 #ifndef VL_NO_LEGACY
 # define VL_FUNC __func__  // Deprecated
 # define VL_THREAD  // Deprecated
+# define VL_THREAD_LOCAL thread_local  // Deprecated
 # define VL_STATIC_OR_THREAD static  // Deprecated
 #endif
 
 // Comment tag that Function is pure (and thus also VL_MT_SAFE)
 #define VL_PURE
-// Comment tag that function is threadsafe when VL_THREADED
+// Comment tag that function is threadsafe
 #if defined(__clang__)
 # define VL_MT_SAFE __attribute__((annotate("MT_SAFE")))
 #else
 # define VL_MT_SAFE
 #endif
-// Comment tag that function is threadsafe when VL_THREADED, only
+// Comment tag that function is threadsafe, only
 // during normal operation (post-init)
 #define VL_MT_SAFE_POSTINIT
 // Attribute that function is clang threadsafe and uses given mutex
 #define VL_MT_SAFE_EXCLUDES(mutex) VL_EXCLUDES(mutex)
-// Comment tag that function is not threadsafe when VL_THREADED
+// Comment tag that function is not threadsafe
 #if defined(__clang__)
 # define VL_MT_UNSAFE __attribute__((annotate("MT_UNSAFE")))
 #else
 # define VL_MT_UNSAFE
 #endif
-// Comment tag that function is not threadsafe when VL_THREADED,
+// Comment tag that function is not threadsafe
 // protected to make sure single-caller
 #define VL_MT_UNSAFE_ONE
 
@@ -482,28 +469,26 @@ using ssize_t = uint32_t;  ///< signed size_t; returned from read()
 //=========================================================================
 // Threading related OS-specific functions
 
-#if VL_THREADED
-# ifdef _WIN32
-#  define WIN32_LEAN_AND_MEAN
-#  define NOMINMAX
-#  include "Windows.h"
-#  define VL_CPU_RELAX() YieldProcessor()
-# elif defined(__i386__) || defined(__x86_64__) || defined(VL_CPPCHECK)
+#ifdef _WIN32
+# define WIN32_LEAN_AND_MEAN
+# define NOMINMAX
+# include "Windows.h"
+# define VL_CPU_RELAX() YieldProcessor()
+#elif defined(__i386__) || defined(__x86_64__) || defined(VL_CPPCHECK)
 // For more efficient busy waiting on SMT CPUs, let the processor know
 // we're just waiting so it can let another thread run
-#  define VL_CPU_RELAX() asm volatile("rep; nop" ::: "memory")
-# elif defined(__ia64__)
-#  define VL_CPU_RELAX() asm volatile("hint @pause" ::: "memory")
-# elif defined(__aarch64__)
-#  define VL_CPU_RELAX() asm volatile("yield" ::: "memory")
-# elif defined(__powerpc64__)
-#  define VL_CPU_RELAX() asm volatile("or 1, 1, 1; or 2, 2, 2;" ::: "memory")
-# elif defined(__loongarch__)
-// LoongArch does not currently have a yield/pause instruction
-#  define VL_CPU_RELAX() asm volatile("nop" ::: "memory")
-# else
-#  error "Missing VL_CPU_RELAX() definition. Or, don't use VL_THREADED"
-# endif
+# define VL_CPU_RELAX() asm volatile("rep; nop" ::: "memory")
+#elif defined(__ia64__)
+# define VL_CPU_RELAX() asm volatile("hint @pause" ::: "memory")
+#elif defined(__aarch64__)
+# define VL_CPU_RELAX() asm volatile("yield" ::: "memory")
+#elif defined(__powerpc64__)
+# define VL_CPU_RELAX() asm volatile("or 1, 1, 1; or 2, 2, 2;" ::: "memory")
+#elif defined(__loongarch__)
+/ LoongArch does not currently have a yield/pause instruction
+# define VL_CPU_RELAX() asm volatile("nop" ::: "memory")
+#else
+# error "Missing VL_CPU_RELAX() definition."
 #endif
 
 //=========================================================================
diff --git a/src/V3EmitCBase.cpp b/src/V3EmitCBase.cpp
index 40198fa76..c481f5bba 100644
--- a/src/V3EmitCBase.cpp
+++ b/src/V3EmitCBase.cpp
@@ -210,7 +210,7 @@ void EmitCBaseVisitor::emitVarDecl(const AstVar* nodep, bool asRef) {
             // Issue 2622.
             const bool beStatic = name.size() >= suffix.size()
                                   && name.substr(name.size() - suffix.size()) == suffix;
-            if (beStatic) puts("static VL_THREAD_LOCAL ");
+            if (beStatic) puts("static thread_local ");
         }
         puts(nodep->vlArgType(true, false, false, "", asRef));
         puts(";\n");
diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp
index cf7b17563..a2206af5e 100644
--- a/src/V3EmitCMake.cpp
+++ b/src/V3EmitCMake.cpp
@@ -116,7 +116,7 @@ class CMakeEmitter final {
         cmake_set_raw(*of, name + "_COVERAGE", v3Global.opt.coverage() ? "1" : "0");
         *of << "# Timing mode?  0/1\n";
         cmake_set_raw(*of, name + "_TIMING", v3Global.usesTiming() ? "1" : "0");
-        *of << "# Threaded output mode?  0/1/N threads (from --threads)\n";
+        *of << "# Threaded output mode?  1/N threads (from --threads)\n";
         cmake_set_raw(*of, name + "_THREADS", cvtToStr(v3Global.opt.threads()));
         *of << "# VCD Tracing output mode?  0/1 (from --trace)\n";
         cmake_set_raw(*of, name + "_TRACE_VCD",
diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp
index 163e408ba..f51f0fe34 100644
--- a/src/V3EmitMk.cpp
+++ b/src/V3EmitMk.cpp
@@ -63,10 +63,6 @@ public:
         of.puts("VM_PARALLEL_BUILDS = ");
         of.puts(v3Global.useParallelBuild() ? "1" : "0");
         of.puts("\n");
-        of.puts("# Threaded output mode?  0/1/N threads (from --threads)\n");
-        of.puts("VM_THREADS = ");
-        of.puts(cvtToStr(v3Global.opt.threads()));
-        of.puts("\n");
         of.puts("# Tracing output mode?  0/1 (from --trace/--trace-fst)\n");
         of.puts("VM_TRACE = ");
         of.puts(v3Global.opt.trace() ? "1" : "0");
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index f009a5f2d..287cdd93e 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -1388,10 +1388,17 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
     DECL_OPTION("-sv", CbCall, [this]() { m_defaultLanguage = V3LangCode::L1800_2017; });
 
     DECL_OPTION("-threads-coarsen", OnOff, &m_threadsCoarsen).undocumented();  // Debug
-    DECL_OPTION("-no-threads", CbCall, [this]() { m_threads = 0; });
+    DECL_OPTION("-no-threads", CbCall, [this, fl]() {
+        fl->v3warn(DEPRECATED, "Option --no-threads is deprecated, use '--threads 1' instead");
+        m_threads = 1;
+    });
     DECL_OPTION("-threads", CbVal, [this, fl](const char* valp) {
         m_threads = std::atoi(valp);
         if (m_threads < 0) fl->v3fatal("--threads must be >= 0: " << valp);
+        if (m_threads == 0) {
+            fl->v3warn(DEPRECATED, "Option --threads 0 is deprecated, use '--threads 1' instead");
+            m_threads = 1;
+        }
     });
     DECL_OPTION("-threads-dpi", CbVal, [this, fl](const char* valp) {
         if (!std::strcmp(valp, "all")) {
diff --git a/src/V3Options.h b/src/V3Options.h
index c2c3852fc..1dcb95edf 100644
--- a/src/V3Options.h
+++ b/src/V3Options.h
@@ -304,7 +304,7 @@ private:
     int         m_pinsBv = 65;       // main switch: --pins-bv
     int         m_reloopLimit = 40; // main switch: --reloop-limit
     VOptionBool m_skipIdentical;  // main switch: --skip-identical
-    int         m_threads = 0;      // main switch: --threads (0 == --no-threads)
+    int         m_threads = 1;      // main switch: --threads
     int         m_threadsMaxMTasks = 0;  // main switch: --threads-max-mtasks
     VTimescale  m_timeDefaultPrec;  // main switch: --timescale
     VTimescale  m_timeDefaultUnit;  // main switch: --timescale
diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 4bd739304..1f227d341 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -904,7 +904,7 @@ sub compile_vlt_flags {
                           @{$param{verilator_flags}},
                           @{$param{verilator_flags2}},
                           @{$param{verilator_flags3}});
-    die "%Error: specify threads via 'threads =>' argument, not as a command line option" unless ($checkflags !~ /(^|\s)-?-threads\s/ && $checkflags !~ /(^|\s)-?-no-threads($|\s)/);
+    die "%Error: specify threads via 'threads =>' argument, not as a command line option" unless ($checkflags !~ /(^|\s)-?-threads\s/);
     $self->{sc} = 1 if ($checkflags =~ /-sc\b/);
     $self->{trace} = ($opt_trace || $checkflags =~ /-trace\b/
                       || $checkflags =~ /-trace-fst\b/);
diff --git a/test_regress/t/t_embed1.pl b/test_regress/t/t_embed1.pl
index 2c5b8a918..85d36addd 100755
--- a/test_regress/t/t_embed1.pl
+++ b/test_regress/t/t_embed1.pl
@@ -23,7 +23,7 @@ mkdir $child_dir;
          top_filename => "$Self->{name}_child.v",
          verilator_flags => ["-cc", "-Mdir", "${child_dir}", "--debug-check"],
          # Can't use multi threading (like hier blocks), but needs to be thread safe
-         threads => $Self->{vltmt} ? 1 : 0,
+         threads => 1,
         );
 
     run(logfile => "${child_dir}/vlt_compile.log",
diff --git a/test_regress/t/t_flag_values_deprecated.out b/test_regress/t/t_flag_values_deprecated.out
new file mode 100644
index 000000000..5f5efc6a9
--- /dev/null
+++ b/test_regress/t/t_flag_values_deprecated.out
@@ -0,0 +1,5 @@
+%Warning-DEPRECATED: Option --threads 0 is deprecated, use '--threads 1' instead
+                     ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest
+                     ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message.
+%Error-DEPRECATED: Option --no-threads is deprecated, use '--threads 1' instead
+%Error: Exiting due to
diff --git a/test_regress/t/t_flag_values_deprecated.pl b/test_regress/t/t_flag_values_deprecated.pl
new file mode 100755
index 000000000..a4d6ad3c2
--- /dev/null
+++ b/test_regress/t/t_flag_values_deprecated.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    verilator_flags2 => ["-Werror-DEPRECATED", "--no-threads"],
+    fails => 1,
+    threads => 0,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gantt.pl b/test_regress/t/t_gantt.pl
index 1f92de577..e1c1c93c3 100755
--- a/test_regress/t/t_gantt.pl
+++ b/test_regress/t/t_gantt.pl
@@ -20,7 +20,7 @@ top_filename("t/t_gen_alw.v");
 compile(
     v_flags2 => ["--prof-exec"],
     # Checks below care about thread count, so use 2 (minimum reasonable)
-    threads => $Self->{vltmt} ? 2 : 0
+    threads => $Self->{vltmt} ? 2 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_gantt_two.cpp b/test_regress/t/t_gantt_two.cpp
index ecd0be219..5754c91fe 100644
--- a/test_regress/t/t_gantt_two.cpp
+++ b/test_regress/t/t_gantt_two.cpp
@@ -16,9 +16,8 @@ int main(int argc, char** argv, char** env) {
     srand48(5);
 
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
-#ifdef VL_THREADED
-    contextp->threads(2);
-#endif
+    // VL_USE_THREADS define is set in t_gantt_two.pl
+    contextp->threads(TEST_USE_THREADS);
     contextp->commandArgs(argc, argv);
     contextp->debug(0);
 
diff --git a/test_regress/t/t_gantt_two.pl b/test_regress/t/t_gantt_two.pl
index 768f55440..60d41117c 100755
--- a/test_regress/t/t_gantt_two.pl
+++ b/test_regress/t/t_gantt_two.pl
@@ -17,13 +17,15 @@ scenarios(vlt_all => 1);
 # enough for the profiling to happen:
 top_filename("t/t_gen_alw.v");
 
+my $threads_num = $Self->{vltmt} ? 2 : 1;
+
 compile(
     make_top_shell => 0,
     make_main => 0,
     v_flags2 => ["--prof-exec --exe $Self->{t_dir}/$Self->{name}.cpp"],
     # Checks below care about thread count, so use 2 (minimum reasonable)
-    threads => $Self->{vltmt} ? 2 : 0,
-    make_flags => 'CPPFLAGS_ADD=-DVL_NO_LEGACY',
+    threads => $threads_num,
+    make_flags => "CPPFLAGS_ADD=\"-DVL_NO_LEGACY -DTEST_USE_THREADS=$threads_num\"",
     );
 
 execute(
diff --git a/test_regress/t/t_hier_block.pl b/test_regress/t/t_hier_block.pl
index e861c733e..64e8f45ed 100755
--- a/test_regress/t/t_hier_block.pl
+++ b/test_regress/t/t_hier_block.pl
@@ -23,7 +23,7 @@ compile(
                          '--Wno-TIMESCALEMOD',
                          '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"'
     ],
-    threads => $Self->{vltmt} ? 6 : 0
+    threads => $Self->{vltmt} ? 6 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_hier_block_cmake.pl b/test_regress/t/t_hier_block_cmake.pl
index a4d74b89b..5c03ac6eb 100755
--- a/test_regress/t/t_hier_block_cmake.pl
+++ b/test_regress/t/t_hier_block_cmake.pl
@@ -13,17 +13,19 @@ clean_objs();
 scenarios(simulator => 1);
 top_filename("t/t_hier_block.v");
 
+my $threads = ($Self->{vltmt} ? '-DTEST_THREADS=6' : '-DTEST_THREADS=1');
+
 if (!$Self->have_cmake) {
     $Self->skip("Test requires CMake; ignore error since not available or version too old\n");
 } else {
     run(logfile => "$Self->{obj_dir}/cmake.log",
         cmd => ['cd "' . $Self->{obj_dir} . '" && cmake ' . $Self->{t_dir} . '/t_hier_block_cmake',
             "-DCMAKE_PREFIX_PATH=$ENV{VERILATOR_ROOT}",
-            ($Self->{vltmt} ? '-DTEST_THREADS=6' : '')
+            $threads
         ]);
 
     run(logfile => "$Self->{obj_dir}/build.log",
-        cmd => ['cd "' . $Self->{obj_dir} . '" && cmake --build', '.']
+        cmd => ['cd "' . $Self->{obj_dir} . '" && cmake --build', '.', '--', "CXX_FLAGS=$threads"]
     );
 
     run(logfile => "$Self->{obj_dir}/run.log",
diff --git a/test_regress/t/t_hier_block_cmake/main.cpp b/test_regress/t/t_hier_block_cmake/main.cpp
index 58bc8d5ad..beebaabff 100644
--- a/test_regress/t/t_hier_block_cmake/main.cpp
+++ b/test_regress/t/t_hier_block_cmake/main.cpp
@@ -14,9 +14,8 @@
 
 int main(int argc, char *argv[]) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
-#if VL_THREADED
-    contextp->threads(6);
-#endif
+    // TEST_THREADS is set in t_hier_block_cmake.pl
+    contextp->threads(TEST_THREADS);
     contextp->commandArgs(argc, argv);
     std::unique_ptr<Vt_hier_block> top{new Vt_hier_block{contextp.get(), "top"}};
     for (int i = 0; i < 100 && !contextp->gotFinish(); ++i) {
diff --git a/test_regress/t/t_hier_block_nohier.pl b/test_regress/t/t_hier_block_nohier.pl
index 8da19e163..97586ec08 100755
--- a/test_regress/t/t_hier_block_nohier.pl
+++ b/test_regress/t/t_hier_block_nohier.pl
@@ -24,7 +24,7 @@ compile(
     verilator_flags2 => ['--stats',
                          '+define+USE_VLT', 't/t_hier_block_vlt.vlt',
                          '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"'],
-    threads => $Self->{vltmt} ? 6 : 0
+    threads => $Self->{vltmt} ? 6 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_hier_block_sc.pl b/test_regress/t/t_hier_block_sc.pl
index 8aff1358d..b2264712f 100755
--- a/test_regress/t/t_hier_block_sc.pl
+++ b/test_regress/t/t_hier_block_sc.pl
@@ -24,7 +24,7 @@ compile(
                          '--hierarchical',
                          '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"'
     ],
-    threads => $Self->{vltmt} ? 6 : 0
+    threads => $Self->{vltmt} ? 6 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_hier_block_sc_trace_fst.pl b/test_regress/t/t_hier_block_sc_trace_fst.pl
index b2497ad14..331f3fe87 100755
--- a/test_regress/t/t_hier_block_sc_trace_fst.pl
+++ b/test_regress/t/t_hier_block_sc_trace_fst.pl
@@ -26,7 +26,7 @@ compile(
                          "--CFLAGS", '"-O0 -ggdb"',
                          "--trace-fst"
     ],
-    threads => $Self->{vltmt} ? 6 : 0
+    threads => $Self->{vltmt} ? 6 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.pl b/test_regress/t/t_hier_block_sc_trace_vcd.pl
index 7239369c7..5f27738e6 100755
--- a/test_regress/t/t_hier_block_sc_trace_vcd.pl
+++ b/test_regress/t/t_hier_block_sc_trace_vcd.pl
@@ -26,7 +26,7 @@ compile(
                          "--CFLAGS", '"-O0 -ggdb"',
                          "--trace"
     ],
-    threads => $Self->{vltmt} ? 6 : 0
+    threads => $Self->{vltmt} ? 6 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_hier_block_trace_fst.pl b/test_regress/t/t_hier_block_trace_fst.pl
index 753b9dda1..d05251cfd 100755
--- a/test_regress/t/t_hier_block_trace_fst.pl
+++ b/test_regress/t/t_hier_block_trace_fst.pl
@@ -22,7 +22,7 @@ compile(
                          '--trace-fst',
                          '--no-trace-underscore',  # To avoid handle mismatches
     ],
-    threads => $Self->{vltmt} ? 6 : 0
+    threads => $Self->{vltmt} ? 6 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_hier_block_trace_vcd.pl b/test_regress/t/t_hier_block_trace_vcd.pl
index 4f3b80f09..b53533adf 100755
--- a/test_regress/t/t_hier_block_trace_vcd.pl
+++ b/test_regress/t/t_hier_block_trace_vcd.pl
@@ -22,7 +22,7 @@ compile(
                          '--trace',
                          '--no-trace-underscore',  # To avoid handle mismatches
     ],
-    threads => $Self->{vltmt} ? 6 : 0
+    threads => $Self->{vltmt} ? 6 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_hier_block_vlt.pl b/test_regress/t/t_hier_block_vlt.pl
index ef467ede9..63e0d466d 100755
--- a/test_regress/t/t_hier_block_vlt.pl
+++ b/test_regress/t/t_hier_block_vlt.pl
@@ -23,7 +23,7 @@ compile(
                          '+define+SHOW_TIMESCALE',
                          '+define+USE_VLT', 't/t_hier_block_vlt.vlt',
                          '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"'],
-    threads => $Self->{vltmt} ? 6 : 0
+    threads => $Self->{vltmt} ? 6 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_inst_tree_inl0_pub1.pl b/test_regress/t/t_inst_tree_inl0_pub1.pl
index 107b1e56d..5979621aa 100755
--- a/test_regress/t/t_inst_tree_inl0_pub1.pl
+++ b/test_regress/t/t_inst_tree_inl0_pub1.pl
@@ -16,7 +16,7 @@ my $default_vltmt_threads = $Self->get_default_vltmt_threads();
 compile(
     verilator_flags2 => ['--stats', "$Self->{t_dir}/$Self->{name}.vlt"],
     # Force 3 threads even if we have fewer cores
-    threads => $Self->{vltmt} ? $default_vltmt_threads : 0
+    threads => $Self->{vltmt} ? $default_vltmt_threads : 1
     );
 
 sub checkRelativeRefs {
diff --git a/test_regress/t/t_lib_prot_shared.pl b/test_regress/t/t_lib_prot_shared.pl
index cd8b2a1c6..b7fab1e92 100755
--- a/test_regress/t/t_lib_prot_shared.pl
+++ b/test_regress/t/t_lib_prot_shared.pl
@@ -61,7 +61,7 @@ while (1) {
                              "-LDFLAGS",
                              "'-Wl,-rpath,$abs_secret_dir -L$abs_secret_dir -l$secret_prefix'"],
         xsim_flags2 => ["$secret_dir/secret.sv"],
-        threads => $Self->{vltmt} ? 1 : 0,
+        threads => 1,
         context_threads => $Self->{vltmt} ? 6 : 1
         );
 
diff --git a/test_regress/t/t_split_var_0.pl b/test_regress/t/t_split_var_0.pl
index 0441871e4..321950306 100755
--- a/test_regress/t/t_split_var_0.pl
+++ b/test_regress/t/t_split_var_0.pl
@@ -15,7 +15,7 @@ scenarios(simulator => 1);
 # So use 6 threads here though it's not optimal in performace wise, but ok.
 compile(
     verilator_flags2 => ['--stats', "$Self->{t_dir}/t_split_var_0.vlt"],
-    threads => $Self->{vltmt} ? 6 : 0
+    threads => $Self->{vltmt} ? 6 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_split_var_2_trace.pl b/test_regress/t/t_split_var_2_trace.pl
index 35d20007a..9395d8cc5 100755
--- a/test_regress/t/t_split_var_2_trace.pl
+++ b/test_regress/t/t_split_var_2_trace.pl
@@ -16,7 +16,7 @@ top_filename("t/t_split_var_0.v");
 # So use 6 threads here though it's not optimal in performace wise, but ok.
 compile(
     verilator_flags2 => ['--cc --trace --stats +define+TEST_ATTRIBUTES'],
-    threads => $Self->{vltmt} ? 6 : 0
+    threads => $Self->{vltmt} ? 6 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_threads_counter_0.pl b/test_regress/t/t_threads_counter_0.pl
index b93572929..6c3744eeb 100755
--- a/test_regress/t/t_threads_counter_0.pl
+++ b/test_regress/t/t_threads_counter_0.pl
@@ -14,7 +14,7 @@ top_filename("t/t_threads_counter.v");
 
 compile(
     verilator_flags2 => ['--cc'],
-    threads => 0,
+    threads => 1,
     );
 
 execute(
diff --git a/test_regress/t/t_threads_crazy_context.pl b/test_regress/t/t_threads_crazy_context.pl
index 8e28bb87a..6a3f1512e 100755
--- a/test_regress/t/t_threads_crazy_context.pl
+++ b/test_regress/t/t_threads_crazy_context.pl
@@ -18,7 +18,7 @@ top_filename("t/t_threads_crazy.v");
 
 compile(
     verilator_flags2 => ['--cc'],
-    threads => $Self->{vltmt} ? 2 : 0,
+    threads => $Self->{vltmt} ? 2 : 1,
     context_threads => 1024
     );
 
@@ -28,8 +28,6 @@ execute(
 
 if ($Self->{vltmt}) {
     file_grep($Self->{run_log_filename}, qr/System has \d+ hardware threads but simulation thread count set to 1024\. This will likely cause significant slowdown\./);
-} else {
-    file_grep($Self->{run_log_filename}, qr/Verilator run-time library built without VL_THREADS\. Ignoring call to 'VerilatedContext::threads' with argument 1024\./);
 }
 
 ok(1);
diff --git a/test_regress/t/t_timing_debug1.out b/test_regress/t/t_timing_debug1.out
index 792642e49..5775d0dde 100644
--- a/test_regress/t/t_timing_debug1.out
+++ b/test_regress/t/t_timing_debug1.out
@@ -32,6 +32,7 @@
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__stl
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__stl
 -V{t#,#}         No triggers active
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -61,8 +62,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -119,8 +122,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -156,8 +161,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -188,8 +195,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -238,8 +247,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -301,8 +312,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -342,8 +355,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -373,8 +388,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -428,8 +445,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -464,8 +483,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -495,8 +516,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -544,8 +567,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -580,8 +605,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -616,8 +643,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -647,8 +676,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -696,8 +727,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -732,8 +765,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -763,8 +798,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -834,8 +871,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -866,8 +905,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -902,8 +943,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -933,8 +976,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -988,8 +1033,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1024,8 +1071,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1055,8 +1104,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1090,8 +1141,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1139,8 +1192,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1175,8 +1230,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1206,8 +1263,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1255,8 +1314,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1291,8 +1352,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1356,8 +1419,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1387,8 +1452,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1442,8 +1509,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1478,8 +1547,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1509,8 +1580,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1558,8 +1631,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1598,8 +1673,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1629,8 +1706,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1678,8 +1757,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1714,8 +1795,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1745,8 +1828,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1794,8 +1879,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1855,8 +1942,10 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug1::eval_step
 -V{t#,#}+    Vt_timing_debug1___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval
 -V{t#,#}+    Vt_timing_debug1___024root___eval_triggers__act
@@ -1898,4 +1987,5 @@
 -V{t#,#}+    Vt_timing_debug1___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug1___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+    Vt_timing_debug1___024root___eval_final
diff --git a/test_regress/t/t_timing_debug2.out b/test_regress/t/t_timing_debug2.out
index 6243cc26c..bbb0b3fe2 100644
--- a/test_regress/t/t_timing_debug2.out
+++ b/test_regress/t/t_timing_debug2.out
@@ -60,6 +60,7 @@
 -V{t#,#}             Awaiting join of fork at: t/t_timing_class.v:209
 -V{t#,#}+      Vt_timing_debug2_t___eval_initial__TOP__t__7
 -V{t#,#}+    Vt_timing_debug2___024root___eval_settle
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -69,8 +70,10 @@
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
 -V{t#,#}         Committing processes waiting for @([event] t.ec.e):
 -V{t#,#}           - Process waiting at t/t_timing_class.v:80
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
 -V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -107,8 +110,10 @@
 -V{t#,#}+    Vt_timing_debug2___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
 -V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -174,8 +179,10 @@
 -V{t#,#}             Resuming: Process waiting at t/t_timing_class.v:29
 -V{t#,#}         Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:29
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
 -V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -230,8 +237,10 @@
 -V{t#,#}             Resuming: Process waiting at t/t_timing_class.v:29
 -V{t#,#}         Suspending process waiting for @([event] t::EventClass.e) at t/t_timing_class.v:29
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
 -V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -305,8 +314,10 @@
 -V{t#,#}+    Vt_timing_debug2___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
 -V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -344,8 +355,10 @@
 -V{t#,#}+    Vt_timing_debug2___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
 -V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -401,8 +414,10 @@
 -V{t#,#}+    Vt_timing_debug2___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
 -V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -459,10 +474,12 @@
 -V{t#,#}+    Vt_timing_debug2___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
 -V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
 -V{t#,#}+        Vt_timing_debug2_t__03a__03aForkDelayClass::~
 -V{t#,#}+        Vt_timing_debug2_t__03a__03aForkClass::~
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -490,8 +507,10 @@
 -V{t#,#}+    Vt_timing_debug2___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
 -V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -521,8 +540,10 @@
 -V{t#,#}+    Vt_timing_debug2___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
 -V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -549,8 +570,10 @@
 -V{t#,#}+    Vt_timing_debug2___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
 -V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -577,9 +600,11 @@
 -V{t#,#}+    Vt_timing_debug2___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_timing_debug2::eval_step
 -V{t#,#}+    Vt_timing_debug2___024root___eval_debug_assertions
 -V{t#,#}+        Vt_timing_debug2_t__03a__03aAssignDelayClass::~
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval
 -V{t#,#}+    Vt_timing_debug2___024root___eval_triggers__act
@@ -606,6 +631,7 @@
 -V{t#,#}+    Vt_timing_debug2___024root___dump_triggers__act
 -V{t#,#}         No triggers active
 -V{t#,#}+    Vt_timing_debug2___024root___timing_commit
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+    Vt_timing_debug2___024root___eval_final
 -V{t#,#}+        Vt_timing_debug2_t__03a__03aDelay40::~
 -V{t#,#}+        Vt_timing_debug2_t__03a__03aDelayClass::~
diff --git a/test_regress/t/t_trace_litendian.pl b/test_regress/t/t_trace_litendian.pl
index 5b7289295..3ecfa6bc6 100755
--- a/test_regress/t/t_trace_litendian.pl
+++ b/test_regress/t/t_trace_litendian.pl
@@ -15,7 +15,7 @@ scenarios(simulator => 1);
 # Strangely, asking for more threads makes it go away.
 compile(
     verilator_flags2 => ['--cc --trace --trace-params -Wno-LITENDIAN'],
-    threads => $Self->{vltmt} ? 6 : 0
+    threads => $Self->{vltmt} ? 6 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_trace_litendian_fst.pl b/test_regress/t/t_trace_litendian_fst.pl
index 3e24bf901..754bea6fd 100755
--- a/test_regress/t/t_trace_litendian_fst.pl
+++ b/test_regress/t/t_trace_litendian_fst.pl
@@ -17,7 +17,7 @@ top_filename("t/t_trace_litendian.v");
 # Strangely, asking for more threads makes it go away.
 compile(
     verilator_flags2 => ['--cc --trace-fst --trace-params -Wno-LITENDIAN'],
-    threads => $Self->{vltmt} ? 6 : 0
+    threads => $Self->{vltmt} ? 6 : 1
     );
 
 execute(
diff --git a/test_regress/t/t_trace_litendian_fst_sc.pl b/test_regress/t/t_trace_litendian_fst_sc.pl
index b79e1e78f..40366a231 100755
--- a/test_regress/t/t_trace_litendian_fst_sc.pl
+++ b/test_regress/t/t_trace_litendian_fst_sc.pl
@@ -21,7 +21,7 @@ else {
     # Strangely, asking for more threads makes it go away.
     compile(
         verilator_flags2 => ['--sc --trace-fst --trace-params -Wno-LITENDIAN'],
-        threads => $Self->{vltmt} ? 6 : 0
+        threads => $Self->{vltmt} ? 6 : 1
         );
 
     execute(
diff --git a/test_regress/t/t_verilated_debug.out b/test_regress/t/t_verilated_debug.out
index 4227ea526..55cf9f490 100644
--- a/test_regress/t/t_verilated_debug.out
+++ b/test_regress/t/t_verilated_debug.out
@@ -13,13 +13,16 @@ internalsDump:
 -V{t#,#}+    Vt_verilated_debug___024root___eval_initial__TOP
   Data: w96: 000000aa 000000bb 000000cc 
 -V{t#,#}+    Vt_verilated_debug___024root___eval_settle
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_verilated_debug___024root___eval
 -V{t#,#}+    Vt_verilated_debug___024root___eval_triggers__act
 -V{t#,#}+    Vt_verilated_debug___024root___dump_triggers__act
 -V{t#,#}         No triggers active
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+++++TOP Evaluate Vt_verilated_debug::eval_step
 -V{t#,#}+    Vt_verilated_debug___024root___eval_debug_assertions
+-V{t#,#}MTask0 starting
 -V{t#,#}+ Eval
 -V{t#,#}+    Vt_verilated_debug___024root___eval
 -V{t#,#}+    Vt_verilated_debug___024root___eval_triggers__act
@@ -35,4 +38,5 @@ internalsDump:
 -V{t#,#}+    Vt_verilated_debug___024root___eval_triggers__act
 -V{t#,#}+    Vt_verilated_debug___024root___dump_triggers__act
 -V{t#,#}         No triggers active
+-V{t#,#}End-of-eval cleanup
 -V{t#,#}+    Vt_verilated_debug___024root___eval_final
diff --git a/verilator-config.cmake.in b/verilator-config.cmake.in
index 2210b3297..8c19a2711 100644
--- a/verilator-config.cmake.in
+++ b/verilator-config.cmake.in
@@ -79,8 +79,8 @@ endif()
 
 define_property(TARGET
   PROPERTY VERILATOR_THREADED
-  BRIEF_DOCS "Verilator multithreading enabled"
-  FULL_DOCS "Verilator multithreading enabled"
+  BRIEF_DOCS "Deprecated and has no effect (ignored)"
+  FULL_DOCS "Deprecated and has no effect (ignored)"
 )
 
 define_property(TARGET
@@ -262,11 +262,6 @@ function(verilate TARGET)
                      "${VCMAKE}" "${VCMAKE_COPY}"
                      DEPENDS "${VCMAKE}" VERBATIM)
 
-  if (${VERILATE_PREFIX}_THREADS)
-    # If any verilate() call specifies THREADS, define VL_THREADED in the final build
-    set_property(TARGET ${TARGET} PROPERTY VERILATOR_THREADED ON)
-  endif()
-
   if (${VERILATE_PREFIX}_COVERAGE)
     # If any verilate() call specifies COVERAGE, define VM_COVERAGE in the final build
     set_property(TARGET ${TARGET} PROPERTY VERILATOR_COVERAGE ON)
@@ -326,7 +321,6 @@ function(verilate TARGET)
   target_compile_definitions(${TARGET} PRIVATE
     VM_COVERAGE=$<BOOL:$<TARGET_PROPERTY:VERILATOR_COVERAGE>>
     VM_SC=$<BOOL:$<TARGET_PROPERTY:VERILATOR_SYSTEMC>>
-    $<$<BOOL:$<TARGET_PROPERTY:VERILATOR_THREADED>>:VL_THREADED>
     VM_TRACE=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE>>
     VM_TRACE_VCD=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE_VCD>>
     VM_TRACE_FST=$<BOOL:$<TARGET_PROPERTY:VERILATOR_TRACE_FST>>
@@ -336,11 +330,9 @@ function(verilate TARGET)
     ${${VERILATE_PREFIX}_USER_LDLIBS}
   )
 
-  if (${VERILATE_PREFIX}_THREADS OR ${VERILATE_PREFIX}_TRACE_THREADS)
-    target_link_libraries(${TARGET} PUBLIC
-      ${VERILATOR_MT_CFLAGS}
-    )
-  endif()
+  target_link_libraries(${TARGET} PUBLIC
+    ${VERILATOR_MT_CFLAGS}
+  )
 
   target_compile_features(${TARGET} PRIVATE cxx_std_11)
 

From 167f4ebbd4a28b726a6189729f13fd8e7099e0dd Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 5 Nov 2022 09:32:41 -0400
Subject: [PATCH 007/156] Commentary: Changes update

---
 Changes | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Changes b/Changes
index ccadf7afb..ee0c002a2 100644
--- a/Changes
+++ b/Changes
@@ -13,6 +13,10 @@ Verilator 5.003 devel
 
 **Minor:**
 
+* Deprecate --no-threads; use --threads 1 for single threaded (#3703). [Kamil Rakoczy, Antmicro Ltd]
+* Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd]
+* Internal AST improvements, also affect XML format (#3721). [Geza Lore]
+* Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
 
 
 Verilator 5.002 2022-10-29

From 6ae6b16223ebaf03f3fef418ee1bd69fd758fe9c Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Sat, 5 Nov 2022 11:35:42 +0000
Subject: [PATCH 008/156] V3Const: Fix folding of LogAnd with non-bool operands

Folding an AstLogAnd with a non-zero constant operand used to coerce the
type of the other operand, yielding an ill-typed node that DFG was then
unhappy about. Add a RedOr instead if the width of the replacement
operand is greater than zero.

Fixes #3726
---
 src/V3Const.cpp              | 24 ++++++++++++++++++------
 test_regress/t/t_dfg_3726.pl | 16 ++++++++++++++++
 test_regress/t/t_dfg_3726.v  | 19 +++++++++++++++++++
 3 files changed, 53 insertions(+), 6 deletions(-)
 create mode 100755 test_regress/t/t_dfg_3726.pl
 create mode 100644 test_regress/t/t_dfg_3726.v

diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 3f75f93ae..08ad3272d 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -1646,6 +1646,16 @@ private:
         nodep->replaceWith(childp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
+    void replaceWChildBool(AstNode* nodep, AstNode* childp) {
+        // NODE(..., CHILD(...)) -> REDOR(CHILD(...))
+        childp->unlinkFrBack();
+        if (childp->width1()) {
+            nodep->replaceWith(childp);
+        } else {
+            nodep->replaceWith(new AstRedOr{childp->fileline(), childp});
+        }
+        VL_DO_DANGLING(nodep->deleteTree(), nodep);
+    }
 
     //! Replace a ternary node with its RHS after iterating
     //! Used with short-circuiting, where the RHS has not yet been iterated.
@@ -1672,6 +1682,8 @@ private:
         // Keep RHS, remove LHS
         replaceWChild(nodep, nodep->rhsp());
     }
+    void replaceWLhsBool(AstNodeBiop* nodep) { replaceWChildBool(nodep, nodep->lhsp()); }
+    void replaceWRhsBool(AstNodeBiop* nodep) { replaceWChildBool(nodep, nodep->rhsp()); }
     void replaceAsv(AstNodeBiop* nodep) {
         // BIASV(CONSTa, BIASV(CONSTb, c)) -> BIASV( BIASV_CONSTED(a,b), c)
         // BIASV(SAMEa,  BIASV(SAMEb, c))  -> BIASV( BIASV(SAMEa,SAMEb), c)
@@ -3282,7 +3294,7 @@ private:
     TREEOP ("AstLogAnd{$lhsp.isZero, $rhsp}",   "replaceZero(nodep)");
     // This visit function here must allow for short-circuiting.
     TREEOPS("AstLogOr   {$lhsp.isOne}",         "replaceNum(nodep, 1)");
-    TREEOP ("AstLogOr {$lhsp.isZero, $rhsp}",   "replaceWRhs(nodep)");
+    TREEOP ("AstLogOr {$lhsp.isZero, $rhsp}",   "replaceWRhsBool(nodep)");
     TREEOP ("AstDiv   {$lhsp.isZero, $rhsp}",   "replaceZeroChkPure(nodep,$rhsp)");
     TREEOP ("AstDivS  {$lhsp.isZero, $rhsp}",   "replaceZeroChkPure(nodep,$rhsp)");
     TREEOP ("AstMul   {$lhsp.isZero, $rhsp}",   "replaceZeroChkPure(nodep,$rhsp)");
@@ -3304,7 +3316,7 @@ private:
     TREEOP ("AstAdd   {$lhsp, $rhsp.isZero}",   "replaceWLhs(nodep)");
     TREEOP ("AstAnd   {$lhsp, $rhsp.isZero}",   "replaceZeroChkPure(nodep,$lhsp)");
     TREEOP ("AstLogAnd{$lhsp, $rhsp.isZero}",   "replaceZeroChkPure(nodep,$lhsp)");
-    TREEOP ("AstLogOr {$lhsp, $rhsp.isZero}",   "replaceWLhs(nodep)");
+    TREEOP ("AstLogOr {$lhsp, $rhsp.isZero}",   "replaceWLhsBool(nodep)");
     TREEOP ("AstMul   {$lhsp, $rhsp.isZero}",   "replaceZeroChkPure(nodep,$lhsp)");
     TREEOP ("AstMulS  {$lhsp, $rhsp.isZero}",   "replaceZeroChkPure(nodep,$lhsp)");
     TREEOP ("AstOr    {$lhsp, $rhsp.isZero}",   "replaceWLhs(nodep)");
@@ -3315,11 +3327,11 @@ private:
     TREEOP ("AstXor   {$lhsp, $rhsp.isZero}",   "replaceWLhs(nodep)");
     // Non-zero on one side or the other
     TREEOP ("AstAnd   {$lhsp.isAllOnes, $rhsp}",        "replaceWRhs(nodep)");
-    TREEOP ("AstLogAnd{$lhsp.isNeqZero, $rhsp}",        "replaceWRhs(nodep)");
+    TREEOP ("AstLogAnd{$lhsp.isNeqZero, $rhsp}",        "replaceWRhsBool(nodep)");
     TREEOP ("AstOr    {$lhsp.isAllOnes, $rhsp, isTPure($rhsp)}",        "replaceWLhs(nodep)");  // ->allOnes
     TREEOP ("AstLogOr {$lhsp.isNeqZero, $rhsp}",        "replaceNum(nodep,1)");
     TREEOP ("AstAnd   {$lhsp, $rhsp.isAllOnes}",        "replaceWLhs(nodep)");
-    TREEOP ("AstLogAnd{$lhsp, $rhsp.isNeqZero}",        "replaceWLhs(nodep)");
+    TREEOP ("AstLogAnd{$lhsp, $rhsp.isNeqZero}",        "replaceWLhsBool(nodep)");
     TREEOP ("AstOr    {$lhsp, $rhsp.isAllOnes, isTPure($lhsp)}",        "replaceWRhs(nodep)");  // ->allOnes
     TREEOP ("AstLogOr {$lhsp, $rhsp.isNeqZero, isTPure($lhsp), nodep->isPure()}",        "replaceNum(nodep,1)");
     TREEOP ("AstXor   {$lhsp.isAllOnes, $rhsp}",        "AstNot{$rhsp}");
@@ -3460,8 +3472,8 @@ private:
     TREEOP ("AstNeqN   {operandsSame($lhsp,,$rhsp)}",   "replaceZero(nodep)");
     TREEOP ("AstNeqCase{operandsSame($lhsp,,$rhsp)}",   "replaceZero(nodep)");
     TREEOP ("AstNeqWild{operandsSame($lhsp,,$rhsp)}",   "replaceZero(nodep)");
-    TREEOP ("AstLogAnd {operandsSame($lhsp,,$rhsp), $lhsp.width1}",     "replaceWLhs(nodep)");
-    TREEOP ("AstLogOr  {operandsSame($lhsp,,$rhsp), $lhsp.width1}",     "replaceWLhs(nodep)");
+    TREEOP ("AstLogAnd {operandsSame($lhsp,,$rhsp)}",   "replaceWLhsBool(nodep)");
+    TREEOP ("AstLogOr  {operandsSame($lhsp,,$rhsp)}",   "replaceWLhsBool(nodep)");
     ///=== Verilog operators
     // Comparison against 1'b0/1'b1; must be careful about widths.
     // These use Not, so must be Verilog only
diff --git a/test_regress/t/t_dfg_3726.pl b/test_regress/t/t_dfg_3726.pl
new file mode 100755
index 000000000..84ae125be
--- /dev/null
+++ b/test_regress/t/t_dfg_3726.pl
@@ -0,0 +1,16 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Geza Lore. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile();
+
+ok(1);
+1;
diff --git a/test_regress/t/t_dfg_3726.v b/test_regress/t/t_dfg_3726.v
new file mode 100644
index 000000000..8331d8b95
--- /dev/null
+++ b/test_regress/t/t_dfg_3726.v
@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Geza Lore.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/
+   // Outputs
+   x,
+   // Inputs
+   i
+   );
+
+   input i;
+   output x;
+
+   assign x = (i ? 0 : 1) && 1;
+
+endmodule

From 21926eeb6b853f680a999160b7bbd852fcfbf9a0 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 5 Nov 2022 11:40:34 -0400
Subject: [PATCH 009/156] Tests: Improve some coverage

---
 src/V3Config.cpp                              |  2 +-
 src/V3Options.cpp                             |  2 +-
 src/V3Width.cpp                               |  5 +-
 src/V3WidthSel.cpp                            |  2 +-
 test_regress/t/t_class_member_bad2.out        | 25 ++++++
 test_regress/t/t_class_member_bad2.pl         | 19 ++++
 test_regress/t/t_class_member_bad2.v          | 23 +++++
 test_regress/t/t_class_new_bad.out            | 13 ++-
 test_regress/t/t_class_new_bad.v              |  1 +
 test_regress/t/t_dist_warn_coverage.pl        | 31 ++-----
 test_regress/t/t_gen_missing_bad2.out         | 17 ++++
 test_regress/t/t_gen_missing_bad2.pl          | 19 ++++
 test_regress/t/t_gen_missing_bad2.v           | 15 ++++
 test_regress/t/t_gen_nonconst_bad.out         | 29 +++----
 test_regress/t/t_gen_nonconst_bad.pl          |  4 +
 test_regress/t/t_gen_nonconst_bad.v           | 10 +--
 .../t/t_lint_pragma_protected_bad.out         | 13 ++-
 test_regress/t/t_lint_pragma_protected_bad.v  |  5 ++
 test_regress/t/t_preproc_eof5_bad.out         |  4 +
 test_regress/t/t_preproc_eof5_bad.pl          | 19 ++++
 test_regress/t/t_preproc_eof5_bad.v           |  7 ++
 test_regress/t/t_savable_coverage_bad.out     |  2 +
 test_regress/t/t_savable_coverage_bad.pl      | 21 +++++
 test_regress/t/t_savable_coverage_bad.v       |  8 ++
 test_regress/t/t_select_bad_range4.out        | 87 +++++++++++++++++++
 test_regress/t/t_select_bad_range4.pl         | 19 ++++
 test_regress/t/t_select_bad_range4.v          | 27 ++++++
 test_regress/t/t_select_bad_range5.out        | 19 ++++
 test_regress/t/t_select_bad_range5.pl         | 19 ++++
 test_regress/t/t_select_bad_range5.v          | 17 ++++
 test_regress/t/t_sys_fscanf_bad.out           |  8 ++
 test_regress/t/t_sys_fscanf_bad.pl            | 19 ++++
 test_regress/t/t_sys_fscanf_bad.v             | 18 ++++
 33 files changed, 475 insertions(+), 54 deletions(-)
 create mode 100644 test_regress/t/t_class_member_bad2.out
 create mode 100755 test_regress/t/t_class_member_bad2.pl
 create mode 100644 test_regress/t/t_class_member_bad2.v
 create mode 100644 test_regress/t/t_gen_missing_bad2.out
 create mode 100755 test_regress/t/t_gen_missing_bad2.pl
 create mode 100644 test_regress/t/t_gen_missing_bad2.v
 create mode 100644 test_regress/t/t_preproc_eof5_bad.out
 create mode 100755 test_regress/t/t_preproc_eof5_bad.pl
 create mode 100644 test_regress/t/t_preproc_eof5_bad.v
 create mode 100644 test_regress/t/t_savable_coverage_bad.out
 create mode 100755 test_regress/t/t_savable_coverage_bad.pl
 create mode 100644 test_regress/t/t_savable_coverage_bad.v
 create mode 100644 test_regress/t/t_select_bad_range4.out
 create mode 100755 test_regress/t/t_select_bad_range4.pl
 create mode 100644 test_regress/t/t_select_bad_range4.v
 create mode 100644 test_regress/t/t_select_bad_range5.out
 create mode 100755 test_regress/t/t_select_bad_range5.pl
 create mode 100644 test_regress/t/t_select_bad_range5.v
 create mode 100644 test_regress/t/t_sys_fscanf_bad.out
 create mode 100755 test_regress/t/t_sys_fscanf_bad.pl
 create mode 100644 test_regress/t/t_sys_fscanf_bad.v

diff --git a/src/V3Config.cpp b/src/V3Config.cpp
index 73d1ed934..d71b7cc16 100644
--- a/src/V3Config.cpp
+++ b/src/V3Config.cpp
@@ -515,7 +515,7 @@ void V3Config::addInline(FileLine* fl, const string& module, const string& ftask
         V3ConfigResolver::s().modules().at(module).setInline(on);
     } else {
         if (!on) {
-            fl->v3error("no_inline not supported for tasks");
+            fl->v3error("Unsupported: no_inline for tasks");
         } else {
             V3ConfigResolver::s().modules().at(module).ftasks().at(ftask).setNoInline(on);
         }
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index 287cdd93e..bd1fa208b 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -835,7 +835,7 @@ void V3Options::notify() {
     }
 
     if (coverage() && savable()) {
-        cmdfl->v3error("--coverage and --savable not supported together");
+        cmdfl->v3error("Unsupported: --coverage and --savable not supported together");
     }
 
     // Mark options as available
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 8136142e2..06e8bfef5 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -802,7 +802,7 @@ private:
             // Don't need to iterate because V3Const already constified
             const int width = nodep->elementsConst();
             if (width > (1 << 28)) {
-                nodep->v3error("Width of bit range is huge; vector of over 1billion bits: 0x"
+                nodep->v3error("Width of bit range is huge; vector of over 1 billion bits: 0x"
                                << std::hex << width);
             }
             // Note width() not set on range; use elementsConst()
@@ -831,7 +831,8 @@ private:
             V3Const::constifyParamsEdit(nodep->widthp());  // widthp may change
             const AstConst* const widthConstp = VN_CAST(nodep->widthp(), Const);
             if (!widthConstp) {
-                nodep->v3error("Width of bit extract isn't a constant");
+                nodep->v3error(
+                    "Width of bit extract isn't a constant");  // Impossible? // LCOV_EXCL_LINE
                 nodep->dtypeSetBit();
                 return;
             }
diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp
index 174d01a36..4b02ad87d 100644
--- a/src/V3WidthSel.cpp
+++ b/src/V3WidthSel.cpp
@@ -499,7 +499,7 @@ private:
         warnTri(rhsp);
         const int width = VN_AS(widthp, Const)->toSInt();
         if (width > (1 << 28)) {
-            nodep->v3error("Width of :+ or :- is huge; vector of over 1billion bits: "
+            nodep->v3error("Width of :+ or :- is huge; vector of over 1 billion bits: "
                            << widthp->prettyName());
         }
         if (width < 0) nodep->v3error("Width of :+ or :- is < 0: " << widthp->prettyName());
diff --git a/test_regress/t/t_class_member_bad2.out b/test_regress/t/t_class_member_bad2.out
new file mode 100644
index 000000000..7bc20f324
--- /dev/null
+++ b/test_regress/t/t_class_member_bad2.out
@@ -0,0 +1,25 @@
+%Error: t/t_class_member_bad2.v:9:8: Duplicate declaration of signal: 'vardup'
+    9 |    int vardup;
+      |        ^~~~~~
+        t/t_class_member_bad2.v:8:8: ... Location of original declaration
+    8 |    int vardup;
+      |        ^~~~~~
+%Error: t/t_class_member_bad2.v:12:9: Duplicate declaration of task: 'memdup'
+   12 |    task memdup;
+      |         ^~~~~~
+        t/t_class_member_bad2.v:10:9: ... Location of original declaration
+   10 |    task memdup;
+      |         ^~~~~~
+%Error: t/t_class_member_bad2.v:17:18: Duplicate declaration of task: 'funcdup'
+   17 |    function void funcdup;
+      |                  ^~~~~~~
+        t/t_class_member_bad2.v:15:18: ... Location of original declaration
+   15 |    function void funcdup;
+      |                  ^~~~~~~
+%Error: t/t_class_member_bad2.v:12:9: Duplicate declaration of member name: 'memdup'
+   12 |    task memdup;
+      |         ^~~~~~
+%Error: t/t_class_member_bad2.v:17:18: Duplicate declaration of member name: 'funcdup'
+   17 |    function void funcdup;
+      |                  ^~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_class_member_bad2.pl b/test_regress/t/t_class_member_bad2.pl
new file mode 100755
index 000000000..7be596e0f
--- /dev/null
+++ b/test_regress/t/t_class_member_bad2.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_class_member_bad2.v b/test_regress/t/t_class_member_bad2.v
new file mode 100644
index 000000000..a8db650e9
--- /dev/null
+++ b/test_regress/t/t_class_member_bad2.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class ClsDup;
+   int vardup;
+   int vardup;
+   task memdup;
+   endtask
+   task memdup;
+   endtask
+
+   function void funcdup;
+   endfunction
+   function void funcdup;
+   endfunction
+
+endclass
+
+module t (/*AUTOARG*/);
+endmodule
diff --git a/test_regress/t/t_class_new_bad.out b/test_regress/t/t_class_new_bad.out
index d85240aab..425a7898e 100644
--- a/test_regress/t/t_class_new_bad.out
+++ b/test_regress/t/t_class_new_bad.out
@@ -10,4 +10,15 @@
                                  : ... In instance t
    33 |       c3 = new();   
       |            ^~~
-%Error: Exiting due to
+%Error: t/t_class_new_bad.v:34:12: dynamic new() not expected in this context (data type must be dynamic array)
+                                 : ... In instance t
+   34 |       c1 = new[2];
+      |            ^~~
+%Error: t/t_class_new_bad.v:34:10: Assign RHS expects a CLASSREFDTYPE 'ClsNoArg'
+                                 : ... In instance t
+   34 |       c1 = new[2];
+      |          ^
+%Error: Internal Error: t/t_class_new_bad.v:34:10: ../V3Width.cpp:#: Node has no type
+                                                 : ... In instance t
+   34 |       c1 = new[2];
+      |          ^
diff --git a/test_regress/t/t_class_new_bad.v b/test_regress/t/t_class_new_bad.v
index 5029ff0fd..f07c9e8f8 100644
--- a/test_regress/t/t_class_new_bad.v
+++ b/test_regress/t/t_class_new_bad.v
@@ -31,6 +31,7 @@ module t (/*AUTOARG*/);
       c1 = new(3);  // Bad, called with arg
       c2 = new(3);  // Bad, called with arg
       c3 = new();  // Bad, called without arg
+      c1 = new[2];
       $stop;
    end
 endmodule
diff --git a/test_regress/t/t_dist_warn_coverage.pl b/test_regress/t/t_dist_warn_coverage.pl
index 52cf64281..85ce9260f 100755
--- a/test_regress/t/t_dist_warn_coverage.pl
+++ b/test_regress/t/t_dist_warn_coverage.pl
@@ -21,14 +21,19 @@ my %Outputs;
 
 my %Suppressed;
 foreach my $s (
-    ' exited with ',  # driver.pl filters out
+    ' exited with ',  # Is hit; driver.pl filters out
     'EOF in unterminated string',  # Instead get normal unterminated
+    'Enum ranges must be integral, per spec',  # Hard to hit
+    'Return with return value isn\'t underneath a function',  # Hard to hit, get other bad return messages
+    'Select from non-array ',  # Instead get type does not have a bit range
+    'Syntax error parsing real: \'',  # Instead can't lex the number
+    'Unsupported: Ranges ignored in port-lists',  # Hard to hit
+    'dynamic new() not expected in this context (expected under an assign)',  # Instead get syntax error
     # Not yet analyzed
     ' is not an in/out/inout/param/interface: ',
     ' loading non-variable',
     '$fopen mode should be <= 4 characters',
     '\'foreach\' loop variable expects simple variable name',
-    '--coverage and --savable not supported together',
     '--pipe-filter protocol error, unexpected: ',
     '/*verilator sformat*/ can only be applied to last argument of ',
     'Argument needed for string.',
@@ -47,10 +52,7 @@ foreach my $s (
     'Circular logic when ordering code (non-cutable edge loop)',
     'Deferred assertions must use \'#0\' (IEEE 1800-2017 16.4)',
     'Define or directive not defined: `',
-    'Duplicate declaration of member name: ',
-    'EOF in (*',
     'Enum names without values only allowed on numeric types',
-    'Enum ranges must be integral, per spec',
     'Exceeded limit of ',
     'Extern declaration\'s scope is not a defined class',
     'Format to $display-like function must have constant format string',
@@ -73,8 +75,6 @@ foreach my $s (
     'Parameter type pin value isn\'t a type: Param ',
     'Parameter type variable isn\'t a type: Param ',
     'Pattern replication value of 0 is not legal.',
-    'Return with return value isn\'t underneath a function',
-    'Select from non-array ',
     'Signals inside functions/tasks cannot be marked forceable',
     'Size-changing cast to zero or negative size',
     'Slice size cannot be zero.',
@@ -82,9 +82,7 @@ foreach my $s (
     'String of ',
     'Symbol matching ',
     'Syntax Error: Range \':\', \'+:\' etc are not allowed in the instance ',
-    'Syntax error parsing real: \'',
     'Syntax error: \'virtual\' not allowed before var declaration',
-    'This may be because there\'s no search path specified with -I<dir>.',
     'Unexpected connection to arrayed port',
     'Unhandled attribute type',
     'Unknown Error Code: ',
@@ -101,8 +99,6 @@ foreach my $s (
     'Unsupported/unknown built-in dynamic array method ',
     'Unsupported: $bits for queue',
     'Unsupported: $c can\'t generate wider than 64 bits',
-    'Unsupported: %l in $fscanf',
-    'Unsupported: %m in $fscanf',
     'Unsupported: --no-structs-packed',
     'Unsupported: 4-state numbers in this context',
     'Unsupported: Concatenation to form ',
@@ -111,7 +107,6 @@ foreach my $s (
     'Unsupported: Per-bit array instantiations ',
     'Unsupported: Public functions with >64 bit outputs; ',
     'Unsupported: RHS of ==? or !=? must be ',
-    'Unsupported: Ranges ignored in port-lists',
     'Unsupported: Replication to form ',
     'Unsupported: Shifting of by over 32-bit number isn\'t supported.',
     'Unsupported: Signal strengths are unsupported ',
@@ -120,19 +115,10 @@ foreach my $s (
     'Unsupported: Unclocked assertion',
     'Unsupported: don\'t know how to deal with ',
     'Unsupported: event arrays',
-    'Unsupported: left < right of bit extract: ',
     'Unsupported: modport export',
+    'Unsupported: no_inline for tasks',
     'Unsupported: static cast to ',
     'Unsupported: super',
-    'Width of :+ or :- is < 0: ',
-    'Width of :+ or :- is huge; vector of over 1billion bits: ',
-    'Width of bit extract isn\'t a constant',
-    'Width of bit range is huge; vector of over 1billion bits: 0x',
-    'dynamic new() not expected in this context (data type must be dynamic array)',
-    'dynamic new() not expected in this context (expected under an assign)',
-    'line_length must be multiple of 4 for BASE64',
-    'new() not expected in this context',
-    'no_inline not supported for tasks',
     ) { $Suppressed{$s} = 1; }
 
 if (!-r "$root/.git") {
@@ -153,6 +139,7 @@ sub check {
     print "\n";
 
     print "Checking for v3error/v3warn messages in sources without coverage in test_regress/t/*.out:\n";
+    print "(Developers: If a message is impossible, use UASSERT or v3fatalSrc instead of v3error)";
     print "\n";
 
     my %used_suppressed;
diff --git a/test_regress/t/t_gen_missing_bad2.out b/test_regress/t/t_gen_missing_bad2.out
new file mode 100644
index 000000000..d7c378472
--- /dev/null
+++ b/test_regress/t/t_gen_missing_bad2.out
@@ -0,0 +1,17 @@
+%Error: t/t_gen_missing_bad2.v:8:8: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant.
+                                  : ... In instance t
+    8 |    if ($test$plusargs("BAD-non-constant")) begin
+      |        ^~~~~~~~~~~~~~
+%Error: t/t_gen_missing_bad2.v:8:8: Generate If condition must evaluate to constant
+                                  : ... In instance t
+    8 |    if ($test$plusargs("BAD-non-constant")) begin
+      |        ^~~~~~~~~~~~~~
+%Error: t/t_gen_missing_bad2.v:12:7: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant.
+                                   : ... In instance t
+   12 |       $test$plusargs("BAD-non-constant"): initial $stop;
+      |       ^~~~~~~~~~~~~~
+%Error: t/t_gen_missing_bad2.v:12:41: Generate Case item does not evaluate to constant
+                                    : ... In instance t
+   12 |       $test$plusargs("BAD-non-constant"): initial $stop;
+      |                                         ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_gen_missing_bad2.pl b/test_regress/t/t_gen_missing_bad2.pl
new file mode 100755
index 000000000..a5846c699
--- /dev/null
+++ b/test_regress/t/t_gen_missing_bad2.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gen_missing_bad2.v b/test_regress/t/t_gen_missing_bad2.v
new file mode 100644
index 000000000..d8714fb72
--- /dev/null
+++ b/test_regress/t/t_gen_missing_bad2.v
@@ -0,0 +1,15 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2012 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+   if ($test$plusargs("BAD-non-constant")) begin
+      initial $stop;
+   end
+   case (1)
+      $test$plusargs("BAD-non-constant"): initial $stop;
+   endcase
+
+endmodule
diff --git a/test_regress/t/t_gen_nonconst_bad.out b/test_regress/t/t_gen_nonconst_bad.out
index 9fb9ebcb3..2a014fe1d 100644
--- a/test_regress/t/t_gen_nonconst_bad.out
+++ b/test_regress/t/t_gen_nonconst_bad.out
@@ -1,17 +1,14 @@
-%Error: t/t_gen_nonconst_bad.v:8:8: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant.
-                                  : ... In instance t
-    8 |    if ($test$plusargs("BAD-non-constant")) begin
-      |        ^~~~~~~~~~~~~~
-%Error: t/t_gen_nonconst_bad.v:8:8: Generate If condition must evaluate to constant
-                                  : ... In instance t
-    8 |    if ($test$plusargs("BAD-non-constant")) begin
-      |        ^~~~~~~~~~~~~~
-%Error: t/t_gen_nonconst_bad.v:12:7: Expecting expression to be constant, but can't convert a TESTPLUSARGS to constant.
-                                   : ... In instance t
-   12 |       $test$plusargs("BAD-non-constant"): initial $stop;
-      |       ^~~~~~~~~~~~~~
-%Error: t/t_gen_nonconst_bad.v:12:41: Generate Case item does not evaluate to constant
-                                    : ... In instance t
-   12 |       $test$plusargs("BAD-non-constant"): initial $stop;
-      |                                         ^
+%Error: t/t_gen_nonconst_bad.v:8:4: Cannot find file containing module: 'nfound'
+    8 |    nfound nfound();
+      |    ^~~~~~
+%Error: t/t_gen_nonconst_bad.v:8:4: This may be because there's no search path specified with -I<dir>.
+    8 |    nfound nfound();
+      |    ^~~~~~
+        ... Looked in:
+             nfound
+             nfound.v
+             nfound.sv
+             obj_dir/nfound
+             obj_dir/nfound.v
+             obj_dir/nfound.sv
 %Error: Exiting due to
diff --git a/test_regress/t/t_gen_nonconst_bad.pl b/test_regress/t/t_gen_nonconst_bad.pl
index a5846c699..d9066a317 100755
--- a/test_regress/t/t_gen_nonconst_bad.pl
+++ b/test_regress/t/t_gen_nonconst_bad.pl
@@ -11,6 +11,10 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(vlt => 1);
 
 lint(
+    v_flags => [],  # To avoid -I
+    v_flags2 => [],  # To avoid -I
+    verilator_flags => ["--lint-only"],  # To avoid -I
+    verilator_flags2 => [],  # To avoid -I
     fails => 1,
     expect_filename => $Self->{golden_filename},
     );
diff --git a/test_regress/t/t_gen_nonconst_bad.v b/test_regress/t/t_gen_nonconst_bad.v
index d8714fb72..fc2aff4cf 100644
--- a/test_regress/t/t_gen_nonconst_bad.v
+++ b/test_regress/t/t_gen_nonconst_bad.v
@@ -1,15 +1,9 @@
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2012 by Wilson Snyder.
+// any use, without warranty, 2022 by Wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
 module t (/*AUTOARG*/);
-   if ($test$plusargs("BAD-non-constant")) begin
-      initial $stop;
-   end
-   case (1)
-      $test$plusargs("BAD-non-constant"): initial $stop;
-   endcase
-
+   nfound nfound();
 endmodule
diff --git a/test_regress/t/t_lint_pragma_protected_bad.out b/test_regress/t/t_lint_pragma_protected_bad.out
index bd33b755d..bb729a9e2 100644
--- a/test_regress/t/t_lint_pragma_protected_bad.out
+++ b/test_regress/t/t_lint_pragma_protected_bad.out
@@ -38,7 +38,16 @@
 %Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:63:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
 %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:64:1: BASE64 line too long in `pragma protect key_bloock/data_block
 %Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:64:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
-%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:72:1: `pragma is missing a pragma_expression.
-   72 | `pragma
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:66:17: multiple `pragma protected encoding sections
+   66 | `pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4)
+      |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:66:17: line_length must be multiple of 4 for BASE64
+   66 | `pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4)
+      |                 ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+%Warning-PROTECTED: t/t_lint_pragma_protected_bad.v:68:17: A '`pragma protected data_block' encrypted section was detected and will be skipped.
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:69:1: BASE64 line too long in `pragma protect key_bloock/data_block
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:69:1: BASE64 encoding length mismatch in `pragma protect key_bloock/data_block
+%Error-BADSTDPRAGMA: t/t_lint_pragma_protected_bad.v:77:1: `pragma is missing a pragma_expression.
+   77 | `pragma
       | ^~~~~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_lint_pragma_protected_bad.v b/test_regress/t/t_lint_pragma_protected_bad.v
index ca0099638..6d4f4e5e2 100644
--- a/test_regress/t/t_lint_pragma_protected_bad.v
+++ b/test_regress/t/t_lint_pragma_protected_bad.v
@@ -63,6 +63,11 @@ ZCBXb3JrIGFzIG==
 aW5pdGlvbnMuCgogIEFzIHVzZWQgaGVyZWluLCAidGhpcyBMaWNlbnNlIiByZWZlcnMgdG8gdmVyTOOLONG
 
 
+`pragma protect encoding = (enctype = "BASE64", line_length = 1, bytes = 4)
+`pragma protect data_block
+aW5p
+
+
 `pragma protect end_protected
 
 // Should trigger unknown pragma warning, although in principle unknown pragmas should be safely ignored.
diff --git a/test_regress/t/t_preproc_eof5_bad.out b/test_regress/t/t_preproc_eof5_bad.out
new file mode 100644
index 000000000..51a45069b
--- /dev/null
+++ b/test_regress/t/t_preproc_eof5_bad.out
@@ -0,0 +1,4 @@
+%Error: t/t_preproc_eof5_bad.v:7:1: EOF in (*
+    7 | (* attr
+      | ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_preproc_eof5_bad.pl b/test_regress/t/t_preproc_eof5_bad.pl
new file mode 100755
index 000000000..a60503a1f
--- /dev/null
+++ b/test_regress/t/t_preproc_eof5_bad.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_preproc_eof5_bad.v b/test_regress/t/t_preproc_eof5_bad.v
new file mode 100644
index 000000000..58bed87cd
--- /dev/null
+++ b/test_regress/t/t_preproc_eof5_bad.v
@@ -0,0 +1,7 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+(* attr
diff --git a/test_regress/t/t_savable_coverage_bad.out b/test_regress/t/t_savable_coverage_bad.out
new file mode 100644
index 000000000..a18ad8054
--- /dev/null
+++ b/test_regress/t/t_savable_coverage_bad.out
@@ -0,0 +1,2 @@
+%Error: Unsupported: --coverage and --savable not supported together
+%Error: Exiting due to
diff --git a/test_regress/t/t_savable_coverage_bad.pl b/test_regress/t/t_savable_coverage_bad.pl
new file mode 100755
index 000000000..cb1123397
--- /dev/null
+++ b/test_regress/t/t_savable_coverage_bad.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    v_flags2 => ["--savable --coverage"],
+    save_time => 500,
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_savable_coverage_bad.v b/test_regress/t/t_savable_coverage_bad.v
new file mode 100644
index 000000000..ec0ba931d
--- /dev/null
+++ b/test_regress/t/t_savable_coverage_bad.v
@@ -0,0 +1,8 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+endmodule
diff --git a/test_regress/t/t_select_bad_range4.out b/test_regress/t/t_select_bad_range4.out
new file mode 100644
index 000000000..edbedb1b0
--- /dev/null
+++ b/test_regress/t/t_select_bad_range4.out
@@ -0,0 +1,87 @@
+%Error: t/t_select_bad_range4.v:17:8: Width of bit range is huge; vector of over 1 billion bits: 0x20000001
+                                    : ... In instance t
+   17 |    reg [1<<29 : 0] hugerange;
+      |        ^
+%Error: t/t_select_bad_range4.v:20:16: Width of :+ or :- is < 0: 32'hffffffff
+                                     : ... In instance t
+   20 |       sel2 = mi[44 +: -1];
+      |                ^
+%Error-UNSUPPORTED: t/t_select_bad_range4.v:20:16: Unsupported: left < right of bit extract: 2<4
+                                                 : ... In instance t
+   20 |       sel2 = mi[44 +: -1];
+      |                ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Warning-WIDTH: t/t_select_bad_range4.v:20:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 3 bits.
+                                             : ... In instance t
+   20 |       sel2 = mi[44 +: -1];
+      |            ^
+                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
+%Error: t/t_select_bad_range4.v:21:16: Width of :+ or :- is huge; vector of over 1 billion bits: 32'h20000000
+                                     : ... In instance t
+   21 |       sel2 = mi[44 +: 1<<29];
+      |                ^
+%Warning-SELRANGE: t/t_select_bad_range4.v:21:16: Extracting 20000000 bits from only 6 bit number
+                                                : ... In instance t
+   21 |       sel2 = mi[44 +: 1<<29];
+      |                ^
+%Warning-SELRANGE: t/t_select_bad_range4.v:21:16: Selection index out of range: 20000003:4 outside 2d:28
+                                                : ... In instance t
+   21 |       sel2 = mi[44 +: 1<<29];
+      |                ^
+%Warning-WIDTH: t/t_select_bad_range4.v:21:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 20000000 bits.
+                                             : ... In instance t
+   21 |       sel2 = mi[44 +: 1<<29];
+      |            ^
+%Error: t/t_select_bad_range4.v:22:23: Expecting expression to be constant, but variable isn't const: 'nonconst'
+                                     : ... In instance t
+   22 |       sel2 = mi[44 +: nonconst];
+      |                       ^~~~~~~~
+%Error: t/t_select_bad_range4.v:22:23: Width of :+ or :- bit extract isn't a constant
+                                     : ... In instance t
+   22 |       sel2 = mi[44 +: nonconst];
+      |                       ^~~~~~~~
+%Warning-WIDTH: t/t_select_bad_range4.v:22:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
+                                             : ... In instance t
+   22 |       sel2 = mi[44 +: nonconst];
+      |            ^
+%Warning-WIDTH: t/t_select_bad_range4.v:23:17: Operator SUB expects 20 or 6 bits on the LHS, but LHS's VARREF 'nonconst' generates 1 bits.
+                                             : ... In instance t
+   23 |       sel2 = mi[nonconst];
+      |                 ^~~~~~~~
+%Warning-WIDTH: t/t_select_bad_range4.v:23:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
+                                             : ... In instance t
+   23 |       sel2 = mi[nonconst];
+      |            ^
+%Error: t/t_select_bad_range4.v:24:17: Expecting expression to be constant, but variable isn't const: 'nonconst'
+                                     : ... In instance t
+   24 |       sel2 = mi[nonconst : nonconst];
+      |                 ^~~~~~~~
+%Error: t/t_select_bad_range4.v:24:28: Expecting expression to be constant, but variable isn't const: 'nonconst'
+                                     : ... In instance t
+   24 |       sel2 = mi[nonconst : nonconst];
+      |                            ^~~~~~~~
+%Error: t/t_select_bad_range4.v:24:17: First value of [a:b] isn't a constant, maybe you want +: or -:
+                                     : ... In instance t
+   24 |       sel2 = mi[nonconst : nonconst];
+      |                 ^~~~~~~~
+%Error: t/t_select_bad_range4.v:24:28: Second value of [a:b] isn't a constant, maybe you want +: or -:
+                                     : ... In instance t
+   24 |       sel2 = mi[nonconst : nonconst];
+      |                            ^~~~~~~~
+%Warning-WIDTH: t/t_select_bad_range4.v:24:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 1 bits.
+                                             : ... In instance t
+   24 |       sel2 = mi[nonconst : nonconst];
+      |            ^
+%Warning-SELRANGE: t/t_select_bad_range4.v:25:16: Extracting 20000001 bits from only 6 bit number
+                                                : ... In instance t
+   25 |       sel2 = mi[1<<29 : 0];
+      |                ^
+%Warning-SELRANGE: t/t_select_bad_range4.v:25:16: Selection index out of range: 1fffffd8:ffffffd8 outside 2d:28
+                                                : ... In instance t
+   25 |       sel2 = mi[1<<29 : 0];
+      |                ^
+%Warning-WIDTH: t/t_select_bad_range4.v:25:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 20000001 bits.
+                                             : ... In instance t
+   25 |       sel2 = mi[1<<29 : 0];
+      |            ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_select_bad_range4.pl b/test_regress/t/t_select_bad_range4.pl
new file mode 100755
index 000000000..59ba0d6c6
--- /dev/null
+++ b/test_regress/t/t_select_bad_range4.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_select_bad_range4.v b/test_regress/t/t_select_bad_range4.v
new file mode 100644
index 000000000..e845c9b0d
--- /dev/null
+++ b/test_regress/t/t_select_bad_range4.v
@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk, unk, nonconst, mi
+   );
+   input clk;
+   input unk;
+   input nonconst;
+
+   input [45:40] mi;
+   reg [3:0]  sel2;
+   reg [1<<29 : 0] hugerange;
+
+   always @ (posedge clk) begin
+      sel2 = mi[44 +: -1];
+      sel2 = mi[44 +: 1<<29];
+      sel2 = mi[44 +: nonconst];
+      sel2 = mi[nonconst];
+      sel2 = mi[nonconst : nonconst];
+      sel2 = mi[1<<29 : 0];
+   end
+endmodule
diff --git a/test_regress/t/t_select_bad_range5.out b/test_regress/t/t_select_bad_range5.out
new file mode 100644
index 000000000..b97758309
--- /dev/null
+++ b/test_regress/t/t_select_bad_range5.out
@@ -0,0 +1,19 @@
+%Error: t/t_select_bad_range5.v:16:19: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic'
+                                     : ... In instance t
+   16 |    assign mi = unk[3:2];
+      |                   ^
+%Warning-SELRANGE: t/t_select_bad_range5.v:16:19: Extracting 2 bits from only 1 bit number
+                                                : ... In instance t
+   16 |    assign mi = unk[3:2];
+      |                   ^
+                   ... For warning description see https://verilator.org/warn/SELRANGE?v=latest
+                   ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message.
+%Warning-SELRANGE: t/t_select_bad_range5.v:16:19: Selection index out of range: 3:2 outside 1:0
+                                                : ... In instance t
+   16 |    assign mi = unk[3:2];
+      |                   ^
+%Warning-WIDTH: t/t_select_bad_range5.v:16:14: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's SEL generates 2 bits.
+                                             : ... In instance t
+   16 |    assign mi = unk[3:2];
+      |              ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_select_bad_range5.pl b/test_regress/t/t_select_bad_range5.pl
new file mode 100755
index 000000000..59ba0d6c6
--- /dev/null
+++ b/test_regress/t/t_select_bad_range5.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_select_bad_range5.v b/test_regress/t/t_select_bad_range5.v
new file mode 100644
index 000000000..77e6577e6
--- /dev/null
+++ b/test_regress/t/t_select_bad_range5.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk, unk, mi
+   );
+
+   input clk;
+   input unk;
+   output mi;
+
+   assign mi = unk[3:2];
+endmodule
diff --git a/test_regress/t/t_sys_fscanf_bad.out b/test_regress/t/t_sys_fscanf_bad.out
new file mode 100644
index 000000000..fb5b42426
--- /dev/null
+++ b/test_regress/t/t_sys_fscanf_bad.out
@@ -0,0 +1,8 @@
+%Error-UNSUPPORTED: t/t_sys_fscanf_bad.v:13:7: Unsupported: %l in $fscanf
+   13 |       $fscanf(file, "%l", i);   
+      |       ^~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_sys_fscanf_bad.v:14:7: Unsupported: %m in $fscanf
+   14 |       $fscanf(file, "%m", i);   
+      |       ^~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_sys_fscanf_bad.pl b/test_regress/t/t_sys_fscanf_bad.pl
new file mode 100755
index 000000000..a60503a1f
--- /dev/null
+++ b/test_regress/t/t_sys_fscanf_bad.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_sys_fscanf_bad.v b/test_regress/t/t_sys_fscanf_bad.v
new file mode 100644
index 000000000..ec1321f8a
--- /dev/null
+++ b/test_regress/t/t_sys_fscanf_bad.v
@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   integer file;
+   integer i;
+
+   initial begin
+      $fscanf(file, "%l", i);  // Bad
+      $fscanf(file, "%m", i);  // Bad
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

From fb9ec03c3fd1434b7be393897a18194f13fe1fad Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Fri, 4 Nov 2022 15:50:20 +0000
Subject: [PATCH 010/156] DfgPeephole: Use a work list driven algorithm for
 speed

Replace the 'run to fixed point' algorithm with a work list driven
approach. Instead of marking the graph as changed, we explicitly add
vertices to the work list, to be visited, when a vertex is changed. This
improves both memory locality (as the work list is processed in last in
first out order), and removed unnecessary visitations when only a few
nodes changes.
---
 src/V3Dfg.h                     |  16 ++
 src/V3DfgPeephole.cpp           | 392 +++++++++++++++++++-------------
 test_regress/t/t_dfg_peephole.v |   9 +-
 3 files changed, 251 insertions(+), 166 deletions(-)

diff --git a/src/V3Dfg.h b/src/V3Dfg.h
index f49110296..d8770d6ce 100644
--- a/src/V3Dfg.h
+++ b/src/V3Dfg.h
@@ -375,6 +375,22 @@ public:
         return *storagep;
     }
 
+    // Set user data, becomes current.
+    template <typename T>
+    typename std::enable_if<sizeof(T) <= sizeof(void*), void>::type setUser(T value) {
+        static_assert(sizeof(T) <= sizeof(UserDataStorage),
+                      "Size of user data type 'T' is too large for allocated storage");
+        static_assert(alignof(T) <= alignof(UserDataStorage),
+                      "Alignment of user data type 'T' is larger than allocated storage");
+        T* const storagep = reinterpret_cast<T*>(&m_userDataStorage);
+        const uint32_t userCurrent = m_graphp->m_userCurrent;
+#if VL_DEBUG
+        UASSERT_OBJ(userCurrent, this, "DfgVertex user data used without reserving");
+#endif
+        m_userCnt = userCurrent;
+        *storagep = value;
+    }
+
     // Width of result
     uint32_t width() const {
         // This is a hot enough function that this is an expensive check, so in debug build only.
diff --git a/src/V3DfgPeephole.cpp b/src/V3DfgPeephole.cpp
index bb0fe31b8..df78ea1d3 100644
--- a/src/V3DfgPeephole.cpp
+++ b/src/V3DfgPeephole.cpp
@@ -137,8 +137,14 @@ class V3DfgPeephole final : public DfgVisitor {
     // STATE
     DfgGraph& m_dfg;  // The DfgGraph being visited
     V3DfgPeepholeContext& m_ctx;  // The config structure
-    bool m_changed = false;  // Changed a vertex
+    //    bool m_changed = false;  // Changed a vertex
     AstNodeDType* const m_bitDType = DfgVertex::dtypeForWidth(1);  // Common, so grab it up front
+    // Head of work list. Note that we want all next pointers in the list to be non-zero (including
+    // that of the last element). This allows as to do two important things: detect if an element
+    // is in the list by checking for a non-zero next poitner, and easy prefetching without
+    // conditionals. The 'this' pointer is a good sentinel as it is a valid memory address, and we
+    // can easily check for the end of the list.
+    DfgVertex* m_workListp = reinterpret_cast<DfgVertex*>(this);
 
 #define APPLYING(id) if (checkApplying(VDfgPeepholePattern::id))
 
@@ -147,10 +153,56 @@ class V3DfgPeephole final : public DfgVisitor {
         if (!m_ctx.m_enabled[id]) return false;
         UINFO(9, "Applying DFG patten " << id.ascii() << endl);
         ++m_ctx.m_count[id];
-        m_changed = true;
+        //        m_changed = true;
         return true;
     }
 
+    void addToWorkList(DfgVertex* vtxp) {
+        // We only process actual operation vertices
+        if (vtxp->is<DfgConst>() || vtxp->is<DfgVertexVar>()) return;
+        // If already in work list then nothing to do
+        if (vtxp->getUser<DfgVertex*>()) return;
+        // Actually add to work list.
+        vtxp->setUser<DfgVertex*>(m_workListp);
+        m_workListp = vtxp;
+    }
+
+    void addSourcesToWorkList(DfgVertex* vtxp) {
+        vtxp->forEachSource([&](DfgVertex& src) { addToWorkList(&src); });
+    }
+
+    void addSinksToWorkList(DfgVertex* vtxp) {
+        vtxp->forEachSink([&](DfgVertex& src) { addToWorkList(&src); });
+    }
+
+    void deleteVertex(DfgVertex* vtxp) {
+        // Add all sources to the work list
+        addSourcesToWorkList(vtxp);
+        // If in work list then we can't delete it just yet (as we can't remove from the middle of
+        // the work list), but it will be deleted when the work list is processed.
+        if (vtxp->getUser<DfgVertex*>()) return;
+        // Otherwise we can delete it now.
+        VL_DO_DANGLING(vtxp->unlinkDelete(m_dfg), vtxp);
+    }
+
+    void replace(DfgVertex* vtxp, DfgVertex* replacementp) {
+        // Add sinks of replaced vertex to the work list
+        addSinksToWorkList(vtxp);
+        // Add replacement to the work list
+        addToWorkList(replacementp);
+        // Replace vertex with the replacement
+        vtxp->replaceWith(replacementp);
+        // Vertex is now unused, so delete it
+        deleteVertex(vtxp);
+    }
+
+    void modified(DfgVertex* vtxp) {
+        // Add sinks of modified vertex to the work list
+        addSinksToWorkList(vtxp);
+        // Add the modified vertex itself to the work list
+        addToWorkList(vtxp);
+    }
+
     // Shorthand
     static AstNodeDType* dtypeForWidth(uint32_t width) { return DfgVertex::dtypeForWidth(width); }
 
@@ -160,6 +212,21 @@ class V3DfgPeephole final : public DfgVisitor {
     // Create a DfgConst vertex with the given width and value zero
     DfgConst* makeZero(FileLine* flp, uint32_t width) { return new DfgConst{m_dfg, flp, width}; }
 
+    // Create a new vertex of the given type
+    template <typename Vertex, typename... Args>
+    Vertex* make(FileLine* flp, Args&&... args) {
+        static_assert(std::is_final<Vertex>::value, "Must invoke on final class");
+        static_assert(!std::is_same<DfgConst, Vertex>::value, "Use 'makeZero' instead");
+        static_assert(!std::is_base_of<DfgVertexVar, Vertex>::value, "Can't create variables");
+        // Create the new vertex
+        Vertex* const vtxp = new Vertex{m_dfg, flp, std::forward<Args>(args)...};
+        // Add to work list.
+        vtxp->template setUser<DfgVertex*>(m_workListp);
+        m_workListp = vtxp;
+        // Return new node
+        return vtxp;
+    }
+
     // Constant fold unary vertex, return true if folded
     template <typename Vertex>
     bool foldUnary(Vertex* vtxp) {
@@ -169,7 +236,7 @@ class V3DfgPeephole final : public DfgVisitor {
             APPLYING(FOLD_UNARY) {
                 DfgConst* const resultp = makeZero(vtxp->fileline(), vtxp->width());
                 foldOp<Vertex>(resultp->num(), srcp->num());
-                vtxp->replaceWith(resultp);
+                replace(vtxp, resultp);
                 return true;
             }
         }
@@ -186,7 +253,7 @@ class V3DfgPeephole final : public DfgVisitor {
                 APPLYING(FOLD_BINARY) {
                     DfgConst* const resultp = makeZero(vtxp->fileline(), vtxp->width());
                     foldOp<Vertex>(resultp->num(), lhsp->num(), rhsp->num());
-                    vtxp->replaceWith(resultp);
+                    replace(vtxp, resultp);
                     return true;
                 }
             }
@@ -231,7 +298,7 @@ class V3DfgPeephole final : public DfgVisitor {
             APPLYING(FOLD_ASSOC_BINARY) {
                 DfgConst* const resultp = makeZero(flp, vtxp->width());
                 foldOp<Vertex>(resultp->num(), lConstp->num(), rConstp->num());
-                vtxp->replaceWith(resultp);
+                replace(vtxp, resultp);
                 return true;
             }
         }
@@ -251,14 +318,15 @@ class V3DfgPeephole final : public DfgVisitor {
                         if (!rVtxp->hasMultipleSinks()) {
                             rVtxp->lhsp(constp);
                             rVtxp->dtypep(vtxp->dtypep());
-                            vtxp->replaceWith(rVtxp);
+                            replace(vtxp, rVtxp);
+                            return true;
                         } else {
-                            Vertex* const resp = new Vertex{m_dfg, flp, vtxp->dtypep()};
+                            Vertex* const resp = make<Vertex>(flp, vtxp->dtypep());
                             resp->lhsp(constp);
                             resp->rhsp(rVtxp->rhsp());
-                            vtxp->replaceWith(resp);
+                            replace(vtxp, resp);
+                            return true;
                         }
-                        return true;
                     }
                 }
             }
@@ -279,14 +347,15 @@ class V3DfgPeephole final : public DfgVisitor {
                         if (!lVtxp->hasMultipleSinks()) {
                             lVtxp->rhsp(constp);
                             lVtxp->dtypep(vtxp->dtypep());
-                            vtxp->replaceWith(lVtxp);
+                            replace(vtxp, lVtxp);
+                            return true;
                         } else {
-                            Vertex* const resp = new Vertex{m_dfg, flp, vtxp->dtypep()};
+                            Vertex* const resp = make<Vertex>(flp, vtxp->dtypep());
                             resp->lhsp(lVtxp->lhsp());
                             resp->rhsp(constp);
-                            vtxp->replaceWith(resp);
+                            replace(vtxp, resp);
+                            return true;
                         }
-                        return true;
                     }
                 }
             }
@@ -296,6 +365,7 @@ class V3DfgPeephole final : public DfgVisitor {
         while (vtxp->lhsp()->template is<Vertex>() && !vtxp->lhsp()->hasMultipleSinks()) {
             APPLYING(RIGHT_LEANING_ASSOC) {
                 rotateRight(vtxp);
+                modified(vtxp);
                 continue;
             }
             break;
@@ -314,6 +384,7 @@ class V3DfgPeephole final : public DfgVisitor {
             APPLYING(SWAP_CONST_IN_COMMUTATIVE_BINARY) {
                 vtxp->lhsp(rhsp);
                 vtxp->rhsp(lhsp);
+                modified(vtxp);
                 return;
             }
         }
@@ -323,6 +394,7 @@ class V3DfgPeephole final : public DfgVisitor {
             APPLYING(SWAP_NOT_IN_COMMUTATIVE_BINARY) {
                 vtxp->lhsp(rhsp);
                 vtxp->rhsp(lhsp);
+                modified(vtxp);
                 return;
             }
         }
@@ -335,6 +407,7 @@ class V3DfgPeephole final : public DfgVisitor {
                 APPLYING(SWAP_VAR_IN_COMMUTATIVE_BINARY) {
                     vtxp->lhsp(rhsp);
                     vtxp->rhsp(lhsp);
+                    modified(vtxp);
                     return;
                 }
             }
@@ -361,14 +434,14 @@ class V3DfgPeephole final : public DfgVisitor {
                 const uint32_t rWidth = rDtypep->width();
 
                 // The new Lhs vertex
-                Vertex* const newLhsp = new Vertex{m_dfg, flp, lDtypep};
+                Vertex* const newLhsp = make<Vertex>(flp, lDtypep);
                 DfgConst* const newLhsConstp = makeZero(constp->fileline(), lWidth);
                 newLhsConstp->num().opSel(constp->num(), width - 1, rWidth);
                 newLhsp->lhsp(newLhsConstp);
                 newLhsp->rhsp(concatp->lhsp());
 
                 // The new Rhs vertex
-                Vertex* const newRhsp = new Vertex{m_dfg, flp, rDtypep};
+                Vertex* const newRhsp = make<Vertex>(flp, rDtypep);
                 DfgConst* const newRhsConstp = makeZero(constp->fileline(), rWidth);
                 newRhsConstp->num().opSel(constp->num(), rWidth - 1, 0);
                 newRhsp->lhsp(newRhsConstp);
@@ -376,12 +449,12 @@ class V3DfgPeephole final : public DfgVisitor {
 
                 // The replacement Concat vertex
                 DfgConcat* const newConcat
-                    = new DfgConcat{m_dfg, concatp->fileline(), concatp->dtypep()};
+                    = make<DfgConcat>(concatp->fileline(), concatp->dtypep());
                 newConcat->lhsp(newLhsp);
                 newConcat->rhsp(newRhsp);
 
                 // Replace this vertex
-                vtxp->replaceWith(newConcat);
+                replace(vtxp, newConcat);
                 return true;
             }
         }
@@ -403,14 +476,14 @@ class V3DfgPeephole final : public DfgVisitor {
                 const uint32_t rWidth = concatp->rhsp()->width();
 
                 // The new Lhs vertex
-                Vertex* const newLhsp = new Vertex{m_dfg, flp, m_bitDType};
+                Vertex* const newLhsp = make<Vertex>(flp, m_bitDType);
                 DfgConst* const newLhsConstp = makeZero(constp->fileline(), lWidth);
                 newLhsConstp->num().opSel(constp->num(), width - 1, rWidth);
                 newLhsp->lhsp(newLhsConstp);
                 newLhsp->rhsp(concatp->lhsp());
 
                 // The new Rhs vertex
-                Vertex* const newRhsp = new Vertex{m_dfg, flp, m_bitDType};
+                Vertex* const newRhsp = make<Vertex>(flp, m_bitDType);
                 DfgConst* const newRhsConstp = makeZero(constp->fileline(), rWidth);
                 newRhsConstp->num().opSel(constp->num(), rWidth - 1, 0);
                 newRhsp->lhsp(newRhsConstp);
@@ -419,7 +492,7 @@ class V3DfgPeephole final : public DfgVisitor {
                 // The replacement Vertex
                 DfgVertexBinary* const replacementp
                     = std::is_same<Vertex, DfgEq>::value
-                          ? new DfgAnd{m_dfg, concatp->fileline(), m_bitDType}
+                          ? make<DfgAnd>(concatp->fileline(), m_bitDType)
                           : nullptr;
                 UASSERT_OBJ(replacementp, vtxp,
                             "Unhandled vertex type in 'tryPushCompareOpThroughConcat': "
@@ -428,7 +501,7 @@ class V3DfgPeephole final : public DfgVisitor {
                 replacementp->relinkSource<1>(newRhsp);
 
                 // Replace this vertex
-                vtxp->replaceWith(replacementp);
+                replace(vtxp, replacementp);
                 return true;
             }
         }
@@ -447,12 +520,12 @@ class V3DfgPeephole final : public DfgVisitor {
                     && !lSrcp->hasMultipleSinks() && !rSrcp->hasMultipleSinks()) {
                     APPLYING(PUSH_BITWISE_THROUGH_REDUCTION) {
                         FileLine* const flp = vtxp->fileline();
-                        Bitwise* const bwp = new Bitwise{m_dfg, flp, lSrcp->dtypep()};
+                        Bitwise* const bwp = make<Bitwise>(flp, lSrcp->dtypep());
                         bwp->lhsp(lSrcp);
                         bwp->rhsp(rSrcp);
-                        Reduction* const redp = new Reduction{m_dfg, flp, m_bitDType};
+                        Reduction* const redp = make<Reduction>(flp, m_bitDType);
                         redp->srcp(bwp);
-                        vtxp->replaceWith(redp);
+                        replace(vtxp, redp);
                         return true;
                     }
                 }
@@ -474,7 +547,7 @@ class V3DfgPeephole final : public DfgVisitor {
         // Reduction of 1-bit value
         if (srcp->dtypep() == m_bitDType) {
             APPLYING(REMOVE_WIDTH_ONE_REDUCTION) {
-                vtxp->replaceWith(srcp);
+                replace(vtxp, srcp);
                 return;
             }
         }
@@ -483,21 +556,21 @@ class V3DfgPeephole final : public DfgVisitor {
             if (condp->thenp()->is<DfgConst>() || condp->elsep()->is<DfgConst>()) {
                 APPLYING(PUSH_REDUCTION_THROUGH_COND_WITH_CONST_BRANCH) {
                     // The new 'then' vertex
-                    Reduction* const newThenp = new Reduction{m_dfg, flp, m_bitDType};
+                    Reduction* const newThenp = make<Reduction>(flp, m_bitDType);
                     newThenp->srcp(condp->thenp());
 
                     // The new 'else' vertex
-                    Reduction* const newElsep = new Reduction{m_dfg, flp, m_bitDType};
+                    Reduction* const newElsep = make<Reduction>(flp, m_bitDType);
                     newElsep->srcp(condp->elsep());
 
                     // The replacement Cond vertex
-                    DfgCond* const newCondp = new DfgCond{m_dfg, condp->fileline(), m_bitDType};
+                    DfgCond* const newCondp = make<DfgCond>(condp->fileline(), m_bitDType);
                     newCondp->condp(condp->condp());
                     newCondp->thenp(newThenp);
                     newCondp->elsep(newElsep);
 
                     // Replace this vertex
-                    vtxp->replaceWith(newCondp);
+                    replace(vtxp, newCondp);
                     return;
                 }
             }
@@ -507,21 +580,16 @@ class V3DfgPeephole final : public DfgVisitor {
             if (concatp->lhsp()->is<DfgConst>() || concatp->rhsp()->is<DfgConst>()) {
                 APPLYING(PUSH_REDUCTION_THROUGH_CONCAT) {
                     // Reduce the parts of the concatenation
-                    Reduction* const lRedp = new Reduction{m_dfg, concatp->fileline(), m_bitDType};
+                    Reduction* const lRedp = make<Reduction>(concatp->fileline(), m_bitDType);
                     lRedp->srcp(concatp->lhsp());
-                    Reduction* const rRedp = new Reduction{m_dfg, concatp->fileline(), m_bitDType};
+                    Reduction* const rRedp = make<Reduction>(concatp->fileline(), m_bitDType);
                     rRedp->srcp(concatp->rhsp());
 
                     // Bitwise reduce the results
-                    Bitwise* const replacementp = new Bitwise{m_dfg, flp, m_bitDType};
+                    Bitwise* const replacementp = make<Bitwise>(flp, m_bitDType);
                     replacementp->lhsp(lRedp);
                     replacementp->rhsp(rRedp);
-                    vtxp->replaceWith(replacementp);
-
-                    // Optimize the new terms
-                    optimizeReduction(lRedp);
-                    optimizeReduction(rRedp);
-                    iterate(replacementp);
+                    replace(vtxp, replacementp);
                     return;
                 }
             }
@@ -531,8 +599,9 @@ class V3DfgPeephole final : public DfgVisitor {
     void optimizeShiftRHS(DfgVertexBinary* vtxp) {
         if (const DfgConcat* const concatp = vtxp->rhsp()->cast<DfgConcat>()) {
             if (concatp->lhsp()->isZero()) {  // Drop redundant zero extension
-                APPLYING(REMOVE_REDUNDANT_ZEXT_ON_RHS_OF_SHIFT) {  //
+                APPLYING(REMOVE_REDUNDANT_ZEXT_ON_RHS_OF_SHIFT) {
                     vtxp->rhsp(concatp->rhsp());
+                    modified(vtxp);
                 }
             }
         }
@@ -564,10 +633,11 @@ class V3DfgPeephole final : public DfgVisitor {
         // Extend.
         APPLYING(REPLACE_EXTEND) {
             FileLine* const flp = vtxp->fileline();
-            DfgConcat* const replacementp = new DfgConcat{m_dfg, flp, vtxp->dtypep()};
+            DfgConcat* const replacementp = make<DfgConcat>(flp, vtxp->dtypep());
             replacementp->lhsp(makeZero(flp, vtxp->width() - vtxp->srcp()->width()));
             replacementp->rhsp(vtxp->srcp());
-            vtxp->replaceWith(replacementp);
+            replace(vtxp, replacementp);
+            return;
         }
     }
 
@@ -600,22 +670,21 @@ class V3DfgPeephole final : public DfgVisitor {
             if (condp->thenp()->is<DfgConst>() || condp->elsep()->is<DfgConst>()) {
                 APPLYING(PUSH_NOT_THROUGH_COND) {
                     // The new 'then' vertex
-                    DfgNot* const newThenp = new DfgNot{m_dfg, vtxp->fileline(), vtxp->dtypep()};
+                    DfgNot* const newThenp = make<DfgNot>(vtxp->fileline(), vtxp->dtypep());
                     newThenp->srcp(condp->thenp());
 
                     // The new 'else' vertex
-                    DfgNot* const newElsep = new DfgNot{m_dfg, vtxp->fileline(), vtxp->dtypep()};
+                    DfgNot* const newElsep = make<DfgNot>(vtxp->fileline(), vtxp->dtypep());
                     newElsep->srcp(condp->elsep());
 
                     // The replacement Cond vertex
-                    DfgCond* const newCondp
-                        = new DfgCond{m_dfg, condp->fileline(), vtxp->dtypep()};
+                    DfgCond* const newCondp = make<DfgCond>(condp->fileline(), vtxp->dtypep());
                     newCondp->condp(condp->condp());
                     newCondp->thenp(newThenp);
                     newCondp->elsep(newElsep);
 
                     // Replace this vertex
-                    vtxp->replaceWith(newCondp);
+                    replace(vtxp, newCondp);
                     return;
                 }
             }
@@ -625,7 +694,7 @@ class V3DfgPeephole final : public DfgVisitor {
         if (DfgNot* const notp = vtxp->srcp()->cast<DfgNot>()) {
             UASSERT_OBJ(vtxp->dtypep() == notp->srcp()->dtypep(), vtxp, "Width mismatch");
             APPLYING(REMOVE_NOT_NOT) {
-                vtxp->replaceWith(notp->srcp());
+                replace(vtxp, notp->srcp());
                 return;
             }
         }
@@ -634,11 +703,10 @@ class V3DfgPeephole final : public DfgVisitor {
             // Not of Eq
             if (DfgEq* const eqp = vtxp->srcp()->cast<DfgEq>()) {
                 APPLYING(REPLACE_NOT_EQ) {
-                    DfgNeq* const replacementp
-                        = new DfgNeq{m_dfg, eqp->fileline(), vtxp->dtypep()};
+                    DfgNeq* const replacementp = make<DfgNeq>(eqp->fileline(), vtxp->dtypep());
                     replacementp->lhsp(eqp->lhsp());
                     replacementp->rhsp(eqp->rhsp());
-                    vtxp->replaceWith(replacementp);
+                    replace(vtxp, replacementp);
                     return;
                 }
             }
@@ -646,10 +714,10 @@ class V3DfgPeephole final : public DfgVisitor {
             // Not of Neq
             if (DfgNeq* const neqp = vtxp->srcp()->cast<DfgNeq>()) {
                 APPLYING(REPLACE_NOT_NEQ) {
-                    DfgEq* const replacementp = new DfgEq{m_dfg, neqp->fileline(), vtxp->dtypep()};
+                    DfgEq* const replacementp = make<DfgEq>(neqp->fileline(), vtxp->dtypep());
                     replacementp->lhsp(neqp->lhsp());
                     replacementp->rhsp(neqp->rhsp());
-                    vtxp->replaceWith(replacementp);
+                    replace(vtxp, replacementp);
                     return;
                 }
             }
@@ -683,7 +751,7 @@ class V3DfgPeephole final : public DfgVisitor {
             APPLYING(FOLD_SEL) {
                 DfgConst* const replacementp = makeZero(flp, width);
                 replacementp->num().opSel(constp->num(), msb, lsb);
-                vtxp->replaceWith(replacementp);
+                replace(vtxp, replacementp);
                 return;
             }
         }
@@ -692,7 +760,7 @@ class V3DfgPeephole final : public DfgVisitor {
         if (fromp->width() == width) {
             UASSERT_OBJ(lsb == 0, fromp, "OOPS");
             APPLYING(REMOVE_FULL_WIDTH_SEL) {
-                vtxp->replaceWith(fromp);
+                replace(vtxp, fromp);
                 return;
             }
         }
@@ -706,12 +774,14 @@ class V3DfgPeephole final : public DfgVisitor {
                 // If the select is entirely from rhs, then replace with sel from rhs
                 APPLYING(REMOVE_SEL_FROM_RHS_OF_CONCAT) {  //
                     vtxp->fromp(rhsp);
+                    modified(vtxp);
                 }
             } else if (lsb >= rhsp->width()) {
                 // If the select is entirely from the lhs, then replace with sel from lhs
                 APPLYING(REMOVE_SEL_FROM_LHS_OF_CONCAT) {
                     vtxp->fromp(lhsp);
                     vtxp->lsb(lsb - rhsp->width());
+                    modified(vtxp);
                 }
             } else if (lsb == 0 || msb == concatp->width() - 1  //
                        || lhsp->is<DfgConst>() || rhsp->is<DfgConst>()  //
@@ -724,23 +794,23 @@ class V3DfgPeephole final : public DfgVisitor {
                     const uint32_t lSelWidth = width - rSelWidth;
 
                     // The new Lhs vertex
-                    DfgSel* const newLhsp = new DfgSel{m_dfg, flp, dtypeForWidth(lSelWidth)};
+                    DfgSel* const newLhsp = make<DfgSel>(flp, dtypeForWidth(lSelWidth));
                     newLhsp->fromp(lhsp);
                     newLhsp->lsb(0);
 
                     // The new Rhs vertex
-                    DfgSel* const newRhsp = new DfgSel{m_dfg, flp, dtypeForWidth(rSelWidth)};
+                    DfgSel* const newRhsp = make<DfgSel>(flp, dtypeForWidth(rSelWidth));
                     newRhsp->fromp(rhsp);
                     newRhsp->lsb(lsb);
 
                     // The replacement Concat vertex
                     DfgConcat* const newConcat
-                        = new DfgConcat{m_dfg, concatp->fileline(), vtxp->dtypep()};
+                        = make<DfgConcat>(concatp->fileline(), vtxp->dtypep());
                     newConcat->lhsp(newLhsp);
                     newConcat->rhsp(newRhsp);
 
                     // Replace this vertex
-                    vtxp->replaceWith(newConcat);
+                    replace(vtxp, newConcat);
                     return;
                 }
             }
@@ -756,6 +826,7 @@ class V3DfgPeephole final : public DfgVisitor {
                     APPLYING(PUSH_SEL_THROUGH_REPLICATE) {
                         vtxp->fromp(repp->srcp());
                         vtxp->lsb(newLsb);
+                        modified(vtxp);
                     }
                 }
             }
@@ -770,10 +841,10 @@ class V3DfgPeephole final : public DfgVisitor {
                     // Make Sel select from source of Not
                     vtxp->fromp(notp->srcp());
                     // Add Not after Sel
-                    DfgNot* const replacementp
-                        = new DfgNot{m_dfg, notp->fileline(), vtxp->dtypep()};
+                    DfgNot* const replacementp = make<DfgNot>(notp->fileline(), vtxp->dtypep());
                     vtxp->replaceWith(replacementp);
                     replacementp->srcp(vtxp);
+                    modified(vtxp);
                 }
             }
         }
@@ -785,6 +856,7 @@ class V3DfgPeephole final : public DfgVisitor {
                 vtxp->fromp(selp->fromp());
                 // Adjust LSB
                 vtxp->lsb(lsb + selp->lsb());
+                modified(vtxp);
             }
         }
 
@@ -794,24 +866,23 @@ class V3DfgPeephole final : public DfgVisitor {
             if (condp->thenp()->is<DfgConst>() || condp->elsep()->is<DfgConst>()) {
                 APPLYING(PUSH_SEL_THROUGH_COND) {
                     // The new 'then' vertex
-                    DfgSel* const newThenp = new DfgSel{m_dfg, flp, vtxp->dtypep()};
+                    DfgSel* const newThenp = make<DfgSel>(flp, vtxp->dtypep());
                     newThenp->fromp(condp->thenp());
                     newThenp->lsb(lsb);
 
                     // The new 'else' vertex
-                    DfgSel* const newElsep = new DfgSel{m_dfg, flp, vtxp->dtypep()};
+                    DfgSel* const newElsep = make<DfgSel>(flp, vtxp->dtypep());
                     newElsep->fromp(condp->elsep());
                     newElsep->lsb(lsb);
 
                     // The replacement Cond vertex
-                    DfgCond* const newCondp
-                        = new DfgCond{m_dfg, condp->fileline(), vtxp->dtypep()};
+                    DfgCond* const newCondp = make<DfgCond>(condp->fileline(), vtxp->dtypep());
                     newCondp->condp(condp->condp());
                     newCondp->thenp(newThenp);
                     newCondp->elsep(newElsep);
 
                     // Replace this vertex
-                    vtxp->replaceWith(newCondp);
+                    replace(vtxp, newCondp);
                     return;
                 }
             }
@@ -825,10 +896,11 @@ class V3DfgPeephole final : public DfgVisitor {
                 APPLYING(PUSH_SEL_THROUGH_SHIFTL) {
                     vtxp->fromp(shiftLp->lhsp());
                     DfgShiftL* const newShiftLp
-                        = new DfgShiftL{m_dfg, shiftLp->fileline(), vtxp->dtypep()};
+                        = make<DfgShiftL>(shiftLp->fileline(), vtxp->dtypep());
                     vtxp->replaceWith(newShiftLp);
                     newShiftLp->lhsp(vtxp);
                     newShiftLp->rhsp(shiftLp->rhsp());
+                    modified(vtxp);
                 }
             }
         }
@@ -855,26 +927,26 @@ class V3DfgPeephole final : public DfgVisitor {
             if (DfgNot* const lhsNotp = lhsp->cast<DfgNot>()) {
                 if (DfgNot* const rhsNotp = rhsp->cast<DfgNot>()) {
                     APPLYING(REPLACE_AND_OF_NOT_AND_NOT) {
-                        DfgOr* const orp = new DfgOr{m_dfg, flp, vtxp->dtypep()};
+                        DfgOr* const orp = make<DfgOr>(flp, vtxp->dtypep());
                         orp->lhsp(lhsNotp->srcp());
                         orp->rhsp(rhsNotp->srcp());
-                        DfgNot* const notp = new DfgNot{m_dfg, flp, vtxp->dtypep()};
+                        DfgNot* const notp = make<DfgNot>(flp, vtxp->dtypep());
                         notp->srcp(orp);
-                        vtxp->replaceWith(notp);
+                        replace(vtxp, notp);
                         return;
                     }
                 }
                 if (DfgNeq* const rhsNeqp = rhsp->cast<DfgNeq>()) {
                     APPLYING(REPLACE_AND_OF_NOT_AND_NEQ) {
-                        DfgOr* const orp = new DfgOr{m_dfg, flp, vtxp->dtypep()};
+                        DfgOr* const orp = make<DfgOr>(flp, vtxp->dtypep());
                         orp->lhsp(lhsNotp->srcp());
-                        DfgEq* const newRhsp = new DfgEq{m_dfg, rhsp->fileline(), rhsp->dtypep()};
+                        DfgEq* const newRhsp = make<DfgEq>(rhsp->fileline(), rhsp->dtypep());
                         newRhsp->lhsp(rhsNeqp->lhsp());
                         newRhsp->rhsp(rhsNeqp->rhsp());
                         orp->rhsp(newRhsp);
-                        DfgNot* const notp = new DfgNot{m_dfg, flp, vtxp->dtypep()};
+                        DfgNot* const notp = make<DfgNot>(flp, vtxp->dtypep());
                         notp->srcp(orp);
-                        vtxp->replaceWith(notp);
+                        replace(vtxp, notp);
                         return;
                     }
                 }
@@ -884,14 +956,14 @@ class V3DfgPeephole final : public DfgVisitor {
         if (DfgConst* const lhsConstp = lhsp->cast<DfgConst>()) {
             if (lhsConstp->isZero()) {
                 APPLYING(REPLACE_AND_WITH_ZERO) {
-                    vtxp->replaceWith(lhsConstp);
+                    replace(vtxp, lhsConstp);
                     return;
                 }
             }
 
             if (lhsConstp->isOnes()) {
                 APPLYING(REMOVE_AND_WITH_ONES) {
-                    vtxp->replaceWith(rhsp);
+                    replace(vtxp, rhsp);
                     return;
                 }
             }
@@ -908,7 +980,7 @@ class V3DfgPeephole final : public DfgVisitor {
             if (lhsNotp->srcp() == rhsp) {
                 APPLYING(REPLACE_CONTRADICTORY_AND) {
                     DfgConst* const replacementp = makeZero(flp, vtxp->width());
-                    vtxp->replaceWith(replacementp);
+                    replace(vtxp, replacementp);
                     return;
                 }
             }
@@ -932,26 +1004,26 @@ class V3DfgPeephole final : public DfgVisitor {
             if (DfgNot* const lhsNotp = lhsp->cast<DfgNot>()) {
                 if (DfgNot* const rhsNotp = rhsp->cast<DfgNot>()) {
                     APPLYING(REPLACE_OR_OF_NOT_AND_NOT) {
-                        DfgAnd* const andp = new DfgAnd{m_dfg, flp, vtxp->dtypep()};
+                        DfgAnd* const andp = make<DfgAnd>(flp, vtxp->dtypep());
                         andp->lhsp(lhsNotp->srcp());
                         andp->rhsp(rhsNotp->srcp());
-                        DfgNot* const notp = new DfgNot{m_dfg, flp, vtxp->dtypep()};
+                        DfgNot* const notp = make<DfgNot>(flp, vtxp->dtypep());
                         notp->srcp(andp);
-                        vtxp->replaceWith(notp);
+                        replace(vtxp, notp);
                         return;
                     }
                 }
                 if (DfgNeq* const rhsNeqp = rhsp->cast<DfgNeq>()) {
                     APPLYING(REPLACE_OR_OF_NOT_AND_NEQ) {
-                        DfgAnd* const andp = new DfgAnd{m_dfg, flp, vtxp->dtypep()};
+                        DfgAnd* const andp = make<DfgAnd>(flp, vtxp->dtypep());
                         andp->lhsp(lhsNotp->srcp());
-                        DfgEq* const newRhsp = new DfgEq{m_dfg, rhsp->fileline(), rhsp->dtypep()};
+                        DfgEq* const newRhsp = make<DfgEq>(rhsp->fileline(), rhsp->dtypep());
                         newRhsp->lhsp(rhsNeqp->lhsp());
                         newRhsp->rhsp(rhsNeqp->rhsp());
                         andp->rhsp(newRhsp);
-                        DfgNot* const notp = new DfgNot{m_dfg, flp, vtxp->dtypep()};
+                        DfgNot* const notp = make<DfgNot>(flp, vtxp->dtypep());
                         notp->srcp(andp);
-                        vtxp->replaceWith(notp);
+                        replace(vtxp, notp);
                         return;
                     }
                 }
@@ -963,21 +1035,19 @@ class V3DfgPeephole final : public DfgVisitor {
                 if (lhsConcatp->lhsp()->dtypep() == rhsConcatp->lhsp()->dtypep()) {
                     if (lhsConcatp->lhsp()->isZero() && rhsConcatp->rhsp()->isZero()) {
                         APPLYING(REPLACE_OR_OF_CONCAT_ZERO_LHS_AND_CONCAT_RHS_ZERO) {
-                            DfgConcat* const replacementp
-                                = new DfgConcat{m_dfg, flp, vtxp->dtypep()};
+                            DfgConcat* const replacementp = make<DfgConcat>(flp, vtxp->dtypep());
                             replacementp->lhsp(rhsConcatp->lhsp());
                             replacementp->rhsp(lhsConcatp->rhsp());
-                            vtxp->replaceWith(replacementp);
+                            replace(vtxp, replacementp);
                             return;
                         }
                     }
                     if (lhsConcatp->rhsp()->isZero() && rhsConcatp->lhsp()->isZero()) {
                         APPLYING(REPLACE_OR_OF_CONCAT_LHS_ZERO_AND_CONCAT_ZERO_RHS) {
-                            DfgConcat* const replacementp
-                                = new DfgConcat{m_dfg, flp, vtxp->dtypep()};
+                            DfgConcat* const replacementp = make<DfgConcat>(flp, vtxp->dtypep());
                             replacementp->lhsp(lhsConcatp->lhsp());
                             replacementp->rhsp(rhsConcatp->rhsp());
-                            vtxp->replaceWith(replacementp);
+                            replace(vtxp, replacementp);
                             return;
                         }
                     }
@@ -988,14 +1058,14 @@ class V3DfgPeephole final : public DfgVisitor {
         if (DfgConst* const lhsConstp = lhsp->cast<DfgConst>()) {
             if (lhsConstp->isZero()) {
                 APPLYING(REMOVE_OR_WITH_ZERO) {
-                    vtxp->replaceWith(rhsp);
+                    replace(vtxp, rhsp);
                     return;
                 }
             }
 
             if (lhsConstp->isOnes()) {
                 APPLYING(REPLACE_OR_WITH_ONES) {
-                    vtxp->replaceWith(lhsp);
+                    replace(vtxp, lhsp);
                     return;
                 }
             }
@@ -1013,7 +1083,7 @@ class V3DfgPeephole final : public DfgVisitor {
                 APPLYING(REPLACE_TAUTOLOGICAL_OR) {
                     DfgConst* const replacementp = makeZero(flp, vtxp->width());
                     replacementp->num().setAllBits1();
-                    vtxp->replaceWith(replacementp);
+                    replace(vtxp, replacementp);
                     return;
                 }
             }
@@ -1035,15 +1105,15 @@ class V3DfgPeephole final : public DfgVisitor {
         if (DfgConst* const lConstp = lhsp->cast<DfgConst>()) {
             if (lConstp->isZero()) {
                 APPLYING(REMOVE_XOR_WITH_ZERO) {
-                    vtxp->replaceWith(rhsp);
+                    replace(vtxp, rhsp);
                     return;
                 }
             }
             if (lConstp->isOnes()) {
                 APPLYING(REPLACE_XOR_WITH_ONES) {
-                    DfgNot* const replacementp = new DfgNot{m_dfg, flp, vtxp->dtypep()};
+                    DfgNot* const replacementp = make<DfgNot>(flp, vtxp->dtypep());
                     replacementp->srcp(rhsp);
-                    vtxp->replaceWith(replacementp);
+                    replace(vtxp, replacementp);
                     return;
                 }
             }
@@ -1075,7 +1145,7 @@ class V3DfgPeephole final : public DfgVisitor {
                 const size_t idx = idxp->toSizeT();
                 if (DfgVertex* const driverp = varp->driverAt(idx)) {
                     APPLYING(INLINE_ARRAYSEL) {
-                        vtxp->replaceWith(driverp);
+                        replace(vtxp, driverp);
                         return;
                     }
                 }
@@ -1100,10 +1170,10 @@ class V3DfgPeephole final : public DfgVisitor {
                 if (vtxp->dtypep() == rSelp->fromp()->dtypep()
                     && rSelp->lsb() == lConstp->width()) {
                     APPLYING(REPLACE_CONCAT_ZERO_AND_SEL_TOP_WITH_SHIFTR) {
-                        DfgShiftR* const replacementp = new DfgShiftR{m_dfg, flp, vtxp->dtypep()};
+                        DfgShiftR* const replacementp = make<DfgShiftR>(flp, vtxp->dtypep());
                         replacementp->lhsp(rSelp->fromp());
                         replacementp->rhsp(makeI32(flp, lConstp->width()));
-                        vtxp->replaceWith(replacementp);
+                        replace(vtxp, replacementp);
                         return;
                     }
                 }
@@ -1115,10 +1185,10 @@ class V3DfgPeephole final : public DfgVisitor {
             if (DfgSel* const lSelp = lhsp->cast<DfgSel>()) {
                 if (vtxp->dtypep() == lSelp->fromp()->dtypep() && lSelp->lsb() == 0) {
                     APPLYING(REPLACE_CONCAT_SEL_BOTTOM_AND_ZERO_WITH_SHIFTL) {
-                        DfgShiftL* const replacementp = new DfgShiftL{m_dfg, flp, vtxp->dtypep()};
+                        DfgShiftL* const replacementp = make<DfgShiftL>(flp, vtxp->dtypep());
                         replacementp->lhsp(lSelp->fromp());
                         replacementp->rhsp(makeI32(flp, rConstp->width()));
-                        vtxp->replaceWith(replacementp);
+                        replace(vtxp, replacementp);
                         return;
                     }
                 }
@@ -1131,9 +1201,10 @@ class V3DfgPeephole final : public DfgVisitor {
                     APPLYING(PUSH_CONCAT_THROUGH_NOTS) {
                         vtxp->lhsp(lNot->srcp());
                         vtxp->rhsp(rNot->srcp());
-                        DfgNot* const replacementp = new DfgNot{m_dfg, flp, vtxp->dtypep()};
+                        DfgNot* const replacementp = make<DfgNot>(flp, vtxp->dtypep());
                         vtxp->replaceWith(replacementp);
                         replacementp->srcp(vtxp);
+                        modified(vtxp);
                         return;
                     }
                 }
@@ -1146,7 +1217,7 @@ class V3DfgPeephole final : public DfgVisitor {
                     if (lSelp->lsb() == rSelp->lsb() + rSelp->width()) {
                         // Two consecutive Sels, make a single Sel.
                         const uint32_t width = lSelp->width() + rSelp->width();
-                        DfgSel* const joinedSelp = new DfgSel{m_dfg, flp, dtypeForWidth(width)};
+                        DfgSel* const joinedSelp = make<DfgSel>(flp, dtypeForWidth(width));
                         joinedSelp->fromp(rSelp->fromp());
                         joinedSelp->lsb(rSelp->lsb());
                         return joinedSelp;
@@ -1160,7 +1231,7 @@ class V3DfgPeephole final : public DfgVisitor {
             if (lSelp && rSelp) {
                 if (DfgSel* const jointSelp = joinSels(lSelp, rSelp, flp)) {
                     APPLYING(REMOVE_CONCAT_OF_ADJOINING_SELS) {
-                        vtxp->replaceWith(jointSelp);
+                        replace(vtxp, jointSelp);
                         return;
                     }
                 }
@@ -1171,10 +1242,10 @@ class V3DfgPeephole final : public DfgVisitor {
                         if (DfgSel* const jointSelp = joinSels(lSelp, rlSelp, flp)) {
                             APPLYING(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_LHS) {
                                 DfgConcat* const replacementp
-                                    = new DfgConcat{m_dfg, flp, vtxp->dtypep()};
+                                    = make<DfgConcat>(flp, vtxp->dtypep());
                                 replacementp->lhsp(jointSelp);
                                 replacementp->rhsp(rConcatp->rhsp());
-                                vtxp->replaceWith(replacementp);
+                                replace(vtxp, replacementp);
                                 return;
                             }
                         }
@@ -1187,10 +1258,10 @@ class V3DfgPeephole final : public DfgVisitor {
                         if (DfgSel* const jointSelp = joinSels(lrlSelp, rSelp, flp)) {
                             APPLYING(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_RHS) {
                                 DfgConcat* const replacementp
-                                    = new DfgConcat{m_dfg, flp, vtxp->dtypep()};
+                                    = make<DfgConcat>(flp, vtxp->dtypep());
                                 replacementp->lhsp(lConcatp->lhsp());
                                 replacementp->rhsp(jointSelp);
-                                vtxp->replaceWith(replacementp);
+                                replace(vtxp, replacementp);
                                 return;
                             }
                         }
@@ -1320,7 +1391,7 @@ class V3DfgPeephole final : public DfgVisitor {
     void visit(DfgReplicate* vtxp) override {
         if (vtxp->dtypep() == vtxp->srcp()->dtypep()) {
             APPLYING(REMOVE_REPLICATE_ONCE) {
-                vtxp->replaceWith(vtxp->srcp());
+                replace(vtxp, vtxp->srcp());
                 return;
             }
         }
@@ -1364,15 +1435,15 @@ class V3DfgPeephole final : public DfgVisitor {
         if (DfgConst* const rConstp = rhsp->cast<DfgConst>()) {
             if (rConstp->isZero()) {
                 APPLYING(REMOVE_SUB_ZERO) {
-                    vtxp->replaceWith(lhsp);
+                    replace(vtxp, lhsp);
                     return;
                 }
             }
             if (vtxp->dtypep() == m_bitDType && rConstp->hasValue(1)) {
                 APPLYING(REPLACE_SUB_WITH_NOT) {
-                    DfgNot* const replacementp = new DfgNot{m_dfg, vtxp->fileline(), m_bitDType};
+                    DfgNot* const replacementp = make<DfgNot>(vtxp->fileline(), m_bitDType);
                     replacementp->srcp(lhsp);
-                    vtxp->replaceWith(replacementp);
+                    replace(vtxp, replacementp);
                     return;
                 }
             }
@@ -1396,14 +1467,14 @@ class V3DfgPeephole final : public DfgVisitor {
 
         if (condp->isOnes()) {
             APPLYING(REMOVE_COND_WITH_TRUE_CONDITION) {
-                vtxp->replaceWith(thenp);
+                replace(vtxp, thenp);
                 return;
             }
         }
 
         if (condp->isZero()) {
             APPLYING(REMOVE_COND_WITH_FALSE_CONDITION) {
-                vtxp->replaceWith(elsep);
+                replace(vtxp, elsep);
                 return;
             }
         }
@@ -1414,6 +1485,7 @@ class V3DfgPeephole final : public DfgVisitor {
                     vtxp->condp(condNotp->srcp());
                     vtxp->thenp(elsep);
                     vtxp->elsep(thenp);
+                    modified(vtxp);
                     return;
                 }
             }
@@ -1422,12 +1494,13 @@ class V3DfgPeephole final : public DfgVisitor {
         if (DfgNeq* const condNeqp = condp->cast<DfgNeq>()) {
             if (!condp->hasMultipleSinks()) {
                 APPLYING(SWAP_COND_WITH_NEQ_CONDITION) {
-                    DfgEq* const newCondp = new DfgEq{m_dfg, condp->fileline(), condp->dtypep()};
+                    DfgEq* const newCondp = make<DfgEq>(condp->fileline(), condp->dtypep());
                     newCondp->lhsp(condNeqp->lhsp());
                     newCondp->rhsp(condNeqp->rhsp());
                     vtxp->condp(newCondp);
                     vtxp->thenp(elsep);
                     vtxp->elsep(thenp);
+                    modified(vtxp);
                     return;
                 }
             }
@@ -1435,15 +1508,17 @@ class V3DfgPeephole final : public DfgVisitor {
 
         if (DfgNot* const thenNotp = thenp->cast<DfgNot>()) {
             if (DfgNot* const elseNotp = elsep->cast<DfgNot>()) {
-                if ((!thenp->hasMultipleSinks() || thenNotp->hasMultipleSinks())
+                if (!thenNotp->srcp()->is<DfgConst>() && !elseNotp->srcp()->is<DfgConst>()
+                    && (!thenp->hasMultipleSinks() || thenNotp->hasMultipleSinks())
                     && (!elsep->hasMultipleSinks() || elsep->hasMultipleSinks())) {
                     APPLYING(PULL_NOTS_THROUGH_COND) {
                         DfgNot* const replacementp
-                            = new DfgNot{m_dfg, thenp->fileline(), vtxp->dtypep()};
+                            = make<DfgNot>(thenp->fileline(), vtxp->dtypep());
                         vtxp->thenp(thenNotp->srcp());
                         vtxp->elsep(elseNotp->srcp());
                         vtxp->replaceWith(replacementp);
                         replacementp->srcp(vtxp);
+                        modified(vtxp);
                         return;
                     }
                 }
@@ -1457,14 +1532,14 @@ class V3DfgPeephole final : public DfgVisitor {
                     if (constp->hasValue(1)) {
                         if (thenAddp->rhsp() == elsep) {
                             APPLYING(REPLACE_COND_INC) {
-                                DfgConcat* const extp = new DfgConcat{m_dfg, flp, vtxp->dtypep()};
+                                DfgConcat* const extp = make<DfgConcat>(flp, vtxp->dtypep());
                                 extp->rhsp(condp);
                                 extp->lhsp(makeZero(flp, vtxp->width() - 1));
                                 FileLine* const thenFlp = thenAddp->fileline();
-                                DfgAdd* const addp = new DfgAdd{m_dfg, thenFlp, vtxp->dtypep()};
+                                DfgAdd* const addp = make<DfgAdd>(thenFlp, vtxp->dtypep());
                                 addp->lhsp(thenAddp->rhsp());
                                 addp->rhsp(extp);
-                                vtxp->replaceWith(addp);
+                                replace(vtxp, addp);
                                 return;
                             }
                         }
@@ -1477,14 +1552,14 @@ class V3DfgPeephole final : public DfgVisitor {
                     if (constp->hasValue(1)) {
                         if (thenSubp->lhsp() == elsep) {
                             APPLYING(REPLACE_COND_DEC) {
-                                DfgConcat* const extp = new DfgConcat{m_dfg, flp, vtxp->dtypep()};
+                                DfgConcat* const extp = make<DfgConcat>(flp, vtxp->dtypep());
                                 extp->rhsp(condp);
                                 extp->lhsp(makeZero(flp, vtxp->width() - 1));
                                 FileLine* const thenFlp = thenSubp->fileline();
-                                DfgSub* const subp = new DfgSub{m_dfg, thenFlp, vtxp->dtypep()};
+                                DfgSub* const subp = make<DfgSub>(thenFlp, vtxp->dtypep());
                                 subp->lhsp(thenSubp->lhsp());
                                 subp->rhsp(extp);
-                                vtxp->replaceWith(subp);
+                                replace(vtxp, subp);
                                 return;
                             }
                         }
@@ -1497,41 +1572,41 @@ class V3DfgPeephole final : public DfgVisitor {
             AstNodeDType* const dtypep = vtxp->dtypep();
             if (thenp->isZero()) {  // a ? 0 : b becomes ~a & b
                 APPLYING(REPLACE_COND_WITH_THEN_BRANCH_ZERO) {
-                    DfgAnd* const repalcementp = new DfgAnd{m_dfg, flp, dtypep};
-                    DfgNot* const notp = new DfgNot{m_dfg, flp, dtypep};
+                    DfgAnd* const repalcementp = make<DfgAnd>(flp, dtypep);
+                    DfgNot* const notp = make<DfgNot>(flp, dtypep);
                     notp->srcp(condp);
                     repalcementp->lhsp(notp);
                     repalcementp->rhsp(elsep);
-                    vtxp->replaceWith(repalcementp);
+                    replace(vtxp, repalcementp);
                     return;
                 }
             }
             if (thenp->isOnes()) {  // a ? 1 : b becomes a | b
                 APPLYING(REPLACE_COND_WITH_THEN_BRANCH_ONES) {
-                    DfgOr* const repalcementp = new DfgOr{m_dfg, flp, dtypep};
+                    DfgOr* const repalcementp = make<DfgOr>(flp, dtypep);
                     repalcementp->lhsp(condp);
                     repalcementp->rhsp(elsep);
-                    vtxp->replaceWith(repalcementp);
+                    replace(vtxp, repalcementp);
                     return;
                 }
             }
             if (elsep->isZero()) {  // a ? b : 0 becomes a & b
                 APPLYING(REPLACE_COND_WITH_ELSE_BRANCH_ZERO) {
-                    DfgAnd* const repalcementp = new DfgAnd{m_dfg, flp, dtypep};
+                    DfgAnd* const repalcementp = make<DfgAnd>(flp, dtypep);
                     repalcementp->lhsp(condp);
                     repalcementp->rhsp(thenp);
-                    vtxp->replaceWith(repalcementp);
+                    replace(vtxp, repalcementp);
                     return;
                 }
             }
             if (elsep->isOnes()) {  // a ? b : 1 becomes ~a | b
                 APPLYING(REPLACE_COND_WITH_ELSE_BRANCH_ONES) {
-                    DfgOr* const repalcementp = new DfgOr{m_dfg, flp, dtypep};
-                    DfgNot* const notp = new DfgNot{m_dfg, flp, dtypep};
+                    DfgOr* const repalcementp = make<DfgOr>(flp, dtypep);
+                    DfgNot* const notp = make<DfgNot>(flp, dtypep);
                     notp->srcp(condp);
                     repalcementp->lhsp(notp);
                     repalcementp->rhsp(thenp);
-                    vtxp->replaceWith(repalcementp);
+                    replace(vtxp, repalcementp);
                     return;
                 }
             }
@@ -1540,48 +1615,43 @@ class V3DfgPeephole final : public DfgVisitor {
 
 #undef APPLYING
 
-    // Process one vertex. Return true if graph changed
+    //    // Process one vertex. Return true if graph changed
     void processVertex(DfgVertex* vtxp) {
-        // If it has no sinks (unused), we can remove it
+        // Check if unused and remove if so
         if (!vtxp->hasSinks()) {
-            vtxp->unlinkDelete(m_dfg);
-            m_changed = true;
+            deleteVertex(vtxp);
             return;
         }
 
-        // Transform node
+        // Transform node (might get deleted)
         iterate(vtxp);
-
-        // If it became unused, we can remove it
-        if (!vtxp->hasSinks()) {
-            UASSERT_OBJ(m_changed, vtxp, "'m_changed' must be set if node became unused");
-            vtxp->unlinkDelete(m_dfg);
-        }
     }
 
     V3DfgPeephole(DfgGraph& dfg, V3DfgPeepholeContext& ctx)
         : m_dfg{dfg}
         , m_ctx{ctx} {
 
-        while (true) {
-            // Do one pass over the graph in the forward direction.
-            m_changed = false;
-            for (DfgVertex *vtxp = m_dfg.opVerticesBeginp(), *nextp; vtxp; vtxp = nextp) {
-                nextp = vtxp->verticesNext();
-                if (VL_LIKELY(nextp)) VL_PREFETCH_RW(nextp);
-                processVertex(vtxp);
-            }
-            if (!m_changed) break;
+        // DfgVertex::user is the next pointer of the work list elements
+        const auto userDataInUse = m_dfg.userDataInUse();
 
-            // Do another pass in the opposite direction. Alternating directions reduces
-            // the pathological complexity with left/right leaning trees.
-            m_changed = false;
-            for (DfgVertex *vtxp = m_dfg.opVerticesRbeginp(), *nextp; vtxp; vtxp = nextp) {
-                nextp = vtxp->verticesPrev();
-                if (VL_LIKELY(nextp)) VL_PREFETCH_RW(nextp);
-                processVertex(vtxp);
-            }
-            if (!m_changed) break;
+        // Add all vertices to the work list. This also allocates all DfgVertex::user.
+        for (DfgVertex *vtxp = m_dfg.opVerticesBeginp(), *nextp; vtxp; vtxp = nextp) {
+            nextp = vtxp->verticesNext();
+            if (VL_LIKELY(nextp)) VL_PREFETCH_RW(nextp);
+            vtxp->setUser<DfgVertex*>(m_workListp);
+            m_workListp = vtxp;
+        }
+
+        // Process the work list
+        while (m_workListp != reinterpret_cast<DfgVertex*>(this)) {
+            // Pick up the head
+            DfgVertex* const vtxp = m_workListp;
+            // Detach the head and prefetch next
+            m_workListp = vtxp->getUser<DfgVertex*>();
+            VL_PREFETCH_RW(m_workListp);
+            vtxp->setUser<DfgVertex*>(nullptr);
+            // Process the vertex
+            processVertex(vtxp);
         }
     }
 
diff --git a/test_regress/t/t_dfg_peephole.v b/test_regress/t/t_dfg_peephole.v
index e3e3862bd..de4f54229 100644
--- a/test_regress/t/t_dfg_peephole.v
+++ b/test_regress/t/t_dfg_peephole.v
@@ -31,9 +31,6 @@ module t (
    assign array[0] = (rand_a << 32) | (rand_a >> 32);
    assign array[1] = (rand_a << 16) | (rand_a >> 48);
 
-   // x, but with evaluation slightly delayed in DfgPeephole
-`define DFG(x) (&16'hffff ? (x) : (~x))
-
    `signal(FOLD_UNARY_CLog2,       $clog2(const_a));
    `signal(FOLD_UNARY_CountOnes,   $countones(const_a));
    `signal(FOLD_UNARY_IsUnknown,   $isunknown(const_a));
@@ -150,8 +147,10 @@ module t (
    `signal(REPLACE_CONCAT_SEL_BOTTOM_AND_ZERO_WITH_SHIFTL, {rand_a[1:0], 62'd0});
    `signal(PUSH_CONCAT_THROUGH_NOTS, {~(rand_a+64'd101), ~(rand_b+64'd101)} );
    `signal(REMOVE_CONCAT_OF_ADJOINING_SELS, {rand_a[10:3], rand_a[2:1]});
-   `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_LHS, {rand_a[10:3], `DFG({rand_a[2:1], rand_b})});
-   `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_RHS, {`DFG({rand_b, rand_a[10:3]}), rand_a[2:1]});
+   `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_LHS_CAT, {rand_a[2:1], rand_b});
+   `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_RHS_CAT, {rand_b, rand_a[10:3]});
+   `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_LHS, {rand_a[10:3], {rand_a[2:1], rand_b}});
+   `signal(REPLACE_NESTED_CONCAT_OF_ADJOINING_SELS_ON_RHS, {{rand_b, rand_a[10:3]}, rand_a[2:1]});
    `signal(REMOVE_COND_WITH_FALSE_CONDITION, 1'd0 ? rand_a : rand_b);
    `signal(REMOVE_COND_WITH_TRUE_CONDITION, 1'd1 ? rand_a : rand_b);
    `signal(SWAP_COND_WITH_NOT_CONDITION, (~rand_a[0] & 1'd1) ? rand_a : rand_b);

From 454efbe3fc17c55512d667bee69ab9349cf69a75 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Sun, 6 Nov 2022 14:13:42 +0000
Subject: [PATCH 011/156] Dfg: Use a worklist driven algorithm for unused
 vertex removal

This improves verilation speed slightly.
---
 src/V3DfgPasses.cpp | 68 ++++++++++++++++++++++++++++++---------------
 1 file changed, 46 insertions(+), 22 deletions(-)

diff --git a/src/V3DfgPasses.cpp b/src/V3DfgPasses.cpp
index 2abc21986..396a18027 100644
--- a/src/V3DfgPasses.cpp
+++ b/src/V3DfgPasses.cpp
@@ -209,29 +209,53 @@ void V3DfgPasses::removeVars(DfgGraph& dfg, DfgRemoveVarsContext& ctx) {
 }
 
 void V3DfgPasses::removeUnused(DfgGraph& dfg) {
-    // Iteratively remove operation vertices
-    while (true) {
-        // Do one pass over the graph.
-        bool changed = false;
-        for (DfgVertex *vtxp = dfg.opVerticesBeginp(), *nextp; vtxp; vtxp = nextp) {
-            nextp = vtxp->verticesNext();
-            if (!vtxp->hasSinks()) {
-                changed = true;
-                vtxp->unlinkDelete(dfg);
-            }
+    // DfgVertex::user is the next pointer of the work list elements
+    const auto userDataInUse = dfg.userDataInUse();
+
+    // Head of work list. Note that we want all next pointers in the list to be non-zero (including
+    // that of the last element). This allows as to do two important things: detect if an element
+    // is in the list by checking for a non-zero next poitner, and easy prefetching without
+    // conditionals. The address of the graph is a good sentinel as it is a valid memory address,
+    // and we can easily check for the end of the list.
+    DfgVertex* const sentinelp = reinterpret_cast<DfgVertex*>(&dfg);
+    DfgVertex* workListp = sentinelp;
+
+    // Add all unused vertices to the work list. This also allocates all DfgVertex::user.
+    for (DfgVertex *vtxp = dfg.opVerticesBeginp(), *nextp; vtxp; vtxp = nextp) {
+        nextp = vtxp->verticesNext();
+        if (VL_LIKELY(nextp)) VL_PREFETCH_RW(nextp);
+        if (vtxp->hasSinks()) {
+            // This vertex is used. Allocate user, but don't add to work list.
+            vtxp->setUser<DfgVertex*>(nullptr);
+        } else {
+            // This vertex is unused. Add to work list.
+            vtxp->setUser<DfgVertex*>(workListp);
+            workListp = vtxp;
         }
-        if (!changed) break;
-        // Do another pass in the opposite direction. Alternating directions reduces
-        // the pathological complexity with left/right leaning trees.
-        changed = false;
-        for (DfgVertex *vtxp = dfg.opVerticesRbeginp(), *nextp; vtxp; vtxp = nextp) {
-            nextp = vtxp->verticesPrev();
-            if (!vtxp->hasSinks()) {
-                changed = true;
-                vtxp->unlinkDelete(dfg);
-            }
-        }
-        if (!changed) break;
+    }
+
+    // Process the work list
+    while (workListp != sentinelp) {
+        // Pick up the head
+        DfgVertex* const vtxp = workListp;
+        // Detach the head
+        workListp = vtxp->getUser<DfgVertex*>();
+        // Prefetch next item
+        VL_PREFETCH_RW(workListp);
+        // If used, then nothing to do, so move on
+        if (vtxp->hasSinks()) continue;
+        // Add sources of unused vertex to work list
+        vtxp->forEachSource([&](DfgVertex& src) {
+            // We only remove actual operation vertices in this loop
+            if (src.is<DfgConst>() || src.is<DfgVertexVar>()) return;
+            // If already in work list then nothing to do
+            if (src.getUser<DfgVertex*>()) return;
+            // Actually add to work list.
+            src.setUser<DfgVertex*>(workListp);
+            workListp = &src;
+        });
+        // Remove the unused vertex
+        vtxp->unlinkDelete(dfg);
     }
 
     // Finally remove unused constants

From 2a3eabff73149eddba4fc46501540184934b89e7 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Sun, 6 Nov 2022 15:42:01 +0000
Subject: [PATCH 012/156] Various Dfg performance improvements

---
 src/V3Dfg.h           |  12 +++
 src/V3DfgDfgToAst.cpp |  15 +---
 src/V3DfgPasses.cpp   | 174 ++++++++++++++++++++++--------------------
 src/V3DfgPeephole.cpp |  21 ++---
 4 files changed, 114 insertions(+), 108 deletions(-)

diff --git a/src/V3Dfg.h b/src/V3Dfg.h
index d8770d6ce..8578a7c53 100644
--- a/src/V3Dfg.h
+++ b/src/V3Dfg.h
@@ -496,6 +496,9 @@ public:
     // Is this a DfgConst that is all ones
     inline bool isOnes() const;
 
+    // Should this vertex be inlined when rendering to Ast, or be stored to a temporary
+    inline bool inlined() const;
+
     // Methods that allow DfgVertex to participate in error reporting/messaging
     void v3errorEnd(std::ostringstream& str) const { m_filelinep->v3errorEnd(str); }
     void v3errorEndFatal(std::ostringstream& str) const VL_ATTR_NORETURN {
@@ -914,4 +917,13 @@ bool DfgVertex::isOnes() const {
     return false;
 }
 
+bool DfgVertex::inlined() const {
+    // Inline vertices that drive only a single node, or are special
+    if (!hasMultipleSinks()) return true;
+    if (is<DfgConst>()) return true;
+    if (is<DfgVertexVar>()) return true;
+    if (const DfgArraySel* const selp = cast<DfgArraySel>()) return selp->bitp()->is<DfgConst>();
+    return false;
+}
+
 #endif
diff --git a/src/V3DfgDfgToAst.cpp b/src/V3DfgDfgToAst.cpp
index f87c443c8..32fb87b8f 100644
--- a/src/V3DfgDfgToAst.cpp
+++ b/src/V3DfgDfgToAst.cpp
@@ -221,19 +221,8 @@ class DfgToAstVisitor final : DfgVisitor {
         return resultp;
     }
 
-    bool inlineVertex(DfgVertex& vtx) {
-        // Inline vertices that drive only a single node, or are special
-        if (!vtx.hasMultipleSinks()) return true;
-        if (vtx.is<DfgConst>()) return true;
-        if (vtx.is<DfgVertexVar>()) return true;
-        if (const DfgArraySel* const selp = vtx.cast<DfgArraySel>()) {
-            return selp->bitp()->is<DfgConst>();
-        }
-        return false;
-    }
-
     AstNodeExpr* convertSource(DfgVertex* vtxp) {
-        if (inlineVertex(*vtxp)) {
+        if (vtxp->inlined()) {
             // Inlined vertices are simply recursively converted
             UASSERT_OBJ(vtxp->hasSinks(), vtxp, "Must have one sink: " << vtxp->typeName());
             return convertDfgVertexToAstNodeExpr(vtxp);
@@ -406,7 +395,7 @@ class DfgToAstVisitor final : DfgVisitor {
             nextp = vtxp->verticesNext();
 
             // If the vertex is known to be inlined, then there is nothing to do
-            if (inlineVertex(*vtxp)) continue;
+            if (vtxp->inlined()) continue;
 
             // Check if this uses a temporary, vs one of the vars rendered above
             AstVar* const resultVarp = getResultVar(vtxp);
diff --git a/src/V3DfgPasses.cpp b/src/V3DfgPasses.cpp
index 396a18027..26e1b3b6b 100644
--- a/src/V3DfgPasses.cpp
+++ b/src/V3DfgPasses.cpp
@@ -75,59 +75,66 @@ V3DfgOptimizationContext::~V3DfgOptimizationContext() {
             "Inconsistent statistics");
 }
 
-// Common subexpression elimination
+// Common sub-expression elimination
 void V3DfgPasses::cse(DfgGraph& dfg, V3DfgCseContext& ctx) {
-    DfgVertex::EqualsCache equalsCache;
-    std::unordered_map<V3Hash, std::vector<DfgVertex*>> verticesWithEqualHashes;
-    verticesWithEqualHashes.reserve(dfg.size());
+    // Remove common sub-expressions
+    {
+        // Used by DfgVertex::hash
+        const auto userDataInUse = dfg.userDataInUse();
 
-    // Used by DfgVertex::hash
-    const auto userDataInUse = dfg.userDataInUse();
+        DfgVertex::EqualsCache equalsCache;
+        std::unordered_map<V3Hash, std::vector<DfgVertex*>> verticesWithEqualHashes;
+        verticesWithEqualHashes.reserve(dfg.size());
 
-    // Pre-hash variables for speed, these are all unique, so just set their hash to a unique value
-    uint32_t varHash = 0;
-    for (DfgVertexVar *vtxp = dfg.varVerticesBeginp(), *nextp; vtxp; vtxp = nextp) {
-        nextp = vtxp->verticesNext();
-        vtxp->user<V3Hash>() = V3Hash{++varHash};
-    }
-
-    // Similarly pre-hash constants for speed. While we don't combine constants, we do want
-    // expressions using the same constants to be combined, so we do need to hash equal constants
-    // to equal values.
-    for (DfgConst *vtxp = dfg.constVerticesBeginp(), *nextp; vtxp; vtxp = nextp) {
-        nextp = vtxp->verticesNext();
-        // Get rid of unused constants while we are at it
-        if (!vtxp->hasSinks()) {
-            vtxp->unlinkDelete(dfg);
-            continue;
+        // Pre-hash variables, these are all unique, so just set their hash to a unique value
+        uint32_t varHash = 0;
+        for (DfgVertexVar *vtxp = dfg.varVerticesBeginp(), *nextp; vtxp; vtxp = nextp) {
+            nextp = vtxp->verticesNext();
+            vtxp->user<V3Hash>() = V3Hash{++varHash};
         }
-        vtxp->user<V3Hash>() = vtxp->num().toHash();
-    }
 
-    // Combine operation vertices
-    for (DfgVertex *vtxp = dfg.opVerticesBeginp(), *nextp; vtxp; vtxp = nextp) {
-        nextp = vtxp->verticesNext();
-        // Get rid of unused operations while we are at it
-        if (!vtxp->hasSinks()) {
-            vtxp->unlinkDelete(dfg);
-            continue;
-        }
-        const V3Hash hash = vtxp->hash();
-        if (VL_LIKELY(nextp)) VL_PREFETCH_RW(nextp);
-        std::vector<DfgVertex*>& vec = verticesWithEqualHashes[hash];
-        bool replaced = false;
-        for (DfgVertex* const candidatep : vec) {
-            if (candidatep->equals(*vtxp, equalsCache)) {
-                ++ctx.m_eliminated;
-                vtxp->replaceWith(candidatep);
+        // Similarly pre-hash constants for speed. While we don't combine constants, we do want
+        // expressions using the same constants to be combined, so we do need to hash equal
+        // constants to equal values.
+        for (DfgConst *vtxp = dfg.constVerticesBeginp(), *nextp; vtxp; vtxp = nextp) {
+            nextp = vtxp->verticesNext();
+            if (VL_LIKELY(nextp)) VL_PREFETCH_RW(nextp);
+            // Delete unused constants while we are at it.
+            if (!vtxp->hasSinks()) {
                 vtxp->unlinkDelete(dfg);
-                replaced = true;
-                break;
+                continue;
             }
+            vtxp->user<V3Hash>() = vtxp->num().toHash() + varHash;
+        }
+
+        // Combine operation vertices
+        for (DfgVertex *vtxp = dfg.opVerticesBeginp(), *nextp; vtxp; vtxp = nextp) {
+            nextp = vtxp->verticesNext();
+            if (VL_LIKELY(nextp)) VL_PREFETCH_RW(nextp);
+            // Delete unused nodes while we are at it.
+            if (!vtxp->hasSinks()) {
+                vtxp->unlinkDelete(dfg);
+                continue;
+            }
+            const V3Hash hash = vtxp->hash();
+            std::vector<DfgVertex*>& vec = verticesWithEqualHashes[hash];
+            bool replaced = false;
+            for (DfgVertex* const candidatep : vec) {
+                if (candidatep->equals(*vtxp, equalsCache)) {
+                    ++ctx.m_eliminated;
+                    vtxp->replaceWith(candidatep);
+                    vtxp->unlinkDelete(dfg);
+                    replaced = true;
+                    break;
+                }
+            }
+            if (replaced) continue;
+            vec.push_back(vtxp);
         }
-        if (replaced) continue;
-        vec.push_back(vtxp);
     }
+
+    // Prune unused nodes
+    removeUnused(dfg);
 }
 
 void V3DfgPasses::inlineVars(DfgGraph& dfg) {
@@ -167,41 +174,46 @@ void V3DfgPasses::removeVars(DfgGraph& dfg, DfgRemoveVarsContext& ctx) {
         // Can't remove if it has consumers
         if (varp->hasSinks()) continue;
 
-        // Can't remove if read in the module and driven here (i.e.: it's an output of the DFG)
-        if (varp->hasModRefs() && varp->isDrivenByDfg()) continue;
-
-        // Can't remove if only partially driven by the DFG
-        if (varp->isDrivenByDfg() && !varp->isDrivenFullyByDfg()) continue;
-
-        // Can't remove if referenced externally, or other special reasons
-        if (varp->keep()) continue;
-
-        // If the driver of this variable has multiple non-variable sinks, then we would need
-        // a temporary when rendering the graph. Instead of introducing a temporary, keep the
-        // first variable that is driven by that driver
+        // Otherwise if it has drivers
         if (varp->isDrivenByDfg()) {
-            DfgVertex* const driverp = varp->source(0);
-            unsigned nonVarSinks = 0;
-            const DfgVarPacked* firstSinkVarp = nullptr;
-            const bool keepFirst = driverp->findSink<DfgVertex>([&](const DfgVertex& sink) {
-                if (const DfgVarPacked* const sinkVarp = sink.cast<DfgVarPacked>()) {
-                    if (!firstSinkVarp) firstSinkVarp = sinkVarp;
-                } else {
-                    ++nonVarSinks;
+            // Can't remove if read in the module and driven here (i.e.: it's an output of the DFG)
+            if (varp->hasModRefs()) continue;
+
+            // Can't remove if referenced externally, or other special reasons
+            if (varp->keep()) continue;
+
+            // If the driver of this variable is not an inlined vertex, then we would need a
+            // temporary when rendering the graph. Instead of introducing a temporary, keep the
+            // first variable that is driven by that driver. Note that we still remove if the only
+            // sinks we have are variables, as we might be able to remove all of them (we can be
+            // sure the not inlined if we have at least 2 non-variable sinks).
+            if (varp->isDrivenFullyByDfg()) {
+                DfgVertex* const driverp = varp->source(0);
+                if (!driverp->inlined()) {
+                    unsigned nonVarSinks = 0;
+                    const DfgVarPacked* firstp = nullptr;
+                    const bool found = driverp->findSink<DfgVertex>([&](const DfgVertex& sink) {
+                        if (const DfgVarPacked* const sinkVarp = sink.cast<DfgVarPacked>()) {
+                            if (!firstp) firstp = sinkVarp;
+                        } else {
+                            ++nonVarSinks;
+                        }
+                        // We can stop as soon as we found the first var, and 2 non-var sinks
+                        return firstp && nonVarSinks >= 2;
+                    });
+                    // Keep this DfgVarPacked if needed
+                    if (found && firstp == varp) continue;
                 }
-                // We can stop as soon as we found the first var, and 2 non-var sinks
-                return firstSinkVarp && nonVarSinks >= 2;
-            });
-            // Keep this DfgVarPacked if needed
-            if (keepFirst && firstSinkVarp == varp) continue;
+            }
         }
 
-        // OK, we can delete this DfgVarPacked
-        ++ctx.m_removed;
+        // OK, we can delete this DfgVarPacked from the graph.
 
-        // If not referenced outside the DFG, then also delete the referenced AstVar,
-        // as it is now unused.
-        if (!varp->hasRefs()) varp->varp()->unlinkFrBack()->deleteTree();
+        // If not referenced outside the DFG, then also delete the referenced AstVar (now unused).
+        if (!varp->hasRefs()) {
+            ++ctx.m_removed;
+            varp->varp()->unlinkFrBack()->deleteTree();
+        }
 
         // Unlink and delete vertex
         varp->unlinkDelete(dfg);
@@ -283,14 +295,14 @@ void V3DfgPasses::optimize(DfgGraph& dfg, V3DfgOptimizationContext& ctx) {
     };
 
     if (dumpDfg() >= 8) dfg.dumpDotAllVarConesPrefixed(ctx.prefix() + "input");
-    apply(3, "input         ", [&]() {});
-    apply(4, "cse           ", [&]() { cse(dfg, ctx.m_cseContext0); });
-    apply(4, "inlineVars    ", [&]() { inlineVars(dfg); });
+    apply(3, "input           ", [&]() {});
+    apply(4, "inlineVars      ", [&]() { inlineVars(dfg); });
+    apply(4, "cse0            ", [&]() { cse(dfg, ctx.m_cseContext0); });
     if (v3Global.opt.fDfgPeephole()) {
-        apply(4, "peephole      ", [&]() { peephole(dfg, ctx.m_peepholeContext); });
+        apply(4, "peephole        ", [&]() { peephole(dfg, ctx.m_peepholeContext); });
+        // We just did CSE above, so without peephole there is no need to run it again these
+        apply(4, "cse1            ", [&]() { cse(dfg, ctx.m_cseContext1); });
     }
-    apply(4, "cse           ", [&]() { cse(dfg, ctx.m_cseContext1); });
-    apply(4, "removeVars    ", [&]() { removeVars(dfg, ctx.m_removeVarsContext); });
-    apply(3, "optimized     ", [&]() { removeUnused(dfg); });
+    apply(4, "removeVars      ", [&]() { removeVars(dfg, ctx.m_removeVarsContext); });
     if (dumpDfg() >= 8) dfg.dumpDotAllVarConesPrefixed(ctx.prefix() + "optimized");
 }
diff --git a/src/V3DfgPeephole.cpp b/src/V3DfgPeephole.cpp
index df78ea1d3..c17f3776c 100644
--- a/src/V3DfgPeephole.cpp
+++ b/src/V3DfgPeephole.cpp
@@ -1615,18 +1615,6 @@ class V3DfgPeephole final : public DfgVisitor {
 
 #undef APPLYING
 
-    //    // Process one vertex. Return true if graph changed
-    void processVertex(DfgVertex* vtxp) {
-        // Check if unused and remove if so
-        if (!vtxp->hasSinks()) {
-            deleteVertex(vtxp);
-            return;
-        }
-
-        // Transform node (might get deleted)
-        iterate(vtxp);
-    }
-
     V3DfgPeephole(DfgGraph& dfg, V3DfgPeepholeContext& ctx)
         : m_dfg{dfg}
         , m_ctx{ctx} {
@@ -1650,8 +1638,13 @@ class V3DfgPeephole final : public DfgVisitor {
             m_workListp = vtxp->getUser<DfgVertex*>();
             VL_PREFETCH_RW(m_workListp);
             vtxp->setUser<DfgVertex*>(nullptr);
-            // Process the vertex
-            processVertex(vtxp);
+            // Remove unused vertices as we gp
+            if (!vtxp->hasSinks()) {
+                deleteVertex(vtxp);
+                continue;
+            }
+            // Transform node (might get deleted in the process)
+            iterate(vtxp);
         }
     }
 

From a29d9469dadf43eaf7d2d7d881421cdccef61a8b Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Wed, 9 Nov 2022 02:01:08 +0100
Subject: [PATCH 013/156] Fix jump handling in do while loops (#3731)

---
 src/V3Ast.h                                |   5 -
 src/V3AstNodeOther.h                       |  20 +++
 src/V3LinkJump.cpp                         |  35 ++++-
 src/verilog.y                              |   6 +-
 test_regress/t/t_continue_do_while_bad.out |   6 +
 test_regress/t/t_continue_do_while_bad.pl  |  20 +++
 test_regress/t/t_continue_do_while_bad.v   |  24 +++
 test_regress/t/t_jumps_do_while.pl         |  22 +++
 test_regress/t/t_jumps_do_while.v          | 173 +++++++++++++++++++++
 9 files changed, 298 insertions(+), 13 deletions(-)
 create mode 100644 test_regress/t/t_continue_do_while_bad.out
 create mode 100755 test_regress/t/t_continue_do_while_bad.pl
 create mode 100644 test_regress/t/t_continue_do_while_bad.v
 create mode 100755 test_regress/t/t_jumps_do_while.pl
 create mode 100644 test_regress/t/t_jumps_do_while.v

diff --git a/src/V3Ast.h b/src/V3Ast.h
index 0e8f277a7..eaf3f6e58 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -1874,7 +1874,6 @@ public:
         return static_cast<T_NodeResult*>(addNext<AstNode, AstNode>(nodep, newp));
     }
     inline AstNode* addNext(AstNode* newp);
-    inline void addPrev(AstNode* newp);
     void addNextHere(AstNode* newp);  // Insert newp at this->nextp
     void addHereThisAsNext(AstNode* newp);  // Adds at old place of this, this becomes next
     void replaceWith(AstNode* newp);  // Replace current node in tree with new node
@@ -2207,10 +2206,6 @@ AstNode* AstNode::addNext<AstNode, AstNode>(AstNode* nodep, AstNode* newp);
 
 // Inline method implementations
 AstNode* AstNode::addNext(AstNode* newp) { return addNext(this, newp); }
-void AstNode::addPrev(AstNode* newp) {
-    replaceWith(newp);
-    newp->addNext(this);
-}
 
 // Specialisations of privateTypeTest
 #include "V3Ast__gen_type_tests.h"  // From ./astgen
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index cbafbfc8b..a88aa3ee6 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -2725,6 +2725,26 @@ public:
     // * = Add a newline for $display
     bool addNewline() const { return displayType().addNewline(); }
 };
+class AstDoWhile final : public AstNodeStmt {
+    // @astgen op1 := precondsp : List[AstNode]
+    // @astgen op2 := condp : AstNode
+    // @astgen op3 := stmtsp : List[AstNode]
+    // @astgen op4 := incsp : List[AstNode]
+public:
+    AstDoWhile(FileLine* fl, AstNode* conditionp, AstNode* stmtsp = nullptr,
+               AstNode* incsp = nullptr)
+        : ASTGEN_SUPER_DoWhile(fl) {
+        condp(conditionp);
+        addStmtsp(stmtsp);
+        addIncsp(incsp);
+    }
+    ASTGEN_MEMBERS_AstDoWhile;
+    bool isGateOptimizable() const override { return false; }
+    int instrCount() const override { return INSTR_COUNT_BRANCH; }
+    bool same(const AstNode* /*samep*/) const override { return true; }
+    // Stop statement searchback here
+    bool isFirstInMyListOfStatements(AstNode* n) const override { return n == stmtsp(); }
+};
 class AstDumpCtl final : public AstNodeStmt {
     // $dumpon etc
     // Parents: expr
diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp
index e42e37987..6e1b6f319 100644
--- a/src/V3LinkJump.cpp
+++ b/src/V3LinkJump.cpp
@@ -83,6 +83,14 @@ private:
                 underp = nodep;
                 under_and_next = false;  // IE we skip the entire while
             }
+        } else if (AstDoWhile* const dowhilep = VN_CAST(nodep, DoWhile)) {
+            // Handle it the same as AstWhile, because it will be converted to it
+            if (endOfIter) {
+                underp = dowhilep->stmtsp();
+            } else {
+                underp = nodep;
+                under_and_next = false;
+            }
         } else {
             nodep->v3fatalSrc("Unknown jump point for break/disable/continue");
             return nullptr;
@@ -113,7 +121,7 @@ private:
             // Keep any AstVars under the function not under the new JumpLabel
             for (AstNode *nextp, *varp = underp; varp; varp = nextp) {
                 nextp = varp->nextp();
-                if (VN_IS(varp, Var)) blockp->addPrev(varp->unlinkFrBack());
+                if (VN_IS(varp, Var)) blockp->addHereThisAsNext(varp->unlinkFrBack());
             }
             // Label goes last
             blockp->addEndStmtsp(labelp);
@@ -189,6 +197,27 @@ private:
             iterateAndNextNull(nodep->incsp());
         }
     }
+    void visit(AstDoWhile* nodep) override {
+        // It is converted to AstWhile in this visit method
+        VL_RESTORER(m_loopp);
+        VL_RESTORER(m_loopInc);
+        {
+            m_loopp = nodep;
+            m_loopInc = false;
+            iterateAndNextNull(nodep->precondsp());
+            iterateAndNextNull(nodep->condp());
+            iterateAndNextNull(nodep->stmtsp());
+            m_loopInc = true;
+            iterateAndNextNull(nodep->incsp());
+        }
+        AstNode* const condp = nodep->condp() ? nodep->condp()->unlinkFrBack() : nullptr;
+        AstNode* const bodyp = nodep->stmtsp() ? nodep->stmtsp()->unlinkFrBack() : nullptr;
+        AstNode* const incsp = nodep->incsp() ? nodep->incsp()->unlinkFrBack() : nullptr;
+        AstWhile* const whilep = new AstWhile{nodep->fileline(), condp, bodyp, incsp};
+        nodep->replaceWith(whilep);
+        VL_DO_DANGLING(nodep->deleteTree(), nodep);
+        if (bodyp) whilep->addHereThisAsNext(bodyp->cloneTree(false));
+    }
     void visit(AstForeach* nodep) override {
         VL_RESTORER(m_loopp);
         {
@@ -212,14 +241,14 @@ private:
         } else {
             if (funcp && nodep->lhsp()) {
                 // Set output variable to return value
-                nodep->addPrev(new AstAssign(
+                nodep->addHereThisAsNext(new AstAssign(
                     nodep->fileline(),
                     new AstVarRef(nodep->fileline(), VN_AS(funcp->fvarp(), Var), VAccess::WRITE),
                     nodep->lhsp()->unlinkFrBackWithNext()));
             }
             // Jump to the end of the function call
             AstJumpLabel* const labelp = findAddLabel(m_ftaskp, false);
-            nodep->addPrev(new AstJumpGo(nodep->fileline(), labelp));
+            nodep->addHereThisAsNext(new AstJumpGo(nodep->fileline(), labelp));
         }
         nodep->unlinkFrBack();
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
diff --git a/src/verilog.y b/src/verilog.y
index 28f453728..1367e140d 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3324,11 +3324,7 @@ statement_item<nodep>:          // IEEE: statement_item
         |       yWHILE '(' expr ')' stmtBlock           { $$ = new AstWhile{$1, $3, $5}; }
         //                      // for's first ';' is in for_initialization
         |       statementFor                            { $$ = $1; }
-        |       yDO stmtBlock yWHILE '(' expr ')' ';'   { if ($2) {
-                                                             $$ = $2->cloneTree(true);
-                                                             $$->addNext(new AstWhile($1,$5,$2));
-                                                          }
-                                                          else $$ = new AstWhile($1,$5); }
+        |       yDO stmtBlock yWHILE '(' expr ')' ';'   { $$ = new AstDoWhile{$1, $5, $2}; }
         //                      // IEEE says array_identifier here, but dotted accepted in VMM and 1800-2009
         |       yFOREACH '(' idClassSelForeach ')' stmtBlock    { $$ = new AstForeach($1, $3, $5); }
         //
diff --git a/test_regress/t/t_continue_do_while_bad.out b/test_regress/t/t_continue_do_while_bad.out
new file mode 100644
index 000000000..797057234
--- /dev/null
+++ b/test_regress/t/t_continue_do_while_bad.out
@@ -0,0 +1,6 @@
+%Warning-INFINITELOOP: t/t_continue_do_while_bad.v:14:7: Infinite loop (condition always true)
+   14 |       do begin
+      |       ^~
+                       ... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest
+                       ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message.
+%Error: Exiting due to
diff --git a/test_regress/t/t_continue_do_while_bad.pl b/test_regress/t/t_continue_do_while_bad.pl
new file mode 100755
index 000000000..f201521f0
--- /dev/null
+++ b/test_regress/t/t_continue_do_while_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    expect_filename=>$Self->{golden_filename},
+    verilator_flags2=> ['--assert'],
+    fails => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_continue_do_while_bad.v b/test_regress/t/t_continue_do_while_bad.v
new file mode 100644
index 000000000..e1ba1eae9
--- /dev/null
+++ b/test_regress/t/t_continue_do_while_bad.v
@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+
+   function void infinite_loop;
+      do begin
+         continue;
+      end
+      while (1);
+   endfunction
+
+   always @(posedge clk) begin
+      infinite_loop();
+      $stop;
+   end
+endmodule
diff --git a/test_regress/t/t_jumps_do_while.pl b/test_regress/t/t_jumps_do_while.pl
new file mode 100755
index 000000000..c505d6263
--- /dev/null
+++ b/test_regress/t/t_jumps_do_while.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['--assert'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_jumps_do_while.v b/test_regress/t/t_jumps_do_while.v
new file mode 100644
index 000000000..217e46b3e
--- /dev/null
+++ b/test_regress/t/t_jumps_do_while.v
@@ -0,0 +1,173 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+
+   function bit test_1;
+      int iterations = 0;
+      do begin
+         iterations++;
+         break;
+      end
+      while (1);
+      return iterations == 1;
+   endfunction
+
+   function bit test_2;
+      int iterations = 0;
+      do begin
+         break;
+         iterations++;
+      end
+      while (1);
+      return iterations == 0;
+   endfunction
+
+   function bit test_3;
+      do
+         break;
+      while (1);
+      return 1'b1;
+   endfunction
+
+   function bit test_4;
+      int incr = 0;
+      do begin
+         incr++;
+         break;
+         incr++;
+      end
+      while (1);
+      return incr == 1;
+   endfunction
+
+   function bit test_5;
+      int incr = 0;
+      do begin
+         do
+            incr++;
+         while (incr < 9);
+         incr++;
+         break;
+         incr++;
+      end
+      while (1);
+      return incr == 10;
+   endfunction
+
+   function bit test_6;
+      int incr = 0;
+      do begin
+         do begin
+            incr += 1;
+            incr += 2;
+         end
+         while (incr < 9);
+         incr++;
+         break;
+         incr++;
+      end
+      while (1);
+      return incr == 10;
+   endfunction
+
+   function bit test_7;
+      int incr = 0;
+      do begin
+         do begin
+            incr += 1;
+            break;
+            incr += 2;
+         end
+         while (incr < 9);
+         incr++;
+         break;
+         incr++;
+      end
+      while (1);
+      return incr == 2;
+   endfunction
+
+   function bit test_8;
+      int incr = 0;
+      do begin
+         incr++;
+         continue;
+         incr++;
+      end
+      while (0);
+      return incr == 1;
+   endfunction
+
+   function bit test_9;
+      int incr = 0;
+      do begin
+         incr++;
+         continue;
+         incr++;
+      end
+      while (incr < 5);
+      return incr == 5;
+   endfunction
+
+   function bit test_10;
+      do begin
+         continue;
+      end
+      while (0);
+      return 1'b1;
+   endfunction
+
+   function bit test_11;
+      int incr = 0;
+      do begin
+         do
+            incr++;
+         while (0);
+         incr++;
+         continue;
+         incr++;
+      end
+      while (incr < 11);
+      return incr == 12;
+   endfunction
+
+   function bit test_12;
+      int incr = 0;
+      do begin
+         do begin
+            incr++;
+            continue;
+            incr++;
+         end
+         while (0);
+         incr++;
+         continue;
+         incr++;
+      end
+      while (incr < 11);
+      return incr == 12;
+   endfunction
+
+   always @(posedge clk) begin
+      bit [11:0] results = {test_1(), test_2(), test_3(), test_4(), test_5(),
+                            test_6(), test_7(), test_8(), test_9(), test_10(),
+                            test_11(), test_12()};
+
+      if (results == '1) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+      else begin
+         $write("Results: %b\n", results);
+         $stop;
+      end
+   end
+endmodule

From cbf9cc8e5f2d8dce36ec02af71b4c4ca7352b5e0 Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Wed, 9 Nov 2022 12:32:22 +0100
Subject: [PATCH 014/156] Fix return in constructors (#3734)

---
 src/V3LinkJump.cpp                   |  2 +-
 test_regress/t/t_class_new_return.pl | 20 ++++++++++++++++
 test_regress/t/t_class_new_return.v  | 36 ++++++++++++++++++++++++++++
 3 files changed, 57 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_class_new_return.pl
 create mode 100644 test_regress/t/t_class_new_return.v

diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp
index 6e1b6f319..ae38c8fd5 100644
--- a/src/V3LinkJump.cpp
+++ b/src/V3LinkJump.cpp
@@ -234,7 +234,7 @@ private:
             return;
         } else if (!m_ftaskp) {
             nodep->v3error("Return isn't underneath a task or function");
-        } else if (funcp && !nodep->lhsp()) {
+        } else if (funcp && !nodep->lhsp() && !funcp->isConstructor()) {
             nodep->v3error("Return underneath a function should have return value");
         } else if (!funcp && nodep->lhsp()) {
             nodep->v3error("Return underneath a task shouldn't have return value");
diff --git a/test_regress/t/t_class_new_return.pl b/test_regress/t/t_class_new_return.pl
new file mode 100755
index 000000000..bf4e4ce9f
--- /dev/null
+++ b/test_regress/t/t_class_new_return.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile();
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_class_new_return.v b/test_regress/t/t_class_new_return.v
new file mode 100644
index 000000000..2ee65b978
--- /dev/null
+++ b/test_regress/t/t_class_new_return.v
@@ -0,0 +1,36 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+
+   class foo;
+      int a;
+      function new;
+         a = 1;
+         return;
+         a = 2;
+      endfunction
+      function int get_a;
+         return a;
+      endfunction
+   endclass
+
+   foo foo_i;
+   initial foo_i = new;
+
+   always @(posedge clk) begin
+      if (foo_i.get_a() == 1) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+      else
+        $stop;
+   end
+endmodule

From e64295e92b132fffd8842fc98d36453fa6afae51 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 9 Nov 2022 21:45:14 -0500
Subject: [PATCH 015/156] Fix missing UNUSED warnings with --coverage (#3736).

---
 Changes                               |  1 +
 src/V3Coverage.cpp                    | 19 ++++++++++---------
 test_regress/t/t_cover_unused_bad.out |  7 +++++++
 test_regress/t/t_cover_unused_bad.pl  | 20 ++++++++++++++++++++
 test_regress/t/t_cover_unused_bad.v   | 19 +++++++++++++++++++
 5 files changed, 57 insertions(+), 9 deletions(-)
 create mode 100644 test_regress/t/t_cover_unused_bad.out
 create mode 100755 test_regress/t/t_cover_unused_bad.pl
 create mode 100644 test_regress/t/t_cover_unused_bad.v

diff --git a/Changes b/Changes
index ee0c002a2..80280ad36 100644
--- a/Changes
+++ b/Changes
@@ -17,6 +17,7 @@ Verilator 5.003 devel
 * Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd]
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
+* Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
 
 
 Verilator 5.002 2022-10-29
diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp
index 8a5781ddc..5dfb2f878 100644
--- a/src/V3Coverage.cpp
+++ b/src/V3Coverage.cpp
@@ -123,12 +123,13 @@ private:
         m_modp->addStmtsp(declp);
         UINFO(9, "new " << declp << endl);
 
-        AstCoverInc* const incp = new AstCoverInc(fl, declp);
+        AstCoverInc* const incp = new AstCoverInc{fl, declp};
         if (!trace_var_name.empty() && v3Global.opt.traceCoverage()) {
-            AstVar* const varp = new AstVar(incp->fileline(), VVarType::MODULETEMP, trace_var_name,
-                                            incp->findUInt32DType());
+            FileLine* const fl_nowarn = new FileLine{incp->fileline()};
+            fl_nowarn->modifyWarnOff(V3ErrorCode::UNUSEDSIGNAL, true);
+            AstVar* const varp = new AstVar{fl_nowarn, VVarType::MODULETEMP, trace_var_name,
+                                            incp->findUInt32DType()};
             varp->trace(true);
-            varp->fileline()->modifyWarnOff(V3ErrorCode::UNUSEDSIGNAL, true);
             m_modp->addStmtsp(varp);
             UINFO(5, "New coverage trace: " << varp << endl);
             AstAssign* const assp = new AstAssign(
@@ -281,18 +282,18 @@ private:
 
                 // Add signal to hold the old value
                 const string newvarname = std::string{"__Vtogcov__"} + nodep->shortName();
+                FileLine* const fl_nowarn = new FileLine{nodep->fileline()};
+                fl_nowarn->modifyWarnOff(V3ErrorCode::UNUSEDSIGNAL, true);
                 AstVar* const chgVarp
-                    = new AstVar(nodep->fileline(), VVarType::MODULETEMP, newvarname, nodep);
-                chgVarp->fileline()->modifyWarnOff(V3ErrorCode::UNUSEDSIGNAL, true);
+                    = new AstVar{fl_nowarn, VVarType::MODULETEMP, newvarname, nodep};
                 m_modp->addStmtsp(chgVarp);
 
                 // Create bucket for each dimension * bit.
                 // This is necessarily an O(n^2) expansion, which is why
                 // we limit coverage to signals with < 256 bits.
 
-                ToggleEnt newvec{std::string{""},
-                                 new AstVarRef{nodep->fileline(), nodep, VAccess::READ},
-                                 new AstVarRef{nodep->fileline(), chgVarp, VAccess::WRITE}};
+                ToggleEnt newvec{std::string{""}, new AstVarRef{fl_nowarn, nodep, VAccess::READ},
+                                 new AstVarRef{fl_nowarn, chgVarp, VAccess::WRITE}};
                 toggleVarRecurse(nodep->dtypeSkipRefp(), 0, newvec, nodep, chgVarp);
                 newvec.cleanup();
             }
diff --git a/test_regress/t/t_cover_unused_bad.out b/test_regress/t/t_cover_unused_bad.out
new file mode 100644
index 000000000..023d50917
--- /dev/null
+++ b/test_regress/t/t_cover_unused_bad.out
@@ -0,0 +1,7 @@
+%Warning-UNUSEDSIGNAL: t/t_cover_unused_bad.v:14:10: Signal is not used: 'unu3'
+                                                   : ... In instance t
+   14 |    logic unu3 = 0;
+      |          ^~~~
+                       ... For warning description see https://verilator.org/warn/UNUSEDSIGNAL?v=latest
+                       ... Use "/* verilator lint_off UNUSEDSIGNAL */" and lint_on around source to disable this message.
+%Error: Exiting due to
diff --git a/test_regress/t/t_cover_unused_bad.pl b/test_regress/t/t_cover_unused_bad.pl
new file mode 100755
index 000000000..348cfc821
--- /dev/null
+++ b/test_regress/t/t_cover_unused_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ["-Wall -Wno-DECLFILENAME --coverage"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_cover_unused_bad.v b/test_regress/t/t_cover_unused_bad.v
new file mode 100644
index 000000000..c932ff440
--- /dev/null
+++ b/test_regress/t/t_cover_unused_bad.v
@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   logic unu3 = 0;
+
+   logic isusd = 0;
+   cover property (@(posedge clk) isusd == 0);
+
+endmodule

From 207bc2b18a0ed4c8f48083213fc338b209ed2d3a Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Thu, 10 Nov 2022 14:00:14 +0100
Subject: [PATCH 016/156] Fix comment annotation

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---
 include/verilatedos.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/verilatedos.h b/include/verilatedos.h
index 41e74684a..3d755f270 100644
--- a/include/verilatedos.h
+++ b/include/verilatedos.h
@@ -485,7 +485,7 @@ using ssize_t = uint32_t;  ///< signed size_t; returned from read()
 #elif defined(__powerpc64__)
 # define VL_CPU_RELAX() asm volatile("or 1, 1, 1; or 2, 2, 2;" ::: "memory")
 #elif defined(__loongarch__)
-/ LoongArch does not currently have a yield/pause instruction
+// LoongArch does not currently have a yield/pause instruction
 # define VL_CPU_RELAX() asm volatile("nop" ::: "memory")
 #else
 # error "Missing VL_CPU_RELAX() definition."

From 441b5da5ceaca010caf7f288f68897db88a47cfe Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Fri, 11 Nov 2022 00:08:15 +0100
Subject: [PATCH 017/156] Fix 'with' clause handling in functions (#3739)

---
 src/V3LinkDot.cpp                    |  2 +-
 test_regress/t/t_array_query_with.pl | 22 ++++++++++++
 test_regress/t/t_array_query_with.v  | 52 ++++++++++++++++++++++++++++
 3 files changed, 75 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_array_query_with.pl
 create mode 100644 test_regress/t/t_array_query_with.v

diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 6659a4662..0405a38e8 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1731,7 +1731,7 @@ class LinkDotScopeVisitor final : public VNVisitor {
     void visit(AstNodeFTask* nodep) override {
         VSymEnt* const symp = m_statep->insertBlock(m_modSymp, nodep->name(), nodep, nullptr);
         symp->fallbackp(m_modSymp);
-        // No recursion, we don't want to pick up variables
+        iterateChildren(nodep);
     }
     void visit(AstForeach* nodep) override {
         VSymEnt* const symp = m_statep->insertBlock(m_modSymp, nodep->name(), nodep, nullptr);
diff --git a/test_regress/t/t_array_query_with.pl b/test_regress/t/t_array_query_with.pl
new file mode 100755
index 000000000..c505d6263
--- /dev/null
+++ b/test_regress/t/t_array_query_with.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['--assert'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_array_query_with.v b/test_regress/t/t_array_query_with.v
new file mode 100644
index 000000000..423670b00
--- /dev/null
+++ b/test_regress/t/t_array_query_with.v
@@ -0,0 +1,52 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+
+   function bit test_find;
+      string bar[$];
+      string found[$];
+      bar.push_back("baz");
+      bar.push_back("qux");
+      found = bar.find(x) with (x == "baz");
+      return found.size() == 1;
+   endfunction
+
+   function bit test_find_index;
+      int    q[$] = {1, 2, 3, 4};
+      int    found[$] = q.find_index(x) with (x <= 2);
+      return found.size() == 2;
+   endfunction
+
+   function bit test_find_first_index;
+      int    q[] = {1, 2, 3, 4, 5, 6};
+      int    first_even_idx[$] = q.find_first_index(x) with (x % 2 == 0);
+      return first_even_idx[0] == 1;
+   endfunction
+
+   function bit test_sort;
+      int    q[] = {-5, 2, -3, 0, 4};
+      q.sort(x) with (x >= 0 ? x : -x);
+      return q[1] == 2;
+   endfunction
+
+   always @(posedge clk) begin
+      bit [3:0] results = {test_find(), test_find_index(),
+                           test_find_first_index(), test_sort()};
+      if (results == '1) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+      else begin
+         $write("Results: %b\n", results);
+         $stop;
+      end
+   end
+endmodule

From 16586d1d379edca8da9fde2e61b28a2e234ffe84 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 10 Nov 2022 20:30:10 -0500
Subject: [PATCH 018/156] Fix tracing parameters overridden with -G (#3723).

---
 Changes                                      |     1 +
 src/V3LinkDot.cpp                            |    13 +-
 test_regress/t/t_hier_block_sc_trace_fst.out | 11008 +++++++--------
 test_regress/t/t_hier_block_sc_trace_vcd.out | 11810 +++++++++--------
 test_regress/t/t_hier_block_trace_fst.out    | 11008 +++++++--------
 test_regress/t/t_hier_block_trace_vcd.out    | 11810 +++++++++--------
 test_regress/t/t_trace_param_override.out    |    16 +
 test_regress/t/t_trace_param_override.pl     |    25 +
 test_regress/t/t_trace_param_override.v      |    21 +
 9 files changed, 23005 insertions(+), 22707 deletions(-)
 create mode 100644 test_regress/t/t_trace_param_override.out
 create mode 100755 test_regress/t/t_trace_param_override.pl
 create mode 100644 test_regress/t/t_trace_param_override.v

diff --git a/Changes b/Changes
index 80280ad36..d54ef90b1 100644
--- a/Changes
+++ b/Changes
@@ -18,6 +18,7 @@ Verilator 5.003 devel
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
 * Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
+* Fix tracing parameters overridden with -G (#3723). [Iztok Jeras]
 
 
 Verilator 5.002 2022-10-29
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 0405a38e8..011e408b7 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1220,20 +1220,15 @@ class LinkDotFindVisitor final : public VNVisitor {
                     && (m_statep->rootEntp()->nodep() == m_modSymp->parentp()->nodep())) {
                     // This is the toplevel module. Check for command line overwrites of parameters
                     // We first search if the parameter is overwritten and then replace it with a
-                    // new value. It will keep the same FileLine information.
+                    // new value.
                     if (v3Global.opt.hasParameter(nodep->name())) {
-                        AstVar* const newp = new AstVar{
-                            nodep->fileline(), VVarType{VVarType::GPARAM}, nodep->name(), nodep};
-                        newp->combineType(nodep);
                         const string svalue = v3Global.opt.parameter(nodep->name());
                         if (AstNode* const valuep
                             = AstConst::parseParamLiteral(nodep->fileline(), svalue)) {
-                            newp->valuep(valuep);
                             UINFO(9, "       replace parameter " << nodep << endl);
-                            UINFO(9, "       with " << newp << endl);
-                            nodep->replaceWith(newp);
-                            VL_DO_DANGLING(pushDeletep(nodep), nodep);
-                            nodep = newp;
+                            UINFO(9, "       with " << valuep << endl);
+                            if (nodep->valuep()) pushDeletep(nodep->valuep()->unlinkFrBack());
+                            nodep->valuep(valuep);
                         }
                     }
                 }
diff --git a/test_regress/t/t_hier_block_sc_trace_fst.out b/test_regress/t/t_hier_block_sc_trace_fst.out
index 325da4741..0371854fe 100644
--- a/test_regress/t/t_hier_block_sc_trace_fst.out
+++ b/test_regress/t/t_hier_block_sc_trace_fst.out
@@ -1,5 +1,5 @@
 $date
-	Tue Oct 18 17:13:03 2022
+	Thu Nov 10 20:17:06 2022
 
 $end
 $version
@@ -66,49 +66,51 @@ $var wire 1 * clk $end
 $var wire 8 + in [7:0] $end
 $var wire 8 , out [7:0] $end
 $scope module delay_2 $end
-$var parameter 32 - WIDTH [31:0] $end
+$var parameter 32 - N [31:0] $end
+$var parameter 32 . WIDTH [31:0] $end
 $var wire 1 * clk $end
 $var wire 8 + in [7:0] $end
 $var wire 8 , out [7:0] $end
-$var logic 8 . tmp [7:0] $end
+$var logic 8 / tmp [7:0] $end
 $scope module genblk1 $end
 $scope module i_delay $end
-$var parameter 32 / N [31:0] $end
-$var parameter 32 - WIDTH [31:0] $end
+$var parameter 32 0 N [31:0] $end
+$var parameter 32 . WIDTH [31:0] $end
 $var wire 1 * clk $end
-$var wire 8 . in [7:0] $end
+$var wire 8 / in [7:0] $end
 $var wire 8 , out [7:0] $end
-$var logic 8 0 tmp [7:0] $end
+$var logic 8 1 tmp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_delay1 $end
-$var wire 1 1 clk $end
-$var wire 8 2 in [7:0] $end
-$var wire 8 3 out [7:0] $end
+$var wire 1 2 clk $end
+$var wire 8 3 in [7:0] $end
+$var wire 8 4 out [7:0] $end
 $scope module delay_9 $end
-$var parameter 32 4 WIDTH [31:0] $end
-$var wire 1 1 clk $end
-$var wire 8 2 in [7:0] $end
-$var wire 8 3 out [7:0] $end
-$var logic 8 5 tmp [7:0] $end
-$scope module genblk1 $end
-$scope module i_delay $end
-$var parameter 32 6 N [31:0] $end
-$var parameter 32 4 WIDTH [31:0] $end
-$var wire 1 1 clk $end
-$var wire 8 5 in [7:0] $end
-$var wire 8 3 out [7:0] $end
+$var parameter 32 5 N [31:0] $end
+$var parameter 32 6 WIDTH [31:0] $end
+$var wire 1 2 clk $end
+$var wire 8 3 in [7:0] $end
+$var wire 8 4 out [7:0] $end
 $var logic 8 7 tmp [7:0] $end
 $scope module genblk1 $end
 $scope module i_delay $end
 $var parameter 32 8 N [31:0] $end
-$var parameter 32 4 WIDTH [31:0] $end
-$var wire 1 1 clk $end
+$var parameter 32 6 WIDTH [31:0] $end
+$var wire 1 2 clk $end
 $var wire 8 7 in [7:0] $end
-$var wire 8 3 out [7:0] $end
+$var wire 8 4 out [7:0] $end
 $var logic 8 9 tmp [7:0] $end
+$scope module genblk1 $end
+$scope module i_delay $end
+$var parameter 32 : N [31:0] $end
+$var parameter 32 6 WIDTH [31:0] $end
+$var wire 1 2 clk $end
+$var wire 8 9 in [7:0] $end
+$var wire 8 4 out [7:0] $end
+$var logic 8 ; tmp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -116,935 +118,993 @@ $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub0.i_sub0 $end
-$var wire 1 : clk $end
-$var wire 8 ; in [7:0] $end
-$var wire 8 < out [7:0] $end
+$var wire 1 < clk $end
+$var wire 8 = in [7:0] $end
+$var wire 8 > out [7:0] $end
 $scope module sub0 $end
-$var wire 1 : clk $end
-$var wire 8 ; in [7:0] $end
-$var wire 8 < out [7:0] $end
-$var logic 8 = ff [7:0] $end
+$var wire 1 < clk $end
+$var wire 8 = in [7:0] $end
+$var wire 8 > out [7:0] $end
+$var logic 8 ? ff [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub1 $end
-$var wire 1 > clk $end
-$var wire 8 ? in [11:4] $end
-$var wire 8 @ out [7:0] $end
+$var wire 1 @ clk $end
+$var wire 8 A in [11:4] $end
+$var wire 8 B out [7:0] $end
 $scope module sub1 $end
-$var wire 1 > clk $end
-$var wire 8 ? in [11:4] $end
-$var wire 8 @ out [7:0] $end
-$var logic 8 A ff [7:0] $end
+$var wire 1 @ clk $end
+$var wire 8 A in [11:4] $end
+$var wire 8 B out [7:0] $end
+$var logic 8 C ff [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2 $end
-$var wire 1 B clk $end
-$var wire 8 C in [7:0] $end
-$var wire 8 D out [7:0] $end
-$scope module sub2 $end
-$var wire 1 B clk $end
-$var wire 8 C in [7:0] $end
-$var wire 8 D out [7:0] $end
-$var logic 8 E ff [7:0] $end
-$scope module i_sub3 $end
-$var wire 8 E in_wire [7:0] $end
-$var wire 8 F out_1 [7:0] $end
-$var wire 8 G out_2 [7:0] $end
-$scope module i_sub3 $end
-$var wire 1 B clk $end
+$var wire 1 D clk $end
 $var wire 8 E in [7:0] $end
 $var wire 8 F out [7:0] $end
+$scope module sub2 $end
+$var wire 1 D clk $end
+$var wire 8 E in [7:0] $end
+$var wire 8 F out [7:0] $end
+$var logic 8 G ff [7:0] $end
+$scope module i_sub3 $end
+$var wire 8 G in_wire [7:0] $end
+$var wire 8 H out_1 [7:0] $end
+$var wire 8 I out_2 [7:0] $end
+$scope module i_sub3 $end
+$var wire 1 D clk $end
+$var wire 8 G in [7:0] $end
+$var wire 8 H out [7:0] $end
 $upscope $end
 $scope module i_sub3_2 $end
-$var wire 1 B clk $end
-$var wire 8 E in [7:0] $end
-$var wire 8 G out [7:0] $end
+$var wire 1 D clk $end
+$var wire 8 G in [7:0] $end
+$var wire 8 I out [7:0] $end
 $upscope $end
 $scope interface in $end
-$var wire 1 B clk $end
-$var logic 8 E data [7:0] $end
+$var wire 1 D clk $end
+$var logic 8 G data [7:0] $end
 $upscope $end
 $scope interface out $end
-$var wire 1 B clk $end
-$var logic 8 F data [7:0] $end
+$var wire 1 D clk $end
+$var logic 8 H data [7:0] $end
 $upscope $end
 $upscope $end
 $scope interface in_ifs $end
-$var wire 1 B clk $end
-$var logic 8 E data [7:0] $end
+$var wire 1 D clk $end
+$var logic 8 G data [7:0] $end
 $upscope $end
 $scope interface out_ifs $end
-$var wire 1 B clk $end
-$var logic 8 F data [7:0] $end
+$var wire 1 D clk $end
+$var logic 8 H data [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3 $end
-$var wire 1 H clk $end
-$var wire 8 I in [7:0] $end
-$var wire 8 J out [7:0] $end
+$var wire 1 J clk $end
+$var wire 8 K in [7:0] $end
+$var wire 8 L out [7:0] $end
 $scope module sub3_c $end
-$var parameter 32 K UNPACKED_ARRAY[0] [31:0] $end
-$var parameter 32 L UNPACKED_ARRAY[1] [31:0] $end
-$var wire 1 H clk $end
-$var wire 8 I in [7:0] $end
-$var wire 8 J out [7:0] $end
-$var logic 8 M ff [7:0] $end
-$var wire 8 N out4 [7:0] $end
-$var wire 8 O out4_2 [7:0] $end
+$var parameter 8 M P0 [7:0] $end
+$var parameter 32 N UNPACKED_ARRAY[0] [31:0] $end
+$var parameter 32 O UNPACKED_ARRAY[1] [31:0] $end
+$var parameter 16 P UNUSED [15:0] $end
+$var wire 1 J clk $end
+$var wire 8 K in [7:0] $end
+$var wire 8 L out [7:0] $end
+$var logic 8 Q ff [7:0] $end
+$var wire 8 R out4 [7:0] $end
+$var wire 8 S out4_2 [7:0] $end
 $scope module i_sub4_0 $end
-$var wire 1 H clk $end
-$var wire 8 M in [7:0] $end
-$var wire 8 N out [7:0] $end
+$var wire 1 J clk $end
+$var wire 8 Q in [7:0] $end
+$var wire 8 R out [7:0] $end
 $upscope $end
 $scope module i_sub4_1 $end
-$var wire 1 H clk $end
-$var wire 8 M in [7:0] $end
-$var wire 8 O out [7:0] $end
+$var wire 1 J clk $end
+$var wire 8 Q in [7:0] $end
+$var wire 8 S out [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0 $end
-$var wire 1 P clk $end
-$var wire 8 Q in [7:0] $end
-$var wire 8 R out [7:0] $end
+$var wire 1 T clk $end
+$var wire 8 U in [7:0] $end
+$var wire 8 V out [7:0] $end
 $scope module sub4_2 $end
-$var wire 1 P clk $end
-$var wire 8 Q in [7:0] $end
-$var wire 8 R out [7:0] $end
-$var logic 8 S ff [7:0] $end
-$var logic 128 T sub5_in[0][0] [127:0] $end
-$var logic 128 U sub5_in[0][1] [127:0] $end
-$var logic 128 V sub5_in[0][2] [127:0] $end
-$var logic 128 W sub5_in[1][0] [127:0] $end
-$var logic 128 X sub5_in[1][1] [127:0] $end
-$var logic 128 Y sub5_in[1][2] [127:0] $end
-$var wire 8 Z sub5_out[0][0] [7:0] $end
-$var wire 8 [ sub5_out[0][1] [7:0] $end
-$var wire 8 \ sub5_out[0][2] [7:0] $end
-$var wire 8 ] sub5_out[1][0] [7:0] $end
-$var wire 8 ^ sub5_out[1][1] [7:0] $end
-$var wire 8 _ sub5_out[1][2] [7:0] $end
-$var int 32 ` count [31:0] $end
+$var parameter 32 W P0 [31:0] $end
+$var real_parameter 64 X P1 $end
+$var real_parameter 64 Y P3 $end
+$var wire 1 T clk $end
+$var wire 8 U in [7:0] $end
+$var wire 8 V out [7:0] $end
+$var logic 8 Z ff [7:0] $end
+$var logic 128 [ sub5_in[0][0] [127:0] $end
+$var logic 128 \ sub5_in[0][1] [127:0] $end
+$var logic 128 ] sub5_in[0][2] [127:0] $end
+$var logic 128 ^ sub5_in[1][0] [127:0] $end
+$var logic 128 _ sub5_in[1][1] [127:0] $end
+$var logic 128 ` sub5_in[1][2] [127:0] $end
+$var wire 8 a sub5_out[0][0] [7:0] $end
+$var wire 8 b sub5_out[0][1] [7:0] $end
+$var wire 8 c sub5_out[0][2] [7:0] $end
+$var wire 8 d sub5_out[1][0] [7:0] $end
+$var wire 8 e sub5_out[1][1] [7:0] $end
+$var wire 8 f sub5_out[1][2] [7:0] $end
+$var int 32 g count [31:0] $end
 $scope module i_sub5 $end
-$var wire 1 P clk $end
-$var wire 128 a in[0][0] [127:0] $end
-$var wire 128 b in[0][1] [127:0] $end
-$var wire 128 c in[0][2] [127:0] $end
-$var wire 128 d in[1][0] [127:0] $end
-$var wire 128 e in[1][1] [127:0] $end
-$var wire 128 f in[1][2] [127:0] $end
-$var wire 8 g out[0][0] [7:0] $end
-$var wire 8 h out[0][1] [7:0] $end
-$var wire 8 i out[0][2] [7:0] $end
-$var wire 8 j out[1][0] [7:0] $end
-$var wire 8 k out[1][1] [7:0] $end
-$var wire 8 l out[1][2] [7:0] $end
+$var wire 1 T clk $end
+$var wire 128 h in[0][0] [127:0] $end
+$var wire 128 i in[0][1] [127:0] $end
+$var wire 128 j in[0][2] [127:0] $end
+$var wire 128 k in[1][0] [127:0] $end
+$var wire 128 l in[1][1] [127:0] $end
+$var wire 128 m in[1][2] [127:0] $end
+$var wire 8 n out[0][0] [7:0] $end
+$var wire 8 o out[0][1] [7:0] $end
+$var wire 8 p out[0][2] [7:0] $end
+$var wire 8 q out[1][0] [7:0] $end
+$var wire 8 r out[1][1] [7:0] $end
+$var wire 8 s out[1][2] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 m i [31:0] $end
+$var int 32 t i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 n j [31:0] $end
+$var int 32 u j [31:0] $end
 $scope module unnamedblk3 $end
-$var byte 8 o exp [7:0] $end
+$var byte 8 v exp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5 $end
-$var wire 1 p clk $end
-$var wire 128 q in[0][0] [127:0] $end
-$var wire 128 r in[0][1] [127:0] $end
-$var wire 128 s in[0][2] [127:0] $end
-$var wire 128 t in[1][0] [127:0] $end
-$var wire 128 u in[1][1] [127:0] $end
-$var wire 128 v in[1][2] [127:0] $end
-$var wire 8 w out[0][0] [7:0] $end
-$var wire 8 x out[0][1] [7:0] $end
-$var wire 8 y out[0][2] [7:0] $end
-$var wire 8 z out[1][0] [7:0] $end
-$var wire 8 { out[1][1] [7:0] $end
-$var wire 8 | out[1][2] [7:0] $end
+$var wire 1 w clk $end
+$var wire 128 x in[0][0] [127:0] $end
+$var wire 128 y in[0][1] [127:0] $end
+$var wire 128 z in[0][2] [127:0] $end
+$var wire 128 { in[1][0] [127:0] $end
+$var wire 128 | in[1][1] [127:0] $end
+$var wire 128 } in[1][2] [127:0] $end
+$var wire 8 ~ out[0][0] [7:0] $end
+$var wire 8 !! out[0][1] [7:0] $end
+$var wire 8 "! out[0][2] [7:0] $end
+$var wire 8 #! out[1][0] [7:0] $end
+$var wire 8 $! out[1][1] [7:0] $end
+$var wire 8 %! out[1][2] [7:0] $end
 $scope module sub5 $end
-$var wire 1 p clk $end
-$var wire 128 q in[0][0] [127:0] $end
-$var wire 128 r in[0][1] [127:0] $end
-$var wire 128 s in[0][2] [127:0] $end
-$var wire 128 t in[1][0] [127:0] $end
-$var wire 128 u in[1][1] [127:0] $end
-$var wire 128 v in[1][2] [127:0] $end
-$var wire 8 w out[0][0] [7:0] $end
-$var wire 8 x out[0][1] [7:0] $end
-$var wire 8 y out[0][2] [7:0] $end
-$var wire 8 z out[1][0] [7:0] $end
-$var wire 8 { out[1][1] [7:0] $end
-$var wire 8 | out[1][2] [7:0] $end
-$var int 32 } count [31:0] $end
-$var wire 8 ~ val0[0] [7:0] $end
-$var wire 8 !! val0[1] [7:0] $end
-$var wire 8 "! val1[0] [7:0] $end
-$var wire 8 #! val1[1] [7:0] $end
-$var wire 8 $! val2[0] [7:0] $end
-$var wire 8 %! val2[1] [7:0] $end
-$var wire 8 &! val3[0] [7:0] $end
-$var wire 8 '! val3[1] [7:0] $end
+$var wire 1 w clk $end
+$var wire 128 x in[0][0] [127:0] $end
+$var wire 128 y in[0][1] [127:0] $end
+$var wire 128 z in[0][2] [127:0] $end
+$var wire 128 { in[1][0] [127:0] $end
+$var wire 128 | in[1][1] [127:0] $end
+$var wire 128 } in[1][2] [127:0] $end
+$var wire 8 ~ out[0][0] [7:0] $end
+$var wire 8 !! out[0][1] [7:0] $end
+$var wire 8 "! out[0][2] [7:0] $end
+$var wire 8 #! out[1][0] [7:0] $end
+$var wire 8 $! out[1][1] [7:0] $end
+$var wire 8 %! out[1][2] [7:0] $end
+$var int 32 &! count [31:0] $end
+$var wire 8 '! val0[0] [7:0] $end
+$var wire 8 (! val0[1] [7:0] $end
+$var wire 8 )! val1[0] [7:0] $end
+$var wire 8 *! val1[1] [7:0] $end
+$var wire 8 +! val2[0] [7:0] $end
+$var wire 8 ,! val2[1] [7:0] $end
+$var wire 8 -! val3[0] [7:0] $end
+$var wire 8 .! val3[1] [7:0] $end
 $scope module i_sub0 $end
-$var parameter 32 (! P0 [31:0] $end
-$var parameter 32 )! P1 [31:0] $end
-$var wire 8 *! out[0] [7:0] $end
-$var wire 8 +! out[1] [7:0] $end
+$var parameter 32 /! P0 [31:0] $end
+$var parameter 32 0! P1 [31:0] $end
+$var wire 8 1! out[0] [7:0] $end
+$var wire 8 2! out[1] [7:0] $end
 $upscope $end
 $scope module i_sub1 $end
-$var parameter 32 (! P0 [31:0] $end
-$var parameter 32 )! P1 [31:0] $end
-$var wire 8 ,! out[0] [7:0] $end
-$var wire 8 -! out[1] [7:0] $end
+$var parameter 32 /! P0 [31:0] $end
+$var parameter 32 0! P1 [31:0] $end
+$var wire 8 3! out[0] [7:0] $end
+$var wire 8 4! out[1] [7:0] $end
 $upscope $end
 $scope module i_sub2 $end
-$var parameter 32 (! P0 [31:0] $end
-$var parameter 32 )! P1 [31:0] $end
-$var wire 8 .! out[0] [7:0] $end
-$var wire 8 /! out[1] [7:0] $end
+$var parameter 32 /! P0 [31:0] $end
+$var parameter 32 0! P1 [31:0] $end
+$var wire 8 5! out[0] [7:0] $end
+$var wire 8 6! out[1] [7:0] $end
 $upscope $end
 $scope module i_sub3 $end
-$var wire 8 0! out[0] [7:0] $end
-$var wire 8 1! out[1] [7:0] $end
+$var wire 8 7! out[0] [7:0] $end
+$var wire 8 8! out[1] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 2! i [31:0] $end
+$var int 32 9! i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 3! j [31:0] $end
+$var int 32 :! j [31:0] $end
 $scope module unnamedblk3 $end
-$var bit 128 4! exp [127:0] $end
+$var bit 128 ;! exp [127:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end
-$var wire 8 5! out[0] [7:0] $end
-$var wire 8 6! out[1] [7:0] $end
+$var wire 8 <! out[0] [7:0] $end
+$var wire 8 =! out[1] [7:0] $end
 $scope module sub6_9 $end
-$var parameter 32 7! P0 [31:0] $end
-$var wire 8 5! out[0] [7:0] $end
-$var wire 8 6! out[1] [7:0] $end
+$var parameter 32 >! P0 [31:0] $end
+$var parameter 32 ?! P1 [31:0] $end
+$var wire 8 <! out[0] [7:0] $end
+$var wire 8 =! out[1] [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1 $end
-$var wire 1 8! clk $end
-$var wire 8 9! in [7:0] $end
-$var wire 8 :! out [7:0] $end
+$var wire 1 @! clk $end
+$var wire 8 A! in [7:0] $end
+$var wire 8 B! out [7:0] $end
 $scope module sub4_b $end
-$var wire 1 8! clk $end
-$var wire 8 9! in [7:0] $end
-$var wire 8 :! out [7:0] $end
-$var logic 8 ;! ff [7:0] $end
-$var logic 128 <! sub5_in[0][0] [127:0] $end
-$var logic 128 =! sub5_in[0][1] [127:0] $end
-$var logic 128 >! sub5_in[0][2] [127:0] $end
-$var logic 128 ?! sub5_in[1][0] [127:0] $end
-$var logic 128 @! sub5_in[1][1] [127:0] $end
-$var logic 128 A! sub5_in[1][2] [127:0] $end
-$var wire 8 B! sub5_out[0][0] [7:0] $end
-$var wire 8 C! sub5_out[0][1] [7:0] $end
-$var wire 8 D! sub5_out[0][2] [7:0] $end
-$var wire 8 E! sub5_out[1][0] [7:0] $end
-$var wire 8 F! sub5_out[1][1] [7:0] $end
-$var wire 8 G! sub5_out[1][2] [7:0] $end
-$var int 32 H! count [31:0] $end
+$var parameter 32 C! P0 [31:0] $end
+$var real_parameter 64 D! P1 $end
+$var real_parameter 64 E! P3 $end
+$var wire 1 @! clk $end
+$var wire 8 A! in [7:0] $end
+$var wire 8 B! out [7:0] $end
+$var logic 8 F! ff [7:0] $end
+$var logic 128 G! sub5_in[0][0] [127:0] $end
+$var logic 128 H! sub5_in[0][1] [127:0] $end
+$var logic 128 I! sub5_in[0][2] [127:0] $end
+$var logic 128 J! sub5_in[1][0] [127:0] $end
+$var logic 128 K! sub5_in[1][1] [127:0] $end
+$var logic 128 L! sub5_in[1][2] [127:0] $end
+$var wire 8 M! sub5_out[0][0] [7:0] $end
+$var wire 8 N! sub5_out[0][1] [7:0] $end
+$var wire 8 O! sub5_out[0][2] [7:0] $end
+$var wire 8 P! sub5_out[1][0] [7:0] $end
+$var wire 8 Q! sub5_out[1][1] [7:0] $end
+$var wire 8 R! sub5_out[1][2] [7:0] $end
+$var int 32 S! count [31:0] $end
 $scope module i_sub5 $end
-$var wire 1 8! clk $end
-$var wire 128 I! in[0][0] [127:0] $end
-$var wire 128 J! in[0][1] [127:0] $end
-$var wire 128 K! in[0][2] [127:0] $end
-$var wire 128 L! in[1][0] [127:0] $end
-$var wire 128 M! in[1][1] [127:0] $end
-$var wire 128 N! in[1][2] [127:0] $end
-$var wire 8 O! out[0][0] [7:0] $end
-$var wire 8 P! out[0][1] [7:0] $end
-$var wire 8 Q! out[0][2] [7:0] $end
-$var wire 8 R! out[1][0] [7:0] $end
-$var wire 8 S! out[1][1] [7:0] $end
-$var wire 8 T! out[1][2] [7:0] $end
+$var wire 1 @! clk $end
+$var wire 128 T! in[0][0] [127:0] $end
+$var wire 128 U! in[0][1] [127:0] $end
+$var wire 128 V! in[0][2] [127:0] $end
+$var wire 128 W! in[1][0] [127:0] $end
+$var wire 128 X! in[1][1] [127:0] $end
+$var wire 128 Y! in[1][2] [127:0] $end
+$var wire 8 Z! out[0][0] [7:0] $end
+$var wire 8 [! out[0][1] [7:0] $end
+$var wire 8 \! out[0][2] [7:0] $end
+$var wire 8 ]! out[1][0] [7:0] $end
+$var wire 8 ^! out[1][1] [7:0] $end
+$var wire 8 _! out[1][2] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 U! i [31:0] $end
+$var int 32 `! i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 V! j [31:0] $end
+$var int 32 a! j [31:0] $end
 $scope module unnamedblk3 $end
-$var byte 8 W! exp [7:0] $end
+$var byte 8 b! exp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5 $end
-$var wire 1 X! clk $end
-$var wire 128 Y! in[0][0] [127:0] $end
-$var wire 128 Z! in[0][1] [127:0] $end
-$var wire 128 [! in[0][2] [127:0] $end
-$var wire 128 \! in[1][0] [127:0] $end
-$var wire 128 ]! in[1][1] [127:0] $end
-$var wire 128 ^! in[1][2] [127:0] $end
-$var wire 8 _! out[0][0] [7:0] $end
-$var wire 8 `! out[0][1] [7:0] $end
-$var wire 8 a! out[0][2] [7:0] $end
-$var wire 8 b! out[1][0] [7:0] $end
-$var wire 8 c! out[1][1] [7:0] $end
-$var wire 8 d! out[1][2] [7:0] $end
+$var wire 1 c! clk $end
+$var wire 128 d! in[0][0] [127:0] $end
+$var wire 128 e! in[0][1] [127:0] $end
+$var wire 128 f! in[0][2] [127:0] $end
+$var wire 128 g! in[1][0] [127:0] $end
+$var wire 128 h! in[1][1] [127:0] $end
+$var wire 128 i! in[1][2] [127:0] $end
+$var wire 8 j! out[0][0] [7:0] $end
+$var wire 8 k! out[0][1] [7:0] $end
+$var wire 8 l! out[0][2] [7:0] $end
+$var wire 8 m! out[1][0] [7:0] $end
+$var wire 8 n! out[1][1] [7:0] $end
+$var wire 8 o! out[1][2] [7:0] $end
 $scope module sub5 $end
-$var wire 1 X! clk $end
-$var wire 128 Y! in[0][0] [127:0] $end
-$var wire 128 Z! in[0][1] [127:0] $end
-$var wire 128 [! in[0][2] [127:0] $end
-$var wire 128 \! in[1][0] [127:0] $end
-$var wire 128 ]! in[1][1] [127:0] $end
-$var wire 128 ^! in[1][2] [127:0] $end
-$var wire 8 _! out[0][0] [7:0] $end
-$var wire 8 `! out[0][1] [7:0] $end
-$var wire 8 a! out[0][2] [7:0] $end
-$var wire 8 b! out[1][0] [7:0] $end
-$var wire 8 c! out[1][1] [7:0] $end
-$var wire 8 d! out[1][2] [7:0] $end
-$var int 32 e! count [31:0] $end
-$var wire 8 f! val0[0] [7:0] $end
-$var wire 8 g! val0[1] [7:0] $end
-$var wire 8 h! val1[0] [7:0] $end
-$var wire 8 i! val1[1] [7:0] $end
-$var wire 8 j! val2[0] [7:0] $end
-$var wire 8 k! val2[1] [7:0] $end
-$var wire 8 l! val3[0] [7:0] $end
-$var wire 8 m! val3[1] [7:0] $end
+$var wire 1 c! clk $end
+$var wire 128 d! in[0][0] [127:0] $end
+$var wire 128 e! in[0][1] [127:0] $end
+$var wire 128 f! in[0][2] [127:0] $end
+$var wire 128 g! in[1][0] [127:0] $end
+$var wire 128 h! in[1][1] [127:0] $end
+$var wire 128 i! in[1][2] [127:0] $end
+$var wire 8 j! out[0][0] [7:0] $end
+$var wire 8 k! out[0][1] [7:0] $end
+$var wire 8 l! out[0][2] [7:0] $end
+$var wire 8 m! out[1][0] [7:0] $end
+$var wire 8 n! out[1][1] [7:0] $end
+$var wire 8 o! out[1][2] [7:0] $end
+$var int 32 p! count [31:0] $end
+$var wire 8 q! val0[0] [7:0] $end
+$var wire 8 r! val0[1] [7:0] $end
+$var wire 8 s! val1[0] [7:0] $end
+$var wire 8 t! val1[1] [7:0] $end
+$var wire 8 u! val2[0] [7:0] $end
+$var wire 8 v! val2[1] [7:0] $end
+$var wire 8 w! val3[0] [7:0] $end
+$var wire 8 x! val3[1] [7:0] $end
 $scope module i_sub0 $end
-$var parameter 32 n! P0 [31:0] $end
-$var parameter 32 o! P1 [31:0] $end
-$var wire 8 p! out[0] [7:0] $end
-$var wire 8 q! out[1] [7:0] $end
+$var parameter 32 y! P0 [31:0] $end
+$var parameter 32 z! P1 [31:0] $end
+$var wire 8 {! out[0] [7:0] $end
+$var wire 8 |! out[1] [7:0] $end
 $upscope $end
 $scope module i_sub1 $end
-$var parameter 32 n! P0 [31:0] $end
-$var parameter 32 o! P1 [31:0] $end
-$var wire 8 r! out[0] [7:0] $end
-$var wire 8 s! out[1] [7:0] $end
+$var parameter 32 y! P0 [31:0] $end
+$var parameter 32 z! P1 [31:0] $end
+$var wire 8 }! out[0] [7:0] $end
+$var wire 8 ~! out[1] [7:0] $end
 $upscope $end
 $scope module i_sub2 $end
-$var parameter 32 n! P0 [31:0] $end
-$var parameter 32 o! P1 [31:0] $end
-$var wire 8 t! out[0] [7:0] $end
-$var wire 8 u! out[1] [7:0] $end
+$var parameter 32 y! P0 [31:0] $end
+$var parameter 32 z! P1 [31:0] $end
+$var wire 8 !" out[0] [7:0] $end
+$var wire 8 "" out[1] [7:0] $end
 $upscope $end
 $scope module i_sub3 $end
-$var wire 8 v! out[0] [7:0] $end
-$var wire 8 w! out[1] [7:0] $end
+$var wire 8 #" out[0] [7:0] $end
+$var wire 8 $" out[1] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 x! i [31:0] $end
+$var int 32 %" i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 y! j [31:0] $end
+$var int 32 &" j [31:0] $end
 $scope module unnamedblk3 $end
-$var bit 128 z! exp [127:0] $end
+$var bit 128 '" exp [127:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end
-$var wire 8 {! out[0] [7:0] $end
-$var wire 8 |! out[1] [7:0] $end
+$var wire 8 (" out[0] [7:0] $end
+$var wire 8 )" out[1] [7:0] $end
 $scope module sub6_9 $end
-$var parameter 32 }! P0 [31:0] $end
-$var wire 8 {! out[0] [7:0] $end
-$var wire 8 |! out[1] [7:0] $end
+$var parameter 32 *" P0 [31:0] $end
+$var parameter 32 +" P1 [31:0] $end
+$var wire 8 (" out[0] [7:0] $end
+$var wire 8 )" out[1] [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2 $end
-$var wire 1 ~! clk $end
-$var wire 8 !" in [7:0] $end
-$var wire 8 "" out [7:0] $end
+$var wire 1 ," clk $end
+$var wire 8 -" in [7:0] $end
+$var wire 8 ." out [7:0] $end
 $scope module sub3_2 $end
-$var parameter 32 #" UNPACKED_ARRAY[0] [31:0] $end
-$var parameter 32 $" UNPACKED_ARRAY[1] [31:0] $end
-$var parameter 16 %" UNUSED [15:0] $end
-$var wire 1 ~! clk $end
-$var wire 8 !" in [7:0] $end
-$var wire 8 "" out [7:0] $end
-$var logic 8 &" ff [7:0] $end
-$var wire 8 '" out4 [7:0] $end
-$var wire 8 (" out4_2 [7:0] $end
+$var parameter 8 /" P0 [7:0] $end
+$var parameter 32 0" UNPACKED_ARRAY[0] [31:0] $end
+$var parameter 32 1" UNPACKED_ARRAY[1] [31:0] $end
+$var parameter 16 2" UNUSED [15:0] $end
+$var wire 1 ," clk $end
+$var wire 8 -" in [7:0] $end
+$var wire 8 ." out [7:0] $end
+$var logic 8 3" ff [7:0] $end
+$var wire 8 4" out4 [7:0] $end
+$var wire 8 5" out4_2 [7:0] $end
 $scope module i_sub4_0 $end
-$var wire 1 ~! clk $end
-$var wire 8 &" in [7:0] $end
-$var wire 8 '" out [7:0] $end
+$var wire 1 ," clk $end
+$var wire 8 3" in [7:0] $end
+$var wire 8 4" out [7:0] $end
 $upscope $end
 $scope module i_sub4_1 $end
-$var wire 1 ~! clk $end
-$var wire 8 &" in [7:0] $end
-$var wire 8 (" out [7:0] $end
+$var wire 1 ," clk $end
+$var wire 8 3" in [7:0] $end
+$var wire 8 5" out [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2.sub3_2.i_sub4_0 $end
-$var wire 1 )" clk $end
-$var wire 8 *" in [7:0] $end
-$var wire 8 +" out [7:0] $end
+$var wire 1 6" clk $end
+$var wire 8 7" in [7:0] $end
+$var wire 8 8" out [7:0] $end
 $scope module sub4_2 $end
-$var wire 1 )" clk $end
-$var wire 8 *" in [7:0] $end
-$var wire 8 +" out [7:0] $end
-$var logic 8 ," ff [7:0] $end
-$var logic 128 -" sub5_in[0][0] [127:0] $end
-$var logic 128 ." sub5_in[0][1] [127:0] $end
-$var logic 128 /" sub5_in[0][2] [127:0] $end
-$var logic 128 0" sub5_in[1][0] [127:0] $end
-$var logic 128 1" sub5_in[1][1] [127:0] $end
-$var logic 128 2" sub5_in[1][2] [127:0] $end
-$var wire 8 3" sub5_out[0][0] [7:0] $end
-$var wire 8 4" sub5_out[0][1] [7:0] $end
-$var wire 8 5" sub5_out[0][2] [7:0] $end
-$var wire 8 6" sub5_out[1][0] [7:0] $end
-$var wire 8 7" sub5_out[1][1] [7:0] $end
-$var wire 8 8" sub5_out[1][2] [7:0] $end
-$var int 32 9" count [31:0] $end
+$var parameter 32 9" P0 [31:0] $end
+$var real_parameter 64 :" P1 $end
+$var real_parameter 64 ;" P3 $end
+$var wire 1 6" clk $end
+$var wire 8 7" in [7:0] $end
+$var wire 8 8" out [7:0] $end
+$var logic 8 <" ff [7:0] $end
+$var logic 128 =" sub5_in[0][0] [127:0] $end
+$var logic 128 >" sub5_in[0][1] [127:0] $end
+$var logic 128 ?" sub5_in[0][2] [127:0] $end
+$var logic 128 @" sub5_in[1][0] [127:0] $end
+$var logic 128 A" sub5_in[1][1] [127:0] $end
+$var logic 128 B" sub5_in[1][2] [127:0] $end
+$var wire 8 C" sub5_out[0][0] [7:0] $end
+$var wire 8 D" sub5_out[0][1] [7:0] $end
+$var wire 8 E" sub5_out[0][2] [7:0] $end
+$var wire 8 F" sub5_out[1][0] [7:0] $end
+$var wire 8 G" sub5_out[1][1] [7:0] $end
+$var wire 8 H" sub5_out[1][2] [7:0] $end
+$var int 32 I" count [31:0] $end
 $scope module i_sub5 $end
-$var wire 1 )" clk $end
-$var wire 128 :" in[0][0] [127:0] $end
-$var wire 128 ;" in[0][1] [127:0] $end
-$var wire 128 <" in[0][2] [127:0] $end
-$var wire 128 =" in[1][0] [127:0] $end
-$var wire 128 >" in[1][1] [127:0] $end
-$var wire 128 ?" in[1][2] [127:0] $end
-$var wire 8 @" out[0][0] [7:0] $end
-$var wire 8 A" out[0][1] [7:0] $end
-$var wire 8 B" out[0][2] [7:0] $end
-$var wire 8 C" out[1][0] [7:0] $end
-$var wire 8 D" out[1][1] [7:0] $end
-$var wire 8 E" out[1][2] [7:0] $end
+$var wire 1 6" clk $end
+$var wire 128 J" in[0][0] [127:0] $end
+$var wire 128 K" in[0][1] [127:0] $end
+$var wire 128 L" in[0][2] [127:0] $end
+$var wire 128 M" in[1][0] [127:0] $end
+$var wire 128 N" in[1][1] [127:0] $end
+$var wire 128 O" in[1][2] [127:0] $end
+$var wire 8 P" out[0][0] [7:0] $end
+$var wire 8 Q" out[0][1] [7:0] $end
+$var wire 8 R" out[0][2] [7:0] $end
+$var wire 8 S" out[1][0] [7:0] $end
+$var wire 8 T" out[1][1] [7:0] $end
+$var wire 8 U" out[1][2] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 F" i [31:0] $end
+$var int 32 V" i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 G" j [31:0] $end
+$var int 32 W" j [31:0] $end
 $scope module unnamedblk3 $end
-$var byte 8 H" exp [7:0] $end
+$var byte 8 X" exp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5 $end
-$var wire 1 I" clk $end
-$var wire 128 J" in[0][0] [127:0] $end
-$var wire 128 K" in[0][1] [127:0] $end
-$var wire 128 L" in[0][2] [127:0] $end
-$var wire 128 M" in[1][0] [127:0] $end
-$var wire 128 N" in[1][1] [127:0] $end
-$var wire 128 O" in[1][2] [127:0] $end
-$var wire 8 P" out[0][0] [7:0] $end
-$var wire 8 Q" out[0][1] [7:0] $end
-$var wire 8 R" out[0][2] [7:0] $end
-$var wire 8 S" out[1][0] [7:0] $end
-$var wire 8 T" out[1][1] [7:0] $end
-$var wire 8 U" out[1][2] [7:0] $end
+$var wire 1 Y" clk $end
+$var wire 128 Z" in[0][0] [127:0] $end
+$var wire 128 [" in[0][1] [127:0] $end
+$var wire 128 \" in[0][2] [127:0] $end
+$var wire 128 ]" in[1][0] [127:0] $end
+$var wire 128 ^" in[1][1] [127:0] $end
+$var wire 128 _" in[1][2] [127:0] $end
+$var wire 8 `" out[0][0] [7:0] $end
+$var wire 8 a" out[0][1] [7:0] $end
+$var wire 8 b" out[0][2] [7:0] $end
+$var wire 8 c" out[1][0] [7:0] $end
+$var wire 8 d" out[1][1] [7:0] $end
+$var wire 8 e" out[1][2] [7:0] $end
 $scope module sub5 $end
-$var wire 1 I" clk $end
-$var wire 128 J" in[0][0] [127:0] $end
-$var wire 128 K" in[0][1] [127:0] $end
-$var wire 128 L" in[0][2] [127:0] $end
-$var wire 128 M" in[1][0] [127:0] $end
-$var wire 128 N" in[1][1] [127:0] $end
-$var wire 128 O" in[1][2] [127:0] $end
-$var wire 8 P" out[0][0] [7:0] $end
-$var wire 8 Q" out[0][1] [7:0] $end
-$var wire 8 R" out[0][2] [7:0] $end
-$var wire 8 S" out[1][0] [7:0] $end
-$var wire 8 T" out[1][1] [7:0] $end
-$var wire 8 U" out[1][2] [7:0] $end
-$var int 32 V" count [31:0] $end
-$var wire 8 W" val0[0] [7:0] $end
-$var wire 8 X" val0[1] [7:0] $end
-$var wire 8 Y" val1[0] [7:0] $end
-$var wire 8 Z" val1[1] [7:0] $end
-$var wire 8 [" val2[0] [7:0] $end
-$var wire 8 \" val2[1] [7:0] $end
-$var wire 8 ]" val3[0] [7:0] $end
-$var wire 8 ^" val3[1] [7:0] $end
+$var wire 1 Y" clk $end
+$var wire 128 Z" in[0][0] [127:0] $end
+$var wire 128 [" in[0][1] [127:0] $end
+$var wire 128 \" in[0][2] [127:0] $end
+$var wire 128 ]" in[1][0] [127:0] $end
+$var wire 128 ^" in[1][1] [127:0] $end
+$var wire 128 _" in[1][2] [127:0] $end
+$var wire 8 `" out[0][0] [7:0] $end
+$var wire 8 a" out[0][1] [7:0] $end
+$var wire 8 b" out[0][2] [7:0] $end
+$var wire 8 c" out[1][0] [7:0] $end
+$var wire 8 d" out[1][1] [7:0] $end
+$var wire 8 e" out[1][2] [7:0] $end
+$var int 32 f" count [31:0] $end
+$var wire 8 g" val0[0] [7:0] $end
+$var wire 8 h" val0[1] [7:0] $end
+$var wire 8 i" val1[0] [7:0] $end
+$var wire 8 j" val1[1] [7:0] $end
+$var wire 8 k" val2[0] [7:0] $end
+$var wire 8 l" val2[1] [7:0] $end
+$var wire 8 m" val3[0] [7:0] $end
+$var wire 8 n" val3[1] [7:0] $end
 $scope module i_sub0 $end
-$var parameter 32 _" P0 [31:0] $end
-$var parameter 32 `" P1 [31:0] $end
-$var wire 8 a" out[0] [7:0] $end
-$var wire 8 b" out[1] [7:0] $end
+$var parameter 32 o" P0 [31:0] $end
+$var parameter 32 p" P1 [31:0] $end
+$var wire 8 q" out[0] [7:0] $end
+$var wire 8 r" out[1] [7:0] $end
 $upscope $end
 $scope module i_sub1 $end
-$var parameter 32 _" P0 [31:0] $end
-$var parameter 32 `" P1 [31:0] $end
-$var wire 8 c" out[0] [7:0] $end
-$var wire 8 d" out[1] [7:0] $end
+$var parameter 32 o" P0 [31:0] $end
+$var parameter 32 p" P1 [31:0] $end
+$var wire 8 s" out[0] [7:0] $end
+$var wire 8 t" out[1] [7:0] $end
 $upscope $end
 $scope module i_sub2 $end
-$var parameter 32 _" P0 [31:0] $end
-$var parameter 32 `" P1 [31:0] $end
-$var wire 8 e" out[0] [7:0] $end
-$var wire 8 f" out[1] [7:0] $end
+$var parameter 32 o" P0 [31:0] $end
+$var parameter 32 p" P1 [31:0] $end
+$var wire 8 u" out[0] [7:0] $end
+$var wire 8 v" out[1] [7:0] $end
 $upscope $end
 $scope module i_sub3 $end
-$var wire 8 g" out[0] [7:0] $end
-$var wire 8 h" out[1] [7:0] $end
+$var wire 8 w" out[0] [7:0] $end
+$var wire 8 x" out[1] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 i" i [31:0] $end
+$var int 32 y" i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 j" j [31:0] $end
+$var int 32 z" j [31:0] $end
 $scope module unnamedblk3 $end
-$var bit 128 k" exp [127:0] $end
+$var bit 128 {" exp [127:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end
-$var wire 8 l" out[0] [7:0] $end
-$var wire 8 m" out[1] [7:0] $end
+$var wire 8 |" out[0] [7:0] $end
+$var wire 8 }" out[1] [7:0] $end
 $scope module sub6_9 $end
-$var parameter 32 n" P0 [31:0] $end
-$var wire 8 l" out[0] [7:0] $end
-$var wire 8 m" out[1] [7:0] $end
+$var parameter 32 ~" P0 [31:0] $end
+$var parameter 32 !# P1 [31:0] $end
+$var wire 8 |" out[0] [7:0] $end
+$var wire 8 }" out[1] [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2.sub3_2.i_sub4_1 $end
-$var wire 1 o" clk $end
-$var wire 8 p" in [7:0] $end
-$var wire 8 q" out [7:0] $end
+$var wire 1 "# clk $end
+$var wire 8 ## in [7:0] $end
+$var wire 8 $# out [7:0] $end
 $scope module sub4_b $end
-$var wire 1 o" clk $end
-$var wire 8 p" in [7:0] $end
-$var wire 8 q" out [7:0] $end
-$var logic 8 r" ff [7:0] $end
-$var logic 128 s" sub5_in[0][0] [127:0] $end
-$var logic 128 t" sub5_in[0][1] [127:0] $end
-$var logic 128 u" sub5_in[0][2] [127:0] $end
-$var logic 128 v" sub5_in[1][0] [127:0] $end
-$var logic 128 w" sub5_in[1][1] [127:0] $end
-$var logic 128 x" sub5_in[1][2] [127:0] $end
-$var wire 8 y" sub5_out[0][0] [7:0] $end
-$var wire 8 z" sub5_out[0][1] [7:0] $end
-$var wire 8 {" sub5_out[0][2] [7:0] $end
-$var wire 8 |" sub5_out[1][0] [7:0] $end
-$var wire 8 }" sub5_out[1][1] [7:0] $end
-$var wire 8 ~" sub5_out[1][2] [7:0] $end
-$var int 32 !# count [31:0] $end
+$var parameter 32 %# P0 [31:0] $end
+$var real_parameter 64 &# P1 $end
+$var real_parameter 64 '# P3 $end
+$var wire 1 "# clk $end
+$var wire 8 ## in [7:0] $end
+$var wire 8 $# out [7:0] $end
+$var logic 8 (# ff [7:0] $end
+$var logic 128 )# sub5_in[0][0] [127:0] $end
+$var logic 128 *# sub5_in[0][1] [127:0] $end
+$var logic 128 +# sub5_in[0][2] [127:0] $end
+$var logic 128 ,# sub5_in[1][0] [127:0] $end
+$var logic 128 -# sub5_in[1][1] [127:0] $end
+$var logic 128 .# sub5_in[1][2] [127:0] $end
+$var wire 8 /# sub5_out[0][0] [7:0] $end
+$var wire 8 0# sub5_out[0][1] [7:0] $end
+$var wire 8 1# sub5_out[0][2] [7:0] $end
+$var wire 8 2# sub5_out[1][0] [7:0] $end
+$var wire 8 3# sub5_out[1][1] [7:0] $end
+$var wire 8 4# sub5_out[1][2] [7:0] $end
+$var int 32 5# count [31:0] $end
 $scope module i_sub5 $end
-$var wire 1 o" clk $end
-$var wire 128 "# in[0][0] [127:0] $end
-$var wire 128 ## in[0][1] [127:0] $end
-$var wire 128 $# in[0][2] [127:0] $end
-$var wire 128 %# in[1][0] [127:0] $end
-$var wire 128 &# in[1][1] [127:0] $end
-$var wire 128 '# in[1][2] [127:0] $end
-$var wire 8 (# out[0][0] [7:0] $end
-$var wire 8 )# out[0][1] [7:0] $end
-$var wire 8 *# out[0][2] [7:0] $end
-$var wire 8 +# out[1][0] [7:0] $end
-$var wire 8 ,# out[1][1] [7:0] $end
-$var wire 8 -# out[1][2] [7:0] $end
+$var wire 1 "# clk $end
+$var wire 128 6# in[0][0] [127:0] $end
+$var wire 128 7# in[0][1] [127:0] $end
+$var wire 128 8# in[0][2] [127:0] $end
+$var wire 128 9# in[1][0] [127:0] $end
+$var wire 128 :# in[1][1] [127:0] $end
+$var wire 128 ;# in[1][2] [127:0] $end
+$var wire 8 <# out[0][0] [7:0] $end
+$var wire 8 =# out[0][1] [7:0] $end
+$var wire 8 ># out[0][2] [7:0] $end
+$var wire 8 ?# out[1][0] [7:0] $end
+$var wire 8 @# out[1][1] [7:0] $end
+$var wire 8 A# out[1][2] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 .# i [31:0] $end
+$var int 32 B# i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 /# j [31:0] $end
+$var int 32 C# j [31:0] $end
 $scope module unnamedblk3 $end
-$var byte 8 0# exp [7:0] $end
+$var byte 8 D# exp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5 $end
-$var wire 1 1# clk $end
-$var wire 128 2# in[0][0] [127:0] $end
-$var wire 128 3# in[0][1] [127:0] $end
-$var wire 128 4# in[0][2] [127:0] $end
-$var wire 128 5# in[1][0] [127:0] $end
-$var wire 128 6# in[1][1] [127:0] $end
-$var wire 128 7# in[1][2] [127:0] $end
-$var wire 8 8# out[0][0] [7:0] $end
-$var wire 8 9# out[0][1] [7:0] $end
-$var wire 8 :# out[0][2] [7:0] $end
-$var wire 8 ;# out[1][0] [7:0] $end
-$var wire 8 <# out[1][1] [7:0] $end
-$var wire 8 =# out[1][2] [7:0] $end
+$var wire 1 E# clk $end
+$var wire 128 F# in[0][0] [127:0] $end
+$var wire 128 G# in[0][1] [127:0] $end
+$var wire 128 H# in[0][2] [127:0] $end
+$var wire 128 I# in[1][0] [127:0] $end
+$var wire 128 J# in[1][1] [127:0] $end
+$var wire 128 K# in[1][2] [127:0] $end
+$var wire 8 L# out[0][0] [7:0] $end
+$var wire 8 M# out[0][1] [7:0] $end
+$var wire 8 N# out[0][2] [7:0] $end
+$var wire 8 O# out[1][0] [7:0] $end
+$var wire 8 P# out[1][1] [7:0] $end
+$var wire 8 Q# out[1][2] [7:0] $end
 $scope module sub5 $end
-$var wire 1 1# clk $end
-$var wire 128 2# in[0][0] [127:0] $end
-$var wire 128 3# in[0][1] [127:0] $end
-$var wire 128 4# in[0][2] [127:0] $end
-$var wire 128 5# in[1][0] [127:0] $end
-$var wire 128 6# in[1][1] [127:0] $end
-$var wire 128 7# in[1][2] [127:0] $end
-$var wire 8 8# out[0][0] [7:0] $end
-$var wire 8 9# out[0][1] [7:0] $end
-$var wire 8 :# out[0][2] [7:0] $end
-$var wire 8 ;# out[1][0] [7:0] $end
-$var wire 8 <# out[1][1] [7:0] $end
-$var wire 8 =# out[1][2] [7:0] $end
-$var int 32 ># count [31:0] $end
-$var wire 8 ?# val0[0] [7:0] $end
-$var wire 8 @# val0[1] [7:0] $end
-$var wire 8 A# val1[0] [7:0] $end
-$var wire 8 B# val1[1] [7:0] $end
-$var wire 8 C# val2[0] [7:0] $end
-$var wire 8 D# val2[1] [7:0] $end
-$var wire 8 E# val3[0] [7:0] $end
-$var wire 8 F# val3[1] [7:0] $end
+$var wire 1 E# clk $end
+$var wire 128 F# in[0][0] [127:0] $end
+$var wire 128 G# in[0][1] [127:0] $end
+$var wire 128 H# in[0][2] [127:0] $end
+$var wire 128 I# in[1][0] [127:0] $end
+$var wire 128 J# in[1][1] [127:0] $end
+$var wire 128 K# in[1][2] [127:0] $end
+$var wire 8 L# out[0][0] [7:0] $end
+$var wire 8 M# out[0][1] [7:0] $end
+$var wire 8 N# out[0][2] [7:0] $end
+$var wire 8 O# out[1][0] [7:0] $end
+$var wire 8 P# out[1][1] [7:0] $end
+$var wire 8 Q# out[1][2] [7:0] $end
+$var int 32 R# count [31:0] $end
+$var wire 8 S# val0[0] [7:0] $end
+$var wire 8 T# val0[1] [7:0] $end
+$var wire 8 U# val1[0] [7:0] $end
+$var wire 8 V# val1[1] [7:0] $end
+$var wire 8 W# val2[0] [7:0] $end
+$var wire 8 X# val2[1] [7:0] $end
+$var wire 8 Y# val3[0] [7:0] $end
+$var wire 8 Z# val3[1] [7:0] $end
 $scope module i_sub0 $end
-$var parameter 32 G# P0 [31:0] $end
-$var parameter 32 H# P1 [31:0] $end
-$var wire 8 I# out[0] [7:0] $end
-$var wire 8 J# out[1] [7:0] $end
+$var parameter 32 [# P0 [31:0] $end
+$var parameter 32 \# P1 [31:0] $end
+$var wire 8 ]# out[0] [7:0] $end
+$var wire 8 ^# out[1] [7:0] $end
 $upscope $end
 $scope module i_sub1 $end
-$var parameter 32 G# P0 [31:0] $end
-$var parameter 32 H# P1 [31:0] $end
-$var wire 8 K# out[0] [7:0] $end
-$var wire 8 L# out[1] [7:0] $end
+$var parameter 32 [# P0 [31:0] $end
+$var parameter 32 \# P1 [31:0] $end
+$var wire 8 _# out[0] [7:0] $end
+$var wire 8 `# out[1] [7:0] $end
 $upscope $end
 $scope module i_sub2 $end
-$var parameter 32 G# P0 [31:0] $end
-$var parameter 32 H# P1 [31:0] $end
-$var wire 8 M# out[0] [7:0] $end
-$var wire 8 N# out[1] [7:0] $end
+$var parameter 32 [# P0 [31:0] $end
+$var parameter 32 \# P1 [31:0] $end
+$var wire 8 a# out[0] [7:0] $end
+$var wire 8 b# out[1] [7:0] $end
 $upscope $end
 $scope module i_sub3 $end
-$var wire 8 O# out[0] [7:0] $end
-$var wire 8 P# out[1] [7:0] $end
+$var wire 8 c# out[0] [7:0] $end
+$var wire 8 d# out[1] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 Q# i [31:0] $end
+$var int 32 e# i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 R# j [31:0] $end
+$var int 32 f# j [31:0] $end
 $scope module unnamedblk3 $end
-$var bit 128 S# exp [127:0] $end
+$var bit 128 g# exp [127:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end
-$var wire 8 T# out[0] [7:0] $end
-$var wire 8 U# out[1] [7:0] $end
+$var wire 8 h# out[0] [7:0] $end
+$var wire 8 i# out[1] [7:0] $end
 $scope module sub6_9 $end
-$var parameter 32 V# P0 [31:0] $end
-$var wire 8 T# out[0] [7:0] $end
-$var wire 8 U# out[1] [7:0] $end
+$var parameter 32 j# P0 [31:0] $end
+$var parameter 32 k# P1 [31:0] $end
+$var wire 8 h# out[0] [7:0] $end
+$var wire 8 i# out[1] [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3 $end
-$var wire 1 W# clk $end
-$var wire 8 X# in [7:0] $end
-$var wire 8 Y# out [7:0] $end
+$var wire 1 l# clk $end
+$var wire 8 m# in [7:0] $end
+$var wire 8 n# out [7:0] $end
 $scope module sub3_d $end
-$var parameter 32 Z# UNPACKED_ARRAY[0] [31:0] $end
-$var parameter 32 [# UNPACKED_ARRAY[1] [31:0] $end
-$var parameter 16 \# UNUSED [15:0] $end
-$var wire 1 W# clk $end
-$var wire 8 X# in [7:0] $end
-$var wire 8 Y# out [7:0] $end
-$var logic 8 ]# ff [7:0] $end
-$var wire 8 ^# out4 [7:0] $end
-$var wire 8 _# out4_2 [7:0] $end
+$var parameter 8 o# P0 [7:0] $end
+$var parameter 32 p# UNPACKED_ARRAY[0] [31:0] $end
+$var parameter 32 q# UNPACKED_ARRAY[1] [31:0] $end
+$var parameter 16 r# UNUSED [15:0] $end
+$var wire 1 l# clk $end
+$var wire 8 m# in [7:0] $end
+$var wire 8 n# out [7:0] $end
+$var logic 8 s# ff [7:0] $end
+$var wire 8 t# out4 [7:0] $end
+$var wire 8 u# out4_2 [7:0] $end
 $scope module i_sub4_0 $end
-$var wire 1 W# clk $end
-$var wire 8 ]# in [7:0] $end
-$var wire 8 ^# out [7:0] $end
+$var wire 1 l# clk $end
+$var wire 8 s# in [7:0] $end
+$var wire 8 t# out [7:0] $end
 $upscope $end
 $scope module i_sub4_1 $end
-$var wire 1 W# clk $end
-$var wire 8 ]# in [7:0] $end
-$var wire 8 _# out [7:0] $end
+$var wire 1 l# clk $end
+$var wire 8 s# in [7:0] $end
+$var wire 8 u# out [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3.sub3_d.i_sub4_0 $end
-$var wire 1 `# clk $end
-$var wire 8 a# in [7:0] $end
-$var wire 8 b# out [7:0] $end
+$var wire 1 v# clk $end
+$var wire 8 w# in [7:0] $end
+$var wire 8 x# out [7:0] $end
 $scope module sub4_2 $end
-$var wire 1 `# clk $end
-$var wire 8 a# in [7:0] $end
-$var wire 8 b# out [7:0] $end
-$var logic 8 c# ff [7:0] $end
-$var logic 128 d# sub5_in[0][0] [127:0] $end
-$var logic 128 e# sub5_in[0][1] [127:0] $end
-$var logic 128 f# sub5_in[0][2] [127:0] $end
-$var logic 128 g# sub5_in[1][0] [127:0] $end
-$var logic 128 h# sub5_in[1][1] [127:0] $end
-$var logic 128 i# sub5_in[1][2] [127:0] $end
-$var wire 8 j# sub5_out[0][0] [7:0] $end
-$var wire 8 k# sub5_out[0][1] [7:0] $end
-$var wire 8 l# sub5_out[0][2] [7:0] $end
-$var wire 8 m# sub5_out[1][0] [7:0] $end
-$var wire 8 n# sub5_out[1][1] [7:0] $end
-$var wire 8 o# sub5_out[1][2] [7:0] $end
-$var int 32 p# count [31:0] $end
+$var parameter 32 y# P0 [31:0] $end
+$var real_parameter 64 z# P1 $end
+$var real_parameter 64 {# P3 $end
+$var wire 1 v# clk $end
+$var wire 8 w# in [7:0] $end
+$var wire 8 x# out [7:0] $end
+$var logic 8 |# ff [7:0] $end
+$var logic 128 }# sub5_in[0][0] [127:0] $end
+$var logic 128 ~# sub5_in[0][1] [127:0] $end
+$var logic 128 !$ sub5_in[0][2] [127:0] $end
+$var logic 128 "$ sub5_in[1][0] [127:0] $end
+$var logic 128 #$ sub5_in[1][1] [127:0] $end
+$var logic 128 $$ sub5_in[1][2] [127:0] $end
+$var wire 8 %$ sub5_out[0][0] [7:0] $end
+$var wire 8 &$ sub5_out[0][1] [7:0] $end
+$var wire 8 '$ sub5_out[0][2] [7:0] $end
+$var wire 8 ($ sub5_out[1][0] [7:0] $end
+$var wire 8 )$ sub5_out[1][1] [7:0] $end
+$var wire 8 *$ sub5_out[1][2] [7:0] $end
+$var int 32 +$ count [31:0] $end
 $scope module i_sub5 $end
-$var wire 1 `# clk $end
-$var wire 128 q# in[0][0] [127:0] $end
-$var wire 128 r# in[0][1] [127:0] $end
-$var wire 128 s# in[0][2] [127:0] $end
-$var wire 128 t# in[1][0] [127:0] $end
-$var wire 128 u# in[1][1] [127:0] $end
-$var wire 128 v# in[1][2] [127:0] $end
-$var wire 8 w# out[0][0] [7:0] $end
-$var wire 8 x# out[0][1] [7:0] $end
-$var wire 8 y# out[0][2] [7:0] $end
-$var wire 8 z# out[1][0] [7:0] $end
-$var wire 8 {# out[1][1] [7:0] $end
-$var wire 8 |# out[1][2] [7:0] $end
+$var wire 1 v# clk $end
+$var wire 128 ,$ in[0][0] [127:0] $end
+$var wire 128 -$ in[0][1] [127:0] $end
+$var wire 128 .$ in[0][2] [127:0] $end
+$var wire 128 /$ in[1][0] [127:0] $end
+$var wire 128 0$ in[1][1] [127:0] $end
+$var wire 128 1$ in[1][2] [127:0] $end
+$var wire 8 2$ out[0][0] [7:0] $end
+$var wire 8 3$ out[0][1] [7:0] $end
+$var wire 8 4$ out[0][2] [7:0] $end
+$var wire 8 5$ out[1][0] [7:0] $end
+$var wire 8 6$ out[1][1] [7:0] $end
+$var wire 8 7$ out[1][2] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 }# i [31:0] $end
+$var int 32 8$ i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 ~# j [31:0] $end
+$var int 32 9$ j [31:0] $end
 $scope module unnamedblk3 $end
-$var byte 8 !$ exp [7:0] $end
+$var byte 8 :$ exp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5 $end
-$var wire 1 "$ clk $end
-$var wire 128 #$ in[0][0] [127:0] $end
-$var wire 128 $$ in[0][1] [127:0] $end
-$var wire 128 %$ in[0][2] [127:0] $end
-$var wire 128 &$ in[1][0] [127:0] $end
-$var wire 128 '$ in[1][1] [127:0] $end
-$var wire 128 ($ in[1][2] [127:0] $end
-$var wire 8 )$ out[0][0] [7:0] $end
-$var wire 8 *$ out[0][1] [7:0] $end
-$var wire 8 +$ out[0][2] [7:0] $end
-$var wire 8 ,$ out[1][0] [7:0] $end
-$var wire 8 -$ out[1][1] [7:0] $end
-$var wire 8 .$ out[1][2] [7:0] $end
+$var wire 1 ;$ clk $end
+$var wire 128 <$ in[0][0] [127:0] $end
+$var wire 128 =$ in[0][1] [127:0] $end
+$var wire 128 >$ in[0][2] [127:0] $end
+$var wire 128 ?$ in[1][0] [127:0] $end
+$var wire 128 @$ in[1][1] [127:0] $end
+$var wire 128 A$ in[1][2] [127:0] $end
+$var wire 8 B$ out[0][0] [7:0] $end
+$var wire 8 C$ out[0][1] [7:0] $end
+$var wire 8 D$ out[0][2] [7:0] $end
+$var wire 8 E$ out[1][0] [7:0] $end
+$var wire 8 F$ out[1][1] [7:0] $end
+$var wire 8 G$ out[1][2] [7:0] $end
 $scope module sub5 $end
-$var wire 1 "$ clk $end
-$var wire 128 #$ in[0][0] [127:0] $end
-$var wire 128 $$ in[0][1] [127:0] $end
-$var wire 128 %$ in[0][2] [127:0] $end
-$var wire 128 &$ in[1][0] [127:0] $end
-$var wire 128 '$ in[1][1] [127:0] $end
-$var wire 128 ($ in[1][2] [127:0] $end
-$var wire 8 )$ out[0][0] [7:0] $end
-$var wire 8 *$ out[0][1] [7:0] $end
-$var wire 8 +$ out[0][2] [7:0] $end
-$var wire 8 ,$ out[1][0] [7:0] $end
-$var wire 8 -$ out[1][1] [7:0] $end
-$var wire 8 .$ out[1][2] [7:0] $end
-$var int 32 /$ count [31:0] $end
-$var wire 8 0$ val0[0] [7:0] $end
-$var wire 8 1$ val0[1] [7:0] $end
-$var wire 8 2$ val1[0] [7:0] $end
-$var wire 8 3$ val1[1] [7:0] $end
-$var wire 8 4$ val2[0] [7:0] $end
-$var wire 8 5$ val2[1] [7:0] $end
-$var wire 8 6$ val3[0] [7:0] $end
-$var wire 8 7$ val3[1] [7:0] $end
+$var wire 1 ;$ clk $end
+$var wire 128 <$ in[0][0] [127:0] $end
+$var wire 128 =$ in[0][1] [127:0] $end
+$var wire 128 >$ in[0][2] [127:0] $end
+$var wire 128 ?$ in[1][0] [127:0] $end
+$var wire 128 @$ in[1][1] [127:0] $end
+$var wire 128 A$ in[1][2] [127:0] $end
+$var wire 8 B$ out[0][0] [7:0] $end
+$var wire 8 C$ out[0][1] [7:0] $end
+$var wire 8 D$ out[0][2] [7:0] $end
+$var wire 8 E$ out[1][0] [7:0] $end
+$var wire 8 F$ out[1][1] [7:0] $end
+$var wire 8 G$ out[1][2] [7:0] $end
+$var int 32 H$ count [31:0] $end
+$var wire 8 I$ val0[0] [7:0] $end
+$var wire 8 J$ val0[1] [7:0] $end
+$var wire 8 K$ val1[0] [7:0] $end
+$var wire 8 L$ val1[1] [7:0] $end
+$var wire 8 M$ val2[0] [7:0] $end
+$var wire 8 N$ val2[1] [7:0] $end
+$var wire 8 O$ val3[0] [7:0] $end
+$var wire 8 P$ val3[1] [7:0] $end
 $scope module i_sub0 $end
-$var parameter 32 8$ P0 [31:0] $end
-$var parameter 32 9$ P1 [31:0] $end
-$var wire 8 :$ out[0] [7:0] $end
-$var wire 8 ;$ out[1] [7:0] $end
+$var parameter 32 Q$ P0 [31:0] $end
+$var parameter 32 R$ P1 [31:0] $end
+$var wire 8 S$ out[0] [7:0] $end
+$var wire 8 T$ out[1] [7:0] $end
 $upscope $end
 $scope module i_sub1 $end
-$var parameter 32 8$ P0 [31:0] $end
-$var parameter 32 9$ P1 [31:0] $end
-$var wire 8 <$ out[0] [7:0] $end
-$var wire 8 =$ out[1] [7:0] $end
+$var parameter 32 Q$ P0 [31:0] $end
+$var parameter 32 R$ P1 [31:0] $end
+$var wire 8 U$ out[0] [7:0] $end
+$var wire 8 V$ out[1] [7:0] $end
 $upscope $end
 $scope module i_sub2 $end
-$var parameter 32 8$ P0 [31:0] $end
-$var parameter 32 9$ P1 [31:0] $end
-$var wire 8 >$ out[0] [7:0] $end
-$var wire 8 ?$ out[1] [7:0] $end
+$var parameter 32 Q$ P0 [31:0] $end
+$var parameter 32 R$ P1 [31:0] $end
+$var wire 8 W$ out[0] [7:0] $end
+$var wire 8 X$ out[1] [7:0] $end
 $upscope $end
 $scope module i_sub3 $end
-$var wire 8 @$ out[0] [7:0] $end
-$var wire 8 A$ out[1] [7:0] $end
+$var wire 8 Y$ out[0] [7:0] $end
+$var wire 8 Z$ out[1] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 B$ i [31:0] $end
+$var int 32 [$ i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 C$ j [31:0] $end
+$var int 32 \$ j [31:0] $end
 $scope module unnamedblk3 $end
-$var bit 128 D$ exp [127:0] $end
+$var bit 128 ]$ exp [127:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end
-$var wire 8 E$ out[0] [7:0] $end
-$var wire 8 F$ out[1] [7:0] $end
+$var wire 8 ^$ out[0] [7:0] $end
+$var wire 8 _$ out[1] [7:0] $end
 $scope module sub6_9 $end
-$var parameter 32 G$ P0 [31:0] $end
-$var wire 8 E$ out[0] [7:0] $end
-$var wire 8 F$ out[1] [7:0] $end
+$var parameter 32 `$ P0 [31:0] $end
+$var parameter 32 a$ P1 [31:0] $end
+$var wire 8 ^$ out[0] [7:0] $end
+$var wire 8 _$ out[1] [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3.sub3_d.i_sub4_1 $end
-$var wire 1 H$ clk $end
-$var wire 8 I$ in [7:0] $end
-$var wire 8 J$ out [7:0] $end
+$var wire 1 b$ clk $end
+$var wire 8 c$ in [7:0] $end
+$var wire 8 d$ out [7:0] $end
 $scope module sub4_b $end
-$var wire 1 H$ clk $end
-$var wire 8 I$ in [7:0] $end
-$var wire 8 J$ out [7:0] $end
-$var logic 8 K$ ff [7:0] $end
-$var logic 128 L$ sub5_in[0][0] [127:0] $end
-$var logic 128 M$ sub5_in[0][1] [127:0] $end
-$var logic 128 N$ sub5_in[0][2] [127:0] $end
-$var logic 128 O$ sub5_in[1][0] [127:0] $end
-$var logic 128 P$ sub5_in[1][1] [127:0] $end
-$var logic 128 Q$ sub5_in[1][2] [127:0] $end
-$var wire 8 R$ sub5_out[0][0] [7:0] $end
-$var wire 8 S$ sub5_out[0][1] [7:0] $end
-$var wire 8 T$ sub5_out[0][2] [7:0] $end
-$var wire 8 U$ sub5_out[1][0] [7:0] $end
-$var wire 8 V$ sub5_out[1][1] [7:0] $end
-$var wire 8 W$ sub5_out[1][2] [7:0] $end
-$var int 32 X$ count [31:0] $end
+$var parameter 32 e$ P0 [31:0] $end
+$var real_parameter 64 f$ P1 $end
+$var real_parameter 64 g$ P3 $end
+$var wire 1 b$ clk $end
+$var wire 8 c$ in [7:0] $end
+$var wire 8 d$ out [7:0] $end
+$var logic 8 h$ ff [7:0] $end
+$var logic 128 i$ sub5_in[0][0] [127:0] $end
+$var logic 128 j$ sub5_in[0][1] [127:0] $end
+$var logic 128 k$ sub5_in[0][2] [127:0] $end
+$var logic 128 l$ sub5_in[1][0] [127:0] $end
+$var logic 128 m$ sub5_in[1][1] [127:0] $end
+$var logic 128 n$ sub5_in[1][2] [127:0] $end
+$var wire 8 o$ sub5_out[0][0] [7:0] $end
+$var wire 8 p$ sub5_out[0][1] [7:0] $end
+$var wire 8 q$ sub5_out[0][2] [7:0] $end
+$var wire 8 r$ sub5_out[1][0] [7:0] $end
+$var wire 8 s$ sub5_out[1][1] [7:0] $end
+$var wire 8 t$ sub5_out[1][2] [7:0] $end
+$var int 32 u$ count [31:0] $end
 $scope module i_sub5 $end
-$var wire 1 H$ clk $end
-$var wire 128 Y$ in[0][0] [127:0] $end
-$var wire 128 Z$ in[0][1] [127:0] $end
-$var wire 128 [$ in[0][2] [127:0] $end
-$var wire 128 \$ in[1][0] [127:0] $end
-$var wire 128 ]$ in[1][1] [127:0] $end
-$var wire 128 ^$ in[1][2] [127:0] $end
-$var wire 8 _$ out[0][0] [7:0] $end
-$var wire 8 `$ out[0][1] [7:0] $end
-$var wire 8 a$ out[0][2] [7:0] $end
-$var wire 8 b$ out[1][0] [7:0] $end
-$var wire 8 c$ out[1][1] [7:0] $end
-$var wire 8 d$ out[1][2] [7:0] $end
+$var wire 1 b$ clk $end
+$var wire 128 v$ in[0][0] [127:0] $end
+$var wire 128 w$ in[0][1] [127:0] $end
+$var wire 128 x$ in[0][2] [127:0] $end
+$var wire 128 y$ in[1][0] [127:0] $end
+$var wire 128 z$ in[1][1] [127:0] $end
+$var wire 128 {$ in[1][2] [127:0] $end
+$var wire 8 |$ out[0][0] [7:0] $end
+$var wire 8 }$ out[0][1] [7:0] $end
+$var wire 8 ~$ out[0][2] [7:0] $end
+$var wire 8 !% out[1][0] [7:0] $end
+$var wire 8 "% out[1][1] [7:0] $end
+$var wire 8 #% out[1][2] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 e$ i [31:0] $end
+$var int 32 $% i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 f$ j [31:0] $end
+$var int 32 %% j [31:0] $end
 $scope module unnamedblk3 $end
-$var byte 8 g$ exp [7:0] $end
+$var byte 8 &% exp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5 $end
-$var wire 1 h$ clk $end
-$var wire 128 i$ in[0][0] [127:0] $end
-$var wire 128 j$ in[0][1] [127:0] $end
-$var wire 128 k$ in[0][2] [127:0] $end
-$var wire 128 l$ in[1][0] [127:0] $end
-$var wire 128 m$ in[1][1] [127:0] $end
-$var wire 128 n$ in[1][2] [127:0] $end
-$var wire 8 o$ out[0][0] [7:0] $end
-$var wire 8 p$ out[0][1] [7:0] $end
-$var wire 8 q$ out[0][2] [7:0] $end
-$var wire 8 r$ out[1][0] [7:0] $end
-$var wire 8 s$ out[1][1] [7:0] $end
-$var wire 8 t$ out[1][2] [7:0] $end
+$var wire 1 '% clk $end
+$var wire 128 (% in[0][0] [127:0] $end
+$var wire 128 )% in[0][1] [127:0] $end
+$var wire 128 *% in[0][2] [127:0] $end
+$var wire 128 +% in[1][0] [127:0] $end
+$var wire 128 ,% in[1][1] [127:0] $end
+$var wire 128 -% in[1][2] [127:0] $end
+$var wire 8 .% out[0][0] [7:0] $end
+$var wire 8 /% out[0][1] [7:0] $end
+$var wire 8 0% out[0][2] [7:0] $end
+$var wire 8 1% out[1][0] [7:0] $end
+$var wire 8 2% out[1][1] [7:0] $end
+$var wire 8 3% out[1][2] [7:0] $end
 $scope module sub5 $end
-$var wire 1 h$ clk $end
-$var wire 128 i$ in[0][0] [127:0] $end
-$var wire 128 j$ in[0][1] [127:0] $end
-$var wire 128 k$ in[0][2] [127:0] $end
-$var wire 128 l$ in[1][0] [127:0] $end
-$var wire 128 m$ in[1][1] [127:0] $end
-$var wire 128 n$ in[1][2] [127:0] $end
-$var wire 8 o$ out[0][0] [7:0] $end
-$var wire 8 p$ out[0][1] [7:0] $end
-$var wire 8 q$ out[0][2] [7:0] $end
-$var wire 8 r$ out[1][0] [7:0] $end
-$var wire 8 s$ out[1][1] [7:0] $end
-$var wire 8 t$ out[1][2] [7:0] $end
-$var int 32 u$ count [31:0] $end
-$var wire 8 v$ val0[0] [7:0] $end
-$var wire 8 w$ val0[1] [7:0] $end
-$var wire 8 x$ val1[0] [7:0] $end
-$var wire 8 y$ val1[1] [7:0] $end
-$var wire 8 z$ val2[0] [7:0] $end
-$var wire 8 {$ val2[1] [7:0] $end
-$var wire 8 |$ val3[0] [7:0] $end
-$var wire 8 }$ val3[1] [7:0] $end
+$var wire 1 '% clk $end
+$var wire 128 (% in[0][0] [127:0] $end
+$var wire 128 )% in[0][1] [127:0] $end
+$var wire 128 *% in[0][2] [127:0] $end
+$var wire 128 +% in[1][0] [127:0] $end
+$var wire 128 ,% in[1][1] [127:0] $end
+$var wire 128 -% in[1][2] [127:0] $end
+$var wire 8 .% out[0][0] [7:0] $end
+$var wire 8 /% out[0][1] [7:0] $end
+$var wire 8 0% out[0][2] [7:0] $end
+$var wire 8 1% out[1][0] [7:0] $end
+$var wire 8 2% out[1][1] [7:0] $end
+$var wire 8 3% out[1][2] [7:0] $end
+$var int 32 4% count [31:0] $end
+$var wire 8 5% val0[0] [7:0] $end
+$var wire 8 6% val0[1] [7:0] $end
+$var wire 8 7% val1[0] [7:0] $end
+$var wire 8 8% val1[1] [7:0] $end
+$var wire 8 9% val2[0] [7:0] $end
+$var wire 8 :% val2[1] [7:0] $end
+$var wire 8 ;% val3[0] [7:0] $end
+$var wire 8 <% val3[1] [7:0] $end
 $scope module i_sub0 $end
-$var parameter 32 ~$ P0 [31:0] $end
-$var parameter 32 !% P1 [31:0] $end
-$var wire 8 "% out[0] [7:0] $end
-$var wire 8 #% out[1] [7:0] $end
+$var parameter 32 =% P0 [31:0] $end
+$var parameter 32 >% P1 [31:0] $end
+$var wire 8 ?% out[0] [7:0] $end
+$var wire 8 @% out[1] [7:0] $end
 $upscope $end
 $scope module i_sub1 $end
-$var parameter 32 ~$ P0 [31:0] $end
-$var parameter 32 !% P1 [31:0] $end
-$var wire 8 $% out[0] [7:0] $end
-$var wire 8 %% out[1] [7:0] $end
+$var parameter 32 =% P0 [31:0] $end
+$var parameter 32 >% P1 [31:0] $end
+$var wire 8 A% out[0] [7:0] $end
+$var wire 8 B% out[1] [7:0] $end
 $upscope $end
 $scope module i_sub2 $end
-$var parameter 32 ~$ P0 [31:0] $end
-$var parameter 32 !% P1 [31:0] $end
-$var wire 8 &% out[0] [7:0] $end
-$var wire 8 '% out[1] [7:0] $end
+$var parameter 32 =% P0 [31:0] $end
+$var parameter 32 >% P1 [31:0] $end
+$var wire 8 C% out[0] [7:0] $end
+$var wire 8 D% out[1] [7:0] $end
 $upscope $end
 $scope module i_sub3 $end
-$var wire 8 (% out[0] [7:0] $end
-$var wire 8 )% out[1] [7:0] $end
+$var wire 8 E% out[0] [7:0] $end
+$var wire 8 F% out[1] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 *% i [31:0] $end
+$var int 32 G% i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 +% j [31:0] $end
+$var int 32 H% j [31:0] $end
 $scope module unnamedblk3 $end
-$var bit 128 ,% exp [127:0] $end
+$var bit 128 I% exp [127:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end
-$var wire 8 -% out[0] [7:0] $end
-$var wire 8 .% out[1] [7:0] $end
+$var wire 8 J% out[0] [7:0] $end
+$var wire 8 K% out[1] [7:0] $end
 $scope module sub6_9 $end
-$var parameter 32 /% P0 [31:0] $end
-$var wire 8 -% out[0] [7:0] $end
-$var wire 8 .% out[1] [7:0] $end
+$var parameter 32 L% P0 [31:0] $end
+$var parameter 32 M% P1 [31:0] $end
+$var wire 8 J% out[0] [7:0] $end
+$var wire 8 K% out[1] [7:0] $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
 #0
 $dumpvars
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-b00000011 }$
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-b00000010 y$
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@@ -1058,212 +1118,212 @@ b0000000000000000000000000000000000000000000000000000000000000000000000000000000
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-b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 N$
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-b00000000 K$
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 b00011000 ?
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 #161
 #162
 #163
 #164
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 #171
 #172
 #173
diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.out b/test_regress/t/t_hier_block_sc_trace_vcd.out
index cde885b1e..bcb002864 100644
--- a/test_regress/t/t_hier_block_sc_trace_vcd.out
+++ b/test_regress/t/t_hier_block_sc_trace_vcd.out
@@ -1,5 +1,5 @@
 $version Generated by VerilatedVcd $end
-$date Tue Oct 18 17:12:31 2022 $end
+$date Thu Nov 10 20:17:32 2022 $end
 $timescale 1ps $end
 
  $scope module top $end
@@ -60,15 +60,16 @@ $timescale 1ps $end
   $var wire  8 . in [7:0] $end
   $var wire  8 / out [7:0] $end
   $scope module delay_2 $end
-   $var wire 32 2 WIDTH [31:0] $end
+   $var wire 32 2 N [31:0] $end
+   $var wire 32 3 WIDTH [31:0] $end
    $var wire  1 - clk $end
    $var wire  8 . in [7:0] $end
    $var wire  8 / out [7:0] $end
    $var wire  8 0 tmp [7:0] $end
    $scope module genblk1 $end
     $scope module i_delay $end
-     $var wire 32 3 N [31:0] $end
-     $var wire 32 2 WIDTH [31:0] $end
+     $var wire 32 4 N [31:0] $end
+     $var wire 32 3 WIDTH [31:0] $end
      $var wire  1 - clk $end
      $var wire  8 0 in [7:0] $end
      $var wire  8 / out [7:0] $end
@@ -78,31 +79,32 @@ $timescale 1ps $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_delay1 $end
-  $var wire  1 8 clk $end
-  $var wire  8 9 in [7:0] $end
-  $var wire  8 : out [7:0] $end
+  $var wire  1 9 clk $end
+  $var wire  8 : in [7:0] $end
+  $var wire  8 ; out [7:0] $end
   $scope module delay_9 $end
-   $var wire 32 ; WIDTH [31:0] $end
-   $var wire  1 8 clk $end
-   $var wire  8 9 in [7:0] $end
-   $var wire  8 : out [7:0] $end
-   $var wire  8 5 tmp [7:0] $end
+   $var wire 32 < N [31:0] $end
+   $var wire 32 = WIDTH [31:0] $end
+   $var wire  1 9 clk $end
+   $var wire  8 : in [7:0] $end
+   $var wire  8 ; out [7:0] $end
+   $var wire  8 6 tmp [7:0] $end
    $scope module genblk1 $end
     $scope module i_delay $end
-     $var wire 32 < N [31:0] $end
-     $var wire 32 ; WIDTH [31:0] $end
-     $var wire  1 8 clk $end
-     $var wire  8 5 in [7:0] $end
-     $var wire  8 : out [7:0] $end
-     $var wire  8 6 tmp [7:0] $end
+     $var wire 32 > N [31:0] $end
+     $var wire 32 = WIDTH [31:0] $end
+     $var wire  1 9 clk $end
+     $var wire  8 6 in [7:0] $end
+     $var wire  8 ; out [7:0] $end
+     $var wire  8 7 tmp [7:0] $end
      $scope module genblk1 $end
       $scope module i_delay $end
-       $var wire 32 = N [31:0] $end
-       $var wire 32 ; WIDTH [31:0] $end
-       $var wire  1 8 clk $end
-       $var wire  8 6 in [7:0] $end
-       $var wire  8 : out [7:0] $end
-       $var wire  8 7 tmp [7:0] $end
+       $var wire 32 ? N [31:0] $end
+       $var wire 32 = WIDTH [31:0] $end
+       $var wire  1 9 clk $end
+       $var wire  8 7 in [7:0] $end
+       $var wire  8 ; out [7:0] $end
+       $var wire  8 8 tmp [7:0] $end
       $upscope $end
      $upscope $end
     $upscope $end
@@ -110,906 +112,934 @@ $timescale 1ps $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub0.i_sub0 $end
-  $var wire  1 ? clk $end
-  $var wire  8 @ in [7:0] $end
-  $var wire  8 A out [7:0] $end
+  $var wire  1 A clk $end
+  $var wire  8 B in [7:0] $end
+  $var wire  8 C out [7:0] $end
   $scope module sub0 $end
-   $var wire  1 ? clk $end
-   $var wire  8 B ff [7:0] $end
-   $var wire  8 @ in [7:0] $end
-   $var wire  8 A out [7:0] $end
+   $var wire  1 A clk $end
+   $var wire  8 D ff [7:0] $end
+   $var wire  8 B in [7:0] $end
+   $var wire  8 C out [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub1 $end
-  $var wire  1 D clk $end
-  $var wire  8 E in [11:4] $end
-  $var wire  8 F out [7:0] $end
+  $var wire  1 F clk $end
+  $var wire  8 G in [11:4] $end
+  $var wire  8 H out [7:0] $end
   $scope module sub1 $end
-   $var wire  1 D clk $end
-   $var wire  8 G ff [7:0] $end
-   $var wire  8 E in [11:4] $end
-   $var wire  8 F out [7:0] $end
+   $var wire  1 F clk $end
+   $var wire  8 I ff [7:0] $end
+   $var wire  8 G in [11:4] $end
+   $var wire  8 H out [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2 $end
-  $var wire  1 I clk $end
-  $var wire  8 J in [7:0] $end
-  $var wire  8 K out [7:0] $end
+  $var wire  1 K clk $end
+  $var wire  8 L in [7:0] $end
+  $var wire  8 M out [7:0] $end
   $scope module sub2 $end
-   $var wire  1 I clk $end
-   $var wire  8 L ff [7:0] $end
-   $var wire  8 J in [7:0] $end
-   $var wire  8 K out [7:0] $end
+   $var wire  1 K clk $end
+   $var wire  8 N ff [7:0] $end
+   $var wire  8 L in [7:0] $end
+   $var wire  8 M out [7:0] $end
    $scope module i_sub3 $end
-    $var wire  8 L in_wire [7:0] $end
-    $var wire  8 M out_1 [7:0] $end
-    $var wire  8 N out_2 [7:0] $end
+    $var wire  8 N in_wire [7:0] $end
+    $var wire  8 O out_1 [7:0] $end
+    $var wire  8 P out_2 [7:0] $end
     $scope module i_sub3 $end
-     $var wire  1 I clk $end
-     $var wire  8 L in [7:0] $end
-     $var wire  8 M out [7:0] $end
+     $var wire  1 K clk $end
+     $var wire  8 N in [7:0] $end
+     $var wire  8 O out [7:0] $end
     $upscope $end
     $scope module i_sub3_2 $end
-     $var wire  1 I clk $end
-     $var wire  8 L in [7:0] $end
-     $var wire  8 N out [7:0] $end
+     $var wire  1 K clk $end
+     $var wire  8 N in [7:0] $end
+     $var wire  8 P out [7:0] $end
     $upscope $end
     $scope interface in $end
-     $var wire  1 I clk $end
-     $var wire  8 L data [7:0] $end
+     $var wire  1 K clk $end
+     $var wire  8 N data [7:0] $end
     $upscope $end
     $scope interface out $end
-     $var wire  1 I clk $end
-     $var wire  8 M data [7:0] $end
+     $var wire  1 K clk $end
+     $var wire  8 O data [7:0] $end
     $upscope $end
    $upscope $end
    $scope interface in_ifs $end
-    $var wire  1 I clk $end
-    $var wire  8 L data [7:0] $end
+    $var wire  1 K clk $end
+    $var wire  8 N data [7:0] $end
    $upscope $end
    $scope interface out_ifs $end
-    $var wire  1 I clk $end
-    $var wire  8 M data [7:0] $end
+    $var wire  1 K clk $end
+    $var wire  8 O data [7:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3 $end
-  $var wire  1 P clk $end
-  $var wire  8 Q in [7:0] $end
-  $var wire  8 R out [7:0] $end
+  $var wire  1 R clk $end
+  $var wire  8 S in [7:0] $end
+  $var wire  8 T out [7:0] $end
   $scope module sub3_c $end
-   $var wire 32 V UNPACKED_ARRAY[0] [31:0] $end
-   $var wire 32 W UNPACKED_ARRAY[1] [31:0] $end
-   $var wire  1 P clk $end
-   $var wire  8 S ff [7:0] $end
-   $var wire  8 Q in [7:0] $end
-   $var wire  8 R out [7:0] $end
-   $var wire  8 T out4 [7:0] $end
-   $var wire  8 U out4_2 [7:0] $end
+   $var wire  8 X P0 [7:0] $end
+   $var wire 32 Y UNPACKED_ARRAY[0] [31:0] $end
+   $var wire 32 Z UNPACKED_ARRAY[1] [31:0] $end
+   $var wire 16 [ UNUSED [15:0] $end
+   $var wire  1 R clk $end
+   $var wire  8 U ff [7:0] $end
+   $var wire  8 S in [7:0] $end
+   $var wire  8 T out [7:0] $end
+   $var wire  8 V out4 [7:0] $end
+   $var wire  8 W out4_2 [7:0] $end
    $scope module i_sub4_0 $end
-    $var wire  1 P clk $end
-    $var wire  8 S in [7:0] $end
-    $var wire  8 T out [7:0] $end
+    $var wire  1 R clk $end
+    $var wire  8 U in [7:0] $end
+    $var wire  8 V out [7:0] $end
    $upscope $end
    $scope module i_sub4_1 $end
-    $var wire  1 P clk $end
-    $var wire  8 S in [7:0] $end
-    $var wire  8 U out [7:0] $end
+    $var wire  1 R clk $end
+    $var wire  8 U in [7:0] $end
+    $var wire  8 W out [7:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0 $end
-  $var wire  1 <! clk $end
-  $var wire  8 =! in [7:0] $end
-  $var wire  8 >! out [7:0] $end
+  $var wire  1 @! clk $end
+  $var wire  8 A! in [7:0] $end
+  $var wire  8 B! out [7:0] $end
   $scope module sub4_2 $end
-   $var wire  1 <! clk $end
-   $var wire 32 r count [31:0] $end
-   $var wire  8 Y ff [7:0] $end
-   $var wire  8 =! in [7:0] $end
-   $var wire  8 >! out [7:0] $end
-   $var wire 128 Z sub5_in[0][0] [127:0] $end
-   $var wire 128 ^ sub5_in[0][1] [127:0] $end
-   $var wire 128 b sub5_in[0][2] [127:0] $end
-   $var wire 128 f sub5_in[1][0] [127:0] $end
-   $var wire 128 j sub5_in[1][1] [127:0] $end
-   $var wire 128 n sub5_in[1][2] [127:0] $end
-   $var wire  8 0! sub5_out[0][0] [7:0] $end
-   $var wire  8 1! sub5_out[0][1] [7:0] $end
-   $var wire  8 2! sub5_out[0][2] [7:0] $end
-   $var wire  8 3! sub5_out[1][0] [7:0] $end
-   $var wire  8 4! sub5_out[1][1] [7:0] $end
-   $var wire  8 5! sub5_out[1][2] [7:0] $end
+   $var wire 32 C! P0 [31:0] $end
+   $var real 64 D! P1 $end
+   $var real 64 F! P3 $end
+   $var wire  1 @! clk $end
+   $var wire 32 v count [31:0] $end
+   $var wire  8 ] ff [7:0] $end
+   $var wire  8 A! in [7:0] $end
+   $var wire  8 B! out [7:0] $end
+   $var wire 128 ^ sub5_in[0][0] [127:0] $end
+   $var wire 128 b sub5_in[0][1] [127:0] $end
+   $var wire 128 f sub5_in[0][2] [127:0] $end
+   $var wire 128 j sub5_in[1][0] [127:0] $end
+   $var wire 128 n sub5_in[1][1] [127:0] $end
+   $var wire 128 r sub5_in[1][2] [127:0] $end
+   $var wire  8 4! sub5_out[0][0] [7:0] $end
+   $var wire  8 5! sub5_out[0][1] [7:0] $end
+   $var wire  8 6! sub5_out[0][2] [7:0] $end
+   $var wire  8 7! sub5_out[1][0] [7:0] $end
+   $var wire  8 8! sub5_out[1][1] [7:0] $end
+   $var wire  8 9! sub5_out[1][2] [7:0] $end
    $scope module i_sub5 $end
-    $var wire  1 <! clk $end
-    $var wire 128 v in[0][0] [127:0] $end
-    $var wire 128 z in[0][1] [127:0] $end
-    $var wire 128 ~ in[0][2] [127:0] $end
-    $var wire 128 $! in[1][0] [127:0] $end
-    $var wire 128 (! in[1][1] [127:0] $end
-    $var wire 128 ,! in[1][2] [127:0] $end
-    $var wire  8 6! out[0][0] [7:0] $end
-    $var wire  8 7! out[0][1] [7:0] $end
-    $var wire  8 8! out[0][2] [7:0] $end
-    $var wire  8 9! out[1][0] [7:0] $end
-    $var wire  8 :! out[1][1] [7:0] $end
-    $var wire  8 ;! out[1][2] [7:0] $end
+    $var wire  1 @! clk $end
+    $var wire 128 z in[0][0] [127:0] $end
+    $var wire 128 ~ in[0][1] [127:0] $end
+    $var wire 128 $! in[0][2] [127:0] $end
+    $var wire 128 (! in[1][0] [127:0] $end
+    $var wire 128 ,! in[1][1] [127:0] $end
+    $var wire 128 0! in[1][2] [127:0] $end
+    $var wire  8 :! out[0][0] [7:0] $end
+    $var wire  8 ;! out[0][1] [7:0] $end
+    $var wire  8 <! out[0][2] [7:0] $end
+    $var wire  8 =! out[1][0] [7:0] $end
+    $var wire  8 >! out[1][1] [7:0] $end
+    $var wire  8 ?! out[1][2] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 s i [31:0] $end
+    $var wire 32 w i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 t j [31:0] $end
+     $var wire 32 x j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire  8 u exp [7:0] $end
+      $var wire  8 y exp [7:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5 $end
-  $var wire  1 W! clk $end
-  $var wire 128 X! in[0][0] [127:0] $end
-  $var wire 128 \! in[0][1] [127:0] $end
-  $var wire 128 `! in[0][2] [127:0] $end
-  $var wire 128 d! in[1][0] [127:0] $end
-  $var wire 128 h! in[1][1] [127:0] $end
-  $var wire 128 l! in[1][2] [127:0] $end
-  $var wire  8 p! out[0][0] [7:0] $end
-  $var wire  8 q! out[0][1] [7:0] $end
-  $var wire  8 r! out[0][2] [7:0] $end
-  $var wire  8 s! out[1][0] [7:0] $end
-  $var wire  8 t! out[1][1] [7:0] $end
-  $var wire  8 u! out[1][2] [7:0] $end
+  $var wire  1 `! clk $end
+  $var wire 128 a! in[0][0] [127:0] $end
+  $var wire 128 e! in[0][1] [127:0] $end
+  $var wire 128 i! in[0][2] [127:0] $end
+  $var wire 128 m! in[1][0] [127:0] $end
+  $var wire 128 q! in[1][1] [127:0] $end
+  $var wire 128 u! in[1][2] [127:0] $end
+  $var wire  8 y! out[0][0] [7:0] $end
+  $var wire  8 z! out[0][1] [7:0] $end
+  $var wire  8 {! out[0][2] [7:0] $end
+  $var wire  8 |! out[1][0] [7:0] $end
+  $var wire  8 }! out[1][1] [7:0] $end
+  $var wire  8 ~! out[1][2] [7:0] $end
   $scope module sub5 $end
-   $var wire  1 W! clk $end
-   $var wire 32 P! count [31:0] $end
-   $var wire 128 X! in[0][0] [127:0] $end
-   $var wire 128 \! in[0][1] [127:0] $end
-   $var wire 128 `! in[0][2] [127:0] $end
-   $var wire 128 d! in[1][0] [127:0] $end
-   $var wire 128 h! in[1][1] [127:0] $end
-   $var wire 128 l! in[1][2] [127:0] $end
-   $var wire  8 p! out[0][0] [7:0] $end
-   $var wire  8 q! out[0][1] [7:0] $end
-   $var wire  8 r! out[0][2] [7:0] $end
-   $var wire  8 s! out[1][0] [7:0] $end
-   $var wire  8 t! out[1][1] [7:0] $end
-   $var wire  8 u! out[1][2] [7:0] $end
-   $var wire  8 @! val0[0] [7:0] $end
-   $var wire  8 A! val0[1] [7:0] $end
-   $var wire  8 B! val1[0] [7:0] $end
-   $var wire  8 C! val1[1] [7:0] $end
-   $var wire  8 D! val2[0] [7:0] $end
-   $var wire  8 E! val2[1] [7:0] $end
-   $var wire  8 F! val3[0] [7:0] $end
-   $var wire  8 G! val3[1] [7:0] $end
+   $var wire  1 `! clk $end
+   $var wire 32 Y! count [31:0] $end
+   $var wire 128 a! in[0][0] [127:0] $end
+   $var wire 128 e! in[0][1] [127:0] $end
+   $var wire 128 i! in[0][2] [127:0] $end
+   $var wire 128 m! in[1][0] [127:0] $end
+   $var wire 128 q! in[1][1] [127:0] $end
+   $var wire 128 u! in[1][2] [127:0] $end
+   $var wire  8 y! out[0][0] [7:0] $end
+   $var wire  8 z! out[0][1] [7:0] $end
+   $var wire  8 {! out[0][2] [7:0] $end
+   $var wire  8 |! out[1][0] [7:0] $end
+   $var wire  8 }! out[1][1] [7:0] $end
+   $var wire  8 ~! out[1][2] [7:0] $end
+   $var wire  8 I! val0[0] [7:0] $end
+   $var wire  8 J! val0[1] [7:0] $end
+   $var wire  8 K! val1[0] [7:0] $end
+   $var wire  8 L! val1[1] [7:0] $end
+   $var wire  8 M! val2[0] [7:0] $end
+   $var wire  8 N! val2[1] [7:0] $end
+   $var wire  8 O! val3[0] [7:0] $end
+   $var wire  8 P! val3[1] [7:0] $end
    $scope module i_sub0 $end
-    $var wire 32 v! P0 [31:0] $end
-    $var wire 32 w! P1 [31:0] $end
-    $var wire  8 H! out[0] [7:0] $end
-    $var wire  8 I! out[1] [7:0] $end
+    $var wire 32 !" P0 [31:0] $end
+    $var wire 32 "" P1 [31:0] $end
+    $var wire  8 Q! out[0] [7:0] $end
+    $var wire  8 R! out[1] [7:0] $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 32 v! P0 [31:0] $end
-    $var wire 32 w! P1 [31:0] $end
-    $var wire  8 J! out[0] [7:0] $end
-    $var wire  8 K! out[1] [7:0] $end
+    $var wire 32 !" P0 [31:0] $end
+    $var wire 32 "" P1 [31:0] $end
+    $var wire  8 S! out[0] [7:0] $end
+    $var wire  8 T! out[1] [7:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 32 v! P0 [31:0] $end
-    $var wire 32 w! P1 [31:0] $end
-    $var wire  8 L! out[0] [7:0] $end
-    $var wire  8 M! out[1] [7:0] $end
+    $var wire 32 !" P0 [31:0] $end
+    $var wire 32 "" P1 [31:0] $end
+    $var wire  8 U! out[0] [7:0] $end
+    $var wire  8 V! out[1] [7:0] $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire  8 N! out[0] [7:0] $end
-    $var wire  8 O! out[1] [7:0] $end
+    $var wire  8 W! out[0] [7:0] $end
+    $var wire  8 X! out[1] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 Q! i [31:0] $end
+    $var wire 32 Z! i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 R! j [31:0] $end
+     $var wire 32 [! j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire 128 S! exp [127:0] $end
+      $var wire 128 \! exp [127:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end
-  $var wire  8 y! out[0] [7:0] $end
-  $var wire  8 z! out[1] [7:0] $end
+  $var wire  8 $" out[0] [7:0] $end
+  $var wire  8 %" out[1] [7:0] $end
   $scope module sub6_9 $end
-   $var wire 32 {! P0 [31:0] $end
-   $var wire  8 y! out[0] [7:0] $end
-   $var wire  8 z! out[1] [7:0] $end
+   $var wire 32 &" P0 [31:0] $end
+   $var wire 32 '" P1 [31:0] $end
+   $var wire  8 $" out[0] [7:0] $end
+   $var wire  8 %" out[1] [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1 $end
-  $var wire  1 `" clk $end
-  $var wire  8 a" in [7:0] $end
-  $var wire  8 b" out [7:0] $end
+  $var wire  1 j" clk $end
+  $var wire  8 k" in [7:0] $end
+  $var wire  8 l" out [7:0] $end
   $scope module sub4_b $end
-   $var wire  1 `" clk $end
-   $var wire 32 8" count [31:0] $end
-   $var wire  8 }! ff [7:0] $end
-   $var wire  8 a" in [7:0] $end
-   $var wire  8 b" out [7:0] $end
-   $var wire 128 ~! sub5_in[0][0] [127:0] $end
-   $var wire 128 $" sub5_in[0][1] [127:0] $end
-   $var wire 128 (" sub5_in[0][2] [127:0] $end
-   $var wire 128 ," sub5_in[1][0] [127:0] $end
-   $var wire 128 0" sub5_in[1][1] [127:0] $end
-   $var wire 128 4" sub5_in[1][2] [127:0] $end
-   $var wire  8 T" sub5_out[0][0] [7:0] $end
-   $var wire  8 U" sub5_out[0][1] [7:0] $end
-   $var wire  8 V" sub5_out[0][2] [7:0] $end
-   $var wire  8 W" sub5_out[1][0] [7:0] $end
-   $var wire  8 X" sub5_out[1][1] [7:0] $end
-   $var wire  8 Y" sub5_out[1][2] [7:0] $end
+   $var wire 32 m" P0 [31:0] $end
+   $var real 64 n" P1 $end
+   $var real 64 p" P3 $end
+   $var wire  1 j" clk $end
+   $var wire 32 B" count [31:0] $end
+   $var wire  8 )" ff [7:0] $end
+   $var wire  8 k" in [7:0] $end
+   $var wire  8 l" out [7:0] $end
+   $var wire 128 *" sub5_in[0][0] [127:0] $end
+   $var wire 128 ." sub5_in[0][1] [127:0] $end
+   $var wire 128 2" sub5_in[0][2] [127:0] $end
+   $var wire 128 6" sub5_in[1][0] [127:0] $end
+   $var wire 128 :" sub5_in[1][1] [127:0] $end
+   $var wire 128 >" sub5_in[1][2] [127:0] $end
+   $var wire  8 ^" sub5_out[0][0] [7:0] $end
+   $var wire  8 _" sub5_out[0][1] [7:0] $end
+   $var wire  8 `" sub5_out[0][2] [7:0] $end
+   $var wire  8 a" sub5_out[1][0] [7:0] $end
+   $var wire  8 b" sub5_out[1][1] [7:0] $end
+   $var wire  8 c" sub5_out[1][2] [7:0] $end
    $scope module i_sub5 $end
-    $var wire  1 `" clk $end
-    $var wire 128 <" in[0][0] [127:0] $end
-    $var wire 128 @" in[0][1] [127:0] $end
-    $var wire 128 D" in[0][2] [127:0] $end
-    $var wire 128 H" in[1][0] [127:0] $end
-    $var wire 128 L" in[1][1] [127:0] $end
-    $var wire 128 P" in[1][2] [127:0] $end
-    $var wire  8 Z" out[0][0] [7:0] $end
-    $var wire  8 [" out[0][1] [7:0] $end
-    $var wire  8 \" out[0][2] [7:0] $end
-    $var wire  8 ]" out[1][0] [7:0] $end
-    $var wire  8 ^" out[1][1] [7:0] $end
-    $var wire  8 _" out[1][2] [7:0] $end
+    $var wire  1 j" clk $end
+    $var wire 128 F" in[0][0] [127:0] $end
+    $var wire 128 J" in[0][1] [127:0] $end
+    $var wire 128 N" in[0][2] [127:0] $end
+    $var wire 128 R" in[1][0] [127:0] $end
+    $var wire 128 V" in[1][1] [127:0] $end
+    $var wire 128 Z" in[1][2] [127:0] $end
+    $var wire  8 d" out[0][0] [7:0] $end
+    $var wire  8 e" out[0][1] [7:0] $end
+    $var wire  8 f" out[0][2] [7:0] $end
+    $var wire  8 g" out[1][0] [7:0] $end
+    $var wire  8 h" out[1][1] [7:0] $end
+    $var wire  8 i" out[1][2] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 9" i [31:0] $end
+    $var wire 32 C" i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 :" j [31:0] $end
+     $var wire 32 D" j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire  8 ;" exp [7:0] $end
+      $var wire  8 E" exp [7:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5 $end
-  $var wire  1 {" clk $end
-  $var wire 128 |" in[0][0] [127:0] $end
-  $var wire 128 "# in[0][1] [127:0] $end
-  $var wire 128 &# in[0][2] [127:0] $end
-  $var wire 128 *# in[1][0] [127:0] $end
-  $var wire 128 .# in[1][1] [127:0] $end
-  $var wire 128 2# in[1][2] [127:0] $end
-  $var wire  8 6# out[0][0] [7:0] $end
-  $var wire  8 7# out[0][1] [7:0] $end
-  $var wire  8 8# out[0][2] [7:0] $end
-  $var wire  8 9# out[1][0] [7:0] $end
-  $var wire  8 :# out[1][1] [7:0] $end
-  $var wire  8 ;# out[1][2] [7:0] $end
+  $var wire  1 ,# clk $end
+  $var wire 128 -# in[0][0] [127:0] $end
+  $var wire 128 1# in[0][1] [127:0] $end
+  $var wire 128 5# in[0][2] [127:0] $end
+  $var wire 128 9# in[1][0] [127:0] $end
+  $var wire 128 =# in[1][1] [127:0] $end
+  $var wire 128 A# in[1][2] [127:0] $end
+  $var wire  8 E# out[0][0] [7:0] $end
+  $var wire  8 F# out[0][1] [7:0] $end
+  $var wire  8 G# out[0][2] [7:0] $end
+  $var wire  8 H# out[1][0] [7:0] $end
+  $var wire  8 I# out[1][1] [7:0] $end
+  $var wire  8 J# out[1][2] [7:0] $end
   $scope module sub5 $end
-   $var wire  1 {" clk $end
-   $var wire 32 t" count [31:0] $end
-   $var wire 128 |" in[0][0] [127:0] $end
-   $var wire 128 "# in[0][1] [127:0] $end
-   $var wire 128 &# in[0][2] [127:0] $end
-   $var wire 128 *# in[1][0] [127:0] $end
-   $var wire 128 .# in[1][1] [127:0] $end
-   $var wire 128 2# in[1][2] [127:0] $end
-   $var wire  8 6# out[0][0] [7:0] $end
-   $var wire  8 7# out[0][1] [7:0] $end
-   $var wire  8 8# out[0][2] [7:0] $end
-   $var wire  8 9# out[1][0] [7:0] $end
-   $var wire  8 :# out[1][1] [7:0] $end
-   $var wire  8 ;# out[1][2] [7:0] $end
-   $var wire  8 d" val0[0] [7:0] $end
-   $var wire  8 e" val0[1] [7:0] $end
-   $var wire  8 f" val1[0] [7:0] $end
-   $var wire  8 g" val1[1] [7:0] $end
-   $var wire  8 h" val2[0] [7:0] $end
-   $var wire  8 i" val2[1] [7:0] $end
-   $var wire  8 j" val3[0] [7:0] $end
-   $var wire  8 k" val3[1] [7:0] $end
+   $var wire  1 ,# clk $end
+   $var wire 32 %# count [31:0] $end
+   $var wire 128 -# in[0][0] [127:0] $end
+   $var wire 128 1# in[0][1] [127:0] $end
+   $var wire 128 5# in[0][2] [127:0] $end
+   $var wire 128 9# in[1][0] [127:0] $end
+   $var wire 128 =# in[1][1] [127:0] $end
+   $var wire 128 A# in[1][2] [127:0] $end
+   $var wire  8 E# out[0][0] [7:0] $end
+   $var wire  8 F# out[0][1] [7:0] $end
+   $var wire  8 G# out[0][2] [7:0] $end
+   $var wire  8 H# out[1][0] [7:0] $end
+   $var wire  8 I# out[1][1] [7:0] $end
+   $var wire  8 J# out[1][2] [7:0] $end
+   $var wire  8 s" val0[0] [7:0] $end
+   $var wire  8 t" val0[1] [7:0] $end
+   $var wire  8 u" val1[0] [7:0] $end
+   $var wire  8 v" val1[1] [7:0] $end
+   $var wire  8 w" val2[0] [7:0] $end
+   $var wire  8 x" val2[1] [7:0] $end
+   $var wire  8 y" val3[0] [7:0] $end
+   $var wire  8 z" val3[1] [7:0] $end
    $scope module i_sub0 $end
-    $var wire 32 <# P0 [31:0] $end
-    $var wire 32 =# P1 [31:0] $end
-    $var wire  8 l" out[0] [7:0] $end
-    $var wire  8 m" out[1] [7:0] $end
+    $var wire 32 K# P0 [31:0] $end
+    $var wire 32 L# P1 [31:0] $end
+    $var wire  8 {" out[0] [7:0] $end
+    $var wire  8 |" out[1] [7:0] $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 32 <# P0 [31:0] $end
-    $var wire 32 =# P1 [31:0] $end
-    $var wire  8 n" out[0] [7:0] $end
-    $var wire  8 o" out[1] [7:0] $end
+    $var wire 32 K# P0 [31:0] $end
+    $var wire 32 L# P1 [31:0] $end
+    $var wire  8 }" out[0] [7:0] $end
+    $var wire  8 ~" out[1] [7:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 32 <# P0 [31:0] $end
-    $var wire 32 =# P1 [31:0] $end
-    $var wire  8 p" out[0] [7:0] $end
-    $var wire  8 q" out[1] [7:0] $end
+    $var wire 32 K# P0 [31:0] $end
+    $var wire 32 L# P1 [31:0] $end
+    $var wire  8 !# out[0] [7:0] $end
+    $var wire  8 "# out[1] [7:0] $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire  8 r" out[0] [7:0] $end
-    $var wire  8 s" out[1] [7:0] $end
+    $var wire  8 ## out[0] [7:0] $end
+    $var wire  8 $# out[1] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 u" i [31:0] $end
+    $var wire 32 &# i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 v" j [31:0] $end
+     $var wire 32 '# j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire 128 w" exp [127:0] $end
+      $var wire 128 (# exp [127:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end
-  $var wire  8 ?# out[0] [7:0] $end
-  $var wire  8 @# out[1] [7:0] $end
+  $var wire  8 N# out[0] [7:0] $end
+  $var wire  8 O# out[1] [7:0] $end
   $scope module sub6_9 $end
-   $var wire 32 A# P0 [31:0] $end
-   $var wire  8 ?# out[0] [7:0] $end
-   $var wire  8 @# out[1] [7:0] $end
+   $var wire 32 P# P0 [31:0] $end
+   $var wire 32 Q# P1 [31:0] $end
+   $var wire  8 N# out[0] [7:0] $end
+   $var wire  8 O# out[1] [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3 $end
-  $var wire  1 7& clk $end
-  $var wire  8 8& in [7:0] $end
-  $var wire  8 9& out [7:0] $end
+  $var wire  1 T& clk $end
+  $var wire  8 U& in [7:0] $end
+  $var wire  8 V& out [7:0] $end
   $scope module sub3_d $end
-   $var wire 32 =& UNPACKED_ARRAY[0] [31:0] $end
-   $var wire 32 >& UNPACKED_ARRAY[1] [31:0] $end
-   $var wire 16 ?& UNUSED [15:0] $end
-   $var wire  1 7& clk $end
-   $var wire  8 :& ff [7:0] $end
-   $var wire  8 8& in [7:0] $end
-   $var wire  8 9& out [7:0] $end
-   $var wire  8 ;& out4 [7:0] $end
-   $var wire  8 <& out4_2 [7:0] $end
+   $var wire  8 Z& P0 [7:0] $end
+   $var wire 32 [& UNPACKED_ARRAY[0] [31:0] $end
+   $var wire 32 \& UNPACKED_ARRAY[1] [31:0] $end
+   $var wire 16 ]& UNUSED [15:0] $end
+   $var wire  1 T& clk $end
+   $var wire  8 W& ff [7:0] $end
+   $var wire  8 U& in [7:0] $end
+   $var wire  8 V& out [7:0] $end
+   $var wire  8 X& out4 [7:0] $end
+   $var wire  8 Y& out4_2 [7:0] $end
    $scope module i_sub4_0 $end
-    $var wire  1 7& clk $end
-    $var wire  8 :& in [7:0] $end
-    $var wire  8 ;& out [7:0] $end
+    $var wire  1 T& clk $end
+    $var wire  8 W& in [7:0] $end
+    $var wire  8 X& out [7:0] $end
    $upscope $end
    $scope module i_sub4_1 $end
-    $var wire  1 7& clk $end
-    $var wire  8 :& in [7:0] $end
-    $var wire  8 <& out [7:0] $end
+    $var wire  1 T& clk $end
+    $var wire  8 W& in [7:0] $end
+    $var wire  8 Y& out [7:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3.sub3_d.i_sub4_0 $end
-  $var wire  1 $' clk $end
-  $var wire  8 %' in [7:0] $end
-  $var wire  8 &' out [7:0] $end
+  $var wire  1 B' clk $end
+  $var wire  8 C' in [7:0] $end
+  $var wire  8 D' out [7:0] $end
   $scope module sub4_2 $end
-   $var wire  1 $' clk $end
-   $var wire 32 Z& count [31:0] $end
-   $var wire  8 A& ff [7:0] $end
-   $var wire  8 %' in [7:0] $end
-   $var wire  8 &' out [7:0] $end
-   $var wire 128 B& sub5_in[0][0] [127:0] $end
-   $var wire 128 F& sub5_in[0][1] [127:0] $end
-   $var wire 128 J& sub5_in[0][2] [127:0] $end
-   $var wire 128 N& sub5_in[1][0] [127:0] $end
-   $var wire 128 R& sub5_in[1][1] [127:0] $end
-   $var wire 128 V& sub5_in[1][2] [127:0] $end
-   $var wire  8 v& sub5_out[0][0] [7:0] $end
-   $var wire  8 w& sub5_out[0][1] [7:0] $end
-   $var wire  8 x& sub5_out[0][2] [7:0] $end
-   $var wire  8 y& sub5_out[1][0] [7:0] $end
-   $var wire  8 z& sub5_out[1][1] [7:0] $end
-   $var wire  8 {& sub5_out[1][2] [7:0] $end
+   $var wire 32 E' P0 [31:0] $end
+   $var real 64 F' P1 $end
+   $var real 64 H' P3 $end
+   $var wire  1 B' clk $end
+   $var wire 32 x& count [31:0] $end
+   $var wire  8 _& ff [7:0] $end
+   $var wire  8 C' in [7:0] $end
+   $var wire  8 D' out [7:0] $end
+   $var wire 128 `& sub5_in[0][0] [127:0] $end
+   $var wire 128 d& sub5_in[0][1] [127:0] $end
+   $var wire 128 h& sub5_in[0][2] [127:0] $end
+   $var wire 128 l& sub5_in[1][0] [127:0] $end
+   $var wire 128 p& sub5_in[1][1] [127:0] $end
+   $var wire 128 t& sub5_in[1][2] [127:0] $end
+   $var wire  8 6' sub5_out[0][0] [7:0] $end
+   $var wire  8 7' sub5_out[0][1] [7:0] $end
+   $var wire  8 8' sub5_out[0][2] [7:0] $end
+   $var wire  8 9' sub5_out[1][0] [7:0] $end
+   $var wire  8 :' sub5_out[1][1] [7:0] $end
+   $var wire  8 ;' sub5_out[1][2] [7:0] $end
    $scope module i_sub5 $end
-    $var wire  1 $' clk $end
-    $var wire 128 ^& in[0][0] [127:0] $end
-    $var wire 128 b& in[0][1] [127:0] $end
-    $var wire 128 f& in[0][2] [127:0] $end
-    $var wire 128 j& in[1][0] [127:0] $end
-    $var wire 128 n& in[1][1] [127:0] $end
-    $var wire 128 r& in[1][2] [127:0] $end
-    $var wire  8 |& out[0][0] [7:0] $end
-    $var wire  8 }& out[0][1] [7:0] $end
-    $var wire  8 ~& out[0][2] [7:0] $end
-    $var wire  8 !' out[1][0] [7:0] $end
-    $var wire  8 "' out[1][1] [7:0] $end
-    $var wire  8 #' out[1][2] [7:0] $end
+    $var wire  1 B' clk $end
+    $var wire 128 |& in[0][0] [127:0] $end
+    $var wire 128 "' in[0][1] [127:0] $end
+    $var wire 128 &' in[0][2] [127:0] $end
+    $var wire 128 *' in[1][0] [127:0] $end
+    $var wire 128 .' in[1][1] [127:0] $end
+    $var wire 128 2' in[1][2] [127:0] $end
+    $var wire  8 <' out[0][0] [7:0] $end
+    $var wire  8 =' out[0][1] [7:0] $end
+    $var wire  8 >' out[0][2] [7:0] $end
+    $var wire  8 ?' out[1][0] [7:0] $end
+    $var wire  8 @' out[1][1] [7:0] $end
+    $var wire  8 A' out[1][2] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 [& i [31:0] $end
+    $var wire 32 y& i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 \& j [31:0] $end
+     $var wire 32 z& j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire  8 ]& exp [7:0] $end
+      $var wire  8 {& exp [7:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5 $end
-  $var wire  1 ?' clk $end
-  $var wire 128 @' in[0][0] [127:0] $end
-  $var wire 128 D' in[0][1] [127:0] $end
-  $var wire 128 H' in[0][2] [127:0] $end
-  $var wire 128 L' in[1][0] [127:0] $end
-  $var wire 128 P' in[1][1] [127:0] $end
-  $var wire 128 T' in[1][2] [127:0] $end
-  $var wire  8 X' out[0][0] [7:0] $end
-  $var wire  8 Y' out[0][1] [7:0] $end
-  $var wire  8 Z' out[0][2] [7:0] $end
-  $var wire  8 [' out[1][0] [7:0] $end
-  $var wire  8 \' out[1][1] [7:0] $end
-  $var wire  8 ]' out[1][2] [7:0] $end
+  $var wire  1 b' clk $end
+  $var wire 128 c' in[0][0] [127:0] $end
+  $var wire 128 g' in[0][1] [127:0] $end
+  $var wire 128 k' in[0][2] [127:0] $end
+  $var wire 128 o' in[1][0] [127:0] $end
+  $var wire 128 s' in[1][1] [127:0] $end
+  $var wire 128 w' in[1][2] [127:0] $end
+  $var wire  8 {' out[0][0] [7:0] $end
+  $var wire  8 |' out[0][1] [7:0] $end
+  $var wire  8 }' out[0][2] [7:0] $end
+  $var wire  8 ~' out[1][0] [7:0] $end
+  $var wire  8 !( out[1][1] [7:0] $end
+  $var wire  8 "( out[1][2] [7:0] $end
   $scope module sub5 $end
-   $var wire  1 ?' clk $end
-   $var wire 32 8' count [31:0] $end
-   $var wire 128 @' in[0][0] [127:0] $end
-   $var wire 128 D' in[0][1] [127:0] $end
-   $var wire 128 H' in[0][2] [127:0] $end
-   $var wire 128 L' in[1][0] [127:0] $end
-   $var wire 128 P' in[1][1] [127:0] $end
-   $var wire 128 T' in[1][2] [127:0] $end
-   $var wire  8 X' out[0][0] [7:0] $end
-   $var wire  8 Y' out[0][1] [7:0] $end
-   $var wire  8 Z' out[0][2] [7:0] $end
-   $var wire  8 [' out[1][0] [7:0] $end
-   $var wire  8 \' out[1][1] [7:0] $end
-   $var wire  8 ]' out[1][2] [7:0] $end
-   $var wire  8 (' val0[0] [7:0] $end
-   $var wire  8 )' val0[1] [7:0] $end
-   $var wire  8 *' val1[0] [7:0] $end
-   $var wire  8 +' val1[1] [7:0] $end
-   $var wire  8 ,' val2[0] [7:0] $end
-   $var wire  8 -' val2[1] [7:0] $end
-   $var wire  8 .' val3[0] [7:0] $end
-   $var wire  8 /' val3[1] [7:0] $end
+   $var wire  1 b' clk $end
+   $var wire 32 [' count [31:0] $end
+   $var wire 128 c' in[0][0] [127:0] $end
+   $var wire 128 g' in[0][1] [127:0] $end
+   $var wire 128 k' in[0][2] [127:0] $end
+   $var wire 128 o' in[1][0] [127:0] $end
+   $var wire 128 s' in[1][1] [127:0] $end
+   $var wire 128 w' in[1][2] [127:0] $end
+   $var wire  8 {' out[0][0] [7:0] $end
+   $var wire  8 |' out[0][1] [7:0] $end
+   $var wire  8 }' out[0][2] [7:0] $end
+   $var wire  8 ~' out[1][0] [7:0] $end
+   $var wire  8 !( out[1][1] [7:0] $end
+   $var wire  8 "( out[1][2] [7:0] $end
+   $var wire  8 K' val0[0] [7:0] $end
+   $var wire  8 L' val0[1] [7:0] $end
+   $var wire  8 M' val1[0] [7:0] $end
+   $var wire  8 N' val1[1] [7:0] $end
+   $var wire  8 O' val2[0] [7:0] $end
+   $var wire  8 P' val2[1] [7:0] $end
+   $var wire  8 Q' val3[0] [7:0] $end
+   $var wire  8 R' val3[1] [7:0] $end
    $scope module i_sub0 $end
-    $var wire 32 ^' P0 [31:0] $end
-    $var wire 32 _' P1 [31:0] $end
-    $var wire  8 0' out[0] [7:0] $end
-    $var wire  8 1' out[1] [7:0] $end
+    $var wire 32 #( P0 [31:0] $end
+    $var wire 32 $( P1 [31:0] $end
+    $var wire  8 S' out[0] [7:0] $end
+    $var wire  8 T' out[1] [7:0] $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 32 ^' P0 [31:0] $end
-    $var wire 32 _' P1 [31:0] $end
-    $var wire  8 2' out[0] [7:0] $end
-    $var wire  8 3' out[1] [7:0] $end
+    $var wire 32 #( P0 [31:0] $end
+    $var wire 32 $( P1 [31:0] $end
+    $var wire  8 U' out[0] [7:0] $end
+    $var wire  8 V' out[1] [7:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 32 ^' P0 [31:0] $end
-    $var wire 32 _' P1 [31:0] $end
-    $var wire  8 4' out[0] [7:0] $end
-    $var wire  8 5' out[1] [7:0] $end
+    $var wire 32 #( P0 [31:0] $end
+    $var wire 32 $( P1 [31:0] $end
+    $var wire  8 W' out[0] [7:0] $end
+    $var wire  8 X' out[1] [7:0] $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire  8 6' out[0] [7:0] $end
-    $var wire  8 7' out[1] [7:0] $end
+    $var wire  8 Y' out[0] [7:0] $end
+    $var wire  8 Z' out[1] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 9' i [31:0] $end
+    $var wire 32 \' i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 :' j [31:0] $end
+     $var wire 32 ]' j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire 128 ;' exp [127:0] $end
+      $var wire 128 ^' exp [127:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end
-  $var wire  8 a' out[0] [7:0] $end
-  $var wire  8 b' out[1] [7:0] $end
+  $var wire  8 &( out[0] [7:0] $end
+  $var wire  8 '( out[1] [7:0] $end
   $scope module sub6_9 $end
-   $var wire 32 c' P0 [31:0] $end
-   $var wire  8 a' out[0] [7:0] $end
-   $var wire  8 b' out[1] [7:0] $end
+   $var wire 32 (( P0 [31:0] $end
+   $var wire 32 )( P1 [31:0] $end
+   $var wire  8 &( out[0] [7:0] $end
+   $var wire  8 '( out[1] [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3.sub3_d.i_sub4_1 $end
-  $var wire  1 H( clk $end
-  $var wire  8 I( in [7:0] $end
-  $var wire  8 J( out [7:0] $end
+  $var wire  1 l( clk $end
+  $var wire  8 m( in [7:0] $end
+  $var wire  8 n( out [7:0] $end
   $scope module sub4_b $end
-   $var wire  1 H( clk $end
-   $var wire 32 ~' count [31:0] $end
-   $var wire  8 e' ff [7:0] $end
-   $var wire  8 I( in [7:0] $end
-   $var wire  8 J( out [7:0] $end
-   $var wire 128 f' sub5_in[0][0] [127:0] $end
-   $var wire 128 j' sub5_in[0][1] [127:0] $end
-   $var wire 128 n' sub5_in[0][2] [127:0] $end
-   $var wire 128 r' sub5_in[1][0] [127:0] $end
-   $var wire 128 v' sub5_in[1][1] [127:0] $end
-   $var wire 128 z' sub5_in[1][2] [127:0] $end
-   $var wire  8 <( sub5_out[0][0] [7:0] $end
-   $var wire  8 =( sub5_out[0][1] [7:0] $end
-   $var wire  8 >( sub5_out[0][2] [7:0] $end
-   $var wire  8 ?( sub5_out[1][0] [7:0] $end
-   $var wire  8 @( sub5_out[1][1] [7:0] $end
-   $var wire  8 A( sub5_out[1][2] [7:0] $end
+   $var wire 32 o( P0 [31:0] $end
+   $var real 64 p( P1 $end
+   $var real 64 r( P3 $end
+   $var wire  1 l( clk $end
+   $var wire 32 D( count [31:0] $end
+   $var wire  8 +( ff [7:0] $end
+   $var wire  8 m( in [7:0] $end
+   $var wire  8 n( out [7:0] $end
+   $var wire 128 ,( sub5_in[0][0] [127:0] $end
+   $var wire 128 0( sub5_in[0][1] [127:0] $end
+   $var wire 128 4( sub5_in[0][2] [127:0] $end
+   $var wire 128 8( sub5_in[1][0] [127:0] $end
+   $var wire 128 <( sub5_in[1][1] [127:0] $end
+   $var wire 128 @( sub5_in[1][2] [127:0] $end
+   $var wire  8 `( sub5_out[0][0] [7:0] $end
+   $var wire  8 a( sub5_out[0][1] [7:0] $end
+   $var wire  8 b( sub5_out[0][2] [7:0] $end
+   $var wire  8 c( sub5_out[1][0] [7:0] $end
+   $var wire  8 d( sub5_out[1][1] [7:0] $end
+   $var wire  8 e( sub5_out[1][2] [7:0] $end
    $scope module i_sub5 $end
-    $var wire  1 H( clk $end
-    $var wire 128 $( in[0][0] [127:0] $end
-    $var wire 128 (( in[0][1] [127:0] $end
-    $var wire 128 ,( in[0][2] [127:0] $end
-    $var wire 128 0( in[1][0] [127:0] $end
-    $var wire 128 4( in[1][1] [127:0] $end
-    $var wire 128 8( in[1][2] [127:0] $end
-    $var wire  8 B( out[0][0] [7:0] $end
-    $var wire  8 C( out[0][1] [7:0] $end
-    $var wire  8 D( out[0][2] [7:0] $end
-    $var wire  8 E( out[1][0] [7:0] $end
-    $var wire  8 F( out[1][1] [7:0] $end
-    $var wire  8 G( out[1][2] [7:0] $end
+    $var wire  1 l( clk $end
+    $var wire 128 H( in[0][0] [127:0] $end
+    $var wire 128 L( in[0][1] [127:0] $end
+    $var wire 128 P( in[0][2] [127:0] $end
+    $var wire 128 T( in[1][0] [127:0] $end
+    $var wire 128 X( in[1][1] [127:0] $end
+    $var wire 128 \( in[1][2] [127:0] $end
+    $var wire  8 f( out[0][0] [7:0] $end
+    $var wire  8 g( out[0][1] [7:0] $end
+    $var wire  8 h( out[0][2] [7:0] $end
+    $var wire  8 i( out[1][0] [7:0] $end
+    $var wire  8 j( out[1][1] [7:0] $end
+    $var wire  8 k( out[1][2] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 !( i [31:0] $end
+    $var wire 32 E( i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 "( j [31:0] $end
+     $var wire 32 F( j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire  8 #( exp [7:0] $end
+      $var wire  8 G( exp [7:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5 $end
-  $var wire  1 c( clk $end
-  $var wire 128 d( in[0][0] [127:0] $end
-  $var wire 128 h( in[0][1] [127:0] $end
-  $var wire 128 l( in[0][2] [127:0] $end
-  $var wire 128 p( in[1][0] [127:0] $end
-  $var wire 128 t( in[1][1] [127:0] $end
-  $var wire 128 x( in[1][2] [127:0] $end
-  $var wire  8 |( out[0][0] [7:0] $end
-  $var wire  8 }( out[0][1] [7:0] $end
-  $var wire  8 ~( out[0][2] [7:0] $end
-  $var wire  8 !) out[1][0] [7:0] $end
-  $var wire  8 ") out[1][1] [7:0] $end
-  $var wire  8 #) out[1][2] [7:0] $end
+  $var wire  1 .) clk $end
+  $var wire 128 /) in[0][0] [127:0] $end
+  $var wire 128 3) in[0][1] [127:0] $end
+  $var wire 128 7) in[0][2] [127:0] $end
+  $var wire 128 ;) in[1][0] [127:0] $end
+  $var wire 128 ?) in[1][1] [127:0] $end
+  $var wire 128 C) in[1][2] [127:0] $end
+  $var wire  8 G) out[0][0] [7:0] $end
+  $var wire  8 H) out[0][1] [7:0] $end
+  $var wire  8 I) out[0][2] [7:0] $end
+  $var wire  8 J) out[1][0] [7:0] $end
+  $var wire  8 K) out[1][1] [7:0] $end
+  $var wire  8 L) out[1][2] [7:0] $end
   $scope module sub5 $end
-   $var wire  1 c( clk $end
-   $var wire 32 \( count [31:0] $end
-   $var wire 128 d( in[0][0] [127:0] $end
-   $var wire 128 h( in[0][1] [127:0] $end
-   $var wire 128 l( in[0][2] [127:0] $end
-   $var wire 128 p( in[1][0] [127:0] $end
-   $var wire 128 t( in[1][1] [127:0] $end
-   $var wire 128 x( in[1][2] [127:0] $end
-   $var wire  8 |( out[0][0] [7:0] $end
-   $var wire  8 }( out[0][1] [7:0] $end
-   $var wire  8 ~( out[0][2] [7:0] $end
-   $var wire  8 !) out[1][0] [7:0] $end
-   $var wire  8 ") out[1][1] [7:0] $end
-   $var wire  8 #) out[1][2] [7:0] $end
-   $var wire  8 L( val0[0] [7:0] $end
-   $var wire  8 M( val0[1] [7:0] $end
-   $var wire  8 N( val1[0] [7:0] $end
-   $var wire  8 O( val1[1] [7:0] $end
-   $var wire  8 P( val2[0] [7:0] $end
-   $var wire  8 Q( val2[1] [7:0] $end
-   $var wire  8 R( val3[0] [7:0] $end
-   $var wire  8 S( val3[1] [7:0] $end
+   $var wire  1 .) clk $end
+   $var wire 32 ') count [31:0] $end
+   $var wire 128 /) in[0][0] [127:0] $end
+   $var wire 128 3) in[0][1] [127:0] $end
+   $var wire 128 7) in[0][2] [127:0] $end
+   $var wire 128 ;) in[1][0] [127:0] $end
+   $var wire 128 ?) in[1][1] [127:0] $end
+   $var wire 128 C) in[1][2] [127:0] $end
+   $var wire  8 G) out[0][0] [7:0] $end
+   $var wire  8 H) out[0][1] [7:0] $end
+   $var wire  8 I) out[0][2] [7:0] $end
+   $var wire  8 J) out[1][0] [7:0] $end
+   $var wire  8 K) out[1][1] [7:0] $end
+   $var wire  8 L) out[1][2] [7:0] $end
+   $var wire  8 u( val0[0] [7:0] $end
+   $var wire  8 v( val0[1] [7:0] $end
+   $var wire  8 w( val1[0] [7:0] $end
+   $var wire  8 x( val1[1] [7:0] $end
+   $var wire  8 y( val2[0] [7:0] $end
+   $var wire  8 z( val2[1] [7:0] $end
+   $var wire  8 {( val3[0] [7:0] $end
+   $var wire  8 |( val3[1] [7:0] $end
    $scope module i_sub0 $end
-    $var wire 32 $) P0 [31:0] $end
-    $var wire 32 %) P1 [31:0] $end
-    $var wire  8 T( out[0] [7:0] $end
-    $var wire  8 U( out[1] [7:0] $end
+    $var wire 32 M) P0 [31:0] $end
+    $var wire 32 N) P1 [31:0] $end
+    $var wire  8 }( out[0] [7:0] $end
+    $var wire  8 ~( out[1] [7:0] $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 32 $) P0 [31:0] $end
-    $var wire 32 %) P1 [31:0] $end
-    $var wire  8 V( out[0] [7:0] $end
-    $var wire  8 W( out[1] [7:0] $end
+    $var wire 32 M) P0 [31:0] $end
+    $var wire 32 N) P1 [31:0] $end
+    $var wire  8 !) out[0] [7:0] $end
+    $var wire  8 ") out[1] [7:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 32 $) P0 [31:0] $end
-    $var wire 32 %) P1 [31:0] $end
-    $var wire  8 X( out[0] [7:0] $end
-    $var wire  8 Y( out[1] [7:0] $end
+    $var wire 32 M) P0 [31:0] $end
+    $var wire 32 N) P1 [31:0] $end
+    $var wire  8 #) out[0] [7:0] $end
+    $var wire  8 $) out[1] [7:0] $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire  8 Z( out[0] [7:0] $end
-    $var wire  8 [( out[1] [7:0] $end
+    $var wire  8 %) out[0] [7:0] $end
+    $var wire  8 &) out[1] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 ]( i [31:0] $end
+    $var wire 32 () i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 ^( j [31:0] $end
+     $var wire 32 )) j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire 128 _( exp [127:0] $end
+      $var wire 128 *) exp [127:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end
-  $var wire  8 ') out[0] [7:0] $end
-  $var wire  8 () out[1] [7:0] $end
+  $var wire  8 P) out[0] [7:0] $end
+  $var wire  8 Q) out[1] [7:0] $end
   $scope module sub6_9 $end
-   $var wire 32 )) P0 [31:0] $end
-   $var wire  8 ') out[0] [7:0] $end
-   $var wire  8 () out[1] [7:0] $end
+   $var wire 32 R) P0 [31:0] $end
+   $var wire 32 S) P1 [31:0] $end
+   $var wire  8 P) out[0] [7:0] $end
+   $var wire  8 Q) out[1] [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2 $end
-  $var wire  1 C# clk $end
-  $var wire  8 D# in [7:0] $end
-  $var wire  8 E# out [7:0] $end
+  $var wire  1 S# clk $end
+  $var wire  8 T# in [7:0] $end
+  $var wire  8 U# out [7:0] $end
   $scope module sub3_2 $end
-   $var wire 32 I# UNPACKED_ARRAY[0] [31:0] $end
-   $var wire 32 J# UNPACKED_ARRAY[1] [31:0] $end
-   $var wire 16 K# UNUSED [15:0] $end
-   $var wire  1 C# clk $end
-   $var wire  8 F# ff [7:0] $end
-   $var wire  8 D# in [7:0] $end
-   $var wire  8 E# out [7:0] $end
-   $var wire  8 G# out4 [7:0] $end
-   $var wire  8 H# out4_2 [7:0] $end
+   $var wire  8 Y# P0 [7:0] $end
+   $var wire 32 Z# UNPACKED_ARRAY[0] [31:0] $end
+   $var wire 32 [# UNPACKED_ARRAY[1] [31:0] $end
+   $var wire 16 \# UNUSED [15:0] $end
+   $var wire  1 S# clk $end
+   $var wire  8 V# ff [7:0] $end
+   $var wire  8 T# in [7:0] $end
+   $var wire  8 U# out [7:0] $end
+   $var wire  8 W# out4 [7:0] $end
+   $var wire  8 X# out4_2 [7:0] $end
    $scope module i_sub4_0 $end
-    $var wire  1 C# clk $end
-    $var wire  8 F# in [7:0] $end
-    $var wire  8 G# out [7:0] $end
+    $var wire  1 S# clk $end
+    $var wire  8 V# in [7:0] $end
+    $var wire  8 W# out [7:0] $end
    $upscope $end
    $scope module i_sub4_1 $end
-    $var wire  1 C# clk $end
-    $var wire  8 F# in [7:0] $end
-    $var wire  8 H# out [7:0] $end
+    $var wire  1 S# clk $end
+    $var wire  8 V# in [7:0] $end
+    $var wire  8 X# out [7:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2.sub3_2.i_sub4_0 $end
-  $var wire  1 0$ clk $end
-  $var wire  8 1$ in [7:0] $end
-  $var wire  8 2$ out [7:0] $end
+  $var wire  1 A$ clk $end
+  $var wire  8 B$ in [7:0] $end
+  $var wire  8 C$ out [7:0] $end
   $scope module sub4_2 $end
-   $var wire  1 0$ clk $end
-   $var wire 32 f# count [31:0] $end
-   $var wire  8 M# ff [7:0] $end
-   $var wire  8 1$ in [7:0] $end
-   $var wire  8 2$ out [7:0] $end
-   $var wire 128 N# sub5_in[0][0] [127:0] $end
-   $var wire 128 R# sub5_in[0][1] [127:0] $end
-   $var wire 128 V# sub5_in[0][2] [127:0] $end
-   $var wire 128 Z# sub5_in[1][0] [127:0] $end
-   $var wire 128 ^# sub5_in[1][1] [127:0] $end
-   $var wire 128 b# sub5_in[1][2] [127:0] $end
-   $var wire  8 $$ sub5_out[0][0] [7:0] $end
-   $var wire  8 %$ sub5_out[0][1] [7:0] $end
-   $var wire  8 &$ sub5_out[0][2] [7:0] $end
-   $var wire  8 '$ sub5_out[1][0] [7:0] $end
-   $var wire  8 ($ sub5_out[1][1] [7:0] $end
-   $var wire  8 )$ sub5_out[1][2] [7:0] $end
+   $var wire 32 D$ P0 [31:0] $end
+   $var real 64 E$ P1 $end
+   $var real 64 G$ P3 $end
+   $var wire  1 A$ clk $end
+   $var wire 32 w# count [31:0] $end
+   $var wire  8 ^# ff [7:0] $end
+   $var wire  8 B$ in [7:0] $end
+   $var wire  8 C$ out [7:0] $end
+   $var wire 128 _# sub5_in[0][0] [127:0] $end
+   $var wire 128 c# sub5_in[0][1] [127:0] $end
+   $var wire 128 g# sub5_in[0][2] [127:0] $end
+   $var wire 128 k# sub5_in[1][0] [127:0] $end
+   $var wire 128 o# sub5_in[1][1] [127:0] $end
+   $var wire 128 s# sub5_in[1][2] [127:0] $end
+   $var wire  8 5$ sub5_out[0][0] [7:0] $end
+   $var wire  8 6$ sub5_out[0][1] [7:0] $end
+   $var wire  8 7$ sub5_out[0][2] [7:0] $end
+   $var wire  8 8$ sub5_out[1][0] [7:0] $end
+   $var wire  8 9$ sub5_out[1][1] [7:0] $end
+   $var wire  8 :$ sub5_out[1][2] [7:0] $end
    $scope module i_sub5 $end
-    $var wire  1 0$ clk $end
-    $var wire 128 j# in[0][0] [127:0] $end
-    $var wire 128 n# in[0][1] [127:0] $end
-    $var wire 128 r# in[0][2] [127:0] $end
-    $var wire 128 v# in[1][0] [127:0] $end
-    $var wire 128 z# in[1][1] [127:0] $end
-    $var wire 128 ~# in[1][2] [127:0] $end
-    $var wire  8 *$ out[0][0] [7:0] $end
-    $var wire  8 +$ out[0][1] [7:0] $end
-    $var wire  8 ,$ out[0][2] [7:0] $end
-    $var wire  8 -$ out[1][0] [7:0] $end
-    $var wire  8 .$ out[1][1] [7:0] $end
-    $var wire  8 /$ out[1][2] [7:0] $end
+    $var wire  1 A$ clk $end
+    $var wire 128 {# in[0][0] [127:0] $end
+    $var wire 128 !$ in[0][1] [127:0] $end
+    $var wire 128 %$ in[0][2] [127:0] $end
+    $var wire 128 )$ in[1][0] [127:0] $end
+    $var wire 128 -$ in[1][1] [127:0] $end
+    $var wire 128 1$ in[1][2] [127:0] $end
+    $var wire  8 ;$ out[0][0] [7:0] $end
+    $var wire  8 <$ out[0][1] [7:0] $end
+    $var wire  8 =$ out[0][2] [7:0] $end
+    $var wire  8 >$ out[1][0] [7:0] $end
+    $var wire  8 ?$ out[1][1] [7:0] $end
+    $var wire  8 @$ out[1][2] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 g# i [31:0] $end
+    $var wire 32 x# i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 h# j [31:0] $end
+     $var wire 32 y# j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire  8 i# exp [7:0] $end
+      $var wire  8 z# exp [7:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5 $end
-  $var wire  1 K$ clk $end
-  $var wire 128 L$ in[0][0] [127:0] $end
-  $var wire 128 P$ in[0][1] [127:0] $end
-  $var wire 128 T$ in[0][2] [127:0] $end
-  $var wire 128 X$ in[1][0] [127:0] $end
-  $var wire 128 \$ in[1][1] [127:0] $end
-  $var wire 128 `$ in[1][2] [127:0] $end
-  $var wire  8 d$ out[0][0] [7:0] $end
-  $var wire  8 e$ out[0][1] [7:0] $end
-  $var wire  8 f$ out[0][2] [7:0] $end
-  $var wire  8 g$ out[1][0] [7:0] $end
-  $var wire  8 h$ out[1][1] [7:0] $end
-  $var wire  8 i$ out[1][2] [7:0] $end
+  $var wire  1 a$ clk $end
+  $var wire 128 b$ in[0][0] [127:0] $end
+  $var wire 128 f$ in[0][1] [127:0] $end
+  $var wire 128 j$ in[0][2] [127:0] $end
+  $var wire 128 n$ in[1][0] [127:0] $end
+  $var wire 128 r$ in[1][1] [127:0] $end
+  $var wire 128 v$ in[1][2] [127:0] $end
+  $var wire  8 z$ out[0][0] [7:0] $end
+  $var wire  8 {$ out[0][1] [7:0] $end
+  $var wire  8 |$ out[0][2] [7:0] $end
+  $var wire  8 }$ out[1][0] [7:0] $end
+  $var wire  8 ~$ out[1][1] [7:0] $end
+  $var wire  8 !% out[1][2] [7:0] $end
   $scope module sub5 $end
-   $var wire  1 K$ clk $end
-   $var wire 32 D$ count [31:0] $end
-   $var wire 128 L$ in[0][0] [127:0] $end
-   $var wire 128 P$ in[0][1] [127:0] $end
-   $var wire 128 T$ in[0][2] [127:0] $end
-   $var wire 128 X$ in[1][0] [127:0] $end
-   $var wire 128 \$ in[1][1] [127:0] $end
-   $var wire 128 `$ in[1][2] [127:0] $end
-   $var wire  8 d$ out[0][0] [7:0] $end
-   $var wire  8 e$ out[0][1] [7:0] $end
-   $var wire  8 f$ out[0][2] [7:0] $end
-   $var wire  8 g$ out[1][0] [7:0] $end
-   $var wire  8 h$ out[1][1] [7:0] $end
-   $var wire  8 i$ out[1][2] [7:0] $end
-   $var wire  8 4$ val0[0] [7:0] $end
-   $var wire  8 5$ val0[1] [7:0] $end
-   $var wire  8 6$ val1[0] [7:0] $end
-   $var wire  8 7$ val1[1] [7:0] $end
-   $var wire  8 8$ val2[0] [7:0] $end
-   $var wire  8 9$ val2[1] [7:0] $end
-   $var wire  8 :$ val3[0] [7:0] $end
-   $var wire  8 ;$ val3[1] [7:0] $end
+   $var wire  1 a$ clk $end
+   $var wire 32 Z$ count [31:0] $end
+   $var wire 128 b$ in[0][0] [127:0] $end
+   $var wire 128 f$ in[0][1] [127:0] $end
+   $var wire 128 j$ in[0][2] [127:0] $end
+   $var wire 128 n$ in[1][0] [127:0] $end
+   $var wire 128 r$ in[1][1] [127:0] $end
+   $var wire 128 v$ in[1][2] [127:0] $end
+   $var wire  8 z$ out[0][0] [7:0] $end
+   $var wire  8 {$ out[0][1] [7:0] $end
+   $var wire  8 |$ out[0][2] [7:0] $end
+   $var wire  8 }$ out[1][0] [7:0] $end
+   $var wire  8 ~$ out[1][1] [7:0] $end
+   $var wire  8 !% out[1][2] [7:0] $end
+   $var wire  8 J$ val0[0] [7:0] $end
+   $var wire  8 K$ val0[1] [7:0] $end
+   $var wire  8 L$ val1[0] [7:0] $end
+   $var wire  8 M$ val1[1] [7:0] $end
+   $var wire  8 N$ val2[0] [7:0] $end
+   $var wire  8 O$ val2[1] [7:0] $end
+   $var wire  8 P$ val3[0] [7:0] $end
+   $var wire  8 Q$ val3[1] [7:0] $end
    $scope module i_sub0 $end
-    $var wire 32 j$ P0 [31:0] $end
-    $var wire 32 k$ P1 [31:0] $end
-    $var wire  8 <$ out[0] [7:0] $end
-    $var wire  8 =$ out[1] [7:0] $end
+    $var wire 32 "% P0 [31:0] $end
+    $var wire 32 #% P1 [31:0] $end
+    $var wire  8 R$ out[0] [7:0] $end
+    $var wire  8 S$ out[1] [7:0] $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 32 j$ P0 [31:0] $end
-    $var wire 32 k$ P1 [31:0] $end
-    $var wire  8 >$ out[0] [7:0] $end
-    $var wire  8 ?$ out[1] [7:0] $end
+    $var wire 32 "% P0 [31:0] $end
+    $var wire 32 #% P1 [31:0] $end
+    $var wire  8 T$ out[0] [7:0] $end
+    $var wire  8 U$ out[1] [7:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 32 j$ P0 [31:0] $end
-    $var wire 32 k$ P1 [31:0] $end
-    $var wire  8 @$ out[0] [7:0] $end
-    $var wire  8 A$ out[1] [7:0] $end
+    $var wire 32 "% P0 [31:0] $end
+    $var wire 32 #% P1 [31:0] $end
+    $var wire  8 V$ out[0] [7:0] $end
+    $var wire  8 W$ out[1] [7:0] $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire  8 B$ out[0] [7:0] $end
-    $var wire  8 C$ out[1] [7:0] $end
+    $var wire  8 X$ out[0] [7:0] $end
+    $var wire  8 Y$ out[1] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 E$ i [31:0] $end
+    $var wire 32 [$ i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 F$ j [31:0] $end
+     $var wire 32 \$ j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire 128 G$ exp [127:0] $end
+      $var wire 128 ]$ exp [127:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end
-  $var wire  8 m$ out[0] [7:0] $end
-  $var wire  8 n$ out[1] [7:0] $end
+  $var wire  8 %% out[0] [7:0] $end
+  $var wire  8 &% out[1] [7:0] $end
   $scope module sub6_9 $end
-   $var wire 32 o$ P0 [31:0] $end
-   $var wire  8 m$ out[0] [7:0] $end
-   $var wire  8 n$ out[1] [7:0] $end
+   $var wire 32 '% P0 [31:0] $end
+   $var wire 32 (% P1 [31:0] $end
+   $var wire  8 %% out[0] [7:0] $end
+   $var wire  8 &% out[1] [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2.sub3_2.i_sub4_1 $end
-  $var wire  1 T% clk $end
-  $var wire  8 U% in [7:0] $end
-  $var wire  8 V% out [7:0] $end
+  $var wire  1 k% clk $end
+  $var wire  8 l% in [7:0] $end
+  $var wire  8 m% out [7:0] $end
   $scope module sub4_b $end
-   $var wire  1 T% clk $end
-   $var wire 32 ,% count [31:0] $end
-   $var wire  8 q$ ff [7:0] $end
-   $var wire  8 U% in [7:0] $end
-   $var wire  8 V% out [7:0] $end
-   $var wire 128 r$ sub5_in[0][0] [127:0] $end
-   $var wire 128 v$ sub5_in[0][1] [127:0] $end
-   $var wire 128 z$ sub5_in[0][2] [127:0] $end
-   $var wire 128 ~$ sub5_in[1][0] [127:0] $end
-   $var wire 128 $% sub5_in[1][1] [127:0] $end
-   $var wire 128 (% sub5_in[1][2] [127:0] $end
-   $var wire  8 H% sub5_out[0][0] [7:0] $end
-   $var wire  8 I% sub5_out[0][1] [7:0] $end
-   $var wire  8 J% sub5_out[0][2] [7:0] $end
-   $var wire  8 K% sub5_out[1][0] [7:0] $end
-   $var wire  8 L% sub5_out[1][1] [7:0] $end
-   $var wire  8 M% sub5_out[1][2] [7:0] $end
+   $var wire 32 n% P0 [31:0] $end
+   $var real 64 o% P1 $end
+   $var real 64 q% P3 $end
+   $var wire  1 k% clk $end
+   $var wire 32 C% count [31:0] $end
+   $var wire  8 *% ff [7:0] $end
+   $var wire  8 l% in [7:0] $end
+   $var wire  8 m% out [7:0] $end
+   $var wire 128 +% sub5_in[0][0] [127:0] $end
+   $var wire 128 /% sub5_in[0][1] [127:0] $end
+   $var wire 128 3% sub5_in[0][2] [127:0] $end
+   $var wire 128 7% sub5_in[1][0] [127:0] $end
+   $var wire 128 ;% sub5_in[1][1] [127:0] $end
+   $var wire 128 ?% sub5_in[1][2] [127:0] $end
+   $var wire  8 _% sub5_out[0][0] [7:0] $end
+   $var wire  8 `% sub5_out[0][1] [7:0] $end
+   $var wire  8 a% sub5_out[0][2] [7:0] $end
+   $var wire  8 b% sub5_out[1][0] [7:0] $end
+   $var wire  8 c% sub5_out[1][1] [7:0] $end
+   $var wire  8 d% sub5_out[1][2] [7:0] $end
    $scope module i_sub5 $end
-    $var wire  1 T% clk $end
-    $var wire 128 0% in[0][0] [127:0] $end
-    $var wire 128 4% in[0][1] [127:0] $end
-    $var wire 128 8% in[0][2] [127:0] $end
-    $var wire 128 <% in[1][0] [127:0] $end
-    $var wire 128 @% in[1][1] [127:0] $end
-    $var wire 128 D% in[1][2] [127:0] $end
-    $var wire  8 N% out[0][0] [7:0] $end
-    $var wire  8 O% out[0][1] [7:0] $end
-    $var wire  8 P% out[0][2] [7:0] $end
-    $var wire  8 Q% out[1][0] [7:0] $end
-    $var wire  8 R% out[1][1] [7:0] $end
-    $var wire  8 S% out[1][2] [7:0] $end
+    $var wire  1 k% clk $end
+    $var wire 128 G% in[0][0] [127:0] $end
+    $var wire 128 K% in[0][1] [127:0] $end
+    $var wire 128 O% in[0][2] [127:0] $end
+    $var wire 128 S% in[1][0] [127:0] $end
+    $var wire 128 W% in[1][1] [127:0] $end
+    $var wire 128 [% in[1][2] [127:0] $end
+    $var wire  8 e% out[0][0] [7:0] $end
+    $var wire  8 f% out[0][1] [7:0] $end
+    $var wire  8 g% out[0][2] [7:0] $end
+    $var wire  8 h% out[1][0] [7:0] $end
+    $var wire  8 i% out[1][1] [7:0] $end
+    $var wire  8 j% out[1][2] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 -% i [31:0] $end
+    $var wire 32 D% i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 .% j [31:0] $end
+     $var wire 32 E% j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire  8 /% exp [7:0] $end
+      $var wire  8 F% exp [7:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5 $end
-  $var wire  1 o% clk $end
-  $var wire 128 p% in[0][0] [127:0] $end
-  $var wire 128 t% in[0][1] [127:0] $end
-  $var wire 128 x% in[0][2] [127:0] $end
-  $var wire 128 |% in[1][0] [127:0] $end
-  $var wire 128 "& in[1][1] [127:0] $end
-  $var wire 128 && in[1][2] [127:0] $end
-  $var wire  8 *& out[0][0] [7:0] $end
-  $var wire  8 +& out[0][1] [7:0] $end
-  $var wire  8 ,& out[0][2] [7:0] $end
-  $var wire  8 -& out[1][0] [7:0] $end
-  $var wire  8 .& out[1][1] [7:0] $end
-  $var wire  8 /& out[1][2] [7:0] $end
+  $var wire  1 -& clk $end
+  $var wire 128 .& in[0][0] [127:0] $end
+  $var wire 128 2& in[0][1] [127:0] $end
+  $var wire 128 6& in[0][2] [127:0] $end
+  $var wire 128 :& in[1][0] [127:0] $end
+  $var wire 128 >& in[1][1] [127:0] $end
+  $var wire 128 B& in[1][2] [127:0] $end
+  $var wire  8 F& out[0][0] [7:0] $end
+  $var wire  8 G& out[0][1] [7:0] $end
+  $var wire  8 H& out[0][2] [7:0] $end
+  $var wire  8 I& out[1][0] [7:0] $end
+  $var wire  8 J& out[1][1] [7:0] $end
+  $var wire  8 K& out[1][2] [7:0] $end
   $scope module sub5 $end
-   $var wire  1 o% clk $end
-   $var wire 32 h% count [31:0] $end
-   $var wire 128 p% in[0][0] [127:0] $end
-   $var wire 128 t% in[0][1] [127:0] $end
-   $var wire 128 x% in[0][2] [127:0] $end
-   $var wire 128 |% in[1][0] [127:0] $end
-   $var wire 128 "& in[1][1] [127:0] $end
-   $var wire 128 && in[1][2] [127:0] $end
-   $var wire  8 *& out[0][0] [7:0] $end
-   $var wire  8 +& out[0][1] [7:0] $end
-   $var wire  8 ,& out[0][2] [7:0] $end
-   $var wire  8 -& out[1][0] [7:0] $end
-   $var wire  8 .& out[1][1] [7:0] $end
-   $var wire  8 /& out[1][2] [7:0] $end
-   $var wire  8 X% val0[0] [7:0] $end
-   $var wire  8 Y% val0[1] [7:0] $end
-   $var wire  8 Z% val1[0] [7:0] $end
-   $var wire  8 [% val1[1] [7:0] $end
-   $var wire  8 \% val2[0] [7:0] $end
-   $var wire  8 ]% val2[1] [7:0] $end
-   $var wire  8 ^% val3[0] [7:0] $end
-   $var wire  8 _% val3[1] [7:0] $end
+   $var wire  1 -& clk $end
+   $var wire 32 && count [31:0] $end
+   $var wire 128 .& in[0][0] [127:0] $end
+   $var wire 128 2& in[0][1] [127:0] $end
+   $var wire 128 6& in[0][2] [127:0] $end
+   $var wire 128 :& in[1][0] [127:0] $end
+   $var wire 128 >& in[1][1] [127:0] $end
+   $var wire 128 B& in[1][2] [127:0] $end
+   $var wire  8 F& out[0][0] [7:0] $end
+   $var wire  8 G& out[0][1] [7:0] $end
+   $var wire  8 H& out[0][2] [7:0] $end
+   $var wire  8 I& out[1][0] [7:0] $end
+   $var wire  8 J& out[1][1] [7:0] $end
+   $var wire  8 K& out[1][2] [7:0] $end
+   $var wire  8 t% val0[0] [7:0] $end
+   $var wire  8 u% val0[1] [7:0] $end
+   $var wire  8 v% val1[0] [7:0] $end
+   $var wire  8 w% val1[1] [7:0] $end
+   $var wire  8 x% val2[0] [7:0] $end
+   $var wire  8 y% val2[1] [7:0] $end
+   $var wire  8 z% val3[0] [7:0] $end
+   $var wire  8 {% val3[1] [7:0] $end
    $scope module i_sub0 $end
-    $var wire 32 0& P0 [31:0] $end
-    $var wire 32 1& P1 [31:0] $end
-    $var wire  8 `% out[0] [7:0] $end
-    $var wire  8 a% out[1] [7:0] $end
+    $var wire 32 L& P0 [31:0] $end
+    $var wire 32 M& P1 [31:0] $end
+    $var wire  8 |% out[0] [7:0] $end
+    $var wire  8 }% out[1] [7:0] $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 32 0& P0 [31:0] $end
-    $var wire 32 1& P1 [31:0] $end
-    $var wire  8 b% out[0] [7:0] $end
-    $var wire  8 c% out[1] [7:0] $end
+    $var wire 32 L& P0 [31:0] $end
+    $var wire 32 M& P1 [31:0] $end
+    $var wire  8 ~% out[0] [7:0] $end
+    $var wire  8 !& out[1] [7:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 32 0& P0 [31:0] $end
-    $var wire 32 1& P1 [31:0] $end
-    $var wire  8 d% out[0] [7:0] $end
-    $var wire  8 e% out[1] [7:0] $end
+    $var wire 32 L& P0 [31:0] $end
+    $var wire 32 M& P1 [31:0] $end
+    $var wire  8 "& out[0] [7:0] $end
+    $var wire  8 #& out[1] [7:0] $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire  8 f% out[0] [7:0] $end
-    $var wire  8 g% out[1] [7:0] $end
+    $var wire  8 $& out[0] [7:0] $end
+    $var wire  8 %& out[1] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 i% i [31:0] $end
+    $var wire 32 '& i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 j% j [31:0] $end
+     $var wire 32 (& j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire 128 k% exp [127:0] $end
+      $var wire 128 )& exp [127:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end
-  $var wire  8 3& out[0] [7:0] $end
-  $var wire  8 4& out[1] [7:0] $end
+  $var wire  8 O& out[0] [7:0] $end
+  $var wire  8 P& out[1] [7:0] $end
   $scope module sub6_9 $end
-   $var wire 32 5& P0 [31:0] $end
-   $var wire  8 3& out[0] [7:0] $end
-   $var wire  8 4& out[1] [7:0] $end
+   $var wire 32 Q& P0 [31:0] $end
+   $var wire 32 R& P1 [31:0] $end
+   $var wire  8 O& out[0] [7:0] $end
+   $var wire  8 P& out[1] [7:0] $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
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 #171
 #172
 #173
diff --git a/test_regress/t/t_hier_block_trace_fst.out b/test_regress/t/t_hier_block_trace_fst.out
index 1ae808652..c675422c2 100644
--- a/test_regress/t/t_hier_block_trace_fst.out
+++ b/test_regress/t/t_hier_block_trace_fst.out
@@ -1,5 +1,5 @@
 $date
-	Tue Oct 18 17:19:55 2022
+	Thu Nov 10 20:17:52 2022
 
 $end
 $version
@@ -67,49 +67,51 @@ $var wire 1 * clk $end
 $var wire 8 + in [7:0] $end
 $var wire 8 , out [7:0] $end
 $scope module delay_2 $end
-$var parameter 32 - WIDTH [31:0] $end
+$var parameter 32 - N [31:0] $end
+$var parameter 32 . WIDTH [31:0] $end
 $var wire 1 * clk $end
 $var wire 8 + in [7:0] $end
 $var wire 8 , out [7:0] $end
-$var logic 8 . tmp [7:0] $end
+$var logic 8 / tmp [7:0] $end
 $scope module genblk1 $end
 $scope module i_delay $end
-$var parameter 32 / N [31:0] $end
-$var parameter 32 - WIDTH [31:0] $end
+$var parameter 32 0 N [31:0] $end
+$var parameter 32 . WIDTH [31:0] $end
 $var wire 1 * clk $end
-$var wire 8 . in [7:0] $end
+$var wire 8 / in [7:0] $end
 $var wire 8 , out [7:0] $end
-$var logic 8 0 tmp [7:0] $end
+$var logic 8 1 tmp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_delay1 $end
-$var wire 1 1 clk $end
-$var wire 8 2 in [7:0] $end
-$var wire 8 3 out [7:0] $end
+$var wire 1 2 clk $end
+$var wire 8 3 in [7:0] $end
+$var wire 8 4 out [7:0] $end
 $scope module delay_9 $end
-$var parameter 32 4 WIDTH [31:0] $end
-$var wire 1 1 clk $end
-$var wire 8 2 in [7:0] $end
-$var wire 8 3 out [7:0] $end
-$var logic 8 5 tmp [7:0] $end
-$scope module genblk1 $end
-$scope module i_delay $end
-$var parameter 32 6 N [31:0] $end
-$var parameter 32 4 WIDTH [31:0] $end
-$var wire 1 1 clk $end
-$var wire 8 5 in [7:0] $end
-$var wire 8 3 out [7:0] $end
+$var parameter 32 5 N [31:0] $end
+$var parameter 32 6 WIDTH [31:0] $end
+$var wire 1 2 clk $end
+$var wire 8 3 in [7:0] $end
+$var wire 8 4 out [7:0] $end
 $var logic 8 7 tmp [7:0] $end
 $scope module genblk1 $end
 $scope module i_delay $end
 $var parameter 32 8 N [31:0] $end
-$var parameter 32 4 WIDTH [31:0] $end
-$var wire 1 1 clk $end
+$var parameter 32 6 WIDTH [31:0] $end
+$var wire 1 2 clk $end
 $var wire 8 7 in [7:0] $end
-$var wire 8 3 out [7:0] $end
+$var wire 8 4 out [7:0] $end
 $var logic 8 9 tmp [7:0] $end
+$scope module genblk1 $end
+$scope module i_delay $end
+$var parameter 32 : N [31:0] $end
+$var parameter 32 6 WIDTH [31:0] $end
+$var wire 1 2 clk $end
+$var wire 8 9 in [7:0] $end
+$var wire 8 4 out [7:0] $end
+$var logic 8 ; tmp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
@@ -117,935 +119,993 @@ $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub0.i_sub0 $end
-$var wire 1 : clk $end
-$var wire 8 ; in [7:0] $end
-$var wire 8 < out [7:0] $end
+$var wire 1 < clk $end
+$var wire 8 = in [7:0] $end
+$var wire 8 > out [7:0] $end
 $scope module sub0 $end
-$var wire 1 : clk $end
-$var wire 8 ; in [7:0] $end
-$var wire 8 < out [7:0] $end
-$var logic 8 = ff [7:0] $end
+$var wire 1 < clk $end
+$var wire 8 = in [7:0] $end
+$var wire 8 > out [7:0] $end
+$var logic 8 ? ff [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub1 $end
-$var wire 1 > clk $end
-$var wire 8 ? in [11:4] $end
-$var wire 8 @ out [7:0] $end
+$var wire 1 @ clk $end
+$var wire 8 A in [11:4] $end
+$var wire 8 B out [7:0] $end
 $scope module sub1 $end
-$var wire 1 > clk $end
-$var wire 8 ? in [11:4] $end
-$var wire 8 @ out [7:0] $end
-$var logic 8 A ff [7:0] $end
+$var wire 1 @ clk $end
+$var wire 8 A in [11:4] $end
+$var wire 8 B out [7:0] $end
+$var logic 8 C ff [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2 $end
-$var wire 1 B clk $end
-$var wire 8 C in [7:0] $end
-$var wire 8 D out [7:0] $end
-$scope module sub2 $end
-$var wire 1 B clk $end
-$var wire 8 C in [7:0] $end
-$var wire 8 D out [7:0] $end
-$var logic 8 E ff [7:0] $end
-$scope module i_sub3 $end
-$var wire 8 E in_wire [7:0] $end
-$var wire 8 F out_1 [7:0] $end
-$var wire 8 G out_2 [7:0] $end
-$scope module i_sub3 $end
-$var wire 1 B clk $end
+$var wire 1 D clk $end
 $var wire 8 E in [7:0] $end
 $var wire 8 F out [7:0] $end
+$scope module sub2 $end
+$var wire 1 D clk $end
+$var wire 8 E in [7:0] $end
+$var wire 8 F out [7:0] $end
+$var logic 8 G ff [7:0] $end
+$scope module i_sub3 $end
+$var wire 8 G in_wire [7:0] $end
+$var wire 8 H out_1 [7:0] $end
+$var wire 8 I out_2 [7:0] $end
+$scope module i_sub3 $end
+$var wire 1 D clk $end
+$var wire 8 G in [7:0] $end
+$var wire 8 H out [7:0] $end
 $upscope $end
 $scope module i_sub3_2 $end
-$var wire 1 B clk $end
-$var wire 8 E in [7:0] $end
-$var wire 8 G out [7:0] $end
+$var wire 1 D clk $end
+$var wire 8 G in [7:0] $end
+$var wire 8 I out [7:0] $end
 $upscope $end
 $scope interface in $end
-$var wire 1 B clk $end
-$var logic 8 E data [7:0] $end
+$var wire 1 D clk $end
+$var logic 8 G data [7:0] $end
 $upscope $end
 $scope interface out $end
-$var wire 1 B clk $end
-$var logic 8 F data [7:0] $end
+$var wire 1 D clk $end
+$var logic 8 H data [7:0] $end
 $upscope $end
 $upscope $end
 $scope interface in_ifs $end
-$var wire 1 B clk $end
-$var logic 8 E data [7:0] $end
+$var wire 1 D clk $end
+$var logic 8 G data [7:0] $end
 $upscope $end
 $scope interface out_ifs $end
-$var wire 1 B clk $end
-$var logic 8 F data [7:0] $end
+$var wire 1 D clk $end
+$var logic 8 H data [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3 $end
-$var wire 1 H clk $end
-$var wire 8 I in [7:0] $end
-$var wire 8 J out [7:0] $end
+$var wire 1 J clk $end
+$var wire 8 K in [7:0] $end
+$var wire 8 L out [7:0] $end
 $scope module sub3_c $end
-$var parameter 32 K UNPACKED_ARRAY[0] [31:0] $end
-$var parameter 32 L UNPACKED_ARRAY[1] [31:0] $end
-$var wire 1 H clk $end
-$var wire 8 I in [7:0] $end
-$var wire 8 J out [7:0] $end
-$var logic 8 M ff [7:0] $end
-$var wire 8 N out4 [7:0] $end
-$var wire 8 O out4_2 [7:0] $end
+$var parameter 8 M P0 [7:0] $end
+$var parameter 32 N UNPACKED_ARRAY[0] [31:0] $end
+$var parameter 32 O UNPACKED_ARRAY[1] [31:0] $end
+$var parameter 16 P UNUSED [15:0] $end
+$var wire 1 J clk $end
+$var wire 8 K in [7:0] $end
+$var wire 8 L out [7:0] $end
+$var logic 8 Q ff [7:0] $end
+$var wire 8 R out4 [7:0] $end
+$var wire 8 S out4_2 [7:0] $end
 $scope module i_sub4_0 $end
-$var wire 1 H clk $end
-$var wire 8 M in [7:0] $end
-$var wire 8 N out [7:0] $end
+$var wire 1 J clk $end
+$var wire 8 Q in [7:0] $end
+$var wire 8 R out [7:0] $end
 $upscope $end
 $scope module i_sub4_1 $end
-$var wire 1 H clk $end
-$var wire 8 M in [7:0] $end
-$var wire 8 O out [7:0] $end
+$var wire 1 J clk $end
+$var wire 8 Q in [7:0] $end
+$var wire 8 S out [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0 $end
-$var wire 1 P clk $end
-$var wire 8 Q in [7:0] $end
-$var wire 8 R out [7:0] $end
+$var wire 1 T clk $end
+$var wire 8 U in [7:0] $end
+$var wire 8 V out [7:0] $end
 $scope module sub4_2 $end
-$var wire 1 P clk $end
-$var wire 8 Q in [7:0] $end
-$var wire 8 R out [7:0] $end
-$var logic 8 S ff [7:0] $end
-$var logic 128 T sub5_in[0][0] [127:0] $end
-$var logic 128 U sub5_in[0][1] [127:0] $end
-$var logic 128 V sub5_in[0][2] [127:0] $end
-$var logic 128 W sub5_in[1][0] [127:0] $end
-$var logic 128 X sub5_in[1][1] [127:0] $end
-$var logic 128 Y sub5_in[1][2] [127:0] $end
-$var wire 8 Z sub5_out[0][0] [7:0] $end
-$var wire 8 [ sub5_out[0][1] [7:0] $end
-$var wire 8 \ sub5_out[0][2] [7:0] $end
-$var wire 8 ] sub5_out[1][0] [7:0] $end
-$var wire 8 ^ sub5_out[1][1] [7:0] $end
-$var wire 8 _ sub5_out[1][2] [7:0] $end
-$var int 32 ` count [31:0] $end
+$var parameter 32 W P0 [31:0] $end
+$var real_parameter 64 X P1 $end
+$var real_parameter 64 Y P3 $end
+$var wire 1 T clk $end
+$var wire 8 U in [7:0] $end
+$var wire 8 V out [7:0] $end
+$var logic 8 Z ff [7:0] $end
+$var logic 128 [ sub5_in[0][0] [127:0] $end
+$var logic 128 \ sub5_in[0][1] [127:0] $end
+$var logic 128 ] sub5_in[0][2] [127:0] $end
+$var logic 128 ^ sub5_in[1][0] [127:0] $end
+$var logic 128 _ sub5_in[1][1] [127:0] $end
+$var logic 128 ` sub5_in[1][2] [127:0] $end
+$var wire 8 a sub5_out[0][0] [7:0] $end
+$var wire 8 b sub5_out[0][1] [7:0] $end
+$var wire 8 c sub5_out[0][2] [7:0] $end
+$var wire 8 d sub5_out[1][0] [7:0] $end
+$var wire 8 e sub5_out[1][1] [7:0] $end
+$var wire 8 f sub5_out[1][2] [7:0] $end
+$var int 32 g count [31:0] $end
 $scope module i_sub5 $end
-$var wire 1 P clk $end
-$var wire 128 a in[0][0] [127:0] $end
-$var wire 128 b in[0][1] [127:0] $end
-$var wire 128 c in[0][2] [127:0] $end
-$var wire 128 d in[1][0] [127:0] $end
-$var wire 128 e in[1][1] [127:0] $end
-$var wire 128 f in[1][2] [127:0] $end
-$var wire 8 g out[0][0] [7:0] $end
-$var wire 8 h out[0][1] [7:0] $end
-$var wire 8 i out[0][2] [7:0] $end
-$var wire 8 j out[1][0] [7:0] $end
-$var wire 8 k out[1][1] [7:0] $end
-$var wire 8 l out[1][2] [7:0] $end
+$var wire 1 T clk $end
+$var wire 128 h in[0][0] [127:0] $end
+$var wire 128 i in[0][1] [127:0] $end
+$var wire 128 j in[0][2] [127:0] $end
+$var wire 128 k in[1][0] [127:0] $end
+$var wire 128 l in[1][1] [127:0] $end
+$var wire 128 m in[1][2] [127:0] $end
+$var wire 8 n out[0][0] [7:0] $end
+$var wire 8 o out[0][1] [7:0] $end
+$var wire 8 p out[0][2] [7:0] $end
+$var wire 8 q out[1][0] [7:0] $end
+$var wire 8 r out[1][1] [7:0] $end
+$var wire 8 s out[1][2] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 m i [31:0] $end
+$var int 32 t i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 n j [31:0] $end
+$var int 32 u j [31:0] $end
 $scope module unnamedblk3 $end
-$var byte 8 o exp [7:0] $end
+$var byte 8 v exp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5 $end
-$var wire 1 p clk $end
-$var wire 128 q in[0][0] [127:0] $end
-$var wire 128 r in[0][1] [127:0] $end
-$var wire 128 s in[0][2] [127:0] $end
-$var wire 128 t in[1][0] [127:0] $end
-$var wire 128 u in[1][1] [127:0] $end
-$var wire 128 v in[1][2] [127:0] $end
-$var wire 8 w out[0][0] [7:0] $end
-$var wire 8 x out[0][1] [7:0] $end
-$var wire 8 y out[0][2] [7:0] $end
-$var wire 8 z out[1][0] [7:0] $end
-$var wire 8 { out[1][1] [7:0] $end
-$var wire 8 | out[1][2] [7:0] $end
+$var wire 1 w clk $end
+$var wire 128 x in[0][0] [127:0] $end
+$var wire 128 y in[0][1] [127:0] $end
+$var wire 128 z in[0][2] [127:0] $end
+$var wire 128 { in[1][0] [127:0] $end
+$var wire 128 | in[1][1] [127:0] $end
+$var wire 128 } in[1][2] [127:0] $end
+$var wire 8 ~ out[0][0] [7:0] $end
+$var wire 8 !! out[0][1] [7:0] $end
+$var wire 8 "! out[0][2] [7:0] $end
+$var wire 8 #! out[1][0] [7:0] $end
+$var wire 8 $! out[1][1] [7:0] $end
+$var wire 8 %! out[1][2] [7:0] $end
 $scope module sub5 $end
-$var wire 1 p clk $end
-$var wire 128 q in[0][0] [127:0] $end
-$var wire 128 r in[0][1] [127:0] $end
-$var wire 128 s in[0][2] [127:0] $end
-$var wire 128 t in[1][0] [127:0] $end
-$var wire 128 u in[1][1] [127:0] $end
-$var wire 128 v in[1][2] [127:0] $end
-$var wire 8 w out[0][0] [7:0] $end
-$var wire 8 x out[0][1] [7:0] $end
-$var wire 8 y out[0][2] [7:0] $end
-$var wire 8 z out[1][0] [7:0] $end
-$var wire 8 { out[1][1] [7:0] $end
-$var wire 8 | out[1][2] [7:0] $end
-$var int 32 } count [31:0] $end
-$var wire 8 ~ val0[0] [7:0] $end
-$var wire 8 !! val0[1] [7:0] $end
-$var wire 8 "! val1[0] [7:0] $end
-$var wire 8 #! val1[1] [7:0] $end
-$var wire 8 $! val2[0] [7:0] $end
-$var wire 8 %! val2[1] [7:0] $end
-$var wire 8 &! val3[0] [7:0] $end
-$var wire 8 '! val3[1] [7:0] $end
+$var wire 1 w clk $end
+$var wire 128 x in[0][0] [127:0] $end
+$var wire 128 y in[0][1] [127:0] $end
+$var wire 128 z in[0][2] [127:0] $end
+$var wire 128 { in[1][0] [127:0] $end
+$var wire 128 | in[1][1] [127:0] $end
+$var wire 128 } in[1][2] [127:0] $end
+$var wire 8 ~ out[0][0] [7:0] $end
+$var wire 8 !! out[0][1] [7:0] $end
+$var wire 8 "! out[0][2] [7:0] $end
+$var wire 8 #! out[1][0] [7:0] $end
+$var wire 8 $! out[1][1] [7:0] $end
+$var wire 8 %! out[1][2] [7:0] $end
+$var int 32 &! count [31:0] $end
+$var wire 8 '! val0[0] [7:0] $end
+$var wire 8 (! val0[1] [7:0] $end
+$var wire 8 )! val1[0] [7:0] $end
+$var wire 8 *! val1[1] [7:0] $end
+$var wire 8 +! val2[0] [7:0] $end
+$var wire 8 ,! val2[1] [7:0] $end
+$var wire 8 -! val3[0] [7:0] $end
+$var wire 8 .! val3[1] [7:0] $end
 $scope module i_sub0 $end
-$var parameter 32 (! P0 [31:0] $end
-$var parameter 32 )! P1 [31:0] $end
-$var wire 8 *! out[0] [7:0] $end
-$var wire 8 +! out[1] [7:0] $end
+$var parameter 32 /! P0 [31:0] $end
+$var parameter 32 0! P1 [31:0] $end
+$var wire 8 1! out[0] [7:0] $end
+$var wire 8 2! out[1] [7:0] $end
 $upscope $end
 $scope module i_sub1 $end
-$var parameter 32 (! P0 [31:0] $end
-$var parameter 32 )! P1 [31:0] $end
-$var wire 8 ,! out[0] [7:0] $end
-$var wire 8 -! out[1] [7:0] $end
+$var parameter 32 /! P0 [31:0] $end
+$var parameter 32 0! P1 [31:0] $end
+$var wire 8 3! out[0] [7:0] $end
+$var wire 8 4! out[1] [7:0] $end
 $upscope $end
 $scope module i_sub2 $end
-$var parameter 32 (! P0 [31:0] $end
-$var parameter 32 )! P1 [31:0] $end
-$var wire 8 .! out[0] [7:0] $end
-$var wire 8 /! out[1] [7:0] $end
+$var parameter 32 /! P0 [31:0] $end
+$var parameter 32 0! P1 [31:0] $end
+$var wire 8 5! out[0] [7:0] $end
+$var wire 8 6! out[1] [7:0] $end
 $upscope $end
 $scope module i_sub3 $end
-$var wire 8 0! out[0] [7:0] $end
-$var wire 8 1! out[1] [7:0] $end
+$var wire 8 7! out[0] [7:0] $end
+$var wire 8 8! out[1] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 2! i [31:0] $end
+$var int 32 9! i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 3! j [31:0] $end
+$var int 32 :! j [31:0] $end
 $scope module unnamedblk3 $end
-$var bit 128 4! exp [127:0] $end
+$var bit 128 ;! exp [127:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end
-$var wire 8 5! out[0] [7:0] $end
-$var wire 8 6! out[1] [7:0] $end
+$var wire 8 <! out[0] [7:0] $end
+$var wire 8 =! out[1] [7:0] $end
 $scope module sub6_9 $end
-$var parameter 32 7! P0 [31:0] $end
-$var wire 8 5! out[0] [7:0] $end
-$var wire 8 6! out[1] [7:0] $end
+$var parameter 32 >! P0 [31:0] $end
+$var parameter 32 ?! P1 [31:0] $end
+$var wire 8 <! out[0] [7:0] $end
+$var wire 8 =! out[1] [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1 $end
-$var wire 1 8! clk $end
-$var wire 8 9! in [7:0] $end
-$var wire 8 :! out [7:0] $end
+$var wire 1 @! clk $end
+$var wire 8 A! in [7:0] $end
+$var wire 8 B! out [7:0] $end
 $scope module sub4_b $end
-$var wire 1 8! clk $end
-$var wire 8 9! in [7:0] $end
-$var wire 8 :! out [7:0] $end
-$var logic 8 ;! ff [7:0] $end
-$var logic 128 <! sub5_in[0][0] [127:0] $end
-$var logic 128 =! sub5_in[0][1] [127:0] $end
-$var logic 128 >! sub5_in[0][2] [127:0] $end
-$var logic 128 ?! sub5_in[1][0] [127:0] $end
-$var logic 128 @! sub5_in[1][1] [127:0] $end
-$var logic 128 A! sub5_in[1][2] [127:0] $end
-$var wire 8 B! sub5_out[0][0] [7:0] $end
-$var wire 8 C! sub5_out[0][1] [7:0] $end
-$var wire 8 D! sub5_out[0][2] [7:0] $end
-$var wire 8 E! sub5_out[1][0] [7:0] $end
-$var wire 8 F! sub5_out[1][1] [7:0] $end
-$var wire 8 G! sub5_out[1][2] [7:0] $end
-$var int 32 H! count [31:0] $end
+$var parameter 32 C! P0 [31:0] $end
+$var real_parameter 64 D! P1 $end
+$var real_parameter 64 E! P3 $end
+$var wire 1 @! clk $end
+$var wire 8 A! in [7:0] $end
+$var wire 8 B! out [7:0] $end
+$var logic 8 F! ff [7:0] $end
+$var logic 128 G! sub5_in[0][0] [127:0] $end
+$var logic 128 H! sub5_in[0][1] [127:0] $end
+$var logic 128 I! sub5_in[0][2] [127:0] $end
+$var logic 128 J! sub5_in[1][0] [127:0] $end
+$var logic 128 K! sub5_in[1][1] [127:0] $end
+$var logic 128 L! sub5_in[1][2] [127:0] $end
+$var wire 8 M! sub5_out[0][0] [7:0] $end
+$var wire 8 N! sub5_out[0][1] [7:0] $end
+$var wire 8 O! sub5_out[0][2] [7:0] $end
+$var wire 8 P! sub5_out[1][0] [7:0] $end
+$var wire 8 Q! sub5_out[1][1] [7:0] $end
+$var wire 8 R! sub5_out[1][2] [7:0] $end
+$var int 32 S! count [31:0] $end
 $scope module i_sub5 $end
-$var wire 1 8! clk $end
-$var wire 128 I! in[0][0] [127:0] $end
-$var wire 128 J! in[0][1] [127:0] $end
-$var wire 128 K! in[0][2] [127:0] $end
-$var wire 128 L! in[1][0] [127:0] $end
-$var wire 128 M! in[1][1] [127:0] $end
-$var wire 128 N! in[1][2] [127:0] $end
-$var wire 8 O! out[0][0] [7:0] $end
-$var wire 8 P! out[0][1] [7:0] $end
-$var wire 8 Q! out[0][2] [7:0] $end
-$var wire 8 R! out[1][0] [7:0] $end
-$var wire 8 S! out[1][1] [7:0] $end
-$var wire 8 T! out[1][2] [7:0] $end
+$var wire 1 @! clk $end
+$var wire 128 T! in[0][0] [127:0] $end
+$var wire 128 U! in[0][1] [127:0] $end
+$var wire 128 V! in[0][2] [127:0] $end
+$var wire 128 W! in[1][0] [127:0] $end
+$var wire 128 X! in[1][1] [127:0] $end
+$var wire 128 Y! in[1][2] [127:0] $end
+$var wire 8 Z! out[0][0] [7:0] $end
+$var wire 8 [! out[0][1] [7:0] $end
+$var wire 8 \! out[0][2] [7:0] $end
+$var wire 8 ]! out[1][0] [7:0] $end
+$var wire 8 ^! out[1][1] [7:0] $end
+$var wire 8 _! out[1][2] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 U! i [31:0] $end
+$var int 32 `! i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 V! j [31:0] $end
+$var int 32 a! j [31:0] $end
 $scope module unnamedblk3 $end
-$var byte 8 W! exp [7:0] $end
+$var byte 8 b! exp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5 $end
-$var wire 1 X! clk $end
-$var wire 128 Y! in[0][0] [127:0] $end
-$var wire 128 Z! in[0][1] [127:0] $end
-$var wire 128 [! in[0][2] [127:0] $end
-$var wire 128 \! in[1][0] [127:0] $end
-$var wire 128 ]! in[1][1] [127:0] $end
-$var wire 128 ^! in[1][2] [127:0] $end
-$var wire 8 _! out[0][0] [7:0] $end
-$var wire 8 `! out[0][1] [7:0] $end
-$var wire 8 a! out[0][2] [7:0] $end
-$var wire 8 b! out[1][0] [7:0] $end
-$var wire 8 c! out[1][1] [7:0] $end
-$var wire 8 d! out[1][2] [7:0] $end
+$var wire 1 c! clk $end
+$var wire 128 d! in[0][0] [127:0] $end
+$var wire 128 e! in[0][1] [127:0] $end
+$var wire 128 f! in[0][2] [127:0] $end
+$var wire 128 g! in[1][0] [127:0] $end
+$var wire 128 h! in[1][1] [127:0] $end
+$var wire 128 i! in[1][2] [127:0] $end
+$var wire 8 j! out[0][0] [7:0] $end
+$var wire 8 k! out[0][1] [7:0] $end
+$var wire 8 l! out[0][2] [7:0] $end
+$var wire 8 m! out[1][0] [7:0] $end
+$var wire 8 n! out[1][1] [7:0] $end
+$var wire 8 o! out[1][2] [7:0] $end
 $scope module sub5 $end
-$var wire 1 X! clk $end
-$var wire 128 Y! in[0][0] [127:0] $end
-$var wire 128 Z! in[0][1] [127:0] $end
-$var wire 128 [! in[0][2] [127:0] $end
-$var wire 128 \! in[1][0] [127:0] $end
-$var wire 128 ]! in[1][1] [127:0] $end
-$var wire 128 ^! in[1][2] [127:0] $end
-$var wire 8 _! out[0][0] [7:0] $end
-$var wire 8 `! out[0][1] [7:0] $end
-$var wire 8 a! out[0][2] [7:0] $end
-$var wire 8 b! out[1][0] [7:0] $end
-$var wire 8 c! out[1][1] [7:0] $end
-$var wire 8 d! out[1][2] [7:0] $end
-$var int 32 e! count [31:0] $end
-$var wire 8 f! val0[0] [7:0] $end
-$var wire 8 g! val0[1] [7:0] $end
-$var wire 8 h! val1[0] [7:0] $end
-$var wire 8 i! val1[1] [7:0] $end
-$var wire 8 j! val2[0] [7:0] $end
-$var wire 8 k! val2[1] [7:0] $end
-$var wire 8 l! val3[0] [7:0] $end
-$var wire 8 m! val3[1] [7:0] $end
+$var wire 1 c! clk $end
+$var wire 128 d! in[0][0] [127:0] $end
+$var wire 128 e! in[0][1] [127:0] $end
+$var wire 128 f! in[0][2] [127:0] $end
+$var wire 128 g! in[1][0] [127:0] $end
+$var wire 128 h! in[1][1] [127:0] $end
+$var wire 128 i! in[1][2] [127:0] $end
+$var wire 8 j! out[0][0] [7:0] $end
+$var wire 8 k! out[0][1] [7:0] $end
+$var wire 8 l! out[0][2] [7:0] $end
+$var wire 8 m! out[1][0] [7:0] $end
+$var wire 8 n! out[1][1] [7:0] $end
+$var wire 8 o! out[1][2] [7:0] $end
+$var int 32 p! count [31:0] $end
+$var wire 8 q! val0[0] [7:0] $end
+$var wire 8 r! val0[1] [7:0] $end
+$var wire 8 s! val1[0] [7:0] $end
+$var wire 8 t! val1[1] [7:0] $end
+$var wire 8 u! val2[0] [7:0] $end
+$var wire 8 v! val2[1] [7:0] $end
+$var wire 8 w! val3[0] [7:0] $end
+$var wire 8 x! val3[1] [7:0] $end
 $scope module i_sub0 $end
-$var parameter 32 n! P0 [31:0] $end
-$var parameter 32 o! P1 [31:0] $end
-$var wire 8 p! out[0] [7:0] $end
-$var wire 8 q! out[1] [7:0] $end
+$var parameter 32 y! P0 [31:0] $end
+$var parameter 32 z! P1 [31:0] $end
+$var wire 8 {! out[0] [7:0] $end
+$var wire 8 |! out[1] [7:0] $end
 $upscope $end
 $scope module i_sub1 $end
-$var parameter 32 n! P0 [31:0] $end
-$var parameter 32 o! P1 [31:0] $end
-$var wire 8 r! out[0] [7:0] $end
-$var wire 8 s! out[1] [7:0] $end
+$var parameter 32 y! P0 [31:0] $end
+$var parameter 32 z! P1 [31:0] $end
+$var wire 8 }! out[0] [7:0] $end
+$var wire 8 ~! out[1] [7:0] $end
 $upscope $end
 $scope module i_sub2 $end
-$var parameter 32 n! P0 [31:0] $end
-$var parameter 32 o! P1 [31:0] $end
-$var wire 8 t! out[0] [7:0] $end
-$var wire 8 u! out[1] [7:0] $end
+$var parameter 32 y! P0 [31:0] $end
+$var parameter 32 z! P1 [31:0] $end
+$var wire 8 !" out[0] [7:0] $end
+$var wire 8 "" out[1] [7:0] $end
 $upscope $end
 $scope module i_sub3 $end
-$var wire 8 v! out[0] [7:0] $end
-$var wire 8 w! out[1] [7:0] $end
+$var wire 8 #" out[0] [7:0] $end
+$var wire 8 $" out[1] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 x! i [31:0] $end
+$var int 32 %" i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 y! j [31:0] $end
+$var int 32 &" j [31:0] $end
 $scope module unnamedblk3 $end
-$var bit 128 z! exp [127:0] $end
+$var bit 128 '" exp [127:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end
-$var wire 8 {! out[0] [7:0] $end
-$var wire 8 |! out[1] [7:0] $end
+$var wire 8 (" out[0] [7:0] $end
+$var wire 8 )" out[1] [7:0] $end
 $scope module sub6_9 $end
-$var parameter 32 }! P0 [31:0] $end
-$var wire 8 {! out[0] [7:0] $end
-$var wire 8 |! out[1] [7:0] $end
+$var parameter 32 *" P0 [31:0] $end
+$var parameter 32 +" P1 [31:0] $end
+$var wire 8 (" out[0] [7:0] $end
+$var wire 8 )" out[1] [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2 $end
-$var wire 1 ~! clk $end
-$var wire 8 !" in [7:0] $end
-$var wire 8 "" out [7:0] $end
+$var wire 1 ," clk $end
+$var wire 8 -" in [7:0] $end
+$var wire 8 ." out [7:0] $end
 $scope module sub3_2 $end
-$var parameter 32 #" UNPACKED_ARRAY[0] [31:0] $end
-$var parameter 32 $" UNPACKED_ARRAY[1] [31:0] $end
-$var parameter 16 %" UNUSED [15:0] $end
-$var wire 1 ~! clk $end
-$var wire 8 !" in [7:0] $end
-$var wire 8 "" out [7:0] $end
-$var logic 8 &" ff [7:0] $end
-$var wire 8 '" out4 [7:0] $end
-$var wire 8 (" out4_2 [7:0] $end
+$var parameter 8 /" P0 [7:0] $end
+$var parameter 32 0" UNPACKED_ARRAY[0] [31:0] $end
+$var parameter 32 1" UNPACKED_ARRAY[1] [31:0] $end
+$var parameter 16 2" UNUSED [15:0] $end
+$var wire 1 ," clk $end
+$var wire 8 -" in [7:0] $end
+$var wire 8 ." out [7:0] $end
+$var logic 8 3" ff [7:0] $end
+$var wire 8 4" out4 [7:0] $end
+$var wire 8 5" out4_2 [7:0] $end
 $scope module i_sub4_0 $end
-$var wire 1 ~! clk $end
-$var wire 8 &" in [7:0] $end
-$var wire 8 '" out [7:0] $end
+$var wire 1 ," clk $end
+$var wire 8 3" in [7:0] $end
+$var wire 8 4" out [7:0] $end
 $upscope $end
 $scope module i_sub4_1 $end
-$var wire 1 ~! clk $end
-$var wire 8 &" in [7:0] $end
-$var wire 8 (" out [7:0] $end
+$var wire 1 ," clk $end
+$var wire 8 3" in [7:0] $end
+$var wire 8 5" out [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2.sub3_2.i_sub4_0 $end
-$var wire 1 )" clk $end
-$var wire 8 *" in [7:0] $end
-$var wire 8 +" out [7:0] $end
+$var wire 1 6" clk $end
+$var wire 8 7" in [7:0] $end
+$var wire 8 8" out [7:0] $end
 $scope module sub4_2 $end
-$var wire 1 )" clk $end
-$var wire 8 *" in [7:0] $end
-$var wire 8 +" out [7:0] $end
-$var logic 8 ," ff [7:0] $end
-$var logic 128 -" sub5_in[0][0] [127:0] $end
-$var logic 128 ." sub5_in[0][1] [127:0] $end
-$var logic 128 /" sub5_in[0][2] [127:0] $end
-$var logic 128 0" sub5_in[1][0] [127:0] $end
-$var logic 128 1" sub5_in[1][1] [127:0] $end
-$var logic 128 2" sub5_in[1][2] [127:0] $end
-$var wire 8 3" sub5_out[0][0] [7:0] $end
-$var wire 8 4" sub5_out[0][1] [7:0] $end
-$var wire 8 5" sub5_out[0][2] [7:0] $end
-$var wire 8 6" sub5_out[1][0] [7:0] $end
-$var wire 8 7" sub5_out[1][1] [7:0] $end
-$var wire 8 8" sub5_out[1][2] [7:0] $end
-$var int 32 9" count [31:0] $end
+$var parameter 32 9" P0 [31:0] $end
+$var real_parameter 64 :" P1 $end
+$var real_parameter 64 ;" P3 $end
+$var wire 1 6" clk $end
+$var wire 8 7" in [7:0] $end
+$var wire 8 8" out [7:0] $end
+$var logic 8 <" ff [7:0] $end
+$var logic 128 =" sub5_in[0][0] [127:0] $end
+$var logic 128 >" sub5_in[0][1] [127:0] $end
+$var logic 128 ?" sub5_in[0][2] [127:0] $end
+$var logic 128 @" sub5_in[1][0] [127:0] $end
+$var logic 128 A" sub5_in[1][1] [127:0] $end
+$var logic 128 B" sub5_in[1][2] [127:0] $end
+$var wire 8 C" sub5_out[0][0] [7:0] $end
+$var wire 8 D" sub5_out[0][1] [7:0] $end
+$var wire 8 E" sub5_out[0][2] [7:0] $end
+$var wire 8 F" sub5_out[1][0] [7:0] $end
+$var wire 8 G" sub5_out[1][1] [7:0] $end
+$var wire 8 H" sub5_out[1][2] [7:0] $end
+$var int 32 I" count [31:0] $end
 $scope module i_sub5 $end
-$var wire 1 )" clk $end
-$var wire 128 :" in[0][0] [127:0] $end
-$var wire 128 ;" in[0][1] [127:0] $end
-$var wire 128 <" in[0][2] [127:0] $end
-$var wire 128 =" in[1][0] [127:0] $end
-$var wire 128 >" in[1][1] [127:0] $end
-$var wire 128 ?" in[1][2] [127:0] $end
-$var wire 8 @" out[0][0] [7:0] $end
-$var wire 8 A" out[0][1] [7:0] $end
-$var wire 8 B" out[0][2] [7:0] $end
-$var wire 8 C" out[1][0] [7:0] $end
-$var wire 8 D" out[1][1] [7:0] $end
-$var wire 8 E" out[1][2] [7:0] $end
+$var wire 1 6" clk $end
+$var wire 128 J" in[0][0] [127:0] $end
+$var wire 128 K" in[0][1] [127:0] $end
+$var wire 128 L" in[0][2] [127:0] $end
+$var wire 128 M" in[1][0] [127:0] $end
+$var wire 128 N" in[1][1] [127:0] $end
+$var wire 128 O" in[1][2] [127:0] $end
+$var wire 8 P" out[0][0] [7:0] $end
+$var wire 8 Q" out[0][1] [7:0] $end
+$var wire 8 R" out[0][2] [7:0] $end
+$var wire 8 S" out[1][0] [7:0] $end
+$var wire 8 T" out[1][1] [7:0] $end
+$var wire 8 U" out[1][2] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 F" i [31:0] $end
+$var int 32 V" i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 G" j [31:0] $end
+$var int 32 W" j [31:0] $end
 $scope module unnamedblk3 $end
-$var byte 8 H" exp [7:0] $end
+$var byte 8 X" exp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5 $end
-$var wire 1 I" clk $end
-$var wire 128 J" in[0][0] [127:0] $end
-$var wire 128 K" in[0][1] [127:0] $end
-$var wire 128 L" in[0][2] [127:0] $end
-$var wire 128 M" in[1][0] [127:0] $end
-$var wire 128 N" in[1][1] [127:0] $end
-$var wire 128 O" in[1][2] [127:0] $end
-$var wire 8 P" out[0][0] [7:0] $end
-$var wire 8 Q" out[0][1] [7:0] $end
-$var wire 8 R" out[0][2] [7:0] $end
-$var wire 8 S" out[1][0] [7:0] $end
-$var wire 8 T" out[1][1] [7:0] $end
-$var wire 8 U" out[1][2] [7:0] $end
+$var wire 1 Y" clk $end
+$var wire 128 Z" in[0][0] [127:0] $end
+$var wire 128 [" in[0][1] [127:0] $end
+$var wire 128 \" in[0][2] [127:0] $end
+$var wire 128 ]" in[1][0] [127:0] $end
+$var wire 128 ^" in[1][1] [127:0] $end
+$var wire 128 _" in[1][2] [127:0] $end
+$var wire 8 `" out[0][0] [7:0] $end
+$var wire 8 a" out[0][1] [7:0] $end
+$var wire 8 b" out[0][2] [7:0] $end
+$var wire 8 c" out[1][0] [7:0] $end
+$var wire 8 d" out[1][1] [7:0] $end
+$var wire 8 e" out[1][2] [7:0] $end
 $scope module sub5 $end
-$var wire 1 I" clk $end
-$var wire 128 J" in[0][0] [127:0] $end
-$var wire 128 K" in[0][1] [127:0] $end
-$var wire 128 L" in[0][2] [127:0] $end
-$var wire 128 M" in[1][0] [127:0] $end
-$var wire 128 N" in[1][1] [127:0] $end
-$var wire 128 O" in[1][2] [127:0] $end
-$var wire 8 P" out[0][0] [7:0] $end
-$var wire 8 Q" out[0][1] [7:0] $end
-$var wire 8 R" out[0][2] [7:0] $end
-$var wire 8 S" out[1][0] [7:0] $end
-$var wire 8 T" out[1][1] [7:0] $end
-$var wire 8 U" out[1][2] [7:0] $end
-$var int 32 V" count [31:0] $end
-$var wire 8 W" val0[0] [7:0] $end
-$var wire 8 X" val0[1] [7:0] $end
-$var wire 8 Y" val1[0] [7:0] $end
-$var wire 8 Z" val1[1] [7:0] $end
-$var wire 8 [" val2[0] [7:0] $end
-$var wire 8 \" val2[1] [7:0] $end
-$var wire 8 ]" val3[0] [7:0] $end
-$var wire 8 ^" val3[1] [7:0] $end
+$var wire 1 Y" clk $end
+$var wire 128 Z" in[0][0] [127:0] $end
+$var wire 128 [" in[0][1] [127:0] $end
+$var wire 128 \" in[0][2] [127:0] $end
+$var wire 128 ]" in[1][0] [127:0] $end
+$var wire 128 ^" in[1][1] [127:0] $end
+$var wire 128 _" in[1][2] [127:0] $end
+$var wire 8 `" out[0][0] [7:0] $end
+$var wire 8 a" out[0][1] [7:0] $end
+$var wire 8 b" out[0][2] [7:0] $end
+$var wire 8 c" out[1][0] [7:0] $end
+$var wire 8 d" out[1][1] [7:0] $end
+$var wire 8 e" out[1][2] [7:0] $end
+$var int 32 f" count [31:0] $end
+$var wire 8 g" val0[0] [7:0] $end
+$var wire 8 h" val0[1] [7:0] $end
+$var wire 8 i" val1[0] [7:0] $end
+$var wire 8 j" val1[1] [7:0] $end
+$var wire 8 k" val2[0] [7:0] $end
+$var wire 8 l" val2[1] [7:0] $end
+$var wire 8 m" val3[0] [7:0] $end
+$var wire 8 n" val3[1] [7:0] $end
 $scope module i_sub0 $end
-$var parameter 32 _" P0 [31:0] $end
-$var parameter 32 `" P1 [31:0] $end
-$var wire 8 a" out[0] [7:0] $end
-$var wire 8 b" out[1] [7:0] $end
+$var parameter 32 o" P0 [31:0] $end
+$var parameter 32 p" P1 [31:0] $end
+$var wire 8 q" out[0] [7:0] $end
+$var wire 8 r" out[1] [7:0] $end
 $upscope $end
 $scope module i_sub1 $end
-$var parameter 32 _" P0 [31:0] $end
-$var parameter 32 `" P1 [31:0] $end
-$var wire 8 c" out[0] [7:0] $end
-$var wire 8 d" out[1] [7:0] $end
+$var parameter 32 o" P0 [31:0] $end
+$var parameter 32 p" P1 [31:0] $end
+$var wire 8 s" out[0] [7:0] $end
+$var wire 8 t" out[1] [7:0] $end
 $upscope $end
 $scope module i_sub2 $end
-$var parameter 32 _" P0 [31:0] $end
-$var parameter 32 `" P1 [31:0] $end
-$var wire 8 e" out[0] [7:0] $end
-$var wire 8 f" out[1] [7:0] $end
+$var parameter 32 o" P0 [31:0] $end
+$var parameter 32 p" P1 [31:0] $end
+$var wire 8 u" out[0] [7:0] $end
+$var wire 8 v" out[1] [7:0] $end
 $upscope $end
 $scope module i_sub3 $end
-$var wire 8 g" out[0] [7:0] $end
-$var wire 8 h" out[1] [7:0] $end
+$var wire 8 w" out[0] [7:0] $end
+$var wire 8 x" out[1] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 i" i [31:0] $end
+$var int 32 y" i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 j" j [31:0] $end
+$var int 32 z" j [31:0] $end
 $scope module unnamedblk3 $end
-$var bit 128 k" exp [127:0] $end
+$var bit 128 {" exp [127:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end
-$var wire 8 l" out[0] [7:0] $end
-$var wire 8 m" out[1] [7:0] $end
+$var wire 8 |" out[0] [7:0] $end
+$var wire 8 }" out[1] [7:0] $end
 $scope module sub6_9 $end
-$var parameter 32 n" P0 [31:0] $end
-$var wire 8 l" out[0] [7:0] $end
-$var wire 8 m" out[1] [7:0] $end
+$var parameter 32 ~" P0 [31:0] $end
+$var parameter 32 !# P1 [31:0] $end
+$var wire 8 |" out[0] [7:0] $end
+$var wire 8 }" out[1] [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2.sub3_2.i_sub4_1 $end
-$var wire 1 o" clk $end
-$var wire 8 p" in [7:0] $end
-$var wire 8 q" out [7:0] $end
+$var wire 1 "# clk $end
+$var wire 8 ## in [7:0] $end
+$var wire 8 $# out [7:0] $end
 $scope module sub4_b $end
-$var wire 1 o" clk $end
-$var wire 8 p" in [7:0] $end
-$var wire 8 q" out [7:0] $end
-$var logic 8 r" ff [7:0] $end
-$var logic 128 s" sub5_in[0][0] [127:0] $end
-$var logic 128 t" sub5_in[0][1] [127:0] $end
-$var logic 128 u" sub5_in[0][2] [127:0] $end
-$var logic 128 v" sub5_in[1][0] [127:0] $end
-$var logic 128 w" sub5_in[1][1] [127:0] $end
-$var logic 128 x" sub5_in[1][2] [127:0] $end
-$var wire 8 y" sub5_out[0][0] [7:0] $end
-$var wire 8 z" sub5_out[0][1] [7:0] $end
-$var wire 8 {" sub5_out[0][2] [7:0] $end
-$var wire 8 |" sub5_out[1][0] [7:0] $end
-$var wire 8 }" sub5_out[1][1] [7:0] $end
-$var wire 8 ~" sub5_out[1][2] [7:0] $end
-$var int 32 !# count [31:0] $end
+$var parameter 32 %# P0 [31:0] $end
+$var real_parameter 64 &# P1 $end
+$var real_parameter 64 '# P3 $end
+$var wire 1 "# clk $end
+$var wire 8 ## in [7:0] $end
+$var wire 8 $# out [7:0] $end
+$var logic 8 (# ff [7:0] $end
+$var logic 128 )# sub5_in[0][0] [127:0] $end
+$var logic 128 *# sub5_in[0][1] [127:0] $end
+$var logic 128 +# sub5_in[0][2] [127:0] $end
+$var logic 128 ,# sub5_in[1][0] [127:0] $end
+$var logic 128 -# sub5_in[1][1] [127:0] $end
+$var logic 128 .# sub5_in[1][2] [127:0] $end
+$var wire 8 /# sub5_out[0][0] [7:0] $end
+$var wire 8 0# sub5_out[0][1] [7:0] $end
+$var wire 8 1# sub5_out[0][2] [7:0] $end
+$var wire 8 2# sub5_out[1][0] [7:0] $end
+$var wire 8 3# sub5_out[1][1] [7:0] $end
+$var wire 8 4# sub5_out[1][2] [7:0] $end
+$var int 32 5# count [31:0] $end
 $scope module i_sub5 $end
-$var wire 1 o" clk $end
-$var wire 128 "# in[0][0] [127:0] $end
-$var wire 128 ## in[0][1] [127:0] $end
-$var wire 128 $# in[0][2] [127:0] $end
-$var wire 128 %# in[1][0] [127:0] $end
-$var wire 128 &# in[1][1] [127:0] $end
-$var wire 128 '# in[1][2] [127:0] $end
-$var wire 8 (# out[0][0] [7:0] $end
-$var wire 8 )# out[0][1] [7:0] $end
-$var wire 8 *# out[0][2] [7:0] $end
-$var wire 8 +# out[1][0] [7:0] $end
-$var wire 8 ,# out[1][1] [7:0] $end
-$var wire 8 -# out[1][2] [7:0] $end
+$var wire 1 "# clk $end
+$var wire 128 6# in[0][0] [127:0] $end
+$var wire 128 7# in[0][1] [127:0] $end
+$var wire 128 8# in[0][2] [127:0] $end
+$var wire 128 9# in[1][0] [127:0] $end
+$var wire 128 :# in[1][1] [127:0] $end
+$var wire 128 ;# in[1][2] [127:0] $end
+$var wire 8 <# out[0][0] [7:0] $end
+$var wire 8 =# out[0][1] [7:0] $end
+$var wire 8 ># out[0][2] [7:0] $end
+$var wire 8 ?# out[1][0] [7:0] $end
+$var wire 8 @# out[1][1] [7:0] $end
+$var wire 8 A# out[1][2] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 .# i [31:0] $end
+$var int 32 B# i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 /# j [31:0] $end
+$var int 32 C# j [31:0] $end
 $scope module unnamedblk3 $end
-$var byte 8 0# exp [7:0] $end
+$var byte 8 D# exp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5 $end
-$var wire 1 1# clk $end
-$var wire 128 2# in[0][0] [127:0] $end
-$var wire 128 3# in[0][1] [127:0] $end
-$var wire 128 4# in[0][2] [127:0] $end
-$var wire 128 5# in[1][0] [127:0] $end
-$var wire 128 6# in[1][1] [127:0] $end
-$var wire 128 7# in[1][2] [127:0] $end
-$var wire 8 8# out[0][0] [7:0] $end
-$var wire 8 9# out[0][1] [7:0] $end
-$var wire 8 :# out[0][2] [7:0] $end
-$var wire 8 ;# out[1][0] [7:0] $end
-$var wire 8 <# out[1][1] [7:0] $end
-$var wire 8 =# out[1][2] [7:0] $end
+$var wire 1 E# clk $end
+$var wire 128 F# in[0][0] [127:0] $end
+$var wire 128 G# in[0][1] [127:0] $end
+$var wire 128 H# in[0][2] [127:0] $end
+$var wire 128 I# in[1][0] [127:0] $end
+$var wire 128 J# in[1][1] [127:0] $end
+$var wire 128 K# in[1][2] [127:0] $end
+$var wire 8 L# out[0][0] [7:0] $end
+$var wire 8 M# out[0][1] [7:0] $end
+$var wire 8 N# out[0][2] [7:0] $end
+$var wire 8 O# out[1][0] [7:0] $end
+$var wire 8 P# out[1][1] [7:0] $end
+$var wire 8 Q# out[1][2] [7:0] $end
 $scope module sub5 $end
-$var wire 1 1# clk $end
-$var wire 128 2# in[0][0] [127:0] $end
-$var wire 128 3# in[0][1] [127:0] $end
-$var wire 128 4# in[0][2] [127:0] $end
-$var wire 128 5# in[1][0] [127:0] $end
-$var wire 128 6# in[1][1] [127:0] $end
-$var wire 128 7# in[1][2] [127:0] $end
-$var wire 8 8# out[0][0] [7:0] $end
-$var wire 8 9# out[0][1] [7:0] $end
-$var wire 8 :# out[0][2] [7:0] $end
-$var wire 8 ;# out[1][0] [7:0] $end
-$var wire 8 <# out[1][1] [7:0] $end
-$var wire 8 =# out[1][2] [7:0] $end
-$var int 32 ># count [31:0] $end
-$var wire 8 ?# val0[0] [7:0] $end
-$var wire 8 @# val0[1] [7:0] $end
-$var wire 8 A# val1[0] [7:0] $end
-$var wire 8 B# val1[1] [7:0] $end
-$var wire 8 C# val2[0] [7:0] $end
-$var wire 8 D# val2[1] [7:0] $end
-$var wire 8 E# val3[0] [7:0] $end
-$var wire 8 F# val3[1] [7:0] $end
+$var wire 1 E# clk $end
+$var wire 128 F# in[0][0] [127:0] $end
+$var wire 128 G# in[0][1] [127:0] $end
+$var wire 128 H# in[0][2] [127:0] $end
+$var wire 128 I# in[1][0] [127:0] $end
+$var wire 128 J# in[1][1] [127:0] $end
+$var wire 128 K# in[1][2] [127:0] $end
+$var wire 8 L# out[0][0] [7:0] $end
+$var wire 8 M# out[0][1] [7:0] $end
+$var wire 8 N# out[0][2] [7:0] $end
+$var wire 8 O# out[1][0] [7:0] $end
+$var wire 8 P# out[1][1] [7:0] $end
+$var wire 8 Q# out[1][2] [7:0] $end
+$var int 32 R# count [31:0] $end
+$var wire 8 S# val0[0] [7:0] $end
+$var wire 8 T# val0[1] [7:0] $end
+$var wire 8 U# val1[0] [7:0] $end
+$var wire 8 V# val1[1] [7:0] $end
+$var wire 8 W# val2[0] [7:0] $end
+$var wire 8 X# val2[1] [7:0] $end
+$var wire 8 Y# val3[0] [7:0] $end
+$var wire 8 Z# val3[1] [7:0] $end
 $scope module i_sub0 $end
-$var parameter 32 G# P0 [31:0] $end
-$var parameter 32 H# P1 [31:0] $end
-$var wire 8 I# out[0] [7:0] $end
-$var wire 8 J# out[1] [7:0] $end
+$var parameter 32 [# P0 [31:0] $end
+$var parameter 32 \# P1 [31:0] $end
+$var wire 8 ]# out[0] [7:0] $end
+$var wire 8 ^# out[1] [7:0] $end
 $upscope $end
 $scope module i_sub1 $end
-$var parameter 32 G# P0 [31:0] $end
-$var parameter 32 H# P1 [31:0] $end
-$var wire 8 K# out[0] [7:0] $end
-$var wire 8 L# out[1] [7:0] $end
+$var parameter 32 [# P0 [31:0] $end
+$var parameter 32 \# P1 [31:0] $end
+$var wire 8 _# out[0] [7:0] $end
+$var wire 8 `# out[1] [7:0] $end
 $upscope $end
 $scope module i_sub2 $end
-$var parameter 32 G# P0 [31:0] $end
-$var parameter 32 H# P1 [31:0] $end
-$var wire 8 M# out[0] [7:0] $end
-$var wire 8 N# out[1] [7:0] $end
+$var parameter 32 [# P0 [31:0] $end
+$var parameter 32 \# P1 [31:0] $end
+$var wire 8 a# out[0] [7:0] $end
+$var wire 8 b# out[1] [7:0] $end
 $upscope $end
 $scope module i_sub3 $end
-$var wire 8 O# out[0] [7:0] $end
-$var wire 8 P# out[1] [7:0] $end
+$var wire 8 c# out[0] [7:0] $end
+$var wire 8 d# out[1] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 Q# i [31:0] $end
+$var int 32 e# i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 R# j [31:0] $end
+$var int 32 f# j [31:0] $end
 $scope module unnamedblk3 $end
-$var bit 128 S# exp [127:0] $end
+$var bit 128 g# exp [127:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end
-$var wire 8 T# out[0] [7:0] $end
-$var wire 8 U# out[1] [7:0] $end
+$var wire 8 h# out[0] [7:0] $end
+$var wire 8 i# out[1] [7:0] $end
 $scope module sub6_9 $end
-$var parameter 32 V# P0 [31:0] $end
-$var wire 8 T# out[0] [7:0] $end
-$var wire 8 U# out[1] [7:0] $end
+$var parameter 32 j# P0 [31:0] $end
+$var parameter 32 k# P1 [31:0] $end
+$var wire 8 h# out[0] [7:0] $end
+$var wire 8 i# out[1] [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3 $end
-$var wire 1 W# clk $end
-$var wire 8 X# in [7:0] $end
-$var wire 8 Y# out [7:0] $end
+$var wire 1 l# clk $end
+$var wire 8 m# in [7:0] $end
+$var wire 8 n# out [7:0] $end
 $scope module sub3_d $end
-$var parameter 32 Z# UNPACKED_ARRAY[0] [31:0] $end
-$var parameter 32 [# UNPACKED_ARRAY[1] [31:0] $end
-$var parameter 16 \# UNUSED [15:0] $end
-$var wire 1 W# clk $end
-$var wire 8 X# in [7:0] $end
-$var wire 8 Y# out [7:0] $end
-$var logic 8 ]# ff [7:0] $end
-$var wire 8 ^# out4 [7:0] $end
-$var wire 8 _# out4_2 [7:0] $end
+$var parameter 8 o# P0 [7:0] $end
+$var parameter 32 p# UNPACKED_ARRAY[0] [31:0] $end
+$var parameter 32 q# UNPACKED_ARRAY[1] [31:0] $end
+$var parameter 16 r# UNUSED [15:0] $end
+$var wire 1 l# clk $end
+$var wire 8 m# in [7:0] $end
+$var wire 8 n# out [7:0] $end
+$var logic 8 s# ff [7:0] $end
+$var wire 8 t# out4 [7:0] $end
+$var wire 8 u# out4_2 [7:0] $end
 $scope module i_sub4_0 $end
-$var wire 1 W# clk $end
-$var wire 8 ]# in [7:0] $end
-$var wire 8 ^# out [7:0] $end
+$var wire 1 l# clk $end
+$var wire 8 s# in [7:0] $end
+$var wire 8 t# out [7:0] $end
 $upscope $end
 $scope module i_sub4_1 $end
-$var wire 1 W# clk $end
-$var wire 8 ]# in [7:0] $end
-$var wire 8 _# out [7:0] $end
+$var wire 1 l# clk $end
+$var wire 8 s# in [7:0] $end
+$var wire 8 u# out [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3.sub3_d.i_sub4_0 $end
-$var wire 1 `# clk $end
-$var wire 8 a# in [7:0] $end
-$var wire 8 b# out [7:0] $end
+$var wire 1 v# clk $end
+$var wire 8 w# in [7:0] $end
+$var wire 8 x# out [7:0] $end
 $scope module sub4_2 $end
-$var wire 1 `# clk $end
-$var wire 8 a# in [7:0] $end
-$var wire 8 b# out [7:0] $end
-$var logic 8 c# ff [7:0] $end
-$var logic 128 d# sub5_in[0][0] [127:0] $end
-$var logic 128 e# sub5_in[0][1] [127:0] $end
-$var logic 128 f# sub5_in[0][2] [127:0] $end
-$var logic 128 g# sub5_in[1][0] [127:0] $end
-$var logic 128 h# sub5_in[1][1] [127:0] $end
-$var logic 128 i# sub5_in[1][2] [127:0] $end
-$var wire 8 j# sub5_out[0][0] [7:0] $end
-$var wire 8 k# sub5_out[0][1] [7:0] $end
-$var wire 8 l# sub5_out[0][2] [7:0] $end
-$var wire 8 m# sub5_out[1][0] [7:0] $end
-$var wire 8 n# sub5_out[1][1] [7:0] $end
-$var wire 8 o# sub5_out[1][2] [7:0] $end
-$var int 32 p# count [31:0] $end
+$var parameter 32 y# P0 [31:0] $end
+$var real_parameter 64 z# P1 $end
+$var real_parameter 64 {# P3 $end
+$var wire 1 v# clk $end
+$var wire 8 w# in [7:0] $end
+$var wire 8 x# out [7:0] $end
+$var logic 8 |# ff [7:0] $end
+$var logic 128 }# sub5_in[0][0] [127:0] $end
+$var logic 128 ~# sub5_in[0][1] [127:0] $end
+$var logic 128 !$ sub5_in[0][2] [127:0] $end
+$var logic 128 "$ sub5_in[1][0] [127:0] $end
+$var logic 128 #$ sub5_in[1][1] [127:0] $end
+$var logic 128 $$ sub5_in[1][2] [127:0] $end
+$var wire 8 %$ sub5_out[0][0] [7:0] $end
+$var wire 8 &$ sub5_out[0][1] [7:0] $end
+$var wire 8 '$ sub5_out[0][2] [7:0] $end
+$var wire 8 ($ sub5_out[1][0] [7:0] $end
+$var wire 8 )$ sub5_out[1][1] [7:0] $end
+$var wire 8 *$ sub5_out[1][2] [7:0] $end
+$var int 32 +$ count [31:0] $end
 $scope module i_sub5 $end
-$var wire 1 `# clk $end
-$var wire 128 q# in[0][0] [127:0] $end
-$var wire 128 r# in[0][1] [127:0] $end
-$var wire 128 s# in[0][2] [127:0] $end
-$var wire 128 t# in[1][0] [127:0] $end
-$var wire 128 u# in[1][1] [127:0] $end
-$var wire 128 v# in[1][2] [127:0] $end
-$var wire 8 w# out[0][0] [7:0] $end
-$var wire 8 x# out[0][1] [7:0] $end
-$var wire 8 y# out[0][2] [7:0] $end
-$var wire 8 z# out[1][0] [7:0] $end
-$var wire 8 {# out[1][1] [7:0] $end
-$var wire 8 |# out[1][2] [7:0] $end
+$var wire 1 v# clk $end
+$var wire 128 ,$ in[0][0] [127:0] $end
+$var wire 128 -$ in[0][1] [127:0] $end
+$var wire 128 .$ in[0][2] [127:0] $end
+$var wire 128 /$ in[1][0] [127:0] $end
+$var wire 128 0$ in[1][1] [127:0] $end
+$var wire 128 1$ in[1][2] [127:0] $end
+$var wire 8 2$ out[0][0] [7:0] $end
+$var wire 8 3$ out[0][1] [7:0] $end
+$var wire 8 4$ out[0][2] [7:0] $end
+$var wire 8 5$ out[1][0] [7:0] $end
+$var wire 8 6$ out[1][1] [7:0] $end
+$var wire 8 7$ out[1][2] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 }# i [31:0] $end
+$var int 32 8$ i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 ~# j [31:0] $end
+$var int 32 9$ j [31:0] $end
 $scope module unnamedblk3 $end
-$var byte 8 !$ exp [7:0] $end
+$var byte 8 :$ exp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5 $end
-$var wire 1 "$ clk $end
-$var wire 128 #$ in[0][0] [127:0] $end
-$var wire 128 $$ in[0][1] [127:0] $end
-$var wire 128 %$ in[0][2] [127:0] $end
-$var wire 128 &$ in[1][0] [127:0] $end
-$var wire 128 '$ in[1][1] [127:0] $end
-$var wire 128 ($ in[1][2] [127:0] $end
-$var wire 8 )$ out[0][0] [7:0] $end
-$var wire 8 *$ out[0][1] [7:0] $end
-$var wire 8 +$ out[0][2] [7:0] $end
-$var wire 8 ,$ out[1][0] [7:0] $end
-$var wire 8 -$ out[1][1] [7:0] $end
-$var wire 8 .$ out[1][2] [7:0] $end
+$var wire 1 ;$ clk $end
+$var wire 128 <$ in[0][0] [127:0] $end
+$var wire 128 =$ in[0][1] [127:0] $end
+$var wire 128 >$ in[0][2] [127:0] $end
+$var wire 128 ?$ in[1][0] [127:0] $end
+$var wire 128 @$ in[1][1] [127:0] $end
+$var wire 128 A$ in[1][2] [127:0] $end
+$var wire 8 B$ out[0][0] [7:0] $end
+$var wire 8 C$ out[0][1] [7:0] $end
+$var wire 8 D$ out[0][2] [7:0] $end
+$var wire 8 E$ out[1][0] [7:0] $end
+$var wire 8 F$ out[1][1] [7:0] $end
+$var wire 8 G$ out[1][2] [7:0] $end
 $scope module sub5 $end
-$var wire 1 "$ clk $end
-$var wire 128 #$ in[0][0] [127:0] $end
-$var wire 128 $$ in[0][1] [127:0] $end
-$var wire 128 %$ in[0][2] [127:0] $end
-$var wire 128 &$ in[1][0] [127:0] $end
-$var wire 128 '$ in[1][1] [127:0] $end
-$var wire 128 ($ in[1][2] [127:0] $end
-$var wire 8 )$ out[0][0] [7:0] $end
-$var wire 8 *$ out[0][1] [7:0] $end
-$var wire 8 +$ out[0][2] [7:0] $end
-$var wire 8 ,$ out[1][0] [7:0] $end
-$var wire 8 -$ out[1][1] [7:0] $end
-$var wire 8 .$ out[1][2] [7:0] $end
-$var int 32 /$ count [31:0] $end
-$var wire 8 0$ val0[0] [7:0] $end
-$var wire 8 1$ val0[1] [7:0] $end
-$var wire 8 2$ val1[0] [7:0] $end
-$var wire 8 3$ val1[1] [7:0] $end
-$var wire 8 4$ val2[0] [7:0] $end
-$var wire 8 5$ val2[1] [7:0] $end
-$var wire 8 6$ val3[0] [7:0] $end
-$var wire 8 7$ val3[1] [7:0] $end
+$var wire 1 ;$ clk $end
+$var wire 128 <$ in[0][0] [127:0] $end
+$var wire 128 =$ in[0][1] [127:0] $end
+$var wire 128 >$ in[0][2] [127:0] $end
+$var wire 128 ?$ in[1][0] [127:0] $end
+$var wire 128 @$ in[1][1] [127:0] $end
+$var wire 128 A$ in[1][2] [127:0] $end
+$var wire 8 B$ out[0][0] [7:0] $end
+$var wire 8 C$ out[0][1] [7:0] $end
+$var wire 8 D$ out[0][2] [7:0] $end
+$var wire 8 E$ out[1][0] [7:0] $end
+$var wire 8 F$ out[1][1] [7:0] $end
+$var wire 8 G$ out[1][2] [7:0] $end
+$var int 32 H$ count [31:0] $end
+$var wire 8 I$ val0[0] [7:0] $end
+$var wire 8 J$ val0[1] [7:0] $end
+$var wire 8 K$ val1[0] [7:0] $end
+$var wire 8 L$ val1[1] [7:0] $end
+$var wire 8 M$ val2[0] [7:0] $end
+$var wire 8 N$ val2[1] [7:0] $end
+$var wire 8 O$ val3[0] [7:0] $end
+$var wire 8 P$ val3[1] [7:0] $end
 $scope module i_sub0 $end
-$var parameter 32 8$ P0 [31:0] $end
-$var parameter 32 9$ P1 [31:0] $end
-$var wire 8 :$ out[0] [7:0] $end
-$var wire 8 ;$ out[1] [7:0] $end
+$var parameter 32 Q$ P0 [31:0] $end
+$var parameter 32 R$ P1 [31:0] $end
+$var wire 8 S$ out[0] [7:0] $end
+$var wire 8 T$ out[1] [7:0] $end
 $upscope $end
 $scope module i_sub1 $end
-$var parameter 32 8$ P0 [31:0] $end
-$var parameter 32 9$ P1 [31:0] $end
-$var wire 8 <$ out[0] [7:0] $end
-$var wire 8 =$ out[1] [7:0] $end
+$var parameter 32 Q$ P0 [31:0] $end
+$var parameter 32 R$ P1 [31:0] $end
+$var wire 8 U$ out[0] [7:0] $end
+$var wire 8 V$ out[1] [7:0] $end
 $upscope $end
 $scope module i_sub2 $end
-$var parameter 32 8$ P0 [31:0] $end
-$var parameter 32 9$ P1 [31:0] $end
-$var wire 8 >$ out[0] [7:0] $end
-$var wire 8 ?$ out[1] [7:0] $end
+$var parameter 32 Q$ P0 [31:0] $end
+$var parameter 32 R$ P1 [31:0] $end
+$var wire 8 W$ out[0] [7:0] $end
+$var wire 8 X$ out[1] [7:0] $end
 $upscope $end
 $scope module i_sub3 $end
-$var wire 8 @$ out[0] [7:0] $end
-$var wire 8 A$ out[1] [7:0] $end
+$var wire 8 Y$ out[0] [7:0] $end
+$var wire 8 Z$ out[1] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 B$ i [31:0] $end
+$var int 32 [$ i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 C$ j [31:0] $end
+$var int 32 \$ j [31:0] $end
 $scope module unnamedblk3 $end
-$var bit 128 D$ exp [127:0] $end
+$var bit 128 ]$ exp [127:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end
-$var wire 8 E$ out[0] [7:0] $end
-$var wire 8 F$ out[1] [7:0] $end
+$var wire 8 ^$ out[0] [7:0] $end
+$var wire 8 _$ out[1] [7:0] $end
 $scope module sub6_9 $end
-$var parameter 32 G$ P0 [31:0] $end
-$var wire 8 E$ out[0] [7:0] $end
-$var wire 8 F$ out[1] [7:0] $end
+$var parameter 32 `$ P0 [31:0] $end
+$var parameter 32 a$ P1 [31:0] $end
+$var wire 8 ^$ out[0] [7:0] $end
+$var wire 8 _$ out[1] [7:0] $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3.sub3_d.i_sub4_1 $end
-$var wire 1 H$ clk $end
-$var wire 8 I$ in [7:0] $end
-$var wire 8 J$ out [7:0] $end
+$var wire 1 b$ clk $end
+$var wire 8 c$ in [7:0] $end
+$var wire 8 d$ out [7:0] $end
 $scope module sub4_b $end
-$var wire 1 H$ clk $end
-$var wire 8 I$ in [7:0] $end
-$var wire 8 J$ out [7:0] $end
-$var logic 8 K$ ff [7:0] $end
-$var logic 128 L$ sub5_in[0][0] [127:0] $end
-$var logic 128 M$ sub5_in[0][1] [127:0] $end
-$var logic 128 N$ sub5_in[0][2] [127:0] $end
-$var logic 128 O$ sub5_in[1][0] [127:0] $end
-$var logic 128 P$ sub5_in[1][1] [127:0] $end
-$var logic 128 Q$ sub5_in[1][2] [127:0] $end
-$var wire 8 R$ sub5_out[0][0] [7:0] $end
-$var wire 8 S$ sub5_out[0][1] [7:0] $end
-$var wire 8 T$ sub5_out[0][2] [7:0] $end
-$var wire 8 U$ sub5_out[1][0] [7:0] $end
-$var wire 8 V$ sub5_out[1][1] [7:0] $end
-$var wire 8 W$ sub5_out[1][2] [7:0] $end
-$var int 32 X$ count [31:0] $end
+$var parameter 32 e$ P0 [31:0] $end
+$var real_parameter 64 f$ P1 $end
+$var real_parameter 64 g$ P3 $end
+$var wire 1 b$ clk $end
+$var wire 8 c$ in [7:0] $end
+$var wire 8 d$ out [7:0] $end
+$var logic 8 h$ ff [7:0] $end
+$var logic 128 i$ sub5_in[0][0] [127:0] $end
+$var logic 128 j$ sub5_in[0][1] [127:0] $end
+$var logic 128 k$ sub5_in[0][2] [127:0] $end
+$var logic 128 l$ sub5_in[1][0] [127:0] $end
+$var logic 128 m$ sub5_in[1][1] [127:0] $end
+$var logic 128 n$ sub5_in[1][2] [127:0] $end
+$var wire 8 o$ sub5_out[0][0] [7:0] $end
+$var wire 8 p$ sub5_out[0][1] [7:0] $end
+$var wire 8 q$ sub5_out[0][2] [7:0] $end
+$var wire 8 r$ sub5_out[1][0] [7:0] $end
+$var wire 8 s$ sub5_out[1][1] [7:0] $end
+$var wire 8 t$ sub5_out[1][2] [7:0] $end
+$var int 32 u$ count [31:0] $end
 $scope module i_sub5 $end
-$var wire 1 H$ clk $end
-$var wire 128 Y$ in[0][0] [127:0] $end
-$var wire 128 Z$ in[0][1] [127:0] $end
-$var wire 128 [$ in[0][2] [127:0] $end
-$var wire 128 \$ in[1][0] [127:0] $end
-$var wire 128 ]$ in[1][1] [127:0] $end
-$var wire 128 ^$ in[1][2] [127:0] $end
-$var wire 8 _$ out[0][0] [7:0] $end
-$var wire 8 `$ out[0][1] [7:0] $end
-$var wire 8 a$ out[0][2] [7:0] $end
-$var wire 8 b$ out[1][0] [7:0] $end
-$var wire 8 c$ out[1][1] [7:0] $end
-$var wire 8 d$ out[1][2] [7:0] $end
+$var wire 1 b$ clk $end
+$var wire 128 v$ in[0][0] [127:0] $end
+$var wire 128 w$ in[0][1] [127:0] $end
+$var wire 128 x$ in[0][2] [127:0] $end
+$var wire 128 y$ in[1][0] [127:0] $end
+$var wire 128 z$ in[1][1] [127:0] $end
+$var wire 128 {$ in[1][2] [127:0] $end
+$var wire 8 |$ out[0][0] [7:0] $end
+$var wire 8 }$ out[0][1] [7:0] $end
+$var wire 8 ~$ out[0][2] [7:0] $end
+$var wire 8 !% out[1][0] [7:0] $end
+$var wire 8 "% out[1][1] [7:0] $end
+$var wire 8 #% out[1][2] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
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+$var int 32 $% i [31:0] $end
 $scope module unnamedblk2 $end
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+$var int 32 %% j [31:0] $end
 $scope module unnamedblk3 $end
-$var byte 8 g$ exp [7:0] $end
+$var byte 8 &% exp [7:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5 $end
-$var wire 1 h$ clk $end
-$var wire 128 i$ in[0][0] [127:0] $end
-$var wire 128 j$ in[0][1] [127:0] $end
-$var wire 128 k$ in[0][2] [127:0] $end
-$var wire 128 l$ in[1][0] [127:0] $end
-$var wire 128 m$ in[1][1] [127:0] $end
-$var wire 128 n$ in[1][2] [127:0] $end
-$var wire 8 o$ out[0][0] [7:0] $end
-$var wire 8 p$ out[0][1] [7:0] $end
-$var wire 8 q$ out[0][2] [7:0] $end
-$var wire 8 r$ out[1][0] [7:0] $end
-$var wire 8 s$ out[1][1] [7:0] $end
-$var wire 8 t$ out[1][2] [7:0] $end
+$var wire 1 '% clk $end
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+$var wire 128 )% in[0][1] [127:0] $end
+$var wire 128 *% in[0][2] [127:0] $end
+$var wire 128 +% in[1][0] [127:0] $end
+$var wire 128 ,% in[1][1] [127:0] $end
+$var wire 128 -% in[1][2] [127:0] $end
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+$var wire 8 /% out[0][1] [7:0] $end
+$var wire 8 0% out[0][2] [7:0] $end
+$var wire 8 1% out[1][0] [7:0] $end
+$var wire 8 2% out[1][1] [7:0] $end
+$var wire 8 3% out[1][2] [7:0] $end
 $scope module sub5 $end
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-$var wire 128 j$ in[0][1] [127:0] $end
-$var wire 128 k$ in[0][2] [127:0] $end
-$var wire 128 l$ in[1][0] [127:0] $end
-$var wire 128 m$ in[1][1] [127:0] $end
-$var wire 128 n$ in[1][2] [127:0] $end
-$var wire 8 o$ out[0][0] [7:0] $end
-$var wire 8 p$ out[0][1] [7:0] $end
-$var wire 8 q$ out[0][2] [7:0] $end
-$var wire 8 r$ out[1][0] [7:0] $end
-$var wire 8 s$ out[1][1] [7:0] $end
-$var wire 8 t$ out[1][2] [7:0] $end
-$var int 32 u$ count [31:0] $end
-$var wire 8 v$ val0[0] [7:0] $end
-$var wire 8 w$ val0[1] [7:0] $end
-$var wire 8 x$ val1[0] [7:0] $end
-$var wire 8 y$ val1[1] [7:0] $end
-$var wire 8 z$ val2[0] [7:0] $end
-$var wire 8 {$ val2[1] [7:0] $end
-$var wire 8 |$ val3[0] [7:0] $end
-$var wire 8 }$ val3[1] [7:0] $end
+$var wire 1 '% clk $end
+$var wire 128 (% in[0][0] [127:0] $end
+$var wire 128 )% in[0][1] [127:0] $end
+$var wire 128 *% in[0][2] [127:0] $end
+$var wire 128 +% in[1][0] [127:0] $end
+$var wire 128 ,% in[1][1] [127:0] $end
+$var wire 128 -% in[1][2] [127:0] $end
+$var wire 8 .% out[0][0] [7:0] $end
+$var wire 8 /% out[0][1] [7:0] $end
+$var wire 8 0% out[0][2] [7:0] $end
+$var wire 8 1% out[1][0] [7:0] $end
+$var wire 8 2% out[1][1] [7:0] $end
+$var wire 8 3% out[1][2] [7:0] $end
+$var int 32 4% count [31:0] $end
+$var wire 8 5% val0[0] [7:0] $end
+$var wire 8 6% val0[1] [7:0] $end
+$var wire 8 7% val1[0] [7:0] $end
+$var wire 8 8% val1[1] [7:0] $end
+$var wire 8 9% val2[0] [7:0] $end
+$var wire 8 :% val2[1] [7:0] $end
+$var wire 8 ;% val3[0] [7:0] $end
+$var wire 8 <% val3[1] [7:0] $end
 $scope module i_sub0 $end
-$var parameter 32 ~$ P0 [31:0] $end
-$var parameter 32 !% P1 [31:0] $end
-$var wire 8 "% out[0] [7:0] $end
-$var wire 8 #% out[1] [7:0] $end
+$var parameter 32 =% P0 [31:0] $end
+$var parameter 32 >% P1 [31:0] $end
+$var wire 8 ?% out[0] [7:0] $end
+$var wire 8 @% out[1] [7:0] $end
 $upscope $end
 $scope module i_sub1 $end
-$var parameter 32 ~$ P0 [31:0] $end
-$var parameter 32 !% P1 [31:0] $end
-$var wire 8 $% out[0] [7:0] $end
-$var wire 8 %% out[1] [7:0] $end
+$var parameter 32 =% P0 [31:0] $end
+$var parameter 32 >% P1 [31:0] $end
+$var wire 8 A% out[0] [7:0] $end
+$var wire 8 B% out[1] [7:0] $end
 $upscope $end
 $scope module i_sub2 $end
-$var parameter 32 ~$ P0 [31:0] $end
-$var parameter 32 !% P1 [31:0] $end
-$var wire 8 &% out[0] [7:0] $end
-$var wire 8 '% out[1] [7:0] $end
+$var parameter 32 =% P0 [31:0] $end
+$var parameter 32 >% P1 [31:0] $end
+$var wire 8 C% out[0] [7:0] $end
+$var wire 8 D% out[1] [7:0] $end
 $upscope $end
 $scope module i_sub3 $end
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+$var wire 8 E% out[0] [7:0] $end
+$var wire 8 F% out[1] [7:0] $end
 $upscope $end
 $scope module unnamedblk1 $end
-$var int 32 *% i [31:0] $end
+$var int 32 G% i [31:0] $end
 $scope module unnamedblk2 $end
-$var int 32 +% j [31:0] $end
+$var int 32 H% j [31:0] $end
 $scope module unnamedblk3 $end
-$var bit 128 ,% exp [127:0] $end
+$var bit 128 I% exp [127:0] $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $upscope $end
 $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end
-$var wire 8 -% out[0] [7:0] $end
-$var wire 8 .% out[1] [7:0] $end
+$var wire 8 J% out[0] [7:0] $end
+$var wire 8 K% out[1] [7:0] $end
 $scope module sub6_9 $end
-$var parameter 32 /% P0 [31:0] $end
-$var wire 8 -% out[0] [7:0] $end
-$var wire 8 .% out[1] [7:0] $end
+$var parameter 32 L% P0 [31:0] $end
+$var parameter 32 M% P1 [31:0] $end
+$var wire 8 J% out[0] [7:0] $end
+$var wire 8 K% out[1] [7:0] $end
 $upscope $end
 $upscope $end
 $enddefinitions $end
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 b00010101 (
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diff --git a/test_regress/t/t_hier_block_trace_vcd.out b/test_regress/t/t_hier_block_trace_vcd.out
index 993b40bbe..e9b9dbdcb 100644
--- a/test_regress/t/t_hier_block_trace_vcd.out
+++ b/test_regress/t/t_hier_block_trace_vcd.out
@@ -1,5 +1,5 @@
 $version Generated by VerilatedVcd $end
-$date Tue Oct 18 17:20:50 2022 $end
+$date Thu Nov 10 20:18:10 2022 $end
 $timescale 1ps $end
 
  $scope module top $end
@@ -61,15 +61,16 @@ $timescale 1ps $end
   $var wire  8 . in [7:0] $end
   $var wire  8 / out [7:0] $end
   $scope module delay_2 $end
-   $var wire 32 2 WIDTH [31:0] $end
+   $var wire 32 2 N [31:0] $end
+   $var wire 32 3 WIDTH [31:0] $end
    $var wire  1 - clk $end
    $var wire  8 . in [7:0] $end
    $var wire  8 / out [7:0] $end
    $var wire  8 0 tmp [7:0] $end
    $scope module genblk1 $end
     $scope module i_delay $end
-     $var wire 32 3 N [31:0] $end
-     $var wire 32 2 WIDTH [31:0] $end
+     $var wire 32 4 N [31:0] $end
+     $var wire 32 3 WIDTH [31:0] $end
      $var wire  1 - clk $end
      $var wire  8 0 in [7:0] $end
      $var wire  8 / out [7:0] $end
@@ -79,31 +80,32 @@ $timescale 1ps $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_delay1 $end
-  $var wire  1 8 clk $end
-  $var wire  8 9 in [7:0] $end
-  $var wire  8 : out [7:0] $end
+  $var wire  1 9 clk $end
+  $var wire  8 : in [7:0] $end
+  $var wire  8 ; out [7:0] $end
   $scope module delay_9 $end
-   $var wire 32 ; WIDTH [31:0] $end
-   $var wire  1 8 clk $end
-   $var wire  8 9 in [7:0] $end
-   $var wire  8 : out [7:0] $end
-   $var wire  8 5 tmp [7:0] $end
+   $var wire 32 < N [31:0] $end
+   $var wire 32 = WIDTH [31:0] $end
+   $var wire  1 9 clk $end
+   $var wire  8 : in [7:0] $end
+   $var wire  8 ; out [7:0] $end
+   $var wire  8 6 tmp [7:0] $end
    $scope module genblk1 $end
     $scope module i_delay $end
-     $var wire 32 < N [31:0] $end
-     $var wire 32 ; WIDTH [31:0] $end
-     $var wire  1 8 clk $end
-     $var wire  8 5 in [7:0] $end
-     $var wire  8 : out [7:0] $end
-     $var wire  8 6 tmp [7:0] $end
+     $var wire 32 > N [31:0] $end
+     $var wire 32 = WIDTH [31:0] $end
+     $var wire  1 9 clk $end
+     $var wire  8 6 in [7:0] $end
+     $var wire  8 ; out [7:0] $end
+     $var wire  8 7 tmp [7:0] $end
      $scope module genblk1 $end
       $scope module i_delay $end
-       $var wire 32 = N [31:0] $end
-       $var wire 32 ; WIDTH [31:0] $end
-       $var wire  1 8 clk $end
-       $var wire  8 6 in [7:0] $end
-       $var wire  8 : out [7:0] $end
-       $var wire  8 7 tmp [7:0] $end
+       $var wire 32 ? N [31:0] $end
+       $var wire 32 = WIDTH [31:0] $end
+       $var wire  1 9 clk $end
+       $var wire  8 7 in [7:0] $end
+       $var wire  8 ; out [7:0] $end
+       $var wire  8 8 tmp [7:0] $end
       $upscope $end
      $upscope $end
     $upscope $end
@@ -111,906 +113,934 @@ $timescale 1ps $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub0.i_sub0 $end
-  $var wire  1 ? clk $end
-  $var wire  8 @ in [7:0] $end
-  $var wire  8 A out [7:0] $end
+  $var wire  1 A clk $end
+  $var wire  8 B in [7:0] $end
+  $var wire  8 C out [7:0] $end
   $scope module sub0 $end
-   $var wire  1 ? clk $end
-   $var wire  8 B ff [7:0] $end
-   $var wire  8 @ in [7:0] $end
-   $var wire  8 A out [7:0] $end
+   $var wire  1 A clk $end
+   $var wire  8 D ff [7:0] $end
+   $var wire  8 B in [7:0] $end
+   $var wire  8 C out [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub1 $end
-  $var wire  1 D clk $end
-  $var wire  8 E in [11:4] $end
-  $var wire  8 F out [7:0] $end
+  $var wire  1 F clk $end
+  $var wire  8 G in [11:4] $end
+  $var wire  8 H out [7:0] $end
   $scope module sub1 $end
-   $var wire  1 D clk $end
-   $var wire  8 G ff [7:0] $end
-   $var wire  8 E in [11:4] $end
-   $var wire  8 F out [7:0] $end
+   $var wire  1 F clk $end
+   $var wire  8 I ff [7:0] $end
+   $var wire  8 G in [11:4] $end
+   $var wire  8 H out [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2 $end
-  $var wire  1 I clk $end
-  $var wire  8 J in [7:0] $end
-  $var wire  8 K out [7:0] $end
+  $var wire  1 K clk $end
+  $var wire  8 L in [7:0] $end
+  $var wire  8 M out [7:0] $end
   $scope module sub2 $end
-   $var wire  1 I clk $end
-   $var wire  8 L ff [7:0] $end
-   $var wire  8 J in [7:0] $end
-   $var wire  8 K out [7:0] $end
+   $var wire  1 K clk $end
+   $var wire  8 N ff [7:0] $end
+   $var wire  8 L in [7:0] $end
+   $var wire  8 M out [7:0] $end
    $scope module i_sub3 $end
-    $var wire  8 L in_wire [7:0] $end
-    $var wire  8 M out_1 [7:0] $end
-    $var wire  8 N out_2 [7:0] $end
+    $var wire  8 N in_wire [7:0] $end
+    $var wire  8 O out_1 [7:0] $end
+    $var wire  8 P out_2 [7:0] $end
     $scope module i_sub3 $end
-     $var wire  1 I clk $end
-     $var wire  8 L in [7:0] $end
-     $var wire  8 M out [7:0] $end
+     $var wire  1 K clk $end
+     $var wire  8 N in [7:0] $end
+     $var wire  8 O out [7:0] $end
     $upscope $end
     $scope module i_sub3_2 $end
-     $var wire  1 I clk $end
-     $var wire  8 L in [7:0] $end
-     $var wire  8 N out [7:0] $end
+     $var wire  1 K clk $end
+     $var wire  8 N in [7:0] $end
+     $var wire  8 P out [7:0] $end
     $upscope $end
     $scope interface in $end
-     $var wire  1 I clk $end
-     $var wire  8 L data [7:0] $end
+     $var wire  1 K clk $end
+     $var wire  8 N data [7:0] $end
     $upscope $end
     $scope interface out $end
-     $var wire  1 I clk $end
-     $var wire  8 M data [7:0] $end
+     $var wire  1 K clk $end
+     $var wire  8 O data [7:0] $end
     $upscope $end
    $upscope $end
    $scope interface in_ifs $end
-    $var wire  1 I clk $end
-    $var wire  8 L data [7:0] $end
+    $var wire  1 K clk $end
+    $var wire  8 N data [7:0] $end
    $upscope $end
    $scope interface out_ifs $end
-    $var wire  1 I clk $end
-    $var wire  8 M data [7:0] $end
+    $var wire  1 K clk $end
+    $var wire  8 O data [7:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3 $end
-  $var wire  1 P clk $end
-  $var wire  8 Q in [7:0] $end
-  $var wire  8 R out [7:0] $end
+  $var wire  1 R clk $end
+  $var wire  8 S in [7:0] $end
+  $var wire  8 T out [7:0] $end
   $scope module sub3_c $end
-   $var wire 32 V UNPACKED_ARRAY[0] [31:0] $end
-   $var wire 32 W UNPACKED_ARRAY[1] [31:0] $end
-   $var wire  1 P clk $end
-   $var wire  8 S ff [7:0] $end
-   $var wire  8 Q in [7:0] $end
-   $var wire  8 R out [7:0] $end
-   $var wire  8 T out4 [7:0] $end
-   $var wire  8 U out4_2 [7:0] $end
+   $var wire  8 X P0 [7:0] $end
+   $var wire 32 Y UNPACKED_ARRAY[0] [31:0] $end
+   $var wire 32 Z UNPACKED_ARRAY[1] [31:0] $end
+   $var wire 16 [ UNUSED [15:0] $end
+   $var wire  1 R clk $end
+   $var wire  8 U ff [7:0] $end
+   $var wire  8 S in [7:0] $end
+   $var wire  8 T out [7:0] $end
+   $var wire  8 V out4 [7:0] $end
+   $var wire  8 W out4_2 [7:0] $end
    $scope module i_sub4_0 $end
-    $var wire  1 P clk $end
-    $var wire  8 S in [7:0] $end
-    $var wire  8 T out [7:0] $end
+    $var wire  1 R clk $end
+    $var wire  8 U in [7:0] $end
+    $var wire  8 V out [7:0] $end
    $upscope $end
    $scope module i_sub4_1 $end
-    $var wire  1 P clk $end
-    $var wire  8 S in [7:0] $end
-    $var wire  8 U out [7:0] $end
+    $var wire  1 R clk $end
+    $var wire  8 U in [7:0] $end
+    $var wire  8 W out [7:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0 $end
-  $var wire  1 <! clk $end
-  $var wire  8 =! in [7:0] $end
-  $var wire  8 >! out [7:0] $end
+  $var wire  1 @! clk $end
+  $var wire  8 A! in [7:0] $end
+  $var wire  8 B! out [7:0] $end
   $scope module sub4_2 $end
-   $var wire  1 <! clk $end
-   $var wire 32 r count [31:0] $end
-   $var wire  8 Y ff [7:0] $end
-   $var wire  8 =! in [7:0] $end
-   $var wire  8 >! out [7:0] $end
-   $var wire 128 Z sub5_in[0][0] [127:0] $end
-   $var wire 128 ^ sub5_in[0][1] [127:0] $end
-   $var wire 128 b sub5_in[0][2] [127:0] $end
-   $var wire 128 f sub5_in[1][0] [127:0] $end
-   $var wire 128 j sub5_in[1][1] [127:0] $end
-   $var wire 128 n sub5_in[1][2] [127:0] $end
-   $var wire  8 0! sub5_out[0][0] [7:0] $end
-   $var wire  8 1! sub5_out[0][1] [7:0] $end
-   $var wire  8 2! sub5_out[0][2] [7:0] $end
-   $var wire  8 3! sub5_out[1][0] [7:0] $end
-   $var wire  8 4! sub5_out[1][1] [7:0] $end
-   $var wire  8 5! sub5_out[1][2] [7:0] $end
+   $var wire 32 C! P0 [31:0] $end
+   $var real 64 D! P1 $end
+   $var real 64 F! P3 $end
+   $var wire  1 @! clk $end
+   $var wire 32 v count [31:0] $end
+   $var wire  8 ] ff [7:0] $end
+   $var wire  8 A! in [7:0] $end
+   $var wire  8 B! out [7:0] $end
+   $var wire 128 ^ sub5_in[0][0] [127:0] $end
+   $var wire 128 b sub5_in[0][1] [127:0] $end
+   $var wire 128 f sub5_in[0][2] [127:0] $end
+   $var wire 128 j sub5_in[1][0] [127:0] $end
+   $var wire 128 n sub5_in[1][1] [127:0] $end
+   $var wire 128 r sub5_in[1][2] [127:0] $end
+   $var wire  8 4! sub5_out[0][0] [7:0] $end
+   $var wire  8 5! sub5_out[0][1] [7:0] $end
+   $var wire  8 6! sub5_out[0][2] [7:0] $end
+   $var wire  8 7! sub5_out[1][0] [7:0] $end
+   $var wire  8 8! sub5_out[1][1] [7:0] $end
+   $var wire  8 9! sub5_out[1][2] [7:0] $end
    $scope module i_sub5 $end
-    $var wire  1 <! clk $end
-    $var wire 128 v in[0][0] [127:0] $end
-    $var wire 128 z in[0][1] [127:0] $end
-    $var wire 128 ~ in[0][2] [127:0] $end
-    $var wire 128 $! in[1][0] [127:0] $end
-    $var wire 128 (! in[1][1] [127:0] $end
-    $var wire 128 ,! in[1][2] [127:0] $end
-    $var wire  8 6! out[0][0] [7:0] $end
-    $var wire  8 7! out[0][1] [7:0] $end
-    $var wire  8 8! out[0][2] [7:0] $end
-    $var wire  8 9! out[1][0] [7:0] $end
-    $var wire  8 :! out[1][1] [7:0] $end
-    $var wire  8 ;! out[1][2] [7:0] $end
+    $var wire  1 @! clk $end
+    $var wire 128 z in[0][0] [127:0] $end
+    $var wire 128 ~ in[0][1] [127:0] $end
+    $var wire 128 $! in[0][2] [127:0] $end
+    $var wire 128 (! in[1][0] [127:0] $end
+    $var wire 128 ,! in[1][1] [127:0] $end
+    $var wire 128 0! in[1][2] [127:0] $end
+    $var wire  8 :! out[0][0] [7:0] $end
+    $var wire  8 ;! out[0][1] [7:0] $end
+    $var wire  8 <! out[0][2] [7:0] $end
+    $var wire  8 =! out[1][0] [7:0] $end
+    $var wire  8 >! out[1][1] [7:0] $end
+    $var wire  8 ?! out[1][2] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 s i [31:0] $end
+    $var wire 32 w i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 t j [31:0] $end
+     $var wire 32 x j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire  8 u exp [7:0] $end
+      $var wire  8 y exp [7:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5 $end
-  $var wire  1 W! clk $end
-  $var wire 128 X! in[0][0] [127:0] $end
-  $var wire 128 \! in[0][1] [127:0] $end
-  $var wire 128 `! in[0][2] [127:0] $end
-  $var wire 128 d! in[1][0] [127:0] $end
-  $var wire 128 h! in[1][1] [127:0] $end
-  $var wire 128 l! in[1][2] [127:0] $end
-  $var wire  8 p! out[0][0] [7:0] $end
-  $var wire  8 q! out[0][1] [7:0] $end
-  $var wire  8 r! out[0][2] [7:0] $end
-  $var wire  8 s! out[1][0] [7:0] $end
-  $var wire  8 t! out[1][1] [7:0] $end
-  $var wire  8 u! out[1][2] [7:0] $end
+  $var wire  1 `! clk $end
+  $var wire 128 a! in[0][0] [127:0] $end
+  $var wire 128 e! in[0][1] [127:0] $end
+  $var wire 128 i! in[0][2] [127:0] $end
+  $var wire 128 m! in[1][0] [127:0] $end
+  $var wire 128 q! in[1][1] [127:0] $end
+  $var wire 128 u! in[1][2] [127:0] $end
+  $var wire  8 y! out[0][0] [7:0] $end
+  $var wire  8 z! out[0][1] [7:0] $end
+  $var wire  8 {! out[0][2] [7:0] $end
+  $var wire  8 |! out[1][0] [7:0] $end
+  $var wire  8 }! out[1][1] [7:0] $end
+  $var wire  8 ~! out[1][2] [7:0] $end
   $scope module sub5 $end
-   $var wire  1 W! clk $end
-   $var wire 32 P! count [31:0] $end
-   $var wire 128 X! in[0][0] [127:0] $end
-   $var wire 128 \! in[0][1] [127:0] $end
-   $var wire 128 `! in[0][2] [127:0] $end
-   $var wire 128 d! in[1][0] [127:0] $end
-   $var wire 128 h! in[1][1] [127:0] $end
-   $var wire 128 l! in[1][2] [127:0] $end
-   $var wire  8 p! out[0][0] [7:0] $end
-   $var wire  8 q! out[0][1] [7:0] $end
-   $var wire  8 r! out[0][2] [7:0] $end
-   $var wire  8 s! out[1][0] [7:0] $end
-   $var wire  8 t! out[1][1] [7:0] $end
-   $var wire  8 u! out[1][2] [7:0] $end
-   $var wire  8 @! val0[0] [7:0] $end
-   $var wire  8 A! val0[1] [7:0] $end
-   $var wire  8 B! val1[0] [7:0] $end
-   $var wire  8 C! val1[1] [7:0] $end
-   $var wire  8 D! val2[0] [7:0] $end
-   $var wire  8 E! val2[1] [7:0] $end
-   $var wire  8 F! val3[0] [7:0] $end
-   $var wire  8 G! val3[1] [7:0] $end
+   $var wire  1 `! clk $end
+   $var wire 32 Y! count [31:0] $end
+   $var wire 128 a! in[0][0] [127:0] $end
+   $var wire 128 e! in[0][1] [127:0] $end
+   $var wire 128 i! in[0][2] [127:0] $end
+   $var wire 128 m! in[1][0] [127:0] $end
+   $var wire 128 q! in[1][1] [127:0] $end
+   $var wire 128 u! in[1][2] [127:0] $end
+   $var wire  8 y! out[0][0] [7:0] $end
+   $var wire  8 z! out[0][1] [7:0] $end
+   $var wire  8 {! out[0][2] [7:0] $end
+   $var wire  8 |! out[1][0] [7:0] $end
+   $var wire  8 }! out[1][1] [7:0] $end
+   $var wire  8 ~! out[1][2] [7:0] $end
+   $var wire  8 I! val0[0] [7:0] $end
+   $var wire  8 J! val0[1] [7:0] $end
+   $var wire  8 K! val1[0] [7:0] $end
+   $var wire  8 L! val1[1] [7:0] $end
+   $var wire  8 M! val2[0] [7:0] $end
+   $var wire  8 N! val2[1] [7:0] $end
+   $var wire  8 O! val3[0] [7:0] $end
+   $var wire  8 P! val3[1] [7:0] $end
    $scope module i_sub0 $end
-    $var wire 32 v! P0 [31:0] $end
-    $var wire 32 w! P1 [31:0] $end
-    $var wire  8 H! out[0] [7:0] $end
-    $var wire  8 I! out[1] [7:0] $end
+    $var wire 32 !" P0 [31:0] $end
+    $var wire 32 "" P1 [31:0] $end
+    $var wire  8 Q! out[0] [7:0] $end
+    $var wire  8 R! out[1] [7:0] $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 32 v! P0 [31:0] $end
-    $var wire 32 w! P1 [31:0] $end
-    $var wire  8 J! out[0] [7:0] $end
-    $var wire  8 K! out[1] [7:0] $end
+    $var wire 32 !" P0 [31:0] $end
+    $var wire 32 "" P1 [31:0] $end
+    $var wire  8 S! out[0] [7:0] $end
+    $var wire  8 T! out[1] [7:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 32 v! P0 [31:0] $end
-    $var wire 32 w! P1 [31:0] $end
-    $var wire  8 L! out[0] [7:0] $end
-    $var wire  8 M! out[1] [7:0] $end
+    $var wire 32 !" P0 [31:0] $end
+    $var wire 32 "" P1 [31:0] $end
+    $var wire  8 U! out[0] [7:0] $end
+    $var wire  8 V! out[1] [7:0] $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire  8 N! out[0] [7:0] $end
-    $var wire  8 O! out[1] [7:0] $end
+    $var wire  8 W! out[0] [7:0] $end
+    $var wire  8 X! out[1] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 Q! i [31:0] $end
+    $var wire 32 Z! i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 R! j [31:0] $end
+     $var wire 32 [! j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire 128 S! exp [127:0] $end
+      $var wire 128 \! exp [127:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end
-  $var wire  8 y! out[0] [7:0] $end
-  $var wire  8 z! out[1] [7:0] $end
+  $var wire  8 $" out[0] [7:0] $end
+  $var wire  8 %" out[1] [7:0] $end
   $scope module sub6_9 $end
-   $var wire 32 {! P0 [31:0] $end
-   $var wire  8 y! out[0] [7:0] $end
-   $var wire  8 z! out[1] [7:0] $end
+   $var wire 32 &" P0 [31:0] $end
+   $var wire 32 '" P1 [31:0] $end
+   $var wire  8 $" out[0] [7:0] $end
+   $var wire  8 %" out[1] [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1 $end
-  $var wire  1 `" clk $end
-  $var wire  8 a" in [7:0] $end
-  $var wire  8 b" out [7:0] $end
+  $var wire  1 j" clk $end
+  $var wire  8 k" in [7:0] $end
+  $var wire  8 l" out [7:0] $end
   $scope module sub4_b $end
-   $var wire  1 `" clk $end
-   $var wire 32 8" count [31:0] $end
-   $var wire  8 }! ff [7:0] $end
-   $var wire  8 a" in [7:0] $end
-   $var wire  8 b" out [7:0] $end
-   $var wire 128 ~! sub5_in[0][0] [127:0] $end
-   $var wire 128 $" sub5_in[0][1] [127:0] $end
-   $var wire 128 (" sub5_in[0][2] [127:0] $end
-   $var wire 128 ," sub5_in[1][0] [127:0] $end
-   $var wire 128 0" sub5_in[1][1] [127:0] $end
-   $var wire 128 4" sub5_in[1][2] [127:0] $end
-   $var wire  8 T" sub5_out[0][0] [7:0] $end
-   $var wire  8 U" sub5_out[0][1] [7:0] $end
-   $var wire  8 V" sub5_out[0][2] [7:0] $end
-   $var wire  8 W" sub5_out[1][0] [7:0] $end
-   $var wire  8 X" sub5_out[1][1] [7:0] $end
-   $var wire  8 Y" sub5_out[1][2] [7:0] $end
+   $var wire 32 m" P0 [31:0] $end
+   $var real 64 n" P1 $end
+   $var real 64 p" P3 $end
+   $var wire  1 j" clk $end
+   $var wire 32 B" count [31:0] $end
+   $var wire  8 )" ff [7:0] $end
+   $var wire  8 k" in [7:0] $end
+   $var wire  8 l" out [7:0] $end
+   $var wire 128 *" sub5_in[0][0] [127:0] $end
+   $var wire 128 ." sub5_in[0][1] [127:0] $end
+   $var wire 128 2" sub5_in[0][2] [127:0] $end
+   $var wire 128 6" sub5_in[1][0] [127:0] $end
+   $var wire 128 :" sub5_in[1][1] [127:0] $end
+   $var wire 128 >" sub5_in[1][2] [127:0] $end
+   $var wire  8 ^" sub5_out[0][0] [7:0] $end
+   $var wire  8 _" sub5_out[0][1] [7:0] $end
+   $var wire  8 `" sub5_out[0][2] [7:0] $end
+   $var wire  8 a" sub5_out[1][0] [7:0] $end
+   $var wire  8 b" sub5_out[1][1] [7:0] $end
+   $var wire  8 c" sub5_out[1][2] [7:0] $end
    $scope module i_sub5 $end
-    $var wire  1 `" clk $end
-    $var wire 128 <" in[0][0] [127:0] $end
-    $var wire 128 @" in[0][1] [127:0] $end
-    $var wire 128 D" in[0][2] [127:0] $end
-    $var wire 128 H" in[1][0] [127:0] $end
-    $var wire 128 L" in[1][1] [127:0] $end
-    $var wire 128 P" in[1][2] [127:0] $end
-    $var wire  8 Z" out[0][0] [7:0] $end
-    $var wire  8 [" out[0][1] [7:0] $end
-    $var wire  8 \" out[0][2] [7:0] $end
-    $var wire  8 ]" out[1][0] [7:0] $end
-    $var wire  8 ^" out[1][1] [7:0] $end
-    $var wire  8 _" out[1][2] [7:0] $end
+    $var wire  1 j" clk $end
+    $var wire 128 F" in[0][0] [127:0] $end
+    $var wire 128 J" in[0][1] [127:0] $end
+    $var wire 128 N" in[0][2] [127:0] $end
+    $var wire 128 R" in[1][0] [127:0] $end
+    $var wire 128 V" in[1][1] [127:0] $end
+    $var wire 128 Z" in[1][2] [127:0] $end
+    $var wire  8 d" out[0][0] [7:0] $end
+    $var wire  8 e" out[0][1] [7:0] $end
+    $var wire  8 f" out[0][2] [7:0] $end
+    $var wire  8 g" out[1][0] [7:0] $end
+    $var wire  8 h" out[1][1] [7:0] $end
+    $var wire  8 i" out[1][2] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 9" i [31:0] $end
+    $var wire 32 C" i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 :" j [31:0] $end
+     $var wire 32 D" j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire  8 ;" exp [7:0] $end
+      $var wire  8 E" exp [7:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5 $end
-  $var wire  1 {" clk $end
-  $var wire 128 |" in[0][0] [127:0] $end
-  $var wire 128 "# in[0][1] [127:0] $end
-  $var wire 128 &# in[0][2] [127:0] $end
-  $var wire 128 *# in[1][0] [127:0] $end
-  $var wire 128 .# in[1][1] [127:0] $end
-  $var wire 128 2# in[1][2] [127:0] $end
-  $var wire  8 6# out[0][0] [7:0] $end
-  $var wire  8 7# out[0][1] [7:0] $end
-  $var wire  8 8# out[0][2] [7:0] $end
-  $var wire  8 9# out[1][0] [7:0] $end
-  $var wire  8 :# out[1][1] [7:0] $end
-  $var wire  8 ;# out[1][2] [7:0] $end
+  $var wire  1 ,# clk $end
+  $var wire 128 -# in[0][0] [127:0] $end
+  $var wire 128 1# in[0][1] [127:0] $end
+  $var wire 128 5# in[0][2] [127:0] $end
+  $var wire 128 9# in[1][0] [127:0] $end
+  $var wire 128 =# in[1][1] [127:0] $end
+  $var wire 128 A# in[1][2] [127:0] $end
+  $var wire  8 E# out[0][0] [7:0] $end
+  $var wire  8 F# out[0][1] [7:0] $end
+  $var wire  8 G# out[0][2] [7:0] $end
+  $var wire  8 H# out[1][0] [7:0] $end
+  $var wire  8 I# out[1][1] [7:0] $end
+  $var wire  8 J# out[1][2] [7:0] $end
   $scope module sub5 $end
-   $var wire  1 {" clk $end
-   $var wire 32 t" count [31:0] $end
-   $var wire 128 |" in[0][0] [127:0] $end
-   $var wire 128 "# in[0][1] [127:0] $end
-   $var wire 128 &# in[0][2] [127:0] $end
-   $var wire 128 *# in[1][0] [127:0] $end
-   $var wire 128 .# in[1][1] [127:0] $end
-   $var wire 128 2# in[1][2] [127:0] $end
-   $var wire  8 6# out[0][0] [7:0] $end
-   $var wire  8 7# out[0][1] [7:0] $end
-   $var wire  8 8# out[0][2] [7:0] $end
-   $var wire  8 9# out[1][0] [7:0] $end
-   $var wire  8 :# out[1][1] [7:0] $end
-   $var wire  8 ;# out[1][2] [7:0] $end
-   $var wire  8 d" val0[0] [7:0] $end
-   $var wire  8 e" val0[1] [7:0] $end
-   $var wire  8 f" val1[0] [7:0] $end
-   $var wire  8 g" val1[1] [7:0] $end
-   $var wire  8 h" val2[0] [7:0] $end
-   $var wire  8 i" val2[1] [7:0] $end
-   $var wire  8 j" val3[0] [7:0] $end
-   $var wire  8 k" val3[1] [7:0] $end
+   $var wire  1 ,# clk $end
+   $var wire 32 %# count [31:0] $end
+   $var wire 128 -# in[0][0] [127:0] $end
+   $var wire 128 1# in[0][1] [127:0] $end
+   $var wire 128 5# in[0][2] [127:0] $end
+   $var wire 128 9# in[1][0] [127:0] $end
+   $var wire 128 =# in[1][1] [127:0] $end
+   $var wire 128 A# in[1][2] [127:0] $end
+   $var wire  8 E# out[0][0] [7:0] $end
+   $var wire  8 F# out[0][1] [7:0] $end
+   $var wire  8 G# out[0][2] [7:0] $end
+   $var wire  8 H# out[1][0] [7:0] $end
+   $var wire  8 I# out[1][1] [7:0] $end
+   $var wire  8 J# out[1][2] [7:0] $end
+   $var wire  8 s" val0[0] [7:0] $end
+   $var wire  8 t" val0[1] [7:0] $end
+   $var wire  8 u" val1[0] [7:0] $end
+   $var wire  8 v" val1[1] [7:0] $end
+   $var wire  8 w" val2[0] [7:0] $end
+   $var wire  8 x" val2[1] [7:0] $end
+   $var wire  8 y" val3[0] [7:0] $end
+   $var wire  8 z" val3[1] [7:0] $end
    $scope module i_sub0 $end
-    $var wire 32 <# P0 [31:0] $end
-    $var wire 32 =# P1 [31:0] $end
-    $var wire  8 l" out[0] [7:0] $end
-    $var wire  8 m" out[1] [7:0] $end
+    $var wire 32 K# P0 [31:0] $end
+    $var wire 32 L# P1 [31:0] $end
+    $var wire  8 {" out[0] [7:0] $end
+    $var wire  8 |" out[1] [7:0] $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 32 <# P0 [31:0] $end
-    $var wire 32 =# P1 [31:0] $end
-    $var wire  8 n" out[0] [7:0] $end
-    $var wire  8 o" out[1] [7:0] $end
+    $var wire 32 K# P0 [31:0] $end
+    $var wire 32 L# P1 [31:0] $end
+    $var wire  8 }" out[0] [7:0] $end
+    $var wire  8 ~" out[1] [7:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 32 <# P0 [31:0] $end
-    $var wire 32 =# P1 [31:0] $end
-    $var wire  8 p" out[0] [7:0] $end
-    $var wire  8 q" out[1] [7:0] $end
+    $var wire 32 K# P0 [31:0] $end
+    $var wire 32 L# P1 [31:0] $end
+    $var wire  8 !# out[0] [7:0] $end
+    $var wire  8 "# out[1] [7:0] $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire  8 r" out[0] [7:0] $end
-    $var wire  8 s" out[1] [7:0] $end
+    $var wire  8 ## out[0] [7:0] $end
+    $var wire  8 $# out[1] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 u" i [31:0] $end
+    $var wire 32 &# i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 v" j [31:0] $end
+     $var wire 32 '# j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire 128 w" exp [127:0] $end
+      $var wire 128 (# exp [127:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end
-  $var wire  8 ?# out[0] [7:0] $end
-  $var wire  8 @# out[1] [7:0] $end
+  $var wire  8 N# out[0] [7:0] $end
+  $var wire  8 O# out[1] [7:0] $end
   $scope module sub6_9 $end
-   $var wire 32 A# P0 [31:0] $end
-   $var wire  8 ?# out[0] [7:0] $end
-   $var wire  8 @# out[1] [7:0] $end
+   $var wire 32 P# P0 [31:0] $end
+   $var wire 32 Q# P1 [31:0] $end
+   $var wire  8 N# out[0] [7:0] $end
+   $var wire  8 O# out[1] [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3 $end
-  $var wire  1 7& clk $end
-  $var wire  8 8& in [7:0] $end
-  $var wire  8 9& out [7:0] $end
+  $var wire  1 T& clk $end
+  $var wire  8 U& in [7:0] $end
+  $var wire  8 V& out [7:0] $end
   $scope module sub3_d $end
-   $var wire 32 =& UNPACKED_ARRAY[0] [31:0] $end
-   $var wire 32 >& UNPACKED_ARRAY[1] [31:0] $end
-   $var wire 16 ?& UNUSED [15:0] $end
-   $var wire  1 7& clk $end
-   $var wire  8 :& ff [7:0] $end
-   $var wire  8 8& in [7:0] $end
-   $var wire  8 9& out [7:0] $end
-   $var wire  8 ;& out4 [7:0] $end
-   $var wire  8 <& out4_2 [7:0] $end
+   $var wire  8 Z& P0 [7:0] $end
+   $var wire 32 [& UNPACKED_ARRAY[0] [31:0] $end
+   $var wire 32 \& UNPACKED_ARRAY[1] [31:0] $end
+   $var wire 16 ]& UNUSED [15:0] $end
+   $var wire  1 T& clk $end
+   $var wire  8 W& ff [7:0] $end
+   $var wire  8 U& in [7:0] $end
+   $var wire  8 V& out [7:0] $end
+   $var wire  8 X& out4 [7:0] $end
+   $var wire  8 Y& out4_2 [7:0] $end
    $scope module i_sub4_0 $end
-    $var wire  1 7& clk $end
-    $var wire  8 :& in [7:0] $end
-    $var wire  8 ;& out [7:0] $end
+    $var wire  1 T& clk $end
+    $var wire  8 W& in [7:0] $end
+    $var wire  8 X& out [7:0] $end
    $upscope $end
    $scope module i_sub4_1 $end
-    $var wire  1 7& clk $end
-    $var wire  8 :& in [7:0] $end
-    $var wire  8 <& out [7:0] $end
+    $var wire  1 T& clk $end
+    $var wire  8 W& in [7:0] $end
+    $var wire  8 Y& out [7:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3.sub3_d.i_sub4_0 $end
-  $var wire  1 $' clk $end
-  $var wire  8 %' in [7:0] $end
-  $var wire  8 &' out [7:0] $end
+  $var wire  1 B' clk $end
+  $var wire  8 C' in [7:0] $end
+  $var wire  8 D' out [7:0] $end
   $scope module sub4_2 $end
-   $var wire  1 $' clk $end
-   $var wire 32 Z& count [31:0] $end
-   $var wire  8 A& ff [7:0] $end
-   $var wire  8 %' in [7:0] $end
-   $var wire  8 &' out [7:0] $end
-   $var wire 128 B& sub5_in[0][0] [127:0] $end
-   $var wire 128 F& sub5_in[0][1] [127:0] $end
-   $var wire 128 J& sub5_in[0][2] [127:0] $end
-   $var wire 128 N& sub5_in[1][0] [127:0] $end
-   $var wire 128 R& sub5_in[1][1] [127:0] $end
-   $var wire 128 V& sub5_in[1][2] [127:0] $end
-   $var wire  8 v& sub5_out[0][0] [7:0] $end
-   $var wire  8 w& sub5_out[0][1] [7:0] $end
-   $var wire  8 x& sub5_out[0][2] [7:0] $end
-   $var wire  8 y& sub5_out[1][0] [7:0] $end
-   $var wire  8 z& sub5_out[1][1] [7:0] $end
-   $var wire  8 {& sub5_out[1][2] [7:0] $end
+   $var wire 32 E' P0 [31:0] $end
+   $var real 64 F' P1 $end
+   $var real 64 H' P3 $end
+   $var wire  1 B' clk $end
+   $var wire 32 x& count [31:0] $end
+   $var wire  8 _& ff [7:0] $end
+   $var wire  8 C' in [7:0] $end
+   $var wire  8 D' out [7:0] $end
+   $var wire 128 `& sub5_in[0][0] [127:0] $end
+   $var wire 128 d& sub5_in[0][1] [127:0] $end
+   $var wire 128 h& sub5_in[0][2] [127:0] $end
+   $var wire 128 l& sub5_in[1][0] [127:0] $end
+   $var wire 128 p& sub5_in[1][1] [127:0] $end
+   $var wire 128 t& sub5_in[1][2] [127:0] $end
+   $var wire  8 6' sub5_out[0][0] [7:0] $end
+   $var wire  8 7' sub5_out[0][1] [7:0] $end
+   $var wire  8 8' sub5_out[0][2] [7:0] $end
+   $var wire  8 9' sub5_out[1][0] [7:0] $end
+   $var wire  8 :' sub5_out[1][1] [7:0] $end
+   $var wire  8 ;' sub5_out[1][2] [7:0] $end
    $scope module i_sub5 $end
-    $var wire  1 $' clk $end
-    $var wire 128 ^& in[0][0] [127:0] $end
-    $var wire 128 b& in[0][1] [127:0] $end
-    $var wire 128 f& in[0][2] [127:0] $end
-    $var wire 128 j& in[1][0] [127:0] $end
-    $var wire 128 n& in[1][1] [127:0] $end
-    $var wire 128 r& in[1][2] [127:0] $end
-    $var wire  8 |& out[0][0] [7:0] $end
-    $var wire  8 }& out[0][1] [7:0] $end
-    $var wire  8 ~& out[0][2] [7:0] $end
-    $var wire  8 !' out[1][0] [7:0] $end
-    $var wire  8 "' out[1][1] [7:0] $end
-    $var wire  8 #' out[1][2] [7:0] $end
+    $var wire  1 B' clk $end
+    $var wire 128 |& in[0][0] [127:0] $end
+    $var wire 128 "' in[0][1] [127:0] $end
+    $var wire 128 &' in[0][2] [127:0] $end
+    $var wire 128 *' in[1][0] [127:0] $end
+    $var wire 128 .' in[1][1] [127:0] $end
+    $var wire 128 2' in[1][2] [127:0] $end
+    $var wire  8 <' out[0][0] [7:0] $end
+    $var wire  8 =' out[0][1] [7:0] $end
+    $var wire  8 >' out[0][2] [7:0] $end
+    $var wire  8 ?' out[1][0] [7:0] $end
+    $var wire  8 @' out[1][1] [7:0] $end
+    $var wire  8 A' out[1][2] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 [& i [31:0] $end
+    $var wire 32 y& i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 \& j [31:0] $end
+     $var wire 32 z& j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire  8 ]& exp [7:0] $end
+      $var wire  8 {& exp [7:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5 $end
-  $var wire  1 ?' clk $end
-  $var wire 128 @' in[0][0] [127:0] $end
-  $var wire 128 D' in[0][1] [127:0] $end
-  $var wire 128 H' in[0][2] [127:0] $end
-  $var wire 128 L' in[1][0] [127:0] $end
-  $var wire 128 P' in[1][1] [127:0] $end
-  $var wire 128 T' in[1][2] [127:0] $end
-  $var wire  8 X' out[0][0] [7:0] $end
-  $var wire  8 Y' out[0][1] [7:0] $end
-  $var wire  8 Z' out[0][2] [7:0] $end
-  $var wire  8 [' out[1][0] [7:0] $end
-  $var wire  8 \' out[1][1] [7:0] $end
-  $var wire  8 ]' out[1][2] [7:0] $end
+  $var wire  1 b' clk $end
+  $var wire 128 c' in[0][0] [127:0] $end
+  $var wire 128 g' in[0][1] [127:0] $end
+  $var wire 128 k' in[0][2] [127:0] $end
+  $var wire 128 o' in[1][0] [127:0] $end
+  $var wire 128 s' in[1][1] [127:0] $end
+  $var wire 128 w' in[1][2] [127:0] $end
+  $var wire  8 {' out[0][0] [7:0] $end
+  $var wire  8 |' out[0][1] [7:0] $end
+  $var wire  8 }' out[0][2] [7:0] $end
+  $var wire  8 ~' out[1][0] [7:0] $end
+  $var wire  8 !( out[1][1] [7:0] $end
+  $var wire  8 "( out[1][2] [7:0] $end
   $scope module sub5 $end
-   $var wire  1 ?' clk $end
-   $var wire 32 8' count [31:0] $end
-   $var wire 128 @' in[0][0] [127:0] $end
-   $var wire 128 D' in[0][1] [127:0] $end
-   $var wire 128 H' in[0][2] [127:0] $end
-   $var wire 128 L' in[1][0] [127:0] $end
-   $var wire 128 P' in[1][1] [127:0] $end
-   $var wire 128 T' in[1][2] [127:0] $end
-   $var wire  8 X' out[0][0] [7:0] $end
-   $var wire  8 Y' out[0][1] [7:0] $end
-   $var wire  8 Z' out[0][2] [7:0] $end
-   $var wire  8 [' out[1][0] [7:0] $end
-   $var wire  8 \' out[1][1] [7:0] $end
-   $var wire  8 ]' out[1][2] [7:0] $end
-   $var wire  8 (' val0[0] [7:0] $end
-   $var wire  8 )' val0[1] [7:0] $end
-   $var wire  8 *' val1[0] [7:0] $end
-   $var wire  8 +' val1[1] [7:0] $end
-   $var wire  8 ,' val2[0] [7:0] $end
-   $var wire  8 -' val2[1] [7:0] $end
-   $var wire  8 .' val3[0] [7:0] $end
-   $var wire  8 /' val3[1] [7:0] $end
+   $var wire  1 b' clk $end
+   $var wire 32 [' count [31:0] $end
+   $var wire 128 c' in[0][0] [127:0] $end
+   $var wire 128 g' in[0][1] [127:0] $end
+   $var wire 128 k' in[0][2] [127:0] $end
+   $var wire 128 o' in[1][0] [127:0] $end
+   $var wire 128 s' in[1][1] [127:0] $end
+   $var wire 128 w' in[1][2] [127:0] $end
+   $var wire  8 {' out[0][0] [7:0] $end
+   $var wire  8 |' out[0][1] [7:0] $end
+   $var wire  8 }' out[0][2] [7:0] $end
+   $var wire  8 ~' out[1][0] [7:0] $end
+   $var wire  8 !( out[1][1] [7:0] $end
+   $var wire  8 "( out[1][2] [7:0] $end
+   $var wire  8 K' val0[0] [7:0] $end
+   $var wire  8 L' val0[1] [7:0] $end
+   $var wire  8 M' val1[0] [7:0] $end
+   $var wire  8 N' val1[1] [7:0] $end
+   $var wire  8 O' val2[0] [7:0] $end
+   $var wire  8 P' val2[1] [7:0] $end
+   $var wire  8 Q' val3[0] [7:0] $end
+   $var wire  8 R' val3[1] [7:0] $end
    $scope module i_sub0 $end
-    $var wire 32 ^' P0 [31:0] $end
-    $var wire 32 _' P1 [31:0] $end
-    $var wire  8 0' out[0] [7:0] $end
-    $var wire  8 1' out[1] [7:0] $end
+    $var wire 32 #( P0 [31:0] $end
+    $var wire 32 $( P1 [31:0] $end
+    $var wire  8 S' out[0] [7:0] $end
+    $var wire  8 T' out[1] [7:0] $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 32 ^' P0 [31:0] $end
-    $var wire 32 _' P1 [31:0] $end
-    $var wire  8 2' out[0] [7:0] $end
-    $var wire  8 3' out[1] [7:0] $end
+    $var wire 32 #( P0 [31:0] $end
+    $var wire 32 $( P1 [31:0] $end
+    $var wire  8 U' out[0] [7:0] $end
+    $var wire  8 V' out[1] [7:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 32 ^' P0 [31:0] $end
-    $var wire 32 _' P1 [31:0] $end
-    $var wire  8 4' out[0] [7:0] $end
-    $var wire  8 5' out[1] [7:0] $end
+    $var wire 32 #( P0 [31:0] $end
+    $var wire 32 $( P1 [31:0] $end
+    $var wire  8 W' out[0] [7:0] $end
+    $var wire  8 X' out[1] [7:0] $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire  8 6' out[0] [7:0] $end
-    $var wire  8 7' out[1] [7:0] $end
+    $var wire  8 Y' out[0] [7:0] $end
+    $var wire  8 Z' out[1] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 9' i [31:0] $end
+    $var wire 32 \' i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 :' j [31:0] $end
+     $var wire 32 ]' j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire 128 ;' exp [127:0] $end
+      $var wire 128 ^' exp [127:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end
-  $var wire  8 a' out[0] [7:0] $end
-  $var wire  8 b' out[1] [7:0] $end
+  $var wire  8 &( out[0] [7:0] $end
+  $var wire  8 '( out[1] [7:0] $end
   $scope module sub6_9 $end
-   $var wire 32 c' P0 [31:0] $end
-   $var wire  8 a' out[0] [7:0] $end
-   $var wire  8 b' out[1] [7:0] $end
+   $var wire 32 (( P0 [31:0] $end
+   $var wire 32 )( P1 [31:0] $end
+   $var wire  8 &( out[0] [7:0] $end
+   $var wire  8 '( out[1] [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3.sub3_d.i_sub4_1 $end
-  $var wire  1 H( clk $end
-  $var wire  8 I( in [7:0] $end
-  $var wire  8 J( out [7:0] $end
+  $var wire  1 l( clk $end
+  $var wire  8 m( in [7:0] $end
+  $var wire  8 n( out [7:0] $end
   $scope module sub4_b $end
-   $var wire  1 H( clk $end
-   $var wire 32 ~' count [31:0] $end
-   $var wire  8 e' ff [7:0] $end
-   $var wire  8 I( in [7:0] $end
-   $var wire  8 J( out [7:0] $end
-   $var wire 128 f' sub5_in[0][0] [127:0] $end
-   $var wire 128 j' sub5_in[0][1] [127:0] $end
-   $var wire 128 n' sub5_in[0][2] [127:0] $end
-   $var wire 128 r' sub5_in[1][0] [127:0] $end
-   $var wire 128 v' sub5_in[1][1] [127:0] $end
-   $var wire 128 z' sub5_in[1][2] [127:0] $end
-   $var wire  8 <( sub5_out[0][0] [7:0] $end
-   $var wire  8 =( sub5_out[0][1] [7:0] $end
-   $var wire  8 >( sub5_out[0][2] [7:0] $end
-   $var wire  8 ?( sub5_out[1][0] [7:0] $end
-   $var wire  8 @( sub5_out[1][1] [7:0] $end
-   $var wire  8 A( sub5_out[1][2] [7:0] $end
+   $var wire 32 o( P0 [31:0] $end
+   $var real 64 p( P1 $end
+   $var real 64 r( P3 $end
+   $var wire  1 l( clk $end
+   $var wire 32 D( count [31:0] $end
+   $var wire  8 +( ff [7:0] $end
+   $var wire  8 m( in [7:0] $end
+   $var wire  8 n( out [7:0] $end
+   $var wire 128 ,( sub5_in[0][0] [127:0] $end
+   $var wire 128 0( sub5_in[0][1] [127:0] $end
+   $var wire 128 4( sub5_in[0][2] [127:0] $end
+   $var wire 128 8( sub5_in[1][0] [127:0] $end
+   $var wire 128 <( sub5_in[1][1] [127:0] $end
+   $var wire 128 @( sub5_in[1][2] [127:0] $end
+   $var wire  8 `( sub5_out[0][0] [7:0] $end
+   $var wire  8 a( sub5_out[0][1] [7:0] $end
+   $var wire  8 b( sub5_out[0][2] [7:0] $end
+   $var wire  8 c( sub5_out[1][0] [7:0] $end
+   $var wire  8 d( sub5_out[1][1] [7:0] $end
+   $var wire  8 e( sub5_out[1][2] [7:0] $end
    $scope module i_sub5 $end
-    $var wire  1 H( clk $end
-    $var wire 128 $( in[0][0] [127:0] $end
-    $var wire 128 (( in[0][1] [127:0] $end
-    $var wire 128 ,( in[0][2] [127:0] $end
-    $var wire 128 0( in[1][0] [127:0] $end
-    $var wire 128 4( in[1][1] [127:0] $end
-    $var wire 128 8( in[1][2] [127:0] $end
-    $var wire  8 B( out[0][0] [7:0] $end
-    $var wire  8 C( out[0][1] [7:0] $end
-    $var wire  8 D( out[0][2] [7:0] $end
-    $var wire  8 E( out[1][0] [7:0] $end
-    $var wire  8 F( out[1][1] [7:0] $end
-    $var wire  8 G( out[1][2] [7:0] $end
+    $var wire  1 l( clk $end
+    $var wire 128 H( in[0][0] [127:0] $end
+    $var wire 128 L( in[0][1] [127:0] $end
+    $var wire 128 P( in[0][2] [127:0] $end
+    $var wire 128 T( in[1][0] [127:0] $end
+    $var wire 128 X( in[1][1] [127:0] $end
+    $var wire 128 \( in[1][2] [127:0] $end
+    $var wire  8 f( out[0][0] [7:0] $end
+    $var wire  8 g( out[0][1] [7:0] $end
+    $var wire  8 h( out[0][2] [7:0] $end
+    $var wire  8 i( out[1][0] [7:0] $end
+    $var wire  8 j( out[1][1] [7:0] $end
+    $var wire  8 k( out[1][2] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 !( i [31:0] $end
+    $var wire 32 E( i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 "( j [31:0] $end
+     $var wire 32 F( j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire  8 #( exp [7:0] $end
+      $var wire  8 G( exp [7:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5 $end
-  $var wire  1 c( clk $end
-  $var wire 128 d( in[0][0] [127:0] $end
-  $var wire 128 h( in[0][1] [127:0] $end
-  $var wire 128 l( in[0][2] [127:0] $end
-  $var wire 128 p( in[1][0] [127:0] $end
-  $var wire 128 t( in[1][1] [127:0] $end
-  $var wire 128 x( in[1][2] [127:0] $end
-  $var wire  8 |( out[0][0] [7:0] $end
-  $var wire  8 }( out[0][1] [7:0] $end
-  $var wire  8 ~( out[0][2] [7:0] $end
-  $var wire  8 !) out[1][0] [7:0] $end
-  $var wire  8 ") out[1][1] [7:0] $end
-  $var wire  8 #) out[1][2] [7:0] $end
+  $var wire  1 .) clk $end
+  $var wire 128 /) in[0][0] [127:0] $end
+  $var wire 128 3) in[0][1] [127:0] $end
+  $var wire 128 7) in[0][2] [127:0] $end
+  $var wire 128 ;) in[1][0] [127:0] $end
+  $var wire 128 ?) in[1][1] [127:0] $end
+  $var wire 128 C) in[1][2] [127:0] $end
+  $var wire  8 G) out[0][0] [7:0] $end
+  $var wire  8 H) out[0][1] [7:0] $end
+  $var wire  8 I) out[0][2] [7:0] $end
+  $var wire  8 J) out[1][0] [7:0] $end
+  $var wire  8 K) out[1][1] [7:0] $end
+  $var wire  8 L) out[1][2] [7:0] $end
   $scope module sub5 $end
-   $var wire  1 c( clk $end
-   $var wire 32 \( count [31:0] $end
-   $var wire 128 d( in[0][0] [127:0] $end
-   $var wire 128 h( in[0][1] [127:0] $end
-   $var wire 128 l( in[0][2] [127:0] $end
-   $var wire 128 p( in[1][0] [127:0] $end
-   $var wire 128 t( in[1][1] [127:0] $end
-   $var wire 128 x( in[1][2] [127:0] $end
-   $var wire  8 |( out[0][0] [7:0] $end
-   $var wire  8 }( out[0][1] [7:0] $end
-   $var wire  8 ~( out[0][2] [7:0] $end
-   $var wire  8 !) out[1][0] [7:0] $end
-   $var wire  8 ") out[1][1] [7:0] $end
-   $var wire  8 #) out[1][2] [7:0] $end
-   $var wire  8 L( val0[0] [7:0] $end
-   $var wire  8 M( val0[1] [7:0] $end
-   $var wire  8 N( val1[0] [7:0] $end
-   $var wire  8 O( val1[1] [7:0] $end
-   $var wire  8 P( val2[0] [7:0] $end
-   $var wire  8 Q( val2[1] [7:0] $end
-   $var wire  8 R( val3[0] [7:0] $end
-   $var wire  8 S( val3[1] [7:0] $end
+   $var wire  1 .) clk $end
+   $var wire 32 ') count [31:0] $end
+   $var wire 128 /) in[0][0] [127:0] $end
+   $var wire 128 3) in[0][1] [127:0] $end
+   $var wire 128 7) in[0][2] [127:0] $end
+   $var wire 128 ;) in[1][0] [127:0] $end
+   $var wire 128 ?) in[1][1] [127:0] $end
+   $var wire 128 C) in[1][2] [127:0] $end
+   $var wire  8 G) out[0][0] [7:0] $end
+   $var wire  8 H) out[0][1] [7:0] $end
+   $var wire  8 I) out[0][2] [7:0] $end
+   $var wire  8 J) out[1][0] [7:0] $end
+   $var wire  8 K) out[1][1] [7:0] $end
+   $var wire  8 L) out[1][2] [7:0] $end
+   $var wire  8 u( val0[0] [7:0] $end
+   $var wire  8 v( val0[1] [7:0] $end
+   $var wire  8 w( val1[0] [7:0] $end
+   $var wire  8 x( val1[1] [7:0] $end
+   $var wire  8 y( val2[0] [7:0] $end
+   $var wire  8 z( val2[1] [7:0] $end
+   $var wire  8 {( val3[0] [7:0] $end
+   $var wire  8 |( val3[1] [7:0] $end
    $scope module i_sub0 $end
-    $var wire 32 $) P0 [31:0] $end
-    $var wire 32 %) P1 [31:0] $end
-    $var wire  8 T( out[0] [7:0] $end
-    $var wire  8 U( out[1] [7:0] $end
+    $var wire 32 M) P0 [31:0] $end
+    $var wire 32 N) P1 [31:0] $end
+    $var wire  8 }( out[0] [7:0] $end
+    $var wire  8 ~( out[1] [7:0] $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 32 $) P0 [31:0] $end
-    $var wire 32 %) P1 [31:0] $end
-    $var wire  8 V( out[0] [7:0] $end
-    $var wire  8 W( out[1] [7:0] $end
+    $var wire 32 M) P0 [31:0] $end
+    $var wire 32 N) P1 [31:0] $end
+    $var wire  8 !) out[0] [7:0] $end
+    $var wire  8 ") out[1] [7:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 32 $) P0 [31:0] $end
-    $var wire 32 %) P1 [31:0] $end
-    $var wire  8 X( out[0] [7:0] $end
-    $var wire  8 Y( out[1] [7:0] $end
+    $var wire 32 M) P0 [31:0] $end
+    $var wire 32 N) P1 [31:0] $end
+    $var wire  8 #) out[0] [7:0] $end
+    $var wire  8 $) out[1] [7:0] $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire  8 Z( out[0] [7:0] $end
-    $var wire  8 [( out[1] [7:0] $end
+    $var wire  8 %) out[0] [7:0] $end
+    $var wire  8 &) out[1] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 ]( i [31:0] $end
+    $var wire 32 () i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 ^( j [31:0] $end
+     $var wire 32 )) j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire 128 _( exp [127:0] $end
+      $var wire 128 *) exp [127:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end
-  $var wire  8 ') out[0] [7:0] $end
-  $var wire  8 () out[1] [7:0] $end
+  $var wire  8 P) out[0] [7:0] $end
+  $var wire  8 Q) out[1] [7:0] $end
   $scope module sub6_9 $end
-   $var wire 32 )) P0 [31:0] $end
-   $var wire  8 ') out[0] [7:0] $end
-   $var wire  8 () out[1] [7:0] $end
+   $var wire 32 R) P0 [31:0] $end
+   $var wire 32 S) P1 [31:0] $end
+   $var wire  8 P) out[0] [7:0] $end
+   $var wire  8 Q) out[1] [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2 $end
-  $var wire  1 C# clk $end
-  $var wire  8 D# in [7:0] $end
-  $var wire  8 E# out [7:0] $end
+  $var wire  1 S# clk $end
+  $var wire  8 T# in [7:0] $end
+  $var wire  8 U# out [7:0] $end
   $scope module sub3_2 $end
-   $var wire 32 I# UNPACKED_ARRAY[0] [31:0] $end
-   $var wire 32 J# UNPACKED_ARRAY[1] [31:0] $end
-   $var wire 16 K# UNUSED [15:0] $end
-   $var wire  1 C# clk $end
-   $var wire  8 F# ff [7:0] $end
-   $var wire  8 D# in [7:0] $end
-   $var wire  8 E# out [7:0] $end
-   $var wire  8 G# out4 [7:0] $end
-   $var wire  8 H# out4_2 [7:0] $end
+   $var wire  8 Y# P0 [7:0] $end
+   $var wire 32 Z# UNPACKED_ARRAY[0] [31:0] $end
+   $var wire 32 [# UNPACKED_ARRAY[1] [31:0] $end
+   $var wire 16 \# UNUSED [15:0] $end
+   $var wire  1 S# clk $end
+   $var wire  8 V# ff [7:0] $end
+   $var wire  8 T# in [7:0] $end
+   $var wire  8 U# out [7:0] $end
+   $var wire  8 W# out4 [7:0] $end
+   $var wire  8 X# out4_2 [7:0] $end
    $scope module i_sub4_0 $end
-    $var wire  1 C# clk $end
-    $var wire  8 F# in [7:0] $end
-    $var wire  8 G# out [7:0] $end
+    $var wire  1 S# clk $end
+    $var wire  8 V# in [7:0] $end
+    $var wire  8 W# out [7:0] $end
    $upscope $end
    $scope module i_sub4_1 $end
-    $var wire  1 C# clk $end
-    $var wire  8 F# in [7:0] $end
-    $var wire  8 H# out [7:0] $end
+    $var wire  1 S# clk $end
+    $var wire  8 V# in [7:0] $end
+    $var wire  8 X# out [7:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2.sub3_2.i_sub4_0 $end
-  $var wire  1 0$ clk $end
-  $var wire  8 1$ in [7:0] $end
-  $var wire  8 2$ out [7:0] $end
+  $var wire  1 A$ clk $end
+  $var wire  8 B$ in [7:0] $end
+  $var wire  8 C$ out [7:0] $end
   $scope module sub4_2 $end
-   $var wire  1 0$ clk $end
-   $var wire 32 f# count [31:0] $end
-   $var wire  8 M# ff [7:0] $end
-   $var wire  8 1$ in [7:0] $end
-   $var wire  8 2$ out [7:0] $end
-   $var wire 128 N# sub5_in[0][0] [127:0] $end
-   $var wire 128 R# sub5_in[0][1] [127:0] $end
-   $var wire 128 V# sub5_in[0][2] [127:0] $end
-   $var wire 128 Z# sub5_in[1][0] [127:0] $end
-   $var wire 128 ^# sub5_in[1][1] [127:0] $end
-   $var wire 128 b# sub5_in[1][2] [127:0] $end
-   $var wire  8 $$ sub5_out[0][0] [7:0] $end
-   $var wire  8 %$ sub5_out[0][1] [7:0] $end
-   $var wire  8 &$ sub5_out[0][2] [7:0] $end
-   $var wire  8 '$ sub5_out[1][0] [7:0] $end
-   $var wire  8 ($ sub5_out[1][1] [7:0] $end
-   $var wire  8 )$ sub5_out[1][2] [7:0] $end
+   $var wire 32 D$ P0 [31:0] $end
+   $var real 64 E$ P1 $end
+   $var real 64 G$ P3 $end
+   $var wire  1 A$ clk $end
+   $var wire 32 w# count [31:0] $end
+   $var wire  8 ^# ff [7:0] $end
+   $var wire  8 B$ in [7:0] $end
+   $var wire  8 C$ out [7:0] $end
+   $var wire 128 _# sub5_in[0][0] [127:0] $end
+   $var wire 128 c# sub5_in[0][1] [127:0] $end
+   $var wire 128 g# sub5_in[0][2] [127:0] $end
+   $var wire 128 k# sub5_in[1][0] [127:0] $end
+   $var wire 128 o# sub5_in[1][1] [127:0] $end
+   $var wire 128 s# sub5_in[1][2] [127:0] $end
+   $var wire  8 5$ sub5_out[0][0] [7:0] $end
+   $var wire  8 6$ sub5_out[0][1] [7:0] $end
+   $var wire  8 7$ sub5_out[0][2] [7:0] $end
+   $var wire  8 8$ sub5_out[1][0] [7:0] $end
+   $var wire  8 9$ sub5_out[1][1] [7:0] $end
+   $var wire  8 :$ sub5_out[1][2] [7:0] $end
    $scope module i_sub5 $end
-    $var wire  1 0$ clk $end
-    $var wire 128 j# in[0][0] [127:0] $end
-    $var wire 128 n# in[0][1] [127:0] $end
-    $var wire 128 r# in[0][2] [127:0] $end
-    $var wire 128 v# in[1][0] [127:0] $end
-    $var wire 128 z# in[1][1] [127:0] $end
-    $var wire 128 ~# in[1][2] [127:0] $end
-    $var wire  8 *$ out[0][0] [7:0] $end
-    $var wire  8 +$ out[0][1] [7:0] $end
-    $var wire  8 ,$ out[0][2] [7:0] $end
-    $var wire  8 -$ out[1][0] [7:0] $end
-    $var wire  8 .$ out[1][1] [7:0] $end
-    $var wire  8 /$ out[1][2] [7:0] $end
+    $var wire  1 A$ clk $end
+    $var wire 128 {# in[0][0] [127:0] $end
+    $var wire 128 !$ in[0][1] [127:0] $end
+    $var wire 128 %$ in[0][2] [127:0] $end
+    $var wire 128 )$ in[1][0] [127:0] $end
+    $var wire 128 -$ in[1][1] [127:0] $end
+    $var wire 128 1$ in[1][2] [127:0] $end
+    $var wire  8 ;$ out[0][0] [7:0] $end
+    $var wire  8 <$ out[0][1] [7:0] $end
+    $var wire  8 =$ out[0][2] [7:0] $end
+    $var wire  8 >$ out[1][0] [7:0] $end
+    $var wire  8 ?$ out[1][1] [7:0] $end
+    $var wire  8 @$ out[1][2] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 g# i [31:0] $end
+    $var wire 32 x# i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 h# j [31:0] $end
+     $var wire 32 y# j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire  8 i# exp [7:0] $end
+      $var wire  8 z# exp [7:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5 $end
-  $var wire  1 K$ clk $end
-  $var wire 128 L$ in[0][0] [127:0] $end
-  $var wire 128 P$ in[0][1] [127:0] $end
-  $var wire 128 T$ in[0][2] [127:0] $end
-  $var wire 128 X$ in[1][0] [127:0] $end
-  $var wire 128 \$ in[1][1] [127:0] $end
-  $var wire 128 `$ in[1][2] [127:0] $end
-  $var wire  8 d$ out[0][0] [7:0] $end
-  $var wire  8 e$ out[0][1] [7:0] $end
-  $var wire  8 f$ out[0][2] [7:0] $end
-  $var wire  8 g$ out[1][0] [7:0] $end
-  $var wire  8 h$ out[1][1] [7:0] $end
-  $var wire  8 i$ out[1][2] [7:0] $end
+  $var wire  1 a$ clk $end
+  $var wire 128 b$ in[0][0] [127:0] $end
+  $var wire 128 f$ in[0][1] [127:0] $end
+  $var wire 128 j$ in[0][2] [127:0] $end
+  $var wire 128 n$ in[1][0] [127:0] $end
+  $var wire 128 r$ in[1][1] [127:0] $end
+  $var wire 128 v$ in[1][2] [127:0] $end
+  $var wire  8 z$ out[0][0] [7:0] $end
+  $var wire  8 {$ out[0][1] [7:0] $end
+  $var wire  8 |$ out[0][2] [7:0] $end
+  $var wire  8 }$ out[1][0] [7:0] $end
+  $var wire  8 ~$ out[1][1] [7:0] $end
+  $var wire  8 !% out[1][2] [7:0] $end
   $scope module sub5 $end
-   $var wire  1 K$ clk $end
-   $var wire 32 D$ count [31:0] $end
-   $var wire 128 L$ in[0][0] [127:0] $end
-   $var wire 128 P$ in[0][1] [127:0] $end
-   $var wire 128 T$ in[0][2] [127:0] $end
-   $var wire 128 X$ in[1][0] [127:0] $end
-   $var wire 128 \$ in[1][1] [127:0] $end
-   $var wire 128 `$ in[1][2] [127:0] $end
-   $var wire  8 d$ out[0][0] [7:0] $end
-   $var wire  8 e$ out[0][1] [7:0] $end
-   $var wire  8 f$ out[0][2] [7:0] $end
-   $var wire  8 g$ out[1][0] [7:0] $end
-   $var wire  8 h$ out[1][1] [7:0] $end
-   $var wire  8 i$ out[1][2] [7:0] $end
-   $var wire  8 4$ val0[0] [7:0] $end
-   $var wire  8 5$ val0[1] [7:0] $end
-   $var wire  8 6$ val1[0] [7:0] $end
-   $var wire  8 7$ val1[1] [7:0] $end
-   $var wire  8 8$ val2[0] [7:0] $end
-   $var wire  8 9$ val2[1] [7:0] $end
-   $var wire  8 :$ val3[0] [7:0] $end
-   $var wire  8 ;$ val3[1] [7:0] $end
+   $var wire  1 a$ clk $end
+   $var wire 32 Z$ count [31:0] $end
+   $var wire 128 b$ in[0][0] [127:0] $end
+   $var wire 128 f$ in[0][1] [127:0] $end
+   $var wire 128 j$ in[0][2] [127:0] $end
+   $var wire 128 n$ in[1][0] [127:0] $end
+   $var wire 128 r$ in[1][1] [127:0] $end
+   $var wire 128 v$ in[1][2] [127:0] $end
+   $var wire  8 z$ out[0][0] [7:0] $end
+   $var wire  8 {$ out[0][1] [7:0] $end
+   $var wire  8 |$ out[0][2] [7:0] $end
+   $var wire  8 }$ out[1][0] [7:0] $end
+   $var wire  8 ~$ out[1][1] [7:0] $end
+   $var wire  8 !% out[1][2] [7:0] $end
+   $var wire  8 J$ val0[0] [7:0] $end
+   $var wire  8 K$ val0[1] [7:0] $end
+   $var wire  8 L$ val1[0] [7:0] $end
+   $var wire  8 M$ val1[1] [7:0] $end
+   $var wire  8 N$ val2[0] [7:0] $end
+   $var wire  8 O$ val2[1] [7:0] $end
+   $var wire  8 P$ val3[0] [7:0] $end
+   $var wire  8 Q$ val3[1] [7:0] $end
    $scope module i_sub0 $end
-    $var wire 32 j$ P0 [31:0] $end
-    $var wire 32 k$ P1 [31:0] $end
-    $var wire  8 <$ out[0] [7:0] $end
-    $var wire  8 =$ out[1] [7:0] $end
+    $var wire 32 "% P0 [31:0] $end
+    $var wire 32 #% P1 [31:0] $end
+    $var wire  8 R$ out[0] [7:0] $end
+    $var wire  8 S$ out[1] [7:0] $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 32 j$ P0 [31:0] $end
-    $var wire 32 k$ P1 [31:0] $end
-    $var wire  8 >$ out[0] [7:0] $end
-    $var wire  8 ?$ out[1] [7:0] $end
+    $var wire 32 "% P0 [31:0] $end
+    $var wire 32 #% P1 [31:0] $end
+    $var wire  8 T$ out[0] [7:0] $end
+    $var wire  8 U$ out[1] [7:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 32 j$ P0 [31:0] $end
-    $var wire 32 k$ P1 [31:0] $end
-    $var wire  8 @$ out[0] [7:0] $end
-    $var wire  8 A$ out[1] [7:0] $end
+    $var wire 32 "% P0 [31:0] $end
+    $var wire 32 #% P1 [31:0] $end
+    $var wire  8 V$ out[0] [7:0] $end
+    $var wire  8 W$ out[1] [7:0] $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire  8 B$ out[0] [7:0] $end
-    $var wire  8 C$ out[1] [7:0] $end
+    $var wire  8 X$ out[0] [7:0] $end
+    $var wire  8 Y$ out[1] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 E$ i [31:0] $end
+    $var wire 32 [$ i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 F$ j [31:0] $end
+     $var wire 32 \$ j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire 128 G$ exp [127:0] $end
+      $var wire 128 ]$ exp [127:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end
-  $var wire  8 m$ out[0] [7:0] $end
-  $var wire  8 n$ out[1] [7:0] $end
+  $var wire  8 %% out[0] [7:0] $end
+  $var wire  8 &% out[1] [7:0] $end
   $scope module sub6_9 $end
-   $var wire 32 o$ P0 [31:0] $end
-   $var wire  8 m$ out[0] [7:0] $end
-   $var wire  8 n$ out[1] [7:0] $end
+   $var wire 32 '% P0 [31:0] $end
+   $var wire 32 (% P1 [31:0] $end
+   $var wire  8 %% out[0] [7:0] $end
+   $var wire  8 &% out[1] [7:0] $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2.sub3_2.i_sub4_1 $end
-  $var wire  1 T% clk $end
-  $var wire  8 U% in [7:0] $end
-  $var wire  8 V% out [7:0] $end
+  $var wire  1 k% clk $end
+  $var wire  8 l% in [7:0] $end
+  $var wire  8 m% out [7:0] $end
   $scope module sub4_b $end
-   $var wire  1 T% clk $end
-   $var wire 32 ,% count [31:0] $end
-   $var wire  8 q$ ff [7:0] $end
-   $var wire  8 U% in [7:0] $end
-   $var wire  8 V% out [7:0] $end
-   $var wire 128 r$ sub5_in[0][0] [127:0] $end
-   $var wire 128 v$ sub5_in[0][1] [127:0] $end
-   $var wire 128 z$ sub5_in[0][2] [127:0] $end
-   $var wire 128 ~$ sub5_in[1][0] [127:0] $end
-   $var wire 128 $% sub5_in[1][1] [127:0] $end
-   $var wire 128 (% sub5_in[1][2] [127:0] $end
-   $var wire  8 H% sub5_out[0][0] [7:0] $end
-   $var wire  8 I% sub5_out[0][1] [7:0] $end
-   $var wire  8 J% sub5_out[0][2] [7:0] $end
-   $var wire  8 K% sub5_out[1][0] [7:0] $end
-   $var wire  8 L% sub5_out[1][1] [7:0] $end
-   $var wire  8 M% sub5_out[1][2] [7:0] $end
+   $var wire 32 n% P0 [31:0] $end
+   $var real 64 o% P1 $end
+   $var real 64 q% P3 $end
+   $var wire  1 k% clk $end
+   $var wire 32 C% count [31:0] $end
+   $var wire  8 *% ff [7:0] $end
+   $var wire  8 l% in [7:0] $end
+   $var wire  8 m% out [7:0] $end
+   $var wire 128 +% sub5_in[0][0] [127:0] $end
+   $var wire 128 /% sub5_in[0][1] [127:0] $end
+   $var wire 128 3% sub5_in[0][2] [127:0] $end
+   $var wire 128 7% sub5_in[1][0] [127:0] $end
+   $var wire 128 ;% sub5_in[1][1] [127:0] $end
+   $var wire 128 ?% sub5_in[1][2] [127:0] $end
+   $var wire  8 _% sub5_out[0][0] [7:0] $end
+   $var wire  8 `% sub5_out[0][1] [7:0] $end
+   $var wire  8 a% sub5_out[0][2] [7:0] $end
+   $var wire  8 b% sub5_out[1][0] [7:0] $end
+   $var wire  8 c% sub5_out[1][1] [7:0] $end
+   $var wire  8 d% sub5_out[1][2] [7:0] $end
    $scope module i_sub5 $end
-    $var wire  1 T% clk $end
-    $var wire 128 0% in[0][0] [127:0] $end
-    $var wire 128 4% in[0][1] [127:0] $end
-    $var wire 128 8% in[0][2] [127:0] $end
-    $var wire 128 <% in[1][0] [127:0] $end
-    $var wire 128 @% in[1][1] [127:0] $end
-    $var wire 128 D% in[1][2] [127:0] $end
-    $var wire  8 N% out[0][0] [7:0] $end
-    $var wire  8 O% out[0][1] [7:0] $end
-    $var wire  8 P% out[0][2] [7:0] $end
-    $var wire  8 Q% out[1][0] [7:0] $end
-    $var wire  8 R% out[1][1] [7:0] $end
-    $var wire  8 S% out[1][2] [7:0] $end
+    $var wire  1 k% clk $end
+    $var wire 128 G% in[0][0] [127:0] $end
+    $var wire 128 K% in[0][1] [127:0] $end
+    $var wire 128 O% in[0][2] [127:0] $end
+    $var wire 128 S% in[1][0] [127:0] $end
+    $var wire 128 W% in[1][1] [127:0] $end
+    $var wire 128 [% in[1][2] [127:0] $end
+    $var wire  8 e% out[0][0] [7:0] $end
+    $var wire  8 f% out[0][1] [7:0] $end
+    $var wire  8 g% out[0][2] [7:0] $end
+    $var wire  8 h% out[1][0] [7:0] $end
+    $var wire  8 i% out[1][1] [7:0] $end
+    $var wire  8 j% out[1][2] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 -% i [31:0] $end
+    $var wire 32 D% i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 .% j [31:0] $end
+     $var wire 32 E% j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire  8 /% exp [7:0] $end
+      $var wire  8 F% exp [7:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5 $end
-  $var wire  1 o% clk $end
-  $var wire 128 p% in[0][0] [127:0] $end
-  $var wire 128 t% in[0][1] [127:0] $end
-  $var wire 128 x% in[0][2] [127:0] $end
-  $var wire 128 |% in[1][0] [127:0] $end
-  $var wire 128 "& in[1][1] [127:0] $end
-  $var wire 128 && in[1][2] [127:0] $end
-  $var wire  8 *& out[0][0] [7:0] $end
-  $var wire  8 +& out[0][1] [7:0] $end
-  $var wire  8 ,& out[0][2] [7:0] $end
-  $var wire  8 -& out[1][0] [7:0] $end
-  $var wire  8 .& out[1][1] [7:0] $end
-  $var wire  8 /& out[1][2] [7:0] $end
+  $var wire  1 -& clk $end
+  $var wire 128 .& in[0][0] [127:0] $end
+  $var wire 128 2& in[0][1] [127:0] $end
+  $var wire 128 6& in[0][2] [127:0] $end
+  $var wire 128 :& in[1][0] [127:0] $end
+  $var wire 128 >& in[1][1] [127:0] $end
+  $var wire 128 B& in[1][2] [127:0] $end
+  $var wire  8 F& out[0][0] [7:0] $end
+  $var wire  8 G& out[0][1] [7:0] $end
+  $var wire  8 H& out[0][2] [7:0] $end
+  $var wire  8 I& out[1][0] [7:0] $end
+  $var wire  8 J& out[1][1] [7:0] $end
+  $var wire  8 K& out[1][2] [7:0] $end
   $scope module sub5 $end
-   $var wire  1 o% clk $end
-   $var wire 32 h% count [31:0] $end
-   $var wire 128 p% in[0][0] [127:0] $end
-   $var wire 128 t% in[0][1] [127:0] $end
-   $var wire 128 x% in[0][2] [127:0] $end
-   $var wire 128 |% in[1][0] [127:0] $end
-   $var wire 128 "& in[1][1] [127:0] $end
-   $var wire 128 && in[1][2] [127:0] $end
-   $var wire  8 *& out[0][0] [7:0] $end
-   $var wire  8 +& out[0][1] [7:0] $end
-   $var wire  8 ,& out[0][2] [7:0] $end
-   $var wire  8 -& out[1][0] [7:0] $end
-   $var wire  8 .& out[1][1] [7:0] $end
-   $var wire  8 /& out[1][2] [7:0] $end
-   $var wire  8 X% val0[0] [7:0] $end
-   $var wire  8 Y% val0[1] [7:0] $end
-   $var wire  8 Z% val1[0] [7:0] $end
-   $var wire  8 [% val1[1] [7:0] $end
-   $var wire  8 \% val2[0] [7:0] $end
-   $var wire  8 ]% val2[1] [7:0] $end
-   $var wire  8 ^% val3[0] [7:0] $end
-   $var wire  8 _% val3[1] [7:0] $end
+   $var wire  1 -& clk $end
+   $var wire 32 && count [31:0] $end
+   $var wire 128 .& in[0][0] [127:0] $end
+   $var wire 128 2& in[0][1] [127:0] $end
+   $var wire 128 6& in[0][2] [127:0] $end
+   $var wire 128 :& in[1][0] [127:0] $end
+   $var wire 128 >& in[1][1] [127:0] $end
+   $var wire 128 B& in[1][2] [127:0] $end
+   $var wire  8 F& out[0][0] [7:0] $end
+   $var wire  8 G& out[0][1] [7:0] $end
+   $var wire  8 H& out[0][2] [7:0] $end
+   $var wire  8 I& out[1][0] [7:0] $end
+   $var wire  8 J& out[1][1] [7:0] $end
+   $var wire  8 K& out[1][2] [7:0] $end
+   $var wire  8 t% val0[0] [7:0] $end
+   $var wire  8 u% val0[1] [7:0] $end
+   $var wire  8 v% val1[0] [7:0] $end
+   $var wire  8 w% val1[1] [7:0] $end
+   $var wire  8 x% val2[0] [7:0] $end
+   $var wire  8 y% val2[1] [7:0] $end
+   $var wire  8 z% val3[0] [7:0] $end
+   $var wire  8 {% val3[1] [7:0] $end
    $scope module i_sub0 $end
-    $var wire 32 0& P0 [31:0] $end
-    $var wire 32 1& P1 [31:0] $end
-    $var wire  8 `% out[0] [7:0] $end
-    $var wire  8 a% out[1] [7:0] $end
+    $var wire 32 L& P0 [31:0] $end
+    $var wire 32 M& P1 [31:0] $end
+    $var wire  8 |% out[0] [7:0] $end
+    $var wire  8 }% out[1] [7:0] $end
    $upscope $end
    $scope module i_sub1 $end
-    $var wire 32 0& P0 [31:0] $end
-    $var wire 32 1& P1 [31:0] $end
-    $var wire  8 b% out[0] [7:0] $end
-    $var wire  8 c% out[1] [7:0] $end
+    $var wire 32 L& P0 [31:0] $end
+    $var wire 32 M& P1 [31:0] $end
+    $var wire  8 ~% out[0] [7:0] $end
+    $var wire  8 !& out[1] [7:0] $end
    $upscope $end
    $scope module i_sub2 $end
-    $var wire 32 0& P0 [31:0] $end
-    $var wire 32 1& P1 [31:0] $end
-    $var wire  8 d% out[0] [7:0] $end
-    $var wire  8 e% out[1] [7:0] $end
+    $var wire 32 L& P0 [31:0] $end
+    $var wire 32 M& P1 [31:0] $end
+    $var wire  8 "& out[0] [7:0] $end
+    $var wire  8 #& out[1] [7:0] $end
    $upscope $end
    $scope module i_sub3 $end
-    $var wire  8 f% out[0] [7:0] $end
-    $var wire  8 g% out[1] [7:0] $end
+    $var wire  8 $& out[0] [7:0] $end
+    $var wire  8 %& out[1] [7:0] $end
    $upscope $end
    $scope module unnamedblk1 $end
-    $var wire 32 i% i [31:0] $end
+    $var wire 32 '& i [31:0] $end
     $scope module unnamedblk2 $end
-     $var wire 32 j% j [31:0] $end
+     $var wire 32 (& j [31:0] $end
      $scope module unnamedblk3 $end
-      $var wire 128 k% exp [127:0] $end
+      $var wire 128 )& exp [127:0] $end
      $upscope $end
     $upscope $end
    $upscope $end
   $upscope $end
  $upscope $end
  $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end
-  $var wire  8 3& out[0] [7:0] $end
-  $var wire  8 4& out[1] [7:0] $end
+  $var wire  8 O& out[0] [7:0] $end
+  $var wire  8 P& out[1] [7:0] $end
   $scope module sub6_9 $end
-   $var wire 32 5& P0 [31:0] $end
-   $var wire  8 3& out[0] [7:0] $end
-   $var wire  8 4& out[1] [7:0] $end
+   $var wire 32 Q& P0 [31:0] $end
+   $var wire 32 R& P1 [31:0] $end
+   $var wire  8 O& out[0] [7:0] $end
+   $var wire  8 P& out[1] [7:0] $end
   $upscope $end
  $upscope $end
 $enddefinitions $end
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diff --git a/test_regress/t/t_trace_param_override.out b/test_regress/t/t_trace_param_override.out
new file mode 100644
index 000000000..92ff7f265
--- /dev/null
+++ b/test_regress/t/t_trace_param_override.out
@@ -0,0 +1,16 @@
+$version Generated by VerilatedVcd $end
+$date Thu Nov 10 19:19:51 2022 $end
+$timescale 1ps $end
+
+ $scope module TOP $end
+  $scope module t $end
+   $var wire 32 $ PORIG [31:0] $end
+   $var wire 32 # POVERRODE [31:0] $end
+  $upscope $end
+ $upscope $end
+$enddefinitions $end
+
+
+#0
+b00000000000000000000000000011111 #
+b00000000000000000000000000010000 $
diff --git a/test_regress/t/t_trace_param_override.pl b/test_regress/t/t_trace_param_override.pl
new file mode 100755
index 000000000..4e2cf6e81
--- /dev/null
+++ b/test_regress/t/t_trace_param_override.pl
@@ -0,0 +1,25 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--exe --main --trace -GPOVERRODE=31"],
+    make_main => 0,
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+vcd_identical($Self->trace_filename, $Self->{golden_filename});
+
+ok(1);
+1;
diff --git a/test_regress/t/t_trace_param_override.v b/test_regress/t/t_trace_param_override.v
new file mode 100644
index 000000000..072e94e33
--- /dev/null
+++ b/test_regress/t/t_trace_param_override.v
@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define STRINGIFY(x) `"x`"
+
+module t #(
+           parameter int POVERRODE = 16,
+           parameter int PORIG = 16
+           ) (/*AUTOARG*/);
+
+   initial begin
+      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+      $dumpvars;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

From fbf2e59c85eac65cbd4460898dd878e5c20f2cec Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 10 Nov 2022 20:49:11 -0500
Subject: [PATCH 019/156] Fix loss of V3Simulate on expression statements.

---
 src/V3Simulate.h                        | 6 ++++++
 test_regress/t/t_assert_disable_bad.out | 4 +++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/V3Simulate.h b/src/V3Simulate.h
index 7c70e4ba1..02c8344d0 100644
--- a/src/V3Simulate.h
+++ b/src/V3Simulate.h
@@ -863,6 +863,12 @@ private:
 
     void visit(AstComment*) override {}
 
+    void visit(AstStmtExpr* nodep) override {
+        if (jumpingOver(nodep)) return;
+        checkNodeInfo(nodep);
+        iterateChildren(nodep);
+    }
+
     void visit(AstJumpBlock* nodep) override {
         if (jumpingOver(nodep)) return;
         iterateChildren(nodep);
diff --git a/test_regress/t/t_assert_disable_bad.out b/test_regress/t/t_assert_disable_bad.out
index a53fbe9d1..820b9b72d 100644
--- a/test_regress/t/t_assert_disable_bad.out
+++ b/test_regress/t/t_assert_disable_bad.out
@@ -2,4 +2,6 @@
                                       : ... In instance t
    27 |    assert property (disable iff (val == 0) check(1, 1));
       |                                      ^~
-%Error: Exiting due to
+%Error: Internal Error: t/t_assert_disable_bad.v:21:7: ../V3Ast.cpp:#: Adding to non-empty, non-list op2
+   21 |       @(posedge clk)
+      |       ^

From 528a73a492b2a9bd11c978d5f638375531068a02 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 10 Nov 2022 22:09:24 -0500
Subject: [PATCH 020/156] Fix instability after disable iff error.

---
 src/V3AssertPre.cpp                     | 1 +
 test_regress/t/t_assert_disable_bad.out | 4 +---
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp
index 528efcd96..0cd4a9a00 100644
--- a/src/V3AssertPre.cpp
+++ b/src/V3AssertPre.cpp
@@ -109,6 +109,7 @@ private:
                 if (nodep->disablep() && propExprp->disablep()) {
                     nodep->v3error("disable iff expression before property call and in its "
                                    "body is not legal");
+                    pushDeletep(propExprp->disablep()->unlinkFrBack());
                 }
                 // If disable iff is in outer property, move it to inner
                 if (nodep->disablep()) {
diff --git a/test_regress/t/t_assert_disable_bad.out b/test_regress/t/t_assert_disable_bad.out
index 820b9b72d..a53fbe9d1 100644
--- a/test_regress/t/t_assert_disable_bad.out
+++ b/test_regress/t/t_assert_disable_bad.out
@@ -2,6 +2,4 @@
                                       : ... In instance t
    27 |    assert property (disable iff (val == 0) check(1, 1));
       |                                      ^~
-%Error: Internal Error: t/t_assert_disable_bad.v:21:7: ../V3Ast.cpp:#: Adding to non-empty, non-list op2
-   21 |       @(posedge clk)
-      |       ^
+%Error: Exiting due to

From 0c75d4eaca8b38c2592c7ba76a5fb9658d584435 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 10 Nov 2022 22:58:27 -0500
Subject: [PATCH 021/156] Internals: Fix constructor style.

---
 src/V3Graph.h       |  5 +++--
 src/V3ParseImp.h    |  2 +-
 src/V3Slice.cpp     | 16 ++++++++--------
 src/V3SymTable.h    |  6 +++---
 src/V3WidthCommit.h |  4 ++--
 5 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/src/V3Graph.h b/src/V3Graph.h
index 0de50222a..ee7f7a2ef 100644
--- a/src/V3Graph.h
+++ b/src/V3Graph.h
@@ -203,7 +203,7 @@ public:
     explicit V3GraphVertex(V3Graph* graphp);
     //! Clone copy constructor. Doesn't copy edges or user/userp.
     virtual V3GraphVertex* clone(V3Graph* graphp) const {
-        return new V3GraphVertex(graphp, *this);
+        return new V3GraphVertex{graphp, *this};
     }
     virtual ~V3GraphVertex() = default;
     void unlinkEdges(V3Graph* graphp);
@@ -271,6 +271,7 @@ protected:
     friend class V3GraphVertex;
     friend class GraphAcyc;
     friend class GraphAcycEdge;
+
     V3ListEnt<V3GraphEdge*> m_outs;  // Next Outbound edge for same vertex (linked list)
     V3ListEnt<V3GraphEdge*> m_ins;  // Next Inbound edge for same vertex (linked list)
     //
@@ -303,7 +304,7 @@ public:
     }
     //! Clone copy constructor.  Doesn't copy existing vertices or user/userp.
     virtual V3GraphEdge* clone(V3Graph* graphp, V3GraphVertex* fromp, V3GraphVertex* top) const {
-        return new V3GraphEdge(graphp, fromp, top, *this);
+        return new V3GraphEdge{graphp, fromp, top, *this};
     }
     virtual ~V3GraphEdge() = default;
     // METHODS
diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h
index 9e3303923..fb89516ad 100644
--- a/src/V3ParseImp.h
+++ b/src/V3ParseImp.h
@@ -233,7 +233,7 @@ public:
         return strp;
     }
     V3Number* newNumber(FileLine* flp, const char* text) {
-        V3Number* nump = new V3Number(flp, text);
+        V3Number* nump = new V3Number{flp, text};
         m_numberps.push_back(nump);
         return nump;
     }
diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp
index 57cca7785..332612d87 100644
--- a/src/V3Slice.cpp
+++ b/src/V3Slice.cpp
@@ -109,14 +109,14 @@ class SliceVisitor final : public VNVisitor {
                                   + (!snodep->declRange().littleEndian()
                                          ? snodep->declRange().elements() - 1 - offset
                                          : offset));
-            newp = new AstArraySel(nodep->fileline(), snodep->fromp()->cloneTree(false), leOffset);
+            newp = new AstArraySel{nodep->fileline(), snodep->fromp()->cloneTree(false), leOffset};
         } else if (VN_IS(nodep, ArraySel) || VN_IS(nodep, NodeVarRef) || VN_IS(nodep, NodeSel)
                    || VN_IS(nodep, CMethodHard) || VN_IS(nodep, MemberSel)) {
             UINFO(9, "  cloneSel(" << elements << "," << offset << ") " << nodep << endl);
             const int leOffset = !arrayp->rangep()->littleEndian()
                                      ? arrayp->rangep()->elementsConst() - 1 - offset
                                      : offset;
-            newp = new AstArraySel(nodep->fileline(), nodep->cloneTree(false), leOffset);
+            newp = new AstArraySel{nodep->fileline(), nodep->cloneTree(false), leOffset};
         } else {
             if (!m_assignError) {
                 nodep->v3error(nodep->prettyTypeName()
@@ -189,10 +189,10 @@ class SliceVisitor final : public VNVisitor {
                         // EQ(a,b) -> LOGAND(EQ(ARRAYSEL(a,0), ARRAYSEL(b,0)), ...[1])
                         AstNodeBiop* const clonep
                             = VN_AS(nodep->cloneType(
-                                        new AstArraySel(nodep->fileline(),
-                                                        nodep->lhsp()->cloneTree(false), index),
-                                        new AstArraySel(nodep->fileline(),
-                                                        nodep->rhsp()->cloneTree(false), index)),
+                                        new AstArraySel{nodep->fileline(),
+                                                        nodep->lhsp()->cloneTree(false), index},
+                                        new AstArraySel{nodep->fileline(),
+                                                        nodep->rhsp()->cloneTree(false), index}),
                                     NodeBiop);
                         if (!logp) {
                             logp = clonep;
@@ -200,11 +200,11 @@ class SliceVisitor final : public VNVisitor {
                             switch (nodep->type()) {
                             case VNType::atEq:  // FALLTHRU
                             case VNType::atEqCase:
-                                logp = new AstLogAnd(nodep->fileline(), logp, clonep);
+                                logp = new AstLogAnd{nodep->fileline(), logp, clonep};
                                 break;
                             case VNType::atNeq:  // FALLTHRU
                             case VNType::atNeqCase:
-                                logp = new AstLogOr(nodep->fileline(), logp, clonep);
+                                logp = new AstLogOr{nodep->fileline(), logp, clonep};
                                 break;
                             default:
                                 nodep->v3fatalSrc("Unknown node type processing array slice");
diff --git a/src/V3SymTable.h b/src/V3SymTable.h
index 879c898e9..714574096 100644
--- a/src/V3SymTable.h
+++ b/src/V3SymTable.h
@@ -183,7 +183,7 @@ private:
                          bool honorExport) {
         if ((!honorExport || srcp->exported())
             && !findIdFlat(name)) {  // Don't insert over existing entry
-            VSymEnt* const symp = new VSymEnt(graphp, srcp);
+            VSymEnt* const symp = new VSymEnt{graphp, srcp};
             symp->exported(false);  // Can't reimport an import without an export
             symp->imported(true);
             reinsert(name, symp);
@@ -248,7 +248,7 @@ public:
             VSymEnt* const subSrcp = it->second;
             const AstVar* const varp = VN_CAST(subSrcp->nodep(), Var);
             if (!onlyUnmodportable || (varp && varp->isParam())) {
-                VSymEnt* const subSymp = new VSymEnt(graphp, subSrcp);
+                VSymEnt* const subSymp = new VSymEnt{graphp, subSrcp};
                 reinsert(name, subSymp);
                 // And recurse to create children
                 subSymp->importFromIface(graphp, subSrcp);
@@ -290,7 +290,7 @@ class VSymGraph final {
     VL_DEFINE_DEBUG_FUNCTIONS;
 
 public:
-    explicit VSymGraph(AstNetlist* nodep) { m_symRootp = new VSymEnt(this, nodep); }
+    explicit VSymGraph(AstNetlist* nodep) { m_symRootp = new VSymEnt{this, nodep}; }
     ~VSymGraph() {
         for (const VSymEnt* entp : m_symsp) delete entp;
     }
diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h
index ca2f9a584..5dc6283e2 100644
--- a/src/V3WidthCommit.h
+++ b/src/V3WidthCommit.h
@@ -80,10 +80,10 @@ public:
     static AstConst* newIfConstCommitSize(AstConst* nodep) {
         if (((nodep->dtypep()->width() != nodep->num().width()) || !nodep->num().sized())
             && !nodep->num().isString()) {  // Need to force the number from unsized to sized
-            V3Number num(nodep, nodep->dtypep()->width());
+            V3Number num{nodep, nodep->dtypep()->width()};
             num.opAssign(nodep->num());
             num.isSigned(nodep->isSigned());
-            AstConst* const newp = new AstConst(nodep->fileline(), num);
+            AstConst* const newp = new AstConst{nodep->fileline(), num};
             newp->dtypeFrom(nodep);
             return newp;
         } else {

From 9d7c4d9af3db39f4a2df7a0b0c5d09fedd277eac Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 11 Nov 2022 17:18:59 -0500
Subject: [PATCH 022/156] Fix wait 0.

---
 Changes                            |  1 +
 src/V3Timing.cpp                   |  4 ++-
 test_regress/t/t_lint_wait_bad.out | 17 +++++----
 test_regress/t/t_timing_wait.v     | 57 ++++++++++++++++--------------
 4 files changed, 44 insertions(+), 35 deletions(-)

diff --git a/Changes b/Changes
index d54ef90b1..c12d111f4 100644
--- a/Changes
+++ b/Changes
@@ -19,6 +19,7 @@ Verilator 5.003 devel
 * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
 * Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
 * Fix tracing parameters overridden with -G (#3723). [Iztok Jeras]
+* Fix wait 0.
 
 
 Verilator 5.002 2022-10-29
diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp
index 85549de04..30eb3d410 100644
--- a/src/V3Timing.cpp
+++ b/src/V3Timing.cpp
@@ -709,11 +709,13 @@ private:
                 awaitp->dtypeSetVoid();
                 nodep->replaceWith(awaitp->makeStmt());
                 if (stmtsp) VL_DO_DANGLING(stmtsp->deleteTree(), stmtsp);
+                VL_DO_DANGLING(condp->deleteTree(), condp);
             } else if (stmtsp) {
                 // Just put the statements there
                 nodep->replaceWith(stmtsp);
+            } else {
+                nodep->unlinkFrBack();
             }
-            VL_DO_DANGLING(condp->deleteTree(), condp);
         } else if (needDynamicTrigger(condp)) {
             // No point in making a sentree, just use the expression as sensitivity
             // Put the event control in an if so we only wait if the condition isn't met already
diff --git a/test_regress/t/t_lint_wait_bad.out b/test_regress/t/t_lint_wait_bad.out
index 5ceecf26d..3b06a1c50 100644
--- a/test_regress/t/t_lint_wait_bad.out
+++ b/test_regress/t/t_lint_wait_bad.out
@@ -1,12 +1,15 @@
-%Warning-WAITCONST: t/t_timing_wait.v:47:13: Wait statement condition is constant
-   47 |      wait(0 < 1) $write("*-* All Finished *-*\n");
-      |             ^
+%Warning-WAITCONST: t/t_timing_wait.v:48:12: Wait statement condition is constant
+   48 |       wait(1);
+      |            ^
                     ... For warning description see https://verilator.org/warn/WAITCONST?v=latest
                     ... Use "/* verilator lint_off WAITCONST */" and lint_on around source to disable this message.
-%Warning-WAITCONST: t/t_timing_wait.v:51:17: Wait statement condition is constant
-   51 |    initial wait(0) $stop;
+%Warning-WAITCONST: t/t_timing_wait.v:50:14: Wait statement condition is constant
+   50 |       wait(0 < 1) $write("*-* All Finished *-*\n");
+      |              ^
+%Warning-WAITCONST: t/t_timing_wait.v:54:17: Wait statement condition is constant
+   54 |    initial wait(0) $stop;
       |                 ^
-%Warning-WAITCONST: t/t_timing_wait.v:52:19: Wait statement condition is constant
-   52 |    initial wait(1 == 0) $stop;
+%Warning-WAITCONST: t/t_timing_wait.v:55:19: Wait statement condition is constant
+   55 |    initial wait(1 == 0) $stop;
       |                   ^~
 %Error: Exiting due to
diff --git a/test_regress/t/t_timing_wait.v b/test_regress/t/t_timing_wait.v
index abfda1c09..bcf33dcb1 100644
--- a/test_regress/t/t_timing_wait.v
+++ b/test_regress/t/t_timing_wait.v
@@ -16,36 +16,39 @@ module t;
    int c = 0;
 
    initial begin
-     `WRITE_VERBOSE("start with a==0, b==0, c==0\n");
-     #2 a = 1; `WRITE_VERBOSE("assign 1 to a\n");
-     #1 a = 2; `WRITE_VERBOSE("assign 2 to a\n");  // a==2
-     #1 a = 0; `WRITE_VERBOSE("assign 0 to a\n");
-     #1 a = 2; `WRITE_VERBOSE("assign 2 to a\n");  // 1<a<3
-     #1 b = 2; `WRITE_VERBOSE("assign 2 to b\n");
-     #1 a = 1; `WRITE_VERBOSE("assign 1 to a\n");  // b>a
-     #1 c = 3; `WRITE_VERBOSE("assign 3 to c\n");
-     #1 c = 4; `WRITE_VERBOSE("assign 4 to c\n");  // a+b<c
-     #1 c = 4; `WRITE_VERBOSE("assign 5 to b\n");  // a<b && b>c
-     b = 5;
+      `WRITE_VERBOSE("start with a==0, b==0, c==0\n");
+      #2 a = 1; `WRITE_VERBOSE("assign 1 to a\n");
+      #1 a = 2; `WRITE_VERBOSE("assign 2 to a\n");  // a==2
+      #1 a = 0; `WRITE_VERBOSE("assign 0 to a\n");
+      #1 a = 2; `WRITE_VERBOSE("assign 2 to a\n");  // 1<a<3
+      #1 b = 2; `WRITE_VERBOSE("assign 2 to b\n");
+      #1 a = 1; `WRITE_VERBOSE("assign 1 to a\n");  // b>a
+      #1 c = 3; `WRITE_VERBOSE("assign 3 to c\n");
+      #1 c = 4; `WRITE_VERBOSE("assign 4 to c\n");  // a+b<c
+      #1 c = 4; `WRITE_VERBOSE("assign 5 to b\n");  // a<b && b>c
+      b = 5;
    end
 
    initial begin
-     #1 `WRITE_VERBOSE("waiting for a==2\n");
-     wait(a == 2) if (a != 2) $stop;
-     `WRITE_VERBOSE("waiting for a<2\n");
-     wait(a < 2) if (a >= 2) $stop;
-     `WRITE_VERBOSE("waiting for a==0\n");
-     wait(a == 0) if (a != 0) $stop;
-     `WRITE_VERBOSE("waiting for 1<a<3\n");
-     wait(a > 1 && a < 3) if (a <= 1 || a >= 3) $stop;
-     `WRITE_VERBOSE("waiting for b>a\n");
-     wait(b > a) if (b <= a) $stop;
-     `WRITE_VERBOSE("waiting for a+b<c\n");
-     wait(a + b < c) if (a + b >= c) $stop;
-     `WRITE_VERBOSE("waiting for a<b && b>c\n");
-     wait(a < b && b > c) if (a >= b || b <= c) $stop;
-     wait(0 < 1) $write("*-* All Finished *-*\n");
-     $finish;
+      #1 `WRITE_VERBOSE("waiting for a==2\n");
+      wait(a == 2) if (a != 2) $stop;
+      `WRITE_VERBOSE("waiting for a<2\n");
+      wait(a < 2) if (a >= 2) $stop;
+      `WRITE_VERBOSE("waiting for a==0\n");
+      wait(a == 0) if (a != 0) $stop;
+      `WRITE_VERBOSE("waiting for 1<a<3\n");
+      wait(a > 1 && a < 3) if (a <= 1 || a >= 3) $stop;
+      `WRITE_VERBOSE("waiting for b>a\n");
+      wait(b > a) if (b <= a) $stop;
+      `WRITE_VERBOSE("waiting for a+b<c\n");
+      wait(a + b < c) if (a + b >= c) $stop;
+      `WRITE_VERBOSE("waiting for a<b && b>c\n");
+      wait(a < b && b > c) if (a >= b || b <= c) $stop;
+
+      wait(1);
+
+      wait(0 < 1) $write("*-* All Finished *-*\n");
+      $finish;
    end
 
    initial wait(0) $stop;

From b2e61425d6eb55e0a9a56558cd707aa38f69cc7a Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 11 Nov 2022 17:45:34 -0500
Subject: [PATCH 023/156] Fix const initial assignments.

---
 src/V3Width.cpp                 |  1 +
 test_regress/t/t_class_const.pl | 21 +++++++++++++++++++++
 test_regress/t/t_class_const.v  | 20 ++++++++++++++++++++
 3 files changed, 42 insertions(+)
 create mode 100755 test_regress/t/t_class_const.pl
 create mode 100644 test_regress/t/t_class_const.v

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 06e8bfef5..894e610ea 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -2116,6 +2116,7 @@ private:
             nodep->v3error("Assigning to const ref variable: " << nodep->prettyNameQ());
         } else if (nodep->access().isWriteOrRW() && nodep->varp()->isConst() && !m_paramsOnly
                    && (!m_ftaskp || !m_ftaskp->isConstructor())
+                   && !VN_IS(m_procedurep, InitialAutomatic)
                    && !VN_IS(m_procedurep, InitialStatic)) {
             // Too loose, but need to allow our generated first assignment
             // Move this to a property of the AstInitial block
diff --git a/test_regress/t/t_class_const.pl b/test_regress/t/t_class_const.pl
new file mode 100755
index 000000000..1aa73f80a
--- /dev/null
+++ b/test_regress/t/t_class_const.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_class_const.v b/test_regress/t/t_class_const.v
new file mode 100644
index 000000000..5c30fa001
--- /dev/null
+++ b/test_regress/t/t_class_const.v
@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls;
+   const int aconst = 10;
+   static const int astatic = 20;
+endclass
+
+module t;
+   initial begin
+      Cls c = new;
+      if (c.aconst !== 10) $stop;
+      if (Cls::astatic !== 20) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

From 227e61f89152e36bc14bdb01c688449fd9c03822 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 11 Nov 2022 18:01:30 -0500
Subject: [PATCH 024/156] Fix comparing ranged slices of unpacked arrays.

---
 Changes                       |  1 +
 src/V3Slice.cpp               | 10 ++++------
 test_regress/t/t_slice_cmp.pl | 21 +++++++++++++++++++++
 test_regress/t/t_slice_cmp.v  | 27 +++++++++++++++++++++++++++
 4 files changed, 53 insertions(+), 6 deletions(-)
 create mode 100755 test_regress/t/t_slice_cmp.pl
 create mode 100644 test_regress/t/t_slice_cmp.v

diff --git a/Changes b/Changes
index c12d111f4..e00fffb99 100644
--- a/Changes
+++ b/Changes
@@ -20,6 +20,7 @@ Verilator 5.003 devel
 * Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
 * Fix tracing parameters overridden with -G (#3723). [Iztok Jeras]
 * Fix wait 0.
+* Fix comparing ranged slices of unpacked arrays.
 
 
 Verilator 5.002 2022-10-29
diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp
index 332612d87..07041f204 100644
--- a/src/V3Slice.cpp
+++ b/src/V3Slice.cpp
@@ -185,14 +185,12 @@ class SliceVisitor final : public VNVisitor {
                         << nodep->rhsp()->prettyTypeName()
                         << " on non-slicable (e.g. non-vector) right-hand-side operand");
                 } else {
-                    for (int index = 0; index < adtypep->rangep()->elementsConst(); ++index) {
+                    const int elements = adtypep->rangep()->elementsConst();
+                    for (int offset = 0; offset < elements; ++offset) {
                         // EQ(a,b) -> LOGAND(EQ(ARRAYSEL(a,0), ARRAYSEL(b,0)), ...[1])
                         AstNodeBiop* const clonep
-                            = VN_AS(nodep->cloneType(
-                                        new AstArraySel{nodep->fileline(),
-                                                        nodep->lhsp()->cloneTree(false), index},
-                                        new AstArraySel{nodep->fileline(),
-                                                        nodep->rhsp()->cloneTree(false), index}),
+                            = VN_AS(nodep->cloneType(cloneAndSel(nodep->lhsp(), elements, offset),
+                                                     cloneAndSel(nodep->rhsp(), elements, offset)),
                                     NodeBiop);
                         if (!logp) {
                             logp = clonep;
diff --git a/test_regress/t/t_slice_cmp.pl b/test_regress/t/t_slice_cmp.pl
new file mode 100755
index 000000000..2cb5eeaff
--- /dev/null
+++ b/test_regress/t/t_slice_cmp.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2021 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_slice_cmp.v b/test_regress/t/t_slice_cmp.v
new file mode 100644
index 000000000..322c389b6
--- /dev/null
+++ b/test_regress/t/t_slice_cmp.v
@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+
+   bit a [5:0];
+   bit b [5:0];
+
+   initial begin
+      a = '{1, 1, 1, 0, 0, 0};
+      b = '{0, 0, 0, 1, 1, 1};
+      $display(":assert: ('%b%b%b_%b%b%b' == '111_000')",
+               a[5], a[4], a[3], a[2], a[1], a[0]);
+      $display(":assert: ('%b%b%b_%b%b%b' == '000_111')",
+               b[5], b[4], b[3], b[2], b[1], b[0]);
+
+      if ((a[5:3] == b[2:0]) != 1'b1) $stop;
+      if ((a[5:3] != b[2:0]) != 1'b0) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

From 41d2ebe2888f8f1f9560ec5de6e7674c81089aad Mon Sep 17 00:00:00 2001
From: "William D. Jones" <thor0505@comcast.net>
Date: Fri, 11 Nov 2022 21:43:10 -0500
Subject: [PATCH 025/156] Fix CONTEXT compile error on mingw64 (#3741).

---
 src/V3Width.cpp | 115 ++++++++++++++++++++++++------------------------
 1 file changed, 58 insertions(+), 57 deletions(-)

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 894e610ea..8bbb422ca 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -96,7 +96,7 @@ std::ostream& operator<<(std::ostream& str, const Stage& rhs) {
 
 enum Determ : uint8_t {
     SELF,  // Self-determined
-    CONTEXT,  // Context-determined
+    CONTEXT_DET,  // Context-determined
     ASSIGN  // Assignment-like where sign comes from RHS only
 };
 std::ostream& operator<<(std::ostream& str, const Determ& rhs) {
@@ -460,7 +460,7 @@ private:
             // Just once, do the conditional, expect one bit out.
             iterateCheckBool(nodep, "Conditional Test", nodep->condp(), BOTH);
             // Determine sub expression widths only relying on what's in the subops
-            //  CONTEXT determined, but need data type for pattern assignments
+            //  CONTEXT_DET determined, but need data type for pattern assignments
             userIterateAndNext(nodep->thenp(), WidthVP(m_vup->dtypeNullp(), PRELIM).p());
             userIterateAndNext(nodep->elsep(), WidthVP(m_vup->dtypeNullp(), PRELIM).p());
             // Calculate width of this expression.
@@ -485,9 +485,9 @@ private:
             AstNodeDType* const subDTypep = expDTypep;
             nodep->dtypeFrom(expDTypep);
             // Error report and change sizes for suboperands of this node.
-            iterateCheck(nodep, "Conditional True", nodep->thenp(), CONTEXT, FINAL, subDTypep,
+            iterateCheck(nodep, "Conditional True", nodep->thenp(), CONTEXT_DET, FINAL, subDTypep,
                          EXTEND_EXP);
-            iterateCheck(nodep, "Conditional False", nodep->elsep(), CONTEXT, FINAL, subDTypep,
+            iterateCheck(nodep, "Conditional False", nodep->elsep(), CONTEXT_DET, FINAL, subDTypep,
                          EXTEND_EXP);
         }
     }
@@ -823,7 +823,7 @@ private:
         UASSERT_OBJ(m_vup, nodep, "Select under an unexpected context");
         if (m_vup->prelim()) {
             if (debug() >= 9) nodep->dumpTree(cout, "-selWidth: ");
-            userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT, PRELIM).p());
+            userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT_DET, PRELIM).p());
             userIterateAndNext(nodep->lsbp(), WidthVP(SELF, PRELIM).p());
             checkCvtUS(nodep->fromp());
             iterateCheckSizedSelf(nodep, "Select Width", nodep->widthp(), SELF, BOTH);
@@ -1067,9 +1067,9 @@ private:
 
     void visit(AstSelBit* nodep) override {
         // Just a quick check as after V3Param these nodes instead are AstSel's
-        userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->thsp(), WidthVP(CONTEXT, PRELIM).p());  // FINAL in AstSel
+        userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
+        userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
+        userIterateAndNext(nodep->thsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
         userIterateAndNext(nodep->attrp(), WidthVP(SELF, BOTH).p());
         AstNode* const selp = V3Width::widthSelNoIterEdit(nodep);
         if (selp != nodep) {
@@ -1081,9 +1081,9 @@ private:
     }
     void visit(AstSelExtract* nodep) override {
         // Just a quick check as after V3Param these nodes instead are AstSel's
-        userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->thsp(), WidthVP(CONTEXT, PRELIM).p());  // FINAL in AstSel
+        userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
+        userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
+        userIterateAndNext(nodep->thsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
         userIterateAndNext(nodep->attrp(), WidthVP(SELF, BOTH).p());
         AstNode* const selp = V3Width::widthSelNoIterEdit(nodep);
         if (selp != nodep) {
@@ -1094,9 +1094,9 @@ private:
         nodep->v3fatalSrc("AstSelExtract should disappear after widthSel");
     }
     void visit(AstSelPlus* nodep) override {
-        userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->thsp(), WidthVP(CONTEXT, PRELIM).p());  // FINAL in AstSel
+        userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
+        userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
+        userIterateAndNext(nodep->thsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
         userIterateAndNext(nodep->attrp(), WidthVP(SELF, BOTH).p());
         AstNode* const selp = V3Width::widthSelNoIterEdit(nodep);
         if (selp != nodep) {
@@ -1107,9 +1107,9 @@ private:
         nodep->v3fatalSrc("AstSelPlus should disappear after widthSel");
     }
     void visit(AstSelMinus* nodep) override {
-        userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->thsp(), WidthVP(CONTEXT, PRELIM).p());  // FINAL in AstSel
+        userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
+        userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
+        userIterateAndNext(nodep->thsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
         userIterateAndNext(nodep->attrp(), WidthVP(SELF, BOTH).p());
         AstNode* const selp = V3Width::widthSelNoIterEdit(nodep);
         if (selp != nodep) {
@@ -1222,8 +1222,8 @@ private:
         if (m_vup->prelim()) {
             nodep->dtypeSetUInt32();  // Says the spec
             AstNodeDType* const expDTypep = nodep->findUInt32DType();
-            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT, PRELIM).p());
-            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
             iterateCheck(nodep, "LHS", nodep->lhsp(), SELF, FINAL, expDTypep, EXTEND_EXP);
             iterateCheck(nodep, "RHS", nodep->rhsp(), SELF, FINAL, expDTypep, EXTEND_EXP);
         }
@@ -1276,8 +1276,8 @@ private:
         // RHS is self-determined (IEEE)
         // Real if either side is real (as with AstAdd)
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT, PRELIM).p());
-            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
             if (nodep->lhsp()->isDouble() || nodep->rhsp()->isDouble()) {
                 spliceCvtD(nodep->lhsp());
                 spliceCvtD(nodep->rhsp());
@@ -1958,7 +1958,8 @@ private:
                        : nodep->findBitDType(calcWidth, calcWidth, underDtp->numeric()));
             nodep->dtypep(calcDtp);
             // We ignore warnings as that is sort of the point of a cast
-            iterateCheck(nodep, "Cast expr", underp, CONTEXT, FINAL, calcDtp, EXTEND_EXP, false);
+            iterateCheck(nodep, "Cast expr", underp, CONTEXT_DET, FINAL, calcDtp, EXTEND_EXP,
+                         false);
             VL_DANGLING(underp);
             underp = nodep->op1p();  // Above asserts that op1 was underp pre-relink
         }
@@ -2196,10 +2197,10 @@ private:
         nodep->dtypep(vdtypep);
         if (nodep->valuep()) {  // else the value will be assigned sequentially
             // Default type is int, but common to assign narrower values, so minwidth from value
-            userIterateAndNext(nodep->valuep(), WidthVP(CONTEXT, PRELIM).p());
+            userIterateAndNext(nodep->valuep(), WidthVP(CONTEXT_DET, PRELIM).p());
             // Minwidth does not come from value, as spec says set based on parent
             // and if we keep minwidth we'll consider it unsized which is incorrect
-            iterateCheck(nodep, "Enum value", nodep->valuep(), CONTEXT, FINAL, nodep->dtypep(),
+            iterateCheck(nodep, "Enum value", nodep->valuep(), CONTEXT_DET, FINAL, nodep->dtypep(),
                          EXTEND_EXP);
         }
     }
@@ -2223,7 +2224,7 @@ private:
         if (m_vup->prelim()) {
             nodep->dtypeFrom(vdtypep);
             if (nodep->defaultp()) {
-                iterateCheck(nodep, "default", nodep->defaultp(), CONTEXT, FINAL,
+                iterateCheck(nodep, "default", nodep->defaultp(), CONTEXT_DET, FINAL,
                              vdtypep->subDTypep(), EXTEND_EXP);
             }
         }
@@ -2235,9 +2236,9 @@ private:
         if (m_vup->prelim()) {
             nodep->dtypeFrom(vdtypep);
             userIterateAndNext(nodep->lhsp(), WidthVP(vdtypep, BOTH).p());
-            iterateCheck(nodep, "key", nodep->keyp(), CONTEXT, FINAL, vdtypep->keyDTypep(),
+            iterateCheck(nodep, "key", nodep->keyp(), CONTEXT_DET, FINAL, vdtypep->keyDTypep(),
                          EXTEND_EXP);
-            iterateCheck(nodep, "value", nodep->valuep(), CONTEXT, FINAL, vdtypep->subDTypep(),
+            iterateCheck(nodep, "value", nodep->valuep(), CONTEXT_DET, FINAL, vdtypep->subDTypep(),
                          EXTEND_EXP);
         }
     }
@@ -2248,7 +2249,7 @@ private:
         if (m_vup->prelim()) {
             nodep->dtypeFrom(vdtypep);
             if (nodep->defaultp()) {
-                iterateCheck(nodep, "default", nodep->defaultp(), CONTEXT, FINAL,
+                iterateCheck(nodep, "default", nodep->defaultp(), CONTEXT_DET, FINAL,
                              vdtypep->subDTypep(), EXTEND_EXP);
             }
         }
@@ -2260,9 +2261,9 @@ private:
         if (m_vup->prelim()) {
             nodep->dtypeFrom(vdtypep);
             userIterateAndNext(nodep->lhsp(), WidthVP{vdtypep, BOTH}.p());
-            iterateCheck(nodep, "key", nodep->keyp(), CONTEXT, FINAL, vdtypep->findStringDType(),
-                         EXTEND_EXP);
-            iterateCheck(nodep, "value", nodep->valuep(), CONTEXT, FINAL, vdtypep->subDTypep(),
+            iterateCheck(nodep, "key", nodep->keyp(), CONTEXT_DET, FINAL,
+                         vdtypep->findStringDType(), EXTEND_EXP);
+            iterateCheck(nodep, "value", nodep->valuep(), CONTEXT_DET, FINAL, vdtypep->subDTypep(),
                          EXTEND_EXP);
         }
     }
@@ -2349,10 +2350,10 @@ private:
         }
     }
     void visit(AstInside* nodep) override {
-        userIterateAndNext(nodep->exprp(), WidthVP(CONTEXT, PRELIM).p());
+        userIterateAndNext(nodep->exprp(), WidthVP(CONTEXT_DET, PRELIM).p());
         for (AstNode *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) {
             nextip = itemp->nextp();  // iterate may cause the node to get replaced
-            VL_DO_DANGLING(userIterate(itemp, WidthVP(CONTEXT, PRELIM).p()), itemp);
+            VL_DO_DANGLING(userIterate(itemp, WidthVP(CONTEXT_DET, PRELIM).p()), itemp);
         }
         // Take width as maximum across all items
         int width = nodep->exprp()->width();
@@ -2364,11 +2365,11 @@ private:
         // Apply width
         AstNodeDType* const subDTypep
             = nodep->findLogicDType(width, mwidth, nodep->exprp()->dtypep()->numeric());
-        iterateCheck(nodep, "Inside expression", nodep->exprp(), CONTEXT, FINAL, subDTypep,
+        iterateCheck(nodep, "Inside expression", nodep->exprp(), CONTEXT_DET, FINAL, subDTypep,
                      EXTEND_EXP);
         for (AstNode *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) {
             nextip = itemp->nextp();  // iterate may cause the node to get replaced
-            iterateCheck(nodep, "Inside Item", itemp, CONTEXT, FINAL, subDTypep, EXTEND_EXP);
+            iterateCheck(nodep, "Inside Item", itemp, CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP);
         }
         nodep->dtypeSetBit();
         if (debug() >= 9) nodep->dumpTree(cout, "-inside-in: ");
@@ -3008,14 +3009,14 @@ private:
     }
     AstNode* methodCallAssocIndexExpr(AstMethodCall* nodep, AstAssocArrayDType* adtypep) {
         AstNode* const index_exprp = VN_CAST(nodep->pinsp(), Arg)->exprp();
-        iterateCheck(nodep, "index", index_exprp, CONTEXT, FINAL, adtypep->keyDTypep(),
+        iterateCheck(nodep, "index", index_exprp, CONTEXT_DET, FINAL, adtypep->keyDTypep(),
                      EXTEND_EXP);
         VL_DANGLING(index_exprp);  // May have been edited
         return VN_AS(nodep->pinsp(), Arg)->exprp();
     }
     AstNode* methodCallWildcardIndexExpr(AstMethodCall* nodep, AstWildcardArrayDType* adtypep) {
         AstNode* const index_exprp = VN_CAST(nodep->pinsp(), Arg)->exprp();
-        iterateCheck(nodep, "index", index_exprp, CONTEXT, FINAL, adtypep->findStringDType(),
+        iterateCheck(nodep, "index", index_exprp, CONTEXT_DET, FINAL, adtypep->findStringDType(),
                      EXTEND_EXP);
         VL_DANGLING(index_exprp);  // May have been edited
         return VN_AS(nodep->pinsp(), Arg)->exprp();
@@ -4045,13 +4046,13 @@ private:
         //    Width: MAX(expr, all items)
         //    Signed: Only if expr, and all items signed
         assertAtStatement(nodep);
-        userIterateAndNext(nodep->exprp(), WidthVP(CONTEXT, PRELIM).p());
+        userIterateAndNext(nodep->exprp(), WidthVP(CONTEXT_DET, PRELIM).p());
         for (AstCaseItem *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) {
             nextip = VN_AS(itemp->nextp(), CaseItem);  // Prelim may cause the node to get replaced
             if (!VN_IS(nodep, GenCase)) userIterateAndNext(itemp->stmtsp(), nullptr);
             for (AstNode *nextcp, *condp = itemp->condsp(); condp; condp = nextcp) {
                 nextcp = condp->nextp();  // Prelim may cause the node to get replaced
-                VL_DO_DANGLING(userIterate(condp, WidthVP(CONTEXT, PRELIM).p()), condp);
+                VL_DO_DANGLING(userIterate(condp, WidthVP(CONTEXT_DET, PRELIM).p()), condp);
             }
         }
 
@@ -4076,13 +4077,13 @@ private:
             }
         }
         // Apply width
-        iterateCheck(nodep, "Case expression", nodep->exprp(), CONTEXT, FINAL, subDTypep,
+        iterateCheck(nodep, "Case expression", nodep->exprp(), CONTEXT_DET, FINAL, subDTypep,
                      EXTEND_LHS);
         for (AstCaseItem* itemp = nodep->itemsp(); itemp;
              itemp = VN_AS(itemp->nextp(), CaseItem)) {
             for (AstNode *nextcp, *condp = itemp->condsp(); condp; condp = nextcp) {
                 nextcp = condp->nextp();  // Final may cause the node to get replaced
-                iterateCheck(nodep, "Case Item", condp, CONTEXT, FINAL, subDTypep, EXTEND_LHS);
+                iterateCheck(nodep, "Case Item", condp, CONTEXT_DET, FINAL, subDTypep, EXTEND_LHS);
             }
         }
     }
@@ -4886,7 +4887,7 @@ private:
     void visit(AstGatePin* nodep) override {
         if (m_vup->prelim()) {
             userIterateAndNext(nodep->rangep(), WidthVP(SELF, BOTH).p());
-            userIterateAndNext(nodep->exprp(), WidthVP(CONTEXT, PRELIM).p());
+            userIterateAndNext(nodep->exprp(), WidthVP(CONTEXT_DET, PRELIM).p());
             nodep->dtypeFrom(nodep->rangep());
             // Very much like like an pin
             const AstNodeDType* const conDTypep = nodep->exprp()->dtypep();
@@ -5411,8 +5412,8 @@ private:
         //   TODO: chandle/class handle/iface handle no relational compares
         UASSERT_OBJ(nodep->rhsp(), nodep, "For binary ops only!");
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT, PRELIM).p());
-            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
             if (nodep->lhsp()->isDouble() || nodep->rhsp()->isDouble()) {
                 if (!realok) {
                     nodep->v3error("Real is illegal operand to ?== operator");
@@ -5457,9 +5458,9 @@ private:
                         warnOn = false;
                     }
                 }
-                iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT, FINAL, subDTypep,
+                iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT_DET, FINAL, subDTypep,
                              (signedFl ? EXTEND_LHS : EXTEND_ZERO), warnOn);
-                iterateCheck(nodep, "RHS", nodep->rhsp(), CONTEXT, FINAL, subDTypep,
+                iterateCheck(nodep, "RHS", nodep->rhsp(), CONTEXT_DET, FINAL, subDTypep,
                              (signedFl ? EXTEND_LHS : EXTEND_ZERO), warnOn);
             }
             nodep->dtypeSetBit();
@@ -5513,7 +5514,7 @@ private:
         //    Widths: out width = lhs width
         UASSERT_OBJ(!nodep->op2p(), nodep, "For unary ops only!");
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
             if (!real_ok) checkCvtUS(nodep->lhsp());
         }
         if (real_ok && nodep->lhsp()->isDouble()) {
@@ -5540,7 +5541,7 @@ private:
                 // Warn if user wants extra bit from carry
                 if (subDTypep->widthMin() == (nodep->lhsp()->widthMin() + 1)) lhsWarn = false;
             }
-            iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT, FINAL, subDTypep, EXTEND_EXP,
+            iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP,
                          lhsWarn);
         }
     }
@@ -5604,7 +5605,7 @@ private:
             bool warnOn = true;
             // No warning if "X = 1'b1<<N"; assume user is doing what they want
             if (nodep->lhsp()->isOne() && VN_IS(nodep->backp(), NodeAssign)) warnOn = false;
-            iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT, FINAL, subDTypep, EXTEND_EXP,
+            iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP,
                          warnOn);
             if (nodep->rhsp()->width() > 32) {
                 AstConst* const shiftp = VN_CAST(nodep->rhsp(), Const);
@@ -5633,8 +5634,8 @@ private:
         // to be the same for our operations.
         if (m_vup->prelim()) {  // First stage evaluation
             // Determine expression widths only relying on what's in the subops
-            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT, PRELIM).p());
-            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
             checkCvtUS(nodep->lhsp());
             checkCvtUS(nodep->rhsp());
             const int width = std::max(nodep->lhsp()->width(), nodep->rhsp()->width());
@@ -5647,8 +5648,8 @@ private:
             AstNodeDType* const subDTypep = expDTypep;
             nodep->dtypeFrom(expDTypep);
             // Error report and change sizes for suboperands of this node.
-            iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT, FINAL, subDTypep, EXTEND_EXP);
-            iterateCheck(nodep, "RHS", nodep->rhsp(), CONTEXT, FINAL, subDTypep, EXTEND_EXP);
+            iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP);
+            iterateCheck(nodep, "RHS", nodep->rhsp(), CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP);
         }
     }
 
@@ -5667,8 +5668,8 @@ private:
         // if (debug() >= 9) { UINFO(0,"-rus "<<m_vup<<endl); nodep->dumpTree(cout, "-rusin-"); }
         if (m_vup->prelim()) {  // First stage evaluation
             // Determine expression widths only relying on what's in the subops
-            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT, PRELIM).p());
-            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
             if (!real_ok) {
                 checkCvtUS(nodep->lhsp());
                 checkCvtUS(nodep->rhsp());
@@ -5715,9 +5716,9 @@ private:
             }
             // Final call, so make sure children check their sizes
             // Error report and change sizes for suboperands of this node.
-            iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT, FINAL, subDTypep, EXTEND_EXP,
+            iterateCheck(nodep, "LHS", nodep->lhsp(), CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP,
                          lhsWarn);
-            iterateCheck(nodep, "RHS", nodep->rhsp(), CONTEXT, FINAL, subDTypep, EXTEND_EXP,
+            iterateCheck(nodep, "RHS", nodep->rhsp(), CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP,
                          rhsWarn);
         }
         // if (debug() >= 9) nodep->dumpTree(cout, "-rusou-");

From a4278608255d7732a98dd35eb4a14b3c35227a08 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 11 Nov 2022 21:53:05 -0500
Subject: [PATCH 026/156] Support randcase.

---
 Changes                           |  1 +
 src/V3AstNodeExpr.h               |  2 +-
 src/V3AstNodeOther.h              | 10 ++++
 src/V3Randomize.cpp               | 69 ++++++++++++++++++++++++++++
 src/V3Width.cpp                   | 18 ++++++++
 src/verilog.y                     |  9 +++-
 test_regress/t/t_randcase.pl      | 21 +++++++++
 test_regress/t/t_randcase.v       | 76 +++++++++++++++++++++++++++++++
 test_regress/t/t_randcase_bad.out |  1 +
 test_regress/t/t_randcase_bad.pl  | 21 +++++++++
 test_regress/t/t_randcase_bad.v   | 18 ++++++++
 11 files changed, 243 insertions(+), 3 deletions(-)
 create mode 100755 test_regress/t/t_randcase.pl
 create mode 100644 test_regress/t/t_randcase.v
 create mode 100644 test_regress/t/t_randcase_bad.out
 create mode 100755 test_regress/t/t_randcase_bad.pl
 create mode 100644 test_regress/t/t_randcase_bad.v

diff --git a/Changes b/Changes
index e00fffb99..9da2aaabc 100644
--- a/Changes
+++ b/Changes
@@ -15,6 +15,7 @@ Verilator 5.003 devel
 
 * Deprecate --no-threads; use --threads 1 for single threaded (#3703). [Kamil Rakoczy, Antmicro Ltd]
 * Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd]
+* Support randcase.
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
 * Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index 305ac78b8..b1260e062 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -2839,7 +2839,7 @@ public:
 class AstURandomRange final : public AstNodeBiop {
     // $urandom_range
 public:
-    explicit AstURandomRange(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstURandomRange(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
         : ASTGEN_SUPER_URandomRange(fl, lhsp, rhsp) {
         dtypeSetUInt32();  // Says IEEE
     }
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index a88aa3ee6..9b52144fe 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -3012,6 +3012,16 @@ public:
     void timeunit(const VTimescale& flag) { m_timeunit = flag; }
     VTimescale timeunit() const { return m_timeunit; }
 };
+class AstRandCase final : public AstNodeStmt {
+    // @astgen op2 := itemsp : List[AstCaseItem]
+public:
+    AstRandCase(FileLine* fl, AstCaseItem* itemsp)
+        : ASTGEN_SUPER_RandCase(fl) {
+        addItemsp(itemsp);
+    }
+    ASTGEN_MEMBERS_AstRandCase;
+    int instrCount() const override { return INSTR_COUNT_BRANCH; }
+};
 class AstRelease final : public AstNodeStmt {
     // Procedural 'release' statement
     // @astgen op1 := lhsp : AstNode
diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index 385d50b3e..22a5074f2 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -100,6 +100,7 @@ private:
             markMembers(classp);
         }
     }
+
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
@@ -124,7 +125,9 @@ private:
     const VNUser2InUse m_inuser2;
 
     // STATE
+    AstNodeModule* m_modp = nullptr;  // Current module
     size_t m_enumValueTabCount = 0;  // Number of tables with enum values created
+    int m_randCaseNum = 0;  // Randcase number within a module for var naming
 
     // METHODS
     AstVar* enumValueTabp(AstEnumDType* nodep) {
@@ -197,7 +200,16 @@ private:
     }
 
     // VISITORS
+    void visit(AstNodeModule* nodep) override {
+        VL_RESTORER(m_randCaseNum);
+        m_modp = nodep;
+        m_randCaseNum = 0;
+        iterateChildren(nodep);
+    }
     void visit(AstClass* nodep) override {
+        VL_RESTORER(m_randCaseNum);
+        m_modp = nodep;
+        m_randCaseNum = 0;
         iterateChildren(nodep);
         if (!nodep->user1()) return;  // Doesn't need randomize, or already processed
         UINFO(9, "Define randomize() for " << nodep << endl);
@@ -239,6 +251,63 @@ private:
         }
         nodep->user1(false);
     }
+    void visit(AstRandCase* nodep) override {
+        // RANDCASE
+        //   CASEITEM expr1 : stmt1
+        //   CASEITEM expr2 : stmt2
+        // ->
+        //   tmp = URandomRange{0, num} + 1   // + 1 so weight 0 means never
+        //   if (tmp < expr1) stmt1;
+        //   else if (tmp < (expr2 + expr1)) stmt1;
+        //   else warning
+        // Note this code assumes that the expressions after V3Const are fast to compute
+        // Optimize: we would be better with a binary search tree to reduce ifs that execute
+        if (debug() >= 9) nodep->dumpTree(cout, "-rcin:  ");
+        AstNodeDType* const sumDTypep = nodep->findUInt64DType();
+
+        FileLine* const fl = nodep->fileline();
+        const std::string name = "__Vrandcase" + cvtToStr(m_randCaseNum++);
+        AstVar* const randVarp = new AstVar{fl, VVarType::STMTTEMP, name, sumDTypep};
+        randVarp->noSubst(true);
+        AstNodeExpr* sump = new AstConst{fl, AstConst::WidthedValue{}, 64, 0};
+        AstNodeIf* firstIfsp
+            = new AstIf{fl, new AstConst{fl, AstConst::BitFalse{}}, nullptr, nullptr};
+        AstNodeIf* ifsp = firstIfsp;
+
+        for (AstCaseItem* itemp = nodep->itemsp(); itemp;
+             itemp = VN_AS(itemp->nextp(), CaseItem)) {
+            AstNode* const condp = itemp->condsp()->unlinkFrBack();
+            sump
+                = new AstAdd{condp->fileline(), sump, new AstExtend{itemp->fileline(), condp, 64}};
+            AstNode* const stmtsp
+                = itemp->stmtsp() ? itemp->stmtsp()->unlinkFrBackWithNext() : nullptr;
+            AstNodeIf* const newifp
+                = new AstIf{itemp->fileline(),
+                            new AstLte{condp->fileline(),
+                                       new AstVarRef{condp->fileline(), randVarp, VAccess::READ},
+                                       sump->cloneTree(true)},
+                            stmtsp, nullptr};
+            ifsp->addElsesp(newifp);
+            ifsp = newifp;
+        }
+        AstDisplay* dispp = new AstDisplay{
+            fl, VDisplayType::DT_ERROR, "All randcase items had 0 weights (IEEE 1800-2017 18.16)",
+            nullptr, nullptr};
+        UASSERT_OBJ(m_modp, nodep, "randcase not under module");
+        dispp->fmtp()->timeunit(m_modp->timeunit());
+        ifsp->addElsesp(dispp);
+
+        AstNode* newp = randVarp;
+        AstNode* randp = new AstRand{fl, nullptr, false};
+        randp->dtypeSetUInt64();
+        newp->addNext(new AstAssign{fl, new AstVarRef{fl, randVarp, VAccess::WRITE},
+                                    new AstAdd{fl, new AstConst{fl, AstConst::Unsized64{}, 1},
+                                               new AstModDiv{fl, randp, sump}}});
+        newp->addNext(firstIfsp);
+        if (debug() >= 9) newp->dumpTreeAndNext(cout, "-rcnew: ");
+        nodep->replaceWith(newp);
+        VL_DO_DANGLING(pushDeletep(nodep), nodep);
+    }
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 8bbb422ca..758b919fa 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -4087,6 +4087,24 @@ private:
             }
         }
     }
+    void visit(AstRandCase* nodep) override {
+        // IEEE says each item is a int (32-bits), and sizes are based on natural sizing,
+        // but we'll sum to a 64-bit number then math is faster.
+        assertAtStatement(nodep);
+        v3Global.useRandomizeMethods(true);
+        AstNodeDType* const itemDTypep = nodep->findUInt32DType();
+        for (AstCaseItem *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) {
+            nextip = VN_AS(itemp->nextp(), CaseItem);  // Prelim may cause the node to get replaced
+            userIterateAndNext(itemp->stmtsp(), nullptr);
+            for (AstNode *nextcp, *condp = itemp->condsp(); condp; condp = nextcp) {
+                nextcp = condp->nextp();  // Prelim may cause the node to get replaced
+                iterateCheckTyped(itemp, "Randcase Item", condp, itemDTypep, BOTH);
+                VL_DANGLING(condp);  // Might have been replaced
+            }
+            VL_DANGLING(itemp);  // Might have been replaced
+        }
+    }
+
     void visit(AstNodeFor* nodep) override {
         assertAtStatement(nodep);
         userIterateAndNext(nodep->initsp(), nullptr);
diff --git a/src/verilog.y b/src/verilog.y
index 1367e140d..5e112eae8 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3369,8 +3369,7 @@ statement_item<nodep>:          // IEEE: statement_item
         //UNSUP randsequence_statement                  { $$ = $1; }
         //
         //                      // IEEE: randcase_statement
-        |       yRANDCASE case_itemList yENDCASE
-                        { $$ = nullptr; BBUNSUP($1, "Unsupported: SystemVerilog 2005 randcase statements"); }
+        |       yRANDCASE rand_case_itemList yENDCASE   { $$ = new AstRandCase{$1, $2}; }
         //
         //UNSUP expect_property_statement               { $$ = $1; }
         //
@@ -3527,6 +3526,12 @@ case_inside_itemList<caseItemp>:        // IEEE: { case_inside_item + open_range
         |       case_inside_itemList yDEFAULT colon stmtBlock   { $$ = $1->addNext(new AstCaseItem{$2, nullptr, $4}); }
         ;
 
+rand_case_itemList<caseItemp>:       // IEEE: { rand_case_item + ... }
+        //                      // Randcase syntax doesn't have default, or expression lists
+                expr colon stmtBlock                            { $$ = new AstCaseItem{$2, $1, $3}; }
+        |       rand_case_itemList expr colon stmtBlock         { $$ = $1->addNext(new AstCaseItem{$3, $2, $4}); }
+        ;
+
 open_range_list<nodep>:         // ==IEEE: open_range_list + open_value_range
                 open_value_range                        { $$ = $1; }
         |       open_range_list ',' open_value_range    { $$ = $1->addNext($3); }
diff --git a/test_regress/t/t_randcase.pl b/test_regress/t/t_randcase.pl
new file mode 100755
index 000000000..aabcde63e
--- /dev/null
+++ b/test_regress/t/t_randcase.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2020 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_randcase.v b/test_regress/t/t_randcase.v
new file mode 100644
index 000000000..331a53aa0
--- /dev/null
+++ b/test_regress/t/t_randcase.v
@@ -0,0 +1,76 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); $stop; end while(0);
+
+module t (/*AUTOARG*/);
+
+   localparam int COUNT = 1000;
+
+   int v;
+   int counts[8];
+
+   initial begin;
+
+      //
+      for (int i = 0; i < 8; ++i) counts[i] = 0;
+      for (int i = 0; i < COUNT; ++i) begin
+         randcase
+           0 : ;  // Never
+           0 : counts[0]++;  // Never
+           1 : counts[1]++;
+         endcase
+      end
+      `check_range(counts[0], 0, 0);
+      `check_range(counts[1], COUNT, COUNT);
+
+      //
+      for (int i = 0; i < 8; ++i) counts[i] = 0;
+      for (int i = 0; i < COUNT; ++i) begin
+         randcase
+           i - i : counts[0]++;  // Never
+           i + i + 1: counts[1]++;
+         endcase
+      end
+      `check_range(counts[0], 0, 0);
+      `check_range(counts[1], COUNT, COUNT);
+
+      //
+      for (int i = 0; i < 8; ++i) counts[i] = 0;
+      for (int i = 0; i < COUNT; ++i) begin
+         randcase
+           1 : counts[0]++;  // Never
+           4 : counts[1]++;
+         endcase
+      end
+      `check_range(counts[0], (COUNT * 1 / 5) * 70 / 100, (COUNT * 1 / 5) * 130 / 100);
+      `check_range(counts[1], (COUNT * 4 / 5) * 70 / 100, (COUNT * 4 / 5) * 130 / 100);
+
+      //
+      for (int i = 0; i < 8; ++i) counts[i] = 0;
+      for (int i = 0; i < COUNT; ++i) begin
+         randcase
+           2 : counts[0]++;  // Never
+           2 : counts[1]++;  // Never
+           1 : counts[2]++;  // Never
+           1 : counts[3]++;  // Never
+           1 : counts[4]++;  // Never
+           1 : counts[5]++;  // Never
+           1 : counts[6]++;  // Never
+           1 : counts[7]++;  // Never
+         endcase
+      end
+      `check_range(counts[0], (COUNT * 2 / 10) * 70 / 100, (COUNT * 2 / 10) * 130 / 100);
+      `check_range(counts[1], (COUNT * 2 / 10) * 70 / 100, (COUNT * 2 / 10) * 130 / 100);
+      `check_range(counts[2], (COUNT * 1 / 10) * 70 / 100, (COUNT * 1 / 10) * 130 / 100);
+      `check_range(counts[7], (COUNT * 1 / 10) * 70 / 100, (COUNT * 1 / 10) * 130 / 100);
+
+      //
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
diff --git a/test_regress/t/t_randcase_bad.out b/test_regress/t/t_randcase_bad.out
new file mode 100644
index 000000000..fa2e9ec7f
--- /dev/null
+++ b/test_regress/t/t_randcase_bad.out
@@ -0,0 +1 @@
+[0] %Error: t_randcase_bad.v:12: Assertion failed in top.t.unnamedblk1: All randcase items had 0 weights (IEEE 1800-2017 18.16)
diff --git a/test_regress/t/t_randcase_bad.pl b/test_regress/t/t_randcase_bad.pl
new file mode 100755
index 000000000..e988c6264
--- /dev/null
+++ b/test_regress/t/t_randcase_bad.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    );
+
+execute(
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_randcase_bad.v b/test_regress/t/t_randcase_bad.v
new file mode 100644
index 000000000..a299b04e1
--- /dev/null
+++ b/test_regress/t/t_randcase_bad.v
@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Test of select from constant
+//
+// This tests issue 508, bit select of constant fails
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+
+   initial begin
+      randcase  // Bad all zero weights
+        0 : $stop;
+      endcase
+      $finish;
+   end
+
+endmodule

From 6736e92cdb03ff5f43a5bb8f05c2283f4ef61691 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 11 Nov 2022 22:33:17 -0500
Subject: [PATCH 027/156] Internals: Fix some ugly line breaks. No functional
 change.

---
 src/V3LinkDot.cpp     | 4 ++--
 src/V3LinkResolve.cpp | 4 ++--
 src/V3Width.cpp       | 8 ++++----
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 011e408b7..32a02e295 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1165,8 +1165,8 @@ class LinkDotFindVisitor final : public VNVisitor {
                                        << nodep->prettyNameQ() << '\n'
                                        << (ansiWarn ? nodep->warnMore()
                                                           + "... note: ANSI ports must have"
-                                                            " type declared with the I/O (IEEE "
-                                                            "1800-2017 23.2.2.2)\n"
+                                                            " type declared with the I/O"
+                                                            " (IEEE 1800-2017 23.2.2.2)\n"
                                                     : "")
                                        << nodep->warnContextPrimary() << '\n'
                                        << findvarp->warnOther()
diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp
index fdcfb1f80..ca4352e2b 100644
--- a/src/V3LinkResolve.cpp
+++ b/src/V3LinkResolve.cpp
@@ -119,8 +119,8 @@ private:
                 nodep->v3warn(E_UNSUPPORTED, "Unsupported: " << nodep->prettyNameQ());
             } else if (nodep->name() == "randomize") {
                 nodep->v3error(nodep->prettyNameQ()
-                               << " is a predefined class method; redefinition not allowed (IEEE "
-                                  "1800-2017 18.6.3)");
+                               << " is a predefined class method; redefinition not allowed"
+                                  " (IEEE 1800-2017 18.6.3)");
             }
             nodep->classMethod(true);
         }
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 758b919fa..d3d9ce430 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -683,8 +683,8 @@ private:
             uint32_t times = constp->toUInt();
             if (times == 0
                 && !VN_IS(nodep->backp(), Concat)) {  // Concat Visitor will clean it up.
-                nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE "
-                               "1800-2017 11.4.12.1)");
+                nodep->v3error("Replication value of 0 is only legal under a concatenation"
+                               " (IEEE 1800-2017 11.4.12.1)");
                 times = 1;
             }
 
@@ -743,8 +743,8 @@ private:
             const uint32_t times = constp->toUInt();
             if (times == 0
                 && !VN_IS(nodep->backp(), Concat)) {  // Concat Visitor will clean it up.
-                nodep->v3error("Replication value of 0 is only legal under a concatenation (IEEE "
-                               "1800-2017 11.4.12.1)");
+                nodep->v3error("Replication value of 0 is only legal under a concatenation"
+                               " (IEEE 1800-2017 11.4.12.1)");
             }
             nodep->dtypeSetString();
         }

From dbcaad99c5ec083f79bb5d7781132d4252d0cd7e Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Sat, 12 Nov 2022 11:35:23 +0000
Subject: [PATCH 028/156] Dfg: Fix crash on additional driver from non-DFG
 logic

Ensure variables written by non-DFG code are kept

Fixes #3740
---
 src/V3DfgAstToDfg.cpp                       |  3 +++
 src/V3DfgDfgToAst.cpp                       | 14 ++++++-------
 src/V3DfgOptimizer.cpp                      |  7 +++++--
 src/V3DfgVertices.h                         |  2 ++
 test_regress/t/t_dfg_multidriver_non_dfg.pl | 16 +++++++++++++++
 test_regress/t/t_dfg_multidriver_non_dfg.v  | 22 +++++++++++++++++++++
 6 files changed, 55 insertions(+), 9 deletions(-)
 create mode 100755 test_regress/t/t_dfg_multidriver_non_dfg.pl
 create mode 100644 test_regress/t/t_dfg_multidriver_non_dfg.v

diff --git a/src/V3DfgAstToDfg.cpp b/src/V3DfgAstToDfg.cpp
index d81ecbfb3..b9445d674 100644
--- a/src/V3DfgAstToDfg.cpp
+++ b/src/V3DfgAstToDfg.cpp
@@ -94,7 +94,10 @@ class AstToDfgVisitor final : public VNVisitor {
         nodep->foreach([this](const AstVarRef* refp) {
             // No need to (and in fact cannot) mark variables with unsupported dtypes
             if (!DfgVertex::isSupportedDType(refp->varp()->dtypep())) return;
+            // Mark vertex as having a module reference outside current DFG
             getNet(refp->varp())->setHasModRefs();
+            // Mark variable as written from non-DFG logic
+            if (refp->access().isWriteOrRW()) refp->varp()->user3(true);
         });
     }
 
diff --git a/src/V3DfgDfgToAst.cpp b/src/V3DfgDfgToAst.cpp
index 32fb87b8f..315088dec 100644
--- a/src/V3DfgDfgToAst.cpp
+++ b/src/V3DfgDfgToAst.cpp
@@ -415,14 +415,14 @@ class DfgToAstVisitor final : DfgVisitor {
         // Remap all references to point to the canonical variables, if one exists
         VNDeleter deleter;
         m_modp->foreach([&](AstVarRef* refp) {
-            // Any variable that is written outside the DFG will have itself as the canonical
-            // var, so need not be replaced, furthermore, if a variable is traced, we don't
-            // want to update the write ref we just created above, so we only replace read only
-            // references.
-            if (!refp->access().isReadOnly()) return;
+            // Any variable that is written partially outside the DFG will have itself as the
+            // canonical var, so need not be replaced, furthermore, if a variable is traced, we
+            // don't want to update the write-refs we just created above, so we only replace
+            // read-only references to those variables to those variables we know are not written
+            // in non-DFG logic.
+            if (!refp->access().isReadOnly() || refp->varp()->user3()) return;
             const auto it = m_canonVars.find(refp->varp());
-            if (it == m_canonVars.end()) return;
-            if (it->second == refp->varp()) return;
+            if (it == m_canonVars.end() || it->second == refp->varp()) return;
             refp->replaceWith(new AstVarRef{refp->fileline(), it->second, refp->access()});
             deleter.pushDeletep(refp);
         });
diff --git a/src/V3DfgOptimizer.cpp b/src/V3DfgOptimizer.cpp
index f093b453d..d3b2eba4f 100644
--- a/src/V3DfgOptimizer.cpp
+++ b/src/V3DfgOptimizer.cpp
@@ -244,9 +244,12 @@ void V3DfgOptimizer::optimize(AstNetlist* netlistp, const string& label) {
     UINFO(2, __FUNCTION__ << ": " << endl);
 
     // NODE STATE
-    // AstVar::user1        -> Used by V3DfgPasses::astToDfg
-    // AstVar::user2        -> bool: Flag indicating referenced by AstVarXRef
+    // AstVar::user1 -> Used by V3DfgPasses::astToDfg and DfgPassed::dfgToAst
+    // AstVar::user2 -> bool: Flag indicating referenced by AstVarXRef (set just below)
+    // AstVar::user3 -> bool: Flag indicating written by logic not representable as DFG
+    //                        (set by V3DfgPasses::astToDfg)
     const VNUser2InUse user2InUse;
+    const VNUser3InUse user3InUse;
 
     // Mark cross-referenced variables
     netlistp->foreach([](const AstVarXRef* xrefp) { xrefp->varp()->user2(true); });
diff --git a/src/V3DfgVertices.h b/src/V3DfgVertices.h
index 5c3700308..a440f9b8d 100644
--- a/src/V3DfgVertices.h
+++ b/src/V3DfgVertices.h
@@ -76,6 +76,8 @@ public:
         if (v3Global.opt.trace() && varp()->isTrace()) return true;
         // Keep if public
         if (varp()->isSigPublic()) return true;
+        // Keep if written in non-DFG code
+        if (varp()->user3()) return true;
         // Otherwise it can be removed
         return false;
     }
diff --git a/test_regress/t/t_dfg_multidriver_non_dfg.pl b/test_regress/t/t_dfg_multidriver_non_dfg.pl
new file mode 100755
index 000000000..84ae125be
--- /dev/null
+++ b/test_regress/t/t_dfg_multidriver_non_dfg.pl
@@ -0,0 +1,16 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Geza Lore. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile();
+
+ok(1);
+1;
diff --git a/test_regress/t/t_dfg_multidriver_non_dfg.v b/test_regress/t/t_dfg_multidriver_non_dfg.v
new file mode 100644
index 000000000..9fcb61b5e
--- /dev/null
+++ b/test_regress/t/t_dfg_multidriver_non_dfg.v
@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Geza Lore.
+// SPDX-License-Identifier: CC0-1.0
+
+`default_nettype none
+
+module t(
+    input  wire i,
+    output wire o
+);
+    logic a;
+    logic b;
+    initial begin
+        a = 1'd0;
+        b = 1'd0;
+    end
+    assign a = ~i;
+    assign b = a;
+    assign o = b;
+endmodule

From 0a045a7bf6fe928645c9895520a5aae0be4537a0 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 12 Nov 2022 12:09:37 -0500
Subject: [PATCH 029/156] Change ENDLABEL from warning into an error.

---
 Changes                                       |  1 +
 docs/guide/exe_verilator.rst                  |  4 ++--
 docs/guide/warnings.rst                       |  8 ++++----
 src/V3Error.h                                 |  6 +++---
 test_regress/t/t_hierarchy_identifier_bad.out | 13 ++++++-------
 5 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/Changes b/Changes
index 9da2aaabc..13e49197e 100644
--- a/Changes
+++ b/Changes
@@ -17,6 +17,7 @@ Verilator 5.003 devel
 * Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd]
 * Support randcase.
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
+* Change ENDLABEL from warning into an error.
 * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
 * Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
 * Fix tracing parameters overridden with -G (#3723). [Iztok Jeras]
diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst
index 35b589351..ffb990356 100644
--- a/docs/guide/exe_verilator.rst
+++ b/docs/guide/exe_verilator.rst
@@ -1490,7 +1490,7 @@ Summary:
    Disable all lint related warning messages, and all style warnings.  This is
    equivalent to ``-Wno-ALWCOMBORDER -Wno-BSSPACE -Wno-CASEINCOMPLETE
    -Wno-CASEOVERLAP -Wno-CASEX -Wno-CASTCONST -Wno-CASEWITHX -Wno-CMPCONST -Wno-COLONPLUS
-   -Wno-ENDLABEL -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINCONNECTEMPTY
+   -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINCONNECTEMPTY
    -Wno-PINMISSING -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED
    -Wno-UNUSEDGENVAR -Wno-UNUSEDPARAM -Wno-UNUSEDSIGNAL
    -Wno-WIDTH`` plus the list shown for Wno-style.
@@ -1526,7 +1526,7 @@ Summary:
    enabled), but do not affect style messages.  This is equivalent to
    ``-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE -Wwarn-CASEINCOMPLETE
    -Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASTCONST -Wwarn-CASEWITHX -Wwarn-CMPCONST
-   -Wwarn-COLONPLUS -Wwarn-ENDLABEL -Wwarn-IMPLICIT -Wwarn-LITENDIAN
+   -Wwarn-COLONPLUS -Wwarn-IMPLICIT -Wwarn-LITENDIAN
    -Wwarn-PINMISSING -Wwarn-REALCVT -Wwarn-UNSIGNED -Wwarn-WIDTH``.
 
 .. option:: -Wwarn-style
diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst
index 681f11ab5..3a5f625de 100644
--- a/docs/guide/warnings.rst
+++ b/docs/guide/warnings.rst
@@ -537,11 +537,11 @@ List Of Warnings
 
 .. option:: ENDLABEL
 
-   Warns that a label attached to a "end"-something statement does not
+   Error that a label attached to a "end"-something statement does not
    match the label attached to the block start.
 
-   Ignoring this warning will only suppress the lint check, it will
-   simulate correctly.
+   This error is required by IEEE. Ignoring this warning will only suppress
+   the lint check, it will simulate correctly.
 
    Faulty example:
 
@@ -556,7 +556,7 @@ List Of Warnings
 
    .. code-block::
 
-         %Warning-ENDLABEL: example.v:2:13: End label 'not_mine' does not match begin label 'mine'
+         %Error-ENDLABEL: example.v:2:13: End label 'not_mine' does not match begin label 'mine'
 
    To repair either fix the end label's name, or remove entirely.
 
diff --git a/src/V3Error.h b/src/V3Error.h
index 2aca831d9..1268136a2 100644
--- a/src/V3Error.h
+++ b/src/V3Error.h
@@ -206,8 +206,8 @@ public:
     // Later -Werror- options may make more of these.
     bool pretendError() const VL_MT_SAFE {
         return (m_e == ASSIGNIN || m_e == BADSTDPRAGMA || m_e == BLKANDNBLK || m_e == BLKLOOPINIT
-                || m_e == CONTASSREG || m_e == IMPURE || m_e == PINNOTFOUND || m_e == PKGNODECL
-                || m_e == PROCASSWIRE  // Says IEEE
+                || m_e == CONTASSREG || m_e == ENDLABEL || m_e == IMPURE || m_e == PINNOTFOUND
+                || m_e == PKGNODECL || m_e == PROCASSWIRE  // Says IEEE
                 || m_e == ZERODLY);
     }
     // Warnings to mention manual
@@ -218,7 +218,7 @@ public:
     bool lintError() const VL_MT_SAFE {
         return (m_e == ALWCOMBORDER || m_e == BSSPACE || m_e == CASEINCOMPLETE
                 || m_e == CASEOVERLAP || m_e == CASEWITHX || m_e == CASEX || m_e == CASTCONST
-                || m_e == CMPCONST || m_e == COLONPLUS || m_e == ENDLABEL || m_e == IMPLICIT
+                || m_e == CMPCONST || m_e == COLONPLUS || m_e == IMPLICIT
                 || m_e == LATCH || m_e == LITENDIAN || m_e == PINMISSING || m_e == REALCVT
                 || m_e == UNSIGNED || m_e == WIDTH);
     }
diff --git a/test_regress/t/t_hierarchy_identifier_bad.out b/test_regress/t/t_hierarchy_identifier_bad.out
index b18adbb8e..fb853a322 100644
--- a/test_regress/t/t_hierarchy_identifier_bad.out
+++ b/test_regress/t/t_hierarchy_identifier_bad.out
@@ -1,18 +1,17 @@
-%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:34:10: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish'
+%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:34:10: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish'
    34 |    end : if_cnt_finish_bad
       |          ^~~~~~~~~~~~~~~~~
-                   ... For warning description see https://verilator.org/warn/ENDLABEL?v=latest
-                   ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message.
-%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:40:10: End label 'generate_for_bad' does not match begin label 'generate_for'
+                 ... For error description see https://verilator.org/warn/ENDLABEL?v=latest
+%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:40:10: End label 'generate_for_bad' does not match begin label 'generate_for'
    40 |    end : generate_for_bad
       |          ^~~~~~~~~~~~~~~~
-%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:47:10: End label 'generate_if_if_bad' does not match begin label 'generate_if_if'
+%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:47:10: End label 'generate_if_if_bad' does not match begin label 'generate_if_if'
    47 |    end : generate_if_if_bad
       |          ^~~~~~~~~~~~~~~~~~
-%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:51:10: End label 'generate_if_else_bad' does not match begin label 'generate_if_else'
+%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:51:10: End label 'generate_if_else_bad' does not match begin label 'generate_if_else'
    51 |    end : generate_if_else_bad
       |          ^~~~~~~~~~~~~~~~~~~~
-%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:54:13: End label 't_bad' does not match begin label 't'
+%Error-ENDLABEL: t/t_hierarchy_identifier_bad.v:54:13: End label 't_bad' does not match begin label 't'
    54 | endmodule : t_bad
       |             ^~~~~
 %Error: Exiting due to

From 8291d8bcc1f91c8a83d5cabdb96751373d5e17af Mon Sep 17 00:00:00 2001
From: github action <action@example.com>
Date: Sat, 12 Nov 2022 17:10:41 +0000
Subject: [PATCH 030/156] Apply 'make format'

---
 src/V3Error.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/V3Error.h b/src/V3Error.h
index 1268136a2..f22107cd8 100644
--- a/src/V3Error.h
+++ b/src/V3Error.h
@@ -218,9 +218,9 @@ public:
     bool lintError() const VL_MT_SAFE {
         return (m_e == ALWCOMBORDER || m_e == BSSPACE || m_e == CASEINCOMPLETE
                 || m_e == CASEOVERLAP || m_e == CASEWITHX || m_e == CASEX || m_e == CASTCONST
-                || m_e == CMPCONST || m_e == COLONPLUS || m_e == IMPLICIT
-                || m_e == LATCH || m_e == LITENDIAN || m_e == PINMISSING || m_e == REALCVT
-                || m_e == UNSIGNED || m_e == WIDTH);
+                || m_e == CMPCONST || m_e == COLONPLUS || m_e == IMPLICIT || m_e == LATCH
+                || m_e == LITENDIAN || m_e == PINMISSING || m_e == REALCVT || m_e == UNSIGNED
+                || m_e == WIDTH);
     }
     // Warnings that are style only
     bool styleError() const VL_MT_SAFE {

From eaf09ba0e78e0f797130d08ab664325b22587728 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Sat, 12 Nov 2022 14:14:32 +0000
Subject: [PATCH 031/156] Dfg: resolve multi-driven signal ranges

In order to avoid unexpected breakage on multi-driven variables, we
resolve in DFG construction by using only the first driver encountered.
Also issues the MULTIDRIVEN error for these signals.
---
 src/V3DfgAstToDfg.cpp                        | 142 +++++++++++++++----
 test_regress/t/t_dfg_multidriver_dfg_bad.out |  39 +++++
 test_regress/t/t_dfg_multidriver_dfg_bad.pl  |  19 +++
 test_regress/t/t_dfg_multidriver_dfg_bad.v   |  23 +++
 test_regress/t/t_mem_multi_io3.v             |   2 +
 test_regress/t/t_param_type3.v               |  15 +-
 test_regress/t/t_unoptflat_simple_2.v        |   2 +
 test_regress/t/t_unoptflat_simple_2_bad.out  |  14 +-
 8 files changed, 211 insertions(+), 45 deletions(-)
 create mode 100644 test_regress/t/t_dfg_multidriver_dfg_bad.out
 create mode 100755 test_regress/t/t_dfg_multidriver_dfg_bad.pl
 create mode 100644 test_regress/t/t_dfg_multidriver_dfg_bad.v

diff --git a/src/V3DfgAstToDfg.cpp b/src/V3DfgAstToDfg.cpp
index b9445d674..a47f7262c 100644
--- a/src/V3DfgAstToDfg.cpp
+++ b/src/V3DfgAstToDfg.cpp
@@ -79,6 +79,18 @@ class AstToDfgVisitor final : public VNVisitor {
     // AstNode::user1p   // DfgVertex for this AstNode
     const VNUser1InUse m_user1InUse;
 
+    // TYPES
+    // Represents a driver during canonicalization
+    struct Driver {
+        FileLine* m_fileline;
+        DfgVertex* m_vtxp;
+        uint32_t m_lsb;
+        Driver(FileLine* flp, uint32_t lsb, DfgVertex* vtxp)
+            : m_fileline{flp}
+            , m_vtxp{vtxp}
+            , m_lsb{lsb} {}
+    };
+
     // STATE
 
     DfgGraph* const m_dfgp;  // The graph being built
@@ -259,6 +271,21 @@ class AstToDfgVisitor final : public VNVisitor {
         return true;
     }
 
+    // Sometime assignment ranges are coalesced by V3Const,
+    // so we unpack concatenations for better error reporting.
+    void addDriver(FileLine* flp, uint32_t lsb, DfgVertex* vtxp,
+                   std::vector<Driver>& drivers) const {
+        if (DfgConcat* const concatp = vtxp->cast<DfgConcat>()) {
+            DfgVertex* const rhsp = concatp->rhsp();
+            addDriver(rhsp->fileline(), lsb, rhsp, drivers);
+            DfgVertex* const lhsp = concatp->lhsp();
+            addDriver(lhsp->fileline(), lsb + rhsp->width(), lhsp, drivers);
+            concatp->unlinkDelete(*m_dfgp);
+        } else {
+            drivers.emplace_back(flp, lsb, vtxp);
+        }
+    }
+
     // Canonicalize packed variables
     void canonicalizePacked() {
         for (DfgVarPacked* const varp : m_varPackedps) {
@@ -270,29 +297,71 @@ class AstToDfgVisitor final : public VNVisitor {
             }
 
             // Gather (and unlink) all drivers
-            struct Driver {
-                FileLine* flp;
-                uint32_t lsb;
-                DfgVertex* vtxp;
-                Driver(FileLine* flp, uint32_t lsb, DfgVertex* vtxp)
-                    : flp{flp}
-                    , lsb{lsb}
-                    , vtxp{vtxp} {}
-            };
             std::vector<Driver> drivers;
             drivers.reserve(varp->arity());
-            varp->forEachSourceEdge([varp, &drivers](DfgEdge& edge, size_t idx) {
-                UASSERT(edge.sourcep(), "Should not have created undriven sources");
-                drivers.emplace_back(varp->driverFileLine(idx), varp->driverLsb(idx),
-                                     edge.sourcep());
+            varp->forEachSourceEdge([this, varp, &drivers](DfgEdge& edge, size_t idx) {
+                DfgVertex* const driverp = edge.sourcep();
+                UASSERT(driverp, "Should not have created undriven sources");
+                addDriver(varp->driverFileLine(idx), varp->driverLsb(idx), driverp, drivers);
                 edge.unlinkSource();
             });
 
-            // Sort drivers by LSB
-            std::stable_sort(drivers.begin(), drivers.end(),
-                             [](const Driver& a, const Driver& b) { return a.lsb < b.lsb; });
+            const auto cmp = [](const Driver& a, const Driver& b) {
+                if (a.m_lsb != b.m_lsb) return a.m_lsb < b.m_lsb;
+                return a.m_fileline->operatorCompare(*b.m_fileline) < 0;
+            };
 
-            // TODO: bail on multidriver
+            // Sort drivers by LSB
+            std::stable_sort(drivers.begin(), drivers.end(), cmp);
+
+            // Vertices that might have become unused due to multiple driver resolution. Having
+            // multiple drivers is an error and is hence assumed to be rare, so performance is
+            // not very important, set will suffice.
+            std::set<DfgVertex*> prune;
+
+            // Fix multiply driven ranges
+            for (auto it = drivers.begin(); it != drivers.end();) {
+                Driver& a = *it++;
+                const uint32_t aWidth = a.m_vtxp->width();
+                const uint32_t aEnd = a.m_lsb + aWidth;
+                while (it != drivers.end()) {
+                    Driver& b = *it;
+                    // If no overlap, then nothing to do
+                    if (b.m_lsb >= aEnd) break;
+
+                    const uint32_t bWidth = b.m_vtxp->width();
+                    const uint32_t bEnd = b.m_lsb + bWidth;
+                    const uint32_t overlapEnd = std::min(aEnd, bEnd) - 1;
+
+                    varp->varp()->v3warn(  //
+                        MULTIDRIVEN,
+                        "Bits ["  //
+                            << overlapEnd << ":" << b.m_lsb << "] of signal "
+                            << varp->varp()->prettyNameQ()
+                            << " have multiple combinational drivers\n"
+                            << a.m_fileline->warnOther() << "... Location of first driver\n"
+                            << a.m_fileline->warnContextPrimary() << '\n'
+                            << b.m_fileline->warnOther() << "... Location of other driver\n"
+                            << b.m_fileline->warnContextSecondary() << varp->varp()->warnOther()
+                            << "... Only the first driver will be respected");
+
+                    // If the first driver completely covers the range of the second driver,
+                    // we can just delete the second driver completely, otherwise adjust the
+                    // second driver to apply from the end of the range of the first driver.
+                    if (aEnd >= bEnd) {
+                        prune.emplace(b.m_vtxp);
+                        it = drivers.erase(it);
+                    } else {
+                        const auto dtypep = DfgVertex::dtypeForWidth(bEnd - aEnd);
+                        DfgSel* const selp = new DfgSel{*m_dfgp, b.m_vtxp->fileline(), dtypep};
+                        selp->fromp(b.m_vtxp);
+                        selp->lsb(aEnd - b.m_lsb);
+                        b.m_lsb = aEnd;
+                        b.m_vtxp = selp;
+                        std::stable_sort(it, drivers.end(), cmp);
+                    }
+                }
+            }
 
             // Coalesce adjacent ranges
             for (size_t i = 0, j = 1; j < drivers.size(); ++j) {
@@ -300,15 +369,15 @@ class AstToDfgVisitor final : public VNVisitor {
                 Driver& b = drivers[j];
 
                 // Coalesce adjacent range
-                const uint32_t aWidth = a.vtxp->width();
-                const uint32_t bWidth = b.vtxp->width();
-                if (a.lsb + aWidth == b.lsb) {
+                const uint32_t aWidth = a.m_vtxp->width();
+                const uint32_t bWidth = b.m_vtxp->width();
+                if (a.m_lsb + aWidth == b.m_lsb) {
                     const auto dtypep = DfgVertex::dtypeForWidth(aWidth + bWidth);
-                    DfgConcat* const concatp = new DfgConcat{*m_dfgp, a.flp, dtypep};
-                    concatp->rhsp(a.vtxp);
-                    concatp->lhsp(b.vtxp);
-                    a.vtxp = concatp;
-                    b.vtxp = nullptr;  // Mark as moved
+                    DfgConcat* const concatp = new DfgConcat{*m_dfgp, a.m_fileline, dtypep};
+                    concatp->rhsp(a.m_vtxp);
+                    concatp->lhsp(b.m_vtxp);
+                    a.m_vtxp = concatp;
+                    b.m_vtxp = nullptr;  // Mark as moved
                     ++m_ctx.m_coalescedAssignments;
                     continue;
                 }
@@ -318,17 +387,30 @@ class AstToDfgVisitor final : public VNVisitor {
                 // Compact non-adjacent ranges within the vector
                 if (j != i) {
                     Driver& c = drivers[i];
-                    UASSERT_OBJ(!c.vtxp, c.flp, "Should have been marked moved");
+                    UASSERT_OBJ(!c.m_vtxp, c.m_fileline, "Should have been marked moved");
                     c = b;
-                    b.vtxp = nullptr;  // Mark as moved
+                    b.m_vtxp = nullptr;  // Mark as moved
                 }
             }
 
-            // Reinsert sources in order
+            // Reinsert drivers in order
             varp->resetSources();
             for (const Driver& driver : drivers) {
-                if (!driver.vtxp) break;  // Stop at end of cmpacted list
-                varp->addDriver(driver.flp, driver.lsb, driver.vtxp);
+                if (!driver.m_vtxp) break;  // Stop at end of compacted list
+                varp->addDriver(driver.m_fileline, driver.m_lsb, driver.m_vtxp);
+            }
+
+            // Prune vertices potentially unused due to resolving multiple drivers.
+            while (!prune.empty()) {
+                // Pop last vertex
+                const auto it = prune.begin();
+                DfgVertex* const vtxp = *it;
+                prune.erase(it);
+                // If used (or a variable), then done
+                if (vtxp->hasSinks() || vtxp->is<DfgVertexVar>()) continue;
+                // If unused, then add sources to work list and delete
+                vtxp->forEachSource([&](DfgVertex& src) { prune.emplace(&src); });
+                vtxp->unlinkDelete(*m_dfgp);
             }
         }
     }
diff --git a/test_regress/t/t_dfg_multidriver_dfg_bad.out b/test_regress/t/t_dfg_multidriver_dfg_bad.out
new file mode 100644
index 000000000..ce36240b8
--- /dev/null
+++ b/test_regress/t/t_dfg_multidriver_dfg_bad.out
@@ -0,0 +1,39 @@
+%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:13:18: Bits [3:1] of signal 'a' have multiple combinational drivers
+                                                         : ... In instance t
+                      t/t_dfg_multidriver_dfg_bad.v:14:19: ... Location of first driver
+   14 |     assign a[3:0] = i[3:0];
+      |                   ^
+                      t/t_dfg_multidriver_dfg_bad.v:15:19: ... Location of other driver
+   15 |     assign a[4:1] = ~i[4:1];
+      |                   ^
+                      t/t_dfg_multidriver_dfg_bad.v:13:18: ... Only the first driver will be respected
+                      ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest
+                      ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message.
+%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:13:18: Bits [3:3] of signal 'a' have multiple combinational drivers
+                                                         : ... In instance t
+                      t/t_dfg_multidriver_dfg_bad.v:14:19: ... Location of first driver
+   14 |     assign a[3:0] = i[3:0];
+      |                   ^
+                      t/t_dfg_multidriver_dfg_bad.v:16:17: ... Location of other driver
+   16 |     assign a[3] = ~i[3];
+      |                 ^
+                      t/t_dfg_multidriver_dfg_bad.v:13:18: ... Only the first driver will be respected
+%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:13:18: Bits [7:6] of signal 'a' have multiple combinational drivers
+                                                         : ... In instance t
+                      t/t_dfg_multidriver_dfg_bad.v:17:19: ... Location of first driver
+   17 |     assign a[8:5] = i[8:5];
+      |                   ^
+                      t/t_dfg_multidriver_dfg_bad.v:18:19: ... Location of other driver
+   18 |     assign a[7:6] = ~i[7:6];
+      |                   ^
+                      t/t_dfg_multidriver_dfg_bad.v:13:18: ... Only the first driver will be respected
+%Warning-MULTIDRIVEN: t/t_dfg_multidriver_dfg_bad.v:13:18: Bits [9:9] of signal 'a' have multiple combinational drivers
+                                                         : ... In instance t
+                      t/t_dfg_multidriver_dfg_bad.v:19:17: ... Location of first driver
+   19 |     assign a[9] = i[9];
+      |                 ^
+                      t/t_dfg_multidriver_dfg_bad.v:20:19: ... Location of other driver
+   20 |     assign a[9] = ~i[9];
+      |                   ^
+                      t/t_dfg_multidriver_dfg_bad.v:13:18: ... Only the first driver will be respected
+%Error: Exiting due to
diff --git a/test_regress/t/t_dfg_multidriver_dfg_bad.pl b/test_regress/t/t_dfg_multidriver_dfg_bad.pl
new file mode 100755
index 000000000..eae347a52
--- /dev/null
+++ b/test_regress/t/t_dfg_multidriver_dfg_bad.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Geza Lore. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+);
+
+ok(1);
+1;
diff --git a/test_regress/t/t_dfg_multidriver_dfg_bad.v b/test_regress/t/t_dfg_multidriver_dfg_bad.v
new file mode 100644
index 000000000..724b33539
--- /dev/null
+++ b/test_regress/t/t_dfg_multidriver_dfg_bad.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Geza Lore.
+// SPDX-License-Identifier: CC0-1.0
+
+`default_nettype none
+
+module t(
+    input  wire [10:0] i,
+    output wire [10:0] o
+);
+    logic [10:0] a;
+    assign a[3:0] = i[3:0];
+    assign a[4:1] = ~i[4:1];
+    assign a[3] = ~i[3];
+    assign a[8:5] = i[8:5];
+    assign a[7:6] = ~i[7:6];
+    assign a[9] = i[9];
+    assign a[9] = ~i[9];
+    assign a[10] = i[10];
+    assign o = a;
+endmodule
diff --git a/test_regress/t/t_mem_multi_io3.v b/test_regress/t/t_mem_multi_io3.v
index 1e4d7434d..3a70d6e26 100644
--- a/test_regress/t/t_mem_multi_io3.v
+++ b/test_regress/t/t_mem_multi_io3.v
@@ -40,7 +40,9 @@ module testio
    input logic signed [3:0] [3:0] [8:0] arr3d_in,
    output logic signed [3:0] [35:0]     arr2d_out
    );
+   /* verilator lint_off MULTIDRIVEN */
    logic signed [3:0] [35:0]            ar2d_out_pre;
+   /* verilator lint_on MULTIDRIVEN */
 
    always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
    always_comb ar2d_out_pre[0][35:0] = {arr3d_in[0][0][8:0], arr3d_in[0][1][8:0], arr3d_in[0][2][8:0], arr3d_in[0][3][8:0]};
diff --git a/test_regress/t/t_param_type3.v b/test_regress/t/t_param_type3.v
index dca6bdc19..cbce4c24b 100644
--- a/test_regress/t/t_param_type3.v
+++ b/test_regress/t/t_param_type3.v
@@ -8,26 +8,25 @@ typedef logic T_t;
 
 module t (/*AUTOARG*/
    // Outputs
-   o, o2,
+   o, ob, o2, o2b,
    // Inputs
    i
    );
 
    input T_t i;
-   output T_t o;
-   output T_t o2;
+   output T_t o, ob, o2, o2b;
 
    sub1 #(.T_t(T_t), .CHECK(1))
-   sub1 (.i, .o);
+   sub1 (.i, .o(o));
 
    sub2 #(.T_t(T_t), .CHECK(2))
    sub2 (.i, .o(o2));
 
    sub1 #(T_t, 1)
-   sub1b (i, o);
+   sub1b (i, ob);
 
    sub2 #(T_t, 2)
-   sub2b (i, o2);
+   sub2b (i, o2b);
 
 endmodule
 
@@ -35,8 +34,8 @@ module sub1 (i,o);
    parameter type T_t = real;
    localparam type T2_t = T_t;
    parameter int CHECK = 0;
-   input  T_t i;
-   output T2_t o;
+   input         T_t i;
+   output        T2_t o;
    assign o = i;
    if (CHECK != 1) $error;
 endmodule
diff --git a/test_regress/t/t_unoptflat_simple_2.v b/test_regress/t/t_unoptflat_simple_2.v
index 549f69b43..b455b1469 100644
--- a/test_regress/t/t_unoptflat_simple_2.v
+++ b/test_regress/t/t_unoptflat_simple_2.v
@@ -12,7 +12,9 @@ module t (/*AUTOARG*/
    );
    input clk;
 
+   /* verilator lint_off MULTIDRIVEN */
    wire [2:0] x;
+   /* verilator lint_on MULTIDRIVEN */
 
    assign x[1:0] = { x[0], clk };
    assign x[2:1] = x[1:0];
diff --git a/test_regress/t/t_unoptflat_simple_2_bad.out b/test_regress/t/t_unoptflat_simple_2_bad.out
index 6ec899e69..be3386782 100644
--- a/test_regress/t/t_unoptflat_simple_2_bad.out
+++ b/test_regress/t/t_unoptflat_simple_2_bad.out
@@ -1,14 +1,14 @@
-%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:15:15: Signal unoptimizable: Circular combinational logic: 't.x'
-   15 |    wire [2:0] x;
+%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:16:15: Signal unoptimizable: Circular combinational logic: 't.x'
+   16 |    wire [2:0] x;
       |               ^
                     ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest
                     ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message.
-                    t/t_unoptflat_simple_2.v:15:15:      Example path: t.x
-                    t/t_unoptflat_simple_2.v:17:18:      Example path: ASSIGNW
-                    t/t_unoptflat_simple_2.v:15:15:      Example path: t.x
+                    t/t_unoptflat_simple_2.v:16:15:      Example path: t.x
+                    t/t_unoptflat_simple_2.v:13:10:      Example path: ASSIGNW
+                    t/t_unoptflat_simple_2.v:16:15:      Example path: t.x
                     ... Widest variables candidate to splitting:
-                        t/t_unoptflat_simple_2.v:15:15:  t.x, width 3, circular fanout 2, can split_var
+                        t/t_unoptflat_simple_2.v:16:15:  t.x, width 3, circular fanout 1, can split_var
                     ... Candidates with the highest fanout:
-                        t/t_unoptflat_simple_2.v:15:15:  t.x, width 3, circular fanout 2, can split_var
+                        t/t_unoptflat_simple_2.v:16:15:  t.x, width 3, circular fanout 1, can split_var
                     ... Suggest add /*verilator split_var*/ to appropriate variables above.
 %Error: Exiting due to

From 218dd4322bd1d297f0ab8986f941fe68c95371cf Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 12 Nov 2022 16:02:58 -0500
Subject: [PATCH 032/156] Fix C++11 warnings

---
 include/verilated.cpp         | 2 ++
 include/verilated_threads.h   | 2 +-
 include/verilated_trace_imp.h | 2 +-
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/verilated.cpp b/include/verilated.cpp
index 148c5b459..e88fc0c1b 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -2398,7 +2398,9 @@ void VerilatedContext::timeunit(int value) VL_MT_SAFE {
 }
 void VerilatedContext::timeprecision(int value) VL_MT_SAFE {
     if (value < 0) value = -value;  // Stored as 0..15
+#ifdef SYSTEMC_VERSION
     int sc_prec = 99;
+#endif
     {
         const VerilatedLockGuard lock{m_mutex};
         m_s.m_timeprecision = value;
diff --git a/include/verilated_threads.h b/include/verilated_threads.h
index 6100ac057..e4c2b9cc3 100644
--- a/include/verilated_threads.h
+++ b/include/verilated_threads.h
@@ -217,7 +217,7 @@ public:
     int numThreads() const { return m_workers.size(); }
     VlWorkerThread* workerp(int index) {
         assert(index >= 0);
-        assert(index < m_workers.size());
+        assert(static_cast<size_t>(index) < m_workers.size());
         return m_workers[index];
     }
 
diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h
index 7718ded13..c863649c6 100644
--- a/include/verilated_trace_imp.h
+++ b/include/verilated_trace_imp.h
@@ -616,7 +616,7 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::dump(uint64_t timeui) VL_MT_SAFE_EXCLUD
         *m_offloadBufferWritep++ = VerilatedTraceOffloadCommand::END;
 
         // Assert no buffer overflow
-        assert(m_offloadBufferWritep - bufferp <= m_offloadBufferSize);
+        assert(static_cast<size_t>(m_offloadBufferWritep - bufferp) <= m_offloadBufferSize);
 
         // Reset our pointers as we are giving up the buffer
         m_offloadBufferWritep = nullptr;

From 4f50073feb47ba4c60a8c006219815ae666a1c42 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 12 Nov 2022 19:51:03 -0500
Subject: [PATCH 033/156] Internals: Fix constructor style.

---
 src/V3AstNodeExpr.h  | 166 ++++++++++++++++++++++---------------------
 src/V3AstNodeOther.h |   8 +--
 src/V3GraphStream.h  |   8 +--
 src/V3Width.cpp      |   9 ++-
 src/verilog.y        |  11 +++
 5 files changed, 107 insertions(+), 95 deletions(-)

diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index b1260e062..93e59a566 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -802,7 +802,7 @@ public:
     // For parser, make only if non-null package
     static AstNodeExpr* newIfPkg(FileLine* fl, AstNode* packageOrClassp, AstNodeExpr* rhsp) {
         if (!packageOrClassp) return rhsp;
-        return new AstDot(fl, true, packageOrClassp, rhsp);
+        return new AstDot{fl, true, packageOrClassp, rhsp};
     }
     void dump(std::ostream& str) const override;
     bool colon() const { return m_colon; }
@@ -1703,7 +1703,7 @@ public:
     }
     ASTGEN_MEMBERS_AstBufIf1;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstBufIf1(this->fileline(), lhsp, rhsp);
+        return new AstBufIf1{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opBufIf1(lhs, rhs);
@@ -1731,7 +1731,7 @@ public:
         V3ERROR_NA;
     }
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstCastDynamic(this->fileline(), lhsp, rhsp);
+        return new AstCastDynamic{fileline(), lhsp, rhsp};
     }
     string emitVerilog() override { return "%f$cast(%r, %l)"; }
     string emitC() override { return "VL_DYNAMIC_CAST(%r, %l)"; }
@@ -1756,7 +1756,7 @@ public:
     }
     ASTGEN_MEMBERS_AstCompareNN;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstCompareNN(this->fileline(), lhsp, rhsp, m_ignoreCase);
+        return new AstCompareNN{fileline(), lhsp, rhsp, m_ignoreCase};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opCompareNN(lhs, rhs, m_ignoreCase);
@@ -1787,7 +1787,7 @@ public:
     }
     ASTGEN_MEMBERS_AstConcat;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstConcat(this->fileline(), lhsp, rhsp);
+        return new AstConcat{fileline(), lhsp, rhsp};
     }
     string emitVerilog() override { return "%f{%l, %k%r}"; }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -1810,7 +1810,7 @@ public:
     }
     ASTGEN_MEMBERS_AstConcatN;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstConcatN(this->fileline(), lhsp, rhsp);
+        return new AstConcatN{fileline(), lhsp, rhsp};
     }
     string emitVerilog() override { return "%f{%l, %k%r}"; }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -1833,7 +1833,7 @@ public:
     }
     ASTGEN_MEMBERS_AstDiv;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstDiv(this->fileline(), lhsp, rhsp);
+        return new AstDiv{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opDiv(lhs, rhs);
@@ -1855,7 +1855,7 @@ public:
     }
     ASTGEN_MEMBERS_AstDivD;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstDivD(this->fileline(), lhsp, rhsp);
+        return new AstDivD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opDivD(lhs, rhs);
@@ -1879,7 +1879,7 @@ public:
     }
     ASTGEN_MEMBERS_AstDivS;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstDivS(this->fileline(), lhsp, rhsp);
+        return new AstDivS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opDivS(lhs, rhs);
@@ -1903,7 +1903,7 @@ public:
     }
     ASTGEN_MEMBERS_AstEqWild;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstEqWild(this->fileline(), lhsp, rhsp);
+        return new AstEqWild{fileline(), lhsp, rhsp};
     }
     static AstNodeBiop* newTyped(FileLine* fl, AstNode* lhsp,
                                  AstNode* rhsp);  // Return AstEqWild/AstEqD
@@ -1925,7 +1925,7 @@ public:
         : ASTGEN_SUPER_FGetS(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstFGetS;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstFGetS(this->fileline(), lhsp, rhsp);
+        return new AstFGetS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         V3ERROR_NA;
@@ -1953,7 +1953,7 @@ public:
         V3ERROR_NA;
     }
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstFUngetC(this->fileline(), lhsp, rhsp);
+        return new AstFUngetC{fileline(), lhsp, rhsp};
     }
     string emitVerilog() override { return "%f$ungetc(%r, %l)"; }
     // Non-existent filehandle returns EOF
@@ -1979,7 +1979,7 @@ public:
     }
     ASTGEN_MEMBERS_AstGetcN;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstGetcN(this->fileline(), lhsp, rhsp);
+        return new AstGetcN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opGetcN(lhs, rhs);
@@ -2004,7 +2004,7 @@ public:
     }
     ASTGEN_MEMBERS_AstGetcRefN;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstGetcRefN(this->fileline(), lhsp, rhsp);
+        return new AstGetcRefN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         V3ERROR_NA;
@@ -2026,7 +2026,7 @@ public:
     }
     ASTGEN_MEMBERS_AstGt;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstGt(this->fileline(), lhsp, rhsp);
+        return new AstGt{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opGt(lhs, rhs);
@@ -2048,7 +2048,7 @@ public:
     }
     ASTGEN_MEMBERS_AstGtD;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstGtD(this->fileline(), lhsp, rhsp);
+        return new AstGtD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opGtD(lhs, rhs);
@@ -2072,7 +2072,7 @@ public:
     }
     ASTGEN_MEMBERS_AstGtN;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstGtN(this->fileline(), lhsp, rhsp);
+        return new AstGtN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opGtN(lhs, rhs);
@@ -2096,7 +2096,7 @@ public:
     }
     ASTGEN_MEMBERS_AstGtS;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstGtS(this->fileline(), lhsp, rhsp);
+        return new AstGtS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opGtS(lhs, rhs);
@@ -2119,7 +2119,7 @@ public:
     }
     ASTGEN_MEMBERS_AstGte;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstGte(this->fileline(), lhsp, rhsp);
+        return new AstGte{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opGte(lhs, rhs);
@@ -2141,7 +2141,7 @@ public:
     }
     ASTGEN_MEMBERS_AstGteD;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstGteD(this->fileline(), lhsp, rhsp);
+        return new AstGteD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opGteD(lhs, rhs);
@@ -2165,7 +2165,7 @@ public:
     }
     ASTGEN_MEMBERS_AstGteN;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstGteN(this->fileline(), lhsp, rhsp);
+        return new AstGteN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opGteN(lhs, rhs);
@@ -2189,7 +2189,7 @@ public:
     }
     ASTGEN_MEMBERS_AstGteS;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstGteS(this->fileline(), lhsp, rhsp);
+        return new AstGteS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opGteS(lhs, rhs);
@@ -2212,7 +2212,7 @@ public:
     }
     ASTGEN_MEMBERS_AstLogAnd;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstLogAnd(this->fileline(), lhsp, rhsp);
+        return new AstLogAnd{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opLogAnd(lhs, rhs);
@@ -2235,7 +2235,7 @@ public:
     }
     ASTGEN_MEMBERS_AstLogIf;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstLogIf(this->fileline(), lhsp, rhsp);
+        return new AstLogIf{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opLogIf(lhs, rhs);
@@ -2263,7 +2263,7 @@ public:
     }
     ASTGEN_MEMBERS_AstLogOr;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstLogOr(this->fileline(), lhsp, rhsp);
+        return new AstLogOr{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opLogOr(lhs, rhs);
@@ -2294,7 +2294,7 @@ public:
     }
     ASTGEN_MEMBERS_AstLt;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstLt(this->fileline(), lhsp, rhsp);
+        return new AstLt{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opLt(lhs, rhs);
@@ -2316,7 +2316,7 @@ public:
     }
     ASTGEN_MEMBERS_AstLtD;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstLtD(this->fileline(), lhsp, rhsp);
+        return new AstLtD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opLtD(lhs, rhs);
@@ -2340,7 +2340,7 @@ public:
     }
     ASTGEN_MEMBERS_AstLtN;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstLtN(this->fileline(), lhsp, rhsp);
+        return new AstLtN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opLtN(lhs, rhs);
@@ -2364,7 +2364,7 @@ public:
     }
     ASTGEN_MEMBERS_AstLtS;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstLtS(this->fileline(), lhsp, rhsp);
+        return new AstLtS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opLtS(lhs, rhs);
@@ -2387,7 +2387,7 @@ public:
     }
     ASTGEN_MEMBERS_AstLte;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstLte(this->fileline(), lhsp, rhsp);
+        return new AstLte{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opLte(lhs, rhs);
@@ -2409,7 +2409,7 @@ public:
     }
     ASTGEN_MEMBERS_AstLteD;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstLteD(this->fileline(), lhsp, rhsp);
+        return new AstLteD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opLteD(lhs, rhs);
@@ -2433,7 +2433,7 @@ public:
     }
     ASTGEN_MEMBERS_AstLteN;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstLteN(this->fileline(), lhsp, rhsp);
+        return new AstLteN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opLteN(lhs, rhs);
@@ -2457,7 +2457,7 @@ public:
     }
     ASTGEN_MEMBERS_AstLteS;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstLteS(this->fileline(), lhsp, rhsp);
+        return new AstLteS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opLteS(lhs, rhs);
@@ -2480,7 +2480,7 @@ public:
     }
     ASTGEN_MEMBERS_AstModDiv;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstModDiv(this->fileline(), lhsp, rhsp);
+        return new AstModDiv{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opModDiv(lhs, rhs);
@@ -2502,7 +2502,7 @@ public:
     }
     ASTGEN_MEMBERS_AstModDivS;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstModDivS(this->fileline(), lhsp, rhsp);
+        return new AstModDivS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opModDivS(lhs, rhs);
@@ -2525,7 +2525,7 @@ public:
     }
     ASTGEN_MEMBERS_AstNeqWild;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstNeqWild(this->fileline(), lhsp, rhsp);
+        return new AstNeqWild{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opWildNeq(lhs, rhs);
@@ -2547,7 +2547,7 @@ public:
     }
     ASTGEN_MEMBERS_AstPow;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstPow(this->fileline(), lhsp, rhsp);
+        return new AstPow{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opPow(lhs, rhs);
@@ -2570,7 +2570,7 @@ public:
     }
     ASTGEN_MEMBERS_AstPowD;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstPowD(this->fileline(), lhsp, rhsp);
+        return new AstPowD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opPowD(lhs, rhs);
@@ -2593,7 +2593,7 @@ public:
     }
     ASTGEN_MEMBERS_AstPowSS;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstPowSS(this->fileline(), lhsp, rhsp);
+        return new AstPowSS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opPowSS(lhs, rhs);
@@ -2617,7 +2617,7 @@ public:
     }
     ASTGEN_MEMBERS_AstPowSU;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstPowSU(this->fileline(), lhsp, rhsp);
+        return new AstPowSU{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opPowSU(lhs, rhs);
@@ -2641,7 +2641,7 @@ public:
     }
     ASTGEN_MEMBERS_AstPowUS;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstPowUS(this->fileline(), lhsp, rhsp);
+        return new AstPowUS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opPowUS(lhs, rhs);
@@ -2672,10 +2672,10 @@ public:
         }
     }
     AstReplicate(FileLine* fl, AstNode* lhsp, uint32_t repCount)
-        : AstReplicate(fl, lhsp, new AstConst(fl, repCount)) {}
+        : AstReplicate{fl, lhsp, new AstConst{fl, repCount}} {}
     ASTGEN_MEMBERS_AstReplicate;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstReplicate(this->fileline(), lhsp, rhsp);
+        return new AstReplicate{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opRepl(lhs, rhs);
@@ -2697,10 +2697,10 @@ public:
         dtypeSetString();
     }
     AstReplicateN(FileLine* fl, AstNode* lhsp, uint32_t repCount)
-        : AstReplicateN(fl, lhsp, new AstConst(fl, repCount)) {}
+        : AstReplicateN{fl, lhsp, new AstConst{fl, repCount}} {}
     ASTGEN_MEMBERS_AstReplicateN;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstReplicateN(this->fileline(), lhsp, rhsp);
+        return new AstReplicateN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opReplN(lhs, rhs);
@@ -2723,7 +2723,7 @@ public:
     }
     ASTGEN_MEMBERS_AstShiftL;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstShiftL(this->fileline(), lhsp, rhsp);
+        return new AstShiftL{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opShiftL(lhs, rhs);
@@ -2747,7 +2747,7 @@ public:
     }
     ASTGEN_MEMBERS_AstShiftR;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstShiftR(this->fileline(), lhsp, rhsp);
+        return new AstShiftR{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opShiftR(lhs, rhs);
@@ -2775,7 +2775,7 @@ public:
     }
     ASTGEN_MEMBERS_AstShiftRS;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstShiftRS(this->fileline(), lhsp, rhsp);
+        return new AstShiftRS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opShiftRS(lhs, rhs, lhsp()->widthMinV());
@@ -2798,7 +2798,7 @@ public:
     }
     ASTGEN_MEMBERS_AstSub;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstSub(this->fileline(), lhsp, rhsp);
+        return new AstSub{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opSub(lhs, rhs);
@@ -2820,7 +2820,7 @@ public:
     }
     ASTGEN_MEMBERS_AstSubD;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstSubD(this->fileline(), lhsp, rhsp);
+        return new AstSubD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opSubD(lhs, rhs);
@@ -2845,7 +2845,7 @@ public:
     }
     ASTGEN_MEMBERS_AstURandomRange;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstURandomRange(fileline(), lhsp, rhsp);
+        return new AstURandomRange{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         V3ERROR_NA;
@@ -2871,7 +2871,7 @@ public:
     }
     ASTGEN_MEMBERS_AstEq;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstEq(this->fileline(), lhsp, rhsp);
+        return new AstEq{fileline(), lhsp, rhsp};
     }
     static AstNodeBiop* newTyped(FileLine* fl, AstNode* lhsp,
                                  AstNode* rhsp);  // Return AstEq/AstEqD
@@ -2895,7 +2895,7 @@ public:
     }
     ASTGEN_MEMBERS_AstEqCase;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstEqCase(this->fileline(), lhsp, rhsp);
+        return new AstEqCase{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opCaseEq(lhs, rhs);
@@ -2917,7 +2917,7 @@ public:
     }
     ASTGEN_MEMBERS_AstEqD;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstEqD(this->fileline(), lhsp, rhsp);
+        return new AstEqD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opEqD(lhs, rhs);
@@ -2941,7 +2941,7 @@ public:
     }
     ASTGEN_MEMBERS_AstEqN;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstEqN(this->fileline(), lhsp, rhsp);
+        return new AstEqN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opEqN(lhs, rhs);
@@ -2965,7 +2965,7 @@ public:
     }
     ASTGEN_MEMBERS_AstLogEq;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstLogEq(this->fileline(), lhsp, rhsp);
+        return new AstLogEq{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opLogEq(lhs, rhs);
@@ -2988,7 +2988,7 @@ public:
     }
     ASTGEN_MEMBERS_AstNeq;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstNeq(this->fileline(), lhsp, rhsp);
+        return new AstNeq{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opNeq(lhs, rhs);
@@ -3010,7 +3010,7 @@ public:
     }
     ASTGEN_MEMBERS_AstNeqCase;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstNeqCase(this->fileline(), lhsp, rhsp);
+        return new AstNeqCase{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opCaseNeq(lhs, rhs);
@@ -3032,7 +3032,7 @@ public:
     }
     ASTGEN_MEMBERS_AstNeqD;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstNeqD(this->fileline(), lhsp, rhsp);
+        return new AstNeqD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opNeqD(lhs, rhs);
@@ -3056,7 +3056,7 @@ public:
     }
     ASTGEN_MEMBERS_AstNeqN;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstNeqN(this->fileline(), lhsp, rhsp);
+        return new AstNeqN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opNeqN(lhs, rhs);
@@ -3082,7 +3082,7 @@ public:
     }
     ASTGEN_MEMBERS_AstAdd;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstAdd(this->fileline(), lhsp, rhsp);
+        return new AstAdd{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opAdd(lhs, rhs);
@@ -3104,7 +3104,7 @@ public:
     }
     ASTGEN_MEMBERS_AstAddD;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstAddD(this->fileline(), lhsp, rhsp);
+        return new AstAddD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opAddD(lhs, rhs);
@@ -3128,7 +3128,7 @@ public:
     }
     ASTGEN_MEMBERS_AstAnd;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstAnd(this->fileline(), lhsp, rhsp);
+        return new AstAnd{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opAnd(lhs, rhs);
@@ -3150,7 +3150,7 @@ public:
     }
     ASTGEN_MEMBERS_AstMul;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstMul(this->fileline(), lhsp, rhsp);
+        return new AstMul{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opMul(lhs, rhs);
@@ -3173,7 +3173,7 @@ public:
     }
     ASTGEN_MEMBERS_AstMulD;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstMulD(this->fileline(), lhsp, rhsp);
+        return new AstMulD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opMulD(lhs, rhs);
@@ -3197,7 +3197,7 @@ public:
     }
     ASTGEN_MEMBERS_AstMulS;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstMulS(this->fileline(), lhsp, rhsp);
+        return new AstMulS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opMulS(lhs, rhs);
@@ -3222,7 +3222,7 @@ public:
     }
     ASTGEN_MEMBERS_AstOr;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstOr(this->fileline(), lhsp, rhsp);
+        return new AstOr{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opOr(lhs, rhs);
@@ -3244,7 +3244,7 @@ public:
     }
     ASTGEN_MEMBERS_AstXor;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstXor(this->fileline(), lhsp, rhsp);
+        return new AstXor{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opXor(lhs, rhs);
@@ -3274,12 +3274,12 @@ public:
         init(fromp);
     }
     AstArraySel(FileLine* fl, AstNode* fromp, int bit)
-        : ASTGEN_SUPER_ArraySel(fl, fromp, new AstConst(fl, bit)) {
+        : ASTGEN_SUPER_ArraySel(fl, fromp, new AstConst(fl, bit)) {  // Need () constructor
         init(fromp);
     }
     ASTGEN_MEMBERS_AstArraySel;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstArraySel(this->fileline(), lhsp, rhsp);
+        return new AstArraySel{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         V3ERROR_NA; /* How can from be a const? */
@@ -3314,7 +3314,7 @@ public:
     }
     ASTGEN_MEMBERS_AstAssocSel;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstAssocSel(this->fileline(), lhsp, rhsp);
+        return new AstAssocSel{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         V3ERROR_NA;
@@ -3346,7 +3346,7 @@ public:
     }
     ASTGEN_MEMBERS_AstWildcardSel;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstWildcardSel{this->fileline(), lhsp, rhsp};
+        return new AstWildcardSel{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         V3ERROR_NA;
@@ -3372,7 +3372,7 @@ public:
     }
     ASTGEN_MEMBERS_AstWordSel;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstWordSel(this->fileline(), lhsp, rhsp);
+        return new AstWordSel{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& from, const V3Number& bit) override {
         V3ERROR_NA;
@@ -3397,7 +3397,7 @@ public:
         : ASTGEN_SUPER_StreamL(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstStreamL;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstStreamL(this->fileline(), lhsp, rhsp);
+        return new AstStreamL{fileline(), lhsp, rhsp};
     }
     string emitVerilog() override { return "%f{ << %r %k{%l} }"; }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3418,7 +3418,7 @@ public:
         : ASTGEN_SUPER_StreamR(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstStreamR;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstStreamR(this->fileline(), lhsp, rhsp);
+        return new AstStreamR{fileline(), lhsp, rhsp};
     }
     string emitVerilog() override { return "%f{ >> %r %k{%l} }"; }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3440,7 +3440,7 @@ public:
         : ASTGEN_SUPER_Atan2D(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstAtan2D;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstAtan2D(this->fileline(), lhsp, rhsp);
+        return new AstAtan2D{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.setDouble(std::atan2(lhs.toDouble(), rhs.toDouble()));
@@ -3454,7 +3454,7 @@ public:
         : ASTGEN_SUPER_HypotD(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstHypotD;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstHypotD(this->fileline(), lhsp, rhsp);
+        return new AstHypotD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.setDouble(std::hypot(lhs.toDouble(), rhs.toDouble()));
@@ -3810,7 +3810,8 @@ public:
         }
     }
     AstSel(FileLine* fl, AstNode* fromp, int lsb, int bitwidth)
-        : ASTGEN_SUPER_Sel(fl, fromp, new AstConst(fl, lsb), new AstConst(fl, bitwidth))
+        : ASTGEN_SUPER_Sel(fl, fromp, new AstConst(fl, lsb),  // Need () constructor
+                           new AstConst(fl, bitwidth))  // Need () constructor
         , m_declElWidth{1} {
         dtypeSetLogicSized(bitwidth, VSigning::UNSIGNED);
     }
@@ -3850,8 +3851,9 @@ class AstSliceSel final : public AstNodeTriop {
     VNumRange m_declRange;  // Range of the 'from' array if isRanged() is set, else invalid
 public:
     AstSliceSel(FileLine* fl, AstNode* fromp, const VNumRange& declRange)
-        : ASTGEN_SUPER_SliceSel(fl, fromp, new AstConst(fl, declRange.lo()),
-                                new AstConst(fl, declRange.elements()))
+        : ASTGEN_SUPER_SliceSel(fl, fromp,
+                                new AstConst(fl, declRange.lo()),  // Need () constructor
+                                new AstConst(fl, declRange.elements()))  // Need () constructor
         , m_declRange{declRange} {}
     ASTGEN_MEMBERS_AstSliceSel;
     void dump(std::ostream& str) const override;
@@ -3908,7 +3910,7 @@ public:
         : ASTGEN_SUPER_Cond(fl, condp, thenp, elsep) {}
     ASTGEN_MEMBERS_AstCond;
     AstNode* cloneType(AstNode* condp, AstNode* thenp, AstNode* elsep) override {
-        return new AstCond(this->fileline(), condp, thenp, elsep);
+        return new AstCond{fileline(), condp, thenp, elsep};
     }
 };
 class AstCondBound final : public AstNodeCond {
@@ -3918,7 +3920,7 @@ public:
         : ASTGEN_SUPER_CondBound(fl, condp, thenp, elsep) {}
     ASTGEN_MEMBERS_AstCondBound;
     AstNode* cloneType(AstNode* condp, AstNode* thenp, AstNode* elsep) override {
-        return new AstCondBound(this->fileline(), condp, thenp, elsep);
+        return new AstCondBound{fileline(), condp, thenp, elsep};
     }
 };
 
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index 9b52144fe..a3c741ce8 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -3411,7 +3411,7 @@ public:
         : ASTGEN_SUPER_AssignForce(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstAssignForce;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstAssignForce{this->fileline(), lhsp, rhsp};
+        return new AstAssignForce{fileline(), lhsp, rhsp};
     }
     bool brokeLhsMustBeLvalue() const override { return true; }
 };
@@ -3422,7 +3422,7 @@ public:
         : ASTGEN_SUPER_AssignPost(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstAssignPost;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstAssignPost(this->fileline(), lhsp, rhsp);
+        return new AstAssignPost{fileline(), lhsp, rhsp};
     }
     bool brokeLhsMustBeLvalue() const override { return true; }
 };
@@ -3433,7 +3433,7 @@ public:
         : ASTGEN_SUPER_AssignPre(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstAssignPre;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstAssignPre(this->fileline(), lhsp, rhsp);
+        return new AstAssignPre{fileline(), lhsp, rhsp};
     }
     bool brokeLhsMustBeLvalue() const override { return true; }
 };
@@ -3446,7 +3446,7 @@ public:
     }
     ASTGEN_MEMBERS_AstAssignVarScope;
     AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
-        return new AstAssignVarScope(this->fileline(), lhsp, rhsp);
+        return new AstAssignVarScope{fileline(), lhsp, rhsp};
     }
     bool brokeLhsMustBeLvalue() const override { return false; }
 };
diff --git a/src/V3GraphStream.h b/src/V3GraphStream.h
index 5c53f0a0f..2c1a50545 100644
--- a/src/V3GraphStream.h
+++ b/src/V3GraphStream.h
@@ -110,26 +110,26 @@ public:
             // Every vertex initially is waiting, or ready.
             if (way == GraphWay::FORWARD) {
                 if (vxp->inEmpty()) {
-                    const VxHolder newVx(vxp, pos++, 0);
+                    const VxHolder newVx{vxp, pos++, 0};
                     m_readyVertices.insert(newVx);
                 } else {
                     uint32_t depCount = 0;
                     for (V3GraphEdge* depp = vxp->inBeginp(); depp; depp = depp->inNextp()) {
                         ++depCount;
                     }
-                    const VxHolder newVx(vxp, pos++, depCount);
+                    const VxHolder newVx{vxp, pos++, depCount};
                     m_waitingVertices.emplace(vxp, newVx);
                 }
             } else {  // REVERSE
                 if (vxp->outEmpty()) {
-                    const VxHolder newVx(vxp, pos++, 0);
+                    const VxHolder newVx{vxp, pos++, 0};
                     m_readyVertices.insert(newVx);
                 } else {
                     uint32_t depCount = 0;
                     for (V3GraphEdge* depp = vxp->outBeginp(); depp; depp = depp->outNextp()) {
                         ++depCount;
                     }
-                    const VxHolder newVx(vxp, pos++, depCount);
+                    const VxHolder newVx{vxp, pos++, depCount};
                     m_waitingVertices.emplace(vxp, newVx);
                 }
             }
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index d3d9ce430..d0c2c9d03 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1765,7 +1765,7 @@ private:
                 const int selwidth = V3Number::log2b(maxval) + 1;  // Width to address a bit
                 AstVar* const varp
                     = enumVarp(enumDtp, VAttrType::ENUM_VALID, false, (1ULL << selwidth) - 1);
-                FileLine* const fl_nowarn = new FileLine(fl);
+                FileLine* const fl_nowarn = new FileLine{fl};
                 fl_nowarn->warnOff(V3ErrorCode::WIDTH, true);
                 testp = new AstCond{
                     fl,
@@ -1780,8 +1780,8 @@ private:
                                new AstExprStmt{fl,
                                                new AstAssign{fl, nodep->top()->unlinkFrBack(),
                                                              nodep->fromp()->unlinkFrBack()},
-                                               new AstConst{fl, AstConst::Signed32(), 1}},
-                               new AstConst{fl, AstConst::Signed32(), 0}};
+                                               new AstConst{fl, AstConst::Signed32{}, 1}},
+                               new AstConst{fl, AstConst::Signed32{}, 0}};
         } else if (castable == COMPATIBLE) {
             nodep->v3warn(CASTCONST, "$cast will always return one as "
                                          << toDtp->prettyDTypeNameQ()
@@ -1792,7 +1792,7 @@ private:
                 fl,
                 new AstAssign{fl, nodep->top()->unlinkFrBack(),
                               new AstCast{fl, nodep->fromp()->unlinkFrBack(), toDtp}},
-                new AstConst{fl, AstConst::Signed32(), 1}};
+                new AstConst{fl, AstConst::Signed32{}, 1}};
         } else if (castable == INCOMPATIBLE) {
             newp = new AstConst{fl, 0};
             nodep->v3warn(CASTCONST, "$cast will always return zero as "
@@ -2735,7 +2735,6 @@ private:
     void methodCallEnum(AstMethodCall* nodep, AstEnumDType* adtypep) {
         // Method call on enum without following parenthesis, e.g. "ENUM.next"
         // Convert this into a method call, and let that visitor figure out what to do next
-        if (adtypep) {}
         if (nodep->name() == "num"  //
             || nodep->name() == "first"  //
             || nodep->name() == "last") {
diff --git a/src/verilog.y b/src/verilog.y
index 5e112eae8..846fde896 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1086,6 +1086,17 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
 //  Blank lines for type insertion
 //  Blank lines for type insertion
 //  Blank lines for type insertion
+//  Blank lines for type insertion
+//  Blank lines for type insertion
+//  Blank lines for type insertion
+//  Blank lines for type insertion
+//  Blank lines for type insertion
+//  Blank lines for type insertion
+//  Blank lines for type insertion
+//  Blank lines for type insertion
+//  Blank lines for type insertion
+//  Blank lines for type insertion
+//  Blank lines for type insertion
 
 %start source_text
 

From d25834e57b77fd9712628143646ddd82a8de3c1d Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 12 Nov 2022 20:11:05 -0500
Subject: [PATCH 034/156] Add ENUMVALUE warning when value misused for enum
 (#726).

---
 Changes                            |  1 +
 docs/guide/warnings.rst            | 34 ++++++++++++++++++
 src/V3Error.h                      |  3 +-
 src/V3Width.cpp                    | 56 ++++++++++++++++++++++--------
 test_regress/t/t_enum_type_bad.out | 17 +++++++++
 test_regress/t/t_enum_type_bad.pl  |  3 +-
 test_regress/t/t_enum_type_bad.v   |  1 +
 7 files changed, 99 insertions(+), 16 deletions(-)
 create mode 100644 test_regress/t/t_enum_type_bad.out

diff --git a/Changes b/Changes
index 13e49197e..96b17667d 100644
--- a/Changes
+++ b/Changes
@@ -16,6 +16,7 @@ Verilator 5.003 devel
 * Deprecate --no-threads; use --threads 1 for single threaded (#3703). [Kamil Rakoczy, Antmicro Ltd]
 * Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd]
 * Support randcase.
+* Add ENUMVALUE warning when value misused for enum (#726).
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Change ENDLABEL from warning into an error.
 * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst
index 3a5f625de..b91ed900a 100644
--- a/docs/guide/warnings.rst
+++ b/docs/guide/warnings.rst
@@ -572,6 +572,40 @@ List Of Warnings
    missing."
 
 
+.. option:: ENUMVALUE
+
+   Error that an enum data type value is being assigned from another data
+   type that is not implicitly assignment compatible with that enumerated
+   type.  This error is required by IEEE, but it may be disabled.
+
+   Faulty example:
+
+   .. code-block:: sv
+      :linenos:
+      :emphasize-lines: 2
+
+         typedef enum { ZERO } e_t;
+         initial e_t en = 0;  //<--- Warning
+
+   The ideal repair is to use the enumeration value's mnemonic:
+
+   .. code-block:: sv
+      :linenos:
+      :emphasize-lines: 2
+
+         typedef enum { ZERO } e_t;
+         initial e_t en = ZERO;  //<--- Repaired
+
+   Or, alternatively use a static cast:
+
+   .. code-block:: sv
+      :linenos:
+      :emphasize-lines: 2
+
+         typedef enum { ZERO } e_t;
+         initial e_t en = e_t'(0);  //<--- Repaired
+
+
 .. option:: EOFNEWLINE
 
    Warns that a file does not end in a newline.  POSIX defines that a line
diff --git a/src/V3Error.h b/src/V3Error.h
index f22107cd8..47e222dd7 100644
--- a/src/V3Error.h
+++ b/src/V3Error.h
@@ -56,6 +56,7 @@ public:
         I_TIMING,       // Enable timing from /*verilator timing_on/off*/
         // Error codes:
         E_ENCAPSULATED, // Error: local/protected violation
+        E_ENUMVALUE,    // Error: enum type needs explicit cast
         E_PORTSHORT,    // Error: Output port is connected to a constant, electrical short
         E_UNSUPPORTED,  // Error: Unsupported (generally)
         E_TASKNSVAR,    // Error: Task I/O not simple
@@ -169,7 +170,7 @@ public:
             // Boolean
             " I_CELLDEFINE", " I_COVERAGE", " I_TRACING", " I_LINT", " I_UNUSED", " I_DEF_NETTYPE_WIRE", " I_TIMING",
             // Errors
-            "ENCAPSULATED", "PORTSHORT", "UNSUPPORTED", "TASKNSVAR", "NEEDTIMINGOPT", "NOTIMING",
+            "ENCAPSULATED", "ENUMVALUE", "PORTSHORT", "UNSUPPORTED", "TASKNSVAR", "NEEDTIMINGOPT", "NOTIMING",
             // Warnings
             " EC_FIRST_WARN",
             "ALWCOMBORDER", "ASSIGNDLY", "ASSIGNIN", "BADSTDPRAGMA",
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index d0c2c9d03..1b8db1311 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -216,6 +216,7 @@ private:
     // STATE
     WidthVP* m_vup = nullptr;  // Current node state
     const AstCell* m_cellp = nullptr;  // Current cell for arrayed instantiations
+    const AstEnumItem* m_enumItemp = nullptr;  // Current enum item
     const AstNodeFTask* m_ftaskp = nullptr;  // Current function/task
     const AstNodeProcedure* m_procedurep = nullptr;  // Current final/always
     const AstWith* m_withp = nullptr;  // Current 'with' statement
@@ -468,7 +469,10 @@ private:
             //  the size of this subexpression only.
             // Second call (final()) m_vup->width() is probably the expression size, so
             //  the expression includes the size of the output too.
-            if (nodep->thenp()->isDouble() || nodep->elsep()->isDouble()) {
+            if (nodep->thenp()->dtypep()->skipRefp() == nodep->elsep()->dtypep()->skipRefp()) {
+                // TODO might need a broader equation, use the Castable function?
+                nodep->dtypeFrom(nodep->thenp()->dtypep());
+            } else if (nodep->thenp()->isDouble() || nodep->elsep()->isDouble()) {
                 nodep->dtypeSetDouble();
             } else if (nodep->thenp()->isString() || nodep->elsep()->isString()) {
                 nodep->dtypeSetString();
@@ -1757,31 +1761,34 @@ private:
             const uint64_t maxval = enumMaxValue(nodep, enumDtp);
             const bool assoc = maxval > ENUM_LOOKUP_BITS;
             AstNode* testp = nullptr;
+            FileLine* const fl_novalue = new FileLine{fl};
+            fl_novalue->warnOff(V3ErrorCode::E_ENUMVALUE, true);
             if (assoc) {
                 AstVar* const varp = enumVarp(enumDtp, VAttrType::ENUM_VALID, true, 0);
-                testp = new AstAssocSel{fl, newVarRefDollarUnit(varp),
+                testp = new AstAssocSel{fl_novalue, newVarRefDollarUnit(varp),
                                         nodep->fromp()->cloneTree(false)};
             } else {
                 const int selwidth = V3Number::log2b(maxval) + 1;  // Width to address a bit
                 AstVar* const varp
                     = enumVarp(enumDtp, VAttrType::ENUM_VALID, false, (1ULL << selwidth) - 1);
-                FileLine* const fl_nowarn = new FileLine{fl};
-                fl_nowarn->warnOff(V3ErrorCode::WIDTH, true);
+                FileLine* const fl_nowidth = new FileLine{fl};
+                fl_nowidth->warnOff(V3ErrorCode::WIDTH, true);
                 testp = new AstCond{
                     fl,
-                    new AstGt{fl_nowarn, nodep->fromp()->cloneTree(false),
-                              new AstConst{fl_nowarn, AstConst::Unsized64{}, maxval}},
+                    new AstGt{fl_nowidth, nodep->fromp()->cloneTree(false),
+                              new AstConst{fl_nowidth, AstConst::Unsized64{}, maxval}},
                     new AstConst{fl, AstConst::BitFalse{}},
                     new AstArraySel{
                         fl, newVarRefDollarUnit(varp),
-                        new AstSel{fl, nodep->fromp()->cloneTree(false), 0, selwidth}}};
+                        new AstSel{fl_novalue, nodep->fromp()->cloneTree(false), 0, selwidth}}};
             }
-            newp = new AstCond{fl, testp,
-                               new AstExprStmt{fl,
-                                               new AstAssign{fl, nodep->top()->unlinkFrBack(),
-                                                             nodep->fromp()->unlinkFrBack()},
-                                               new AstConst{fl, AstConst::Signed32{}, 1}},
-                               new AstConst{fl, AstConst::Signed32{}, 0}};
+            newp = new AstCond{
+                fl, testp,
+                new AstExprStmt{fl,
+                                new AstAssign{fl_novalue, nodep->top()->unlinkFrBack(),
+                                              nodep->fromp()->unlinkFrBack()},
+                                new AstConst{fl, AstConst::Signed32{}, 1}},
+                new AstConst{fl, AstConst::Signed32{}, 0}};
         } else if (castable == COMPATIBLE) {
             nodep->v3warn(CASTCONST, "$cast will always return one as "
                                          << toDtp->prettyDTypeNameQ()
@@ -1893,7 +1900,8 @@ private:
                 } else if (!basicp->isSigned() && nodep->fromp()->isSigned()) {
                     newp = new AstUnsigned(nodep->fileline(), nodep->fromp()->unlinkFrBack());
                 } else {
-                    // Can just remove cast
+                    // Can just remove cast, but need extend placeholder
+                    // so we can avoid warning message
                 }
             } else if (VN_IS(toDtp, ClassRefDType)) {
                 // Can just remove cast
@@ -2192,6 +2200,8 @@ private:
     }
     void visit(AstEnumItem* nodep) override {
         UINFO(5, "   ENUMITEM " << nodep << endl);
+        VL_RESTORER(m_enumItemp);
+        m_enumItemp = nodep;
         AstNodeDType* const vdtypep = m_vup->dtypep();
         UASSERT_OBJ(vdtypep, nodep, "ENUMITEM not under ENUM");
         nodep->dtypep(vdtypep);
@@ -2752,6 +2762,7 @@ private:
                                         0);  // Spec doesn't say what to do
                 } else {
                     newp = VN_AS(itemp->valuep()->cloneTree(false), Const);  // A const
+                    newp->dtypeFrom(adtypep);  // To prevent a later E_ENUMVALUE
                 }
             } else if (nodep->name() == "last") {
                 const AstEnumItem* itemp = adtypep->itemsp();
@@ -2761,6 +2772,7 @@ private:
                                         0);  // Spec doesn't say what to do
                 } else {
                     newp = VN_AS(itemp->valuep()->cloneTree(false), Const);  // A const
+                    newp->dtypeFrom(adtypep);  // To prevent a later E_ENUMVALUE
                 }
             }
             UASSERT_OBJ(newp, nodep, "Enum method (perhaps enum item) not const");
@@ -2808,6 +2820,7 @@ private:
                 AstVar* const varp = enumVarp(adtypep, attrType, true, 0);
                 AstNode* const newp = new AstAssocSel{nodep->fileline(), newVarRefDollarUnit(varp),
                                                       nodep->fromp()->unlinkFrBack()};
+                newp->dtypeFrom(adtypep);  // To prevent a later E_ENUMVALUE
                 nodep->replaceWith(newp);
             } else {
                 const int selwidth = V3Number::log2b(msbdim) + 1;  // Width to address a bit
@@ -2818,6 +2831,7 @@ private:
                     // We return "random" values if outside the range, which is fine
                     // as next/previous on illegal values just need something good out
                     new AstSel(nodep->fileline(), nodep->fromp()->unlinkFrBack(), 0, selwidth));
+                newp->dtypeFrom(adtypep);  // To prevent a later E_ENUMVALUE
                 nodep->replaceWith(newp);
             }
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -6101,6 +6115,20 @@ private:
             const AstBasicDType* const expBasicp = expDTypep->basicp();
             const AstBasicDType* const underBasicp = underp->dtypep()->basicp();
             if (expBasicp && underBasicp) {
+                if (const AstEnumDType* const expEnump
+                    = VN_CAST(expDTypep->skipRefToEnump(), EnumDType)) {
+                    const auto castable = computeCastable(expEnump, underp->dtypep(), underp);
+                    if (castable != COMPATIBLE && castable != ENUM_IMPLICIT && !VN_IS(underp, Cast)
+                        && !VN_IS(underp, CastDynamic) && !m_enumItemp && warnOn) {
+                        nodep->v3warn(E_ENUMVALUE,
+                                      "Illegal implicit conversion to enum "
+                                          << expDTypep->prettyDTypeNameQ() << " from "
+                                          << underp->dtypep()->prettyDTypeNameQ()
+                                          << " (IEEE 1800-2017 6.19.3)\n"
+                                          << nodep->warnMore()
+                                          << "... Suggest use enum's mnemonic, or static cast");
+                    }
+                }
                 AstNodeDType* subDTypep = expDTypep;
                 // We then iterate FINAL before width fixes, as if the under-operation
                 // is e.g. an ADD, the ADD will auto-adjust to the proper data type
diff --git a/test_regress/t/t_enum_type_bad.out b/test_regress/t/t_enum_type_bad.out
new file mode 100644
index 000000000..26fe75f83
--- /dev/null
+++ b/test_regress/t/t_enum_type_bad.out
@@ -0,0 +1,17 @@
+%Error-ENUMVALUE: t/t_enum_type_bad.v:28:9: Illegal implicit conversion to enum 't.e_t' from 'logic[31:0]' (IEEE 1800-2017 6.19.3)
+                                          : ... In instance t
+                                          : ... Suggest use enum's mnemonic, or static cast
+   28 |       e = 1;   
+      |         ^
+                  ... For error description see https://verilator.org/warn/ENUMVALUE?v=latest
+%Error-ENUMVALUE: t/t_enum_type_bad.v:29:9: Illegal implicit conversion to enum 't.o_t' from 't.e_t' (IEEE 1800-2017 6.19.3)
+                                          : ... In instance t
+                                          : ... Suggest use enum's mnemonic, or static cast
+   29 |       o = e;   
+      |         ^
+%Error-ENUMVALUE: t/t_enum_type_bad.v:35:9: Illegal implicit conversion to enum 't.o_t' from 'ENUMDTYPE 't.e_t'' (IEEE 1800-2017 6.19.3)
+                                          : ... In instance t
+                                          : ... Suggest use enum's mnemonic, or static cast
+   35 |       o = str.m_e;   
+      |         ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_enum_type_bad.pl b/test_regress/t/t_enum_type_bad.pl
index aa2cd3195..a083f46f5 100755
--- a/test_regress/t/t_enum_type_bad.pl
+++ b/test_regress/t/t_enum_type_bad.pl
@@ -11,7 +11,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(vlt => 1);
 
 lint(
-    fails => 0,  # But should fail
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
     );
 
 ok(1);
diff --git a/test_regress/t/t_enum_type_bad.v b/test_regress/t/t_enum_type_bad.v
index 038646ca6..d46fb9d67 100644
--- a/test_regress/t/t_enum_type_bad.v
+++ b/test_regress/t/t_enum_type_bad.v
@@ -21,6 +21,7 @@ module t;
       struct_t str;
 
       e = ONE;
+      e = $random() == 0 ? ONE : TWO;
       e = e_t'(1);
       e = e;
 

From 201419c646dca3e746c44fa662d19a6532c62e49 Mon Sep 17 00:00:00 2001
From: Kritik Bhimani <bhimanikritik@gmail.com>
Date: Sun, 13 Nov 2022 19:05:06 +0530
Subject: [PATCH 035/156] Fix MSVC compiler errors (#3742) (#3746)

---
 docs/CONTRIBUTORS   | 1 +
 src/V3Os.cpp        | 2 +-
 src/V3TraceDecl.cpp | 2 +-
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS
index 1c78172f7..e072cacb0 100644
--- a/docs/CONTRIBUTORS
+++ b/docs/CONTRIBUTORS
@@ -65,6 +65,7 @@ Kamil Rakoczy
 Kanad Kanhere
 Keith Colbert
 Kevin Kiningham
+Kritik Bhimani
 Krzysztof Bieganski
 Kuba Ober
 Larry Doolittle
diff --git a/src/V3Os.cpp b/src/V3Os.cpp
index 32d78f09c..8088e120f 100644
--- a/src/V3Os.cpp
+++ b/src/V3Os.cpp
@@ -78,7 +78,7 @@ VL_DEFINE_DEBUG_FUNCTIONS;
 string V3Os::getenvStr(const string& envvar, const string& defaultValue) {
 #if defined(_MSC_VER)
     // Note: MinGW does not offer _dupenv_s
-    const char* const envvalue = nullptr;
+    const char* envvalue = nullptr;
     _dupenv_s(&envvalue, nullptr, envvar.c_str());
     if (envvalue != nullptr) {
         const std::string result{envvalue};
diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp
index aab284fc3..b8a5615e6 100644
--- a/src/V3TraceDecl.cpp
+++ b/src/V3TraceDecl.cpp
@@ -285,7 +285,7 @@ private:
                 // Recurse into data type of the signal. The visit methods will add AstTraceDecls.
                 iterate(m_traVscp->varp()->dtypep()->skipRefToEnump());
                 // Cleanup
-                if (m_traValuep) VL_DO_DANGLING(m_traValuep->deleteTree(), m_traValuep);
+                if (m_traValuep) VL_DO_CLEAR(m_traValuep->deleteTree(), m_traValuep = nullptr);
             }
         }
         pathAdjustor.unwind();

From 818347f99b3a463386277f08bf9778da020fa093 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 13 Nov 2022 09:26:46 -0500
Subject: [PATCH 036/156] Internals: Fix some unnecessary member paddings. No
 functional change intended.

---
 include/verilated.h    |  2 +-
 src/V3Ast.h            |  8 ++++----
 src/V3AstNodeDType.h   |  4 ++--
 src/V3AstNodeOther.h   | 39 ++++++++++++++++++++-------------------
 src/V3Cdc.cpp          |  2 +-
 src/V3EmitCConstInit.h |  2 +-
 src/V3File.h           |  4 ++--
 src/V3PreLex.h         |  2 +-
 src/V3String.h         |  2 +-
 src/VlcSource.h        |  2 +-
 src/verilog.y          | 14 +++++++-------
 11 files changed, 41 insertions(+), 40 deletions(-)

diff --git a/include/verilated.h b/include/verilated.h
index e07c8f878..09a8c8670 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -364,8 +364,8 @@ protected:
     // assumption is that the restore is allowed to pass different arguments
     struct NonSerializedCommandArgs {
         // Medium speed
-        bool m_argVecLoaded = false;  // Ever loaded argument list
         std::vector<std::string> m_argVec;  // Aargument list
+        bool m_argVecLoaded = false;  // Ever loaded argument list
     } m_args VL_GUARDED_BY(m_argMutex);
 
     // Implementation details
diff --git a/src/V3Ast.h b/src/V3Ast.h
index eaf3f6e58..778b8f252 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -1179,9 +1179,9 @@ class VBasicTypeKey final {
 public:
     const int m_width;  // From AstNodeDType: Bit width of operation
     const int m_widthMin;  // From AstNodeDType: If unsized, bitwidth of minimum implementation
+    const VNumRange m_nrange;  // From AstBasicDType: Numeric msb/lsb (if non-opaque keyword)
     const VSigning m_numeric;  // From AstNodeDType: Node is signed
     const VBasicDTypeKwd m_keyword;  // From AstBasicDType: What keyword created basic type
-    const VNumRange m_nrange;  // From AstBasicDType: Numeric msb/lsb (if non-opaque keyword)
     bool operator==(const VBasicTypeKey& rhs) const {
         return m_width == rhs.m_width && m_widthMin == rhs.m_widthMin && m_numeric == rhs.m_numeric
                && m_keyword == rhs.m_keyword && m_nrange == rhs.m_nrange;
@@ -1203,9 +1203,9 @@ public:
                   const VNumRange& nrange)
         : m_width{width}
         , m_widthMin{widthMin}
+        , m_nrange{nrange}
         , m_numeric{numeric}
-        , m_keyword{kwd}
-        , m_nrange{nrange} {}
+        , m_keyword{kwd} {}
     ~VBasicTypeKey() = default;
 };
 
@@ -1419,8 +1419,8 @@ protected:
     };
     AstNode* m_oldp = nullptr;  // The old node that was linked to this point in the tree
     AstNode* m_backp = nullptr;
-    RelinkWhatEn m_chg = RELINK_BAD;
     AstNode** m_iterpp = nullptr;
+    RelinkWhatEn m_chg = RELINK_BAD;
 
 public:
     VNRelinker() = default;
diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h
index a69c0ad8d..45f5dac64 100644
--- a/src/V3AstNodeDType.h
+++ b/src/V3AstNodeDType.h
@@ -200,10 +200,10 @@ private:
     using MemberNameMap = std::map<const std::string, AstMemberDType*>;
     // MEMBERS
     string m_name;  // Name from upper typedef, if any
-    bool m_packed;
-    bool m_isFourstate = false;  // V3Width computes
     MemberNameMap m_members;
     const int m_uniqueNum;
+    bool m_packed;
+    bool m_isFourstate = false;  // V3Width computes
 
 protected:
     AstNodeUOrStructDType(VNType t, FileLine* fl, VSigning numericUnpack)
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index a3c741ce8..77e3c6234 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -201,6 +201,11 @@ private:
     const string m_origName;  // Name of the module, ignoring name() changes, for dot lookup
     string m_someInstanceName;  // Hierarchical name of some arbitrary instance of this module.
                                 // Used for user messages only.
+    int m_level = 0;  // 1=top module, 2=cell off top module, ...
+    VLifetime m_lifetime;  // Lifetime
+    VTimescale m_timeunit;  // Global time unit
+    VOptionBool m_unconnectedDrive;  // State of `unconnected_drive
+
     bool m_modPublic : 1;  // Module has public references
     bool m_modTrace : 1;  // Tracing this module
     bool m_inLibrary : 1;  // From a library, no error if not used, never top level
@@ -209,10 +214,6 @@ private:
     bool m_internal : 1;  // Internally created
     bool m_recursive : 1;  // Recursive module
     bool m_recursiveClone : 1;  // If recursive, what module it clones, otherwise nullptr
-    int m_level = 0;  // 1=top module, 2=cell off top module, ...
-    VLifetime m_lifetime;  // Lifetime
-    VTimescale m_timeunit;  // Global time unit
-    VOptionBool m_unconnectedDrive;  // State of `unconnected_drive
 protected:
     AstNodeModule(VNType t, FileLine* fl, const string& name)
         : AstNode{t, fl}
@@ -356,14 +357,14 @@ class AstNodeCoverOrAssert VL_NOT_FINAL : public AstNodeStmt {
     // @astgen op2 := sentreep : Optional[AstSenTree]
     // op3 used by some sub-types only
     // @astgen op4 := passsp: List[AstNode] // Statments when propp is passing/truthly
-    const bool m_immediate;  // Immediate assertion/cover
     string m_name;  // Name to report
+    const bool m_immediate;  // Immediate assertion/cover
 public:
     AstNodeCoverOrAssert(VNType t, FileLine* fl, AstNode* propp, AstNode* passsp, bool immediate,
                          const string& name = "")
         : AstNodeStmt{t, fl}
-        , m_immediate{immediate}
-        , m_name{name} {
+        , m_name{name}
+        , m_immediate{immediate} {
         this->propp(propp);
         this->addPasssp(passsp);
     }
@@ -702,14 +703,14 @@ class AstCUse final : public AstNode {
     // C++ use of a class or #include; indicates need of forward declaration
     // Parents:  NODEMODULE
 private:
-    const VUseType m_useType;  // What sort of use this is
     const string m_name;
+    const VUseType m_useType;  // What sort of use this is
 
 public:
     AstCUse(FileLine* fl, VUseType useType, const string& name)
         : ASTGEN_SUPER_CUse(fl)
-        , m_useType{useType}
-        , m_name{name} {}
+        , m_name{name}
+        , m_useType{useType} {}
     ASTGEN_MEMBERS_AstCUse;
     void dump(std::ostream& str = std::cout) const override;
     string name() const override { return m_name; }
@@ -1170,8 +1171,8 @@ class AstModportFTaskRef final : public AstNode {
     // PARENT: AstModport
 private:
     string m_name;  // Name of the variable referenced
-    bool m_export;  // Type of the function (import/export)
     AstNodeFTask* m_ftaskp = nullptr;  // Link to the function
+    bool m_export;  // Type of the function (import/export)
 public:
     AstModportFTaskRef(FileLine* fl, const string& name, bool isExport)
         : ASTGEN_SUPER_ModportFTaskRef(fl)
@@ -1193,8 +1194,8 @@ class AstModportVarRef final : public AstNode {
     // PARENT: AstModport
 private:
     string m_name;  // Name of the variable referenced
-    VDirection m_direction;  // Direction of the variable (in/out)
     AstVar* m_varp = nullptr;  // Link to the actual Var
+    VDirection m_direction;  // Direction of the variable (in/out)
 public:
     AstModportVarRef(FileLine* fl, const string& name, VDirection::en direction)
         : ASTGEN_SUPER_ModportVarRef(fl)
@@ -1627,8 +1628,8 @@ class AstTypedef final : public AstNode {
     // @astgen op4 := attrsp : List[AstNode] // Attributes during early parse
 
     string m_name;
-    bool m_attrPublic = false;
     string m_tag;  // Holds the string of the verilator tag -- used in XML output.
+    bool m_attrPublic = false;
 public:
     AstTypedef(FileLine* fl, const string& name, AstNode* attrsp, VFlagChildDType,
                AstNodeDType* dtp)
@@ -2515,13 +2516,13 @@ public:
 class AstComment final : public AstNodeStmt {
     // Some comment to put into the output stream
     // Parents:  {statement list}
-    const bool m_showAt;  // Show "at <fileline>"
     const string m_name;  // Text of comment
+    const bool m_showAt;  // Show "at <fileline>"
 public:
     AstComment(FileLine* fl, const string& name, bool showAt = false)
         : ASTGEN_SUPER_Comment(fl)
-        , m_showAt{showAt}
-        , m_name{name} {}
+        , m_name{name}
+        , m_showAt{showAt} {}
     ASTGEN_MEMBERS_AstComment;
     string name() const override { return m_name; }  // * = Text
     bool same(const AstNode* samep) const override { return true; }  // Ignore name in comments
@@ -3227,15 +3228,15 @@ class AstTraceInc final : public AstNodeStmt {
 
 private:
     AstTraceDecl* m_declp;  // Pointer to declaration
-    const bool m_full;  // Is this a full vs incremental dump
     const uint32_t m_baseCode;  // Trace code base value in function containing this AstTraceInc
+    const bool m_full;  // Is this a full vs incremental dump
 
 public:
     AstTraceInc(FileLine* fl, AstTraceDecl* declp, bool full, uint32_t baseCode = 0)
         : ASTGEN_SUPER_TraceInc(fl)
         , m_declp{declp}
-        , m_full{full}
-        , m_baseCode{baseCode} {
+        , m_baseCode{baseCode}
+        , m_full{full} {
         dtypeFrom(declp);
         this->valuep(
             declp->valuep()->cloneTree(true));  // TODO: maybe use reference to TraceDecl instead?
diff --git a/src/V3Cdc.cpp b/src/V3Cdc.cpp
index 0bd371111..54edca7c1 100644
--- a/src/V3Cdc.cpp
+++ b/src/V3Cdc.cpp
@@ -177,8 +177,8 @@ public:
 
 class CdcWidthVisitor final : public CdcBaseVisitor {
 private:
-    int m_maxLineno = 0;
     size_t m_maxFilenameLen = 0;
+    int m_maxLineno = 0;
 
     void visit(AstNode* nodep) override {
         iterateChildren(nodep);
diff --git a/src/V3EmitCConstInit.h b/src/V3EmitCConstInit.h
index 9b4c2b4e9..adc317b36 100644
--- a/src/V3EmitCConstInit.h
+++ b/src/V3EmitCConstInit.h
@@ -28,8 +28,8 @@
 
 class EmitCConstInit VL_NOT_FINAL : public EmitCBaseVisitor {
     // MEMBERS
-    bool m_inUnpacked = false;
     uint32_t m_unpackedWord = 0;
+    bool m_inUnpacked = false;
 
     // METHODS
 
diff --git a/src/V3File.h b/src/V3File.h
index 38f4dc6ff..eb6673e38 100644
--- a/src/V3File.h
+++ b/src/V3File.h
@@ -195,9 +195,9 @@ class V3OutFile VL_NOT_FINAL : public V3OutFormatter {
     static constexpr std::size_t WRITE_BUFFER_SIZE_BYTES = 128 * 1024;
 
     // MEMBERS
-    std::unique_ptr<std::array<char, WRITE_BUFFER_SIZE_BYTES>> m_bufferp;  // Write buffer
-    std::size_t m_usedBytes = 0;  // Number of bytes stored in m_bufferp
     FILE* m_fp = nullptr;
+    std::size_t m_usedBytes = 0;  // Number of bytes stored in m_bufferp
+    std::unique_ptr<std::array<char, WRITE_BUFFER_SIZE_BYTES>> m_bufferp;  // Write buffer
 
 public:
     V3OutFile(const string& filename, V3OutFormatter::Language lang);
diff --git a/src/V3PreLex.h b/src/V3PreLex.h
index 4389c506d..3a001153f 100644
--- a/src/V3PreLex.h
+++ b/src/V3PreLex.h
@@ -132,9 +132,9 @@ public:
     V3PreLex* const m_lexp;  // Lexer, for resource tracking
     std::deque<string> m_buffers;  // Buffer of characters to process
     int m_ignNewlines = 0;  // Ignore multiline newlines
+    int m_termState = 0;  // Termination fsm
     bool m_eof = false;  // "EOF" buffer
     bool m_file = false;  // Buffer is start of new file
-    int m_termState = 0;  // Termination fsm
     VPreStream(FileLine* fl, V3PreLex* lexp)
         : m_curFilelinep{fl}
         , m_lexp{lexp} {
diff --git a/src/V3String.h b/src/V3String.h
index 7aacdb150..e004347f5 100644
--- a/src/V3String.h
+++ b/src/V3String.h
@@ -132,8 +132,8 @@ class VHashSha256 final {
     // MEMBERS
     uint32_t m_inthash[8];  // Intermediate hash, in host order
     string m_remainder;  // Unhashed data
-    bool m_final = false;  // Finalized
     size_t m_totLength = 0;  // Total all-chunk length as needed by output digest
+    bool m_final = false;  // Finalized
 public:
     // CONSTRUCTORS
     VHashSha256() {
diff --git a/src/VlcSource.h b/src/VlcSource.h
index b1ec313f2..af711f0af 100644
--- a/src/VlcSource.h
+++ b/src/VlcSource.h
@@ -67,8 +67,8 @@ public:
 private:
     // MEMBERS
     string m_name;  //< Name of the source file
-    bool m_needed = false;  //< Need to annotate; has low coverage
     LinenoMap m_lines;  //< Map of each annotated line
+    bool m_needed = false;  //< Need to annotate; has low coverage
 
 public:
     // CONSTRUCTORS
diff --git a/src/verilog.y b/src/verilog.y
index 846fde896..330cd4c0f 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -75,11 +75,6 @@
 
 class V3ParseGrammar {
 public:
-    bool m_impliedDecl = false;  // Allow implied wire declarations
-    VVarType m_varDecl;  // Type for next signal declaration (reg/wire/etc)
-    bool m_varDeclTyped = false;  // Var got reg/wire for dedup check
-    VDirection m_varIO;  // Direction for next signal declaration (reg/wire/etc)
-    VLifetime m_varLifetime;  // Static/Automatic for next signal
     AstVar* m_varAttrp = nullptr;  // Current variable for attribute adding
     AstRange* m_gateRangep = nullptr;  // Current range for gate declarations
     AstCase* m_caseAttrp = nullptr;  // Current case statement for attribute adding
@@ -88,10 +83,15 @@ public:
     AstDelay* m_netDelayp = nullptr;  // Pointer to delay for next signal declaration
     AstStrengthSpec* m_netStrengthp = nullptr;  // Pointer to strength for next net declaration
     AstNodeModule* m_modp = nullptr;  // Last module for timeunits
-    bool m_pinAnsi = false;  // In ANSI port list
     FileLine* m_instModuleFl = nullptr;  // Fileline of module referenced for instantiations
-    string m_instModule;  // Name of module referenced for instantiations
     AstPin* m_instParamp = nullptr;  // Parameters for instantiations
+    string m_instModule;  // Name of module referenced for instantiations
+    VVarType m_varDecl;  // Type for next signal declaration (reg/wire/etc)
+    VDirection m_varIO;  // Direction for next signal declaration (reg/wire/etc)
+    VLifetime m_varLifetime;  // Static/Automatic for next signal
+    bool m_impliedDecl = false;  // Allow implied wire declarations
+    bool m_varDeclTyped = false;  // Var got reg/wire for dedup check
+    bool m_pinAnsi = false;  // In ANSI port list
     bool m_tracingParse = true;  // Tracing disable for parser
     bool m_insideProperty = false;  // Is inside property declaration
     bool m_typedPropertyPort = false;  // True if typed property port occured on port lists

From d1658b9e82d57c65092459294d488f6a1a1fb275 Mon Sep 17 00:00:00 2001
From: github action <action@example.com>
Date: Sun, 13 Nov 2022 14:27:37 +0000
Subject: [PATCH 037/156] Apply 'make format'

---
 src/V3AstNodeOther.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index 77e3c6234..8d5009bea 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -1630,6 +1630,7 @@ class AstTypedef final : public AstNode {
     string m_name;
     string m_tag;  // Holds the string of the verilator tag -- used in XML output.
     bool m_attrPublic = false;
+
 public:
     AstTypedef(FileLine* fl, const string& name, AstNode* attrsp, VFlagChildDType,
                AstNodeDType* dtp)

From ee26dddfa1b78cf4f10cff9cbc075c603d6ba668 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 13 Nov 2022 11:23:57 -0500
Subject: [PATCH 038/156] Internals: Fix constructor style.

---
 src/V3Randomize.cpp | 97 +++++++++++++++++++++++----------------------
 1 file changed, 49 insertions(+), 48 deletions(-)

diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index 22a5074f2..0552865df 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -86,7 +86,7 @@ private:
         iterateChildren(nodep);
         if (nodep->extendsp()) {
             // Save pointer to derived class
-            auto* const basep = nodep->extendsp()->classp();
+            AstClass* const basep = nodep->extendsp()->classp();
             m_baseToDerivedMap[basep].insert(nodep);
         }
     }
@@ -95,7 +95,7 @@ private:
         if (nodep->name() != "randomize") return;
         if (const AstClassRefDType* const classRefp
             = VN_CAST(nodep->fromp()->dtypep(), ClassRefDType)) {
-            auto* const classp = classRefp->classp();
+            AstClass* const classp = classRefp->classp();
             classp->user1(true);
             markMembers(classp);
         }
@@ -134,13 +134,13 @@ private:
         if (nodep->user2p()) return VN_AS(nodep->user2p(), Var);
         UINFO(9, "Construct Venumvaltab " << nodep << endl);
         AstNodeArrayDType* const vardtypep
-            = new AstUnpackArrayDType(nodep->fileline(), nodep->dtypep(),
-                                      new AstRange(nodep->fileline(), nodep->itemCount(), 0));
-        AstInitArray* const initp = new AstInitArray(nodep->fileline(), vardtypep, nullptr);
+            = new AstUnpackArrayDType{nodep->fileline(), nodep->dtypep(),
+                                      new AstRange{nodep->fileline(), nodep->itemCount(), 0}};
+        AstInitArray* const initp = new AstInitArray{nodep->fileline(), vardtypep, nullptr};
         v3Global.rootp()->typeTablep()->addTypesp(vardtypep);
         AstVar* const varp
-            = new AstVar(nodep->fileline(), VVarType::MODULETEMP,
-                         "__Venumvaltab_" + cvtToStr(m_enumValueTabCount++), vardtypep);
+            = new AstVar{nodep->fileline(), VVarType::MODULETEMP,
+                         "__Venumvaltab_" + cvtToStr(m_enumValueTabCount++), vardtypep};
         varp->isConst(true);
         varp->isStatic(true);
         varp->valuep(initp);
@@ -163,10 +163,10 @@ private:
                       StructDType)) {
             AstNodeStmt* stmtsp = nullptr;
             offset += memberp ? memberp->lsb() : 0;
-            for (auto* smemberp = structDtp->membersp(); smemberp;
+            for (AstMemberDType* smemberp = structDtp->membersp(); smemberp;
                  smemberp = VN_AS(smemberp->nextp(), MemberDType)) {
-                auto* const randp = newRandStmtsp(fl, stmtsp ? varrefp->cloneTree(false) : varrefp,
-                                                  offset, smemberp);
+                AstNodeStmt* const randp = newRandStmtsp(
+                    fl, stmtsp ? varrefp->cloneTree(false) : varrefp, offset, smemberp);
                 if (stmtsp) {
                     stmtsp->addNext(randp);
                 } else {
@@ -176,26 +176,26 @@ private:
             return stmtsp;
         } else {
             AstNodeExpr* valp;
-            if (auto* const enumDtp = VN_CAST(memberp ? memberp->subDTypep()->subDTypep()
-                                                      : varrefp->dtypep()->subDTypep(),
-                                              EnumDType)) {
+            if (AstEnumDType* const enumDtp = VN_CAST(memberp ? memberp->subDTypep()->subDTypep()
+                                                              : varrefp->dtypep()->subDTypep(),
+                                                      EnumDType)) {
                 AstVarRef* const tabRefp
-                    = new AstVarRef(fl, enumValueTabp(enumDtp), VAccess::READ);
+                    = new AstVarRef{fl, enumValueTabp(enumDtp), VAccess::READ};
                 tabRefp->classOrPackagep(v3Global.rootp()->dollarUnitPkgAddp());
-                auto* const randp = new AstRand(fl, nullptr, false);
-                auto* const moddivp
-                    = new AstModDiv(fl, randp, new AstConst(fl, enumDtp->itemCount()));
+                AstRand* const randp = new AstRand{fl, nullptr, false};
+                AstNode* const moddivp = new AstModDiv{
+                    fl, randp, new AstConst{fl, static_cast<uint32_t>(enumDtp->itemCount())}};
                 randp->dtypep(varrefp->findBasicDType(VBasicDTypeKwd::UINT32));
                 moddivp->dtypep(enumDtp);
-                valp = new AstArraySel(fl, tabRefp, moddivp);
+                valp = new AstArraySel{fl, tabRefp, moddivp};
             } else {
-                valp = new AstRand(fl, nullptr, false);
+                valp = new AstRand{fl, nullptr, false};
                 valp->dtypep(memberp ? memberp->dtypep() : varrefp->varp()->dtypep());
             }
-            return new AstAssign(fl,
-                                 new AstSel(fl, varrefp, offset + (memberp ? memberp->lsb() : 0),
-                                            memberp ? memberp->width() : varrefp->width()),
-                                 valp);
+            return new AstAssign{fl,
+                                 new AstSel{fl, varrefp, offset + (memberp ? memberp->lsb() : 0),
+                                            memberp ? memberp->width() : varrefp->width()},
+                                 valp};
         }
     }
 
@@ -213,35 +213,36 @@ private:
         iterateChildren(nodep);
         if (!nodep->user1()) return;  // Doesn't need randomize, or already processed
         UINFO(9, "Define randomize() for " << nodep << endl);
-        auto* const funcp = V3Randomize::newRandomizeFunc(nodep);
-        auto* const fvarp = VN_AS(funcp->fvarp(), Var);
-        funcp->addStmtsp(new AstAssign(
-            nodep->fileline(), new AstVarRef(nodep->fileline(), fvarp, VAccess::WRITE),
-            new AstConst(nodep->fileline(), AstConst::WidthedValue(), 32, 1)));
-        for (auto* classp = nodep; classp;
+        AstFunc* const funcp = V3Randomize::newRandomizeFunc(nodep);
+        AstVar* const fvarp = VN_AS(funcp->fvarp(), Var);
+        funcp->addStmtsp(new AstAssign{
+            nodep->fileline(), new AstVarRef{nodep->fileline(), fvarp, VAccess::WRITE},
+            new AstConst{nodep->fileline(), AstConst::WidthedValue{}, 32, 1}});
+        for (AstClass* classp = nodep; classp;
              classp = classp->extendsp() ? classp->extendsp()->classp() : nullptr) {
             for (auto* memberp = classp->stmtsp(); memberp; memberp = memberp->nextp()) {
-                auto* const memberVarp = VN_CAST(memberp, Var);
+                AstVar* const memberVarp = VN_CAST(memberp, Var);
                 if (!memberVarp || !memberVarp->isRand()) continue;
-                const auto* const dtypep = memberp->dtypep()->skipRefp();
+                const AstNodeDType* const dtypep = memberp->dtypep()->skipRefp();
                 if (VN_IS(dtypep, BasicDType) || VN_IS(dtypep, StructDType)) {
-                    auto* const refp
-                        = new AstVarRef(nodep->fileline(), memberVarp, VAccess::WRITE);
-                    auto* const stmtp = newRandStmtsp(nodep->fileline(), refp);
+                    AstVarRef* const refp
+                        = new AstVarRef{nodep->fileline(), memberVarp, VAccess::WRITE};
+                    AstNodeStmt* const stmtp = newRandStmtsp(nodep->fileline(), refp);
                     funcp->addStmtsp(stmtp);
                 } else if (const auto* const classRefp = VN_CAST(dtypep, ClassRefDType)) {
-                    auto* const refp
-                        = new AstVarRef(nodep->fileline(), memberVarp, VAccess::WRITE);
-                    auto* const memberFuncp = V3Randomize::newRandomizeFunc(classRefp->classp());
-                    auto* const callp
-                        = new AstMethodCall(nodep->fileline(), refp, "randomize", nullptr);
+                    AstVarRef* const refp
+                        = new AstVarRef{nodep->fileline(), memberVarp, VAccess::WRITE};
+                    AstFunc* const memberFuncp
+                        = V3Randomize::newRandomizeFunc(classRefp->classp());
+                    AstMethodCall* const callp
+                        = new AstMethodCall{nodep->fileline(), refp, "randomize", nullptr};
                     callp->taskp(memberFuncp);
                     callp->dtypeFrom(memberFuncp);
-                    funcp->addStmtsp(new AstAssign(
-                        nodep->fileline(), new AstVarRef(nodep->fileline(), fvarp, VAccess::WRITE),
-                        new AstAnd(nodep->fileline(),
-                                   new AstVarRef(nodep->fileline(), fvarp, VAccess::READ),
-                                   callp)));
+                    funcp->addStmtsp(new AstAssign{
+                        nodep->fileline(), new AstVarRef{nodep->fileline(), fvarp, VAccess::WRITE},
+                        new AstAnd{nodep->fileline(),
+                                   new AstVarRef{nodep->fileline(), fvarp, VAccess::READ},
+                                   callp}});
                 } else {
                     memberp->v3warn(E_UNSUPPORTED,
                                     "Unsupported: random member variables with type "
@@ -329,16 +330,16 @@ void V3Randomize::randomizeNetlist(AstNetlist* nodep) {
 }
 
 AstFunc* V3Randomize::newRandomizeFunc(AstClass* nodep) {
-    auto* funcp = VN_AS(nodep->findMember("randomize"), Func);
+    AstFunc* funcp = VN_AS(nodep->findMember("randomize"), Func);
     if (!funcp) {
-        auto* const dtypep
+        AstNodeDType* const dtypep
             = nodep->findBitDType(32, 32, VSigning::SIGNED);  // IEEE says int return of 0/1
-        auto* const fvarp = new AstVar(nodep->fileline(), VVarType::MEMBER, "randomize", dtypep);
+        AstVar* const fvarp = new AstVar{nodep->fileline(), VVarType::MEMBER, "randomize", dtypep};
         fvarp->lifetime(VLifetime::AUTOMATIC);
         fvarp->funcLocal(true);
         fvarp->funcReturn(true);
         fvarp->direction(VDirection::OUTPUT);
-        funcp = new AstFunc(nodep->fileline(), "randomize", nullptr, fvarp);
+        funcp = new AstFunc{nodep->fileline(), "randomize", nullptr, fvarp};
         funcp->dtypep(dtypep);
         funcp->classMethod(true);
         funcp->isVirtual(nodep->isExtended());

From c6ecd6099306bcd37ff93128578ba288e5401ab7 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 13 Nov 2022 11:59:40 -0500
Subject: [PATCH 039/156] Support pre_randomize and post_randomize.

---
 Changes                                       |  1 +
 src/V3AstNodeExpr.h                           |  2 +-
 src/V3LinkDot.cpp                             |  2 +-
 src/V3LinkResolve.cpp                         |  4 +-
 src/V3Randomize.cpp                           | 10 ++++
 test_regress/t/t_randomize_method_unsup.out   |  8 ----
 test_regress/t/t_randomize_method_unsup.v     | 16 -------
 ...method_unsup.pl => t_randomize_prepost.pl} |  6 ++-
 test_regress/t/t_randomize_prepost.v          | 47 +++++++++++++++++++
 9 files changed, 65 insertions(+), 31 deletions(-)
 delete mode 100644 test_regress/t/t_randomize_method_unsup.out
 delete mode 100644 test_regress/t/t_randomize_method_unsup.v
 rename test_regress/t/{t_randomize_method_unsup.pl => t_randomize_prepost.pl} (86%)
 create mode 100644 test_regress/t/t_randomize_prepost.v

diff --git a/Changes b/Changes
index 96b17667d..449c8a3ae 100644
--- a/Changes
+++ b/Changes
@@ -16,6 +16,7 @@ Verilator 5.003 devel
 * Deprecate --no-threads; use --threads 1 for single threaded (#3703). [Kamil Rakoczy, Antmicro Ltd]
 * Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd]
 * Support randcase.
+* Support pre_randomize and post_randomize.
 * Add ENUMVALUE warning when value misused for enum (#726).
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Change ENDLABEL from warning into an error.
diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index 93e59a566..880d757d9 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -1585,7 +1585,7 @@ class AstThisRef final : public AstNodeExpr {
     // Reference to 'this'.
     // @astgen op1 := childDTypep : Optional[AstClassRefDType] // dtype of the node
 public:
-    explicit AstThisRef(FileLine* fl, AstClassRefDType* dtypep)
+    AstThisRef(FileLine* fl, VFlagChildDType, AstClassRefDType* dtypep)
         : ASTGEN_SUPER_ThisRef(fl) {
         childDTypep(dtypep);
     }
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 32a02e295..693acbc38 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -2342,7 +2342,7 @@ private:
             AstClass* const classp = VN_AS(classSymp->nodep(), Class);
             AstClassRefDType* const dtypep
                 = new AstClassRefDType{nodep->fileline(), classp, nullptr};
-            AstThisRef* const newp = new AstThisRef{nodep->fileline(), dtypep};
+            AstThisRef* const newp = new AstThisRef{nodep->fileline(), VFlagChildDType{}, dtypep};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
             return;
diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp
index ca4352e2b..9b6729e72 100644
--- a/src/V3LinkResolve.cpp
+++ b/src/V3LinkResolve.cpp
@@ -115,9 +115,7 @@ private:
         if (m_underGenerate) nodep->underGenerate(true);
         // Remember the existing symbol table scope
         if (m_classp) {
-            if (nodep->name() == "pre_randomize" || nodep->name() == "post_randomize") {
-                nodep->v3warn(E_UNSUPPORTED, "Unsupported: " << nodep->prettyNameQ());
-            } else if (nodep->name() == "randomize") {
+            if (nodep->name() == "randomize") {
                 nodep->v3error(nodep->prettyNameQ()
                                << " is a predefined class method; redefinition not allowed"
                                   " (IEEE 1800-2017 18.6.3)");
diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index 0552865df..89ddac9d2 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -198,6 +198,14 @@ private:
                                  valp};
         }
     }
+    void addPrePostCall(AstClass* classp, AstFunc* funcp, const string& name) {
+        if (AstTask* userFuncp = VN_CAST(classp->findMember(name), Task)) {
+            AstTaskRef* const callp
+                = new AstTaskRef{userFuncp->fileline(), userFuncp->name(), nullptr};
+            callp->taskp(userFuncp);
+            funcp->addStmtsp(callp->makeStmt());
+        }
+    }
 
     // VISITORS
     void visit(AstNodeModule* nodep) override {
@@ -215,6 +223,7 @@ private:
         UINFO(9, "Define randomize() for " << nodep << endl);
         AstFunc* const funcp = V3Randomize::newRandomizeFunc(nodep);
         AstVar* const fvarp = VN_AS(funcp->fvarp(), Var);
+        addPrePostCall(nodep, funcp, "pre_randomize");
         funcp->addStmtsp(new AstAssign{
             nodep->fileline(), new AstVarRef{nodep->fileline(), fvarp, VAccess::WRITE},
             new AstConst{nodep->fileline(), AstConst::WidthedValue{}, 32, 1}});
@@ -250,6 +259,7 @@ private:
                 }
             }
         }
+        addPrePostCall(nodep, funcp, "post_randomize");
         nodep->user1(false);
     }
     void visit(AstRandCase* nodep) override {
diff --git a/test_regress/t/t_randomize_method_unsup.out b/test_regress/t/t_randomize_method_unsup.out
deleted file mode 100644
index 42f6c65fa..000000000
--- a/test_regress/t/t_randomize_method_unsup.out
+++ /dev/null
@@ -1,8 +0,0 @@
-%Error-UNSUPPORTED: t/t_randomize_method_unsup.v:8:18: Unsupported: 'pre_randomize'
-    8 |    function void pre_randomize;
-      |                  ^~~~~~~~~~~~~
-                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_randomize_method_unsup.v:11:18: Unsupported: 'post_randomize'
-   11 |    function void post_randomize;
-      |                  ^~~~~~~~~~~~~~
-%Error: Exiting due to
diff --git a/test_regress/t/t_randomize_method_unsup.v b/test_regress/t/t_randomize_method_unsup.v
deleted file mode 100644
index 898bf9fff..000000000
--- a/test_regress/t/t_randomize_method_unsup.v
+++ /dev/null
@@ -1,16 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2020 by Wilson Snyder.
-// SPDX-License-Identifier: CC0-1.0
-
-class Cls;
-   function void pre_randomize;
-   endfunction;
-
-   function void post_randomize;
-   endfunction;
-endclass
-
-module t (/*AUTOARG*/);
-endmodule
diff --git a/test_regress/t/t_randomize_method_unsup.pl b/test_regress/t/t_randomize_prepost.pl
similarity index 86%
rename from test_regress/t/t_randomize_method_unsup.pl
rename to test_regress/t/t_randomize_prepost.pl
index 6ad7137de..aabcde63e 100755
--- a/test_regress/t/t_randomize_method_unsup.pl
+++ b/test_regress/t/t_randomize_prepost.pl
@@ -11,8 +11,10 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    fails => $Self->{vlt_all},
-    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
     );
 
 ok(1);
diff --git a/test_regress/t/t_randomize_prepost.v b/test_regress/t/t_randomize_prepost.v
new file mode 100644
index 000000000..734bb3c31
--- /dev/null
+++ b/test_regress/t/t_randomize_prepost.v
@@ -0,0 +1,47 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef enum int {
+   RANDOMIZED = 20
+} enumed_t;
+
+class Cls;
+   int       pre;
+   rand enumed_t r;
+   int       post;
+
+   function void pre_randomize;
+      if (pre != 0) $stop;
+      $display("%d", r);
+      if (r != enumed_t'(0)) $stop;
+      if (post != 0) $stop;
+      pre = 10;
+   endfunction
+
+   function void post_randomize;
+      if (pre != 10) $stop;
+      if (r != RANDOMIZED) $stop;
+      if (post != 0) $stop;
+      post = 30;
+   endfunction
+endclass
+
+module t (/*AUTOARG*/);
+
+   initial begin
+      Cls c;
+      int rand_result;
+
+      c = new;
+      rand_result = c.randomize();
+      if (rand_result != 1) $stop;
+      if (c.pre != 10) $stop;
+      if (c.r != RANDOMIZED) $stop;
+      if (c.post != 30) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

From 8c6d1e53ca4ed431bc19195dfe921f0abf8156dd Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 13 Nov 2022 17:40:50 -0500
Subject: [PATCH 040/156] Internals: Fix some 'p' names, and make new base
 class for VlDeleter. No functional change intended.

---
 include/verilated.cpp       |  2 +-
 include/verilated_fst_c.cpp |  8 ++++----
 include/verilated_fst_c.h   |  4 ++--
 include/verilated_funcs.h   | 16 ++++++++--------
 include/verilated_types.h   | 28 +++++++++++++++++-----------
 include/verilated_vpi.cpp   | 32 ++++++++++++++++----------------
 6 files changed, 48 insertions(+), 42 deletions(-)

diff --git a/include/verilated.cpp b/include/verilated.cpp
index e88fc0c1b..8ca1c4781 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -3102,7 +3102,7 @@ void VlDeleter::deleteAll() {
         VerilatedLockGuard deleteLock{m_deleteMutex};
         std::swap(m_newGarbage, m_toDelete);
         lock.unlock();  // So destuctors can enqueue new objects
-        for (VlClass* const objp : m_toDelete) delete objp;
+        for (VlDeletable* const objp : m_toDelete) delete objp;
         m_toDelete.clear();
     }
 }
diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp
index 1247b46ed..6e1f5a33b 100644
--- a/include/verilated_fst_c.cpp
+++ b/include/verilated_fst_c.cpp
@@ -95,7 +95,7 @@ VerilatedFst::VerilatedFst(void* /*fst*/) {}
 VerilatedFst::~VerilatedFst() {
     if (m_fst) fstWriterClose(m_fst);
     if (m_symbolp) VL_DO_CLEAR(delete[] m_symbolp, m_symbolp = nullptr);
-    if (m_strbuf) VL_DO_CLEAR(delete[] m_strbuf, m_strbuf = nullptr);
+    if (m_strbufp) VL_DO_CLEAR(delete[] m_strbufp, m_strbufp = nullptr);
 }
 
 void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
@@ -125,7 +125,7 @@ void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) {
     m_code2symbol.clear();
 
     // Allocate string buffer for arrays
-    if (!m_strbuf) m_strbuf = new char[maxBits() + 32];
+    if (!m_strbufp) m_strbufp = new char[maxBits() + 32];
 }
 
 void VerilatedFst::close() VL_MT_SAFE_EXCLUDES(m_mutex) {
@@ -320,7 +320,7 @@ void VerilatedFstBuffer::emitQData(uint32_t code, QData newval, int bits) {
 VL_ATTR_ALWINLINE
 void VerilatedFstBuffer::emitWData(uint32_t code, const WData* newvalp, int bits) {
     int words = VL_WORDS_I(bits);
-    char* wp = m_strbuf;
+    char* wp = m_strbufp;
     // Convert the most significant word
     const int bitsInMSW = VL_BITBIT_E(bits) ? VL_BITBIT_E(bits) : VL_EDATASIZE;
     cvtEDataToStr(wp, newvalp[--words] << (VL_EDATASIZE - bitsInMSW));
@@ -330,7 +330,7 @@ void VerilatedFstBuffer::emitWData(uint32_t code, const WData* newvalp, int bits
         cvtEDataToStr(wp, newvalp[--words]);
         wp += VL_EDATASIZE;
     }
-    fstWriterEmitValueChange(m_fst, m_symbolp[code], m_strbuf);
+    fstWriterEmitValueChange(m_fst, m_symbolp[code], m_strbufp);
 }
 
 VL_ATTR_ALWINLINE
diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h
index 8b33b4855..fafcd415c 100644
--- a/include/verilated_fst_c.h
+++ b/include/verilated_fst_c.h
@@ -53,7 +53,7 @@ private:
     std::map<int, fstEnumHandle> m_local2fstdtype;
     std::list<std::string> m_curScope;
     fstHandle* m_symbolp = nullptr;  // same as m_code2symbol, but as an array
-    char* m_strbuf = nullptr;  // String buffer long enough to hold maxBits() chars
+    char* m_strbufp = nullptr;  // String buffer long enough to hold maxBits() chars
 
     bool m_useFstWriterThread = false;  // Whether to use the separate FST writer thread
 
@@ -149,7 +149,7 @@ class VerilatedFstBuffer VL_NOT_FINAL {
     // code to fstHande map, as an array
     const fstHandle* const m_symbolp = m_owner.m_symbolp;
     // String buffer long enough to hold maxBits() chars
-    char* const m_strbuf = m_owner.m_strbuf;
+    char* const m_strbufp = m_owner.m_strbufp;
 
     // CONSTRUCTOR
     explicit VerilatedFstBuffer(VerilatedFst& owner)
diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h
index c226426d8..37c0d85b5 100644
--- a/include/verilated_funcs.h
+++ b/include/verilated_funcs.h
@@ -444,16 +444,16 @@ static inline void VL_ASSIGNBIT_WO(int bit, WDataOutP owp) VL_MT_SAFE {
     { \
         const int words = VL_WORDS_I(obits); \
         sc_biguint<(obits)> _butemp = (svar).read(); \
-        uint32_t* chunk = _butemp.get_raw(); \
+        uint32_t* chunkp = _butemp.get_raw(); \
         int32_t lsb = 0; \
         while (lsb < obits - BITS_PER_DIGIT) { \
-            const uint32_t data = *chunk; \
-            ++chunk; \
+            const uint32_t data = *chunkp; \
+            ++chunkp; \
             _vl_insert_WI(owp.data(), data, lsb + BITS_PER_DIGIT - 1, lsb); \
             lsb += BITS_PER_DIGIT; \
         } \
         if (lsb < obits) { \
-            const uint32_t msb_data = *chunk; \
+            const uint32_t msb_data = *chunkp; \
             _vl_insert_WI(owp.data(), msb_data, obits - 1, lsb); \
         } \
         (owp)[words - 1] &= VL_MASK_E(obits); \
@@ -500,18 +500,18 @@ static inline void VL_ASSIGNBIT_WO(int bit, WDataOutP owp) VL_MT_SAFE {
     { \
         sc_biguint<(obits)> _butemp; \
         int32_t lsb = 0; \
-        uint32_t* chunk = _butemp.get_raw(); \
+        uint32_t* chunkp = _butemp.get_raw(); \
         while (lsb + VL_SC_BITS_PER_DIGIT < (obits)) { \
             static_assert(std::is_same<IData, EData>::value, "IData and EData missmatch"); \
             const uint32_t data = VL_SEL_IWII(lsb + VL_SC_BITS_PER_DIGIT + 1, (rwp).data(), lsb, \
                                               VL_SC_BITS_PER_DIGIT); \
-            *chunk = data & VL_MASK_E(VL_SC_BITS_PER_DIGIT); \
-            ++chunk; \
+            *chunkp = data & VL_MASK_E(VL_SC_BITS_PER_DIGIT); \
+            ++chunkp; \
             lsb += VL_SC_BITS_PER_DIGIT; \
         } \
         if (lsb < (obits)) { \
             const uint32_t msb_data = VL_SEL_IWII((obits) + 1, (rwp).data(), lsb, (obits)-lsb); \
-            *chunk = msb_data & VL_MASK_E((obits)-lsb); \
+            *chunkp = msb_data & VL_MASK_E((obits)-lsb); \
         } \
         (svar).write(_butemp); \
     }
diff --git a/include/verilated_types.h b/include/verilated_types.h
index 0aae11ea1..271de4f67 100644
--- a/include/verilated_types.h
+++ b/include/verilated_types.h
@@ -1004,7 +1004,14 @@ std::string VL_TO_STRING(const VlUnpacked<T_Value, T_Depth>& obj) {
     return obj.to_string();
 }
 
-class VlClass;  // See below
+//===================================================================
+// Object that VlDeleter is capable of deleting
+
+class VlDeletable VL_NOT_FINAL {
+public:
+    VlDeletable() = default;
+    virtual ~VlDeletable() = default;
+};
 
 //===================================================================
 // Class providing delayed deletion of garbage objects. Objects get deleted only when 'deleteAll()'
@@ -1013,9 +1020,9 @@ class VlClass;  // See below
 class VlDeleter final {
     // MEMBERS
     // Queue of new objects that should be deleted
-    std::vector<VlClass*> m_newGarbage VL_GUARDED_BY(m_mutex);
+    std::vector<VlDeletable*> m_newGarbage VL_GUARDED_BY(m_mutex);
     // Queue of objects currently being deleted (only for deleteAll())
-    std::vector<VlClass*> m_toDelete VL_GUARDED_BY(m_deleteMutex);
+    std::vector<VlDeletable*> m_toDelete VL_GUARDED_BY(m_deleteMutex);
     mutable VerilatedMutex m_mutex;  // Mutex protecting the 'new garbage' queue
     mutable VerilatedMutex m_deleteMutex;  // Mutex protecting the delete queue
 
@@ -1030,7 +1037,7 @@ private:
 public:
     // METHODS
     // Adds a new object to the 'new garbage' queue.
-    void put(VlClass* const objp) VL_MT_SAFE {
+    void put(VlDeletable* const objp) VL_MT_SAFE {
         const VerilatedLockGuard lock{m_mutex};
         m_newGarbage.push_back(objp);
     }
@@ -1042,17 +1049,16 @@ public:
 //===================================================================
 // Base class for all verilated classes. Includes a reference counter, and a pointer to the deleter
 // object that should destroy it after the counter reaches 0. This allows for easy construction of
-// VlClassRefs from 'this'. Also declares a virtual constructor, so that the object can be deleted
-// using a base pointer.
+// VlClassRefs from 'this'.
 
-class VlClass VL_NOT_FINAL {
+class VlClass VL_NOT_FINAL : public VlDeletable {
     // TYPES
     template <typename T_Class>
     friend class VlClassRef;  // Needed for access to the ref counter and deleter
 
     // MEMBERS
     std::atomic<size_t> m_counter{0};  // Reference count for this object
-    VlDeleter* m_deleter = nullptr;  // The deleter that will delete this object
+    VlDeleter* m_deleterp = nullptr;  // The deleter that will delete this object
 
     // METHODS
     // Atomically increments the reference counter
@@ -1060,14 +1066,14 @@ class VlClass VL_NOT_FINAL {
     // Atomically decrements the reference counter. Assuming VlClassRef semantics are sound, it
     // should never get called at m_counter == 0.
     void refCountDec() VL_MT_SAFE {
-        if (!--m_counter) m_deleter->put(this);
+        if (!--m_counter) m_deleterp->put(this);
     }
 
 public:
     // CONSTRUCTORS
     VlClass() = default;
     VlClass(const VlClass& copied) {}
-    virtual ~VlClass() {}
+    ~VlClass() override = default;
 };
 
 //===================================================================
@@ -1110,7 +1116,7 @@ public:
     template <typename... T_Args>
     VlClassRef(VlDeleter& deleter, T_Args&&... args)
         : m_objp{new T_Class{std::forward<T_Args>(args)...}} {
-        m_objp->m_deleter = &deleter;
+        m_objp->m_deleterp = &deleter;
         refCountInc();
     }
     // Explicit to avoid implicit conversion from 0
diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp
index 023c6683d..24070d620 100644
--- a/include/verilated_vpi.cpp
+++ b/include/verilated_vpi.cpp
@@ -71,7 +71,7 @@ class VerilatedVpio VL_NOT_FINAL {
 
     // MEM MANGLEMENT
     // Internal note: Globals may multi-construct, see verilated.cpp top.
-    static thread_local uint8_t* t_freeHead;
+    static thread_local uint8_t* t_freeHeadp;
 
 public:
     // CONSTRUCTORS
@@ -85,9 +85,9 @@ public:
         static constexpr size_t CHUNK_SIZE = 96;
         if (VL_UNCOVERABLE(size > CHUNK_SIZE))
             VL_FATAL_MT(__FILE__, __LINE__, "", "increase CHUNK_SIZE");
-        if (VL_LIKELY(t_freeHead)) {
-            uint8_t* const newp = t_freeHead;
-            t_freeHead = *(reinterpret_cast<uint8_t**>(newp));
+        if (VL_LIKELY(t_freeHeadp)) {
+            uint8_t* const newp = t_freeHeadp;
+            t_freeHeadp = *(reinterpret_cast<uint8_t**>(newp));
             *(reinterpret_cast<uint32_t*>(newp)) = activeMagic();
             return newp + 8;
         }
@@ -106,8 +106,8 @@ public:
 #ifdef VL_VPI_IMMEDIATE_FREE  // Define to aid in finding leaky handles
         ::operator delete(oldp);
 #else
-        *(reinterpret_cast<void**>(oldp)) = t_freeHead;
-        t_freeHead = oldp;
+        *(reinterpret_cast<void**>(oldp)) = t_freeHeadp;
+        t_freeHeadp = oldp;
 #endif
     }
     // MEMBERS
@@ -225,28 +225,28 @@ public:
 };
 
 class VerilatedVpioRange final : public VerilatedVpio {
-    const VerilatedRange* const m_range;
+    const VerilatedRange* const m_rangep;
 
 public:
-    explicit VerilatedVpioRange(const VerilatedRange* range)
-        : m_range{range} {}
+    explicit VerilatedVpioRange(const VerilatedRange* rangep)
+        : m_rangep{rangep} {}
     ~VerilatedVpioRange() override = default;
     static VerilatedVpioRange* castp(vpiHandle h) {
         return dynamic_cast<VerilatedVpioRange*>(reinterpret_cast<VerilatedVpio*>(h));
     }
     uint32_t type() const override { return vpiRange; }
-    uint32_t size() const override { return m_range->elements(); }
-    const VerilatedRange* rangep() const override { return m_range; }
+    uint32_t size() const override { return m_rangep->elements(); }
+    const VerilatedRange* rangep() const override { return m_rangep; }
 };
 
 class VerilatedVpioRangeIter final : public VerilatedVpio {
     // Only supports 1 dimension
-    const VerilatedRange* const m_range;
+    const VerilatedRange* const m_rangep;
     bool m_done = false;
 
 public:
-    explicit VerilatedVpioRangeIter(const VerilatedRange* range)
-        : m_range{range} {}
+    explicit VerilatedVpioRangeIter(const VerilatedRange* rangep)
+        : m_rangep{rangep} {}
     ~VerilatedVpioRangeIter() override = default;
     static VerilatedVpioRangeIter* castp(vpiHandle h) {
         return dynamic_cast<VerilatedVpioRangeIter*>(reinterpret_cast<VerilatedVpio*>(h));
@@ -258,7 +258,7 @@ public:
             return nullptr;
         }
         m_done = true;
-        return ((new VerilatedVpioRange{m_range})->castVpiHandle());
+        return ((new VerilatedVpioRange{m_rangep})->castVpiHandle());
     }
 };
 
@@ -666,7 +666,7 @@ public:
 // Statics
 // Internal note: Globals may multi-construct, see verilated.cpp top.
 
-thread_local uint8_t* VerilatedVpio::t_freeHead = nullptr;
+thread_local uint8_t* VerilatedVpio::t_freeHeadp = nullptr;
 
 //======================================================================
 // VerilatedVpiError

From 04f68cbd994e32a875d10028ff7fc9e4418b57f3 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 13 Nov 2022 21:58:18 -0500
Subject: [PATCH 041/156] Internals: Spacing

---
 include/verilated_types.h | 27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)

diff --git a/include/verilated_types.h b/include/verilated_types.h
index 271de4f67..ef0611ac9 100644
--- a/include/verilated_types.h
+++ b/include/verilated_types.h
@@ -1079,6 +1079,7 @@ public:
 //===================================================================
 // Represents the null pointer. Used for setting VlClassRef to null instead of
 // via nullptr_t, to prevent the implicit conversion of 0 to nullptr.
+
 struct VlNull {
     operator bool() const { return false; }
 };
@@ -1178,18 +1179,6 @@ public:
     operator bool() const { return m_objp; }
 };
 
-#define VL_NEW(Class, ...) \
-    VlClassRef<Class> { vlSymsp->__Vm_deleter, __VA_ARGS__ }
-
-#define VL_KEEP_THIS \
-    VlClassRef<std::remove_pointer<decltype(this)>::type> __Vthisref { this }
-
-template <class T>  // T typically of type VlClassRef<x>
-inline T VL_NULL_CHECK(T t, const char* filename, int linenum) {
-    if (VL_UNLIKELY(!t)) Verilated::nullPointerError(filename, linenum);
-    return t;
-}
-
 template <typename T, typename U>
 static inline bool VL_CAST_DYNAMIC(VlClassRef<T> in, VlClassRef<U>& outr) {
     VlClassRef<U> casted = in.template dynamicCast<U>();
@@ -1203,4 +1192,18 @@ static inline bool VL_CAST_DYNAMIC(VlClassRef<T> in, VlClassRef<U>& outr) {
 
 //======================================================================
 
+#define VL_NEW(Class, ...) \
+    VlClassRef<Class> { vlSymsp->__Vm_deleter, __VA_ARGS__ }
+
+#define VL_KEEP_THIS \
+    VlClassRef<std::remove_pointer<decltype(this)>::type> __Vthisref { this }
+
+template <class T>  // T typically of type VlClassRef<x>
+inline T VL_NULL_CHECK(T t, const char* filename, int linenum) {
+    if (VL_UNLIKELY(!t)) Verilated::nullPointerError(filename, linenum);
+    return t;
+}
+
+//======================================================================
+
 #endif  // Guard

From e6da59eecd45e531dcda30c30703f432782c61da Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 15 Nov 2022 09:18:47 -0500
Subject: [PATCH 042/156] Internals: Mark some VL_PURE functions. No functional
 change.

---
 include/verilated_funcs.h | 24 ++++++++++++------------
 include/verilated_types.h |  2 +-
 include/verilated_vpi.cpp | 20 ++++++++++----------
 src/V3Number.h            |  2 +-
 4 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h
index 37c0d85b5..1f26f56af 100644
--- a/include/verilated_funcs.h
+++ b/include/verilated_funcs.h
@@ -586,7 +586,7 @@ static inline WDataOutP VL_EXTENDS_WW(int obits, int lbits, WDataOutP owp,
 // EMIT_RULE: VL_REDAND:  oclean=clean; lclean==clean; obits=1;
 #define VL_REDAND_II(lbits, lhs) ((lhs) == VL_MASK_I(lbits))
 #define VL_REDAND_IQ(lbits, lhs) ((lhs) == VL_MASK_Q(lbits))
-static inline IData VL_REDAND_IW(int lbits, WDataInP const lwp) VL_MT_SAFE {
+static inline IData VL_REDAND_IW(int lbits, WDataInP const lwp) VL_PURE {
     const int words = VL_WORDS_I(lbits);
     EData combine = lwp[0];
     for (int i = 1; i < words - 1; ++i) combine &= lwp[i];
@@ -597,7 +597,7 @@ static inline IData VL_REDAND_IW(int lbits, WDataInP const lwp) VL_MT_SAFE {
 // EMIT_RULE: VL_REDOR:  oclean=clean; lclean==clean; obits=1;
 #define VL_REDOR_I(lhs) ((lhs) != 0)
 #define VL_REDOR_Q(lhs) ((lhs) != 0)
-static inline IData VL_REDOR_W(int words, WDataInP const lwp) VL_MT_SAFE {
+static inline IData VL_REDOR_W(int words, WDataInP const lwp) VL_PURE {
     EData equal = 0;
     for (int i = 0; i < words; ++i) equal |= lwp[i];
     return (equal != 0);
@@ -664,7 +664,7 @@ static inline IData VL_REDXOR_64(QData r) VL_PURE {
     return static_cast<IData>(r);
 #endif
 }
-static inline IData VL_REDXOR_W(int words, WDataInP const lwp) VL_MT_SAFE {
+static inline IData VL_REDXOR_W(int words, WDataInP const lwp) VL_PURE {
     EData r = lwp[0];
     for (int i = 1; i < words; ++i) r ^= lwp[i];
     return VL_REDXOR_32(r);
@@ -683,7 +683,7 @@ static inline IData VL_COUNTONES_Q(QData lhs) VL_PURE {
     return VL_COUNTONES_I(static_cast<IData>(lhs)) + VL_COUNTONES_I(static_cast<IData>(lhs >> 32));
 }
 #define VL_COUNTONES_E VL_COUNTONES_I
-static inline IData VL_COUNTONES_W(int words, WDataInP const lwp) VL_MT_SAFE {
+static inline IData VL_COUNTONES_W(int words, WDataInP const lwp) VL_PURE {
     EData r = 0;
     for (int i = 0; i < words; ++i) r += VL_COUNTONES_E(lwp[i]);
     return r;
@@ -725,7 +725,7 @@ static inline IData VL_ONEHOT_I(IData lhs) VL_PURE {
 static inline IData VL_ONEHOT_Q(QData lhs) VL_PURE {
     return (((lhs & (lhs - 1)) == 0) & (lhs != 0));
 }
-static inline IData VL_ONEHOT_W(int words, WDataInP const lwp) VL_MT_SAFE {
+static inline IData VL_ONEHOT_W(int words, WDataInP const lwp) VL_PURE {
     EData one = 0;
     for (int i = 0; (i < words); ++i) {
         if (lwp[i]) {
@@ -739,7 +739,7 @@ static inline IData VL_ONEHOT_W(int words, WDataInP const lwp) VL_MT_SAFE {
 
 static inline IData VL_ONEHOT0_I(IData lhs) VL_PURE { return ((lhs & (lhs - 1)) == 0); }
 static inline IData VL_ONEHOT0_Q(QData lhs) VL_PURE { return ((lhs & (lhs - 1)) == 0); }
-static inline IData VL_ONEHOT0_W(int words, WDataInP const lwp) VL_MT_SAFE {
+static inline IData VL_ONEHOT0_W(int words, WDataInP const lwp) VL_PURE {
     bool one = false;
     for (int i = 0; (i < words); ++i) {
         if (lwp[i]) {
@@ -766,7 +766,7 @@ static inline IData VL_CLOG2_Q(QData lhs) VL_PURE {
     for (; lhs != 0; ++shifts) lhs = lhs >> 1ULL;
     return shifts;
 }
-static inline IData VL_CLOG2_W(int words, WDataInP const lwp) VL_MT_SAFE {
+static inline IData VL_CLOG2_W(int words, WDataInP const lwp) VL_PURE {
     const EData adjust = (VL_COUNTONES_W(words, lwp) == 1) ? 0 : 1;
     for (int i = words - 1; i >= 0; --i) {
         if (VL_UNLIKELY(lwp[i])) {  // Shorter worst case if predict not taken
@@ -781,7 +781,7 @@ static inline IData VL_CLOG2_W(int words, WDataInP const lwp) VL_MT_SAFE {
     return 0;
 }
 
-static inline IData VL_MOSTSETBITP1_W(int words, WDataInP const lwp) VL_MT_SAFE {
+static inline IData VL_MOSTSETBITP1_W(int words, WDataInP const lwp) VL_PURE {
     // MSB set bit plus one; similar to FLS.  0=value is zero
     for (int i = words - 1; i >= 0; --i) {
         if (VL_UNLIKELY(lwp[i])) {  // Shorter worst case if predict not taken
@@ -810,7 +810,7 @@ static inline WDataOutP VL_OR_W(int words, WDataOutP owp, WDataInP const lwp,
     return owp;
 }
 // EMIT_RULE: VL_CHANGEXOR:  oclean=1; obits=32; lbits==rbits;
-static inline IData VL_CHANGEXOR_W(int words, WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE {
+static inline IData VL_CHANGEXOR_W(int words, WDataInP const lwp, WDataInP const rwp) VL_PURE {
     IData od = 0;
     for (int i = 0; (i < words); ++i) od |= (lwp[i] ^ rwp[i]);
     return od;
@@ -843,14 +843,14 @@ static inline WDataOutP VL_NOT_W(int words, WDataOutP owp, WDataInP const lwp) V
 #define VL_GTE_W(words, lwp, rwp) (_vl_cmp_w(words, lwp, rwp) >= 0)
 
 // Output clean, <lhs> AND <rhs> MUST BE CLEAN
-static inline IData VL_EQ_W(int words, WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE {
+static inline IData VL_EQ_W(int words, WDataInP const lwp, WDataInP const rwp) VL_PURE {
     EData nequal = 0;
     for (int i = 0; (i < words); ++i) nequal |= (lwp[i] ^ rwp[i]);
     return (nequal == 0);
 }
 
 // Internal usage
-static inline int _vl_cmp_w(int words, WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE {
+static inline int _vl_cmp_w(int words, WDataInP const lwp, WDataInP const rwp) VL_PURE {
     for (int i = words - 1; i >= 0; --i) {
         if (lwp[i] > rwp[i]) return 1;
         if (lwp[i] < rwp[i]) return -1;
@@ -909,7 +909,7 @@ static inline IData VL_LTES_IQQ(int lbits, QData lhs, QData rhs) VL_PURE {
     return lhs_signed <= rhs_signed;
 }
 
-static inline int _vl_cmps_w(int lbits, WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE {
+static inline int _vl_cmps_w(int lbits, WDataInP const lwp, WDataInP const rwp) VL_PURE {
     const int words = VL_WORDS_I(lbits);
     int i = words - 1;
     // We need to flip sense if negative comparison
diff --git a/include/verilated_types.h b/include/verilated_types.h
index ef0611ac9..4d080e942 100644
--- a/include/verilated_types.h
+++ b/include/verilated_types.h
@@ -197,7 +197,7 @@ public:
 /// zero in memory, but during intermediate operations in the Verilated
 /// internals is unpredictable.
 
-static int _vl_cmp_w(int words, WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE;
+static int _vl_cmp_w(int words, WDataInP const lwp, WDataInP const rwp) VL_PURE;
 
 template <std::size_t T_Words>
 struct VlWide final {
diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp
index 24070d620..2fb4ecdba 100644
--- a/include/verilated_vpi.cpp
+++ b/include/verilated_vpi.cpp
@@ -732,11 +732,11 @@ public:
         }
         VL_FATAL_MT(__FILE__, __LINE__, "", "vpi_unsupported called without error info set");
     }
-    static const char* strFromVpiVal(PLI_INT32 vpiVal) VL_MT_SAFE;
-    static const char* strFromVpiObjType(PLI_INT32 vpiVal) VL_MT_SAFE;
-    static const char* strFromVpiMethod(PLI_INT32 vpiVal) VL_MT_SAFE;
-    static const char* strFromVpiCallbackReason(PLI_INT32 vpiVal) VL_MT_SAFE;
-    static const char* strFromVpiProp(PLI_INT32 vpiVal) VL_MT_SAFE;
+    static const char* strFromVpiVal(PLI_INT32 vpiVal) VL_PURE;
+    static const char* strFromVpiObjType(PLI_INT32 vpiVal) VL_PURE;
+    static const char* strFromVpiMethod(PLI_INT32 vpiVal) VL_PURE;
+    static const char* strFromVpiCallbackReason(PLI_INT32 vpiVal) VL_PURE;
+    static const char* strFromVpiProp(PLI_INT32 vpiVal) VL_PURE;
 };
 
 //======================================================================
@@ -775,7 +775,7 @@ VerilatedVpiError* VerilatedVpiImp::error_info() VL_MT_UNSAFE_ONE {
 //======================================================================
 // VerilatedVpiError Methods
 
-const char* VerilatedVpiError::strFromVpiVal(PLI_INT32 vpiVal) VL_MT_SAFE {
+const char* VerilatedVpiError::strFromVpiVal(PLI_INT32 vpiVal) VL_PURE {
     // clang-format off
     static const char* const names[] = {
         "*undefined*",
@@ -802,7 +802,7 @@ const char* VerilatedVpiError::strFromVpiVal(PLI_INT32 vpiVal) VL_MT_SAFE {
     if (VL_UNCOVERABLE(vpiVal < 0)) return names[0];
     return names[(vpiVal <= vpiRawFourStateVal) ? vpiVal : 0];
 }
-const char* VerilatedVpiError::strFromVpiObjType(PLI_INT32 vpiVal) VL_MT_SAFE {
+const char* VerilatedVpiError::strFromVpiObjType(PLI_INT32 vpiVal) VL_PURE {
     // clang-format off
     static const char* const names[] = {
         "*undefined*",
@@ -947,7 +947,7 @@ const char* VerilatedVpiError::strFromVpiObjType(PLI_INT32 vpiVal) VL_MT_SAFE {
     if (VL_UNCOVERABLE(vpiVal < 0)) return names[0];
     return names[(vpiVal <= vpiAutomatics) ? vpiVal : 0];
 }
-const char* VerilatedVpiError::strFromVpiMethod(PLI_INT32 vpiVal) VL_MT_SAFE {
+const char* VerilatedVpiError::strFromVpiMethod(PLI_INT32 vpiVal) VL_PURE {
     // clang-format off
     static const char* const names[] = {
         "vpiCondition",
@@ -990,7 +990,7 @@ const char* VerilatedVpiError::strFromVpiMethod(PLI_INT32 vpiVal) VL_MT_SAFE {
     return names[vpiVal - vpiCondition];
 }
 
-const char* VerilatedVpiError::strFromVpiCallbackReason(PLI_INT32 vpiVal) VL_MT_SAFE {
+const char* VerilatedVpiError::strFromVpiCallbackReason(PLI_INT32 vpiVal) VL_PURE {
     // clang-format off
     static const char* const names[] = {
         "*undefined*",
@@ -1031,7 +1031,7 @@ const char* VerilatedVpiError::strFromVpiCallbackReason(PLI_INT32 vpiVal) VL_MT_
     return names[(vpiVal <= cbAtEndOfSimTime) ? vpiVal : 0];
 }
 
-const char* VerilatedVpiError::strFromVpiProp(PLI_INT32 vpiVal) VL_MT_SAFE {
+const char* VerilatedVpiError::strFromVpiProp(PLI_INT32 vpiVal) VL_PURE {
     // clang-format off
     static const char* const names[] = {
         "*undefined or other*",
diff --git a/src/V3Number.h b/src/V3Number.h
index 10032b68d..ea4fd2cae 100644
--- a/src/V3Number.h
+++ b/src/V3Number.h
@@ -275,7 +275,7 @@ public:
     }
 
 private:
-    static constexpr int bitsToWords(int bitsCount) VL_MT_SAFE { return (bitsCount + 31) / 32; }
+    static constexpr int bitsToWords(int bitsCount) VL_PURE { return (bitsCount + 31) / 32; }
 
     bool isNumber() const VL_MT_SAFE {
         return m_type == V3NumberDataType::DOUBLE || m_type == V3NumberDataType::LOGIC;

From dc28e7f3e27e148bd826c5e3234669d20ab00104 Mon Sep 17 00:00:00 2001
From: Mariusz Glebocki <mglebocki@antmicro.com>
Date: Wed, 16 Nov 2022 14:32:32 +0100
Subject: [PATCH 043/156] Commentary. Remove repeated entry in Verilator help.
 (#3754)

---
 bin/verilator | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/bin/verilator b/bin/verilator
index cd3a25c35..e5af6da66 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -364,7 +364,6 @@ detailed descriptions of these arguments.
      -O<optimization-letter>    Selectable optimizations
      -o <executable>            Name of final executable
     --no-order-clock-delay      Disable ordering clock enable assignments
-    --no-verilate               Skip Verilation, only compile previously Verilated code
     --output-split <statements>          Split .cpp files into pieces
     --output-split-cfuncs <statements>   Split model functions
     --output-split-ctrace <statements>   Split tracing functions
@@ -425,7 +424,7 @@ detailed descriptions of these arguments.
     --unused-regexp <regexp>    Tune UNUSED lint signals
      -V                         Verbose version and config
      -v <filename>              Verilog library
-    --no-verilate               Skip verilation and just compile previously Verilated code.
+    --no-verilate               Skip verilation and just compile previously Verilated code
      +verilog1995ext+<ext>      Synonym for +1364-1995ext+<ext>
      +verilog2001ext+<ext>      Synonym for +1364-2001ext+<ext>
     --version                   Displays program version and exits

From f78249609219c1912af03b509a5e602b58b8c5fb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Miodrag=20Milanovi=C4=87?= <mmicko@gmail.com>
Date: Wed, 16 Nov 2022 14:34:25 +0100
Subject: [PATCH 044/156] Fix for mingw cross-compile, arm and riscv (#3752)

---
 include/verilatedos.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/include/verilatedos.h b/include/verilatedos.h
index 3d755f270..eff312137 100644
--- a/include/verilatedos.h
+++ b/include/verilatedos.h
@@ -471,8 +471,10 @@ using ssize_t = uint32_t;  ///< signed size_t; returned from read()
 
 #ifdef _WIN32
 # define WIN32_LEAN_AND_MEAN
-# define NOMINMAX
-# include "Windows.h"
+# ifndef NOMINMAX
+#  define NOMINMAX
+# endif
+# include "windows.h"
 # define VL_CPU_RELAX() YieldProcessor()
 #elif defined(__i386__) || defined(__x86_64__) || defined(VL_CPPCHECK)
 // For more efficient busy waiting on SMT CPUs, let the processor know
@@ -480,11 +482,11 @@ using ssize_t = uint32_t;  ///< signed size_t; returned from read()
 # define VL_CPU_RELAX() asm volatile("rep; nop" ::: "memory")
 #elif defined(__ia64__)
 # define VL_CPU_RELAX() asm volatile("hint @pause" ::: "memory")
-#elif defined(__aarch64__)
+#elif defined(__aarch64__) || defined(__arm__)
 # define VL_CPU_RELAX() asm volatile("yield" ::: "memory")
 #elif defined(__powerpc64__)
 # define VL_CPU_RELAX() asm volatile("or 1, 1, 1; or 2, 2, 2;" ::: "memory")
-#elif defined(__loongarch__)
+#elif defined(__loongarch__) || defined(__riscv)
 // LoongArch does not currently have a yield/pause instruction
 # define VL_CPU_RELAX() asm volatile("nop" ::: "memory")
 #else

From 79e0fa33276912e16b58a282fc23d2d4d022f800 Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Wed, 16 Nov 2022 16:14:12 +0100
Subject: [PATCH 045/156] CI: Switch building pull requests to ubuntu 22.04
 (#3753)

---
 .github/workflows/build.yml | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index ac09746fe..073721400 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -35,13 +35,13 @@ jobs:
           - { cc: gcc,   cxx: g++     }
         m32: [0, 1]
         exclude:
-          # Build pull requests only with ubuntu-20.04 and without m32
+          # Build pull requests only with ubuntu-22.04 and without m32
           - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-18.04' || 'do-not-exclude' }}
-          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-22.04' || 'do-not-exclude' }}
+          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-20.04' || 'do-not-exclude' }}
           - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
-          # Build -m32 only on ubuntu-20.04
+          # Build -m32 only on ubuntu-22.04
           - {os: ubuntu-18.04, m32: 1}
-          - {os: ubuntu-22.04, m32: 1}
+          - {os: ubuntu-20.04, m32: 1}
         include:
           # Build GCC 10 on ubuntu-20.04
           - os: ubuntu-20.04
@@ -104,13 +104,13 @@ jobs:
         m32: [0, 1]
         suite: [dist-vlt-0, dist-vlt-1, dist-vlt-2, vltmt-0, vltmt-1]
         exclude:
-          # Build pull requests only with ubuntu-20.04 and without m32
+          # Build pull requests only with ubuntu-22.04 and without m32
           - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-18.04' || 'do-not-exclude' }}
-          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-22.04' || 'do-not-exclude' }}
+          - os:  ${{ github.event_name == 'pull_request' && 'ubuntu-20.04' || 'do-not-exclude' }}
           - m32: ${{ github.event_name == 'pull_request' && 1              || 'do-not-exclude' }}
-          # Build -m32 only on ubuntu-20.04
+          # Build -m32 only on ubuntu-22.04
           - {os: ubuntu-18.04, m32: 1}
-          - {os: ubuntu-22.04, m32: 1}
+          - {os: ubuntu-20.04, m32: 1}
         include:
           # Test with GCC 10 on ubuntu-20.04 without m32
           - {os: ubuntu-20.04, compiler: { cc: gcc-10, cxx: g++-10 }, m32: 0, suite: dist-vlt-0}

From a58cd66358c32f00eb0a69000970ced7388f54ed Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 16 Nov 2022 18:17:24 -0500
Subject: [PATCH 046/156] Fix printtimescale

---
 src/V3EmitCFunc.h                   | 2 +-
 test_regress/t/t_timescale_unit.out | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h
index 45f863d21..d7ff08772 100644
--- a/src/V3EmitCFunc.h
+++ b/src/V3EmitCFunc.h
@@ -876,7 +876,7 @@ public:
     }
     void visit(AstPrintTimeScale* nodep) override {
         puts("VL_PRINTTIMESCALE(");
-        putsQuoted(protect(nodep->name()));
+        putsQuoted(protect(nodep->prettyName()));
         puts(", ");
         putsQuoted(nodep->timeunit().ascii());
         puts(", vlSymsp->_vm_contextp__);\n");
diff --git a/test_regress/t/t_timescale_unit.out b/test_regress/t/t_timescale_unit.out
index 6f3bba3f0..dca44f779 100644
--- a/test_regress/t/t_timescale_unit.out
+++ b/test_regress/t/t_timescale_unit.out
@@ -1,4 +1,4 @@
-Time scale of __024unit is 10ps / 10ps
+Time scale of $unit is 10ps / 10ps
 Time scale of from_unit is 10ps / 10ps
 Time scale of t is 100ps / 10ps
 *-* All Finished *-*

From 3ddfa214e31ea0cd8ae151ec656f2c6fc4436b51 Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Thu, 17 Nov 2022 00:58:57 +0100
Subject: [PATCH 047/156] Fix $unit as base package for other packages (#3755)

---
 src/V3LinkDot.cpp                             |  2 +-
 .../t/t_pkg_using_dollar_unit_items.pl        | 20 ++++++
 .../t/t_pkg_using_dollar_unit_items.v         | 62 +++++++++++++++++++
 3 files changed, 83 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_pkg_using_dollar_unit_items.pl
 create mode 100644 test_regress/t/t_pkg_using_dollar_unit_items.v

diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 693acbc38..e80ac901a 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -868,7 +868,6 @@ class LinkDotFindVisitor final : public VNVisitor {
         } else if (doit) {
             UINFO(4, "     Link Module: " << nodep << endl);
             UASSERT_OBJ(!nodep->dead(), nodep, "Module in instance tree mislabeled as dead?");
-            VSymEnt* const upperSymp = m_curSymp ? m_curSymp : m_statep->rootEntp();
             AstPackage* const pkgp = VN_CAST(nodep, Package);
             m_classOrPackagep = pkgp;
             if (standalonePkg) {
@@ -876,6 +875,7 @@ class LinkDotFindVisitor final : public VNVisitor {
                     m_curSymp = m_modSymp = m_statep->dunitEntp();
                     nodep->user1p(m_curSymp);
                 } else {
+                    VSymEnt* const upperSymp = m_statep->dunitEntp();
                     m_scope = nodep->name();
                     m_curSymp = m_modSymp = m_statep->insertBlock(
                         upperSymp, nodep->name() + "::", nodep, m_classOrPackagep);
diff --git a/test_regress/t/t_pkg_using_dollar_unit_items.pl b/test_regress/t/t_pkg_using_dollar_unit_items.pl
new file mode 100755
index 000000000..bf4e4ce9f
--- /dev/null
+++ b/test_regress/t/t_pkg_using_dollar_unit_items.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile();
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_pkg_using_dollar_unit_items.v b/test_regress/t/t_pkg_using_dollar_unit_items.v
new file mode 100644
index 000000000..73b000329
--- /dev/null
+++ b/test_regress/t/t_pkg_using_dollar_unit_items.v
@@ -0,0 +1,62 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef int my_type;
+
+class my_class;
+   static int a = 1;
+endclass
+
+function int get_val;
+   return 2;
+endfunction
+
+package my_pkg;
+   int      my_type_size = $bits(my_type);
+   int      my_class_a = my_class::a;
+   int      get_val_result = get_val();
+endpackage
+
+package overwriting_pkg;
+   typedef logic [9:0] my_type;
+
+   class my_class;
+      static int a = 2;
+   endclass
+
+   function int get_val;
+      return 3;
+   endfunction
+
+   int      my_type_size = $bits(my_type);
+   int      my_class_a = my_class::a;
+   int      get_val_result = get_val();
+endpackage
+
+module t (/*AUTOARG*/
+      clk
+   );
+
+   input clk;
+
+   always @(posedge clk) begin
+      bit [5:0] results = {my_pkg::my_type_size == 32,
+                           my_pkg::my_class_a == 1,
+                           my_pkg::get_val_result == 2,
+                           overwriting_pkg::my_type_size == 10,
+                           overwriting_pkg::my_class_a == 2,
+                           overwriting_pkg::get_val_result == 3};
+
+      if (results == '1) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+      else begin
+         $write("Results: %b\n", results);
+         $stop;
+      end
+   end
+endmodule

From 3c77c7bb924349615e672a61419f9c2b6aebc8ba Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 16 Nov 2022 21:10:39 -0500
Subject: [PATCH 048/156] Support  and

---
 Changes                           |  1 +
 docs/guide/extensions.rst         | 10 ++++++++++
 src/V3AstNodeExpr.h               | 33 +++++++++++++++++++++++++++++++
 src/V3EmitCFunc.h                 |  3 +++
 src/V3LinkParse.cpp               |  4 ++++
 src/V3Width.cpp                   |  5 +++++
 src/verilog.l                     |  2 ++
 src/verilog.y                     | 17 ++++++++++++----
 test_regress/t/t_time_timeunit.pl | 22 +++++++++++++++++++++
 test_regress/t/t_time_timeunit.v  | 26 ++++++++++++++++++++++++
 10 files changed, 119 insertions(+), 4 deletions(-)
 create mode 100755 test_regress/t/t_time_timeunit.pl
 create mode 100644 test_regress/t/t_time_timeunit.v

diff --git a/Changes b/Changes
index 449c8a3ae..15133343c 100644
--- a/Changes
+++ b/Changes
@@ -17,6 +17,7 @@ Verilator 5.003 devel
 * Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd]
 * Support randcase.
 * Support pre_randomize and post_randomize.
+* Support $timeunit and $timeprecision.
 * Add ENUMVALUE warning when value misused for enum (#726).
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Change ENDLABEL from warning into an error.
diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst
index fd65e8b0a..6aad4c6e6 100644
--- a/docs/guide/extensions.rst
+++ b/docs/guide/extensions.rst
@@ -73,6 +73,16 @@ or "`ifdef`"'s may break other tools.
    prints 5 digits per the C standard (this is unspecified in Verilog, but
    was incorporated into the 1800-2009).
 
+.. option:: $timeprecision
+
+   Returns the timeprecision of the model as an integer.  This extension is
+   experimental and may be removed without deprecation.
+
+.. option:: $timeunit
+
+   Returns the timeunit of the current module as an integer.  This
+   extension is experimental and may be removed without deprecation.
+
 .. option:: `coverage_block_off
 
    Specifies the entire begin/end block should be ignored for coverage
diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index 880d757d9..608e0db31 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -1597,6 +1597,39 @@ public:
     AstNodeDType* getChildDTypep() const override { return childDTypep(); }
     AstNodeDType* subDTypep() const { return dtypep() ? dtypep() : childDTypep(); }
 };
+class AstTimePrecision final : public AstNodeExpr {
+    // Verilog $timeprecision
+public:
+    AstTimePrecision(FileLine* fl)
+        : ASTGEN_SUPER_TimePrecision(fl) {
+        dtypeSetSigned32();
+    }
+    ASTGEN_MEMBERS_AstTimePrecision;
+    string emitVerilog() override { return "$timeprecision"; }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    string emitSimpleOperator() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { return true; }
+    int instrCount() const override { return widthInstrs(); }
+    bool same(const AstNode* /*samep*/) const override { return true; }
+};
+class AstTimeUnit final : public AstNodeExpr {
+    VTimescale m_timeunit;  // Parent module time unit
+    // Verilog $timeunit
+public:
+    AstTimeUnit(FileLine* fl)
+        : ASTGEN_SUPER_TimeUnit(fl) {
+        dtypeSetSigned32();
+    }
+    ASTGEN_MEMBERS_AstTimeUnit;
+    string emitVerilog() override { return "$timeunit"; }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    string emitSimpleOperator() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { return true; }
+    int instrCount() const override { return widthInstrs(); }
+    bool same(const AstNode* /*samep*/) const override { return true; }
+    void timeunit(const VTimescale& flag) { m_timeunit = flag; }
+    VTimescale timeunit() const { return m_timeunit; }
+};
 class AstUCFunc final : public AstNodeExpr {
     // User's $c function
     // Perhaps this should be an AstNodeListop; but there's only one list math right now
diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h
index d7ff08772..50b2f55c6 100644
--- a/src/V3EmitCFunc.h
+++ b/src/V3EmitCFunc.h
@@ -909,6 +909,9 @@ public:
         iterateAndNextNull(nodep->widthp());
         puts(", vlSymsp->_vm_contextp__);\n");
     }
+    void visit(AstTimePrecision* nodep) override {
+        puts("vlSymsp->_vm_contextp__->timeprecision()");
+    }
     void visit(AstNodeSimpleText* nodep) override {
         const string text = m_inUC && m_useSelfForThis
                                 ? VString::replaceWord(nodep->text(), "this", "vlSelf")
diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index 7dd81fb2a..4c8411869 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -577,6 +577,10 @@ private:
         iterateChildren(nodep);
         nodep->timeunit(m_modp->timeunit());
     }
+    void visit(AstTimeUnit* nodep) override {
+        iterateChildren(nodep);
+        nodep->timeunit(m_modp->timeunit());
+    }
     void visit(AstEventControl* nodep) override {
         cleanFileline(nodep);
         iterateChildren(nodep);
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 1b8db1311..fff0970b9 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -446,6 +446,11 @@ private:
     // Widths: Constant, terminal
     void visit(AstTime* nodep) override { nodep->dtypeSetUInt64(); }
     void visit(AstTimeD* nodep) override { nodep->dtypeSetDouble(); }
+    void visit(AstTimePrecision* nodep) override { nodep->dtypeSetSigned32(); }
+    void visit(AstTimeUnit* nodep) override {
+        nodep->replaceWith(
+            new AstConst{nodep->fileline(), AstConst::Signed32(), nodep->timeunit().powerOfTen()});
+    }
     void visit(AstScopeName* nodep) override {
         nodep->dtypeSetUInt64();  // A pointer, but not that it matters
     }
diff --git a/src/verilog.l b/src/verilog.l
index b0a6d01e3..07f165c92 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -281,7 +281,9 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "$test$plusargs"      { FL; return yD_TESTPLUSARGS; }
   "$time"               { FL; return yD_TIME; }
   "$timeformat"         { FL; return yD_TIMEFORMAT; }
+  "$timeprecision"      { FL; return yD_TIMEPRECISION; }
   "$timeskew"           { FL; return yaTIMINGSPEC; }
+  "$timeunit"           { FL; return yD_TIMEUNIT; }
   "$typename"           { FL; return yD_TYPENAME; }
   "$ungetc"             { FL; return yD_UNGETC; }
   "$urandom"            { FL; return yD_URANDOM; }
diff --git a/src/verilog.y b/src/verilog.y
index 330cd4c0f..6ad8d718c 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -876,6 +876,8 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
 %token<fl>              yD_TESTPLUSARGS "$test$plusargs"
 %token<fl>              yD_TIME         "$time"
 %token<fl>              yD_TIMEFORMAT   "$timeformat"
+%token<fl>              yD_TIMEPRECISION "$timeprecision"
+%token<fl>              yD_TIMEUNIT     "$timeunit"
 %token<fl>              yD_TYPENAME     "$typename"
 %token<fl>              yD_UNGETC       "$ungetc"
 %token<fl>              yD_UNIT         "$unit"
@@ -3861,10 +3863,11 @@ system_t_call<nodep>:           // IEEE: system_tf_call (as task)
         |       yD_MONITOROFF parenE                    { $$ = new AstMonitorOff($1, true); }
         |       yD_MONITORON parenE                     { $$ = new AstMonitorOff($1, false); }
         //
-        |       yD_PRINTTIMESCALE                       { $$ = new AstPrintTimeScale($1); }
-        |       yD_PRINTTIMESCALE '(' ')'               { $$ = new AstPrintTimeScale($1); }
-        |       yD_PRINTTIMESCALE '(' idClassSel ')'    { $$ = new AstPrintTimeScale($1); DEL($3); }
-        |       yD_TIMEFORMAT '(' expr ',' expr ',' expr ',' expr ')'   { $$ = new AstTimeFormat($1, $3, $5, $7, $9); }
+        |       yD_PRINTTIMESCALE                       { $$ = new AstPrintTimeScale{$1}; }
+        |       yD_PRINTTIMESCALE '(' ')'               { $$ = new AstPrintTimeScale{$1}; }
+        |       yD_PRINTTIMESCALE '(' idClassSel ')'    { $$ = new AstPrintTimeScale{$1}; DEL($3); }
+        |       yD_TIMEFORMAT '(' expr ',' expr ',' expr ',' expr ')'
+                        { $$ = new AstTimeFormat{$1, $3, $5, $7, $9}; }
         //
         |       yD_READMEMB '(' expr ',' idClassSel ')'                         { $$ = new AstReadMem($1,false,$3,$5,nullptr,nullptr); }
         |       yD_READMEMB '(' expr ',' idClassSel ',' expr ')'                { $$ = new AstReadMem($1,false,$3,$5,$7,nullptr); }
@@ -3994,6 +3997,12 @@ system_f_call_or_t<nodeExprp>:      // IEEE: part of system_tf_call (can be task
         |       yD_TANH '(' expr ')'                    { $$ = new AstTanhD($1,$3); }
         |       yD_TESTPLUSARGS '(' expr ')'            { $$ = new AstTestPlusArgs($1, $3); }
         |       yD_TIME parenE                          { $$ = new AstTime{$1, VTimescale{VTimescale::NONE}}; }
+        |       yD_TIMEPRECISION                        { $$ = new AstTimePrecision{$1}; }
+        |       yD_TIMEPRECISION '(' ')'                { $$ = new AstTimePrecision{$1}; }
+        |       yD_TIMEPRECISION '(' idClassSel ')'     { $$ = new AstTimePrecision{$1}; DEL($3); }
+        |       yD_TIMEUNIT                             { $$ = new AstTimeUnit{$1}; }
+        |       yD_TIMEUNIT '(' ')'                     { $$ = new AstTimeUnit{$1}; }
+        |       yD_TIMEUNIT '(' idClassSel ')'          { $$ = new AstTimeUnit{$1}; DEL($3); }
         |       yD_TYPENAME '(' exprOrDataType ')'      { $$ = new AstAttrOf($1, VAttrType::TYPENAME, $3); }
         |       yD_UNGETC '(' expr ',' expr ')'         { $$ = new AstFUngetC($1, $5, $3); }  // Arg swap to file first
         |       yD_UNPACKED_DIMENSIONS '(' exprOrDataType ')'   { $$ = new AstAttrOf($1,VAttrType::DIM_UNPK_DIMENSIONS,$3); }
diff --git a/test_regress/t/t_time_timeunit.pl b/test_regress/t/t_time_timeunit.pl
new file mode 100755
index 000000000..4e42b8db0
--- /dev/null
+++ b/test_regress/t/t_time_timeunit.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+
+1;
diff --git a/test_regress/t/t_time_timeunit.v b/test_regress/t/t_time_timeunit.v
new file mode 100644
index 000000000..e75d5ab98
--- /dev/null
+++ b/test_regress/t/t_time_timeunit.v
@@ -0,0 +1,26 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under The Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+module t;
+
+   timeunit 1ns;
+   timeprecision 1ps;
+
+   initial begin
+      `checkd($timeunit, -9);
+      `checkd($timeunit(), -9);
+      `checkd($timeunit(t), -9);
+
+      `checkd($timeprecision, -12);
+      `checkd($timeprecision(), -12);
+      `checkd($timeprecision(t), -12);
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

From d41efb189d82b4344f4ca0a828ca6decca55c1a3 Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Thu, 17 Nov 2022 19:26:45 +0100
Subject: [PATCH 049/156] Fix pre/postincrement operations (#3744) (#3756)

---
 src/V3LinkInc.cpp                     | 19 ++++++----------
 src/V3Width.cpp                       |  4 ++--
 test_regress/t/t_delay_incr.pl        | 22 ++++++++++++++++++
 test_regress/t/t_delay_incr.v         | 27 ++++++++++++++++++++++
 test_regress/t/t_delay_incr_timing.pl | 32 +++++++++++++++++++++++++++
 5 files changed, 90 insertions(+), 14 deletions(-)
 create mode 100755 test_regress/t/t_delay_incr.pl
 create mode 100644 test_regress/t/t_delay_incr.v
 create mode 100755 test_regress/t/t_delay_incr_timing.pl

diff --git a/src/V3LinkInc.cpp b/src/V3LinkInc.cpp
index 6f1fe68f0..d4b486e67 100644
--- a/src/V3LinkInc.cpp
+++ b/src/V3LinkInc.cpp
@@ -85,8 +85,6 @@ private:
         } else {
             nodep->v3fatalSrc("Unknown InsertMode");
         }
-        m_insMode = IM_AFTER;
-        m_insStmtp = newp;
     }
 
     // VISITORS
@@ -259,21 +257,18 @@ private:
         if (VN_IS(nodep, PreAdd) || VN_IS(nodep, PreSub)) {
             // PreAdd/PreSub operations
             // Immediately after declaration - increment it by one
-            m_insStmtp->addHereThisAsNext(
-                new AstAssign(fl, new AstVarRef(fl, varp, VAccess::WRITE), operp));
+            varp->addNextHere(new AstAssign{fl, new AstVarRef{fl, varrefp->varp(), VAccess::WRITE},
+                                            new AstVarRef{fl, varp, VAccess::READ}});
             // Immediately after incrementing - assign it to the original variable
-            m_insStmtp->addHereThisAsNext(
-                new AstAssign(fl, new AstVarRef(fl, varrefp->varp(), VAccess::WRITE),
-                              new AstVarRef(fl, varp, VAccess::READ)));
+            varp->addNextHere(new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE}, operp});
         } else {
             // PostAdd/PostSub operations
             // assign the original variable to the temporary one
-            m_insStmtp->addHereThisAsNext(
-                new AstAssign(fl, new AstVarRef(fl, varp, VAccess::WRITE),
-                              new AstVarRef(fl, varrefp->varp(), VAccess::READ)));
+            varp->addNextHere(
+                new AstAssign{fl, new AstVarRef{fl, varrefp->varp(), VAccess::WRITE}, operp});
             // Increment the original variable by one
-            m_insStmtp->addHereThisAsNext(
-                new AstAssign(fl, new AstVarRef(fl, varrefp->varp(), VAccess::WRITE), operp));
+            varp->addNextHere(new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE},
+                                            new AstVarRef{fl, varrefp->varp(), VAccess::READ}});
         }
 
         // Replace the node with the temporary
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index fff0970b9..2fb61d8c0 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -614,7 +614,7 @@ private:
         if (nodep->fileline()->timingOn()) {
             if (v3Global.opt.timing().isSetTrue()) {
                 userIterate(nodep->lhsp(), WidthVP{nullptr, BOTH}.p());
-                iterateNull(nodep->stmtsp());
+                iterateAndNextNull(nodep->stmtsp());
                 return;
             } else if (v3Global.opt.timing().isSetFalse()) {
                 nodep->v3warn(STMTDLY, "Ignoring delay on this statement due to --no-timing");
@@ -624,7 +624,7 @@ private:
                     "Use --timing or --no-timing to specify how delays should be handled");
             }
         }
-        if (nodep->stmtsp()) nodep->addNextHere(nodep->stmtsp()->unlinkFrBack());
+        if (nodep->stmtsp()) nodep->addNextHere(nodep->stmtsp()->unlinkFrBackWithNext());
         VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
     }
     void visit(AstFork* nodep) override {
diff --git a/test_regress/t/t_delay_incr.pl b/test_regress/t/t_delay_incr.pl
new file mode 100755
index 000000000..3e8a3c919
--- /dev/null
+++ b/test_regress/t/t_delay_incr.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['-Wno-STMTDLY -Wno-ASSIGNDLY --no-timing'],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_delay_incr.v b/test_regress/t/t_delay_incr.v
new file mode 100644
index 000000000..2ba72abea
--- /dev/null
+++ b/test_regress/t/t_delay_incr.v
@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2003 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`timescale 100ns/1ns
+
+module t;
+   int   ia;
+   int   ib;
+
+   initial begin
+      ia = 0;
+      #1 ib = ++ia;
+      #1
+        if (ia !== ib) $stop;
+
+      #1 ib = ia++;
+      #1
+        if (ia == ib) $stop;
+      #10;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
diff --git a/test_regress/t/t_delay_incr_timing.pl b/test_regress/t/t_delay_incr_timing.pl
new file mode 100755
index 000000000..6b78f49a3
--- /dev/null
+++ b/test_regress/t/t_delay_incr_timing.pl
@@ -0,0 +1,32 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+$Self->{main_time_multiplier} = 10e-7 / 10e-9;
+
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    top_filename("t/t_delay_incr.v");
+
+    compile(
+        timing_loop => 1,
+        verilator_flags2 => ['--timing -Wno-ZERODLY'],
+        );
+
+    execute(
+        check_finished => 1,
+        );
+}
+
+ok(1);
+1;

From 96306b763018484c1297ae8672b53b640f3d27ad Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 17 Nov 2022 18:15:38 -0500
Subject: [PATCH 050/156] Tests: Update t_class_class

---
 test_regress/t/t_class_class.v | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/test_regress/t/t_class_class.v b/test_regress/t/t_class_class.v
index 7453ffac1..bf1ae7da4 100644
--- a/test_regress/t/t_class_class.v
+++ b/test_regress/t/t_class_class.v
@@ -6,12 +6,12 @@
 
 // Note UVM internals do not require classes-in-classes
 package P;
-class Cls;
-   int imembera;
-   int imemberb;
+class Cls #(type STORE_T=string);
+   STORE_T imembera;
+   STORE_T imemberb;
    class SubCls;
-      int smembera;
-      int smemberb;
+      STORE_T smembera;
+      STORE_T smemberb;
       // TODO put extern function here or in t_class_extern.v to check link
    endclass : SubCls
    SubCls sc;
@@ -19,7 +19,7 @@ endclass : Cls
 endpackage : P
 
 module t (/*AUTOARG*/);
-   P::Cls c;
+   P::Cls#(int) c;
    initial begin
       c = new;
       c.imembera = 10;

From e8a1e4745ccc061f53b59e7606d22207639f7142 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 17 Nov 2022 19:12:54 -0500
Subject: [PATCH 051/156] Support $stacktrace

---
 docs/guide/extensions.rst      | 11 +++++++++++
 include/verilated.cpp          | 31 +++++++++++++++++++++++++++++++
 include/verilated_funcs.h      |  2 ++
 src/V3AstNodeExpr.h            | 19 +++++++++++++++++++
 src/V3AstNodeOther.h           | 14 ++++++++++++++
 src/V3EmitCFunc.h              |  6 ++++++
 src/V3Width.cpp                |  3 +++
 src/verilog.l                  |  1 +
 src/verilog.y                  |  3 +++
 test_regress/t/t_stacktrace.pl | 22 ++++++++++++++++++++++
 test_regress/t/t_stacktrace.v  | 27 +++++++++++++++++++++++++++
 11 files changed, 139 insertions(+)
 create mode 100755 test_regress/t/t_stacktrace.pl
 create mode 100644 test_regress/t/t_stacktrace.v

diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst
index 6aad4c6e6..1e8c629f7 100644
--- a/docs/guide/extensions.rst
+++ b/docs/guide/extensions.rst
@@ -554,3 +554,14 @@ or "`ifdef`"'s may break other tools.
 
    Re-enable waveform tracing for all future signals or instances that are
    declared.
+
+.. option:: $stacktrace
+
+   Called as a task, orint a stack trace.  Called as a function, return a
+   string with a stack trace.  This relies on the C++ system trace, which
+   may give less meaningful results if the model was not compiled with
+   debug symbols.  Also the data represents the C++ stack, the
+   SystemVerilog functions/tasks involved may be renamed and/or inlined
+   before becoming the C++ functions that may be visible in the stack
+   trace.  This extension is experimental and may be removed without
+   deprecation.
diff --git a/include/verilated.cpp b/include/verilated.cpp
index 8ca1c4781..0749ff68e 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -67,6 +67,10 @@
 #if defined(_WIN32) || defined(__MINGW32__)
 # include <direct.h>  // mkdir
 #endif
+#ifdef __linux__
+# include <execinfo.h>
+# define _VL_HAVE_STACKTRACE
+#endif
 
 #include "verilated_threads.h"
 // clang-format on
@@ -1623,6 +1627,33 @@ IData VL_FREAD_I(int width, int array_lsb, int array_size, void* memp, IData fpi
     return read_count;
 }
 
+std::string VL_STACKTRACE_N() VL_MT_SAFE {
+    static VerilatedMutex s_stackTraceMutex;
+    const VerilatedLockGuard lock{s_stackTraceMutex};
+
+    constexpr int BT_BUF_SIZE = 100;
+    void *buffer[BT_BUF_SIZE];
+    int nptrs = 0;
+    char ** strings = nullptr;
+
+#ifdef _VL_HAVE_STACKTRACE
+    nptrs = backtrace(buffer, BT_BUF_SIZE);
+    strings = backtrace_symbols(buffer, nptrs);
+#endif
+
+    if (!strings) return "Unable to backtrace\n";
+
+    std::string out = "Backtrace:\n";
+    for (int j = 0; j < nptrs; j++) out += std::string{strings[j]} + std::string{"\n"};
+    free(strings);
+    return out;
+}
+
+void VL_STACKTRACE() VL_MT_SAFE {
+    const std::string out = VL_STACKTRACE_N();
+    VL_PRINTF("%s", out.c_str());
+}
+
 IData VL_SYSTEM_IQ(QData lhs) VL_MT_SAFE {
     VlWide<VL_WQ_WORDS_E> lhsw;
     VL_SET_WQ(lhsw, lhs);
diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h
index 1f26f56af..0252411aa 100644
--- a/include/verilated_funcs.h
+++ b/include/verilated_funcs.h
@@ -138,6 +138,8 @@ extern void VL_SFORMAT_X(int obits, IData& destr, const char* formatp, ...);
 extern void VL_SFORMAT_X(int obits, QData& destr, const char* formatp, ...);
 extern void VL_SFORMAT_X(int obits, void* destp, const char* formatp, ...);
 
+extern void VL_STACKTRACE() VL_MT_SAFE;
+extern std::string VL_STACKTRACE_N() VL_MT_SAFE;
 extern IData VL_SYSTEM_IW(int lhswords, WDataInP const lhsp);
 extern IData VL_SYSTEM_IQ(QData lhs);
 inline IData VL_SYSTEM_II(IData lhs) VL_MT_SAFE { return VL_SYSTEM_IQ(lhs); }
diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index 608e0db31..b44af081a 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -1525,6 +1525,25 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
+class AstStackTraceF final : public AstNodeExpr {
+    // $stacktrace used as function
+public:
+    AstStackTraceF(FileLine* fl)
+        : ASTGEN_SUPER_StackTraceF(fl) {
+        dtypeSetString();
+    }
+    ASTGEN_MEMBERS_AstStackTraceF;
+    string verilogKwd() const override { return "$stacktrace"; }
+    string emitVerilog() override { return verilogKwd(); }
+    string emitC() override { return "VL_STACKTRACE_N()"; }
+    bool isGateOptimizable() const override { return false; }
+    bool isPredictOptimizable() const override { return false; }
+    bool isPure() const override { return false; }
+    bool isOutputter() const override { return true; }
+    bool isUnlikely() const override { return true; }
+    bool cleanOut() const override { return true; }
+    bool same(const AstNode* /*samep*/) const override { return true; }
+};
 class AstSysIgnore final : public AstNodeExpr {
     // @astgen op1 := exprsp : List[AstNode] // Expressions to output (???)
 public:
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index 8d5009bea..ae9a9639a 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -3092,6 +3092,20 @@ public:
     int instrCount() const override { return INSTR_COUNT_PLI; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
+class AstStackTraceT final : public AstNodeStmt {
+    // $stacktrace used as task
+public:
+    AstStackTraceT(FileLine* fl)
+        : ASTGEN_SUPER_StackTraceT(fl) { }
+    ASTGEN_MEMBERS_AstStackTraceT;
+    string verilogKwd() const override { return "$stacktrace"; }
+    bool isGateOptimizable() const override { return false; }
+    bool isPredictOptimizable() const override { return false; }
+    bool isPure() const override { return false; }
+    bool isOutputter() const override { return true; }
+    bool isUnlikely() const override { return true; }
+    bool same(const AstNode* /*samep*/) const override { return true; }
+};
 class AstStmtExpr final : public AstNodeStmt {
     // Expression in statement position
     // @astgen op1 := exprp : AstNodeExpr
diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h
index 50b2f55c6..82a5b605c 100644
--- a/src/V3EmitCFunc.h
+++ b/src/V3EmitCFunc.h
@@ -775,6 +775,12 @@ public:
         iterateAndNextNull(nodep->lhsp());
         if (!nodep->lhsp()->isWide()) puts(";");
     }
+    void visit(AstStackTraceF* nodep) override {
+        puts("VL_STACKTRACE_N()");
+    }
+    void visit(AstStackTraceT* nodep) override {
+        puts("VL_STACKTRACE();\n");
+    }
     void visit(AstSystemT* nodep) override {
         puts("(void)VL_SYSTEM_I");
         emitIQW(nodep->lhsp());
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 2fb61d8c0..bfd03e8ef 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -4676,6 +4676,9 @@ private:
             userIterateAndNext(nodep->exprsp(), WidthVP(SELF, BOTH).p());
         }
     }
+    void visit(AstStackTraceF* nodep) override {
+        nodep->dtypeSetString();
+    }
     void visit(AstSysIgnore* nodep) override {
         userIterateAndNext(nodep->exprsp(), WidthVP(SELF, BOTH).p());
     }
diff --git a/src/verilog.l b/src/verilog.l
index 07f165c92..b5cdd53ca 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -265,6 +265,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "$skew"               { FL; return yaTIMINGSPEC; }
   "$sqrt"               { FL; return yD_SQRT; }
   "$sscanf"             { FL; return yD_SSCANF; }
+  "$stacktrace"         { FL; return yD_STACKTRACE; }
   "$stime"              { FL; return yD_STIME; }
   "$stop"               { FL; return yD_STOP; }
   "$strobe"             { FL; return yD_STROBE; }
diff --git a/src/verilog.y b/src/verilog.y
index 6ad8d718c..9c977f542 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -860,6 +860,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
 %token<fl>              yD_SQRT         "$sqrt"
 %token<fl>              yD_SSCANF       "$sscanf"
 %token<fl>              yD_STABLE       "$stable"
+%token<fl>              yD_STACKTRACE   "$stacktrace"
 %token<fl>              yD_STIME        "$stime"
 %token<fl>              yD_STOP         "$stop"
 %token<fl>              yD_STROBE       "$strobe"
@@ -3788,6 +3789,7 @@ system_t_call<nodep>:           // IEEE: system_tf_call (as task)
         |       yD_DUMPON '(' expr ')'                  { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::ON); DEL($3); }
         //
         |       yD_C '(' cStrList ')'                   { $$ = (v3Global.opt.ignc() ? nullptr : new AstUCStmt($1,$3)); }
+        |       yD_STACKTRACE parenE                    { $$ = new AstStackTraceT{$1}; }
         |       yD_SYSTEM '(' expr ')'                  { $$ = new AstSystemT($1, $3); }
         //
         |       yD_EXIT parenE                          { $$ = new AstFinish($1); }
@@ -3897,6 +3899,7 @@ system_f_call<nodeExprp>:           // IEEE: system_tf_call (as func)
         //
         |       yD_C '(' cStrList ')'                   { $$ = (v3Global.opt.ignc() ? nullptr : new AstUCFunc($1,$3)); }
         |       yD_CAST '(' expr ',' expr ')'           { $$ = new AstCastDynamic($1, $5, $3); }
+        |       yD_STACKTRACE parenE                    { $$ = new AstStackTraceF{$1}; }
         |       yD_SYSTEM  '(' expr ')'                 { $$ = new AstSystemF($1,$3); }
         //
         |       system_f_call_or_t                      { $$ = $1; }
diff --git a/test_regress/t/t_stacktrace.pl b/test_regress/t/t_stacktrace.pl
new file mode 100755
index 000000000..4e42b8db0
--- /dev/null
+++ b/test_regress/t/t_stacktrace.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+
+1;
diff --git a/test_regress/t/t_stacktrace.v b/test_regress/t/t_stacktrace.v
new file mode 100644
index 000000000..c4662bf82
--- /dev/null
+++ b/test_regress/t/t_stacktrace.v
@@ -0,0 +1,27 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under The Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   task t;
+      // verilator no_inline_task
+      string trace;
+
+      $display("== Trace Func");
+      trace = $stacktrace();
+      if (trace == "") $stop;
+      $display("%s", trace);
+
+      $display("== Trace Task");
+      $stacktrace;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   endtask
+
+   initial t();
+
+endmodule

From cd8528e83b79774892cc147afb22103007a4cc77 Mon Sep 17 00:00:00 2001
From: github action <action@example.com>
Date: Fri, 18 Nov 2022 00:14:05 +0000
Subject: [PATCH 052/156] Apply 'make format'

---
 include/verilated.cpp | 4 ++--
 src/V3AstNodeOther.h  | 2 +-
 src/V3EmitCFunc.h     | 8 ++------
 src/V3Width.cpp       | 4 +---
 4 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/include/verilated.cpp b/include/verilated.cpp
index 0749ff68e..5105bca90 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -1632,9 +1632,9 @@ std::string VL_STACKTRACE_N() VL_MT_SAFE {
     const VerilatedLockGuard lock{s_stackTraceMutex};
 
     constexpr int BT_BUF_SIZE = 100;
-    void *buffer[BT_BUF_SIZE];
+    void* buffer[BT_BUF_SIZE];
     int nptrs = 0;
-    char ** strings = nullptr;
+    char** strings = nullptr;
 
 #ifdef _VL_HAVE_STACKTRACE
     nptrs = backtrace(buffer, BT_BUF_SIZE);
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index ae9a9639a..deb657f65 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -3096,7 +3096,7 @@ class AstStackTraceT final : public AstNodeStmt {
     // $stacktrace used as task
 public:
     AstStackTraceT(FileLine* fl)
-        : ASTGEN_SUPER_StackTraceT(fl) { }
+        : ASTGEN_SUPER_StackTraceT(fl) {}
     ASTGEN_MEMBERS_AstStackTraceT;
     string verilogKwd() const override { return "$stacktrace"; }
     bool isGateOptimizable() const override { return false; }
diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h
index 82a5b605c..5ab0211af 100644
--- a/src/V3EmitCFunc.h
+++ b/src/V3EmitCFunc.h
@@ -775,12 +775,8 @@ public:
         iterateAndNextNull(nodep->lhsp());
         if (!nodep->lhsp()->isWide()) puts(";");
     }
-    void visit(AstStackTraceF* nodep) override {
-        puts("VL_STACKTRACE_N()");
-    }
-    void visit(AstStackTraceT* nodep) override {
-        puts("VL_STACKTRACE();\n");
-    }
+    void visit(AstStackTraceF* nodep) override { puts("VL_STACKTRACE_N()"); }
+    void visit(AstStackTraceT* nodep) override { puts("VL_STACKTRACE();\n"); }
     void visit(AstSystemT* nodep) override {
         puts("(void)VL_SYSTEM_I");
         emitIQW(nodep->lhsp());
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index bfd03e8ef..9b7e67920 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -4676,9 +4676,7 @@ private:
             userIterateAndNext(nodep->exprsp(), WidthVP(SELF, BOTH).p());
         }
     }
-    void visit(AstStackTraceF* nodep) override {
-        nodep->dtypeSetString();
-    }
+    void visit(AstStackTraceF* nodep) override { nodep->dtypeSetString(); }
     void visit(AstSysIgnore* nodep) override {
         userIterateAndNext(nodep->exprsp(), WidthVP(SELF, BOTH).p());
     }

From 749aab0a56602bc4fa8b1cc2884bc3f699126316 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 17 Nov 2022 20:37:51 -0500
Subject: [PATCH 053/156] Support triple-quote blocks.

---
 docs/guide/extensions.rst             |  6 +++++
 src/V3ParseGrammar.cpp                |  2 +-
 src/V3PreLex.l                        | 39 ++++++++++++++++++++-------
 src/verilog.l                         | 16 ++++++++++-
 test_regress/t/t_display_qqq.out      |  5 ++++
 test_regress/t/t_display_qqq.pl       | 23 ++++++++++++++++
 test_regress/t/t_display_qqq.v        | 17 ++++++++++++
 test_regress/t/t_preproc.out          | 16 ++++++++++-
 test_regress/t/t_preproc.v            | 12 +++++++++
 test_regress/t/t_preproc_comments.out | 16 ++++++++++-
 test_regress/t/t_preproc_eof6_bad.out |  2 ++
 test_regress/t/t_preproc_eof6_bad.pl  | 19 +++++++++++++
 test_regress/t/t_preproc_eof6_bad.v   |  7 +++++
 13 files changed, 167 insertions(+), 13 deletions(-)
 create mode 100644 test_regress/t/t_display_qqq.out
 create mode 100755 test_regress/t/t_display_qqq.pl
 create mode 100644 test_regress/t/t_display_qqq.v
 create mode 100644 test_regress/t/t_preproc_eof6_bad.out
 create mode 100755 test_regress/t/t_preproc_eof6_bad.pl
 create mode 100644 test_regress/t/t_preproc_eof6_bad.v

diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst
index 1e8c629f7..5cb0cf572 100644
--- a/docs/guide/extensions.rst
+++ b/docs/guide/extensions.rst
@@ -25,6 +25,12 @@ or "`ifdef`"'s may break other tools.
 
    This will report an error when encountered, like C++'s #error.
 
+.. option:: """ [string] """
+
+   A triple-quoted block specifies a string which may include newlines and
+   single quotes.  This extension is experimental and may be removed
+   without deprecation.
+
 .. option:: $c([string], ...);
 
    The string will be embedded directly in the output C++ code at the point
diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp
index 8d495716a..0c0fbf969 100644
--- a/src/V3ParseGrammar.cpp
+++ b/src/V3ParseGrammar.cpp
@@ -298,7 +298,7 @@ string V3ParseGrammar::deQuote(FileLine* fileline, string text) {
         } else if (*cp == '\\') {
             quoted = true;
             octal_digits = 0;
-        } else if (*cp != '"') {
+        } else {
             newtext += *cp;
         }
     }
diff --git a/src/V3PreLex.l b/src/V3PreLex.l
index bc1dda03d..e423341f2 100644
--- a/src/V3PreLex.l
+++ b/src/V3PreLex.l
@@ -65,23 +65,24 @@ static void appendDefValue(const char* t, size_t l) { LEXP->appendDefValue(t, l)
 /**********************************************************************/
 %}
 
-%x CMTONEM
+%x ARGMODE
 %x CMTBEGM
 %x CMTMODE
-%x STRMODE
-%x DEFFPAR
-%x DEFFORM
-%x DEFVAL
+%x CMTONEM
 %x DEFCMT
-%x STRIFY
-%x ARGMODE
+%x DEFFORM
+%x DEFFPAR
+%x DEFVAL
+%x ENCBASE64
 %x INCMODE
-%x PRTMODE
 %x PRAGMA
 %x PRAGMAERR
 %x PRAGMAPRT
 %x PRAGMAPRTERR
-%x ENCBASE64
+%x PRTMODE
+%x QQQMODE
+%x STRIFY
+%x STRMODE
 
 /* drop: Drop Ctrl-Z - can't pass thru or may EOF the output too soon */
 
@@ -262,6 +263,23 @@ bom             [\357\273\277]
                               yyleng=0; FL_BRK;
                           } else return VP_STRING; }
 
+        /* Pass-through quote-quote-quote */
+<INITIAL>{quote}{quote}{quote}        { yy_push_state(QQQMODE); yymore(); }
+<QQQMODE><<EOF>>        { FL_FWDC; linenoInc(); yyerrorf("EOF in unterminated \"\"\" string");
+                          yyleng=0; return VP_EOF_ERROR; }
+<QQQMODE>{crnl}         { FL_FWDC; linenoInc(); yymore(); }
+<QQQMODE>{word}         { yymore(); }
+<QQQMODE>[^\"\\]        { yymore(); }
+<QQQMODE>[\\]{crnl}     { linenoInc(); yymore(); }
+<QQQMODE>[\\]{wsn}+{crnl}  { LEXP->warnBackslashSpace(); yyless(1); }
+<QQQMODE>[\\].          { yymore(); }
+<QQQMODE>.              { yymore(); }
+<QQQMODE>{quote}{quote}{quote}        { FL_FWDC; yy_pop_state();
+                          if (LEXP->m_parenLevel || LEXP->m_defQuote) {
+                              LEXP->m_defQuote=false; appendDefValue(yytext, yyleng);
+                              yyleng=0; FL_BRK;
+                          } else return VP_STRING; }
+
         /* Stringification */
 <INITIAL>{tickquote}    { FL_FWDC; yy_push_state(STRIFY); return VP_STRIFY; }
 <STRIFY><<EOF>>         { FL_FWDC; linenoInc(); yyerrorf("EOF in unterminated '\"");
@@ -319,6 +337,7 @@ bom             [\357\273\277]
 <DEFFORM>[\\]{wsn}+{crnl}  { LEXP->warnBackslashSpace(); yyless(1); }
 <DEFFORM>[\\]{crnl}     { FL_FWDC; linenoInc(); appendDefValue((char*)"\\\n", 2); FL_BRK; }  /* Include return so can maintain output line count */
 <DEFFORM>{quote}        { LEXP->m_defQuote=true; yy_push_state(STRMODE); yymore(); }  /* Legal only in default values */
+<DEFFORM>{quote}{quote}{quote}   { LEXP->m_defQuote=true; yy_push_state(QQQMODE); yymore(); }  /* Legal only in default values */
 <DEFFORM>"`\\`\""       { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; }  /* Maybe illegal, otherwise in default value */
 <DEFFORM>{tickquote}    { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; }  /* Maybe illegal, otherwise in default value */
 <DEFFORM>[{\[]          { FL_FWDC; LEXP->m_formalLevel++; appendDefValue(yytext, yyleng); FL_BRK; }
@@ -337,6 +356,7 @@ bom             [\357\273\277]
 <DEFVAL>[\\]{wsn}+{crnl}  { LEXP->warnBackslashSpace(); yyless(1); }
 <DEFVAL>[\\]{crnl}      { FL_FWDC; linenoInc(); appendDefValue((char*)"\\\n", 2); FL_BRK; }  /* Return, AND \ is part of define value */
 <DEFVAL>{quote}         { LEXP->m_defQuote = true; yy_push_state(STRMODE); yymore(); }
+<DEFVAL>{quote}{quote}{quote}   { LEXP->m_defQuote = true; yy_push_state(QQQMODE); yymore(); }
 <DEFVAL>[^\/\*\n\r\\\"]+        |
 <DEFVAL>[\\][^\n\r]     |
 <DEFVAL>.               { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; }
@@ -364,6 +384,7 @@ bom             [\357\273\277]
                           yyleng = 0; return VP_EOF_ERROR; }
 <ARGMODE>{crnl}         { FL_FWDC; linenoInc(); yytext=(char*)"\n"; yyleng=1; return VP_WHITE; }
 <ARGMODE>{quote}        { yy_push_state(STRMODE); yymore(); }
+<ARGMODE>{quote}{quote}{quote}    { yy_push_state(QQQMODE); yymore(); }
 <ARGMODE>"`\\`\""       { FL_FWDC; appendDefValue(yytext, yyleng); FL_BRK; }  /* Literal text */
 <ARGMODE>{tickquote}    { FL_FWDC; yy_push_state(STRIFY); return VP_STRIFY; }
 <ARGMODE>[{\[]          { FL_FWDC; LEXP->m_parenLevel++; appendDefValue(yytext, yyleng); FL_BRK; }
diff --git a/src/verilog.l b/src/verilog.l
index b5cdd53ca..96e1d5718 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -79,7 +79,7 @@ static double lexParseDouble(FileLine* fl, const char* textp, size_t length) {
 %o 25000
 
 %s V95 V01NC V01C V05 S05 S09 S12 S17
-%s STRING ATTRMODE TABLE
+%s ATTRMODE QQQ STRING TABLE
 %s VA5 SAX VLT
 %s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
 %s IGNORE
@@ -886,6 +886,7 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
                           return yaSTRING;
                         }
   \"                    { yy_push_state(STRING); yymore(); }
+  \"\"\"                { yy_push_state(QQQ); yymore(); }
   {vnum}                {
                           /* "# 1'b0" is a delay value so must lex as "#" "1" "'b0" */
                           if (PARSEP->lexPrevToken()=='#') {
@@ -940,6 +941,19 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
 <STRING>{word}          { yymore(); }
 <STRING>.               { yymore(); }
 
+  /************************************************************************/
+  /* """ */
+<QQQ><<EOF>>            { FL; yylval.fl->v3error("EOF in unterminated \"\"\" string");
+                          yyleng = 0; yy_pop_state(); FL_BRK; yyterminate(); }
+<QQQ>\\.                { yymore(); }
+<QQQ>\n                 { yymore(); }
+<QQQ>\"\"\"             { yy_pop_state();
+                          FL; yylval.strp = PARSEP->newString(yytext + 3, yyleng - 6);
+                          return yaSTRING; }
+<QQQ>\"                 { yymore(); }
+<QQQ>{word}             { yymore(); }
+<QQQ>.                  { yymore(); }
+
   /************************************************************************/
   /* Attributes */
 <ATTRMODE>{crnl}        { yymore(); }
diff --git a/test_regress/t/t_display_qqq.out b/test_regress/t/t_display_qqq.out
new file mode 100644
index 000000000..de4991997
--- /dev/null
+++ b/test_regress/t/t_display_qqq.out
@@ -0,0 +1,5 @@
+First "quoted"
+second
+third
+fourth
+*-* All Finished *-*
diff --git a/test_regress/t/t_display_qqq.pl b/test_regress/t/t_display_qqq.pl
new file mode 100755
index 000000000..3db494e80
--- /dev/null
+++ b/test_regress/t/t_display_qqq.pl
@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+
+1;
diff --git a/test_regress/t/t_display_qqq.v b/test_regress/t/t_display_qqq.v
new file mode 100644
index 000000000..1b5568269
--- /dev/null
+++ b/test_regress/t/t_display_qqq.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   initial begin
+      $display("""First "quoted"\nsecond\
+third
+fourth""");
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
diff --git a/test_regress/t/t_preproc.out b/test_regress/t/t_preproc.out
index 34e54dbe2..1aa204271 100644
--- a/test_regress/t/t_preproc.out
+++ b/test_regress/t/t_preproc.out
@@ -1005,6 +1005,20 @@ endmodule
 
 `line 695 "t/t_preproc.v" 0
  
+
+"""First line with "quoted"\nSecond line\
+Third line"""
+"""First line
+Second line"""
+
+`line 702 "t/t_preproc.v" 0
+ 
+ 
+"""QQQ defform"""
+"""QQQ defval"""
+
+`line 707 "t/t_preproc.v" 0
+ 
  
    
 predef 0 0
@@ -1026,4 +1040,4 @@ predef 2 2
  
  
 
-`line 717 "t/t_preproc.v" 2
+`line 729 "t/t_preproc.v" 2
diff --git a/test_regress/t/t_preproc.v b/test_regress/t/t_preproc.v
index c804ad797..527bea0d5 100644
--- a/test_regress/t/t_preproc.v
+++ b/test_regress/t/t_preproc.v
@@ -692,6 +692,18 @@ endmodule
 `define stringify(text) `"text`"
 `stringify(`NOT_DEFINED_STR)
 
+//======================================================================
+
+"""First line with "quoted"\nSecond line\
+Third line"""
+"""First line
+Second line"""
+
+`define QQQ """QQQ defform"""
+`define QQQS(x) x
+`QQQ
+`QQQS("""QQQ defval""")
+
 //======================================================================
 // IEEE mandated predefines
 `undefineall  // undefineall should have no effect on these
diff --git a/test_regress/t/t_preproc_comments.out b/test_regress/t/t_preproc_comments.out
index 7777d4332..4c6a565ab 100644
--- a/test_regress/t/t_preproc_comments.out
+++ b/test_regress/t/t_preproc_comments.out
@@ -1010,6 +1010,20 @@ endmodule
 
 `line 695 "t/t_preproc.v" 0
 //====================================================================== 
+
+"""First line with "quoted"\nSecond line\
+Third line"""
+"""First line
+Second line"""
+
+`line 702 "t/t_preproc.v" 0
+ 
+ 
+"""QQQ defform"""
+"""QQQ defval"""
+
+`line 707 "t/t_preproc.v" 0
+//====================================================================== 
 // IEEE mandated predefines 
   // undefineall should have no effect on these 
 predef 0 0
@@ -1031,4 +1045,4 @@ predef 2 2
 // After `undefineall above, for testing --dump-defines 
  
 
-`line 717 "t/t_preproc.v" 2
+`line 729 "t/t_preproc.v" 2
diff --git a/test_regress/t/t_preproc_eof6_bad.out b/test_regress/t/t_preproc_eof6_bad.out
new file mode 100644
index 000000000..7449bf833
--- /dev/null
+++ b/test_regress/t/t_preproc_eof6_bad.out
@@ -0,0 +1,2 @@
+%Error: t/t_preproc_eof6_bad.v:10:1: EOF in unterminated """ string
+%Error: Exiting due to
diff --git a/test_regress/t/t_preproc_eof6_bad.pl b/test_regress/t/t_preproc_eof6_bad.pl
new file mode 100755
index 000000000..a60503a1f
--- /dev/null
+++ b/test_regress/t/t_preproc_eof6_bad.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_preproc_eof6_bad.v b/test_regress/t/t_preproc_eof6_bad.v
new file mode 100644
index 000000000..6f936b832
--- /dev/null
+++ b/test_regress/t/t_preproc_eof6_bad.v
@@ -0,0 +1,7 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2019 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+"""str

From ef72b73a5957d365ebbb461d0f5be7847aceb7bf Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Fri, 18 Nov 2022 13:07:56 +0100
Subject: [PATCH 054/156] Support foreach loops on strings (#3760)

---
 src/V3Width.cpp            | 20 ++++++++++++++++----
 test_regress/t/t_foreach.v | 16 ++++++++++++++++
 2 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 9b7e67920..da8e1e924 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -4203,15 +4203,27 @@ private:
                 // Prep for next
                 fromDtp = fromDtp->subDTypep();
             } else if (AstBasicDType* const adtypep = VN_CAST(fromDtp, BasicDType)) {
-                if (!adtypep->isRanged()) {
+                if (adtypep->isString()) {
+                    if (varp) {
+                        AstConst* const leftp = new AstConst{fl, AstConst::Signed32{}, 0};
+                        AstLt* const condp = new AstLt{fl, new AstVarRef{fl, varp, VAccess::READ},
+                                                       new AstLenN{fl, fromp->cloneTree(false)}};
+                        AstAdd* const incp
+                            = new AstAdd{fl, new AstConst{fl, AstConst::Signed32{}, 1},
+                                         new AstVarRef{fl, varp, VAccess::READ}};
+                        loopp = createForeachLoop(nodep, bodyPointp, varp, leftp, condp, incp);
+                    }
+                } else if (!adtypep->isRanged()) {
                     argsp->v3error("Illegal to foreach loop on basic '" + fromDtp->prettyTypeName()
                                    + "'");
                     VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
                     VL_DO_DANGLING(bodyPointp->deleteTree(), bodyPointp);
                     return;
-                }
-                if (varp) {
-                    loopp = createForeachLoopRanged(nodep, bodyPointp, varp, adtypep->declRange());
+                } else {
+                    if (varp) {
+                        loopp = createForeachLoopRanged(nodep, bodyPointp, varp,
+                                                        adtypep->declRange());
+                    }
                 }
                 // Prep for next
                 fromDtp = nullptr;
diff --git a/test_regress/t/t_foreach.v b/test_regress/t/t_foreach.v
index c1405a73c..e7f75f0a5 100644
--- a/test_regress/t/t_foreach.v
+++ b/test_regress/t/t_foreach.v
@@ -18,6 +18,8 @@ module t (/*AUTOARG*/);
    bit [31:0]      depth1_array [0:0];
    int             oned [3:1];
    int             twod [3:1][9:8];
+   string          str1;
+   string          str2;
 
    typedef struct packed {
       reg [1:0] [63:0] subarray;
@@ -150,6 +152,20 @@ module t (/*AUTOARG*/);
 
       foreach (twod[i, j]);  // Null body check
 
+      str1 = "abcd";
+      str2 = "1234";
+      foreach (str1[i]) begin
+         str2[i] = str1[i];
+      end
+      if (str1 != str2) $stop;
+
+      str1 = "";
+      add = 0;
+      foreach(str1[i]) begin
+         add++;
+      end
+      `checkh(add, 0);
+
       $write("*-* All Finished *-*\n");
       $finish;
    end

From b2d92b7c2587bdd5eac6cf73413c5d39077bc78c Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 18 Nov 2022 20:58:24 -0500
Subject: [PATCH 055/156] Allow ENCAPSULATED and ENUMVALUE to be disabled

---
 src/V3Error.h       | 25 +++++++++++++------------
 src/V3Width.cpp     | 12 ++++++------
 src/V3WidthCommit.h | 14 +++++++-------
 3 files changed, 26 insertions(+), 25 deletions(-)

diff --git a/src/V3Error.h b/src/V3Error.h
index 47e222dd7..63fb4828d 100644
--- a/src/V3Error.h
+++ b/src/V3Error.h
@@ -55,8 +55,6 @@ public:
         I_DEF_NETTYPE_WIRE,  // `default_nettype is WIRE (false=NONE)
         I_TIMING,       // Enable timing from /*verilator timing_on/off*/
         // Error codes:
-        E_ENCAPSULATED, // Error: local/protected violation
-        E_ENUMVALUE,    // Error: enum type needs explicit cast
         E_PORTSHORT,    // Error: Output port is connected to a constant, electrical short
         E_UNSUPPORTED,  // Error: Unsupported (generally)
         E_TASKNSVAR,    // Error: Task I/O not simple
@@ -85,12 +83,12 @@ public:
         COLONPLUS,      // :+ instead of +:
         COMBDLY,        // Combinatorial delayed assignment
         CONTASSREG,     // Continuous assignment on reg
-        DEFPARAM,       // Style: Defparam
         DECLFILENAME,   // Declaration doesn't match filename
+        DEFPARAM,       // Style: Defparam
         DEPRECATED,     // Feature will be deprecated
-        RISEFALLDLY,    // Unsupported: rise/fall/turn-off delays
-        MINTYPMAXDLY,   // Unsupported: min/typ/max delay expressions
+        ENCAPSULATED,   // Error: local/protected violation
         ENDLABEL,       // End lable name mismatch
+        ENUMVALUE,      // Error: enum type needs explicit cast
         EOFNEWLINE,     // End-of-file missing newline
         GENCLK,         // Generated Clock. Historical, never issued.
         HIERBLOCK,      // Ignored hierarchical block setting
@@ -106,6 +104,7 @@ public:
         INSECURE,       // Insecure options
         LATCH,          // Latch detected outside of always_latch block
         LITENDIAN,      // Little bit endian vector
+        MINTYPMAXDLY,   // Unsupported: min/typ/max delay expressions
         MODDUP,         // Duplicate module
         MULTIDRIVEN,    // Driven from multiple blocks
         MULTITOP,       // Multiple top level modules
@@ -122,6 +121,7 @@ public:
         RANDC,          // Unsupported: 'randc' converted to 'rand'
         REALCVT,        // Real conversion
         REDEFMACRO,     // Redefining existing define macro
+        RISEFALLDLY,    // Unsupported: rise/fall/turn-off delays
         SELRANGE,       // Selection index out of range
         SHORTREAL,      // Shortreal not supported
         SPLITVAR,       // Cannot split the variable
@@ -170,22 +170,22 @@ public:
             // Boolean
             " I_CELLDEFINE", " I_COVERAGE", " I_TRACING", " I_LINT", " I_UNUSED", " I_DEF_NETTYPE_WIRE", " I_TIMING",
             // Errors
-            "ENCAPSULATED", "ENUMVALUE", "PORTSHORT", "UNSUPPORTED", "TASKNSVAR", "NEEDTIMINGOPT", "NOTIMING",
+            "PORTSHORT", "UNSUPPORTED", "TASKNSVAR", "NEEDTIMINGOPT", "NOTIMING",
             // Warnings
             " EC_FIRST_WARN",
             "ALWCOMBORDER", "ASSIGNDLY", "ASSIGNIN", "BADSTDPRAGMA",
             "BLKANDNBLK", "BLKLOOPINIT", "BLKSEQ", "BSSPACE",
             "CASEINCOMPLETE", "CASEOVERLAP", "CASEWITHX", "CASEX", "CASTCONST", "CDCRSTLOGIC", "CLKDATA",
             "CMPCONST", "COLONPLUS", "COMBDLY", "CONTASSREG",
-            "DEFPARAM", "DECLFILENAME", "DEPRECATED", "RISEFALLDLY", "MINTYPMAXDLY",
-            "ENDLABEL", "EOFNEWLINE", "GENCLK", "HIERBLOCK",
+            "DECLFILENAME", "DEFPARAM", "DEPRECATED",
+            "ENCAPSULATED", "ENDLABEL", "ENUMVALUE", "EOFNEWLINE", "GENCLK", "HIERBLOCK",
             "IFDEPTH", "IGNOREDRETURN",
             "IMPERFECTSCH", "IMPLICIT", "IMPORTSTAR", "IMPURE",
             "INCABSPATH", "INFINITELOOP", "INITIALDLY", "INSECURE",
-            "LATCH", "LITENDIAN", "MODDUP",
+            "LATCH", "LITENDIAN", "MINTYPMAXDLY", "MODDUP",
             "MULTIDRIVEN", "MULTITOP","NOLATCH", "NULLPORT", "PINCONNECTEMPTY",
             "PINMISSING", "PINNOCONNECT",  "PINNOTFOUND", "PKGNODECL", "PROCASSWIRE",
-            "PROFOUTOFDATE", "PROTECTED", "RANDC", "REALCVT", "REDEFMACRO",
+            "PROFOUTOFDATE", "PROTECTED", "RANDC", "REALCVT", "REDEFMACRO", "RISEFALLDLY",
             "SELRANGE", "SHORTREAL", "SPLITVAR", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET",
             "TICKCOUNT", "TIMESCALEMOD",
             "UNDRIVEN", "UNOPT", "UNOPTFLAT", "UNOPTTHREADS",
@@ -207,8 +207,9 @@ public:
     // Later -Werror- options may make more of these.
     bool pretendError() const VL_MT_SAFE {
         return (m_e == ASSIGNIN || m_e == BADSTDPRAGMA || m_e == BLKANDNBLK || m_e == BLKLOOPINIT
-                || m_e == CONTASSREG || m_e == ENDLABEL || m_e == IMPURE || m_e == PINNOTFOUND
-                || m_e == PKGNODECL || m_e == PROCASSWIRE  // Says IEEE
+                || m_e == CONTASSREG || m_e == ENCAPSULATED || m_e == ENDLABEL || m_e == ENUMVALUE
+                || m_e == IMPURE || m_e == PINNOTFOUND || m_e == PKGNODECL
+                || m_e == PROCASSWIRE  // Says IEEE
                 || m_e == ZERODLY);
     }
     // Warnings to mention manual
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index da8e1e924..3654b48f4 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1767,7 +1767,7 @@ private:
             const bool assoc = maxval > ENUM_LOOKUP_BITS;
             AstNode* testp = nullptr;
             FileLine* const fl_novalue = new FileLine{fl};
-            fl_novalue->warnOff(V3ErrorCode::E_ENUMVALUE, true);
+            fl_novalue->warnOff(V3ErrorCode::ENUMVALUE, true);
             if (assoc) {
                 AstVar* const varp = enumVarp(enumDtp, VAttrType::ENUM_VALID, true, 0);
                 testp = new AstAssocSel{fl_novalue, newVarRefDollarUnit(varp),
@@ -2767,7 +2767,7 @@ private:
                                         0);  // Spec doesn't say what to do
                 } else {
                     newp = VN_AS(itemp->valuep()->cloneTree(false), Const);  // A const
-                    newp->dtypeFrom(adtypep);  // To prevent a later E_ENUMVALUE
+                    newp->dtypeFrom(adtypep);  // To prevent a later ENUMVALUE
                 }
             } else if (nodep->name() == "last") {
                 const AstEnumItem* itemp = adtypep->itemsp();
@@ -2777,7 +2777,7 @@ private:
                                         0);  // Spec doesn't say what to do
                 } else {
                     newp = VN_AS(itemp->valuep()->cloneTree(false), Const);  // A const
-                    newp->dtypeFrom(adtypep);  // To prevent a later E_ENUMVALUE
+                    newp->dtypeFrom(adtypep);  // To prevent a later ENUMVALUE
                 }
             }
             UASSERT_OBJ(newp, nodep, "Enum method (perhaps enum item) not const");
@@ -2825,7 +2825,7 @@ private:
                 AstVar* const varp = enumVarp(adtypep, attrType, true, 0);
                 AstNode* const newp = new AstAssocSel{nodep->fileline(), newVarRefDollarUnit(varp),
                                                       nodep->fromp()->unlinkFrBack()};
-                newp->dtypeFrom(adtypep);  // To prevent a later E_ENUMVALUE
+                newp->dtypeFrom(adtypep);  // To prevent a later ENUMVALUE
                 nodep->replaceWith(newp);
             } else {
                 const int selwidth = V3Number::log2b(msbdim) + 1;  // Width to address a bit
@@ -2836,7 +2836,7 @@ private:
                     // We return "random" values if outside the range, which is fine
                     // as next/previous on illegal values just need something good out
                     new AstSel(nodep->fileline(), nodep->fromp()->unlinkFrBack(), 0, selwidth));
-                newp->dtypeFrom(adtypep);  // To prevent a later E_ENUMVALUE
+                newp->dtypeFrom(adtypep);  // To prevent a later ENUMVALUE
                 nodep->replaceWith(newp);
             }
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -6138,7 +6138,7 @@ private:
                     const auto castable = computeCastable(expEnump, underp->dtypep(), underp);
                     if (castable != COMPATIBLE && castable != ENUM_IMPLICIT && !VN_IS(underp, Cast)
                         && !VN_IS(underp, CastDynamic) && !m_enumItemp && warnOn) {
-                        nodep->v3warn(E_ENUMVALUE,
+                        nodep->v3warn(ENUMVALUE,
                                       "Illegal implicit conversion to enum "
                                           << expDTypep->prettyDTypeNameQ() << " from "
                                           << underp->dtypep()->prettyDTypeNameQ()
diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h
index 5dc6283e2..c3823b2a4 100644
--- a/src/V3WidthCommit.h
+++ b/src/V3WidthCommit.h
@@ -142,13 +142,13 @@ private:
             if (how) {
                 UINFO(9, "refclass " << refClassp << endl);
                 UINFO(9, "defclass " << defClassp << endl);
-                nodep->v3warn(E_ENCAPSULATED, nodep->prettyNameQ()
-                                                  << " is hidden as " << how
-                                                  << " within this context (IEEE 1800-2017 8.18)\n"
-                                                  << nodep->warnContextPrimary() << endl
-                                                  << nodep->warnOther()
-                                                  << "... Location of definition" << endl
-                                                  << defp->warnContextSecondary());
+                nodep->v3warn(ENCAPSULATED, nodep->prettyNameQ()
+                                                << " is hidden as " << how
+                                                << " within this context (IEEE 1800-2017 8.18)\n"
+                                                << nodep->warnContextPrimary() << endl
+                                                << nodep->warnOther()
+                                                << "... Location of definition" << endl
+                                                << defp->warnContextSecondary());
             }
         }
     }

From 0322e9da7ed52bca9b8fa5d8d7170f3fea7f8c56 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 18 Nov 2022 21:30:24 -0500
Subject: [PATCH 056/156] Fix randcase inside function.

---
 src/V3Randomize.cpp         | 11 ++++++++++-
 test_regress/t/t_randcase.v | 10 ++++++++++
 2 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index 89ddac9d2..e912f5e90 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -126,6 +126,7 @@ private:
 
     // STATE
     AstNodeModule* m_modp = nullptr;  // Current module
+    AstNodeFTask* m_ftaskp = nullptr;  // Current function/task
     size_t m_enumValueTabCount = 0;  // Number of tables with enum values created
     int m_randCaseNum = 0;  // Randcase number within a module for var naming
 
@@ -209,12 +210,19 @@ private:
 
     // VISITORS
     void visit(AstNodeModule* nodep) override {
+        VL_RESTORER(m_modp);
         VL_RESTORER(m_randCaseNum);
         m_modp = nodep;
         m_randCaseNum = 0;
         iterateChildren(nodep);
     }
+    void visit(AstNodeFTask* nodep) override {
+        VL_RESTORER(m_ftaskp);
+        m_ftaskp = nodep;
+        iterateChildren(nodep);
+    }
     void visit(AstClass* nodep) override {
+        VL_RESTORER(m_modp);
         VL_RESTORER(m_randCaseNum);
         m_modp = nodep;
         m_randCaseNum = 0;
@@ -278,8 +286,9 @@ private:
 
         FileLine* const fl = nodep->fileline();
         const std::string name = "__Vrandcase" + cvtToStr(m_randCaseNum++);
-        AstVar* const randVarp = new AstVar{fl, VVarType::STMTTEMP, name, sumDTypep};
+        AstVar* const randVarp = new AstVar{fl, VVarType::BLOCKTEMP, name, sumDTypep};
         randVarp->noSubst(true);
+        if (m_ftaskp) randVarp->funcLocal(true);
         AstNodeExpr* sump = new AstConst{fl, AstConst::WidthedValue{}, 64, 0};
         AstNodeIf* firstIfsp
             = new AstIf{fl, new AstConst{fl, AstConst::BitFalse{}}, nullptr, nullptr};
diff --git a/test_regress/t/t_randcase.v b/test_regress/t/t_randcase.v
index 331a53aa0..0d3ff6465 100644
--- a/test_regress/t/t_randcase.v
+++ b/test_regress/t/t_randcase.v
@@ -13,7 +13,17 @@ module t (/*AUTOARG*/);
    int v;
    int counts[8];
 
+   function int randfunc();
+      int i;
+      randcase
+        0 : i = 50;  // Never
+        1 : i = 100;
+      endcase
+      return i;
+   endfunction
+
    initial begin;
+      if (randfunc() != 100) $stop;
 
       //
       for (int i = 0; i < 8; ++i) counts[i] = 0;

From de9c92fd14dbb8d152e3699a6963365f34fcc32a Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 19 Nov 2022 10:48:46 -0500
Subject: [PATCH 057/156] Internals: Add missing const. No functional change.

---
 src/V3Randomize.cpp     | 2 +-
 src/V3StatsReport.cpp   | 2 +-
 src/V3VariableOrder.cpp | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index e912f5e90..99ade5062 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -126,7 +126,7 @@ private:
 
     // STATE
     AstNodeModule* m_modp = nullptr;  // Current module
-    AstNodeFTask* m_ftaskp = nullptr;  // Current function/task
+    const AstNodeFTask* m_ftaskp = nullptr;  // Current function/task
     size_t m_enumValueTabCount = 0;  // Number of tables with enum values created
     int m_randCaseNum = 0;  // Randcase number within a module for var naming
 
diff --git a/src/V3StatsReport.cpp b/src/V3StatsReport.cpp
index 03be5d71c..0135bd547 100644
--- a/src/V3StatsReport.cpp
+++ b/src/V3StatsReport.cpp
@@ -228,7 +228,7 @@ void V3Stats::statsReport() {
     std::ofstream* ofp{V3File::new_ofstream(filename)};
     if (ofp->fail()) v3fatal("Can't write " << filename);
 
-    const StatsReport reporter(ofp);
+    { StatsReport{ofp}; }  // Destruct before cleanup
 
     // Cleanup
     ofp->close();
diff --git a/src/V3VariableOrder.cpp b/src/V3VariableOrder.cpp
index 562bc7225..6ebd72c87 100644
--- a/src/V3VariableOrder.cpp
+++ b/src/V3VariableOrder.cpp
@@ -118,7 +118,7 @@ class VariableOrder final {
         V3TSP::StateVec states;
         for (const auto& pair : m2v) {
             if (pair.first.empty()) continue;
-            states.push_back(new VarTspSorter(pair.first));
+            states.push_back(new VarTspSorter{pair.first});
         }
 
         // Do the TSP sort

From f266b02bc77eacba4c5efb045f2b6b01a1cae9aa Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 19 Nov 2022 13:23:28 -0500
Subject: [PATCH 058/156] Internals: Improve dtype small dump.

---
 src/V3AstNodeDType.h |  3 +++
 src/V3AstNodes.cpp   | 12 ++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h
index 45f5dac64..8bb23b9f1 100644
--- a/src/V3AstNodeDType.h
+++ b/src/V3AstNodeDType.h
@@ -755,6 +755,8 @@ public:
     void virtRefDTypep(AstNodeDType* nodep) override { refDTypep(nodep); }
     string name() const override { return m_name; }
     void name(const string& flag) override { m_name = flag; }
+    void dump(std::ostream& str = std::cout) const override;
+    void dumpSmall(std::ostream& str) const override;
     // METHODS
     AstBasicDType* basicp() const override VL_MT_SAFE { return subDTypep()->basicp(); }
     AstNodeDType* skipRefp() const override VL_MT_SAFE { return subDTypep()->skipRefp(); }
@@ -1068,6 +1070,7 @@ public:
         return skipRefp()->similarDType(samep->skipRefp());
     }
     void dump(std::ostream& str = std::cout) const override;
+    void dumpSmall(std::ostream& str) const override;
     string name() const override { return m_name; }
     string prettyDTypeName() const override {
         return subDTypep() ? subDTypep()->name() : prettyName();
diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index 9f6dde5b0..c3083a152 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -1505,6 +1505,14 @@ void AstDisplay::dump(std::ostream& str) const {
     this->AstNodeStmt::dump(str);
     // str << " " << displayType().ascii();
 }
+void AstEnumDType::dump(std::ostream& str) const {
+    this->AstNodeDType::dump(str);
+    str << " enum";
+}
+void AstEnumDType::dumpSmall(std::ostream& str) const {
+    this->AstNodeDType::dumpSmall(str);
+    str << "enum";
+}
 void AstEnumItemRef::dump(std::ostream& str) const {
     this->AstNodeExpr::dump(str);
     str << " -> ";
@@ -1759,6 +1767,10 @@ void AstRefDType::dump(std::ostream& str) const {
         str << " -> UNLINKED";
     }
 }
+void AstRefDType::dumpSmall(std::ostream& str) const {
+    this->AstNodeDType::dumpSmall(str);
+    str << "ref";
+}
 const char* AstRefDType::broken() const {
     BROKEN_RTN(m_typedefp && !m_typedefp->brokeExists());
     BROKEN_RTN(m_refDTypep && !m_refDTypep->brokeExists());

From 09dff9c3a785b5f27f900fad8d0c9bef296798d8 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 19 Nov 2022 13:30:23 -0500
Subject: [PATCH 059/156] Fix false ENUMVALUE errors in unstable branch (#3761)

---
 src/V3Width.cpp                       | 13 +++++++++-
 src/V3WidthCommit.h                   |  2 ++
 test_regress/t/t_enum_type_bad.out    |  6 ++---
 test_regress/t/t_enum_value_assign.pl | 21 +++++++++++++++++
 test_regress/t/t_enum_value_assign.v  | 34 +++++++++++++++++++++++++++
 5 files changed, 72 insertions(+), 4 deletions(-)
 create mode 100755 test_regress/t/t_enum_value_assign.pl
 create mode 100644 test_regress/t/t_enum_value_assign.v

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 3654b48f4..246c02cad 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1841,9 +1841,12 @@ private:
         }
     }
     void visit(AstCast* nodep) override {
+        if (nodep->didWidth()) return;
+        UINFO(9, "CAST " << nodep << endl);
         nodep->dtypep(iterateEditMoveDTypep(nodep, nodep->subDTypep()));
         if (m_vup->prelim()) {
             // if (debug()) nodep->dumpTree(cout, "  CastPre: ");
+            // if (debug()) nodep->backp()->dumpTree(cout, "  CastPreUpUp: ");
             userIterateAndNext(nodep->fromp(), WidthVP(SELF, PRELIM).p());
             AstNodeDType* const toDtp = nodep->dtypep()->skipRefToEnump();
             AstNodeDType* const fromDtp = nodep->fromp()->dtypep()->skipRefToEnump();
@@ -1878,8 +1881,10 @@ private:
             if (bad) {
             } else if (const AstBasicDType* const basicp = toDtp->basicp()) {
                 if (!basicp->isDouble() && !fromDtp->isDouble()) {
+                    AstNodeDType* const origDTypep = nodep->dtypep();
                     const int width = toDtp->width();
                     castSized(nodep, nodep->fromp(), width);
+                    nodep->dtypeFrom(origDTypep);  // If was enum, need dtype to preserve as enum
                     // Note castSized might modify nodep->fromp()
                 } else {
                     iterateCheck(nodep, "value", nodep->fromp(), SELF, FINAL, fromDtp, EXTEND_EXP,
@@ -1924,8 +1929,10 @@ private:
                          EXTEND_EXP, false);
             AstNode* const underp = nodep->fromp()->unlinkFrBack();
             // if (debug()) underp->dumpTree(cout, "  CastRep: ");
+            underp->dtypeFrom(nodep);
             nodep->replaceWith(underp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
+            underp->didWidth(true);
         }
     }
     void visit(AstCastSize* nodep) override {
@@ -2217,6 +2224,9 @@ private:
             // and if we keep minwidth we'll consider it unsized which is incorrect
             iterateCheck(nodep, "Enum value", nodep->valuep(), CONTEXT_DET, FINAL, nodep->dtypep(),
                          EXTEND_EXP);
+            // Always create a cast, to avoid later ENUMVALUE warnings
+            nodep->valuep(new AstCast{nodep->valuep()->fileline(), nodep->valuep()->unlinkFrBack(),
+                                      nodep->dtypep()});
         }
     }
     void visit(AstEnumItemRef* nodep) override {
@@ -6139,12 +6149,13 @@ private:
                     if (castable != COMPATIBLE && castable != ENUM_IMPLICIT && !VN_IS(underp, Cast)
                         && !VN_IS(underp, CastDynamic) && !m_enumItemp && warnOn) {
                         nodep->v3warn(ENUMVALUE,
-                                      "Illegal implicit conversion to enum "
+                                      "Implicit conversion to enum "
                                           << expDTypep->prettyDTypeNameQ() << " from "
                                           << underp->dtypep()->prettyDTypeNameQ()
                                           << " (IEEE 1800-2017 6.19.3)\n"
                                           << nodep->warnMore()
                                           << "... Suggest use enum's mnemonic, or static cast");
+                        if (debug()) nodep->backp()->dumpTree(cout, "- back: ");
                     }
                 }
                 AstNodeDType* subDTypep = expDTypep;
diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h
index c3823b2a4..39e1ad8c5 100644
--- a/src/V3WidthCommit.h
+++ b/src/V3WidthCommit.h
@@ -85,6 +85,7 @@ public:
             num.isSigned(nodep->isSigned());
             AstConst* const newp = new AstConst{nodep->fileline(), num};
             newp->dtypeFrom(nodep);
+            newp->user1(true);
             return newp;
         } else {
             return nullptr;
@@ -163,6 +164,7 @@ private:
         }
     }
     void visit(AstConst* nodep) override {
+        if (nodep->user1SetOnce()) return;  // Process once
         UASSERT_OBJ(nodep->dtypep(), nodep, "No dtype");
         iterate(nodep->dtypep());  // Do datatype first
         if (AstConst* const newp = newIfConstCommitSize(nodep)) {
diff --git a/test_regress/t/t_enum_type_bad.out b/test_regress/t/t_enum_type_bad.out
index 26fe75f83..2d782732e 100644
--- a/test_regress/t/t_enum_type_bad.out
+++ b/test_regress/t/t_enum_type_bad.out
@@ -1,15 +1,15 @@
-%Error-ENUMVALUE: t/t_enum_type_bad.v:28:9: Illegal implicit conversion to enum 't.e_t' from 'logic[31:0]' (IEEE 1800-2017 6.19.3)
+%Error-ENUMVALUE: t/t_enum_type_bad.v:28:9: Implicit conversion to enum 't.e_t' from 'logic[31:0]' (IEEE 1800-2017 6.19.3)
                                           : ... In instance t
                                           : ... Suggest use enum's mnemonic, or static cast
    28 |       e = 1;   
       |         ^
                   ... For error description see https://verilator.org/warn/ENUMVALUE?v=latest
-%Error-ENUMVALUE: t/t_enum_type_bad.v:29:9: Illegal implicit conversion to enum 't.o_t' from 't.e_t' (IEEE 1800-2017 6.19.3)
+%Error-ENUMVALUE: t/t_enum_type_bad.v:29:9: Implicit conversion to enum 't.o_t' from 't.e_t' (IEEE 1800-2017 6.19.3)
                                           : ... In instance t
                                           : ... Suggest use enum's mnemonic, or static cast
    29 |       o = e;   
       |         ^
-%Error-ENUMVALUE: t/t_enum_type_bad.v:35:9: Illegal implicit conversion to enum 't.o_t' from 'ENUMDTYPE 't.e_t'' (IEEE 1800-2017 6.19.3)
+%Error-ENUMVALUE: t/t_enum_type_bad.v:35:9: Implicit conversion to enum 't.o_t' from 'ENUMDTYPE 't.e_t'' (IEEE 1800-2017 6.19.3)
                                           : ... In instance t
                                           : ... Suggest use enum's mnemonic, or static cast
    35 |       o = str.m_e;   
diff --git a/test_regress/t/t_enum_value_assign.pl b/test_regress/t/t_enum_value_assign.pl
new file mode 100755
index 000000000..1aa73f80a
--- /dev/null
+++ b/test_regress/t/t_enum_value_assign.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_enum_value_assign.v b/test_regress/t/t_enum_value_assign.v
new file mode 100644
index 000000000..28e55cf02
--- /dev/null
+++ b/test_regress/t/t_enum_value_assign.v
@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+
+   localparam logic [9:0] V2 = (1 << 2);
+   localparam logic [9:0] V1 = (1 << 1);
+   localparam logic [9:0] V0 = (1 << 0);
+   typedef enum logic [9:0] {
+                             ZERO = '0,
+                             VAL0 = V0,
+                             VAL1 = V1,
+                             VAL01 = V0 | V1
+                             } enum_t;
+
+   localparam enum_t PARAMVAL1 = VAL1;
+   localparam enum_t PARAMVAL1CONST = enum_t'(2);
+
+   initial begin
+      enum_t e;
+      e = VAL01;
+      if (e != VAL01) $stop;
+
+      if (PARAMVAL1 != VAL1) $stop;
+      if (PARAMVAL1CONST != VAL1) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

From 3a27e3d67b27c424f0d4f9c40581bc6ab3cc8650 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 19 Nov 2022 14:07:39 -0500
Subject: [PATCH 060/156] Fix false ENUMVALUE errors in unstable branch (#3761)

---
 src/V3Width.cpp                      | 6 +++++-
 test_regress/t/t_enum_value_assign.v | 5 +++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 246c02cad..176f8c00e 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1139,8 +1139,12 @@ private:
         // The node got setup with the signed/real state of the node.
         // However a later operation may have changed the node->signed w/o changing
         // the number's sign.  So we don't: nodep->dtypeChgSigned(nodep->num().isSigned());
+        if (nodep->didWidthAndSet()) return;
         if (m_vup && m_vup->prelim()) {
-            if (nodep->num().isString()) {
+            if (VN_IS(nodep->dtypep()->skipRefToEnump(), EnumDType)) {
+                // Assume this constant was properly casted ealier
+                // (Otherwise it couldn't have an enum data type)
+            } else if (nodep->num().isString()) {
                 nodep->dtypeSetString();
             } else if (nodep->num().sized()) {
                 nodep->dtypeChgWidth(nodep->num().width(), nodep->num().width());
diff --git a/test_regress/t/t_enum_value_assign.v b/test_regress/t/t_enum_value_assign.v
index 28e55cf02..953245910 100644
--- a/test_regress/t/t_enum_value_assign.v
+++ b/test_regress/t/t_enum_value_assign.v
@@ -19,6 +19,9 @@ module t(/*AUTOARG*/);
    localparam enum_t PARAMVAL1 = VAL1;
    localparam enum_t PARAMVAL1CONST = enum_t'(2);
 
+   typedef enum {I_ZERO, I_ONE, I_TWO} inte_t;
+   localparam inte_t I_PARAM = inte_t'(1);
+
    initial begin
       enum_t e;
       e = VAL01;
@@ -27,6 +30,8 @@ module t(/*AUTOARG*/);
       if (PARAMVAL1 != VAL1) $stop;
       if (PARAMVAL1CONST != VAL1) $stop;
 
+      if (I_PARAM != I_ONE) $stop;
+
       $write("*-* All Finished *-*\n");
       $finish;
    end

From cd2208ea3ff86fc09f4c15dbbc3aee8d51a93635 Mon Sep 17 00:00:00 2001
From: Andrew Nolte <anolte@hudson-trading.com>
Date: Sat, 19 Nov 2022 14:09:51 -0500
Subject: [PATCH 061/156] Contributors (#3762)

---
 docs/CONTRIBUTORS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS
index e072cacb0..8ff9995ad 100644
--- a/docs/CONTRIBUTORS
+++ b/docs/CONTRIBUTORS
@@ -11,6 +11,7 @@ Alex Chadwick
 Aliaksei Chapyzhenka
 Ameya Vikram Singh
 Andreas Kuster
+Andrew Nolte
 Arkadiusz Kozdra
 Chris Randall
 Chuxuan Wang

From d0e7177d8e73227717070c657910c5601d1646cc Mon Sep 17 00:00:00 2001
From: Mariusz Glebocki <mglb@arccos-1.net>
Date: Sat, 19 Nov 2022 20:44:54 +0100
Subject: [PATCH 062/156] Disable stack size limit (#3706) (#3751)

---
 bin/verilator                               | 46 +++++++++++++++------
 docs/guide/exe_verilator.rst                |  5 +++
 src/V3Options.cpp                           |  1 +
 test_regress/t/t_flag_no_unlimited_stack.pl | 19 +++++++++
 test_regress/t/t_flag_no_unlimited_stack.v  |  8 ++++
 5 files changed, 66 insertions(+), 13 deletions(-)
 create mode 100755 test_regress/t/t_flag_no_unlimited_stack.pl
 create mode 100644 test_regress/t/t_flag_no_unlimited_stack.v

diff --git a/bin/verilator b/bin/verilator
index e5af6da66..c78b8c2d5 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -31,6 +31,7 @@ my $opt_gdb;
 my $opt_rr;
 my $opt_gdbbt;
 my $opt_quiet_exit;
+my $opt_unlimited_stack = 1;
 
 # No arguments can't do anything useful.  Give help
 if ($#ARGV < 0) {
@@ -49,16 +50,17 @@ foreach my $sw (@ARGV) {
 Getopt::Long::config("no_auto_abbrev", "pass_through");
 if (! GetOptions(
           # Major operating modes
-          "help"        => \&usage,
-          "debug"       => \&debug,
-          # "version!"  => \&version,   # Also passthru'ed
+          "help"             => \&usage,
+          "debug"            => \&debug,
+          # "version!"       => \&version,   # Also passthru'ed
           # Switches
-          "gdb!"        => \$opt_gdb,
-          "gdbbt!"      => \$opt_gdbbt,
-          "quiet-exit!" => \$opt_quiet_exit,
-          "rr!"         => \$opt_rr,
+          "gdb!"             => \$opt_gdb,
+          "gdbbt!"           => \$opt_gdbbt,
+          "quiet-exit!"      => \$opt_quiet_exit,
+          "rr!"              => \$opt_rr,
+          "unlimited-stack!" => \$opt_unlimited_stack,
           # Additional parameters
-          "<>"          => sub {},      # Ignored
+          "<>"               => sub {},      # Ignored
     )) {
     pod2usage(-exitstatus => 2, -verbose => 0);
 }
@@ -76,7 +78,8 @@ if ($opt_gdbbt && !gdb_works()) {
 my @quoted_sw = map { sh_escape($_) } @Opt_Verilator_Sw;
 if ($opt_gdb) {
     # Generic GDB interactive
-    run (aslr_off()
+    run (ulimit_stack_unlimited()
+         . aslr_off()
          . ($ENV{VERILATOR_GDB} || "gdb")
          . " " . verilator_bin()
          # Note, uncomment to set breakpoints before running:
@@ -92,12 +95,14 @@ if ($opt_gdb) {
          . " -ex 'bt'");
 } elsif ($opt_rr) {
     # Record with rr
-    run (aslr_off()
+    run (ulimit_stack_unlimited()
+         . aslr_off()
          . "rr record " . verilator_bin()
          . " " . join(' ', @quoted_sw));
 } elsif ($opt_gdbbt && $Debug) {
     # Run under GDB to get gdbbt
-    run (aslr_off()
+    run (ulimit_stack_unlimited()
+         . aslr_off()
          . "gdb"
          . " " . verilator_bin()
          . " --batch --quiet --return-child-result"
@@ -106,10 +111,13 @@ if ($opt_gdb) {
          . " -ex 'bt' -ex 'quit'");
 } elsif ($Debug) {
     # Debug
-    run(aslr_off() . verilator_bin() . " " . join(' ', @quoted_sw));
+    run(ulimit_stack_unlimited()
+        . aslr_off()
+        . verilator_bin()
+        . " " . join(' ', @quoted_sw));
 } else {
     # Normal, non gdb
-    run(verilator_bin() . " " . join(' ', @quoted_sw));
+    run(ulimit_stack_unlimited() . verilator_bin() . " " . join(' ', @quoted_sw));
 }
 
 #----------------------------------------------------------------------
@@ -180,6 +188,17 @@ sub aslr_off {
     }
 }
 
+sub ulimit_stack_unlimited {
+    return "" if !$opt_unlimited_stack;
+    system("ulimit -s unlimited 2>/dev/null");
+    my $status = $?;
+    if ($status == 0) {
+        return "ulimit -s unlimited 2>/dev/null; exec ";
+    } else {
+        return "";
+    }
+}
+
 sub run {
     # Run command, check errors
     my $command = shift;
@@ -419,6 +438,7 @@ detailed descriptions of these arguments.
     --trace-threads <threads>   Enable FST waveform creation on separate threads
     --trace-underscore          Enable tracing of _signals
      -U<var>                    Undefine preprocessor define
+    --no-unlimited-stack        Don't disable stack size limit
     --unroll-count <loops>      Tune maximum loop iterations
     --unroll-stmts <stmts>      Tune maximum loop body size
     --unused-regexp <regexp>    Tune UNUSED lint signals
diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst
index ffb990356..21be8775f 100644
--- a/docs/guide/exe_verilator.rst
+++ b/docs/guide/exe_verilator.rst
@@ -1383,6 +1383,11 @@ Summary:
 
    Undefines the given preprocessor symbol.
 
+.. option:: --no-unlimited-stack
+
+   Verilator tries to disable stack size limit using
+   :command:`ulimit -s unlimited` command. This option turns this behavior off.
+
 .. option:: --unroll-count <loops>
 
    Rarely needed.  Specifies the maximum number of loop iterations that may be
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index bd1fa208b..64b9d2b60 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -1472,6 +1472,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
 
     DECL_OPTION("-U", CbPartialMatch, &V3PreShell::undef);
     DECL_OPTION("-underline-zero", OnOff, &m_underlineZero);  // Deprecated
+    DECL_OPTION("-no-unlimited-stack", CbCall, []() {});  // Processed only in bin/verilator shell
     DECL_OPTION("-unroll-count", Set, &m_unrollCount).undocumented();  // Optimization tweak
     DECL_OPTION("-unroll-stmts", Set, &m_unrollStmts).undocumented();  // Optimization tweak
     DECL_OPTION("-unused-regexp", Set, &m_unusedRegexp);
diff --git a/test_regress/t/t_flag_no_unlimited_stack.pl b/test_regress/t/t_flag_no_unlimited_stack.pl
new file mode 100755
index 000000000..ef1a415a2
--- /dev/null
+++ b/test_regress/t/t_flag_no_unlimited_stack.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+# Just check whether the flag is recognized.
+lint(
+    verilator_flags2 => ["--no-unlimited-stack"],
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_flag_no_unlimited_stack.v b/test_regress/t/t_flag_no_unlimited_stack.v
new file mode 100644
index 000000000..a56f76564
--- /dev/null
+++ b/test_regress/t/t_flag_no_unlimited_stack.v
@@ -0,0 +1,8 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2005 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+endmodule

From 21d80cdfa1fd68665003ba91ce25f060603aee6d Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 19 Nov 2022 14:45:33 -0500
Subject: [PATCH 063/156] Internals: Fix constructor style.

---
 src/V3Begin.cpp        |  4 ++--
 src/V3Broken.cpp       |  4 ++--
 src/V3Clock.cpp        |  8 ++++----
 src/V3Config.cpp       | 20 ++++++++++----------
 src/V3DepthBlock.cpp   |  4 ++--
 src/V3EmitXml.cpp      |  2 +-
 src/V3Global.cpp       |  8 ++++----
 src/V3InstrCount.cpp   |  2 +-
 src/V3Localize.cpp     |  2 +-
 src/V3Options.cpp      |  2 +-
 src/V3ParseGrammar.cpp | 26 +++++++++++++-------------
 src/V3ParseImp.cpp     | 10 +++++-----
 src/V3PreProc.cpp      |  6 +++---
 src/V3PreShell.cpp     |  6 +++---
 src/V3Scoreboard.cpp   |  6 +++---
 src/V3String.cpp       | 10 +++++-----
 src/V3Subst.cpp        |  4 ++--
 src/V3TSP.cpp          | 30 +++++++++++++++---------------
 src/V3Undriven.cpp     |  2 +-
 19 files changed, 78 insertions(+), 78 deletions(-)

diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp
index 680f3b8b4..9af5384a6 100644
--- a/src/V3Begin.cpp
+++ b/src/V3Begin.cpp
@@ -95,8 +95,8 @@ private:
                 m_unnamedScope = dot(m_unnamedScope, ident);
                 // Create CellInline for dotted var resolution
                 if (!m_ftaskp) {
-                    AstCellInline* const inlinep = new AstCellInline(
-                        nodep->fileline(), m_unnamedScope, blockName, m_modp->timeunit());
+                    AstCellInline* const inlinep = new AstCellInline{
+                        nodep->fileline(), m_unnamedScope, blockName, m_modp->timeunit()};
                     m_modp->addInlinesp(inlinep);  // Must be parsed before any AstCells
                 }
             }
diff --git a/src/V3Broken.cpp b/src/V3Broken.cpp
index 9b76b8d2b..2ff17e9f6 100644
--- a/src/V3Broken.cpp
+++ b/src/V3Broken.cpp
@@ -355,8 +355,8 @@ void V3Broken::brokenAll(AstNetlist* nodep) {
 
 void V3Broken::selfTest() {
     // Exercise addNewed and deleted for coverage, as otherwise only used with VL_LEAK_CHECKS
-    FileLine* const fl = new FileLine(FileLine::commandLineFilename());
-    const AstNode* const newp = new AstBegin(fl, "[EditWrapper]", nullptr);
+    FileLine* const fl = new FileLine{FileLine::commandLineFilename()};
+    const AstNode* const newp = new AstBegin{fl, "[EditWrapper]", nullptr};
     addNewed(newp);
     deleted(newp);
     VL_DO_DANGLING(delete newp, newp);
diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp
index 31661a277..501e42098 100644
--- a/src/V3Clock.cpp
+++ b/src/V3Clock.cpp
@@ -58,7 +58,7 @@ private:
         UASSERT_OBJ(!nodep->access().isRW(), nodep, "Cannot handle a READWRITE reference");
         if (nodep->access().isWriteOnly()) {
             nodep->replaceWith(
-                new AstVarRef(nodep->fileline(), nodep->varScopep(), VAccess::READ));
+                new AstVarRef{nodep->fileline(), nodep->varScopep(), VAccess::READ});
         }
     }
 
@@ -113,7 +113,7 @@ private:
     AstIf* makeActiveIf(AstSenTree* sensesp) {
         AstNode* const senEqnp = createSenseEquation(sensesp->sensesp());
         UASSERT_OBJ(senEqnp, sensesp, "No sense equation, shouldn't be in sequent activation.");
-        AstIf* const newifp = new AstIf(sensesp->fileline(), senEqnp);
+        AstIf* const newifp = new AstIf{sensesp->fileline(), senEqnp};
         return newifp;
     }
     void clearLastSen() {
@@ -130,11 +130,11 @@ private:
         AstNode* const changeWrp = nodep->changep()->unlinkFrBack();
         AstNode* const changeRdp = ConvertWriteRefsToRead::main(changeWrp->cloneTree(false));
         AstIf* const newp
-            = new AstIf(nodep->fileline(), new AstXor(nodep->fileline(), origp, changeRdp), incp);
+            = new AstIf{nodep->fileline(), new AstXor{nodep->fileline(), origp, changeRdp}, incp};
         // We could add another IF to detect posedges, and only increment if so.
         // It's another whole branch though versus a potential memory miss.
         // We'll go with the miss.
-        newp->addThensp(new AstAssign(nodep->fileline(), changeWrp, origp->cloneTree(false)));
+        newp->addThensp(new AstAssign{nodep->fileline(), changeWrp, origp->cloneTree(false)});
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
diff --git a/src/V3Config.cpp b/src/V3Config.cpp
index d71b7cc16..9570c7245 100644
--- a/src/V3Config.cpp
+++ b/src/V3Config.cpp
@@ -105,10 +105,10 @@ public:
     // Apply all attributes to the variable
     void apply(AstVar* varp) {
         for (const_iterator it = begin(); it != end(); ++it) {
-            AstNode* const newp = new AstAttrOf(varp->fileline(), it->m_type);
+            AstNode* const newp = new AstAttrOf{varp->fileline(), it->m_type};
             varp->addAttrsp(newp);
             if (it->m_type == VAttrType::VAR_PUBLIC_FLAT_RW && it->m_sentreep) {
-                newp->addNext(new AstAlwaysPublic(varp->fileline(), it->m_sentreep, nullptr));
+                newp->addNext(new AstAlwaysPublic{varp->fileline(), it->m_sentreep, nullptr});
             }
         }
     }
@@ -143,9 +143,9 @@ public:
 
     void apply(AstNodeFTask* ftaskp) const {
         if (m_noinline)
-            ftaskp->addStmtsp(new AstPragma(ftaskp->fileline(), VPragmaType::NO_INLINE_TASK));
+            ftaskp->addStmtsp(new AstPragma{ftaskp->fileline(), VPragmaType::NO_INLINE_TASK});
         if (m_public)
-            ftaskp->addStmtsp(new AstPragma(ftaskp->fileline(), VPragmaType::PUBLIC_TASK));
+            ftaskp->addStmtsp(new AstPragma{ftaskp->fileline(), VPragmaType::PUBLIC_TASK});
         // Only functions can have isolate (return value)
         if (VN_IS(ftaskp, Func)) ftaskp->attrIsolateAssign(m_isolate);
     }
@@ -194,7 +194,7 @@ public:
         if (m_inline) {
             const VPragmaType type
                 = m_inlineValue ? VPragmaType::INLINE_MODULE : VPragmaType::NO_INLINE_MODULE;
-            AstNode* const nodep = new AstPragma(modp->fileline(), type);
+            AstNode* const nodep = new AstPragma{modp->fileline(), type};
             modp->addStmtsp(nodep);
         }
         for (const auto& itr : m_modPragmas) {
@@ -208,7 +208,7 @@ public:
         if (!nodep->unnamed()) {
             for (const string& i : m_coverageOffBlocks) {
                 if (VString::wildmatch(nodep->name(), i)) {
-                    nodep->addStmtsp(new AstPragma(nodep->fileline(), pragma));
+                    nodep->addStmtsp(new AstPragma{nodep->fileline(), pragma});
                 }
             }
         }
@@ -302,7 +302,7 @@ public:
         // Apply to block at this line
         const VPragmaType pragma = VPragmaType::COVERAGE_BLOCK_OFF;
         if (lineMatch(nodep->fileline()->lineno(), pragma)) {
-            nodep->addStmtsp(new AstPragma(nodep->fileline(), pragma));
+            nodep->addStmtsp(new AstPragma{nodep->fileline(), pragma});
         }
     }
     void applyCase(AstCase* nodep) {
@@ -569,14 +569,14 @@ void V3Config::addVarAttr(FileLine* fl, const string& module, const string& ftas
                 fl->v3error("Signals inside functions/tasks cannot be marked forceable");
             } else {
                 V3ConfigResolver::s().modules().at(module).vars().at(var).push_back(
-                    V3ConfigVarAttr(attr));
+                    V3ConfigVarAttr{attr});
             }
         } else {
             V3ConfigModule& mod = V3ConfigResolver::s().modules().at(module);
             if (ftask.empty()) {
-                mod.vars().at(var).push_back(V3ConfigVarAttr(attr, sensep));
+                mod.vars().at(var).push_back(V3ConfigVarAttr{attr, sensep});
             } else {
-                mod.ftasks().at(ftask).vars().at(var).push_back(V3ConfigVarAttr(attr, sensep));
+                mod.ftasks().at(ftask).vars().at(var).push_back(V3ConfigVarAttr{attr, sensep});
             }
         }
     }
diff --git a/src/V3DepthBlock.cpp b/src/V3DepthBlock.cpp
index 69497def3..09ea0c1eb 100644
--- a/src/V3DepthBlock.cpp
+++ b/src/V3DepthBlock.cpp
@@ -53,14 +53,14 @@ private:
         // Create sub function
         AstScope* const scopep = m_cfuncp->scopep();
         const string name = m_cfuncp->name() + "__deep" + cvtToStr(++m_deepNum);
-        AstCFunc* const funcp = new AstCFunc(nodep->fileline(), name, scopep);
+        AstCFunc* const funcp = new AstCFunc{nodep->fileline(), name, scopep};
         funcp->slow(m_cfuncp->slow());
         funcp->isStatic(m_cfuncp->isStatic());
         funcp->isLoose(m_cfuncp->isLoose());
         funcp->addStmtsp(nodep);
         scopep->addBlocksp(funcp);
         // Call sub function at the point where the body was removed from
-        AstCCall* const callp = new AstCCall(nodep->fileline(), funcp);
+        AstCCall* const callp = new AstCCall{nodep->fileline(), funcp};
         callp->dtypeSetVoid();
         if (VN_IS(m_modp, Class)) {
             funcp->argTypes(EmitCBaseVisitor::symClassVar());
diff --git a/src/V3EmitXml.cpp b/src/V3EmitXml.cpp
index 17a35a426..db6ec800f 100644
--- a/src/V3EmitXml.cpp
+++ b/src/V3EmitXml.cpp
@@ -441,7 +441,7 @@ void V3EmitXml::emitxml() {
     const string filename = (v3Global.opt.xmlOutput().empty()
                                  ? v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + ".xml"
                                  : v3Global.opt.xmlOutput());
-    V3OutXmlFile of(filename);
+    V3OutXmlFile of{filename};
     of.putsHeader();
     of.puts("<!-- DESCR"
             "IPTION: Verilator output: XML representation of netlist -->\n");
diff --git a/src/V3Global.cpp b/src/V3Global.cpp
index 34cbe343b..dd9ec4ac5 100644
--- a/src/V3Global.cpp
+++ b/src/V3Global.cpp
@@ -52,14 +52,14 @@ void V3Global::readFiles() {
     //   AstNode::user4p()      // VSymEnt*    Package and typedef symbol names
     const VNUser4InUse inuser4;
 
-    VInFilter filter(v3Global.opt.pipeFilter());
-    V3ParseSym parseSyms(v3Global.rootp());  // Symbol table must be common across all parsing
+    VInFilter filter{v3Global.opt.pipeFilter()};
+    V3ParseSym parseSyms{v3Global.rootp()};  // Symbol table must be common across all parsing
 
     V3Parse parser(v3Global.rootp(), &filter, &parseSyms);
     // Read top module
     const V3StringList& vFiles = v3Global.opt.vFiles();
     for (const string& filename : vFiles) {
-        parser.parseFile(new FileLine(FileLine::commandLineFilename()), filename, false,
+        parser.parseFile(new FileLine{FileLine::commandLineFilename()}, filename, false,
                          "Cannot find file containing module: ");
     }
 
@@ -68,7 +68,7 @@ void V3Global::readFiles() {
     // this needs to be done after the top file is read
     const V3StringSet& libraryFiles = v3Global.opt.libraryFiles();
     for (const string& filename : libraryFiles) {
-        parser.parseFile(new FileLine(FileLine::commandLineFilename()), filename, true,
+        parser.parseFile(new FileLine{FileLine::commandLineFilename()}, filename, true,
                          "Cannot find file containing library module: ");
     }
     // v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("parse.tree"));
diff --git a/src/V3InstrCount.cpp b/src/V3InstrCount.cpp
index 7aff91d73..b72e352e6 100644
--- a/src/V3InstrCount.cpp
+++ b/src/V3InstrCount.cpp
@@ -333,6 +333,6 @@ private:
 
 uint32_t V3InstrCount::count(AstNode* nodep, bool assertNoDups, std::ostream* osp) {
     const InstrCountVisitor visitor{nodep, assertNoDups, osp};
-    if (osp) InstrCountDumpVisitor dumper(nodep, osp);
+    if (osp) InstrCountDumpVisitor dumper{nodep, osp};
     return visitor.instrCount();
 }
diff --git a/src/V3Localize.cpp b/src/V3Localize.cpp
index 1de5d06e3..4a30bcc7b 100644
--- a/src/V3Localize.cpp
+++ b/src/V3Localize.cpp
@@ -106,7 +106,7 @@ private:
                           ? oldVarp->name()
                           : nodep->scopep()->nameDotless() + "__DOT__" + oldVarp->name();
                 AstVar* const newVarp
-                    = new AstVar(oldVarp->fileline(), oldVarp->varType(), newName, oldVarp);
+                    = new AstVar{oldVarp->fileline(), oldVarp->varType(), newName, oldVarp};
                 newVarp->funcLocal(true);
                 funcp->addInitsp(newVarp);
 
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index 64b9d2b60..e438d646e 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -1688,7 +1688,7 @@ void V3Options::parseOptsFile(FileLine* fl, const string& filename, bool rel) {
     whole_file += "\n";  // So string match below is simplified
     if (inCmt) fl->v3error("Unterminated /* comment inside -f file.");
 
-    fl = new FileLine(filename);
+    fl = new FileLine{filename};
 
     // Split into argument list and process
     // Note we try to respect escaped char, double/simple quoted strings
diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp
index 0c0fbf969..2c1c31e47 100644
--- a/src/V3ParseGrammar.cpp
+++ b/src/V3ParseGrammar.cpp
@@ -73,12 +73,12 @@ AstArg* V3ParseGrammar::argWrapList(AstNode* nodep) {
     // Convert list of expressions to list of arguments
     if (!nodep) return nullptr;
     AstArg* outp = nullptr;
-    AstBegin* const tempp = new AstBegin(nodep->fileline(), "[EditWrapper]", nodep);
+    AstBegin* const tempp = new AstBegin{nodep->fileline(), "[EditWrapper]", nodep};
     while (nodep) {
         AstNode* const nextp = nodep->nextp();
         AstNode* const exprp = nodep->unlinkFrBack();
         nodep = nextp;
-        outp = AstNode::addNext(outp, new AstArg(exprp->fileline(), "", exprp));
+        outp = AstNode::addNext(outp, new AstArg{exprp->fileline(), "", exprp});
     }
     VL_DO_DANGLING(tempp->deleteTree(), tempp);
     return outp;
@@ -127,22 +127,22 @@ AstNodeDType* V3ParseGrammar::createArray(AstNodeDType* basep, AstNodeRange* nra
             AstRange* const rangep = VN_CAST(nrangep, Range);
             if (rangep && isPacked) {
                 arrayp
-                    = new AstPackArrayDType(rangep->fileline(), VFlagChildDType(), arrayp, rangep);
+                    = new AstPackArrayDType{rangep->fileline(), VFlagChildDType(), arrayp, rangep};
             } else if (rangep
                        && (VN_IS(rangep->leftp(), Unbounded)
                            || VN_IS(rangep->rightp(), Unbounded))) {
-                arrayp = new AstQueueDType(nrangep->fileline(), VFlagChildDType(), arrayp,
-                                           rangep->rightp()->cloneTree(true));
+                arrayp = new AstQueueDType{nrangep->fileline(), VFlagChildDType(), arrayp,
+                                           rangep->rightp()->cloneTree(true)};
             } else if (rangep) {
-                arrayp = new AstUnpackArrayDType(rangep->fileline(), VFlagChildDType(), arrayp,
-                                                 rangep);
+                arrayp = new AstUnpackArrayDType{rangep->fileline(), VFlagChildDType{}, arrayp,
+                                                 rangep};
             } else if (VN_IS(nrangep, UnsizedRange)) {
-                arrayp = new AstUnsizedArrayDType(nrangep->fileline(), VFlagChildDType(), arrayp);
+                arrayp = new AstUnsizedArrayDType{nrangep->fileline(), VFlagChildDType{}, arrayp};
             } else if (VN_IS(nrangep, BracketRange)) {
                 const AstBracketRange* const arangep = VN_AS(nrangep, BracketRange);
                 AstNode* const keyp = arangep->elementsp()->unlinkFrBack();
-                arrayp = new AstBracketArrayDType(nrangep->fileline(), VFlagChildDType(), arrayp,
-                                                  keyp);
+                arrayp = new AstBracketArrayDType{nrangep->fileline(), VFlagChildDType{}, arrayp,
+                                                  keyp};
             } else if (VN_IS(nrangep, WildcardRange)) {
                 arrayp = new AstWildcardArrayDType{nrangep->fileline(), VFlagChildDType{}, arrayp};
             } else {
@@ -166,7 +166,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name,
     }
     if (GRAMMARP->m_varDecl == VVarType::WREAL) {
         // dtypep might not be null, might be implicit LOGIC before we knew better
-        dtypep = new AstBasicDType(fileline, VBasicDTypeKwd::DOUBLE);
+        dtypep = new AstBasicDType{fileline, VBasicDTypeKwd::DOUBLE};
     }
     if (!dtypep) {  // Created implicitly
         if (m_insideProperty) {
@@ -199,7 +199,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name,
     // ARRAYDTYPE0(ARRAYDTYPE1(ARRAYDTYPE2(BASICTYPE3), RANGE), RANGE)
     AstNodeDType* const arrayDTypep = createArray(dtypep, arrayp, false);
 
-    AstVar* const nodep = new AstVar(fileline, type, name, VFlagChildDType(), arrayDTypep);
+    AstVar* const nodep = new AstVar{fileline, type, name, VFlagChildDType(), arrayDTypep};
     nodep->addAttrsp(attrsp);
     nodep->ansi(m_pinAnsi);
     nodep->declTyped(m_varDeclTyped);
@@ -222,7 +222,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name,
     }
     if (VN_IS(dtypep, ParseTypeDType)) {
         // Parser needs to know what is a type
-        AstNode* const newp = new AstTypedefFwd(fileline, name);
+        AstNode* const newp = new AstTypedefFwd{fileline, name};
         AstNode::addNext<AstNode, AstNode>(nodep, newp);
         SYMP->reinsert(newp);
     }
diff --git a/src/V3ParseImp.cpp b/src/V3ParseImp.cpp
index cb26c7026..c73b6b64c 100644
--- a/src/V3ParseImp.cpp
+++ b/src/V3ParseImp.cpp
@@ -196,7 +196,7 @@ double V3ParseImp::lexParseTimenum(const char* textp) {
     }
     *dp++ = '\0';
     const double d = strtod(strgp, nullptr);
-    const string suffix(sp);
+    const string suffix{sp};
 
     double divisor = 1;
     if (suffix == "s") {
@@ -240,7 +240,7 @@ size_t V3ParseImp::ppInputToLex(char* buf, size_t max_size) {
         got += len;
     }
     if (debug() >= 9) {
-        const string out = string(buf, got);
+        const string out = std::string{buf, got};
         cout << "   inputToLex  got=" << got << " '" << out << "'" << endl;
     }
     // Note returns 0 at EOF
@@ -274,7 +274,7 @@ void V3ParseImp::parseFile(FileLine* fileline, const string& modfilename, bool i
     const string modname = V3Os::filenameNonExt(modfilename);
 
     UINFO(2, __FUNCTION__ << ": " << modname << (inLibrary ? " [LIB]" : "") << endl);
-    m_lexFileline = new FileLine(fileline);
+    m_lexFileline = new FileLine{fileline};
     m_lexFileline->newContent();
     m_bisonLastFileline = m_lexFileline;
     m_inLibrary = inLibrary;
@@ -284,7 +284,7 @@ void V3ParseImp::parseFile(FileLine* fileline, const string& modfilename, bool i
     if (!ok) {
         if (errmsg != "") return;  // Threw error already
         // Create fake node for later error reporting
-        AstNodeModule* const nodep = new AstNotFoundModule(fileline, modname);
+        AstNodeModule* const nodep = new AstNotFoundModule{fileline, modname};
         v3Global.rootp()->addModulesp(nodep);
         return;
     }
@@ -589,7 +589,7 @@ std::ostream& operator<<(std::ostream& os, const V3ParseBisonYYSType& rhs) {
 // V3Parse functions
 
 V3Parse::V3Parse(AstNetlist* rootp, VInFilter* filterp, V3ParseSym* symp) {
-    m_impp = new V3ParseImp(rootp, filterp, symp);
+    m_impp = new V3ParseImp{rootp, filterp, symp};
 }
 V3Parse::~V3Parse() {  //
     VL_DO_CLEAR(delete m_impp, m_impp = nullptr);
diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp
index 6aadb69f7..4bc4f0d76 100644
--- a/src/V3PreProc.cpp
+++ b/src/V3PreProc.cpp
@@ -263,10 +263,10 @@ public:
     void configure(FileLine* filelinep) {
         // configure() separate from constructor to avoid calling abstract functions
         m_preprocp = this;  // Silly, but to make code more similar to Verilog-Perl
-        m_finFilelinep = new FileLine(filelinep->filename());
+        m_finFilelinep = new FileLine{filelinep->filename()};
         m_finFilelinep->lineno(1);
         // Create lexer
-        m_lexp = new V3PreLex(this, filelinep);
+        m_lexp = new V3PreLex{this, filelinep};
         m_lexp->m_keepComments = keepComments();
         m_lexp->m_keepWhitespace = keepWhitespace();
         m_lexp->m_pedantic = pedantic();
@@ -793,7 +793,7 @@ void V3PreProcImp::openFile(FileLine*, VInFilter* filterp, const string& filenam
     }
 
     // Save file contents for future error reporting
-    FileLine* const flsp = new FileLine(filename);
+    FileLine* const flsp = new FileLine{filename};
     flsp->lineno(1);
     flsp->newContent();
     for (const string& i : wholefile) flsp->contentp()->pushText(i);
diff --git a/src/V3PreShell.cpp b/src/V3PreShell.cpp
index 0502535af..9236283ca 100644
--- a/src/V3PreShell.cpp
+++ b/src/V3PreShell.cpp
@@ -46,10 +46,10 @@ protected:
     void boot() {
         // Create the implementation pointer
         if (!s_preprocp) {
-            FileLine* const cmdfl = new FileLine(FileLine::commandLineFilename());
+            FileLine* const cmdfl = new FileLine{FileLine::commandLineFilename()};
             s_preprocp = V3PreProc::createPreProc(cmdfl);
             // Default defines
-            FileLine* const prefl = new FileLine(FileLine::builtInFilename());
+            FileLine* const prefl = new FileLine{FileLine::builtInFilename()};
             s_preprocp->defineCmdLine(prefl, "VERILATOR", "1");  // LEAK_OK
             s_preprocp->defineCmdLine(prefl, "verilator", "1");  // LEAK_OK
             s_preprocp->defineCmdLine(prefl, "verilator3", "1");  // LEAK_OK
@@ -161,7 +161,7 @@ void V3PreShell::preprocInclude(FileLine* fl, const string& modname) {
     V3PreShellImp::s_preImp.preprocInclude(fl, modname);
 }
 void V3PreShell::defineCmdLine(const string& name, const string& value) {
-    FileLine* const prefl = new FileLine(FileLine::commandLineFilename());
+    FileLine* const prefl = new FileLine{FileLine::commandLineFilename()};
     V3PreShellImp::s_preprocp->defineCmdLine(prefl, name, value);
 }
 void V3PreShell::undef(const string& name) { V3PreShellImp::s_preprocp->undef(name); }
diff --git a/src/V3Scoreboard.cpp b/src/V3Scoreboard.cpp
index d21422a81..b46aee6fb 100644
--- a/src/V3Scoreboard.cpp
+++ b/src/V3Scoreboard.cpp
@@ -58,9 +58,9 @@ void V3ScoreboardBase::selfTest() {
 
     UASSERT(!sb.needsRescore(), "SelfTest: Empty sb should not need rescore.");
 
-    ScoreboardTestElem e1(10);
-    ScoreboardTestElem e2(20);
-    ScoreboardTestElem e3(30);
+    ScoreboardTestElem e1{10};
+    ScoreboardTestElem e2{20};
+    ScoreboardTestElem e3{30};
 
     sb.add(&e1);
     sb.add(&e2);
diff --git a/src/V3String.cpp b/src/V3String.cpp
index af6122e7d..4b1f2f7f6 100644
--- a/src/V3String.cpp
+++ b/src/V3String.cpp
@@ -263,7 +263,7 @@ void VHashSha256::insert(const void* datap, size_t length) {
         // If there are large inserts it would be more efficient to avoid this copy
         // by copying bytes in the loop below from either m_remainder or the data
         // as appropriate.
-        tempData = m_remainder + string(static_cast<const char*>(datap), length);
+        tempData = m_remainder + std::string{static_cast<const char*>(datap), length};
         chunkLen = tempData.length();
         chunkp = reinterpret_cast<const uint8_t*>(tempData.data());
     }
@@ -286,7 +286,7 @@ void VHashSha256::insert(const void* datap, size_t length) {
         sha256Block(m_inthash, w);
     }
 
-    m_remainder = string(reinterpret_cast<const char*>(chunkp + posBegin), chunkLen - posEnd);
+    m_remainder = std::string(reinterpret_cast<const char*>(chunkp + posBegin), chunkLen - posEnd);
 }
 
 void VHashSha256::finalize() {
@@ -426,7 +426,7 @@ string VName::dehash(const string& in) {
         const auto begin_vhsh
             = std::search(search_begin, search_end, std::begin(VHSH), std::end(VHSH) - 1);
         if (begin_vhsh != search_end) {
-            const std::string vhsh(begin_vhsh, search_end);
+            const std::string vhsh{begin_vhsh, search_end};
             const auto& it = s_dehashMap.find(vhsh);
             UASSERT(it != s_dehashMap.end(), "String not in reverse hash map '" << vhsh << "'");
             // Is this not the first component, but the first to require dehashing?
@@ -435,13 +435,13 @@ string VName::dehash(const string& in) {
                 dehashed = in.substr(0, last_dot_pos);
             }
             // Append the unhashed part of the component.
-            dehashed += std::string(search_begin, begin_vhsh);
+            dehashed += std::string{search_begin, begin_vhsh};
             // Append the bit that was lost to truncation but retrieved from the dehash map.
             dehashed += it->second;
         }
         // This component doesn't need dehashing but a previous one might have.
         else if (!dehashed.empty()) {
-            dehashed += std::string(search_begin, search_end);
+            dehashed += std::string{search_begin, search_end};
         }
 
         if (next_dot_pos != string::npos) {
diff --git a/src/V3Subst.cpp b/src/V3Subst.cpp
index 60a664786..4df63e5c8 100644
--- a/src/V3Subst.cpp
+++ b/src/V3Subst.cpp
@@ -238,7 +238,7 @@ private:
     // METHODS
     SubstVarEntry* getEntryp(AstVarRef* nodep) {
         if (!nodep->varp()->user1p()) {
-            SubstVarEntry* const entryp = new SubstVarEntry(nodep->varp());
+            SubstVarEntry* const entryp = new SubstVarEntry{nodep->varp()};
             m_entryps.push_back(entryp);
             nodep->varp()->user1p(entryp);
             return entryp;
@@ -290,7 +290,7 @@ private:
         if (debug() > 5) nodep->dumpTree(cout, "  substw_old: ");
         AstNode* newp = substp->cloneTree(true);
         if (!nodep->isQuad() && newp->isQuad()) {
-            newp = new AstCCast(newp->fileline(), newp, nodep);
+            newp = new AstCCast{newp->fileline(), newp, nodep};
         }
         if (debug() > 5) newp->dumpTree(cout, "       w_new: ");
         nodep->replaceWith(newp);
diff --git a/src/V3TSP.cpp b/src/V3TSP.cpp
index 0e488ca45..522856da2 100644
--- a/src/V3TSP.cpp
+++ b/src/V3TSP.cpp
@@ -90,7 +90,7 @@ public:
     void addVertex(const T_Key& key) {
         const auto itr = m_vertices.find(key);
         UASSERT(itr == m_vertices.end(), "Vertex already exists with same key");
-        Vertex* v = new Vertex(this, key);
+        Vertex* v = new Vertex{this, key};
         m_vertices[key] = v;
     }
 
@@ -118,8 +118,8 @@ public:
         // which uniquely identifies a single bidir edge. Luckily we
         // can do both efficiently.
         const uint64_t userValue = (static_cast<uint64_t>(cost) << 32) | edgeId;
-        (new V3GraphEdge(this, fp, tp, cost))->user(userValue);
-        (new V3GraphEdge(this, tp, fp, cost))->user(userValue);
+        (new V3GraphEdge{this, fp, tp, cost})->user(userValue);
+        (new V3GraphEdge{this, tp, fp, cost})->user(userValue);
     }
 
     static uint32_t getEdgeId(const V3GraphEdge* edgep) {
@@ -581,11 +581,11 @@ void V3TSP::selfTestStates() {
     // Linear test -- coords all along the x-axis
     {
         V3TSP::StateVec states;
-        const TspTestState s10(10, 0);
-        const TspTestState s60(60, 0);
-        const TspTestState s20(20, 0);
-        const TspTestState s100(100, 0);
-        const TspTestState s5(5, 0);
+        const TspTestState s10{10, 0};
+        const TspTestState s60{60, 0};
+        const TspTestState s20{20, 0};
+        const TspTestState s100{100, 0};
+        const TspTestState s5{5, 0};
         states.push_back(&s10);
         states.push_back(&s60);
         states.push_back(&s20);
@@ -615,13 +615,13 @@ void V3TSP::selfTestStates() {
     // Test that tspSort() will rotate the list for minimum cost.
     {
         V3TSP::StateVec states;
-        const TspTestState a(0, 0);
-        const TspTestState b(100, 0);
-        const TspTestState c(200, 0);
-        const TspTestState d(200, 100);
-        const TspTestState e(150, 150);
-        const TspTestState f(0, 150);
-        const TspTestState g(0, 100);
+        const TspTestState a{0, 0};
+        const TspTestState b{100, 0};
+        const TspTestState c{200, 0};
+        const TspTestState d{200, 100};
+        const TspTestState e{150, 150};
+        const TspTestState f{0, 150};
+        const TspTestState g{0, 100};
 
         states.push_back(&a);
         states.push_back(&b);
diff --git a/src/V3Undriven.cpp b/src/V3Undriven.cpp
index c2a757a9b..2a2b2943d 100644
--- a/src/V3Undriven.cpp
+++ b/src/V3Undriven.cpp
@@ -267,7 +267,7 @@ private:
 
     UndrivenVarEntry* getEntryp(AstVar* nodep, int which_user) {
         if (!(which_user == 1 ? nodep->user1p() : nodep->user2p())) {
-            UndrivenVarEntry* const entryp = new UndrivenVarEntry(nodep);
+            UndrivenVarEntry* const entryp = new UndrivenVarEntry{nodep};
             // UINFO(9," Associate u="<<which_user<<" "<<cvtToHex(this)<<" "<<nodep->name()<<endl);
             m_entryps[which_user].push_back(entryp);
             if (which_user == 1) {

From aacb38b776c3d3998d37dd22d509c994407dda98 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 19 Nov 2022 15:23:37 -0500
Subject: [PATCH 064/156] Support assignment expressions.

---
 Changes                         |   1 +
 src/V3Cdc.cpp                   |   3 +-
 src/V3Delayed.cpp               |   4 +-
 src/V3DfgOptimizer.cpp          |   4 +-
 src/V3Expand.cpp                |   4 +-
 src/V3Order.cpp                 |   4 +-
 src/V3Simulate.h                |   4 +-
 src/V3Slice.cpp                 |   2 +-
 src/V3Split.cpp                 |   2 +-
 src/V3Subst.cpp                 |   3 +-
 src/V3Task.cpp                  |   2 +-
 src/V3Tristate.cpp              |   5 +-
 src/verilog.y                   | 117 ++++++++++++++++++++++----------
 test_regress/t/t_assign_expr.pl |  21 ++++++
 test_regress/t/t_assign_expr.v  |  77 +++++++++++++++++++++
 15 files changed, 201 insertions(+), 52 deletions(-)
 create mode 100755 test_regress/t/t_assign_expr.pl
 create mode 100644 test_regress/t/t_assign_expr.v

diff --git a/Changes b/Changes
index 15133343c..205064554 100644
--- a/Changes
+++ b/Changes
@@ -18,6 +18,7 @@ Verilator 5.003 devel
 * Support randcase.
 * Support pre_randomize and post_randomize.
 * Support $timeunit and $timeprecision.
+* Support assignment expressions.
 * Add ENUMVALUE warning when value misused for enum (#726).
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Change ENDLABEL from warning into an error.
diff --git a/src/V3Cdc.cpp b/src/V3Cdc.cpp
index 54edca7c1..b47dc53d3 100644
--- a/src/V3Cdc.cpp
+++ b/src/V3Cdc.cpp
@@ -237,6 +237,7 @@ private:
     // METHODS
     void iterateNewStmt(AstNode* nodep) {
         if (m_scopep) {
+            VL_RESTORER(m_logicVertexp);
             UINFO(4, "   STMT " << nodep << endl);
             m_logicVertexp = new CdcLogicVertex(&m_graph, m_scopep, nodep, m_domainp);
             if (m_domainp && m_domainp->hasClocked()) {  // To/from a flop
@@ -247,7 +248,6 @@ private:
                 m_logicVertexp->dstDomainSet(true);
             }
             iterateChildren(nodep);
-            m_logicVertexp = nullptr;
 
             if (false && debug() >= 9) {
                 UINFO(9, "Trace Logic:\n");
@@ -680,6 +680,7 @@ private:
         }
     }
     void visit(AstAssignDly* nodep) override {
+        VL_RESTORER(m_inDly);
         m_inDly = true;
         iterateChildren(nodep);
         m_inDly = false;
diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp
index 56f67b57d..db5a07182 100644
--- a/src/V3Delayed.cpp
+++ b/src/V3Delayed.cpp
@@ -505,6 +505,8 @@ private:
         nodep->deleteTree();
     }
     void visit(AstAssignDly* nodep) override {
+        VL_RESTORER(m_inDly);
+        VL_RESTORER(m_nextDlyp);
         m_inDly = true;
         m_nextDlyp
             = VN_CAST(nodep->nextp(), AssignDly);  // Next assignment in same block, maybe nullptr.
@@ -537,8 +539,6 @@ private:
         } else {
             iterateChildren(nodep);
         }
-        m_inDly = false;
-        m_nextDlyp = nullptr;
     }
 
     void visit(AstVarRef* nodep) override {
diff --git a/src/V3DfgOptimizer.cpp b/src/V3DfgOptimizer.cpp
index d3b2eba4f..94f880edb 100644
--- a/src/V3DfgOptimizer.cpp
+++ b/src/V3DfgOptimizer.cpp
@@ -190,18 +190,18 @@ class DataflowExtractVisitor final : public VNVisitor {
     }
 
     void visit(AstAssignForce* nodep) override {
+        VL_RESTORER(m_inForceReleaseLhs);
         iterate(nodep->rhsp());
         UASSERT_OBJ(!m_inForceReleaseLhs, nodep, "Should not nest");
         m_inForceReleaseLhs = true;
         iterate(nodep->lhsp());
-        m_inForceReleaseLhs = false;
     }
 
     void visit(AstRelease* nodep) override {
+        VL_RESTORER(m_inForceReleaseLhs);
         UASSERT_OBJ(!m_inForceReleaseLhs, nodep, "Should not nest");
         m_inForceReleaseLhs = true;
         iterate(nodep->lhsp());
-        m_inForceReleaseLhs = false;
     }
 
     void visit(AstNodeExpr* nodep) override { iterateChildrenConst(nodep); }
diff --git a/src/V3Expand.cpp b/src/V3Expand.cpp
index d7d957654..d67b05d5a 100644
--- a/src/V3Expand.cpp
+++ b/src/V3Expand.cpp
@@ -828,12 +828,13 @@ private:
 
     void visit(AstNodeStmt* nodep) override {
         if (nodep->user1SetOnce()) return;  // Process once
+        VL_RESTORER(m_stmtp);
         m_stmtp = nodep;
         iterateChildren(nodep);
-        m_stmtp = nullptr;
     }
     void visit(AstNodeAssign* nodep) override {
         if (nodep->user1SetOnce()) return;  // Process once
+        VL_RESTORER(m_stmtp);
         m_stmtp = nodep;
         iterateChildren(nodep);
         bool did = false;
@@ -869,7 +870,6 @@ private:
         }
         // Cleanup common code
         if (did) VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
-        m_stmtp = nullptr;
     }
 
     //--------------------
diff --git a/src/V3Order.cpp b/src/V3Order.cpp
index 450ecd583..bd3a3ee6e 100644
--- a/src/V3Order.cpp
+++ b/src/V3Order.cpp
@@ -396,15 +396,15 @@ class OrderBuildVisitor final : public VNVisitor {
     void visit(AstAssignW* nodep) override { iterateLogic(nodep); }
     void visit(AstAssignPre* nodep) override {
         UASSERT_OBJ(!m_inPre, nodep, "Should not nest");
+        VL_RESTORER(m_inPre);
         m_inPre = true;
         iterateLogic(nodep);
-        m_inPre = false;
     }
     void visit(AstAssignPost* nodep) override {
         UASSERT_OBJ(!m_inPost, nodep, "Should not nest");
+        VL_RESTORER(m_inPost);
         m_inPost = true;
         iterateLogic(nodep);
-        m_inPost = false;
     }
 
     //--- Verilator concoctions
diff --git a/src/V3Simulate.h b/src/V3Simulate.h
index 02c8344d0..788d5e696 100644
--- a/src/V3Simulate.h
+++ b/src/V3Simulate.h
@@ -759,6 +759,9 @@ private:
         if (jumpingOver(nodep)) return;
         if (!optimizable()) return;  // Accelerate
         checkNodeInfo(nodep);
+
+        VL_RESTORER(m_inDlyAssign);
+
         if (VN_IS(nodep, AssignForce)) {
             clearOptimizable(nodep, "Force");
         } else if (VN_IS(nodep, AssignDly)) {
@@ -793,7 +796,6 @@ private:
                 assignOutValue(nodep, vscp, fetchValue(nodep->rhsp()));
             }
         }
-        m_inDlyAssign = false;
     }
     void visit(AstArraySel* nodep) override {
         checkNodeInfo(nodep);
diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp
index 07041f204..6cab91c4f 100644
--- a/src/V3Slice.cpp
+++ b/src/V3Slice.cpp
@@ -156,9 +156,9 @@ class SliceVisitor final : public VNVisitor {
                 // This will potentially call this function again to resolve next level of slicing
                 return;
             }
+            VL_RESTORER(m_assignp);
             m_assignp = nodep;
             iterateChildren(nodep);
-            m_assignp = nullptr;
         }
     }
 
diff --git a/src/V3Split.cpp b/src/V3Split.cpp
index f5828b111..a27d1f62c 100644
--- a/src/V3Split.cpp
+++ b/src/V3Split.cpp
@@ -340,10 +340,10 @@ protected:
     // of what is before vs. after
 
     void visit(AstAssignDly* nodep) override {
+        VL_RESTORER(m_inDly);
         m_inDly = true;
         UINFO(4, "    ASSIGNDLY " << nodep << endl);
         iterateChildren(nodep);
-        m_inDly = false;
     }
     void visit(AstVarRef* nodep) override {
         if (!m_stmtStackps.empty()) {
diff --git a/src/V3Subst.cpp b/src/V3Subst.cpp
index 4df63e5c8..34fa8951e 100644
--- a/src/V3Subst.cpp
+++ b/src/V3Subst.cpp
@@ -252,6 +252,7 @@ private:
 
     // VISITORS
     void visit(AstNodeAssign* nodep) override {
+        VL_RESTORER(m_ops);
         m_ops = 0;
         m_assignStep++;
         iterateAndNextNull(nodep->rhsp());
@@ -360,7 +361,7 @@ private:
         doDeletes();
     }
     void visit(AstNode* nodep) override {
-        m_ops++;
+        ++m_ops;
         if (!nodep->isSubstOptimizable()) m_ops = SUBST_MAX_OPS_NA;
         iterateChildren(nodep);
     }
diff --git a/src/V3Task.cpp b/src/V3Task.cpp
index fea8d97c1..59aaca246 100644
--- a/src/V3Task.cpp
+++ b/src/V3Task.cpp
@@ -189,9 +189,9 @@ private:
         iterateChildren(nodep);
     }
     void visit(AstAssignW* nodep) override {
+        VL_RESTORER(m_assignwp);
         m_assignwp = nodep;
         VL_DO_DANGLING(iterateChildren(nodep), nodep);  // May delete nodep.
-        m_assignwp = nullptr;
     }
     void visit(AstNodeFTaskRef* nodep) override {
         // Includes handling AstMethodCall, AstNew
diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp
index 7e35067eb..d5dda0f54 100644
--- a/src/V3Tristate.cpp
+++ b/src/V3Tristate.cpp
@@ -1229,6 +1229,8 @@ class TristateVisitor final : public TristateBaseVisitor {
     void visit(AstOr* nodep) override { visitAndOr(nodep, false); }
 
     void visitAssign(AstNodeAssign* nodep) {
+        VL_RESTORER(m_alhs);
+        VL_RESTORER(m_currentStrength);
         if (m_graphing) {
             if (AstAssignW* assignWp = VN_CAST(nodep, AssignW)) addToAssignmentList(assignWp);
 
@@ -1279,9 +1281,6 @@ class TristateVisitor final : public TristateBaseVisitor {
                 }
             }
             iterateAndNextNull(nodep->lhsp());
-            // back to default strength
-            m_currentStrength = VStrength::STRONG;
-            m_alhs = false;
         }
     }
     void visit(AstAssignW* nodep) override { visitAssign(nodep); }
diff --git a/src/verilog.y b/src/verilog.y
index 9c977f542..930683c25 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -2691,18 +2691,30 @@ genvar_initialization<nodep>:   // ==IEEE: genvar_initialization
         ;
 
 genvar_iteration<nodep>:        // ==IEEE: genvar_iteration
-                varRefBase '='          expr            { $$ = new AstAssign($2,$1,$3); }
-        |       varRefBase yP_PLUSEQ    expr            { $$ = new AstAssign($2,$1,new AstAdd    ($2,$1->cloneTree(true),$3)); }
-        |       varRefBase yP_MINUSEQ   expr            { $$ = new AstAssign($2,$1,new AstSub    ($2,$1->cloneTree(true),$3)); }
-        |       varRefBase yP_TIMESEQ   expr            { $$ = new AstAssign($2,$1,new AstMul    ($2,$1->cloneTree(true),$3)); }
-        |       varRefBase yP_DIVEQ     expr            { $$ = new AstAssign($2,$1,new AstDiv    ($2,$1->cloneTree(true),$3)); }
-        |       varRefBase yP_MODEQ     expr            { $$ = new AstAssign($2,$1,new AstModDiv ($2,$1->cloneTree(true),$3)); }
-        |       varRefBase yP_ANDEQ     expr            { $$ = new AstAssign($2,$1,new AstAnd    ($2,$1->cloneTree(true),$3)); }
-        |       varRefBase yP_OREQ      expr            { $$ = new AstAssign($2,$1,new AstOr     ($2,$1->cloneTree(true),$3)); }
-        |       varRefBase yP_XOREQ     expr            { $$ = new AstAssign($2,$1,new AstXor    ($2,$1->cloneTree(true),$3)); }
-        |       varRefBase yP_SLEFTEQ   expr            { $$ = new AstAssign($2,$1,new AstShiftL ($2,$1->cloneTree(true),$3)); }
-        |       varRefBase yP_SRIGHTEQ  expr            { $$ = new AstAssign($2,$1,new AstShiftR ($2,$1->cloneTree(true),$3)); }
-        |       varRefBase yP_SSRIGHTEQ expr            { $$ = new AstAssign($2,$1,new AstShiftRS($2,$1->cloneTree(true),$3)); }
+                varRefBase '='          expr
+                        { $$ = new AstAssign{$2, $1, $3}; }
+        |       varRefBase yP_PLUSEQ    expr
+                        { $$ = new AstAssign{$2, $1, new AstAdd{$2, $1->cloneTree(true), $3}}; }
+        |       varRefBase yP_MINUSEQ   expr
+                        { $$ = new AstAssign{$2, $1, new AstSub{$2, $1->cloneTree(true), $3}}; }
+        |       varRefBase yP_TIMESEQ   expr
+                        { $$ = new AstAssign{$2, $1, new AstMul{$2, $1->cloneTree(true), $3}}; }
+        |       varRefBase yP_DIVEQ     expr
+                        { $$ = new AstAssign{$2, $1, new AstDiv{$2, $1->cloneTree(true), $3}}; }
+        |       varRefBase yP_MODEQ     expr
+                        { $$ = new AstAssign{$2, $1, new AstModDiv{$2, $1->cloneTree(true), $3}}; }
+        |       varRefBase yP_ANDEQ     expr
+                        { $$ = new AstAssign{$2, $1, new AstAnd{$2, $1->cloneTree(true), $3}}; }
+        |       varRefBase yP_OREQ      expr
+                        { $$ = new AstAssign{$2, $1, new AstOr{$2, $1->cloneTree(true), $3}}; }
+        |       varRefBase yP_XOREQ     expr
+                        { $$ = new AstAssign{$2, $1, new AstXor{$2, $1->cloneTree(true), $3}}; }
+        |       varRefBase yP_SLEFTEQ   expr
+                        { $$ = new AstAssign{$2, $1, new AstShiftL{$2, $1->cloneTree(true), $3}}; }
+        |       varRefBase yP_SRIGHTEQ  expr
+                        { $$ = new AstAssign{$2, $1, new AstShiftR{$2, $1->cloneTree(true), $3}}; }
+        |       varRefBase yP_SSRIGHTEQ expr
+                        { $$ = new AstAssign{$2, $1, new AstShiftRS{$2, $1->cloneTree(true), $3}}; }
         //                      // inc_or_dec_operator
         // When support ++ as a real AST type, maybe AstWhile::precondsp() becomes generic AstNodeExprStmt?
         |       yP_PLUSPLUS   varRefBase
@@ -3425,17 +3437,28 @@ foperator_assignment<nodep>:    // IEEE: operator_assignment (for first part of
         |       fexprLvalue '=' yD_FOPEN '(' expr ',' expr ')'  { $$ = new AstFOpen($3,$1,$5,$7); }
         //
         //UNSUP ~f~exprLvalue yP_PLUS(etc) expr         { UNSUP }
-        |       fexprLvalue yP_PLUSEQ    expr           { $$ = new AstAssign($2,$1,new AstAdd    ($2,$1->cloneTree(true),$3)); }
-        |       fexprLvalue yP_MINUSEQ   expr           { $$ = new AstAssign($2,$1,new AstSub    ($2,$1->cloneTree(true),$3)); }
-        |       fexprLvalue yP_TIMESEQ   expr           { $$ = new AstAssign($2,$1,new AstMul    ($2,$1->cloneTree(true),$3)); }
-        |       fexprLvalue yP_DIVEQ     expr           { $$ = new AstAssign($2,$1,new AstDiv    ($2,$1->cloneTree(true),$3)); }
-        |       fexprLvalue yP_MODEQ     expr           { $$ = new AstAssign($2,$1,new AstModDiv ($2,$1->cloneTree(true),$3)); }
-        |       fexprLvalue yP_ANDEQ     expr           { $$ = new AstAssign($2,$1,new AstAnd    ($2,$1->cloneTree(true),$3)); }
-        |       fexprLvalue yP_OREQ      expr           { $$ = new AstAssign($2,$1,new AstOr     ($2,$1->cloneTree(true),$3)); }
-        |       fexprLvalue yP_XOREQ     expr           { $$ = new AstAssign($2,$1,new AstXor    ($2,$1->cloneTree(true),$3)); }
-        |       fexprLvalue yP_SLEFTEQ   expr           { $$ = new AstAssign($2,$1,new AstShiftL ($2,$1->cloneTree(true),$3)); }
-        |       fexprLvalue yP_SRIGHTEQ  expr           { $$ = new AstAssign($2,$1,new AstShiftR ($2,$1->cloneTree(true),$3)); }
-        |       fexprLvalue yP_SSRIGHTEQ expr           { $$ = new AstAssign($2,$1,new AstShiftRS($2,$1->cloneTree(true),$3)); }
+        |       fexprLvalue yP_PLUSEQ    expr
+                        { $$ = new AstAssign{$2, $1, new AstAdd{$2, $1->cloneTree(true), $3}}; }
+        |       fexprLvalue yP_MINUSEQ   expr
+                        { $$ = new AstAssign{$2, $1, new AstSub{$2, $1->cloneTree(true), $3}}; }
+        |       fexprLvalue yP_TIMESEQ   expr
+                        { $$ = new AstAssign{$2, $1, new AstMul{$2, $1->cloneTree(true), $3}}; }
+        |       fexprLvalue yP_DIVEQ     expr
+                        { $$ = new AstAssign{$2, $1, new AstDiv{$2, $1->cloneTree(true), $3}}; }
+        |       fexprLvalue yP_MODEQ     expr
+                        { $$ = new AstAssign{$2, $1, new AstModDiv{$2, $1->cloneTree(true), $3}}; }
+        |       fexprLvalue yP_ANDEQ     expr
+                        { $$ = new AstAssign{$2, $1, new AstAnd{$2, $1->cloneTree(true), $3}}; }
+        |       fexprLvalue yP_OREQ      expr
+                        { $$ = new AstAssign{$2, $1, new AstOr{$2, $1->cloneTree(true), $3}}; }
+        |       fexprLvalue yP_XOREQ     expr
+                        { $$ = new AstAssign{$2, $1, new AstXor{$2, $1->cloneTree(true), $3}}; }
+        |       fexprLvalue yP_SLEFTEQ   expr
+                        { $$ = new AstAssign{$2, $1, new AstShiftL{$2, $1->cloneTree(true), $3}}; }
+        |       fexprLvalue yP_SRIGHTEQ  expr
+                        { $$ = new AstAssign{$2, $1, new AstShiftR{$2, $1->cloneTree(true), $3}}; }
+        |       fexprLvalue yP_SSRIGHTEQ expr
+                        { $$ = new AstAssign{$2, $1, new AstShiftRS{$2, $1->cloneTree(true), $3}}; }
         //UNSUP replace above with:
         //UNSUP BISONPRE_COPY(operator_assignment,{s/~f~/f/g})  // {copied}
         ;
@@ -4403,18 +4426,42 @@ expr<nodeExprp>:                // IEEE: part of expression/constant_expression/
         //
         //                      // IEEE: '(' operator_assignment ')'
         //                      // Need exprScope of variable_lvalue to prevent conflict
-        //UNSUP '(' ~p~exprScope '='          expr ')'  { UNSUP }
-        //UNSUP '(' ~p~exprScope yP_PLUSEQ    expr ')'  { UNSUP }
-        //UNSUP '(' ~p~exprScope yP_MINUSEQ   expr ')'  { UNSUP }
-        //UNSUP '(' ~p~exprScope yP_TIMESEQ   expr ')'  { UNSUP }
-        //UNSUP '(' ~p~exprScope yP_DIVEQ     expr ')'  { UNSUP }
-        //UNSUP '(' ~p~exprScope yP_MODEQ     expr ')'  { UNSUP }
-        //UNSUP '(' ~p~exprScope yP_ANDEQ     expr ')'  { UNSUP }
-        //UNSUP '(' ~p~exprScope yP_OREQ      expr ')'  { UNSUP }
-        //UNSUP '(' ~p~exprScope yP_XOREQ     expr ')'  { UNSUP }
-        //UNSUP '(' ~p~exprScope yP_SLEFTEQ   expr ')'  { UNSUP }
-        //UNSUP '(' ~p~exprScope yP_SRIGHTEQ  expr ')'  { UNSUP }
-        //UNSUP '(' ~p~exprScope yP_SSRIGHTEQ expr ')'  { UNSUP }
+        |       '(' ~p~exprScope '='          expr ')'
+                        { $$ = new AstExprStmt{$1, new AstAssign{$3, $2, $4},
+                                               $2->cloneTree(true)}; }
+        |       '(' ~p~exprScope yP_PLUSEQ    expr ')'
+                        { $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstAdd{$3, $2->cloneTree(true), $4}},
+                                               $2->cloneTree(true)}; }
+        |       '(' ~p~exprScope yP_MINUSEQ   expr ')'
+                        { $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstSub{$3, $2->cloneTree(true), $4}},
+                                               $2->cloneTree(true)}; }
+        |       '(' ~p~exprScope yP_TIMESEQ   expr ')'
+                        { $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstMul{$3, $2->cloneTree(true), $4}},
+                                               $2->cloneTree(true)}; }
+        |       '(' ~p~exprScope yP_DIVEQ     expr ')'
+                        { $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstDiv{$3, $2->cloneTree(true), $4}},
+                                               $2->cloneTree(true)}; }
+        |       '(' ~p~exprScope yP_MODEQ     expr ')'
+                        { $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstModDiv{$3, $2->cloneTree(true), $4}},
+                                               $2->cloneTree(true)}; }
+        |       '(' ~p~exprScope yP_ANDEQ     expr ')'
+                        { $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstAnd{$3, $2->cloneTree(true), $4}},
+                                               $2->cloneTree(true)}; }
+        |       '(' ~p~exprScope yP_OREQ      expr ')'
+                        { $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstOr{$3, $2->cloneTree(true), $4}},
+                                               $2->cloneTree(true)}; }
+        |       '(' ~p~exprScope yP_XOREQ     expr ')'
+                        { $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstXor{$3, $2->cloneTree(true), $4}},
+                                               $2->cloneTree(true)}; }
+        |       '(' ~p~exprScope yP_SLEFTEQ   expr ')'
+                        { $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstShiftL{$3, $2->cloneTree(true), $4}},
+                                               $2->cloneTree(true)}; }
+        |       '(' ~p~exprScope yP_SRIGHTEQ  expr ')'
+                        { $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstShiftR{$3, $2->cloneTree(true), $4}},
+                                               $2->cloneTree(true)}; }
+        |       '(' ~p~exprScope yP_SSRIGHTEQ expr ')'
+                        { $$ = new AstExprStmt{$1, new AstAssign{$3, $2, new AstShiftRS{$3, $2->cloneTree(true), $4}},
+                                               $2->cloneTree(true)}; }
         //
         //                      // IEEE: expression binary_operator expression
         |       ~l~expr '+' ~r~expr                     { $$ = new AstAdd       ($2,$1,$3); }
diff --git a/test_regress/t/t_assign_expr.pl b/test_regress/t/t_assign_expr.pl
new file mode 100755
index 000000000..1aa73f80a
--- /dev/null
+++ b/test_regress/t/t_assign_expr.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_assign_expr.v b/test_regress/t/t_assign_expr.v
new file mode 100644
index 000000000..b54320153
--- /dev/null
+++ b/test_regress/t/t_assign_expr.v
@@ -0,0 +1,77 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+module t(/*AUTOARG*/);
+
+   int a;
+   int b;
+   int i;
+
+   initial begin
+      a = 10;
+      i = (a = 2);
+      `checkd(a, 2); `checkd(i, 2);
+
+      a = 10;
+      i = (a += 2);
+      `checkd(a, 12); `checkd(i, 12);
+
+      a = 10;
+      i = (a -= 2);
+      `checkd(a, 8); `checkd(i, 8);
+
+      a = 10;
+      i = (a *= 2);
+      `checkd(a, 20); `checkd(i, 20);
+
+      a = 10;
+      i = (a /= 2);
+      `checkd(a, 5); `checkd(i, 5);
+
+      a = 11;
+      i = (a %= 2);
+      `checkd(a, 1); `checkd(i, 1);
+
+      a = 10;
+      i = (a &= 2);
+      `checkd(a, 2); `checkd(i, 2);
+
+      a = 8;
+      i = (a |= 2);
+      `checkd(a, 10); `checkd(i, 10);
+
+      a = 10;
+      i = (a ^= 2);
+      `checkd(a, 8); `checkd(i, 8);
+
+      a = 10;
+      i = (a <<= 2);
+      `checkd(a, 40); `checkd(i, 40);
+
+      a = 10;
+      i = (a >>= 2);
+      `checkd(a, 2); `checkd(i, 2);
+
+      a = 10;
+      i = (a >>>= 2);
+      `checkd(a, 2); `checkd(i, 2);
+
+      a = 10;
+      i = (a = (b = 5));
+      `checkd(a, 5); `checkd(i, 5); `checkd(b, 5);
+
+      a = 10;
+      b = 6;
+      i = ((a += (b += 1) + 1));
+      `checkd(a, 18); `checkd(i, 18); `checkd(b, 7);
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

From d3e1c40238cff7b6a44fd9681b65b1ed8061ecfa Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 19 Nov 2022 17:06:11 -0500
Subject: [PATCH 065/156] Tests: Cleaner macro. No functional change.

---
 test_regress/t/t_randcase.v | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/test_regress/t/t_randcase.v b/test_regress/t/t_randcase.v
index 0d3ff6465..cc4acb948 100644
--- a/test_regress/t/t_randcase.v
+++ b/test_regress/t/t_randcase.v
@@ -5,6 +5,7 @@
 // SPDX-License-Identifier: CC0-1.0
 
 `define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); $stop; end while(0);
+`define check_within_30_percent(gotv,val) `check_range((gotv), (val) * 70 / 100, (val) * 130 / 100)
 
 module t (/*AUTOARG*/);
 
@@ -56,8 +57,8 @@ module t (/*AUTOARG*/);
            4 : counts[1]++;
          endcase
       end
-      `check_range(counts[0], (COUNT * 1 / 5) * 70 / 100, (COUNT * 1 / 5) * 130 / 100);
-      `check_range(counts[1], (COUNT * 4 / 5) * 70 / 100, (COUNT * 4 / 5) * 130 / 100);
+      `check_within_30_percent(counts[0], (COUNT * 1 / 5));
+      `check_within_30_percent(counts[1], (COUNT * 4 / 5));
 
       //
       for (int i = 0; i < 8; ++i) counts[i] = 0;
@@ -73,10 +74,10 @@ module t (/*AUTOARG*/);
            1 : counts[7]++;  // Never
          endcase
       end
-      `check_range(counts[0], (COUNT * 2 / 10) * 70 / 100, (COUNT * 2 / 10) * 130 / 100);
-      `check_range(counts[1], (COUNT * 2 / 10) * 70 / 100, (COUNT * 2 / 10) * 130 / 100);
-      `check_range(counts[2], (COUNT * 1 / 10) * 70 / 100, (COUNT * 1 / 10) * 130 / 100);
-      `check_range(counts[7], (COUNT * 1 / 10) * 70 / 100, (COUNT * 1 / 10) * 130 / 100);
+      `check_within_30_percent(counts[0], (COUNT * 2 / 10));
+      `check_within_30_percent(counts[1], (COUNT * 2 / 10));
+      `check_within_30_percent(counts[2], (COUNT * 1 / 10));
+      `check_within_30_percent(counts[7], (COUNT * 1 / 10));
 
       //
       $write("*-* All Finished *-*\n");

From 0af3efda5c09e27bf364d021de777ab3df569932 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 19 Nov 2022 17:09:43 -0500
Subject: [PATCH 066/156] Tests: Fix top_filename to properly test (#3767)

---
 test_regress/t/t_mailbox_std.out   | 17 ++++++-----------
 test_regress/t/t_mailbox_std.pl    |  2 +-
 test_regress/t/t_process_std.out   | 19 +++++++++----------
 test_regress/t/t_process_std.pl    |  2 +-
 test_regress/t/t_semaphore_std.out | 16 ++++++----------
 test_regress/t/t_semaphore_std.pl  |  2 +-
 6 files changed, 24 insertions(+), 34 deletions(-)

diff --git a/test_regress/t/t_mailbox_std.out b/test_regress/t/t_mailbox_std.out
index d9c517f02..d09756948 100644
--- a/test_regress/t/t_mailbox_std.out
+++ b/test_regress/t/t_mailbox_std.out
@@ -1,11 +1,6 @@
-%Error: t/t_mailbox.pl:1:1: syntax error, unexpected '#'
-    1 | #!/usr/bin/env perl
-      | ^
-%Error-UNSUPPORTED: t/t_mailbox.pl:2:19: Unsupported: Verilog 2001-config reserved word not implemented: 'use'
-    2 | if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-      |                   ^~~
-                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_mailbox.pl:3:47: Unsupported: SystemVerilog 2005 reserved word not implemented: 'expect'
-    3 | # DESCRIPTION: Verilator: Verilog Test driver/expect definition
-      |                                               ^~~~~~
-%Error: Exiting due to
+%Error: t/t_mailbox.v:24:4: Can't find typedef: 'mailbox'
+   24 |    mailbox #(int) m;
+      |    ^~~~~~~
+%Error: Internal Error: t/t_mailbox.v:24:14: ../V3LinkDot.cpp:#: Pin not under instance?
+   24 |    mailbox #(int) m;
+      |              ^~~
diff --git a/test_regress/t/t_mailbox_std.pl b/test_regress/t/t_mailbox_std.pl
index 207b5f005..3b640c6e1 100755
--- a/test_regress/t/t_mailbox_std.pl
+++ b/test_regress/t/t_mailbox_std.pl
@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-top_filename("t/t_mailbox.pl");
+top_filename("t/t_mailbox.v");
 
 compile(
     v_flags2 => ["+define+T_MAILBOX+std::mailbox"],
diff --git a/test_regress/t/t_process_std.out b/test_regress/t/t_process_std.out
index 80b26b03c..a4ada3778 100644
--- a/test_regress/t/t_process_std.out
+++ b/test_regress/t/t_process_std.out
@@ -1,11 +1,10 @@
-%Error: t/t_process.pl:1:1: syntax error, unexpected '#'
-    1 | #!/usr/bin/env perl
-      | ^
-%Error-UNSUPPORTED: t/t_process.pl:2:19: Unsupported: Verilog 2001-config reserved word not implemented: 'use'
-    2 | if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-      |                   ^~~
+%Error: t/t_process.v:22:4: Can't find typedef: 'process'
+   22 |    process p;
+      |    ^~~~~~~
+%Error-UNSUPPORTED: t/t_process.v:26:20: Unsupported: 'process'
+   26 |       p = process::self();
+      |                    ^~~~
                     ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_process.pl:3:47: Unsupported: SystemVerilog 2005 reserved word not implemented: 'expect'
-    3 | # DESCRIPTION: Verilator: Verilog Test driver/expect definition
-      |                                               ^~~~~~
-%Error: Exiting due to
+%Error: Internal Error: t/t_process.v:26:11: ../V3LinkDot.cpp:#: Bad package link
+   26 |       p = process::self();
+      |           ^~~~~~~
diff --git a/test_regress/t/t_process_std.pl b/test_regress/t/t_process_std.pl
index 462019b41..0c23347b2 100755
--- a/test_regress/t/t_process_std.pl
+++ b/test_regress/t/t_process_std.pl
@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-top_filename("t/t_process.pl");
+top_filename("t/t_process.v");
 
 compile(
     v_flags2 => ["+define+T_PROCESS+std::process"],
diff --git a/test_regress/t/t_semaphore_std.out b/test_regress/t/t_semaphore_std.out
index 884a7159b..95ce89973 100644
--- a/test_regress/t/t_semaphore_std.out
+++ b/test_regress/t/t_semaphore_std.out
@@ -1,11 +1,7 @@
-%Error: t/t_semaphore.pl:1:1: syntax error, unexpected '#'
-    1 | #!/usr/bin/env perl
-      | ^
-%Error-UNSUPPORTED: t/t_semaphore.pl:2:19: Unsupported: Verilog 2001-config reserved word not implemented: 'use'
-    2 | if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-      |                   ^~~
-                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
-%Error-UNSUPPORTED: t/t_semaphore.pl:3:47: Unsupported: SystemVerilog 2005 reserved word not implemented: 'expect'
-    3 | # DESCRIPTION: Verilator: Verilog Test driver/expect definition
-      |                                               ^~~~~~
+%Error: t/t_semaphore.v:21:4: Can't find typedef: 'semaphore'
+   21 |    semaphore s;
+      |    ^~~~~~~~~
+%Error: t/t_semaphore.v:22:4: Can't find typedef: 'semaphore'
+   22 |    semaphore s2;
+      |    ^~~~~~~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_semaphore_std.pl b/test_regress/t/t_semaphore_std.pl
index b6c87f81b..ece82f871 100755
--- a/test_regress/t/t_semaphore_std.pl
+++ b/test_regress/t/t_semaphore_std.pl
@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-top_filename("t/t_semaphore.pl");
+top_filename("t/t_semaphore.v");
 
 compile(
     v_flags2 => ["+define+T_SEMAPHORE+std::semaphore"],

From e266b2cb03518ddcfbc6b99f8ef5152f57f214e1 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 19 Nov 2022 22:01:55 -0500
Subject: [PATCH 067/156] Tests: Add $dist tests

---
 test_regress/t/t_package_export.pl |  1 -
 test_regress/t/t_probdist.out      | 43 +++++++++++++++++
 test_regress/t/t_probdist.pl       | 23 +++++++++
 test_regress/t/t_probdist.v        | 77 ++++++++++++++++++++++++++++++
 test_regress/t/t_probdist_bad.out  | 19 ++++++++
 test_regress/t/t_probdist_bad.pl   | 23 +++++++++
 test_regress/t/t_probdist_bad.v    | 34 +++++++++++++
 7 files changed, 219 insertions(+), 1 deletion(-)
 create mode 100644 test_regress/t/t_probdist.out
 create mode 100755 test_regress/t/t_probdist.pl
 create mode 100644 test_regress/t/t_probdist.v
 create mode 100644 test_regress/t/t_probdist_bad.out
 create mode 100755 test_regress/t/t_probdist_bad.pl
 create mode 100644 test_regress/t/t_probdist_bad.v

diff --git a/test_regress/t/t_package_export.pl b/test_regress/t/t_package_export.pl
index 97878d3f5..bfe9a1c14 100755
--- a/test_regress/t/t_package_export.pl
+++ b/test_regress/t/t_package_export.pl
@@ -9,7 +9,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 scenarios(simulator => 1);
-$Self->{vcs} and unsupported("VCS unsupported");
 
 compile(
     v_flags2 => ['+define+T_PACKAGE_EXPORT',],
diff --git a/test_regress/t/t_probdist.out b/test_regress/t/t_probdist.out
new file mode 100644
index 000000000..a41967f44
--- /dev/null
+++ b/test_regress/t/t_probdist.out
@@ -0,0 +1,43 @@
+%Error: t/t_probdist.v:18:11: Unsupported or unknown PLI call: '$dist_chi_square'
+   18 |       r = $dist_chi_square(seed, 5);
+      |           ^~~~~~~~~~~~~~~~
+%Error: t/t_probdist.v:22:25: Unsupported or unknown PLI call: '$dist_chi_square'
+   22 |       repeat(20) sum += $dist_chi_square(seed, 5);
+      |                         ^~~~~~~~~~~~~~~~
+%Error: t/t_probdist.v:26:11: Unsupported or unknown PLI call: '$dist_erlang'
+   26 |       r = $dist_erlang(seed, 5, 10);
+      |           ^~~~~~~~~~~~
+%Error: t/t_probdist.v:30:25: Unsupported or unknown PLI call: '$dist_erlang'
+   30 |       repeat(20) sum += $dist_erlang(seed, 5, 10);
+      |                         ^~~~~~~~~~~~
+%Error: t/t_probdist.v:34:11: Unsupported or unknown PLI call: '$dist_exponential'
+   34 |       r = $dist_exponential(seed, 5);
+      |           ^~~~~~~~~~~~~~~~~
+%Error: t/t_probdist.v:38:25: Unsupported or unknown PLI call: '$dist_exponential'
+   38 |       repeat(20) sum += $dist_exponential(seed, 5);
+      |                         ^~~~~~~~~~~~~~~~~
+%Error: t/t_probdist.v:42:11: Unsupported or unknown PLI call: '$dist_normal'
+   42 |       r = $dist_normal(seed, 5, 10);
+      |           ^~~~~~~~~~~~
+%Error: t/t_probdist.v:46:25: Unsupported or unknown PLI call: '$dist_normal'
+   46 |       repeat(20) sum += $dist_normal(seed, 5, 10);
+      |                         ^~~~~~~~~~~~
+%Error: t/t_probdist.v:50:11: Unsupported or unknown PLI call: '$dist_poisson'
+   50 |       r = $dist_poisson(seed, 5);
+      |           ^~~~~~~~~~~~~
+%Error: t/t_probdist.v:54:25: Unsupported or unknown PLI call: '$dist_poisson'
+   54 |       repeat(20) sum += $dist_poisson(seed, 5);
+      |                         ^~~~~~~~~~~~~
+%Error: t/t_probdist.v:58:11: Unsupported or unknown PLI call: '$dist_t'
+   58 |       r = $dist_t(seed, 5);
+      |           ^~~~~~~
+%Error: t/t_probdist.v:62:25: Unsupported or unknown PLI call: '$dist_t'
+   62 |       repeat(20) sum += $dist_t(seed, 5);
+      |                         ^~~~~~~
+%Error: t/t_probdist.v:66:11: Unsupported or unknown PLI call: '$dist_uniform'
+   66 |       r = $dist_uniform(seed, 5, 10);
+      |           ^~~~~~~~~~~~~
+%Error: t/t_probdist.v:70:25: Unsupported or unknown PLI call: '$dist_uniform'
+   70 |       repeat(20) sum += $dist_uniform(seed, 5, 10);
+      |                         ^~~~~~~~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_probdist.pl b/test_regress/t/t_probdist.pl
new file mode 100755
index 000000000..43720dd0f
--- /dev/null
+++ b/test_regress/t/t_probdist.pl
@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
+    ) if !$Self->{vlt_all};
+
+ok(1);
+1;
diff --git a/test_regress/t/t_probdist.v b/test_regress/t/t_probdist.v
new file mode 100644
index 000000000..ae5a62a6f
--- /dev/null
+++ b/test_regress/t/t_probdist.v
@@ -0,0 +1,77 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+module t(/*AUTOARG*/);
+
+   integer seed;
+   integer r;
+   integer sum;
+
+   initial begin
+      // Illegal values
+      seed = 1234;
+      r = $dist_chi_square(seed, 5);
+      `checkd(seed, 923940542);
+      `checkd(r, 8);
+      sum = 1;
+      repeat(20) sum += $dist_chi_square(seed, 5);
+      `checkd(sum, 130);
+
+      seed = 1234;
+      r = $dist_erlang(seed, 5, 10);
+      `checkd(seed, 1025211431);
+      `checkd(r, 19);
+      sum = 1;
+      repeat(20) sum += $dist_erlang(seed, 5, 10);
+      `checkd(sum, 173);
+
+      seed = 1234;
+      r = $dist_exponential(seed, 5);
+      `checkd(seed, 85231147);
+      `checkd(r, 20);
+      sum = 1;
+      repeat(20) sum += $dist_exponential(seed, 5);
+      `checkd(sum, 104);
+
+      seed = 1234;
+      r = $dist_normal(seed, 5, 10);
+      `checkd(seed, -1570070672);
+      `checkd(r, 4);
+      sum = 1;
+      repeat(20) sum += $dist_normal(seed, 5, 10);
+      `checkd(sum, 114);
+
+      seed = 1234;
+      r = $dist_poisson(seed, 5);
+      `checkd(seed, 418012337);
+      `checkd(r, 2);
+      sum = 1;
+      repeat(20) sum += $dist_poisson(seed, 5);
+      `checkd(sum, 111);
+
+      seed = 1234;
+      r = $dist_t(seed, 5);
+      `checkd(seed, -797481412);
+      `checkd(r, 0);
+      sum = 1;
+      repeat(20) sum += $dist_t(seed, 5);
+      `checkd(sum, -2);
+
+      seed = 1234;
+      r = $dist_uniform(seed, 5, 10);
+      `checkd(seed, 85231147);
+      `checkd(r, 5);
+      sum = 1;
+      repeat(20) sum += $dist_uniform(seed, 5, 10);
+      `checkd(sum, 147);
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
diff --git a/test_regress/t/t_probdist_bad.out b/test_regress/t/t_probdist_bad.out
new file mode 100644
index 000000000..9d7008ac9
--- /dev/null
+++ b/test_regress/t/t_probdist_bad.out
@@ -0,0 +1,19 @@
+%Error: t/t_probdist_bad.v:16:11: Unsupported or unknown PLI call: '$dist_chi_square'
+   16 |       r = $dist_chi_square(seed, 0);
+      |           ^~~~~~~~~~~~~~~~
+%Error: t/t_probdist_bad.v:18:11: Unsupported or unknown PLI call: '$dist_erlang'
+   18 |       r = $dist_erlang(seed, 0, 0);
+      |           ^~~~~~~~~~~~
+%Error: t/t_probdist_bad.v:20:11: Unsupported or unknown PLI call: '$dist_exponential'
+   20 |       r = $dist_exponential(seed, 0);
+      |           ^~~~~~~~~~~~~~~~~
+%Error: t/t_probdist_bad.v:23:11: Unsupported or unknown PLI call: '$dist_poisson'
+   23 |       r = $dist_poisson(seed, 0);
+      |           ^~~~~~~~~~~~~
+%Error: t/t_probdist_bad.v:25:11: Unsupported or unknown PLI call: '$dist_t'
+   25 |       r = $dist_t(seed, 0);
+      |           ^~~~~~~
+%Error: t/t_probdist_bad.v:27:11: Unsupported or unknown PLI call: '$dist_uniform'
+   27 |       r = $dist_uniform(seed, 10, 0);
+      |           ^~~~~~~~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_probdist_bad.pl b/test_regress/t/t_probdist_bad.pl
new file mode 100755
index 000000000..43720dd0f
--- /dev/null
+++ b/test_regress/t/t_probdist_bad.pl
@@ -0,0 +1,23 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
+    );
+
+execute(
+    check_finished => 1,
+    ) if !$Self->{vlt_all};
+
+ok(1);
+1;
diff --git a/test_regress/t/t_probdist_bad.v b/test_regress/t/t_probdist_bad.v
new file mode 100644
index 000000000..ee297af1e
--- /dev/null
+++ b/test_regress/t/t_probdist_bad.v
@@ -0,0 +1,34 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+module t(/*AUTOARG*/);
+
+   integer seed;
+   integer r;
+
+   initial begin
+      // Illegal values
+      r = $dist_chi_square(seed, 0);
+      if (r != 0 && !$isunknown(r)) $stop;
+      r = $dist_erlang(seed, 0, 0);
+      if (r != 0 && !$isunknown(r)) $stop;
+      r = $dist_exponential(seed, 0);
+      if (r != 0 && !$isunknown(r)) $stop;
+      // r =$dist_exponential(seed, mean);  // Always valid
+      r = $dist_poisson(seed, 0);
+      if (r != 0 && !$isunknown(r)) $stop;
+      r = $dist_t(seed, 0);
+      if (r != 0 && !$isunknown(r)) $stop;
+      r = $dist_uniform(seed, 10, 0);
+      if (r != 10 && !$isunknown(r)) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

From 5634e96bb6151b7a1d7f70e57ab81186d74d3793 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 19 Nov 2022 22:43:10 -0500
Subject: [PATCH 068/156] Tests: Remove unsupported() in tests, instead check
 whatever is current behavior

---
 test_regress/driver.pl                        |  71 ++++-------
 test_regress/t/t_class_dead.pl                |   7 +-
 test_regress/t/t_dpi_shortcircuit.out         |  18 +++
 test_regress/t/t_dpi_shortcircuit.pl          |   9 +-
 test_regress/t/t_dpi_shortcircuit.v           |  10 +-
 test_regress/t/t_dpi_shortcircuit2.v          |  13 +--
 test_regress/t/t_dpi_shortcircuit_c.cpp       |   5 +-
 test_regress/t/t_genvar_misuse_bad.pl         |   6 +-
 test_regress/t/t_inst_aport.pl                |  22 ----
 test_regress/t/t_inst_aport.v                 | 110 ------------------
 test_regress/t/t_interface_down_gen.pl        |  23 ----
 test_regress/t/t_interface_down_gen.v         |  79 -------------
 .../t/t_interface_modport_dir_bad.out         |  17 +--
 test_regress/t/t_interface_modport_dir_bad.pl |   2 -
 test_regress/t/t_interface_modport_export.out |   8 ++
 test_regress/t/t_interface_modport_export.pl  |   5 +-
 test_regress/t/t_interface_param2.out         |   8 ++
 test_regress/t/t_interface_param2.pl          |   6 +-
 test_regress/t/t_interface_param_loop_bad.pl  |   7 +-
 .../t/t_interface_parent_scope_bad.pl         |   7 +-
 test_regress/t/t_mem_bound_bad.pl             |   5 +-
 test_regress/t/t_param_width_loc_bad.out      |  22 +---
 test_regress/t/t_param_width_loc_bad.pl       |   2 -
 test_regress/t/t_param_width_loc_bad.v        |   1 +
 test_regress/t/t_tri_array.out                |  21 ++++
 test_regress/t/t_tri_array.pl                 |   7 +-
 26 files changed, 128 insertions(+), 363 deletions(-)
 create mode 100644 test_regress/t/t_dpi_shortcircuit.out
 delete mode 100755 test_regress/t/t_inst_aport.pl
 delete mode 100644 test_regress/t/t_inst_aport.v
 delete mode 100755 test_regress/t/t_interface_down_gen.pl
 delete mode 100644 test_regress/t/t_interface_down_gen.v
 create mode 100644 test_regress/t/t_interface_modport_export.out
 create mode 100644 test_regress/t/t_interface_param2.out
 create mode 100644 test_regress/t/t_tri_array.out

diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 1f227d341..3507e013d 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -87,7 +87,6 @@ my $opt_stop;
 my $opt_trace;
 my $opt_verbose;
 my $Opt_Verilated_Debug;
-our $Opt_Unsupported;
 our $Opt_Verilation = 1;
 our @Opt_Driver_Verilator_Flags;
 
@@ -111,7 +110,6 @@ if (! GetOptions(
           "site!"       => \$opt_site,
           "stop!"       => \$opt_stop,
           "trace!"      => \$opt_trace,
-          "unsupported!"=> \$Opt_Unsupported,
           "verbose!"    => \$opt_verbose,
           "verilation!"         => \$Opt_Verilation,  # Undocumented debugging
           "verilated-debug!"    => \$Opt_Verilated_Debug,
@@ -197,8 +195,7 @@ if ($opt_rerun && $runner->fail_count) {
         quiet => 0,
         fail1_cnt => $orig_runner->fail_count,
         ok_cnt => $orig_runner->{ok_cnt},
-        skip_cnt => $orig_runner->{skip_cnt},
-        unsup_cnt => $orig_runner->{unsup_cnt});
+        skip_cnt => $orig_runner->{skip_cnt});
     foreach my $test (@{$orig_runner->{fail_tests}}) {
         $test->clean;
         # Reschedule test
@@ -313,7 +310,6 @@ sub new {
         fail1_cnt => 0,
         fail_cnt => 0,
         skip_cnt => 0,
-        unsup_cnt => 0,
         skip_msgs => [],
         fail_msgs => [],
         fail_tests => [],
@@ -374,8 +370,6 @@ sub one_test {
                  push @{$self->{skip_msgs}},
                      ("\t#" . $test->soprint("-Skip:  $test->{skips}\n"));
                  $self->{skip_cnt}++;
-             } elsif ($test->unsupporteds && !$test->errors) {
-                 $self->{unsup_cnt}++;
              } else {
                  $test->oprint("FAILED: $test->{errors}\n");
                  my $j = ($opt_jobs > 1 ? " -j" : "");
@@ -485,7 +479,6 @@ sub sprint_summary {
     $out .= "  Failed $self->{fail_cnt}";
     $out .= "  Failed-First $self->{fail1_cnt}" if $self->{fail1_cnt};
     $out .= "  Skipped $self->{skip_cnt}" if $self->{skip_cnt};
-    $out .= "  Unsup $self->{unsup_cnt}";
     $out .= sprintf("  Eta %d:%02d", int($eta / 60), $eta % 60) if $self->{left_cnt} > 10 && $eta > 10;
     $out .= sprintf("  Time %d:%02d", int($delta / 60), $delta % 60);
     return $out;
@@ -751,16 +744,6 @@ sub skip {
     $self->{skips} ||= "Skip: " . $msg;
 }
 
-sub unsupported {
-    my $self = (ref $_[0] ? shift : $Self);
-    my $msg = join('', @_);
-    # Called from tests as: unsupported("Reason message"[, ...]);
-    warn "-Unsupported: $self->{scenario}/$self->{name}: " . $msg . "\n";
-    if (!$::Opt_Unsupported) {
-        $self->{unsupporteds} ||= "Unsupported: " . $msg;
-    }
-}
-
 sub scenarios {
     my $self = (ref $_[0] ? shift : $Self);
     my %params = (@_);
@@ -815,8 +798,6 @@ sub _exit {
         $self->oprint("Self PASSED\n");
     } elsif ($self->skips && !$self->errors) {
         $self->oprint("-Skip: $self->{skips}\n");
-    } elsif ($self->unsupporteds && !$self->errors) {
-        $self->oprint("%Unsupported: $self->{unsupporteds}\n");
     } else {
         $self->error("Missing ok\n") if !$self->errors;
         $self->oprint("%Error: $self->{errors}\n");
@@ -882,7 +863,7 @@ sub clean_objs {
 sub compile_vlt_cmd {
     my $self = (ref $_[0] ? shift : $Self);
     my %param = (%{$self}, @_);  # Default arguments are from $self
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
 
     my @vlt_cmd = (
         "perl", "$ENV{VERILATOR_ROOT}/bin/verilator",
@@ -897,7 +878,7 @@ sub compile_vlt_cmd {
 sub compile_vlt_flags {
     my $self = (ref $_[0] ? shift : $Self);
     my %param = (%{$self}, @_);  # Default arguments are from $self
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
 
     my $checkflags = join(' ', @{$param{v_flags}},
                           @{$param{v_flags2}},
@@ -971,7 +952,7 @@ sub compile {
     my $self = (ref $_[0] ? shift : $Self);
     my %param = (tee => 1,
                  %{$self}, @_);  # Default arguments are from $self
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
     $self->oprint("Compile\n") if $self->{verbose};
 
     die "%Error: 'threads =>' argument must be <= 1 for vlt scenario" if $param{vlt} && $param{threads} > 1;
@@ -1139,7 +1120,7 @@ sub compile {
                         expect_filename => $param{expect_filename},
                         verilator_run => 1,
                         cmd => \@vlt_cmd) if $::Opt_Verilation;
-            return 1 if $self->errors || $self->skips || $self->unsupporteds;
+            return 1 if $self->errors || $self->skips;
         }
 
         if ($param{verilator_make_cmake}) {
@@ -1168,7 +1149,7 @@ sub compile {
                                 "-DTEST_OPT_GLOBAL=\"" . ($param{benchmark} ? "-Os" : "-O0") . "\"",
                                 "-DTEST_VERILATION=\"" . $::Opt_Verilation . "\"",
                         ]);
-            return 1 if $self->errors || $self->skips || $self->unsupporteds;
+            return 1 if $self->errors || $self->skips;
         }
 
         if (!$param{fails} && $param{verilator_make_gmake}) {
@@ -1220,7 +1201,7 @@ sub compile {
 
 sub execute {
     my $self = (ref $_[0] ? shift : $Self);
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
     my %param = (%{$self}, @_);  # Default arguments are from $self
     # params may be expect or {tool}_expect
     $self->oprint("Run\n") if $self->{verbose};
@@ -1367,7 +1348,7 @@ sub setenv {
 
 sub inline_checks {
     my $self = (ref $_[0] ? shift : $Self);
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
     return 1 if !$self->{vlt_all};
 
     my %param = (%{$self}, @_);  # Default arguments are from $self
@@ -1412,13 +1393,13 @@ sub inline_checks {
 sub ok {
     my $self = (ref $_[0] ? shift : $Self);
     $self->{ok} = $_[0] if defined $_[0];
-    $self->{ok} = 0 if $self->{errors} || $self->{errors_keep_going} || $self->{skips} || $self->unsupporteds;
+    $self->{ok} = 0 if $self->{errors} || $self->{errors_keep_going} || $self->{skips};
     return $self->{ok};
 }
 
 sub continuing {
     my $self = (ref $_[0] ? shift : $Self);
-    return !($self->errors || $self->skips || $self->unsupporteds);
+    return !($self->errors || $self->skips);
 }
 
 sub errors {
@@ -1442,11 +1423,6 @@ sub skips {
     return $self->{skips};
 }
 
-sub unsupporteds {
-    my $self = (ref $_[0] ? shift : $Self);
-    return $self->{unsupporteds};
-}
-
 sub top_filename {
     my $self = (ref $_[0] ? shift : $Self);
     $self->{top_filename} = shift if defined $_[0];
@@ -1662,7 +1638,7 @@ sub _run {
     if ($param{fails} && !$status) {
         $self->error("Exec of $param{cmd}[0] ok, but expected to fail\n");
     }
-    return if $self->errors || $self->skips || $self->unsupporteds;
+    return if $self->errors || $self->skips;
 
     # Read the log file a couple of times to allow for NFS delays
     if ($param{check_finished} || $param{expect}) {
@@ -2186,7 +2162,7 @@ sub files_identical {
     my $fn1 = shift;
     my $fn2 = shift;
     my $fn1_is_logfile = shift;
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
 
   try:
     for (my $try = $self->tries - 1; $try >= 0; $try--) {
@@ -2263,7 +2239,7 @@ sub files_identical_sorted {
     my $fn1 = shift;
     my $fn2 = shift;
     my $fn1_is_logfile = shift;
-    return 1 if $self->errors || $self->skips || $self->unsupporteds;
+    return 1 if $self->errors || $self->skips;
     # Set LC_ALL as suggested in the sort manpage to avoid sort order
     # changes from the locale.
     setenv('LC_ALL', "C");
@@ -2287,7 +2263,7 @@ sub vcd_identical {
     my $self = (ref $_[0] ? shift : $Self);
     my $fn1 = shift;
     my $fn2 = shift;
-    return 0 if $self->errors || $self->skips || $self->unsupporteds;
+    return 0 if $self->errors || $self->skips;
     if (!-r $fn1) { $self->error("Vcd_identical file does not exist $fn1\n"); return 0; }
     if (!-r $fn2) { $self->error("Vcd_identical file does not exist $fn2\n"); return 0; }
     {
@@ -2350,7 +2326,7 @@ sub fst_identical {
     my $self = (ref $_[0] ? shift : $Self);
     my $fn1 = shift;
     my $fn2 = shift;
-    return 0 if $self->errors || $self->skips || $self->unsupporteds;
+    return 0 if $self->errors || $self->skips;
     my $tmp = $fn1 . ".vcd";
     fst2vcd($fn1, $tmp);
     return vcd_identical($tmp, $fn2);
@@ -2424,7 +2400,7 @@ sub glob_all {
 sub glob_one {
     my $self = (ref $_[0] ? shift : $Self);
     my $pattern = shift;
-    return if $self->errors || $self->skips || $self->unsupporteds;
+    return if $self->errors || $self->skips;
 
     my @files = glob($pattern);
     my $n = scalar @files;
@@ -2446,7 +2422,7 @@ sub file_grep_not {
     my $filename = shift;
     my $regexp = shift;
     my $expvalue = shift;
-    return if $self->errors || $self->skips || $self->unsupporteds;
+    return if $self->errors || $self->skips;
     !defined $expvalue or $self->error("file_grep_not: Unexpected 3rd argument: $expvalue");
 
     my $contents = $self->file_contents($filename);
@@ -2461,7 +2437,7 @@ sub file_grep {
     my $filename = shift;
     my $regexp = shift;
     my $expvalue = shift;
-    return if $self->errors || $self->skips || $self->unsupporteds;
+    return if $self->errors || $self->skips;
 
     my $contents = $self->file_contents($filename);
     return if ($contents eq "_Already_Errored_");
@@ -2477,7 +2453,7 @@ sub file_grep_any {
     my @filenames = @{$_[0]}; shift;
     my $regexp = shift;
     my $expvalue = shift;
-    return if $self->errors || $self->skips || $self->unsupporteds;
+    return if $self->errors || $self->skips;
 
     foreach my $filename (@filenames) {
         my $contents = $self->file_contents($filename);
@@ -2674,9 +2650,8 @@ driver.pl - Run regression tests
 
 driver.pl invokes Verilator or another simulator on each test file.
 
-The driver reports the number of tests which pass, fail, skipped (some
-resource required by the test is not available, such as SystemC), or are
-unsupported (buggy or require a feature change before will pass.)
+The driver reports the number of tests which pass, fail, or skipped (some
+resource required by the test is not available, such as SystemC).
 
 There are hundreds of tests, and for faster completion you may want to run
 the regression tests with OBJCACHE enabled and in parallel on a machine
@@ -2976,10 +2951,6 @@ Stop on the first error.
 
 Set the simulator specific flags to request waveform tracing.
 
-=item --unsupported
-
-Run tests even if marked as unsupported.
-
 =item --verbose
 
 Compile and run the test in verbose mode. This means C<TEST_VERBOSE> will
diff --git a/test_regress/t/t_class_dead.pl b/test_regress/t/t_class_dead.pl
index fd702254d..0ba7b4fd1 100755
--- a/test_regress/t/t_class_dead.pl
+++ b/test_regress/t/t_class_dead.pl
@@ -8,8 +8,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-$Self->{vlt_all} and unsupported("Verilator unsupported, class dead");
-
 scenarios(simulator => 1);
 
 compile(
@@ -19,7 +17,10 @@ execute(
     check_finished => 1,
     );
 
-file_grep_not("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/dead/ix);
+# bug2227, Verilator unsupported, class dead
+# This is what we really want:
+#   file_grep_not("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/dead/ix);
+file_grep("$Self->{obj_dir}/V$Self->{name}__Syms.h", qr/dead/ix);
 
 ok(1);
 1;
diff --git a/test_regress/t/t_dpi_shortcircuit.out b/test_regress/t/t_dpi_shortcircuit.out
new file mode 100644
index 000000000..e1463672b
--- /dev/null
+++ b/test_regress/t/t_dpi_shortcircuit.out
@@ -0,0 +1,18 @@
+%Error: Line 60: Bad result, got=1 expect=0
+%Error: Line 64: Bad result, got=1 expect=0
+%Error: Line 75: Bad result, got=0 expect=1
+%Error: Line 98: Bad result, got=1 expect=0
+%Error: Line 102: Bad result, got=1 expect=0
+%Error: Line 112: Bad result, got=0 expect=1
+%Error: Line 132: Bad result, got=1 expect=0
+%Error: Line 136: Bad result, got=1 expect=0
+%Error: Line 150: Bad result, got=1 expect=0
+%Error: Line 154: Bad result, got=1 expect=0
+%Error: Line 163: Bad result, got=0 expect=1
+%Error: Line 203: Bad result, got=64 expect=32
+%Error: Line 204: Bad result, got=64 expect=16
+%Error: Line 205: Bad result, got=64 expect=16
+%Error: Line 206: Bad result, got=64 expect=36
+%Error: Line 207: Bad result, got=64 expect=46
+%Error: t/t_dpi_shortcircuit.v:209: Verilog $stop
+Aborting...
diff --git a/test_regress/t/t_dpi_shortcircuit.pl b/test_regress/t/t_dpi_shortcircuit.pl
index d0b657ca1..ee25e9d79 100755
--- a/test_regress/t/t_dpi_shortcircuit.pl
+++ b/test_regress/t/t_dpi_shortcircuit.pl
@@ -8,17 +8,18 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-scenarios(simulator => 1);
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug413 short circuit");
+scenarios(vlt => 1);
 
 compile(
-    # Amazingly VCS, NC and Verilator all just accept the C file here!
     v_flags2 => ["t/t_dpi_shortcircuit_c.cpp"],
     verilator_flags2 => ["-Wno-DECLFILENAME"],
     );
 
 execute(
-    check_finished => 1,
+    # Should pass, Verilator unsupported, bug413 short circuit");
+    fails => $Self->{vlt},
+    check_finished => !$Self->{vlt},
+    expect_filename => $Self->{golden_filename},
     );
 
 ok(1);
diff --git a/test_regress/t/t_dpi_shortcircuit.v b/test_regress/t/t_dpi_shortcircuit.v
index 6aeb3a5e7..b89cdffd4 100644
--- a/test_regress/t/t_dpi_shortcircuit.v
+++ b/test_regress/t/t_dpi_shortcircuit.v
@@ -19,11 +19,11 @@
 module t (/*AUTOARG*/);
 
    // Note these are NOT pure.
-   import "DPI-C" function int dpii_clear ();
-   import "DPI-C" function int dpii_count (input int ctr);
-   import "DPI-C" function bit dpii_inc0  (input int ctr);
-   import "DPI-C" function bit dpii_inc1  (input int ctr);
-   import "DPI-C" function bit dpii_incx  (input int ctr, input bit value);
+   import "DPI-C" function void dpii_clear();
+   import "DPI-C" function int dpii_count(input int ctr);
+   import "DPI-C" function bit dpii_inc0(input int ctr);
+   import "DPI-C" function bit dpii_inc1(input int ctr);
+   import "DPI-C" function bit dpii_incx(input int ctr, input bit value);
 
    integer i;
    integer j;
diff --git a/test_regress/t/t_dpi_shortcircuit2.v b/test_regress/t/t_dpi_shortcircuit2.v
index 07b90a38e..2fcd47c7d 100644
--- a/test_regress/t/t_dpi_shortcircuit2.v
+++ b/test_regress/t/t_dpi_shortcircuit2.v
@@ -19,11 +19,11 @@
 module t (/*AUTOARG*/);
 
    // Note these are NOT pure.
-   import "DPI-C" function int dpii_clear ();
-   import "DPI-C" function int dpii_count (input int ctr);
-   import "DPI-C" function bit dpii_inc0  (input int ctr);
-   import "DPI-C" function bit dpii_inc1  (input int ctr);
-   import "DPI-C" function bit dpii_incx  (input int ctr, input bit value);
+   import "DPI-C" function void dpii_clear();
+   import "DPI-C" function int dpii_count(input int ctr);
+   import "DPI-C" function bit dpii_inc0(input int ctr);
+   import "DPI-C" function bit dpii_inc1(input int ctr);
+   import "DPI-C" function bit dpii_incx(input int ctr, input bit value);
 
    integer i;
    integer j;
@@ -46,10 +46,7 @@ module t (/*AUTOARG*/);
 
    // Test loop
    initial begin
-      // bug963
-      // verilator lint_off IGNOREDRETURN
       dpii_clear();
-      // verilator lint_on IGNOREDRETURN
       j = 0;
       for (i=0; i<64; i++) begin
          if (i[0])
diff --git a/test_regress/t/t_dpi_shortcircuit_c.cpp b/test_regress/t/t_dpi_shortcircuit_c.cpp
index 9abe7e53d..12ff41438 100644
--- a/test_regress/t/t_dpi_shortcircuit_c.cpp
+++ b/test_regress/t/t_dpi_shortcircuit_c.cpp
@@ -36,7 +36,7 @@
 
 #ifdef NEED_EXTERNS
 extern "C" {
-extern int dpii_clear();
+extern void dpii_clear();
 extern int dpii_count(int idx);
 extern unsigned char dpii_inc0(int idx);
 extern unsigned char dpii_inc1(int idx);
@@ -49,9 +49,8 @@ extern unsigned char dpii_incx(int idx, unsigned char value);
 #define COUNTERS 16
 static int global_count[COUNTERS];
 
-int dpii_clear() {
+void dpii_clear() {
     for (int i = 0; i < COUNTERS; ++i) global_count[i] = 0;
-    return 0;
 }
 int dpii_count(int idx) { return (idx >= 0 && idx < COUNTERS) ? global_count[idx] : -1; }
 unsigned char dpii_incx(int idx, unsigned char value) {
diff --git a/test_regress/t/t_genvar_misuse_bad.pl b/test_regress/t/t_genvar_misuse_bad.pl
index 18a57407e..05585a90b 100755
--- a/test_regress/t/t_genvar_misuse_bad.pl
+++ b/test_regress/t/t_genvar_misuse_bad.pl
@@ -9,11 +9,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 scenarios(linter => 1);
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug408");
 
 lint(
-    fails => 1,
-    expect_filename => $Self->{golden_filename},
+    # Should fail, but bug408, Verilator unsupported
+    fails => !$Self->{vlt},
+    # expect_filename => $Self->{golden_filename},
     );
 
 ok(1);
diff --git a/test_regress/t/t_inst_aport.pl b/test_regress/t/t_inst_aport.pl
deleted file mode 100755
index 9a383863d..000000000
--- a/test_regress/t/t_inst_aport.pl
+++ /dev/null
@@ -1,22 +0,0 @@
-#!/usr/bin/env perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-scenarios(simulator => 1);
-unsupported("Verilator/commercial slice unsupported, bug711");
-
-compile(
-    );
-
-execute(
-    check_finished => 1,
-    );
-
-ok(1);
-1;
diff --git a/test_regress/t/t_inst_aport.v b/test_regress/t/t_inst_aport.v
deleted file mode 100644
index e14dcea1a..000000000
--- a/test_regress/t/t_inst_aport.v
+++ /dev/null
@@ -1,110 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2014 by Wilson Snyder.
-// SPDX-License-Identifier: CC0-1.0
-
-module t (/*AUTOARG*/
-   // Inputs
-   clk
-   );
-   input clk;
-
-   integer      cyc = 0;
-   reg [63:0]   crc;
-   reg [63:0]   sum;
-
-   // Take CRC data and apply to testblock inputs
-   wire [31:0]  in = crc[31:0];
-
-   /*AUTOWIRE*/
-   // Beginning of automatic wires (for undeclared instantiated-module outputs)
-   wire [15:0]          out;                    // From test of Test.v
-   // End of automatics
-
-   Test test (/*AUTOINST*/
-              // Outputs
-              .out                      (out[15:0]),
-              // Inputs
-              .in                       (in[31:0]));
-
-   // Aggregate outputs into a single result vector
-   wire [63:0] result = {48'h0, out};
-
-   // Test loop
-   always @ (posedge clk) begin
-`ifdef TEST_VERBOSE
-      $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
-`endif
-      cyc <= cyc + 1;
-      crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
-      sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
-      if (cyc==0) begin
-         // Setup
-         crc <= 64'h5aef0c8d_d70a4497;
-         sum <= 64'h0;
-      end
-      else if (cyc<10) begin
-         sum <= 64'h0;
-      end
-      else if (cyc<90) begin
-      end
-      else if (cyc==99) begin
-         $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
-         if (crc !== 64'hc77bb9b3784ea091) $stop;
-         // What checksum will we end up with (above print should match)
-`define EXPECTED_SUM 64'h4afe43fb79d7b71e
-         if (sum !== `EXPECTED_SUM) $stop;
-         $write("*-* All Finished *-*\n");
-         $finish;
-      end
-   end
-
-endmodule
-
-module callee (input [7:0] port [7:0], output [7:0] o);
-   assign o = ^{port[0], port[1], port[2], port[3],
-                port[4], port[5], port[6], port[7]};
-endmodule // callee
-
-module Test (/*AUTOARG*/
-   // Outputs
-   out,
-   // Inputs
-   in
-   );
-
-   input [31:0] in;
-   output reg [15:0] out;
-
-   wire [7:0] port [15:0];
-   wire [7:0] goodport [7:0];
-
-   always_comb begin
-      port[0][7:0] = in[7:0];
-      port[1][7:0] = in[16:8];
-      port[2] = '0;
-      port[3] = '0;
-      port[4] = '0;
-      port[5] = '0;
-      port[6] = '0;
-      port[7] = '0;
-   end
-
-   always_comb begin
-      goodport[0][7:0] = in[7:0];
-      goodport[1][7:0] = in[16:8];
-      goodport[2] = '0;
-      goodport[3] = '0;
-      goodport[4] = '0;
-      goodport[5] = '0;
-      goodport[6] = '0;
-      goodport[7] = '0;
-   end
-
-   callee good (.port(goodport), .o(out[7:0]));
-
-   // This is a slice, unsupported by other tools, bug711
-   callee bad (.port(port[7:0]), .o(out[15:8]));
-
-endmodule
diff --git a/test_regress/t/t_interface_down_gen.pl b/test_regress/t/t_interface_down_gen.pl
deleted file mode 100755
index d0a85e8ea..000000000
--- a/test_regress/t/t_interface_down_gen.pl
+++ /dev/null
@@ -1,23 +0,0 @@
-#!/usr/bin/env perl
-if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
-# DESCRIPTION: Verilator: Verilog Test driver/expect definition
-#
-# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
-# can redistribute it and/or modify it under the terms of either the GNU
-# Lesser General Public License Version 3 or the Perl Artistic License
-# Version 2.0.
-# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
-
-scenarios(simulator => 1);
-$Self->{vlt_all} and unsupported("Verilator unsupported, interface generates changing types");
-$Self->{vcs} and unsupported("Commercially unsupported, interface crossrefs");
-
-compile(
-    );
-
-execute(
-    check_finished => 1,
-    );
-
-ok(1);
-1;
diff --git a/test_regress/t/t_interface_down_gen.v b/test_regress/t/t_interface_down_gen.v
deleted file mode 100644
index fb65dae46..000000000
--- a/test_regress/t/t_interface_down_gen.v
+++ /dev/null
@@ -1,79 +0,0 @@
-// DESCRIPTION: Verilator: Verilog Test module
-//
-// This file ONLY is placed under the Creative Commons Public Domain, for
-// any use, without warranty, 2013 by Wilson Snyder.
-// SPDX-License-Identifier: CC0-1.0
-
-// This test demonstrates how not only parameters but the type of a parent
-// interface could propagate down to child modules, changing their data type
-// determinations.  Note presently unsupported in all commercial simulators.
-
-interface ifc;
-   parameter MODE = 0;
-   generate
-      // Note block must be named per SystemVerilog 2005
-      if (MODE==1) begin : g
-         integer value;
-      end
-      else if (MODE==2) begin : g
-         real value;
-      end
-   endgenerate
-endinterface
-
-module t (/*AUTOARG*/
-   // Inputs
-   clk
-   );
-
-   input clk;
-   integer cyc=1;
-
-   ifc #(1) itop1a();
-   ifc #(1) itop1b();
-   ifc #(2) itop2a();
-   ifc #(2) itop2b();
-
-   wrapper  c1 (.isuba(itop1a),
-                .isubb(itop1b),
-                .i_valuea(14.1),
-                .i_valueb(15.2));
-   wrapper  c2 (.isuba(itop2a),
-                .isubb(itop2b),
-                .i_valuea(24.3),
-                .i_valueb(25.4));
-
-   always @ (posedge clk) begin
-      cyc <= cyc + 1;
-      if (cyc==20) begin
-         if (itop1a.g.value != 14) $stop;
-         if (itop1b.g.value != 15) $stop;
-         if (itop2a.g.value != 24) $stop;
-         if (itop2b.g.value != 25) $stop;
-         $write("*-* All Finished *-*\n");
-         $finish;
-      end
-   end
-endmodule
-
-module wrapper
-  (
-   ifc isuba,
-   ifc isubb,
-   input real i_valuea,
-   input real i_valueb
-   );
-   lower subsuba (.isub(isuba), .i_value(i_valuea));
-   lower subsubb (.isub(isubb), .i_value(i_valueb));
-endmodule
-
-module lower
-  (
-   ifc isub,
-   input real i_value
-   );
-   always @* begin
-`error Commercial sims choke on cross ref here
-      isub.g.value = i_value;
-   end
-endmodule
diff --git a/test_regress/t/t_interface_modport_dir_bad.out b/test_regress/t/t_interface_modport_dir_bad.out
index 927f0c16e..d7783d86d 100644
--- a/test_regress/t/t_interface_modport_dir_bad.out
+++ b/test_regress/t/t_interface_modport_dir_bad.out
@@ -1,12 +1,5 @@
-Expecting something along the line of:
-
-%Error: t/t_interface_modport_dir_bad.v:36: Attempt to drive input-only modport: 'data'
-: ... In instance t.source_i.source_i
-ctrl.data <= ~ctrl.data;
-^~~~
-%Error: Exiting due to 1 error(s)
-%Error: t/t_interface_modport_dir_bad.v:37: Attempt to drive input-only modport: 'valid'
-: ... In instance t.source_i.source_i
-ctrl.valid<= ~ctrl.valid;
-^~~~
-%Error: Exiting due to 1 error(s)
+%Error: t/t_interface_modport_dir_bad.v:52:25: Port connection 'ctrl' expected 'source' interface modport on pin connection but got 'sink' modport.
+                                             : ... In instance t.source_i
+   52 |    sourceMod source_i (.ctrl);
+      |                         ^~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_interface_modport_dir_bad.pl b/test_regress/t/t_interface_modport_dir_bad.pl
index f6a127931..27159da5b 100755
--- a/test_regress/t/t_interface_modport_dir_bad.pl
+++ b/test_regress/t/t_interface_modport_dir_bad.pl
@@ -8,8 +8,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug1622");
-
 scenarios(linter => 1);
 
 lint(
diff --git a/test_regress/t/t_interface_modport_export.out b/test_regress/t/t_interface_modport_export.out
new file mode 100644
index 000000000..27cf64600
--- /dev/null
+++ b/test_regress/t/t_interface_modport_export.out
@@ -0,0 +1,8 @@
+%Error-UNSUPPORTED: t/t_interface_modport_export.v:12:4: Unsupported: extern function
+   12 |    extern function myfunc (input logic val);
+      |    ^~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_interface_modport_export.v:51:31: Unsupported: Out of block function declaration
+   51 |    function automatic logic ie.myfunc (input logic val);
+      |                               ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_interface_modport_export.pl b/test_regress/t/t_interface_modport_export.pl
index 6d4d94235..be66c40e6 100755
--- a/test_regress/t/t_interface_modport_export.pl
+++ b/test_regress/t/t_interface_modport_export.pl
@@ -9,14 +9,15 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 scenarios(simulator => 1);
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug696");
 
 compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
     );
 
 execute(
     check_finished => 1,
-    );
+    ) if !$Self->{vlt_all};
 
 ok(1);
 1;
diff --git a/test_regress/t/t_interface_param2.out b/test_regress/t/t_interface_param2.out
new file mode 100644
index 000000000..916fc7f29
--- /dev/null
+++ b/test_regress/t/t_interface_param2.out
@@ -0,0 +1,8 @@
+%Error-UNSUPPORTED: t/t_interface_param2.v:38:12: Unsupported: generic interfaces
+   38 | module mem(interface a);
+      |            ^~~~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_interface_param2.v:49:12: Unsupported: generic interfaces
+   49 | module cpu(interface b);
+      |            ^~~~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_interface_param2.pl b/test_regress/t/t_interface_param2.pl
index 2319ed539..b5f2e4dd2 100755
--- a/test_regress/t/t_interface_param2.pl
+++ b/test_regress/t/t_interface_param2.pl
@@ -9,14 +9,16 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
 scenarios(simulator => 1);
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug1104");
 
 compile(
+    # Verilator unsupported, bug1104
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
     );
 
 execute(
     check_finished => 1,
-    );
+    ) if !$Self->{vlt_all};
 
 ok(1);
 1;
diff --git a/test_regress/t/t_interface_param_loop_bad.pl b/test_regress/t/t_interface_param_loop_bad.pl
index 538506b75..485e44130 100755
--- a/test_regress/t/t_interface_param_loop_bad.pl
+++ b/test_regress/t/t_interface_param_loop_bad.pl
@@ -8,13 +8,12 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug1626");
-
 scenarios(linter => 1);
 
 lint(
-    fails => 1,
-    expect_filename => $Self->{golden_filename},
+    # Should fail, Verilator unsupported, bug1626");
+    fails => !$Self->{vlt},
+    # expect_filename => $Self->{golden_filename},
     );
 
 ok(1);
diff --git a/test_regress/t/t_interface_parent_scope_bad.pl b/test_regress/t/t_interface_parent_scope_bad.pl
index 85d8dd9a3..2d88dbd1b 100755
--- a/test_regress/t/t_interface_parent_scope_bad.pl
+++ b/test_regress/t/t_interface_parent_scope_bad.pl
@@ -8,13 +8,12 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug1623");
-
 scenarios(linter => 1);
 
 lint(
-    fails => 1,
-    expect_filename => $Self->{golden_filename},
+    # Should fail, Verilator unsupported, bug1623
+    fails => !$Self->{vlt},
+    # expect_filename => $Self->{golden_filename},
     );
 
 ok(1);
diff --git a/test_regress/t/t_mem_bound_bad.pl b/test_regress/t/t_mem_bound_bad.pl
index 6f9cc9875..d86162476 100755
--- a/test_regress/t/t_mem_bound_bad.pl
+++ b/test_regress/t/t_mem_bound_bad.pl
@@ -8,13 +8,10 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug528");
-
 scenarios(linter => 1);
 
 lint(
-    fails => 1,
-    expect_filename => $Self->{golden_filename},
+    fails => !$Self->{vlt_all},  # Should fail, but doesn't
     );
 
 ok(1);
diff --git a/test_regress/t/t_param_width_loc_bad.out b/test_regress/t/t_param_width_loc_bad.out
index f29a54f07..3fed6e9b7 100644
--- a/test_regress/t/t_param_width_loc_bad.out
+++ b/test_regress/t/t_param_width_loc_bad.out
@@ -1,19 +1,7 @@
-%Warning-WIDTH: t/t_param_width_loc_bad.v:22: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
-                                              : ... In instance t.test_i
-    parameter logic param = 1'b0
-                    ^~~~~
+%Warning-WIDTH: t/t_param_width_loc_bad.v:25:21: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
+                                               : ... In instance t.test_i
+   25 |     parameter logic param = 1'b0
+      |                     ^~~~~
+                ... For warning description see https://verilator.org/warn/WIDTH?v=latest
                 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
 %Error: Exiting due to
-
-# I believe this warning message should be pointing to line 12 instead, i.e., wherever the wrongly sized parameter is given as an input rather than the parameter definition.
-# It would be more informative if it looked like this:
-
-%Warning-WIDTH: t/t_param_width_loc_bad.v:12: Operator VAR 'param' expects 1 bits on the Initial value, but Initial value's CONST '32'h0' generates 32 bits.
-      test #(.param(32'd0)) test_i;
-                    ^~~~
-                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
-%Error: Exiting due to
-
-
-
-
diff --git a/test_regress/t/t_param_width_loc_bad.pl b/test_regress/t/t_param_width_loc_bad.pl
index 1ce49be3f..27159da5b 100755
--- a/test_regress/t/t_param_width_loc_bad.pl
+++ b/test_regress/t/t_param_width_loc_bad.pl
@@ -8,8 +8,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-$Self->{vlt_all} and unsupported("Verilator unsupported, bug1624");
-
 scenarios(linter => 1);
 
 lint(
diff --git a/test_regress/t/t_param_width_loc_bad.v b/test_regress/t/t_param_width_loc_bad.v
index 5923bc497..3d61f5d93 100644
--- a/test_regress/t/t_param_width_loc_bad.v
+++ b/test_regress/t/t_param_width_loc_bad.v
@@ -11,6 +11,7 @@ module t (/*AUTOARG*/
 
    input clk;
 
+   // bug1624
    test #(.param(32'd0)) test_i;
 
    initial begin
diff --git a/test_regress/t/t_tri_array.out b/test_regress/t/t_tri_array.out
new file mode 100644
index 000000000..35c846494
--- /dev/null
+++ b/test_regress/t/t_tri_array.out
@@ -0,0 +1,21 @@
+%Error-UNSUPPORTED: t/t_tri_array.v:25:25: Unsupported LHS tristate construct: ARRAYSEL
+                                         : ... In instance t
+   25 |       Pad pad1 (.pad(pad[g]),
+      |                         ^
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error-UNSUPPORTED: t/t_tri_array.v:28:25: Unsupported LHS tristate construct: ARRAYSEL
+                                         : ... In instance t
+   28 |       Pad pad0 (.pad(pad[g]),
+      |                         ^
+%Error: t/t_tri_array.v:25:25: Select from non-array BASICDTYPE 'bit'
+                             : ... In instance t
+   25 |       Pad pad1 (.pad(pad[g]),
+      |                         ^
+%Error: t/t_tri_array.v:28:25: Select from non-array BASICDTYPE 'bit'
+                             : ... In instance t
+   28 |       Pad pad0 (.pad(pad[g]),
+      |                         ^
+%Error: Internal Error: t/t_tri_array.v:25:22: ../V3Dfg.h:529: DfgVertex is not of expected type, but instead has type 'VARPACKED'
+   25 |       Pad pad1 (.pad(pad[g]),
+      |                      ^~~
+                        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.
diff --git a/test_regress/t/t_tri_array.pl b/test_regress/t/t_tri_array.pl
index afd57d2de..be66c40e6 100755
--- a/test_regress/t/t_tri_array.pl
+++ b/test_regress/t/t_tri_array.pl
@@ -10,15 +10,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-# When fix, update ifdefs in t_sv_cpu files; search for t_tri_array
-$Self->{vlt_all} and unsupported("Verilator unsupported, tristate arrays");
-
 compile(
+    fails => $Self->{vlt_all},
+    expect_filename => $Self->{golden_filename},
     );
 
 execute(
     check_finished => 1,
-    );
+    ) if !$Self->{vlt_all};
 
 ok(1);
 1;

From 6297650fef588ab887d371e7c07c8b7e56680bd2 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 20 Nov 2022 07:45:51 -0500
Subject: [PATCH 069/156] Tests: Fix internal error stability

---
 test_regress/driver.pl         | 2 +-
 test_regress/t/t_tri_array.out | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 3507e013d..77ff135ed 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -2195,7 +2195,7 @@ sub files_identical {
                     && !/\+\+\+ \/tmp\//  # t_difftree.pl
             } @l1;
             @l1 = map {
-                s/(Internal Error: [^\n]+\.cpp):[0-9]+:/$1:#:/;
+                s/(Internal Error: [^\n]+\.(cpp|h)):[0-9]+:/$1:#:/;
                 s/^-V\{t[0-9]+,[0-9]+\}/-V{t#,#}/;  # --vlt vs --vltmt run differences
                 $_;
             } @l1;
diff --git a/test_regress/t/t_tri_array.out b/test_regress/t/t_tri_array.out
index 35c846494..4ca9228ce 100644
--- a/test_regress/t/t_tri_array.out
+++ b/test_regress/t/t_tri_array.out
@@ -15,7 +15,7 @@
                              : ... In instance t
    28 |       Pad pad0 (.pad(pad[g]),
       |                         ^
-%Error: Internal Error: t/t_tri_array.v:25:22: ../V3Dfg.h:529: DfgVertex is not of expected type, but instead has type 'VARPACKED'
+%Error: Internal Error: t/t_tri_array.v:25:22: ../V3Dfg.h:#: DfgVertex is not of expected type, but instead has type 'VARPACKED'
    25 |       Pad pad1 (.pad(pad[g]),
       |                      ^~~
                         ... See the manual at https://verilator.org/verilator_doc.html for more assistance.

From 278d53236845a8c861d5f8c85cbb7e4b11e5c7d6 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 20 Nov 2022 09:40:02 -0500
Subject: [PATCH 070/156] Tests: Add TEST_DUMPFILE define

---
 test_regress/driver.pl                  | 6 ++++++
 test_regress/t/t_gen_intdot2.v          | 2 +-
 test_regress/t/t_preproc_defines.out    | 1 +
 test_regress/t/t_timing_trace.v         | 2 +-
 test_regress/t/t_trace_binary.v         | 2 +-
 test_regress/t/t_trace_param_override.v | 2 +-
 test_regress/t/t_trace_timing1.v        | 2 +-
 7 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 77ff135ed..86bee331e 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -688,6 +688,7 @@ sub new {
         $self->{top_shell_filename} = "$self->{obj_dir}/$self->{VM_PREFIX}__top.v";
     }
     $self->{pli_filename} ||= $self->{name} . ".cpp";
+
     return $self;
 }
 
@@ -964,6 +965,11 @@ sub compile {
 
     compile_vlt_cmd(%param);
 
+    my $define_opt = defineOpt($self->{xsim});
+    if (join(' ', @{$self->{v_flags}}) !~ /TEST_DUMPFILE/) {
+        push @{$self->{v_flags}}, ($define_opt . "TEST_DUMPFILE=" . $self->trace_filename);
+    }
+
     if (!$param{make_top_shell}) {
         $param{top_shell_filename}
         = $self->{top_shell_filename} = "";
diff --git a/test_regress/t/t_gen_intdot2.v b/test_regress/t/t_gen_intdot2.v
index b496c4f05..785d9dd13 100644
--- a/test_regress/t/t_gen_intdot2.v
+++ b/test_regress/t/t_gen_intdot2.v
@@ -36,7 +36,7 @@ module t (/*AUTOARG*/
 //`define WAVES
 `ifdef WAVES
    initial begin
-      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+      $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
       $dumpvars(12, t);
    end
 `endif
diff --git a/test_regress/t/t_preproc_defines.out b/test_regress/t/t_preproc_defines.out
index e410899bc..58f7d85b4 100644
--- a/test_regress/t/t_preproc_defines.out
+++ b/test_regress/t/t_preproc_defines.out
@@ -16,6 +16,7 @@
 `define SV_COV_STOP 1
 `define SV_COV_TOGGLE 23
 `define SYSTEMVERILOG 1
+`define TEST_DUMPFILE obj_vlt/t_preproc_defines/simx.vcd
 `define TEST_OBJ_DIR obj_vlt/t_preproc_defines
 `define VERILATOR 1
 `define WITH_ARG(a) (a)(a)
diff --git a/test_regress/t/t_timing_trace.v b/test_regress/t/t_timing_trace.v
index 25782e267..af789dbeb 100644
--- a/test_regress/t/t_timing_trace.v
+++ b/test_regress/t/t_timing_trace.v
@@ -18,7 +18,7 @@ module t;
     logic d;
 
     initial begin
-        $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+        $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
         $dumpvars;
         forever clk = #CLK_HALF_PERIOD ~clk;
     end
diff --git a/test_regress/t/t_trace_binary.v b/test_regress/t/t_trace_binary.v
index 445c2b375..b25c30841 100644
--- a/test_regress/t/t_trace_binary.v
+++ b/test_regress/t/t_trace_binary.v
@@ -10,7 +10,7 @@ module t(/*AUTOARG*/);
    int sig;
    initial begin
       sig = 10;
-      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+      $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
       $dumpvars();
       #20;
       sig = 20;
diff --git a/test_regress/t/t_trace_param_override.v b/test_regress/t/t_trace_param_override.v
index 072e94e33..fb5798f0a 100644
--- a/test_regress/t/t_trace_param_override.v
+++ b/test_regress/t/t_trace_param_override.v
@@ -12,7 +12,7 @@ module t #(
            ) (/*AUTOARG*/);
 
    initial begin
-      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+      $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
       $dumpvars;
 
       $write("*-* All Finished *-*\n");
diff --git a/test_regress/t/t_trace_timing1.v b/test_regress/t/t_trace_timing1.v
index 26aef7ea9..57afab182 100644
--- a/test_regress/t/t_trace_timing1.v
+++ b/test_regress/t/t_trace_timing1.v
@@ -14,7 +14,7 @@ module t(/*AUTOARG*/);
    logic clk;
 
    initial begin
-      $dumpfile({`STRINGIFY(`TEST_OBJ_DIR),"/simx.vcd"});
+      $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
       $dumpvars;
    end
 

From 47253450a4159a7c9908c8153d5e009b3516adfa Mon Sep 17 00:00:00 2001
From: Jiacheng Qian <2000303206@cjlu.edu.cn>
Date: Sun, 20 Nov 2022 23:25:41 +0800
Subject: [PATCH 071/156] Fix to escape VERILATOR_ROOT file paths (#3764)
 (#3765)

---
 docs/CONTRIBUTORS   |  1 +
 src/V3EmitCMake.cpp | 41 ++++++++++++++++-------------------------
 src/V3Os.cpp        | 10 ++++++----
 src/V3String.cpp    | 13 +++++++++++++
 src/V3String.h      |  3 +++
 src/Verilator.cpp   |  2 +-
 6 files changed, 40 insertions(+), 30 deletions(-)

diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS
index 8ff9995ad..c9756852e 100644
--- a/docs/CONTRIBUTORS
+++ b/docs/CONTRIBUTORS
@@ -54,6 +54,7 @@ Jamie Iles
 Jan Van Winkel
 Jean Berniolles
 Jeremy Bennett
+Jiacheng Qian
 Jiuyang Liu
 John Coiner
 John Demme
diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp
index a2206af5e..902cd0526 100644
--- a/src/V3EmitCMake.cpp
+++ b/src/V3EmitCMake.cpp
@@ -71,15 +71,6 @@ class CMakeEmitter final {
         cmake_set_raw(of, name, raw_value, cache_type, docstring);
     }
 
-    // Swap all backslashes for forward slashes, because of Windows
-    static string deslash(const string& s) {
-        std::string res = s;
-        for (char& c : res) {
-            if (c == '\\') c = '/';
-        }
-        return res;
-    }
-
     static void emitOverallCMake() {
         const std::unique_ptr<std::ofstream> of{
             V3File::new_ofstream(v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + ".cmake")};
@@ -95,9 +86,9 @@ class CMakeEmitter final {
         *of << "# which becomes available after executing `find_package(verilator).\n";
 
         *of << "\n### Constants...\n";
-        cmake_set(*of, "PERL", deslash(V3Options::getenvPERL()), "FILEPATH",
+        cmake_set(*of, "PERL", V3Options::getenvPERL(), "FILEPATH",
                   "Perl executable (from $PERL)");
-        cmake_set(*of, "VERILATOR_ROOT", deslash(V3Options::getenvVERILATOR_ROOT()), "PATH",
+        cmake_set(*of, "VERILATOR_ROOT", V3Options::getenvVERILATOR_ROOT(), "PATH",
                   "Path to Verilator kit (from $VERILATOR_ROOT)");
 
         *of << "\n### Compiler flags...\n";
@@ -186,22 +177,22 @@ class CMakeEmitter final {
         }
 
         *of << "# Global classes, need linked once per executable\n";
-        cmake_set_raw(*of, name + "_GLOBAL", deslash(cmake_list(global)));
+        cmake_set_raw(*of, name + "_GLOBAL", cmake_list(global));
         *of << "# Generated module classes, non-fast-path, compile with low/medium optimization\n";
-        cmake_set_raw(*of, name + "_CLASSES_SLOW", deslash(cmake_list(classes_slow)));
+        cmake_set_raw(*of, name + "_CLASSES_SLOW", cmake_list(classes_slow));
         *of << "# Generated module classes, fast-path, compile with highest optimization\n";
-        cmake_set_raw(*of, name + "_CLASSES_FAST", deslash(cmake_list(classes_fast)));
+        cmake_set_raw(*of, name + "_CLASSES_FAST", cmake_list(classes_fast));
         *of << "# Generated support classes, non-fast-path, compile with "
                "low/medium optimization\n";
-        cmake_set_raw(*of, name + "_SUPPORT_SLOW", deslash(cmake_list(support_slow)));
+        cmake_set_raw(*of, name + "_SUPPORT_SLOW", cmake_list(support_slow));
         *of << "# Generated support classes, fast-path, compile with highest optimization\n";
-        cmake_set_raw(*of, name + "_SUPPORT_FAST", deslash(cmake_list(support_fast)));
+        cmake_set_raw(*of, name + "_SUPPORT_FAST", cmake_list(support_fast));
 
         *of << "# All dependencies\n";
-        cmake_set_raw(*of, name + "_DEPS", deslash(cmake_list(V3File::getAllDeps())));
+        cmake_set_raw(*of, name + "_DEPS", cmake_list(V3File::getAllDeps()));
 
         *of << "# User .cpp files (from .cpp's on Verilator command line)\n";
-        cmake_set_raw(*of, name + "_USER_CLASSES", deslash(cmake_list(v3Global.opt.cppFiles())));
+        cmake_set_raw(*of, name + "_USER_CLASSES", cmake_list(v3Global.opt.cppFiles()));
         if (const V3HierBlockPlan* const planp = v3Global.hierPlanp()) {
             *of << "# Verilate hierarchical blocks\n";
             // Sorted hierarchical blocks in order of leaf-first.
@@ -221,10 +212,10 @@ class CMakeEmitter final {
                 }
                 *of << "verilate(" << prefix << " PREFIX " << prefix << " TOP_MODULE "
                     << hblockp->modp()->name() << " DIRECTORY "
-                    << deslash(v3Global.opt.makeDir() + "/" + prefix) << " SOURCES ";
+                    << v3Global.opt.makeDir() + "/" + prefix << " SOURCES ";
                 for (const auto& childr : children) {
                     *of << " "
-                        << deslash(v3Global.opt.makeDir() + "/" + childr->hierWrapper(true));
+                        << v3Global.opt.makeDir() + "/" + childr->hierWrapper(true);
                 }
                 *of << " ";
                 const string vFile = hblockp->vFileIfNecessary();
@@ -232,7 +223,7 @@ class CMakeEmitter final {
                 const V3StringList& vFiles = v3Global.opt.vFiles();
                 for (const string& i : vFiles) *of << V3Os::filenameRealPath(i) << " ";
                 *of << " VERILATOR_ARGS ";
-                *of << "-f " << deslash(hblockp->commandArgsFileName(true))
+                *of << "-f " << hblockp->commandArgsFileName(true)
                     << " -CFLAGS -fPIC"  // hierarchical block will be static, but may be linked
                                          // with .so
                     << ")\n";
@@ -240,14 +231,14 @@ class CMakeEmitter final {
             *of << "\n# Verilate the top module that refers to lib-create wrappers of above\n";
             *of << "verilate(${TOP_TARGET_NAME} PREFIX " << v3Global.opt.prefix() << " TOP_MODULE "
                 << v3Global.rootp()->topModulep()->name() << " DIRECTORY "
-                << deslash(v3Global.opt.makeDir()) << " SOURCES ";
+                << v3Global.opt.makeDir() << " SOURCES ";
             for (const auto& itr : *planp) {
                 *of << " "
-                    << deslash(v3Global.opt.makeDir() + "/" + itr.second->hierWrapper(true));
+                    << v3Global.opt.makeDir() + "/" + itr.second->hierWrapper(true);
             }
-            *of << " " << deslash(cmake_list(v3Global.opt.vFiles()));
+            *of << " " << cmake_list(v3Global.opt.vFiles());
             *of << " VERILATOR_ARGS ";
-            *of << "-f " << deslash(planp->topCommandArgsFileName(true));
+            *of << "-f " << planp->topCommandArgsFileName(true);
             *of << ")\n";
         }
     }
diff --git a/src/V3Os.cpp b/src/V3Os.cpp
index 8088e120f..a0f936e4c 100644
--- a/src/V3Os.cpp
+++ b/src/V3Os.cpp
@@ -76,6 +76,7 @@ VL_DEFINE_DEBUG_FUNCTIONS;
 // Environment
 
 string V3Os::getenvStr(const string& envvar, const string& defaultValue) {
+    string ret = "";
 #if defined(_MSC_VER)
     // Note: MinGW does not offer _dupenv_s
     const char* envvalue = nullptr;
@@ -83,17 +84,18 @@ string V3Os::getenvStr(const string& envvar, const string& defaultValue) {
     if (envvalue != nullptr) {
         const std::string result{envvalue};
         free(envvalue);
-        return result;
+        ret = result;
     } else {
-        return defaultValue;
+        ret = defaultValue;
     }
 #else
     if (const char* const envvalue = getenv(envvar.c_str())) {
-        return envvalue;
+        ret = envvalue;
     } else {
-        return defaultValue;
+        ret = defaultValue;
     }
 #endif
+    return VString::escapeStringForPath(ret);
 }
 
 void V3Os::setenvStr(const string& envvar, const string& value, const string& why) {
diff --git a/src/V3String.cpp b/src/V3String.cpp
index 4b1f2f7f6..a688958e4 100644
--- a/src/V3String.cpp
+++ b/src/V3String.cpp
@@ -116,6 +116,19 @@ string VString::quoteStringLiteralForShell(const string& str) {
     return result;
 }
 
+string VString::escapeStringForPath(const string &str) {
+    if (str.find(R"(\\)") != string::npos) return str; // if it has been escaped already, don't do it again
+    if (str.find('/') != string::npos) return str; // can be replaced by `__MINGW32__` or `_WIN32`
+    string result;
+    const char space = ' '; // escape space like this `Program Files`
+    const char escape = '\\';
+    for (const char c: str) {
+        if (c == space || c == escape) result.push_back(escape);
+        result.push_back(c);
+    }
+    return result;
+}
+
 string VString::spaceUnprintable(const string& str) {
     string out;
     for (const char c : str) {
diff --git a/src/V3String.h b/src/V3String.h
index e004347f5..5cbd32402 100644
--- a/src/V3String.h
+++ b/src/V3String.h
@@ -100,6 +100,9 @@ public:
     static string quotePercent(const string& str) { return quoteAny(str, '%', '%'); }
     // Surround a raw string by double quote and escape if necessary
     // e.g. input abc's  becomes "\"abc\'s\""
+    static string escapeStringForPath(const string& str);
+    // Escape path in Windows
+    // e.g. input `C:\Program Files\My Program\My Program.exe` becomes `C:\\Program\ Files\\My\ Program\\My\ Program.exe`
     static string quoteStringLiteralForShell(const string& str);
     // Replace any unprintable with space
     // This includes removing tabs, so column tracking is correct
diff --git a/src/Verilator.cpp b/src/Verilator.cpp
index 536c523da..febe42703 100644
--- a/src/Verilator.cpp
+++ b/src/Verilator.cpp
@@ -737,7 +737,7 @@ int main(int argc, char** argv, char** /*env*/) {
     V3PreShell::boot();
 
     // Command option parsing
-    v3Global.opt.buildDepBin(argv[0]);
+    v3Global.opt.buildDepBin(VString::escapeStringForPath(argv[0]));
     const string argString = V3Options::argString(argc - 1, argv + 1);
     v3Global.opt.parseOpts(new FileLine{FileLine::commandLineFilename()}, argc - 1, argv + 1);
 

From a60e273c2991d865d6bffab06b4b271cc9b88c8a Mon Sep 17 00:00:00 2001
From: github action <action@example.com>
Date: Sun, 20 Nov 2022 15:26:23 +0000
Subject: [PATCH 072/156] Apply 'make format'

---
 src/V3EmitCMake.cpp |  6 ++----
 src/V3String.cpp    | 11 ++++++-----
 src/V3String.h      |  3 ++-
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp
index 902cd0526..06ef3be8f 100644
--- a/src/V3EmitCMake.cpp
+++ b/src/V3EmitCMake.cpp
@@ -214,8 +214,7 @@ class CMakeEmitter final {
                     << hblockp->modp()->name() << " DIRECTORY "
                     << v3Global.opt.makeDir() + "/" + prefix << " SOURCES ";
                 for (const auto& childr : children) {
-                    *of << " "
-                        << v3Global.opt.makeDir() + "/" + childr->hierWrapper(true);
+                    *of << " " << v3Global.opt.makeDir() + "/" + childr->hierWrapper(true);
                 }
                 *of << " ";
                 const string vFile = hblockp->vFileIfNecessary();
@@ -233,8 +232,7 @@ class CMakeEmitter final {
                 << v3Global.rootp()->topModulep()->name() << " DIRECTORY "
                 << v3Global.opt.makeDir() << " SOURCES ";
             for (const auto& itr : *planp) {
-                *of << " "
-                    << v3Global.opt.makeDir() + "/" + itr.second->hierWrapper(true);
+                *of << " " << v3Global.opt.makeDir() + "/" + itr.second->hierWrapper(true);
             }
             *of << " " << cmake_list(v3Global.opt.vFiles());
             *of << " VERILATOR_ARGS ";
diff --git a/src/V3String.cpp b/src/V3String.cpp
index a688958e4..58369df21 100644
--- a/src/V3String.cpp
+++ b/src/V3String.cpp
@@ -116,13 +116,14 @@ string VString::quoteStringLiteralForShell(const string& str) {
     return result;
 }
 
-string VString::escapeStringForPath(const string &str) {
-    if (str.find(R"(\\)") != string::npos) return str; // if it has been escaped already, don't do it again
-    if (str.find('/') != string::npos) return str; // can be replaced by `__MINGW32__` or `_WIN32`
+string VString::escapeStringForPath(const string& str) {
+    if (str.find(R"(\\)") != string::npos)
+        return str;  // if it has been escaped already, don't do it again
+    if (str.find('/') != string::npos) return str;  // can be replaced by `__MINGW32__` or `_WIN32`
     string result;
-    const char space = ' '; // escape space like this `Program Files`
+    const char space = ' ';  // escape space like this `Program Files`
     const char escape = '\\';
-    for (const char c: str) {
+    for (const char c : str) {
         if (c == space || c == escape) result.push_back(escape);
         result.push_back(c);
     }
diff --git a/src/V3String.h b/src/V3String.h
index 5cbd32402..bad040651 100644
--- a/src/V3String.h
+++ b/src/V3String.h
@@ -102,7 +102,8 @@ public:
     // e.g. input abc's  becomes "\"abc\'s\""
     static string escapeStringForPath(const string& str);
     // Escape path in Windows
-    // e.g. input `C:\Program Files\My Program\My Program.exe` becomes `C:\\Program\ Files\\My\ Program\\My\ Program.exe`
+    // e.g. input `C:\Program Files\My Program\My Program.exe` becomes
+    // `C:\\Program\ Files\\My\ Program\\My\ Program.exe`
     static string quoteStringLiteralForShell(const string& str);
     // Replace any unprintable with space
     // This includes removing tabs, so column tracking is correct

From 352d0b4582010ad1091af9370ddf296abe4f3c70 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 20 Nov 2022 13:11:01 -0500
Subject: [PATCH 073/156] Internals: Fix constructor style.

---
 include/verilated_profiler.cpp |   2 +-
 src/V3Config.cpp               |   2 +-
 src/V3Descope.cpp              |  16 +--
 src/V3EmitCBase.cpp            |   2 +-
 src/V3EmitCConstPool.cpp       |   2 +-
 src/V3EmitCHeaders.cpp         |   4 +-
 src/V3EmitCImp.cpp             |  12 +--
 src/V3EmitCModel.cpp           |   4 +-
 src/V3EmitCSyms.cpp            |  12 +--
 src/V3EmitMk.cpp               |   6 +-
 src/V3EmitV.cpp                |   2 +-
 src/V3File.cpp                 |  10 +-
 src/V3FileLine.cpp             |   4 +-
 src/V3Graph.cpp                |   4 +-
 src/V3GraphAcyc.cpp            |  10 +-
 src/V3GraphAlg.cpp             |  12 +--
 src/V3GraphTest.cpp            | 174 ++++++++++++++++-----------------
 src/V3Hash.h                   |   2 +-
 src/V3Hasher.cpp               |  10 +-
 src/V3HierBlock.cpp            |   2 +-
 src/V3Inline.cpp               |  24 ++---
 src/V3Life.cpp                 |  12 +--
 src/V3LifePost.cpp             |   2 +-
 src/V3LinkLevel.cpp            |  22 +++--
 src/V3LinkResolve.cpp          |  26 ++---
 src/V3Options.cpp              |  10 +-
 src/V3Order.cpp                |  10 +-
 src/V3Param.cpp                |  10 +-
 src/V3PreProc.cpp              |  12 +--
 src/V3Scope.cpp                |  10 +-
 src/V3Stats.h                  |   8 +-
 src/V3String.cpp               |   4 +-
 src/V3Unroll.cpp               |  10 +-
 src/VlcSource.h                |   4 +-
 34 files changed, 230 insertions(+), 226 deletions(-)

diff --git a/include/verilated_profiler.cpp b/include/verilated_profiler.cpp
index 85d76352b..7ea499c1b 100644
--- a/include/verilated_profiler.cpp
+++ b/include/verilated_profiler.cpp
@@ -173,7 +173,7 @@ void VlExecutionProfiler::dump(const char* filenamep, uint64_t tickEnd)
     // Copy /proc/cpuinfo into this output so verilator_gantt can be run on
     // a different machine
     {
-        const std::unique_ptr<std::ifstream> ifp{new std::ifstream("/proc/cpuinfo")};
+        const std::unique_ptr<std::ifstream> ifp{new std::ifstream{"/proc/cpuinfo"}};
         if (!ifp->fail()) {
             std::string line;
             while (std::getline(*ifp, line)) { fprintf(fp, "VLPROFPROC %s\n", line.c_str()); }
diff --git a/src/V3Config.cpp b/src/V3Config.cpp
index 9570c7245..1cefb40cf 100644
--- a/src/V3Config.cpp
+++ b/src/V3Config.cpp
@@ -291,7 +291,7 @@ public:
     }
     void addLineAttribute(int lineno, VPragmaType attr) { m_lineAttrs[lineno].set(attr); }
     void addIgnore(V3ErrorCode code, int lineno, bool on) {
-        m_ignLines.insert(V3ConfigIgnoresLine(code, lineno, on));
+        m_ignLines.insert(V3ConfigIgnoresLine{code, lineno, on});
         m_lastIgnore.it = m_ignLines.begin();
     }
     void addWaiver(V3ErrorCode code, const string& match) {
diff --git a/src/V3Descope.cpp b/src/V3Descope.cpp
index 07f985362..1cfccf607 100644
--- a/src/V3Descope.cpp
+++ b/src/V3Descope.cpp
@@ -144,9 +144,9 @@ private:
                     for (AstNode* stmtp = newfuncp->argsp(); stmtp; stmtp = stmtp->nextp()) {
                         if (AstVar* const portp = VN_CAST(stmtp, Var)) {
                             if (portp->isIO() && !portp->isFuncReturn()) {
-                                AstVarRef* const newp = new AstVarRef(
+                                AstVarRef* const newp = new AstVarRef{
                                     portp->fileline(), portp,
-                                    portp->isWritable() ? VAccess::WRITE : VAccess::READ);
+                                    portp->isWritable() ? VAccess::WRITE : VAccess::READ};
                                 argsp = AstNode::addNext(argsp, newp);
                             }
                         }
@@ -161,14 +161,14 @@ private:
                     AstNode* const returnp = new AstCReturn{funcp->fileline(), callp};
 
                     if (moreOfSame) {
-                        AstIf* const ifp = new AstIf(
+                        AstIf* const ifp = new AstIf{
                             funcp->fileline(),
-                            new AstEq(
-                                funcp->fileline(), new AstCExpr(funcp->fileline(), "this", 64),
-                                new AstCExpr(funcp->fileline(),
+                            new AstEq{
+                                funcp->fileline(), new AstCExpr{funcp->fileline(), "this", 64},
+                                new AstCExpr{funcp->fileline(),
                                              string("&(") + funcp->scopep()->nameVlSym() + ")",
-                                             64)),
-                            returnp);
+                                             64}},
+                            returnp};
                         newfuncp->addStmtsp(ifp);
                     } else {
                         newfuncp->addStmtsp(returnp);
diff --git a/src/V3EmitCBase.cpp b/src/V3EmitCBase.cpp
index c481f5bba..1a426e1bb 100644
--- a/src/V3EmitCBase.cpp
+++ b/src/V3EmitCBase.cpp
@@ -58,7 +58,7 @@ string EmitCBaseVisitor::funcNameProtect(const AstCFunc* nodep, const AstNodeMod
 }
 
 AstCFile* EmitCBaseVisitor::newCFile(const string& filename, bool slow, bool source, bool add) {
-    AstCFile* const cfilep = new AstCFile(v3Global.rootp()->fileline(), filename);
+    AstCFile* const cfilep = new AstCFile{v3Global.rootp()->fileline(), filename};
     cfilep->slow(slow);
     cfilep->source(source);
     if (add) v3Global.rootp()->addFilesp(cfilep);
diff --git a/src/V3EmitCConstPool.cpp b/src/V3EmitCConstPool.cpp
index 672d2cabb..00c3d9459 100644
--- a/src/V3EmitCConstPool.cpp
+++ b/src/V3EmitCConstPool.cpp
@@ -45,7 +45,7 @@ class EmitCConstPool final : public EmitCConstInit {
         const string fileName = v3Global.opt.makeDir() + "/" + topClassName() + "__ConstPool_"
                                 + cvtToStr(m_outFileCount) + ".cpp";
         newCFile(fileName, /* slow: */ true, /* source: */ true);
-        V3OutCFile* const ofp = new V3OutCFile(fileName);
+        V3OutCFile* const ofp = new V3OutCFile{fileName};
         ofp->putsHeader();
         ofp->puts("// DESCRIPTION: Verilator output: Constant pool\n");
         ofp->puts("//\n");
diff --git a/src/V3EmitCHeaders.cpp b/src/V3EmitCHeaders.cpp
index d9197cd0c..a20c622ab 100644
--- a/src/V3EmitCHeaders.cpp
+++ b/src/V3EmitCHeaders.cpp
@@ -301,7 +301,7 @@ class EmitCHeader final : public EmitCConstInit {
         // Open output file
         const string filename = v3Global.opt.makeDir() + "/" + prefixNameProtect(modp) + ".h";
         newCFile(filename, /* slow: */ false, /* source: */ false);
-        m_ofp = v3Global.opt.systemC() ? new V3OutScFile(filename) : new V3OutCFile(filename);
+        m_ofp = v3Global.opt.systemC() ? new V3OutScFile{filename} : new V3OutCFile{filename};
 
         ofp()->putsHeader();
         puts("// DESCRIPTION: Verilator output: Design internal header\n");
@@ -333,7 +333,7 @@ class EmitCHeader final : public EmitCConstInit {
     ~EmitCHeader() override = default;
 
 public:
-    static void main(const AstNodeModule* modp) { EmitCHeader emitCHeader(modp); }
+    static void main(const AstNodeModule* modp) { EmitCHeader emitCHeader{modp}; }
 };
 
 //######################################################################
diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp
index 05749c259..cf6fa6ccd 100644
--- a/src/V3EmitCImp.cpp
+++ b/src/V3EmitCImp.cpp
@@ -167,7 +167,7 @@ class EmitCImp final : EmitCFunc {
             const string filename = VL_DEV_NULL;
             m_cfilesr.push_back(
                 newCFile(filename, /* slow: */ m_slow, /* source: */ true, /* add */ false));
-            m_ofp = new V3OutCFile(filename);
+            m_ofp = new V3OutCFile{filename};
         } else {
             string filename = v3Global.opt.makeDir() + "/" + prefixNameProtect(m_fileModp);
             if (!subFileName.empty()) {
@@ -178,7 +178,7 @@ class EmitCImp final : EmitCFunc {
             filename += ".cpp";
             m_cfilesr.push_back(
                 newCFile(filename, /* slow: */ m_slow, /* source: */ true, /* add */ false));
-            m_ofp = v3Global.opt.systemC() ? new V3OutScFile(filename) : new V3OutCFile(filename);
+            m_ofp = v3Global.opt.systemC() ? new V3OutScFile{filename} : new V3OutCFile{filename};
         }
 
         ofp()->putsHeader();
@@ -593,9 +593,9 @@ class EmitCTrace final : EmitCFunc {
         m_cfilesr.push_back(cfilep);
 
         if (optSystemC()) {
-            m_ofp = new V3OutScFile(filename);
+            m_ofp = new V3OutScFile{filename};
         } else {
-            m_ofp = new V3OutCFile(filename);
+            m_ofp = new V3OutCFile{filename};
         }
         m_ofp->putsHeader();
         m_ofp->puts("// DESCR"
@@ -937,10 +937,10 @@ void V3EmitC::emitcFiles() {
          filep = VN_AS(filep->nextp(), NodeFile)) {
         AstCFile* const cfilep = VN_CAST(filep, CFile);
         if (cfilep && cfilep->tblockp()) {
-            V3OutCFile of(cfilep->name());
+            V3OutCFile of{cfilep->name()};
             of.puts("// DESCR"
                     "IPTION: Verilator generated C++\n");
-            const EmitCFunc visitor(cfilep->tblockp(), &of, true);
+            const EmitCFunc visitor{cfilep->tblockp(), &of, true};
         }
     }
 }
diff --git a/src/V3EmitCModel.cpp b/src/V3EmitCModel.cpp
index 517d2618c..32cceae3a 100644
--- a/src/V3EmitCModel.cpp
+++ b/src/V3EmitCModel.cpp
@@ -59,7 +59,7 @@ class EmitCModel final : public EmitCFunc {
 
         const string filename = v3Global.opt.makeDir() + "/" + topClassName() + ".h";
         newCFile(filename, /* slow: */ false, /* source: */ false);
-        m_ofp = v3Global.opt.systemC() ? new V3OutScFile(filename) : new V3OutCFile(filename);
+        m_ofp = v3Global.opt.systemC() ? new V3OutScFile{filename} : new V3OutCFile{filename};
 
         ofp()->putsHeader();
         puts("// DESCRIPTION: Verilator output: Primary model header\n");
@@ -598,7 +598,7 @@ class EmitCModel final : public EmitCFunc {
 
         const string filename = v3Global.opt.makeDir() + "/" + topClassName() + ".cpp";
         newCFile(filename, /* slow: */ false, /* source: */ true);
-        m_ofp = v3Global.opt.systemC() ? new V3OutScFile(filename) : new V3OutCFile(filename);
+        m_ofp = v3Global.opt.systemC() ? new V3OutScFile{filename} : new V3OutCFile{filename};
 
         ofp()->putsHeader();
         puts("// DESCRIPTION: Verilator output: "
diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp
index 756b29096..f19410b84 100644
--- a/src/V3EmitCSyms.cpp
+++ b/src/V3EmitCSyms.cpp
@@ -378,9 +378,9 @@ void EmitCSyms::emitSymHdr() {
     newCFile(filename, true /*slow*/, false /*source*/);
 
     if (v3Global.opt.systemC()) {
-        m_ofp = new V3OutScFile(filename);
+        m_ofp = new V3OutScFile{filename};
     } else {
-        m_ofp = new V3OutCFile(filename);
+        m_ofp = new V3OutCFile{filename};
     }
 
     ofp()->putsHeader();
@@ -569,9 +569,9 @@ void EmitCSyms::checkSplit(bool usesVfinal) {
     closeSplit();
 
     if (v3Global.opt.systemC()) {
-        m_ofp = new V3OutScFile(filename);
+        m_ofp = new V3OutScFile{filename};
     } else {
-        m_ofp = new V3OutCFile(filename);
+        m_ofp = new V3OutCFile{filename};
     }
 
     m_ofpBase->puts(symClassName() + "_" + cvtToStr(m_funcNum) + "(");
@@ -650,9 +650,9 @@ void EmitCSyms::emitSymImp() {
     cfilep->support(true);
 
     if (v3Global.opt.systemC()) {
-        m_ofp = new V3OutScFile(filename);
+        m_ofp = new V3OutScFile{filename};
     } else {
-        m_ofp = new V3OutCFile(filename);
+        m_ofp = new V3OutCFile{filename};
     }
 
     m_ofpBase = m_ofp;
diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp
index f51f0fe34..7c1bf0094 100644
--- a/src/V3EmitMk.cpp
+++ b/src/V3EmitMk.cpp
@@ -39,7 +39,7 @@ public:
 
     void emitClassMake() {
         // Generate the makefile
-        V3OutMkFile of(v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + "_classes.mk");
+        V3OutMkFile of{v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + "_classes.mk"};
         of.putsHeader();
         of.puts("# DESCR"
                 "IPTION: Verilator output: Make include file with class lists\n");
@@ -135,7 +135,7 @@ public:
 
     void emitOverallMake() {
         // Generate the makefile
-        V3OutMkFile of(v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + ".mk");
+        V3OutMkFile of{v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + ".mk"};
         of.putsHeader();
         of.puts("# DESCR"
                 "IPTION: Verilator output: "
@@ -398,7 +398,7 @@ public:
     explicit EmitMkHierVerilation(const V3HierBlockPlan* planp)
         : m_planp{planp}
         , m_makefile{v3Global.opt.makeDir() + "/" + v3Global.opt.prefix() + "_hier.mk"} {
-        V3OutMkFile of(m_makefile);
+        V3OutMkFile of{m_makefile};
         emit(of);
     }
 };
diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp
index 02f658334..bf56a4b11 100644
--- a/src/V3EmitV.cpp
+++ b/src/V3EmitV.cpp
@@ -880,7 +880,7 @@ void V3EmitV::emitvFiles() {
          filep = VN_AS(filep->nextp(), NodeFile)) {
         AstVFile* const vfilep = VN_CAST(filep, VFile);
         if (vfilep && vfilep->tblockp()) {
-            V3OutVFile of(vfilep->name());
+            V3OutVFile of{vfilep->name()};
             of.puts("// DESCR"
                     "IPTION: Verilator generated Verilog\n");
             { EmitVFileVisitor{vfilep->tblockp(), &of, true, false}; }
diff --git a/src/V3File.cpp b/src/V3File.cpp
index a8e23182a..eef75c73a 100644
--- a/src/V3File.cpp
+++ b/src/V3File.cpp
@@ -125,7 +125,7 @@ public:
         if (m_filenameSet.find(filename) == m_filenameSet.end()) {
             // cppcheck-suppress stlFindInsert  // cppcheck 1.90 bug
             m_filenameSet.insert(filename);
-            DependFile df(filename, false);
+            DependFile df{filename, false};
             df.loadStats();  // Get size now, in case changes during the run
             m_filenameList.insert(df);
         }
@@ -134,7 +134,7 @@ public:
         if (m_filenameSet.find(filename) == m_filenameSet.end()) {
             // cppcheck-suppress stlFindInsert  // cppcheck 1.90 bug
             m_filenameSet.insert(filename);
-            m_filenameList.insert(DependFile(filename, true));
+            m_filenameList.insert(DependFile{filename, true});
         }
     }
     void writeDepend(const string& filename);
@@ -603,7 +603,7 @@ protected:
 // VInFilter
 // Just dispatch to the implementation
 
-VInFilter::VInFilter(const string& command) { m_impp = new VInFilterImp(command); }
+VInFilter::VInFilter(const string& command) { m_impp = new VInFilterImp{command}; }
 VInFilter::~VInFilter() {
     if (m_impp) VL_DO_CLEAR(delete m_impp, m_impp = nullptr);
 }
@@ -1002,7 +1002,7 @@ public:
                 // missing a protect()
                 out = "PS" + old;
             } else {
-                VHashSha256 digest(v3Global.opt.protectKeyDefaulted());
+                VHashSha256 digest{v3Global.opt.protectKeyDefaulted()};
                 digest.insert(old);
                 // Add "PS" prefix (Protect Symbols) as cannot start symbol with number
                 out = "PS" + digest.digestSymbol();
@@ -1044,7 +1044,7 @@ public:
         return out;
     }
     void writeMapFile(const string& filename) const {
-        V3OutXmlFile of(filename);
+        V3OutXmlFile of{filename};
         of.putsHeader();
         of.puts("<!-- DESCR"
                 "IPTION: Verilator output: XML representation of netlist -->\n");
diff --git a/src/V3FileLine.cpp b/src/V3FileLine.cpp
index 3704d4631..8a83b110e 100644
--- a/src/V3FileLine.cpp
+++ b/src/V3FileLine.cpp
@@ -279,7 +279,7 @@ FileLine* FileLine::copyOrSameFileLine() {
     if (lastNewp && *lastNewp == *this) {  // Compares lineno, filename, etc
         return lastNewp;
     }
-    FileLine* const newp = new FileLine(this);
+    FileLine* const newp = new FileLine{this};
     lastNewp = newp;
     return newp;
 }
@@ -340,7 +340,7 @@ bool FileLine::warnOff(const string& msg, bool flag) {
         warnOff(V3ErrorCode::UNUSEDSIGNAL, flag);
         return true;
     }
-    const V3ErrorCode code(cmsg);
+    const V3ErrorCode code{cmsg};
     if (code < V3ErrorCode::EC_FIRST_WARN) {
         return false;
     } else {
diff --git a/src/V3Graph.cpp b/src/V3Graph.cpp
index 4218394fa..ca3a4ed91 100644
--- a/src/V3Graph.cpp
+++ b/src/V3Graph.cpp
@@ -80,9 +80,9 @@ void V3GraphVertex::rerouteEdges(V3Graph* graphp) {
     // Make new edges for each from/to pair
     for (V3GraphEdge* iedgep = inBeginp(); iedgep; iedgep = iedgep->inNextp()) {
         for (V3GraphEdge* oedgep = outBeginp(); oedgep; oedgep = oedgep->outNextp()) {
-            new V3GraphEdge(graphp, iedgep->fromp(), oedgep->top(),
+            new V3GraphEdge{graphp, iedgep->fromp(), oedgep->top(),
                             std::min(iedgep->weight(), oedgep->weight()),
-                            iedgep->cutable() && oedgep->cutable());
+                            iedgep->cutable() && oedgep->cutable()};
         }
     }
     // Remove old edges
diff --git a/src/V3GraphAcyc.cpp b/src/V3GraphAcyc.cpp
index e2be3e019..5a6b4bff2 100644
--- a/src/V3GraphAcyc.cpp
+++ b/src/V3GraphAcyc.cpp
@@ -126,8 +126,8 @@ private:
     }
     V3GraphEdge* edgeFromEdge(V3GraphEdge* oldedgep, V3GraphVertex* fromp, V3GraphVertex* top) {
         // Make new breakGraph edge, with old edge as a template
-        GraphAcycEdge* const newEdgep = new GraphAcycEdge(&m_breakGraph, fromp, top,
-                                                          oldedgep->weight(), oldedgep->cutable());
+        GraphAcycEdge* const newEdgep = new GraphAcycEdge{&m_breakGraph, fromp, top,
+                                                          oldedgep->weight(), oldedgep->cutable()};
         newEdgep->userp(oldedgep->userp());  // Keep pointer to OrigEdgeList
         return newEdgep;
     }
@@ -203,7 +203,7 @@ void GraphAcyc::buildGraph(V3Graph* origGraphp) {
     for (V3GraphVertex* overtexp = origGraphp->verticesBeginp(); overtexp;
          overtexp = overtexp->verticesNextp()) {
         if (overtexp->color()) {
-            GraphAcycVertex* const avertexp = new GraphAcycVertex(&m_breakGraph, overtexp);
+            GraphAcycVertex* const avertexp = new GraphAcycVertex{&m_breakGraph, overtexp};
             overtexp->userp(avertexp);  // Stash so can look up later
         }
     }
@@ -228,8 +228,8 @@ void GraphAcyc::buildGraphIterate(V3GraphVertex* overtexp, GraphAcycVertex* aver
                     = static_cast<GraphAcycVertex*>(toVertexp->userp());
                 // Replicate the old edge into the new graph
                 // There may be multiple edges between same pairs of vertices
-                V3GraphEdge* breakEdgep = new GraphAcycEdge(&m_breakGraph, avertexp, toAVertexp,
-                                                            edgep->weight(), edgep->cutable());
+                V3GraphEdge* breakEdgep = new GraphAcycEdge{&m_breakGraph, avertexp, toAVertexp,
+                                                            edgep->weight(), edgep->cutable()};
                 addOrigEdgep(breakEdgep, edgep);  // So can find original edge
             }
         }
diff --git a/src/V3GraphAlg.cpp b/src/V3GraphAlg.cpp
index b74de1351..c8af95e3f 100644
--- a/src/V3GraphAlg.cpp
+++ b/src/V3GraphAlg.cpp
@@ -106,7 +106,7 @@ public:
     explicit GraphAlgRemoveTransitiveEdges(V3Graph* graphp)
         : GraphAlg<>(graphp, nullptr) {}
     void go() {
-        GraphPathChecker checker(m_graphp);
+        GraphPathChecker checker{m_graphp};
         for (V3GraphVertex* vxp = m_graphp->verticesBeginp(); vxp; vxp = vxp->verticesNextp()) {
             V3GraphEdge* deletep = nullptr;
             for (V3GraphEdge* edgep = vxp->outBeginp(); edgep; edgep = edgep->outNextp()) {
@@ -125,7 +125,7 @@ private:
     VL_UNCOPYABLE(GraphAlgRemoveTransitiveEdges);
 };
 
-void V3Graph::removeTransitiveEdges() { GraphAlgRemoveTransitiveEdges(this).go(); }
+void V3Graph::removeTransitiveEdges() { GraphAlgRemoveTransitiveEdges{this}.go(); }
 
 //######################################################################
 //######################################################################
@@ -166,7 +166,7 @@ public:
     ~GraphAlgWeakly() = default;
 };
 
-void V3Graph::weaklyConnected(V3EdgeFuncP edgeFuncp) { GraphAlgWeakly(this, edgeFuncp); }
+void V3Graph::weaklyConnected(V3EdgeFuncP edgeFuncp) { GraphAlgWeakly{this, edgeFuncp}; }
 
 //######################################################################
 //######################################################################
@@ -257,7 +257,7 @@ public:
     ~GraphAlgStrongly() = default;
 };
 
-void V3Graph::stronglyConnected(V3EdgeFuncP edgeFuncp) { GraphAlgStrongly(this, edgeFuncp); }
+void V3Graph::stronglyConnected(V3EdgeFuncP edgeFuncp) { GraphAlgStrongly{this, edgeFuncp}; }
 
 //######################################################################
 //######################################################################
@@ -310,9 +310,9 @@ public:
     ~GraphAlgRank() = default;
 };
 
-void V3Graph::rank() { GraphAlgRank(this, &V3GraphEdge::followAlwaysTrue); }
+void V3Graph::rank() { GraphAlgRank{this, &V3GraphEdge::followAlwaysTrue}; }
 
-void V3Graph::rank(V3EdgeFuncP edgeFuncp) { GraphAlgRank(this, edgeFuncp); }
+void V3Graph::rank(V3EdgeFuncP edgeFuncp) { GraphAlgRank{this, edgeFuncp}; }
 
 //######################################################################
 //######################################################################
diff --git a/src/V3GraphTest.cpp b/src/V3GraphTest.cpp
index 3fdb8dfe7..540a5d85a 100644
--- a/src/V3GraphTest.cpp
+++ b/src/V3GraphTest.cpp
@@ -83,24 +83,24 @@ public:
         V3Graph* gp = &m_graph;
         // Verify we break edges at a good point
         // A simple alg would make 3 breaks, below only requires b->i to break
-        V3GraphTestVertex* i = new V3GraphTestVarVertex(gp, "*INPUTS*");
-        V3GraphTestVertex* a = new V3GraphTestVarVertex(gp, "a");
-        V3GraphTestVertex* b = new V3GraphTestVarVertex(gp, "b");
-        V3GraphTestVertex* g1 = new V3GraphTestVarVertex(gp, "g1");
-        V3GraphTestVertex* g2 = new V3GraphTestVarVertex(gp, "g2");
-        V3GraphTestVertex* g3 = new V3GraphTestVarVertex(gp, "g3");
-        V3GraphTestVertex* q = new V3GraphTestVarVertex(gp, "q");
-        new V3GraphEdge(gp, i, a, 2, true);
-        new V3GraphEdge(gp, a, b, 2, true);
-        new V3GraphEdge(gp, b, g1, 2, true);
-        new V3GraphEdge(gp, b, g2, 2, true);
-        new V3GraphEdge(gp, b, g3, 2, true);
-        new V3GraphEdge(gp, g1, a, 2, true);
-        new V3GraphEdge(gp, g3, g2, 2, true);
-        new V3GraphEdge(gp, g2, g3, 2, true);
-        new V3GraphEdge(gp, g1, q, 2, true);
-        new V3GraphEdge(gp, g2, q, 2, true);
-        new V3GraphEdge(gp, g3, q, 2, true);
+        V3GraphTestVertex* i = new V3GraphTestVarVertex{gp, "*INPUTS*"};
+        V3GraphTestVertex* a = new V3GraphTestVarVertex{gp, "a"};
+        V3GraphTestVertex* b = new V3GraphTestVarVertex{gp, "b"};
+        V3GraphTestVertex* g1 = new V3GraphTestVarVertex{gp, "g1"};
+        V3GraphTestVertex* g2 = new V3GraphTestVarVertex{gp, "g2"};
+        V3GraphTestVertex* g3 = new V3GraphTestVarVertex{gp, "g3"};
+        V3GraphTestVertex* q = new V3GraphTestVarVertex{gp, "q"};
+        new V3GraphEdge{gp, i, a, 2, true};
+        new V3GraphEdge{gp, a, b, 2, true};
+        new V3GraphEdge{gp, b, g1, 2, true};
+        new V3GraphEdge{gp, b, g2, 2, true};
+        new V3GraphEdge{gp, b, g3, 2, true};
+        new V3GraphEdge{gp, g1, a, 2, true};
+        new V3GraphEdge{gp, g3, g2, 2, true};
+        new V3GraphEdge{gp, g2, g3, 2, true};
+        new V3GraphEdge{gp, g1, q, 2, true};
+        new V3GraphEdge{gp, g2, q, 2, true};
+        new V3GraphEdge{gp, g3, q, 2, true};
 
         gp->stronglyConnected(&V3GraphEdge::followAlwaysTrue);
         dumpSelf();
@@ -121,20 +121,20 @@ public:
         V3Graph* gp = &m_graph;
         // Verify we break edges at a good point
         // A simple alg would make 3 breaks, below only requires b->i to break
-        V3GraphTestVertex* i = new V3GraphTestVarVertex(gp, "*INPUTS*");
-        V3GraphTestVertex* a = new V3GraphTestVarVertex(gp, "a");
-        V3GraphTestVertex* b = new V3GraphTestVarVertex(gp, "b");
-        V3GraphTestVertex* g1 = new V3GraphTestVarVertex(gp, "g1");
-        V3GraphTestVertex* g2 = new V3GraphTestVarVertex(gp, "g2");
-        V3GraphTestVertex* g3 = new V3GraphTestVarVertex(gp, "g3");
-        new V3GraphEdge(gp, i, a, 2, true);
-        new V3GraphEdge(gp, a, b, 2, true);
-        new V3GraphEdge(gp, b, g1, 2, true);
-        new V3GraphEdge(gp, b, g2, 2, true);
-        new V3GraphEdge(gp, b, g3, 2, true);
-        new V3GraphEdge(gp, g1, a, 2, true);
-        new V3GraphEdge(gp, g2, a, 2, true);
-        new V3GraphEdge(gp, g3, a, 2, true);
+        V3GraphTestVertex* i = new V3GraphTestVarVertex{gp, "*INPUTS*"};
+        V3GraphTestVertex* a = new V3GraphTestVarVertex{gp, "a"};
+        V3GraphTestVertex* b = new V3GraphTestVarVertex{gp, "b"};
+        V3GraphTestVertex* g1 = new V3GraphTestVarVertex{gp, "g1"};
+        V3GraphTestVertex* g2 = new V3GraphTestVarVertex{gp, "g2"};
+        V3GraphTestVertex* g3 = new V3GraphTestVarVertex{gp, "g3"};
+        new V3GraphEdge{gp, i, a, 2, true};
+        new V3GraphEdge{gp, a, b, 2, true};
+        new V3GraphEdge{gp, b, g1, 2, true};
+        new V3GraphEdge{gp, b, g2, 2, true};
+        new V3GraphEdge{gp, b, g3, 2, true};
+        new V3GraphEdge{gp, g1, a, 2, true};
+        new V3GraphEdge{gp, g2, a, 2, true};
+        new V3GraphEdge{gp, g3, a, 2, true};
 
         gp->acyclic(&V3GraphEdge::followAlwaysTrue);
         gp->order();
@@ -148,20 +148,20 @@ public:
     void runTest() override {
         V3Graph* gp = &m_graph;
 
-        V3GraphTestVertex* clk = new V3GraphTestVarVertex(gp, "$clk");
+        V3GraphTestVertex* clk = new V3GraphTestVarVertex{gp, "$clk"};
 
-        V3GraphTestVertex* a = new V3GraphTestVarVertex(gp, "$a");
-        V3GraphTestVertex* a_dly = new V3GraphTestVarVertex(gp, "$a_dly");
-        V3GraphTestVertex* a_dlyblk = new V3GraphTestVarVertex(gp, "$a_dlyblk");
-        V3GraphTestVertex* b = new V3GraphTestVarVertex(gp, "$b");
-        V3GraphTestVertex* b_dly = new V3GraphTestVarVertex(gp, "$b_dly");
-        V3GraphTestVertex* b_dlyblk = new V3GraphTestVarVertex(gp, "$b_dlyblk");
-        V3GraphTestVertex* c = new V3GraphTestVarVertex(gp, "$c");
-        V3GraphTestVertex* i = new V3GraphTestVarVertex(gp, "$i");
+        V3GraphTestVertex* a = new V3GraphTestVarVertex{gp, "$a"};
+        V3GraphTestVertex* a_dly = new V3GraphTestVarVertex{gp, "$a_dly"};
+        V3GraphTestVertex* a_dlyblk = new V3GraphTestVarVertex{gp, "$a_dlyblk"};
+        V3GraphTestVertex* b = new V3GraphTestVarVertex{gp, "$b"};
+        V3GraphTestVertex* b_dly = new V3GraphTestVarVertex{gp, "$b_dly"};
+        V3GraphTestVertex* b_dlyblk = new V3GraphTestVarVertex{gp, "$b_dlyblk"};
+        V3GraphTestVertex* c = new V3GraphTestVarVertex{gp, "$c"};
+        V3GraphTestVertex* i = new V3GraphTestVarVertex{gp, "$i"};
 
-        V3GraphTestVertex* ap = new V3GraphTestVarVertex(gp, "$a_pre");
-        V3GraphTestVertex* bp = new V3GraphTestVarVertex(gp, "$b_pre");
-        V3GraphTestVertex* cp = new V3GraphTestVarVertex(gp, "$c_pre");
+        V3GraphTestVertex* ap = new V3GraphTestVarVertex{gp, "$a_pre"};
+        V3GraphTestVertex* bp = new V3GraphTestVarVertex{gp, "$b_pre"};
+        V3GraphTestVertex* cp = new V3GraphTestVarVertex{gp, "$c_pre"};
 
         V3GraphTestVertex* n;
 
@@ -176,68 +176,68 @@ public:
         // Desired order between different _DLY blocks so we can elim temporaries
         //   implemented by cutable "pre" signal dependencies
 
-        n = new V3GraphTestVertex(gp, "*INPUTS*");
+        n = new V3GraphTestVertex{gp, "*INPUTS*"};
         {
-            new V3GraphEdge(gp, n, clk, 2);
-            new V3GraphEdge(gp, n, i, 2);
+            new V3GraphEdge{gp, n, clk, 2};
+            new V3GraphEdge{gp, n, i, 2};
         }
 
-        V3GraphTestVertex* posedge = n = new V3GraphTestVertex(gp, "*posedge clk*");
-        { new V3GraphEdge(gp, clk, n, 2); }
+        V3GraphTestVertex* posedge = n = new V3GraphTestVertex{gp, "*posedge clk*"};
+        { new V3GraphEdge{gp, clk, n, 2}; }
 
         // AssignPre's     VarRefs on LHS:  generate special BLK
         //    normal:      VarRefs on LHS:  generate normal
         //    underSBlock: VarRefs on RHS:  consume 'pre' (required to save cutable tests)
-        n = new V3GraphTestVertex(gp, "a_dly<PRE=a");
+        n = new V3GraphTestVertex{gp, "a_dly<PRE=a"};
         {
-            new V3GraphEdge(gp, n, a_dlyblk, 2);  // Block ordering
-            new V3GraphEdge(gp, n, a_dly, 2);
-            new V3GraphEdge(gp, ap, n, 2, true);  // DESIRED delayed ordering (inp is required)
-            new V3GraphEdge(gp, posedge, n, 2);
+            new V3GraphEdge{gp, n, a_dlyblk, 2};  // Block ordering
+            new V3GraphEdge{gp, n, a_dly, 2};
+            new V3GraphEdge{gp, ap, n, 2, true};  // DESIRED delayed ordering (inp is required)
+            new V3GraphEdge{gp, posedge, n, 2};
         }
-        n = new V3GraphTestVertex(gp, "b_dly<PRE=b");
+        n = new V3GraphTestVertex{gp, "b_dly<PRE=b"};
         {
-            new V3GraphEdge(gp, n, b_dlyblk, 2);  // Block ordering
-            new V3GraphEdge(gp, n, b_dly, 2);
-            new V3GraphEdge(gp, bp, n, 2, true);  // DESIRED delayed ordering
-            new V3GraphEdge(gp, posedge, n, 2);
+            new V3GraphEdge{gp, n, b_dlyblk, 2};  // Block ordering
+            new V3GraphEdge{gp, n, b_dly, 2};
+            new V3GraphEdge{gp, bp, n, 2, true};  // DESIRED delayed ordering
+            new V3GraphEdge{gp, posedge, n, 2};
         }
 
         // AssignDly's     VarRefs on LHS:  consume special BLK
         //    normal:      VarRefs on LHS:  generate normal
         //    underSBlock: VarRefs on RHS:  generate 'pre' signals (cutable)
         //    SenItems:    consume CLOCK dependency
-        n = new V3GraphTestVertex(gp, "a_dly<=b|c");
+        n = new V3GraphTestVertex{gp, "a_dly<=b|c"};
         {
-            new V3GraphEdge(gp, a_dlyblk, n, 2);  // Block ordering in
-            new V3GraphEdge(gp, n, a_dly, 2);
+            new V3GraphEdge{gp, a_dlyblk, n, 2};  // Block ordering in
+            new V3GraphEdge{gp, n, a_dly, 2};
             // Note we don't include ap as we're generating a_dly
-            new V3GraphEdge(gp, n, bp, 2);  // DESIRED delayed usage
-            new V3GraphEdge(gp, n, cp, 2);  // DESIRED delayed usage
-            new V3GraphEdge(gp, posedge, n, 2);
+            new V3GraphEdge{gp, n, bp, 2};  // DESIRED delayed usage
+            new V3GraphEdge{gp, n, cp, 2};  // DESIRED delayed usage
+            new V3GraphEdge{gp, posedge, n, 2};
         }
-        n = new V3GraphTestVertex(gp, "b_dly<=a");
+        n = new V3GraphTestVertex{gp, "b_dly<=a"};
         {
-            new V3GraphEdge(gp, b_dlyblk, n, 2);  // Block ordering in
-            new V3GraphEdge(gp, n, b_dly, 2);
-            new V3GraphEdge(gp, n, ap, 2);  // DESIRED delayed usage
-            new V3GraphEdge(gp, posedge, n, 2);
+            new V3GraphEdge{gp, b_dlyblk, n, 2};  // Block ordering in
+            new V3GraphEdge{gp, n, b_dly, 2};
+            new V3GraphEdge{gp, n, ap, 2};  // DESIRED delayed usage
+            new V3GraphEdge{gp, posedge, n, 2};
         }
 
         // AssignPost's
         //    normal:      VarRefs on LHS:  generate normal
         //    underSBlock: VarRefs on RHS:  consume normal
-        n = new V3GraphTestVertex(gp, "a=POST=a_dly");
+        n = new V3GraphTestVertex{gp, "a=POST=a_dly"};
         {
-            new V3GraphEdge(gp, n, a, 3);
-            new V3GraphEdge(gp, a_dly, n, 3);
-            new V3GraphEdge(gp, posedge, n, 2);
+            new V3GraphEdge{gp, n, a, 3};
+            new V3GraphEdge{gp, a_dly, n, 3};
+            new V3GraphEdge{gp, posedge, n, 2};
         }
-        n = new V3GraphTestVertex(gp, "b=POST=b_dly");
+        n = new V3GraphTestVertex{gp, "b=POST=b_dly"};
         {
-            new V3GraphEdge(gp, n, b, 3);
-            new V3GraphEdge(gp, b_dly, n, 3);
-            new V3GraphEdge(gp, posedge, n, 2);
+            new V3GraphEdge{gp, n, b, 3};
+            new V3GraphEdge{gp, b_dly, n, 3};
+            new V3GraphEdge{gp, posedge, n, 2};
         }
 
         // COMBO
@@ -245,11 +245,11 @@ public:
         // Outbound are cutable, as we may need to evaluate multiple times
 
         {
-            n = new V3GraphTestVertex(gp, "c=a|b|i");
-            new V3GraphEdge(gp, n, c, 1, true);
-            new V3GraphEdge(gp, a, n, 1, false);
-            new V3GraphEdge(gp, b, n, 1, false);
-            new V3GraphEdge(gp, i, n, 1, false);
+            n = new V3GraphTestVertex{gp, "c=a|b|i"};
+            new V3GraphEdge{gp, n, c, 1, true};
+            new V3GraphEdge{gp, a, n, 1, false};
+            new V3GraphEdge{gp, b, n, 1, false};
+            new V3GraphEdge{gp, i, n, 1, false};
         }
 
         gp->acyclic(&V3GraphEdge::followAlwaysTrue);
@@ -294,9 +294,9 @@ void V3Graph::selfTest() {
     // Execute all of the tests
     UINFO(2, __FUNCTION__ << ": " << endl);
     // clang-format off
-    { V3GraphTestStrong test; test.run(); }
-    { V3GraphTestAcyc test; test.run(); }
-    { V3GraphTestVars test; test.run(); }
-    { V3GraphTestImport test; test.run(); }
+    { V3GraphTestStrong{}.run(); }
+    { V3GraphTestAcyc{}.run(); }
+    { V3GraphTestVars{}.run(); }
+    { V3GraphTestImport{}.run(); }
     // clang-format on
 }
diff --git a/src/V3Hash.h b/src/V3Hash.h
index 0fda1b6c9..b9ab8bd98 100644
--- a/src/V3Hash.h
+++ b/src/V3Hash.h
@@ -59,7 +59,7 @@ public:
     // '+' combines hashes
     template <class T>
     V3Hash operator+(T that) const {
-        return V3Hash(combine(m_value, V3Hash(that).m_value));
+        return V3Hash(combine(m_value, V3Hash{that}.m_value));
     }
 
     // '+=' combines in place
diff --git a/src/V3Hasher.cpp b/src/V3Hasher.cpp
index 2916d70cf..2b72c0bc5 100644
--- a/src/V3Hasher.cpp
+++ b/src/V3Hasher.cpp
@@ -42,11 +42,11 @@ private:
                               std::function<void()>&& f) {
         // See comments in visit(AstCFunc) about this breaking recursion
         if (m_cacheInUser4 && nodep->user4()) {
-            return V3Hash(nodep->user4());
+            return V3Hash{nodep->user4()};
         } else {
             VL_RESTORER(m_hash);
             // Reset accumulator
-            m_hash = V3Hash(nodep->type());  // Node type
+            m_hash = V3Hash{nodep->type()};  // Node type
             f();  // Node specific hash
             if (hashDType && nodep != nodep->dtypep()) iterateNull(nodep->dtypep());  // Node dtype
             if (hashChildren) iterateChildrenConst(nodep);  // Children
@@ -401,7 +401,7 @@ private:
         m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {  //
             // We might be in a recursive function, if so on *second* call
             // here we need to break what would be an infinite loop.
-            nodep->user4(V3Hash(1).value());  // Set this "first" call
+            nodep->user4(V3Hash{1}.value());  // Set this "first" call
             // So that a second call will then exit hashNodeAndIterate
             // Having a constant in the hash just means the recursion will
             // end, it shouldn't change the CFunc having a unique hash itself.
@@ -518,13 +518,13 @@ public:
 
 V3Hash V3Hasher::operator()(AstNode* nodep) const {
     if (!nodep->user4()) HasherVisitor{nodep};
-    return V3Hash(nodep->user4());
+    return V3Hash{nodep->user4()};
 }
 
 V3Hash V3Hasher::rehash(AstNode* nodep) const {
     nodep->user4(0);
     { HasherVisitor{nodep}; }
-    return V3Hash(nodep->user4());
+    return V3Hash{nodep->user4()};
 }
 
 V3Hash V3Hasher::uncachedHash(const AstNode* nodep) {
diff --git a/src/V3HierBlock.cpp b/src/V3HierBlock.cpp
index 5f4754925..a1a2342aa 100644
--- a/src/V3HierBlock.cpp
+++ b/src/V3HierBlock.cpp
@@ -311,7 +311,7 @@ public:
 void V3HierBlockPlan::add(const AstNodeModule* modp, const std::vector<AstVar*>& gparams) {
     const iterator it = m_blocks.find(modp);
     if (it == m_blocks.end()) {
-        V3HierBlock* hblockp = new V3HierBlock(modp, gparams);
+        V3HierBlock* hblockp = new V3HierBlock{modp, gparams};
         UINFO(3, "Add " << modp->prettyNameQ() << " with " << gparams.size() << " parameters"
                         << std::endl);
         m_blocks.emplace(modp, hblockp);
diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp
index 8d0eb3b6d..26abb43c6 100644
--- a/src/V3Inline.cpp
+++ b/src/V3Inline.cpp
@@ -292,8 +292,8 @@ private:
             UASSERT_OBJ(exprconstp || exprvarrefp, nodep,
                         "Unknown interconnect type; pinReconnectSimple should have cleared up");
             if (exprconstp) {
-                m_modp->addStmtsp(new AstAssignW(flp, new AstVarRef(flp, nodep, VAccess::WRITE),
-                                                 exprconstp->cloneTree(false)));
+                m_modp->addStmtsp(new AstAssignW{flp, new AstVarRef{flp, nodep, VAccess::WRITE},
+                                                 exprconstp->cloneTree(false)});
             } else if (nodep->user3()) {
                 // Public variable at the lower module end - we need to make sure we propagate
                 // the logic changes up and down; if we aliased, we might
@@ -301,8 +301,8 @@ private:
                 UINFO(9, "public pin assign: " << exprvarrefp << endl);
                 UASSERT_OBJ(!nodep->isNonOutput(), nodep, "Outputs only - inputs use AssignAlias");
                 m_modp->addStmtsp(
-                    new AstAssignW(flp, new AstVarRef(flp, exprvarrefp->varp(), VAccess::WRITE),
-                                   new AstVarRef(flp, nodep, VAccess::READ)));
+                    new AstAssignW{flp, new AstVarRef{flp, exprvarrefp->varp(), VAccess::WRITE},
+                                   new AstVarRef{flp, nodep, VAccess::READ}});
             } else if (nodep->isSigPublic() && VN_IS(nodep->dtypep(), UnpackArrayDType)) {
                 // Public variable at this end and it is an unpacked array. We need to assign
                 // instead of aliased, because otherwise it will pass V3Slice and invalid
@@ -313,8 +313,8 @@ private:
                                    new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}});
             } else if (nodep->isIfaceRef()) {
                 m_modp->addStmtsp(
-                    new AstAssignVarScope(flp, new AstVarRef(flp, nodep, VAccess::WRITE),
-                                          new AstVarRef(flp, exprvarrefp->varp(), VAccess::READ)));
+                    new AstAssignVarScope{flp, new AstVarRef{flp, nodep, VAccess::WRITE},
+                                          new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}});
                 FileLine* const flbp = exprvarrefp->varp()->fileline();
                 flp->modifyStateInherit(flbp);
                 flbp->modifyStateInherit(flp);
@@ -322,8 +322,8 @@ private:
                 // Do to inlining child's variable now within the same
                 // module, so a AstVarRef not AstVarXRef below
                 m_modp->addStmtsp(
-                    new AstAssignAlias(flp, new AstVarRef(flp, nodep, VAccess::WRITE),
-                                       new AstVarRef(flp, exprvarrefp->varp(), VAccess::READ)));
+                    new AstAssignAlias{flp, new AstVarRef{flp, nodep, VAccess::WRITE},
+                                       new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}});
                 FileLine* const flbp = exprvarrefp->varp()->fileline();
                 flp->modifyStateInherit(flbp);
                 flbp->modifyStateInherit(flp);
@@ -519,8 +519,8 @@ private:
         });
         // Create data for dotted variable resolution
         AstCellInline* const inlinep
-            = new AstCellInline(nodep->fileline(), nodep->name(), nodep->modp()->origName(),
-                                nodep->modp()->timeunit());
+            = new AstCellInline{nodep->fileline(), nodep->name(), nodep->modp()->origName(),
+                                nodep->modp()->timeunit()};
         m_modp->addInlinesp(inlinep);  // Must be parsed before any AstCells
         // Create assignments to the pins
         for (AstPin* pinp = nodep->pinsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) {
@@ -659,7 +659,7 @@ private:
                 if ((cellp = VN_CAST(fromVarp->user1p(), Cell)) || (cellp = irdtp->cellp())) {
                     varp->user1p(cellp);
                     const string alias = m_scope + "__DOT__" + pinp->name();
-                    cellp->addIntfRefsp(new AstIntfRef(pinp->fileline(), alias));
+                    cellp->addIntfRefsp(new AstIntfRef{pinp->fileline(), alias});
                 }
             }
 
@@ -688,7 +688,7 @@ private:
         string alias;
         if (!m_scope.empty()) alias = m_scope + "__DOT__";
         alias += varlp->name();
-        cellp->addIntfRefsp(new AstIntfRef(varlp->fileline(), alias));
+        cellp->addIntfRefsp(new AstIntfRef{varlp->fileline(), alias});
     }
     //--------------------
     void visit(AstNodeExpr*) override {}  // Accelerate
diff --git a/src/V3Life.cpp b/src/V3Life.cpp
index d1a3ff617..407880934 100644
--- a/src/V3Life.cpp
+++ b/src/V3Life.cpp
@@ -350,8 +350,8 @@ private:
         // Condition is part of PREVIOUS block
         iterateAndNextNull(nodep->condp());
         LifeBlock* const prevLifep = m_lifep;
-        LifeBlock* const ifLifep = new LifeBlock(prevLifep, m_statep);
-        LifeBlock* const elseLifep = new LifeBlock(prevLifep, m_statep);
+        LifeBlock* const ifLifep = new LifeBlock{prevLifep, m_statep};
+        LifeBlock* const elseLifep = new LifeBlock{prevLifep, m_statep};
         {
             m_lifep = ifLifep;
             iterateAndNextNull(nodep->thensp());
@@ -380,8 +380,8 @@ private:
         // it as a IF statement, and just don't allow elimination of
         // variables across the body.
         LifeBlock* const prevLifep = m_lifep;
-        LifeBlock* const condLifep = new LifeBlock(prevLifep, m_statep);
-        LifeBlock* const bodyLifep = new LifeBlock(prevLifep, m_statep);
+        LifeBlock* const condLifep = new LifeBlock{prevLifep, m_statep};
+        LifeBlock* const bodyLifep = new LifeBlock{prevLifep, m_statep};
         {
             m_lifep = condLifep;
             iterateAndNextNull(nodep->precondsp());
@@ -405,7 +405,7 @@ private:
         // It's worse though as an IF(..., JUMPGO) may change the control flow.
         // Just don't optimize blocks with labels; they're rare - so far.
         LifeBlock* const prevLifep = m_lifep;
-        LifeBlock* const bodyLifep = new LifeBlock(prevLifep, m_statep);
+        LifeBlock* const bodyLifep = new LifeBlock{prevLifep, m_statep};
         {
             VL_RESTORER(m_noopt);
             m_lifep = bodyLifep;
@@ -461,7 +461,7 @@ public:
         : m_statep{statep} {
         UINFO(4, "  LifeVisitor on " << nodep << endl);
         {
-            m_lifep = new LifeBlock(nullptr, m_statep);
+            m_lifep = new LifeBlock{nullptr, m_statep};
             iterate(nodep);
             if (m_lifep) VL_DO_CLEAR(delete m_lifep, m_lifep = nullptr);
         }
diff --git a/src/V3LifePost.cpp b/src/V3LifePost.cpp
index 6ad15bad7..780026a4f 100644
--- a/src/V3LifePost.cpp
+++ b/src/V3LifePost.cpp
@@ -263,7 +263,7 @@ private:
 
         if (v3Global.opt.mtasks()) {
             UASSERT_OBJ(m_mtasksGraphp, nodep, "Should have initted m_mtasksGraphp by now");
-            m_checker.reset(new GraphPathChecker(m_mtasksGraphp));
+            m_checker.reset(new GraphPathChecker{m_mtasksGraphp});
         } else {
             UASSERT_OBJ(!m_mtasksGraphp, nodep,
                         "Did not expect any m_mtasksGraphp in serial mode");
diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp
index 417cd08dc..171349790 100644
--- a/src/V3LinkLevel.cpp
+++ b/src/V3LinkLevel.cpp
@@ -147,7 +147,7 @@ void V3LinkLevel::wrapTop(AstNetlist* rootp) {
         return;
     }
 
-    AstNodeModule* const newmodp = new AstModule(oldmodp->fileline(), "$root");
+    AstNodeModule* const newmodp = new AstModule{oldmodp->fileline(), "$root"};
     newmodp->name(AstNode::encodeName(newmodp->name()));  // so origName is nice
     // Make the new module first in the list
     oldmodp->unlinkFrBackWithNext();
@@ -167,10 +167,10 @@ void V3LinkLevel::wrapTop(AstNetlist* rootp) {
     for (AstNodeModule* modp = rootp->modulesp(); modp; modp = VN_AS(modp->nextp(), NodeModule)) {
         if (VN_IS(modp, Package)) {
             AstCell* const cellp
-                = new AstCell(modp->fileline(), modp->fileline(),
+                = new AstCell{modp->fileline(), modp->fileline(),
                               // Could add __03a__03a="::" to prevent conflict
                               // with module names/"v"
-                              modp->name(), modp->name(), nullptr, nullptr, nullptr);
+                              modp->name(), modp->name(), nullptr, nullptr, nullptr};
             cellp->modp(modp);
             newmodp->addStmtsp(cellp);
         }
@@ -240,10 +240,14 @@ void V3LinkLevel::wrapTopCell(AstNetlist* rootp) {
         if (VN_IS(oldmodp, Package)) continue;
         // Add instance
         UINFO(5, "LOOP " << oldmodp << endl);
-        AstCell* const cellp = new AstCell(
-            newmodp->fileline(), newmodp->fileline(),
+        AstCell* const cellp = new AstCell{
+            newmodp->fileline(),
+            newmodp->fileline(),
             (!v3Global.opt.l2Name().empty() ? v3Global.opt.l2Name() : oldmodp->name()),
-            oldmodp->name(), nullptr, nullptr, nullptr);
+            oldmodp->name(),
+            nullptr,
+            nullptr,
+            nullptr};
         cellp->modp(oldmodp);
         newmodp->addStmtsp(cellp);
 
@@ -279,10 +283,10 @@ void V3LinkLevel::wrapTopCell(AstNetlist* rootp) {
                         varp->trace(false);
                     }
 
-                    AstPin* const pinp = new AstPin(
+                    AstPin* const pinp = new AstPin{
                         oldvarp->fileline(), 0, varp->name(),
-                        new AstVarRef(varp->fileline(), varp,
-                                      oldvarp->isWritable() ? VAccess::WRITE : VAccess::READ));
+                        new AstVarRef{varp->fileline(), varp,
+                                      oldvarp->isWritable() ? VAccess::WRITE : VAccess::READ}};
                     // Skip length and width comp; we know it's a direct assignment
                     pinp->modVarp(oldvarp);
                     cellp->addPinsp(pinp);
diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp
index 9b6729e72..06d1bc27e 100644
--- a/src/V3LinkResolve.cpp
+++ b/src/V3LinkResolve.cpp
@@ -152,21 +152,21 @@ private:
             AstNode* const basefromp = AstArraySel::baseFromp(nodep, false);
             if (AstNodeVarRef* const varrefp
                 = VN_CAST(basefromp, NodeVarRef)) {  // Maybe varxref - so need to clone
-                nodep->attrp(new AstAttrOf(nodep->fileline(), VAttrType::VAR_BASE,
-                                           varrefp->cloneTree(false)));
+                nodep->attrp(new AstAttrOf{nodep->fileline(), VAttrType::VAR_BASE,
+                                           varrefp->cloneTree(false)});
             } else if (AstUnlinkedRef* const uvxrp
                        = VN_CAST(basefromp, UnlinkedRef)) {  // Maybe unlinked - so need to clone
-                nodep->attrp(new AstAttrOf(nodep->fileline(), VAttrType::VAR_BASE,
-                                           uvxrp->cloneTree(false)));
+                nodep->attrp(new AstAttrOf{nodep->fileline(), VAttrType::VAR_BASE,
+                                           uvxrp->cloneTree(false)});
             } else if (auto* const fromp = VN_CAST(basefromp, LambdaArgRef)) {
-                nodep->attrp(new AstAttrOf(nodep->fileline(), VAttrType::VAR_BASE,
-                                           fromp->cloneTree(false)));
+                nodep->attrp(new AstAttrOf{nodep->fileline(), VAttrType::VAR_BASE,
+                                           fromp->cloneTree(false)});
             } else if (AstMemberSel* const fromp = VN_CAST(basefromp, MemberSel)) {
-                nodep->attrp(new AstAttrOf(nodep->fileline(), VAttrType::MEMBER_BASE,
-                                           fromp->cloneTree(false)));
+                nodep->attrp(new AstAttrOf{nodep->fileline(), VAttrType::MEMBER_BASE,
+                                           fromp->cloneTree(false)});
             } else if (AstEnumItemRef* const fromp = VN_CAST(basefromp, EnumItemRef)) {
-                nodep->attrp(new AstAttrOf(nodep->fileline(), VAttrType::ENUM_BASE,
-                                           fromp->cloneTree(false)));
+                nodep->attrp(new AstAttrOf{nodep->fileline(), VAttrType::ENUM_BASE,
+                                           fromp->cloneTree(false)});
             } else if (VN_IS(basefromp, Replicate)) {
                 // From {...}[...] syntax in IEEE 2017
                 if (basefromp) UINFO(1, "    Related node: " << basefromp << endl);
@@ -412,9 +412,9 @@ private:
                         varoutp = varp;
                         // Tie off
                         m_modp->addStmtsp(
-                            new AstAssignW(varp->fileline(),
-                                           new AstVarRef(varp->fileline(), varp, VAccess::WRITE),
-                                           new AstConst(varp->fileline(), AstConst::BitFalse())));
+                            new AstAssignW{varp->fileline(),
+                                           new AstVarRef{varp->fileline(), varp, VAccess::WRITE},
+                                           new AstConst{varp->fileline(), AstConst::BitFalse{}}});
                     } else {
                         varp->v3error("Only inputs and outputs are allowed in udp modules");
                     }
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index e438d646e..f8dd03135 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -133,7 +133,7 @@ VTimescale::VTimescale(const string& value, bool& badr)
     badr = true;
     const string spaceless = VString::removeWhitespace(value);
     for (int i = TS_100S; i < _ENUM_END; ++i) {
-        const VTimescale ts(i);
+        const VTimescale ts{i};
         if (spaceless == ts.ascii()) {
             badr = false;
             m_e = ts.m_e;
@@ -258,7 +258,7 @@ void VTimescale::parseSlashed(FileLine* fl, const char* textp, VTimescale& unitr
     }
 
     bool unitbad;
-    const VTimescale unit(unitStr, unitbad /*ref*/);
+    const VTimescale unit{unitStr, unitbad /*ref*/};
     if (unitbad && !(unitStr.empty() && allowEmpty)) {
         fl->v3error("`timescale timeunit syntax error: '" << unitStr << "'");
         return;
@@ -863,7 +863,7 @@ string V3Options::protectKeyDefaulted() {
     if (m_protectKey.empty()) {
         // Create a key with a human-readable symbol-like name.
         // This conversion drops ~2 bits of entropy out of 256, shouldn't matter.
-        VHashSha256 digest(V3Os::trueRandom(32));
+        VHashSha256 digest{V3Os::trueRandom(32)};
         m_protectKey = "VL-KEY-" + digest.digestSymbol();
     }
     return m_protectKey;
@@ -1198,7 +1198,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
 
     DECL_OPTION("-hierarchical", OnOff, &m_hierarchical);
     DECL_OPTION("-hierarchical-block", CbVal, [this](const char* valp) {
-        const V3HierarchicalBlockOption opt(valp);
+        const V3HierarchicalBlockOption opt{valp};
         m_hierBlocks.emplace(opt.mangledName(), opt);
     });
     DECL_OPTION("-hierarchical-child", Set, &m_hierChild);
@@ -1502,7 +1502,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
         V3Error::pretendError(V3ErrorCode::UNUSEDSIGNAL, true);
     });
     DECL_OPTION("-Werror-", CbPartialMatch, [this, fl](const char* optp) {
-        const V3ErrorCode code(optp);
+        const V3ErrorCode code{optp};
         if (code == V3ErrorCode::EC_ERROR) {
             if (!isFuture(optp)) fl->v3fatal("Unknown warning specified: -Werror-" << optp);
         } else {
diff --git a/src/V3Order.cpp b/src/V3Order.cpp
index bd3a3ee6e..1e3f50987 100644
--- a/src/V3Order.cpp
+++ b/src/V3Order.cpp
@@ -498,7 +498,7 @@ public:
         if (iter != s_dsMap.end()) {
             return iter->second;
         } else {
-            OrderMoveDomScope* domScopep = new OrderMoveDomScope(domainp, scopep);
+            OrderMoveDomScope* domScopep = new OrderMoveDomScope{domainp, scopep};
             s_dsMap.emplace(key, domScopep);
             return domScopep;
         }
@@ -736,7 +736,7 @@ public:
     // METHODS
     OrderMoveVertex* makeVertexp(OrderLogicVertex* lvertexp, const OrderEitherVertex*,
                                  const AstSenTree* domainp) override {
-        OrderMoveVertex* const resultp = new OrderMoveVertex(m_pomGraphp, lvertexp);
+        OrderMoveVertex* const resultp = new OrderMoveVertex{m_pomGraphp, lvertexp};
         AstScope* const scopep = lvertexp ? lvertexp->scopep() : nullptr;
         resultp->domScopep(OrderMoveDomScope::findCreate(domainp, scopep));
         resultp->m_pomWaitingE.pushBack(*m_pomWaitingp, resultp);
@@ -1358,7 +1358,7 @@ void OrderProcess::processMTasks() {
         const AbstractLogicMTask* const mtaskp = static_cast<const AbstractLogicMTask*>(mtaskVxp);
 
         // Create a body for this mtask
-        AstMTaskBody* const bodyp = new AstMTaskBody(rootFlp);
+        AstMTaskBody* const bodyp = new AstMTaskBody{rootFlp};
         MTaskState& state = mtaskStates[mtaskp->id()];
         state.m_mtaskBodyp = bodyp;
 
@@ -1388,7 +1388,7 @@ void OrderProcess::processMTasks() {
         // - The ExecMTask graph and the AstMTaskBody's produced here
         //   persist until code generation time.
         V3Graph* const depGraphp = execGraphp->depGraphp();
-        state.m_execMTaskp = new ExecMTask(depGraphp, bodyp, mtaskp->id());
+        state.m_execMTaskp = new ExecMTask{depGraphp, bodyp, mtaskp->id()};
         // Cross-link each ExecMTask and MTaskBody
         //  Q: Why even have two objects?
         //  A: One is an AstNode, the other is a GraphVertex,
@@ -1399,7 +1399,7 @@ void OrderProcess::processMTasks() {
             const AbstractLogicMTask* const fromp
                 = static_cast<const AbstractLogicMTask*>(fromVxp);
             const MTaskState& fromState = mtaskStates[fromp->id()];
-            new V3GraphEdge(depGraphp, fromState.m_execMTaskp, state.m_execMTaskp, 1);
+            new V3GraphEdge{depGraphp, fromState.m_execMTaskp, state.m_execMTaskp, 1};
         }
         execGraphp->addMTaskBodiesp(bodyp);
     }
diff --git a/src/V3Param.cpp b/src/V3Param.cpp
index b1153931b..86434f450 100644
--- a/src/V3Param.cpp
+++ b/src/V3Param.cpp
@@ -211,7 +211,7 @@ public:
             } else {
                 varNum.opAssign(pinValuep->num());
             }
-            V3Number isEq(pinValuep, 1);
+            V3Number isEq{pinValuep, 1};
             isEq.opEq(varNum, hierOptParamp->num());
             return isEq.isNeqZero();
         }
@@ -344,7 +344,7 @@ class ParamProcessor final {
         const string key = paramValueKey(nodep);
         V3Hash hash = V3Hasher::uncachedHash(nodep);
         // Force hash collisions -- for testing only
-        if (VL_UNLIKELY(v3Global.opt.debugCollision())) hash = V3Hash();
+        if (VL_UNLIKELY(v3Global.opt.debugCollision())) hash = V3Hash{};
         int num;
         const auto it = m_valueMap.find(hash);
         if (it != m_valueMap.end() && it->second.second == key) {
@@ -656,8 +656,8 @@ class ParamProcessor final {
                     if (debug()) pinp->dumpTree(cout, "-nodes: ");
                     pinp->v3error("Can't convert defparam value to constant: Param "
                                   << pinp->prettyNameQ() << " of " << nodep->prettyNameQ());
-                    pinp->exprp()->replaceWith(new AstConst(
-                        pinp->fileline(), AstConst::WidthedValue(), modvarp->width(), 0));
+                    pinp->exprp()->replaceWith(new AstConst{
+                        pinp->fileline(), AstConst::WidthedValue{}, modvarp->width(), 0});
                 } else if (origp && exprp->sameTree(origp)) {
                     // Setting parameter to its default value.  Just ignore it.
                     // This prevents making additional modules, and makes coverage more
@@ -1220,7 +1220,7 @@ class ParamVisitor final : public VNVisitor {
             if (!itemp->isDefault()) {
                 for (AstNode* ep = itemp->condsp(); ep; ep = ep->nextp()) {
                     if (const AstConst* const ccondp = VN_CAST(ep, Const)) {
-                        V3Number match(nodep, 1);
+                        V3Number match{nodep, 1};
                         match.opEq(ccondp->num(), exprp->num());
                         if (!keepp && match.isNeqZero()) keepp = itemp->stmtsp();
                     } else {
diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp
index 4bc4f0d76..2236eb934 100644
--- a/src/V3PreProc.cpp
+++ b/src/V3PreProc.cpp
@@ -344,7 +344,7 @@ void V3PreProcImp::define(FileLine* fl, const string& name, const string& value,
             }
             undef(name);
         }
-        m_defines.emplace(name, VDefine(fl, value, params, cmdline));
+        m_defines.emplace(name, VDefine{fl, value, params, cmdline});
     }
 }
 
@@ -1050,7 +1050,7 @@ int V3PreProcImp::getStateToken() {
                     bool enable = defExists(m_lastSym);
                     UINFO(4, "Ifdef " << m_lastSym << (enable ? " ON" : " OFF") << endl);
                     if (state() == ps_DEFNAME_IFNDEF) enable = !enable;
-                    m_ifdefStack.push(VPreIfEntry(enable, false));
+                    m_ifdefStack.push(VPreIfEntry{enable, false});
                     if (!enable) parsingOff();
                     statePop();
                     goto next_tok;
@@ -1065,7 +1065,7 @@ int V3PreProcImp::getStateToken() {
                         // Handle `if portion
                         const bool enable = !lastIf.everOn() && defExists(m_lastSym);
                         UINFO(4, "Elsif " << m_lastSym << (enable ? " ON" : " OFF") << endl);
-                        m_ifdefStack.push(VPreIfEntry(enable, lastIf.everOn()));
+                        m_ifdefStack.push(VPreIfEntry{enable, lastIf.everOn()});
                         if (!enable) parsingOff();
                     }
                     statePop();
@@ -1380,7 +1380,7 @@ int V3PreProcImp::getStateToken() {
                 m_ifdefStack.pop();
                 const bool enable = !lastIf.everOn();
                 UINFO(4, "Else " << (enable ? " ON" : " OFF") << endl);
-                m_ifdefStack.push(VPreIfEntry(enable, lastIf.everOn()));
+                m_ifdefStack.push(VPreIfEntry{enable, lastIf.everOn()});
                 if (!lastIf.on()) parsingOn();
                 if (!enable) parsingOff();
             }
@@ -1428,7 +1428,7 @@ int V3PreProcImp::getStateToken() {
                 if (params == "0" || params == "") {  // Found, as simple substitution
                     string out;
                     if (!m_off) {
-                        VDefineRef tempref(name, "");
+                        VDefineRef tempref{name, ""};
                         out = defineSubst(&tempref);
                     }
                     // Similar code in parenthesized define (Search for END_OF_DEFARG)
@@ -1467,7 +1467,7 @@ int V3PreProcImp::getStateToken() {
                     // The CURRENT macro needs the paren saved, it's not a
                     // property of the child macro
                     if (!m_defRefs.empty()) m_defRefs.top().parenLevel(m_lexp->m_parenLevel);
-                    m_defRefs.push(VDefineRef(name, params));
+                    m_defRefs.push(VDefineRef{name, params});
                     statePush(ps_DEFPAREN);
                     m_lexp->pushStateDefArg(0);
                     goto next_tok;
diff --git a/src/V3Scope.cpp b/src/V3Scope.cpp
index ce60b19de..ffc8127e7 100644
--- a/src/V3Scope.cpp
+++ b/src/V3Scope.cpp
@@ -107,10 +107,10 @@ private:
         UINFO(4, " MOD AT " << scopename << "  " << nodep << endl);
         AstNode::user1ClearTree();
 
-        m_scopep = new AstScope(
+        m_scopep = new AstScope{
             (m_aboveCellp ? static_cast<AstNode*>(m_aboveCellp) : static_cast<AstNode*>(nodep))
                 ->fileline(),
-            nodep, scopename, m_aboveScopep, m_aboveCellp);
+            nodep, scopename, m_aboveScopep, m_aboveCellp};
         if (VN_IS(nodep, Package)) m_packageScopes.emplace(nodep, m_scopep);
 
         // Now for each child cell, iterate the module this cell points to
@@ -173,7 +173,7 @@ private:
             const AstNode* const abovep = (m_aboveCellp ? static_cast<AstNode*>(m_aboveCellp)
                                                         : static_cast<AstNode*>(nodep));
             m_scopep
-                = new AstScope(abovep->fileline(), m_modp, scopename, m_aboveScopep, m_aboveCellp);
+                = new AstScope{abovep->fileline(), m_modp, scopename, m_aboveScopep, m_aboveCellp};
             m_packageScopes.emplace(nodep, m_scopep);
 
             // Create scope for the current usage of this cell
@@ -304,11 +304,11 @@ private:
         // To keep correct visual order, must add before other Text's
         AstText* afterp = nodep->scopeAttrp();
         if (afterp) afterp->unlinkFrBackWithNext();
-        nodep->addScopeAttrp(new AstText(nodep->fileline(), prefix));
+        nodep->addScopeAttrp(new AstText{nodep->fileline(), prefix});
         if (afterp) nodep->addScopeAttrp(afterp);
         afterp = nodep->scopeEntrp();
         if (afterp) afterp->unlinkFrBackWithNext();
-        nodep->addScopeEntrp(new AstText(nodep->fileline(), prefix));
+        nodep->addScopeEntrp(new AstText{nodep->fileline(), prefix});
         if (afterp) nodep->addScopeEntrp(afterp);
         iterateChildren(nodep);
     }
diff --git a/src/V3Stats.h b/src/V3Stats.h
index 1a51619c6..6676797a1 100644
--- a/src/V3Stats.h
+++ b/src/V3Stats.h
@@ -103,16 +103,16 @@ class V3Stats final {
 public:
     static void addStat(const V3Statistic&);
     static void addStat(const string& stage, const string& name, double count) {
-        addStat(V3Statistic(stage, name, count));
+        addStat(V3Statistic{stage, name, count});
     }
     static void addStat(const string& name, double count) {
-        addStat(V3Statistic("*", name, count));
+        addStat(V3Statistic{"*", name, count});
     }
     static void addStatSum(const string& name, double count) {
-        addStat(V3Statistic("*", name, count, true));
+        addStat(V3Statistic{"*", name, count, true});
     }
     static void addStatPerf(const string& name, double count) {
-        addStat(V3Statistic("*", name, count, true, true));
+        addStat(V3Statistic{"*", name, count, true, true});
     }
     /// Called each stage
     static void statsStage(const string& name);
diff --git a/src/V3String.cpp b/src/V3String.cpp
index 58369df21..232673006 100644
--- a/src/V3String.cpp
+++ b/src/V3String.cpp
@@ -386,7 +386,7 @@ string VHashSha256::digestSymbol() {
 
 void VHashSha256::selfTestOne(const string& data, const string& data2, const string& exp,
                               const string& exp64) {
-    VHashSha256 digest(data);
+    VHashSha256 digest{data};
     if (data2 != "") digest.insert(data2);
     if (VL_UNCOVERABLE(digest.digestHex() != exp)) {
         std::cerr << "%Error: When hashing '" << data + data2 << "'\n"  // LCOV_EXCL_LINE
@@ -476,7 +476,7 @@ string VName::hashedName() {
         m_hashed = m_name;
         return m_hashed;
     } else {
-        VHashSha256 hash(m_name);
+        VHashSha256 hash{m_name};
         const string suffix = "__Vhsh" + hash.digestSymbol();
         if (s_minLength < s_maxLength) {
             s_dehashMap[suffix] = m_name.substr(s_minLength);
diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp
index e0b96f4ae..73fbaaabc 100644
--- a/src/V3Unroll.cpp
+++ b/src/V3Unroll.cpp
@@ -198,9 +198,9 @@ private:
         AstNode* clonep = nodep->cloneTree(true);
         UASSERT_OBJ(clonep, nodep, "Failed to clone tree");
         if (loopValue) {
-            m_varValuep = new AstConst(nodep->fileline(), *loopValue);
+            m_varValuep = new AstConst{nodep->fileline(), *loopValue};
             // Iteration requires a back, so put under temporary node
-            AstBegin* tempp = new AstBegin(nodep->fileline(), "[EditWrapper]", clonep);
+            AstBegin* tempp = new AstBegin{nodep->fileline(), "[EditWrapper]", clonep};
             m_varModeReplace = true;
             iterateAndNextNull(tempp->stmtsp());
             m_varModeReplace = false;
@@ -310,12 +310,12 @@ private:
                     // Replace iterator values with constant.
                     AstNode* oneloopp = stmtsp->cloneTree(true);
 
-                    m_varValuep = new AstConst(nodep->fileline(), loopValue);
+                    m_varValuep = new AstConst{nodep->fileline(), loopValue};
 
                     // Iteration requires a back, so put under temporary node
                     if (oneloopp) {
                         AstBegin* const tempp
-                            = new AstBegin(oneloopp->fileline(), "[EditWrapper]", oneloopp);
+                            = new AstBegin{oneloopp->fileline(), "[EditWrapper]", oneloopp};
                         m_varModeReplace = true;
                         iterateAndNextNull(tempp->stmtsp());
                         m_varModeReplace = false;
@@ -325,7 +325,7 @@ private:
                     if (m_generate) {
                         const string index = AstNode::encodeNumber(m_varValuep->toSInt());
                         const string nname = m_beginName + "__BRA__" + index + "__KET__";
-                        oneloopp = new AstBegin(oneloopp->fileline(), nname, oneloopp, true);
+                        oneloopp = new AstBegin{oneloopp->fileline(), nname, oneloopp, true};
                     }
                     VL_DO_CLEAR(pushDeletep(m_varValuep), m_varValuep = nullptr);
                     if (newbodysp) {
diff --git a/src/VlcSource.h b/src/VlcSource.h
index af711f0af..fc40ae241 100644
--- a/src/VlcSource.h
+++ b/src/VlcSource.h
@@ -89,7 +89,7 @@ public:
         ColumnMap& cmap = lit->second;
         ColumnMap::iterator cit = cmap.find(column);
         if (cit == cmap.end()) {
-            cit = cmap.insert(std::make_pair(column, VlcSourceCount(lineno, column))).first;
+            cit = cmap.insert(std::make_pair(column, VlcSourceCount{lineno, column})).first;
         }
         VlcSourceCount& sc = cit->second;
         sc.incCount(count, ok);
@@ -124,7 +124,7 @@ public:
         if (iter != m_sources.end()) {
             return iter->second;
         } else {
-            iter = m_sources.insert(std::make_pair(name, VlcSource(name))).first;
+            iter = m_sources.insert(std::make_pair(name, VlcSource{name})).first;
             return iter->second;
         }
     }

From 3abb65d732f228cfeb16561b2cf081e68c652423 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Sun, 13 Nov 2022 20:33:11 +0000
Subject: [PATCH 074/156] Strengthen AstNode types to AstNodeExpr

Declare every AstNode children and variables as AstNodeExpr where we
statically know this is the appropriate sub-type.
---
 src/V3Assert.cpp                         |  58 +-
 src/V3AssertPre.cpp                      |  28 +-
 src/V3Ast.h                              |   4 +-
 src/V3AstInlines.h                       |   2 +-
 src/V3AstNodeDType.h                     |  14 +-
 src/V3AstNodeExpr.h                      | 922 ++++++++++++++---------
 src/V3AstNodeOther.h                     | 429 +++--------
 src/V3AstNodes.cpp                       |  28 +-
 src/V3CCtors.cpp                         |   5 +-
 src/V3Case.cpp                           |  34 +-
 src/V3Cast.cpp                           |   9 +-
 src/V3Clean.cpp                          |  18 +-
 src/V3Clock.cpp                          |  22 +-
 src/V3Common.cpp                         |   7 +-
 src/V3Const.cpp                          | 370 +++++----
 src/V3Const.h                            |  12 +-
 src/V3Coverage.cpp                       |   6 +-
 src/V3Delayed.cpp                        |  24 +-
 src/V3Depth.cpp                          |   2 +-
 src/V3DfgDfgToAst.cpp                    |   2 +-
 src/V3Expand.cpp                         | 170 ++---
 src/V3Force.cpp                          |   6 +-
 src/V3Inst.cpp                           |  26 +-
 src/V3LinkDot.cpp                        |  21 +-
 src/V3LinkInc.cpp                        |   6 +-
 src/V3LinkJump.cpp                       |   8 +-
 src/V3LinkParse.cpp                      |  10 +-
 src/V3MergeCond.cpp                      |  24 +-
 src/V3ParseGrammar.cpp                   |   6 +-
 src/V3Premit.cpp                         |  15 +-
 src/V3Randomize.cpp                      |   6 +-
 src/V3Reloop.cpp                         |  14 +-
 src/V3SenExprBuilder.h                   |  14 +-
 src/V3Simulate.h                         |  40 +-
 src/V3Slice.cpp                          |  23 +-
 src/V3SplitVar.cpp                       |  29 +-
 src/V3Subst.cpp                          |  12 +-
 src/V3Table.cpp                          |   8 +-
 src/V3Task.cpp                           |  18 +-
 src/V3Timing.cpp                         |  26 +-
 src/V3Trace.cpp                          |   6 +-
 src/V3TraceDecl.cpp                      |   2 +-
 src/V3Tristate.cpp                       | 122 +--
 src/V3Unknown.cpp                        |  52 +-
 src/V3Width.cpp                          | 299 ++++----
 src/V3WidthSel.cpp                       |  59 +-
 src/astgen                               |  15 +-
 src/verilog.y                            | 113 +--
 test_regress/t/t_stream_bad.out          |  15 +
 test_regress/t/t_stream_bad.pl           |  19 +
 test_regress/t/t_stream_bad.v            |  14 +
 test_regress/t/t_stream_integer_type.out | 120 ++-
 52 files changed, 1742 insertions(+), 1572 deletions(-)
 create mode 100644 test_regress/t/t_stream_bad.out
 create mode 100755 test_regress/t/t_stream_bad.pl
 create mode 100644 test_regress/t/t_stream_bad.v

diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp
index 62976a59a..4c37f2f76 100644
--- a/src/V3Assert.cpp
+++ b/src/V3Assert.cpp
@@ -59,8 +59,8 @@ private:
         nodep->displayType(VDisplayType::DT_WRITE);
         nodep->fmtp()->text(assertDisplayMessage(nodep, prefix, nodep->fmtp()->text()));
         // cppcheck-suppress nullPointer
-        AstNode* const timenewp = new AstTime{nodep->fileline(), m_modp->timeunit()};
-        if (AstNode* const timesp = nodep->fmtp()->exprsp()) {
+        AstNodeExpr* const timenewp = new AstTime{nodep->fileline(), m_modp->timeunit()};
+        if (AstNodeExpr* const timesp = nodep->fmtp()->exprsp()) {
             timesp->unlinkFrBackWithNext();
             timenewp->addNext(timesp);
         }
@@ -69,7 +69,7 @@ private:
             nodep->fmtp()->scopeNamep(new AstScopeName{nodep->fileline(), true});
         }
     }
-    AstSampled* newSampledExpr(AstNode* nodep) {
+    AstSampled* newSampledExpr(AstNodeExpr* nodep) {
         const auto sampledp = new AstSampled{nodep->fileline(), nodep};
         sampledp->dtypeFrom(nodep);
         return sampledp;
@@ -98,16 +98,16 @@ private:
         // Add a internal if to check assertions are on.
         // Don't make this a AND term, as it's unlikely to need to test this.
         FileLine* const fl = nodep->fileline();
-        AstNodeIf* const newp = new AstIf{
-            fl,
-            (force ? new AstConst{fl, AstConst::BitTrue{}}
-                   :  // If assertions are off, have constant propagation rip them out later
-                 // This allows syntax errors and such to be detected normally.
-                 (v3Global.opt.assertOn()
-                      ? static_cast<AstNode*>(
-                          new AstCExpr{fl, "vlSymsp->_vm_contextp__->assertOn()", 1})
-                      : static_cast<AstNode*>(new AstConst{fl, AstConst::BitFalse{}}))),
-            nodep};
+
+        // If assertions are off, have constant propagation rip them out later
+        // This allows syntax errors and such to be detected normally.
+        AstNodeExpr* const condp
+            = force ? static_cast<AstNodeExpr*>(new AstConst{fl, AstConst::BitTrue{}})
+              : v3Global.opt.assertOn()
+                  ? static_cast<AstNodeExpr*>(
+                      new AstCExpr{fl, "vlSymsp->_vm_contextp__->assertOn()", 1})
+                  : static_cast<AstNodeExpr*>(new AstConst{fl, AstConst::BitFalse{}});
+        AstNodeIf* const newp = new AstIf{fl, condp, nodep};
         newp->isBoundsCheck(true);  // To avoid LATCH warning
         newp->user1(true);  // Don't assert/cover this if
         return newp;
@@ -133,7 +133,7 @@ private:
     void newPslAssertion(AstNodeCoverOrAssert* nodep, AstNode* failsp) {
         if (m_beginp && nodep->name() == "") nodep->name(m_beginp->name());
 
-        AstNode* const propp = nodep->propp()->unlinkFrBackWithNext();
+        AstNodeExpr* const propp = VN_AS(nodep->propp()->unlinkFrBackWithNext(), NodeExpr);
         AstSenTree* const sentreep = nodep->sentreep();
         const string& message = nodep->name();
         AstNode* passsp = nodep->passsp();
@@ -211,7 +211,7 @@ private:
         if (nodep->user1SetOnce()) return;
         if (nodep->uniquePragma() || nodep->unique0Pragma()) {
             const AstNodeIf* ifp = nodep;
-            AstNode* propp = nullptr;
+            AstNodeExpr* propp = nullptr;
             bool hasDefaultElse = false;
             do {
                 // If this statement ends with 'else if', then nextIf will point to the
@@ -228,7 +228,7 @@ private:
                 }
 
                 // Build a bitmask of the true predicates
-                AstNode* const predp = ifp->condp()->cloneTree(false);
+                AstNodeExpr* const predp = ifp->condp()->cloneTree(false);
                 if (propp) {
                     propp = new AstConcat{nodep->fileline(), predp, propp};
                 } else {
@@ -249,10 +249,10 @@ private:
 
             // Note: if this ends with an 'else', then we don't need to validate that one of the
             // predicates evaluates to true.
-            AstNode* const ohot
+            AstNodeExpr* const ohot
                 = ((allow_none || hasDefaultElse)
-                       ? static_cast<AstNode*>(new AstOneHot0{nodep->fileline(), propp})
-                       : static_cast<AstNode*>(new AstOneHot{nodep->fileline(), propp}));
+                       ? static_cast<AstNodeExpr*>(new AstOneHot0{nodep->fileline(), propp})
+                       : static_cast<AstNodeExpr*>(new AstOneHot{nodep->fileline(), propp}));
             AstIf* const checkifp
                 = new AstIf{nodep->fileline(), new AstLogNot{nodep->fileline(), ohot},
                             newFireAssert(nodep, "'unique if' statement violated"), newifp};
@@ -290,11 +290,12 @@ private:
                 if (!has_default && !nodep->itemsp()) {
                     // Not parallel, but harmlessly so.
                 } else {
-                    AstNode* propp = nullptr;
+                    AstNodeExpr* propp = nullptr;
                     for (AstCaseItem* itemp = nodep->itemsp(); itemp;
                          itemp = VN_AS(itemp->nextp(), CaseItem)) {
-                        for (AstNode* icondp = itemp->condsp(); icondp; icondp = icondp->nextp()) {
-                            AstNode* onep;
+                        for (AstNodeExpr* icondp = itemp->condsp(); icondp;
+                             icondp = VN_AS(icondp->nextp(), NodeExpr)) {
+                            AstNodeExpr* onep;
                             if (AstInsideRange* const rcondp = VN_CAST(icondp, InsideRange)) {
                                 onep = rcondp->newAndFromInside(nodep->exprp(),
                                                                 rcondp->lhsp()->cloneTree(true),
@@ -319,10 +320,11 @@ private:
                     if (!propp) propp = new AstConst{nodep->fileline(), AstConst::BitFalse{}};
 
                     const bool allow_none = has_default || nodep->unique0Pragma();
-                    AstNode* const ohot
-                        = (allow_none
-                               ? static_cast<AstNode*>(new AstOneHot0{nodep->fileline(), propp})
-                               : static_cast<AstNode*>(new AstOneHot{nodep->fileline(), propp}));
+                    AstNodeExpr* const ohot
+                        = (allow_none ? static_cast<AstNodeExpr*>(
+                               new AstOneHot0{nodep->fileline(), propp})
+                                      : static_cast<AstNodeExpr*>(
+                                          new AstOneHot{nodep->fileline(), propp}));
                     AstIf* const ifp = new AstIf{
                         nodep->fileline(), new AstLogNot{nodep->fileline(), ohot},
                         newFireAssert(nodep,
@@ -345,8 +347,8 @@ private:
             ticks = VN_AS(nodep->ticksp(), Const)->toUInt();
         }
         UASSERT_OBJ(ticks >= 1, nodep, "0 tick should have been checked in V3Width");
-        AstNode* const exprp = nodep->exprp()->unlinkFrBack();
-        AstNode* inp = newSampledExpr(exprp);
+        AstNodeExpr* const exprp = nodep->exprp()->unlinkFrBack();
+        AstNodeExpr* inp = newSampledExpr(exprp);
         AstVar* invarp = nullptr;
         AstSenTree* const sentreep = nodep->sentreep();
         sentreep->unlinkFrBack();
diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp
index 0cd4a9a00..43d5f6e32 100644
--- a/src/V3AssertPre.cpp
+++ b/src/V3AssertPre.cpp
@@ -46,7 +46,7 @@ private:
     // Reset each always:
     AstSenItem* m_seniAlwaysp = nullptr;  // Last sensitivity in always
     // Reset each assertion:
-    AstNode* m_disablep = nullptr;  // Last disable
+    AstNodeExpr* m_disablep = nullptr;  // Last disable
 
     // METHODS
 
@@ -113,7 +113,7 @@ private:
                 }
                 // If disable iff is in outer property, move it to inner
                 if (nodep->disablep()) {
-                    AstNode* const disablep = nodep->disablep()->unlinkFrBack();
+                    AstNodeExpr* const disablep = nodep->disablep()->unlinkFrBack();
                     propExprp->disablep(disablep);
                 }
 
@@ -170,9 +170,9 @@ private:
         if (nodep->sentreep()) return;  // Already processed
         iterateChildren(nodep);
         FileLine* const fl = nodep->fileline();
-        AstNode* exprp = nodep->exprp()->unlinkFrBack();
+        AstNodeExpr* exprp = nodep->exprp()->unlinkFrBack();
         if (exprp->width() > 1) exprp = new AstSel(fl, exprp, 0, 1);
-        AstNode* const past = new AstPast(fl, exprp, nullptr);
+        AstNodeExpr* const past = new AstPast(fl, exprp, nullptr);
         past->dtypeFrom(exprp);
         exprp = new AstAnd(fl, past, new AstNot(fl, exprp->cloneTree(false)));
         exprp->dtypeSetBit();
@@ -189,9 +189,9 @@ private:
         if (nodep->sentreep()) return;  // Already processed
         iterateChildren(nodep);
         FileLine* const fl = nodep->fileline();
-        AstNode* exprp = nodep->exprp()->unlinkFrBack();
+        AstNodeExpr* exprp = nodep->exprp()->unlinkFrBack();
         if (exprp->width() > 1) exprp = new AstSel(fl, exprp, 0, 1);
-        AstNode* const past = new AstPast(fl, exprp, nullptr);
+        AstNodeExpr* const past = new AstPast(fl, exprp, nullptr);
         past->dtypeFrom(exprp);
         exprp = new AstAnd(fl, new AstNot(fl, past), exprp->cloneTree(false));
         exprp->dtypeSetBit();
@@ -203,8 +203,8 @@ private:
         if (nodep->sentreep()) return;  // Already processed
         iterateChildren(nodep);
         FileLine* const fl = nodep->fileline();
-        AstNode* exprp = nodep->exprp()->unlinkFrBack();
-        AstNode* const past = new AstPast(fl, exprp, nullptr);
+        AstNodeExpr* exprp = nodep->exprp()->unlinkFrBack();
+        AstNodeExpr* const past = new AstPast(fl, exprp, nullptr);
         past->dtypeFrom(exprp);
         exprp = new AstEq(fl, past, exprp->cloneTree(false));
         exprp->dtypeSetBit();
@@ -217,14 +217,14 @@ private:
         if (nodep->sentreep()) return;  // Already processed
 
         FileLine* const fl = nodep->fileline();
-        AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
-        AstNode* lhsp = nodep->lhsp()->unlinkFrBack();
+        AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* lhsp = nodep->lhsp()->unlinkFrBack();
 
         if (m_disablep) lhsp = new AstAnd(fl, new AstNot(fl, m_disablep), lhsp);
 
-        AstNode* const past = new AstPast(fl, lhsp, nullptr);
+        AstNodeExpr* const past = new AstPast(fl, lhsp, nullptr);
         past->dtypeFrom(lhsp);
-        AstNode* const exprp = new AstOr(fl, new AstNot(fl, past), rhsp);
+        AstNodeExpr* const exprp = new AstOr(fl, new AstNot(fl, past), rhsp);
         exprp->dtypeSetBit();
         nodep->replaceWith(exprp);
         nodep->sentreep(newSenTree(nodep));
@@ -238,8 +238,8 @@ private:
         if (m_senip)
             nodep->v3warn(E_UNSUPPORTED, "Unsupported: Only one PSL clock allowed per assertion");
         // Block is the new expression to evaluate
-        AstNode* blockp = nodep->propp()->unlinkFrBack();
-        if (AstNode* const disablep = nodep->disablep()) {
+        AstNodeExpr* blockp = VN_AS(nodep->propp()->unlinkFrBack(), NodeExpr);
+        if (AstNodeExpr* const disablep = nodep->disablep()) {
             m_disablep = disablep->cloneTree(false);
             if (VN_IS(nodep->backp(), Cover)) {
                 blockp = new AstAnd(disablep->fileline(),
diff --git a/src/V3Ast.h b/src/V3Ast.h
index 778b8f252..486daa879 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -1877,8 +1877,8 @@ public:
     void addNextHere(AstNode* newp);  // Insert newp at this->nextp
     void addHereThisAsNext(AstNode* newp);  // Adds at old place of this, this becomes next
     void replaceWith(AstNode* newp);  // Replace current node in tree with new node
-    AstNode* unlinkFrBack(VNRelinker* linkerp
-                          = nullptr);  // Unlink this from whoever points to it.
+    // Unlink this from whoever points to it.
+    AstNode* unlinkFrBack(VNRelinker* linkerp = nullptr);
     // Unlink this from whoever points to it, keep entire next list with unlinked node
     AstNode* unlinkFrBackWithNext(VNRelinker* linkerp = nullptr);
     void swapWith(AstNode* bp);
diff --git a/src/V3AstInlines.h b/src/V3AstInlines.h
index 3793225c0..c4f574412 100644
--- a/src/V3AstInlines.h
+++ b/src/V3AstInlines.h
@@ -130,7 +130,7 @@ bool AstBasicDType::littleEndian() const {
 bool AstActive::hasClocked() const { return m_sensesp->hasClocked(); }
 bool AstActive::hasCombo() const { return m_sensesp->hasCombo(); }
 
-AstElabDisplay::AstElabDisplay(FileLine* fl, VDisplayType dispType, AstNode* exprsp)
+AstElabDisplay::AstElabDisplay(FileLine* fl, VDisplayType dispType, AstNodeExpr* exprsp)
     : ASTGEN_SUPER_ElabDisplay(fl) {
     addFmtp(new AstSFormatF{fl, AstSFormatF::NoFormat(), exprsp});
     m_displayType = dispType;
diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h
index 8bb23b9f1..2e76588bd 100644
--- a/src/V3AstNodeDType.h
+++ b/src/V3AstNodeDType.h
@@ -261,13 +261,13 @@ public:
 // === AstNode ===
 class AstEnumItem final : public AstNode {
     // @astgen op1 := rangep : Optional[AstRange] // Range for name appending
-    // @astgen op2 := valuep : Optional[AstNode]
+    // @astgen op2 := valuep : Optional[AstNodeExpr]
 private:
     string m_name;
 
 public:
     // Parents: ENUM
-    AstEnumItem(FileLine* fl, const string& name, AstRange* rangep, AstNode* valuep)
+    AstEnumItem(FileLine* fl, const string& name, AstRange* rangep, AstNodeExpr* valuep)
         : ASTGEN_SUPER_EnumItem(fl)
         , m_name{name} {
         this->rangep(rangep);
@@ -972,18 +972,18 @@ public:
 class AstQueueDType final : public AstNodeDType {
     // Queue array data type, ie "[ $ ]"
     // @astgen op1 := childDTypep : Optional[AstNodeDType] // moved to refDTypep() in V3Width
-    // @astgen op2 := boundp : Optional[AstNode]
+    // @astgen op2 := boundp : Optional[AstNodeExpr]
 private:
     AstNodeDType* m_refDTypep = nullptr;  // Elements of this type (after widthing)
 public:
-    AstQueueDType(FileLine* fl, VFlagChildDType, AstNodeDType* dtp, AstNode* boundp)
+    AstQueueDType(FileLine* fl, VFlagChildDType, AstNodeDType* dtp, AstNodeExpr* boundp)
         : ASTGEN_SUPER_QueueDType(fl) {
         this->childDTypep(dtp);
         this->boundp(boundp);
         refDTypep(nullptr);
         dtypep(nullptr);  // V3Width will resolve
     }
-    AstQueueDType(FileLine* fl, AstNodeDType* dtp, AstNode* boundp)
+    AstQueueDType(FileLine* fl, AstNodeDType* dtp, AstNodeExpr* boundp)
         : ASTGEN_SUPER_QueueDType(fl) {
         this->boundp(boundp);
         refDTypep(dtp);
@@ -1032,7 +1032,7 @@ public:
 };
 class AstRefDType final : public AstNodeDType {
     // @astgen op1 := typeofp : Optional[AstNode]
-    // @astgen op2 := classOrPackageOpp : Optional[AstNode]
+    // @astgen op2 := classOrPackageOpp : Optional[AstNodeExpr]
     // @astgen op3 := paramsp : List[AstPin]
 private:
     // Pre-Width must reference the Typeref, not what it points to, as some child
@@ -1046,7 +1046,7 @@ public:
     AstRefDType(FileLine* fl, const string& name)
         : ASTGEN_SUPER_RefDType(fl)
         , m_name{name} {}
-    AstRefDType(FileLine* fl, const string& name, AstNode* classOrPackagep, AstPin* paramsp)
+    AstRefDType(FileLine* fl, const string& name, AstNodeExpr* classOrPackagep, AstPin* paramsp)
         : ASTGEN_SUPER_RefDType(fl)
         , m_name{name} {
         this->classOrPackageOpp(classOrPackagep);
diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index b44af081a..ab1fad6e5 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -6,10 +6,9 @@
 //
 //*************************************************************************
 //
-// Copyright 2003-2022 by Wilson Snyder. This program is free software; you
-// can redistribute it and/or modify it under the terms of either the GNU
-// Lesser General Public License Version 3 or the Perl Artistic License
-// Version 2.0.
+// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU Lesser
+// General Public License Version 3 or the Perl Artistic License Version 2.0.
 // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //*************************************************************************
@@ -18,6 +17,16 @@
 // i.e.: those constructs that represent, or evaluate to [a possible void]
 // value. The root of the hierarchy is 'AstNodeExpr'.
 //
+// Think of expressions in a very general sense as constructs that "name
+// things". The "thing" can be considered the value, but can be highly
+// structured. For example, an AstConst can name the value '1', which is
+// hopefully familiar. On the opposite end of the spectrum of "things" named by
+// expressions, consider AstClassOrPackageRef, that can name a collection of
+// pairs (specifically the collection of ('member name', 'member thing')
+// pairs). Nevertheless, that collection itself can be considered a value. The
+// valid composition of expressions then defines the calculus of values in the
+// language.
+//
 //*************************************************************************
 
 #ifndef VERILATOR_V3ASTNODEEXPR_H_
@@ -41,7 +50,8 @@ public:
     ASTGEN_MEMBERS_AstNodeExpr;
     // METHODS
     void dump(std::ostream& str) const override;
-    bool hasDType() const final override { return true; }
+    // TODO: The only AstNodeExpr without dtype is AstArg. Otherwise this could be final.
+    bool hasDType() const override { return true; }
     virtual string emitVerilog() = 0;  /// Format string for verilog writing; see V3EmitV
     // For documentation on emitC format see EmitCFunc::emitOpName
     virtual string emitC() = 0;
@@ -57,10 +67,10 @@ public:
 };
 class AstNodeBiop VL_NOT_FINAL : public AstNodeExpr {
     // Binary expression
-    // @astgen op1 := lhsp : AstNode
-    // @astgen op2 := rhsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
+    // @astgen op2 := rhsp : AstNodeExpr
 protected:
-    AstNodeBiop(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstNodeBiop(VNType t, FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : AstNodeExpr{t, fl} {
         this->lhsp(lhsp);
         this->rhsp(rhsp);
@@ -69,7 +79,7 @@ protected:
 public:
     ASTGEN_MEMBERS_AstNodeBiop;
     // Clone single node, just get same type back.
-    virtual AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) = 0;
+    virtual AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) = 0;
     // METHODS
     // Set out to evaluation of a AstConst'ed
     virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) = 0;
@@ -87,7 +97,7 @@ public:
 class AstNodeBiCom VL_NOT_FINAL : public AstNodeBiop {
     // Binary expr with commutative properties
 protected:
-    AstNodeBiCom(VNType t, FileLine* fl, AstNode* lhs, AstNode* rhs)
+    AstNodeBiCom(VNType t, FileLine* fl, AstNodeExpr* lhs, AstNodeExpr* rhs)
         : AstNodeBiop{t, fl, lhs, rhs} {}
 
 public:
@@ -96,7 +106,7 @@ public:
 class AstNodeBiComAsv VL_NOT_FINAL : public AstNodeBiCom {
     // Binary expr with commutative & associative properties
 protected:
-    AstNodeBiComAsv(VNType t, FileLine* fl, AstNode* lhs, AstNode* rhs)
+    AstNodeBiComAsv(VNType t, FileLine* fl, AstNodeExpr* lhs, AstNodeExpr* rhs)
         : AstNodeBiCom{t, fl, lhs, rhs} {}
 
 public:
@@ -107,7 +117,7 @@ class AstNodeSel VL_NOT_FINAL : public AstNodeBiop {
     // @astgen alias op1 := fromp // Expression we are indexing into
     // @astgen alias op2 := bitp // The index // TOOD: rename to idxp
 protected:
-    AstNodeSel(VNType t, FileLine* fl, AstNode* fromp, AstNode* bitp)
+    AstNodeSel(VNType t, FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* bitp)
         : AstNodeBiop{t, fl, fromp, bitp} {}
 
 public:
@@ -117,7 +127,7 @@ public:
 class AstNodeStream VL_NOT_FINAL : public AstNodeBiop {
     // Verilog {rhs{lhs}} - Note rhsp() is the slice size, not the lhsp()
 protected:
-    AstNodeStream(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstNodeStream(VNType t, FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : AstNodeBiop{t, fl, lhsp, rhsp} {
         if (lhsp->dtypep()) dtypeSetLogicSized(lhsp->dtypep()->width(), VSigning::UNSIGNED);
     }
@@ -127,7 +137,7 @@ public:
 };
 class AstNodeSystemBiop VL_NOT_FINAL : public AstNodeBiop {
 public:
-    AstNodeSystemBiop(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstNodeSystemBiop(VNType t, FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : AstNodeBiop(t, fl, lhsp, rhsp) {
         dtypeSetDouble();
     }
@@ -142,12 +152,12 @@ public:
 };
 class AstNodeCCall VL_NOT_FINAL : public AstNodeExpr {
     // A call of a C++ function, perhaps a AstCFunc or perhaps globally named
-    // @astgen op2 := argsp : List[AstNode] // Note: op1 used by some sub-types only
+    // @astgen op2 := argsp : List[AstNodeExpr] // Note: op1 used by some sub-types only
     AstCFunc* m_funcp;
     string m_argTypes;
 
 protected:
-    AstNodeCCall(VNType t, FileLine* fl, AstCFunc* funcp, AstNode* argsp = nullptr)
+    AstNodeCCall(VNType t, FileLine* fl, AstCFunc* funcp, AstNodeExpr* argsp = nullptr)
         : AstNodeExpr{t, fl}
         , m_funcp{funcp} {
         addArgsp(argsp);
@@ -180,7 +190,7 @@ class AstNodeFTaskRef VL_NOT_FINAL : public AstNodeExpr {
     // A reference to a task (or function)
     // @astgen op1 := namep : Optional[AstNode]
     // op2 used by some sub-types only
-    // @astgen op3 := pinsp : List[AstNode]
+    // @astgen op3 := pinsp : List[AstNodeExpr]
     // @astgen op4 := scopeNamep : Optional[AstScopeName]
     AstNodeFTask* m_taskp = nullptr;  // [AfterLink] Pointer to task referenced
     AstNodeModule* m_classOrPackagep = nullptr;  // Package hierarchy
@@ -189,12 +199,12 @@ class AstNodeFTaskRef VL_NOT_FINAL : public AstNodeExpr {
     string m_inlinedDots;  // Dotted hierarchy flattened out
     bool m_pli = false;  // Pli system call ($name)
 protected:
-    AstNodeFTaskRef(VNType t, FileLine* fl, AstNode* namep, AstNode* pinsp)
+    AstNodeFTaskRef(VNType t, FileLine* fl, AstNode* namep, AstNodeExpr* pinsp)
         : AstNodeExpr{t, fl} {
         this->namep(namep);
         this->addPinsp(pinsp);
     }
-    AstNodeFTaskRef(VNType t, FileLine* fl, const string& name, AstNode* pinsp)
+    AstNodeFTaskRef(VNType t, FileLine* fl, const string& name, AstNodeExpr* pinsp)
         : AstNodeExpr{t, fl}
         , m_name{name} {
         this->addPinsp(pinsp);
@@ -225,12 +235,12 @@ public:
 };
 class AstNodePreSel VL_NOT_FINAL : public AstNodeExpr {
     // Something that becomes an AstSel
-    // @astgen op1 := fromp : AstNode
-    // @astgen op2 := rhsp : AstNode
-    // @astgen op3 := thsp : Optional[AstNode]
+    // @astgen op1 := fromp : AstNodeExpr
+    // @astgen op2 := rhsp : AstNodeExpr
+    // @astgen op3 := thsp : Optional[AstNodeExpr]
     // @astgen op4 := attrp : Optional[AstAttrOf]
 protected:
-    AstNodePreSel(VNType t, FileLine* fl, AstNode* fromp, AstNode* rhsp, AstNode* thsp)
+    AstNodePreSel(VNType t, FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* rhsp, AstNodeExpr* thsp)
         : AstNodeExpr{t, fl} {
         this->fromp(fromp);
         this->rhsp(rhsp);
@@ -248,13 +258,13 @@ public:
 };
 class AstNodeQuadop VL_NOT_FINAL : public AstNodeExpr {
     // 4-ary expression
-    // @astgen op1 := lhsp : AstNode
-    // @astgen op2 := rhsp : AstNode
-    // @astgen op3 := thsp : AstNode
-    // @astgen op4 := fhsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
+    // @astgen op2 := rhsp : AstNodeExpr
+    // @astgen op3 := thsp : AstNodeExpr
+    // @astgen op4 := fhsp : AstNodeExpr
 protected:
-    AstNodeQuadop(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* thsp,
-                  AstNode* fhsp)
+    AstNodeQuadop(VNType t, FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, AstNodeExpr* thsp,
+                  AstNodeExpr* fhsp)
         : AstNodeExpr{t, fl} {
         this->lhsp(lhsp);
         this->rhsp(rhsp);
@@ -295,11 +305,11 @@ public:
 };
 class AstNodeTriop VL_NOT_FINAL : public AstNodeExpr {
     // Ternary expression
-    // @astgen op1 := lhsp : AstNode
-    // @astgen op2 := rhsp : AstNode
-    // @astgen op3 := thsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
+    // @astgen op2 := rhsp : AstNodeExpr
+    // @astgen op3 := thsp : AstNodeExpr
 protected:
-    AstNodeTriop(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* thsp)
+    AstNodeTriop(VNType t, FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, AstNodeExpr* thsp)
         : AstNodeExpr{t, fl} {
         this->lhsp(lhsp);
         this->rhsp(rhsp);
@@ -328,7 +338,7 @@ class AstNodeCond VL_NOT_FINAL : public AstNodeTriop {
     // @astgen alias op2 := thenp
     // @astgen alias op3 := elsep
 protected:
-    AstNodeCond(VNType t, FileLine* fl, AstNode* condp, AstNode* thenp, AstNode* elsep)
+    AstNodeCond(VNType t, FileLine* fl, AstNodeExpr* condp, AstNodeExpr* thenp, AstNodeExpr* elsep)
         : AstNodeTriop{t, fl, condp, thenp, elsep} {
         if (thenp) {
             dtypeFrom(thenp);
@@ -351,13 +361,13 @@ public:
     bool sizeMattersRhs() const override { return false; }
     bool sizeMattersThs() const override { return false; }
     int instrCount() const override { return INSTR_COUNT_BRANCH; }
-    virtual AstNode* cloneType(AstNode* condp, AstNode* thenp, AstNode* elsep) = 0;
+    virtual AstNodeExpr* cloneType(AstNodeExpr* condp, AstNodeExpr* thenp, AstNodeExpr* elsep) = 0;
 };
 class AstNodeUniop VL_NOT_FINAL : public AstNodeExpr {
     // Unary expression
-    // @astgen op1 := lhsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
 protected:
-    AstNodeUniop(VNType t, FileLine* fl, AstNode* lhsp)
+    AstNodeUniop(VNType t, FileLine* fl, AstNodeExpr* lhsp)
         : AstNodeExpr{t, fl} {
         dtypeFrom(lhsp);
         this->lhsp(lhsp);
@@ -380,7 +390,7 @@ public:
 };
 class AstNodeSystemUniop VL_NOT_FINAL : public AstNodeUniop {
 public:
-    AstNodeSystemUniop(VNType t, FileLine* fl, AstNode* lhsp)
+    AstNodeSystemUniop(VNType t, FileLine* fl, AstNodeExpr* lhsp)
         : AstNodeUniop(t, fl, lhsp) {
         dtypeSetDouble();
     }
@@ -465,13 +475,36 @@ public:
     bool cleanOut() const override { return true; }
     AstCFunc* funcp() const { return m_funcp; }
 };
+class AstArg final : public AstNodeExpr {
+    // An argument to a function/task, which is either an expression, or is a placeholder for an
+    // omitted argument.
+    // TODO: AstArg should not be AstNodeExpr, but is currently used as such widely. Fix later.
+    // @astgen op1 := exprp : Optional[AstNodeExpr] // nullptr if omitted
+    string m_name;  // Pin name, or "" for number based interconnect
+public:
+    AstArg(FileLine* fl, const string& name, AstNodeExpr* exprp)
+        : ASTGEN_SUPER_Arg(fl)
+        , m_name{name} {
+        this->exprp(exprp);
+    }
+    ASTGEN_MEMBERS_AstArg;
+    bool hasDType() const override { return false; }
+    string name() const override { return m_name; }  // * = Pin name, ""=go by number
+    void name(const string& name) override { m_name = name; }
+    bool emptyConnectNoNext() const { return !exprp() && name() == "" && !nextp(); }
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
 class AstAttrOf final : public AstNodeExpr {
     // Return a value of a attribute, for example a LSB or array LSB of a signal
-    // @astgen op1 := fromp : Optional[AstNode]
-    // @astgen op2 := dimp : Optional[AstNode]
+    // @astgen op1 := fromp : Optional[AstNode] // Expr or DType
+    // @astgen op2 := dimp : Optional[AstNodeExpr]
     VAttrType m_attrType;  // What sort of extraction
 public:
-    AstAttrOf(FileLine* fl, VAttrType attrtype, AstNode* fromp = nullptr, AstNode* dimp = nullptr)
+    AstAttrOf(FileLine* fl, VAttrType attrtype, AstNode* fromp = nullptr,
+              AstNodeExpr* dimp = nullptr)
         : ASTGEN_SUPER_AttrOf(fl) {
         this->fromp(fromp);
         this->dimp(dimp);
@@ -512,13 +545,13 @@ public:
 class AstCMethodHard final : public AstNodeExpr {
     // A reference to a "C" hardcoded member task (or function)
     // PARENTS: stmt/expr
-    // @astgen op1 := fromp : AstNode // Subject of method call
-    // @astgen op2 := pinsp : List[AstNode] // Arguments
+    // @astgen op1 := fromp : AstNodeExpr // Subject of method call
+    // @astgen op2 := pinsp : List[AstNodeExpr] // Arguments
     string m_name;  // Name of method
     bool m_pure = false;  // Pure optimizable
 public:
-    AstCMethodHard(FileLine* fl, AstNode* fromp, VFlagChildDType, const string& name,
-                   AstNode* pinsp = nullptr)
+    AstCMethodHard(FileLine* fl, AstNodeExpr* fromp, VFlagChildDType, const string& name,
+                   AstNodeExpr* pinsp = nullptr)
         : ASTGEN_SUPER_CMethodHard(fl)
         , m_name{name} {
         // TODO: this constructor is exactly the same as the other, bar the ignored tag argument
@@ -526,7 +559,8 @@ public:
         this->addPinsp(pinsp);
         dtypep(nullptr);  // V3Width will resolve
     }
-    AstCMethodHard(FileLine* fl, AstNode* fromp, const string& name, AstNode* pinsp = nullptr)
+    AstCMethodHard(FileLine* fl, AstNodeExpr* fromp, const string& name,
+                   AstNodeExpr* pinsp = nullptr)
         : ASTGEN_SUPER_CMethodHard(fl)
         , m_name{name} {
         this->fromp(fromp);
@@ -548,16 +582,16 @@ public:
 };
 class AstCast final : public AstNodeExpr {
     // Cast to appropriate data type
-    // @astgen op1 := fromp : AstNode
+    // @astgen op1 := fromp : AstNodeExpr
     // @astgen op2 := childDTypep : Optional[AstNodeDType]
 public:
-    AstCast(FileLine* fl, AstNode* fromp, VFlagChildDType, AstNodeDType* dtp)
+    AstCast(FileLine* fl, AstNodeExpr* fromp, VFlagChildDType, AstNodeDType* dtp)
         : ASTGEN_SUPER_Cast(fl) {
         this->fromp(fromp);
         this->childDTypep(dtp);
         dtypeFrom(dtp);
     }
-    AstCast(FileLine* fl, AstNode* fromp, AstNodeDType* dtp)
+    AstCast(FileLine* fl, AstNodeExpr* fromp, AstNodeDType* dtp)
         : ASTGEN_SUPER_Cast(fl) {
         this->fromp(fromp);
         dtypeFrom(dtp);
@@ -571,10 +605,10 @@ public:
 };
 class AstCastParse final : public AstNodeExpr {
     // Cast to appropriate type, where we haven't determined yet what the data type is
-    // @astgen op1 := lhsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
     // @astgen op2 := dtp : AstNode
 public:
-    AstCastParse(FileLine* fl, AstNode* lhsp, AstNode* dtp)
+    AstCastParse(FileLine* fl, AstNodeExpr* lhsp, AstNode* dtp)
         : ASTGEN_SUPER_CastParse(fl) {
         this->lhsp(lhsp);
         this->dtp(dtp);
@@ -584,6 +618,102 @@ public:
     string emitC() override { V3ERROR_NA_RETURN(""); }
     bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
 };
+class AstCastSize final : public AstNodeExpr {
+    // Cast to specific size; signed/twostate inherited from lower element per IEEE
+    // @astgen op1 := lhsp : AstNodeExpr
+    // @astgen op2 := rhsp : AstConst
+public:
+    AstCastSize(FileLine* fl, AstNodeExpr* lhsp, AstConst* rhsp)
+        : ASTGEN_SUPER_CastSize(fl) {
+        this->lhsp(lhsp);
+        this->rhsp(rhsp);
+    }
+    ASTGEN_MEMBERS_AstCastSize;
+    // No hasDType because widthing removes this node before the hasDType check
+    string emitVerilog() override { return "((%r)'(%l))"; }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
+class AstCellArrayRef final : public AstNodeExpr {
+    // As-of-yet unlinkable reference into an array of cells
+    // @astgen op1 := selp : List[AstNodeExpr] // Select expression
+    string m_name;  // Array name
+public:
+    AstCellArrayRef(FileLine* fl, const string& name, AstNodeExpr* selp)
+        : ASTGEN_SUPER_CellArrayRef(fl)
+        , m_name{name} {
+        this->addSelp(selp);
+    }
+    ASTGEN_MEMBERS_AstCellArrayRef;
+    // ACCESSORS
+    string name() const override { return m_name; }  // * = Array name
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
+class AstCellRef final : public AstNodeExpr {
+    // As-of-yet unlinkable reference into a cell
+    // @astgen op1 := cellp : AstNode
+    // @astgen op2 := exprp : AstNodeExpr
+private:
+    string m_name;  // Cell name
+public:
+    AstCellRef(FileLine* fl, const string& name, AstNode* cellp, AstNodeExpr* exprp)
+        : ASTGEN_SUPER_CellRef(fl)
+        , m_name{name} {
+        this->cellp(cellp);
+        this->exprp(exprp);
+    }
+    ASTGEN_MEMBERS_AstCellRef;
+    // ACCESSORS
+    string name() const override { return m_name; }  // * = Array name
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
+class AstClassOrPackageRef final : public AstNodeExpr {
+    // @astgen op1 := paramsp : List[AstPin]
+private:
+    string m_name;
+    // Node not NodeModule to appease some early parser usage
+    AstNode* m_classOrPackageNodep;  // Package hierarchy
+public:
+    AstClassOrPackageRef(FileLine* fl, const string& name, AstNode* classOrPackageNodep,
+                         AstPin* paramsp)
+        : ASTGEN_SUPER_ClassOrPackageRef(fl)
+        , m_name{name}
+        , m_classOrPackageNodep{classOrPackageNodep} {
+        this->addParamsp(paramsp);
+    }
+    ASTGEN_MEMBERS_AstClassOrPackageRef;
+    // METHODS
+    const char* broken() const override {
+        BROKEN_RTN(m_classOrPackageNodep && !m_classOrPackageNodep->brokeExists());
+        return nullptr;
+    }
+    void cloneRelink() override {
+        if (m_classOrPackageNodep && m_classOrPackageNodep->clonep()) {
+            m_classOrPackageNodep = m_classOrPackageNodep->clonep();
+        }
+    }
+    bool same(const AstNode* samep) const override {
+        return (m_classOrPackageNodep
+                == static_cast<const AstClassOrPackageRef*>(samep)->m_classOrPackageNodep);
+    }
+    void dump(std::ostream& str = std::cout) const override;
+    string name() const override { return m_name; }  // * = Var name
+    AstNode* classOrPackageNodep() const { return m_classOrPackageNodep; }
+    void classOrPackageNodep(AstNode* nodep) { m_classOrPackageNodep = nodep; }
+    AstNodeModule* classOrPackagep() const;
+    AstPackage* packagep() const { return VN_CAST(classOrPackageNodep(), Package); }
+    void classOrPackagep(AstNodeModule* nodep) { m_classOrPackageNodep = (AstNode*)nodep; }
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
 class AstConsAssoc final : public AstNodeExpr {
     // Construct an assoc array and return object, '{}
     // @astgen op1 := defaultp : Optional[AstNode]
@@ -788,11 +918,11 @@ public:
 class AstDot final : public AstNodeExpr {
     // A dot separating paths in an AstVarXRef, AstFuncRef or AstTaskRef
     // These are eliminated in the link stage
-    // @astgen op1 := lhsp : AstNode
-    // @astgen op2 := rhsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
+    // @astgen op2 := rhsp : AstNodeExpr
     const bool m_colon;  // Is a "::" instead of a "." (lhs must be package/class)
 public:
-    AstDot(FileLine* fl, bool colon, AstNode* lhsp, AstNode* rhsp)
+    AstDot(FileLine* fl, bool colon, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Dot(fl)
         , m_colon{colon} {
         this->lhsp(lhsp);
@@ -800,7 +930,7 @@ public:
     }
     ASTGEN_MEMBERS_AstDot;
     // For parser, make only if non-null package
-    static AstNodeExpr* newIfPkg(FileLine* fl, AstNode* packageOrClassp, AstNodeExpr* rhsp) {
+    static AstNodeExpr* newIfPkg(FileLine* fl, AstNodeExpr* packageOrClassp, AstNodeExpr* rhsp) {
         if (!packageOrClassp) return rhsp;
         return new AstDot{fl, true, packageOrClassp, rhsp};
     }
@@ -855,9 +985,9 @@ class AstExprStmt final : public AstNodeExpr {
     // the parent gets passed the 'resultp()'.
     // resultp is evaluated AFTER the statement(s).
     // @astgen op1 := stmtsp : List[AstNode]
-    // @astgen op2 := resultp : AstNode
+    // @astgen op2 := resultp : AstNodeExpr
 public:
-    AstExprStmt(FileLine* fl, AstNode* stmtsp, AstNode* resultp)
+    AstExprStmt(FileLine* fl, AstNode* stmtsp, AstNodeExpr* resultp)
         : ASTGEN_SUPER_ExprStmt(fl) {
         addStmtsp(stmtsp);
         this->resultp(resultp);
@@ -1001,10 +1131,10 @@ public:
 };
 class AstFell final : public AstNodeExpr {
     // Verilog $fell
-    // @astgen op1 := exprp : AstNode
+    // @astgen op1 := exprp : AstNodeExpr
     // @astgen op2 := sentreep : Optional[AstSenTree]
 public:
-    AstFell(FileLine* fl, AstNode* exprp)
+    AstFell(FileLine* fl, AstNodeExpr* exprp)
         : ASTGEN_SUPER_Fell(fl) {
         this->exprp(exprp);
     }
@@ -1018,10 +1148,10 @@ public:
 };
 class AstGatePin final : public AstNodeExpr {
     // Possibly expand a gate primitive input pin value to match the range of the gate primitive
-    // @astgen op1 := exprp : AstNode // Pin expression
+    // @astgen op1 := exprp : AstNodeExpr // Pin expression
     // @astgen op2 := rangep : AstRange // Range of pin
 public:
-    AstGatePin(FileLine* fl, AstNode* exprp, AstRange* rangep)
+    AstGatePin(FileLine* fl, AstNodeExpr* exprp, AstRange* rangep)
         : ASTGEN_SUPER_GatePin(fl) {
         this->exprp(exprp);
         this->rangep(rangep);
@@ -1033,11 +1163,11 @@ public:
 };
 class AstImplication final : public AstNodeExpr {
     // Verilog |-> |=>
-    // @astgen op1 := lhsp : AstNode
-    // @astgen op2 := rhsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
+    // @astgen op2 := rhsp : AstNodeExpr
     // @astgen op3 := sentreep : Optional[AstSenTree]
 public:
-    AstImplication(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstImplication(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Implication(fl) {
         this->lhsp(lhsp);
         this->rhsp(rhsp);
@@ -1050,11 +1180,51 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
-class AstInside final : public AstNodeExpr {
-    // @astgen op1 := exprp : AstNode
-    // @astgen op2 := itemsp : List[AstNode]
+class AstInitArray final : public AstNodeExpr {
+    // This is also used as an array value in V3Simulate/const prop.
+    // Would be better called as 'AstConstArray'
+    // Set a var to a map of values
+    // The list of initsp() is not relevant
+    // If default is specified, the vector may be sparse, and not provide each value.
+    // Key values are C++ array style, with lo() at index 0
+    // Parents: ASTVAR::init()
+    // @astgen op1 := defaultp : Optional[AstNodeExpr] // Default, if sparse
+    // @astgen op2 := initsp : List[AstNode] // Initial value expressions
+    //
 public:
-    AstInside(FileLine* fl, AstNode* exprp, AstNode* itemsp)
+    using KeyItemMap = std::map<uint64_t, AstInitItem*>;
+
+private:
+    KeyItemMap m_map;  // Node value for each array index
+public:
+    AstInitArray(FileLine* fl, AstNodeDType* newDTypep, AstNodeExpr* defaultp)
+        : ASTGEN_SUPER_InitArray(fl) {
+        dtypep(newDTypep);
+        this->defaultp(defaultp);
+    }
+    ASTGEN_MEMBERS_AstInitArray;
+    void dump(std::ostream& str) const override;
+    const char* broken() const override;
+    void cloneRelink() override;
+    bool same(const AstNode* samep) const override {
+        // Only works if exact same children, instead should override comparison
+        // of children list, and instead use map-vs-map key/value compare
+        return m_map == static_cast<const AstInitArray*>(samep)->m_map;
+    }
+    void addValuep(AstNodeExpr* newp) { addIndexValuep(m_map.size(), newp); }
+    const KeyItemMap& map() const { return m_map; }
+    void addIndexValuep(uint64_t index, AstNodeExpr* newp);
+    AstNodeExpr* getIndexValuep(uint64_t index) const;
+    AstNodeExpr* getIndexDefaultedValuep(uint64_t index) const;
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { return true; }
+};
+class AstInside final : public AstNodeExpr {
+    // @astgen op1 := exprp : AstNodeExpr
+    // @astgen op2 := itemsp : List[AstNodeExpr]
+public:
+    AstInside(FileLine* fl, AstNodeExpr* exprp, AstNodeExpr* itemsp)
         : ASTGEN_SUPER_Inside(fl) {
         this->exprp(exprp);
         this->addItemsp(itemsp);
@@ -1066,10 +1236,10 @@ public:
     bool cleanOut() const override { return false; }  // NA
 };
 class AstInsideRange final : public AstNodeExpr {
-    // @astgen op1 := lhsp : AstNode
-    // @astgen op2 := rhsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
+    // @astgen op2 := rhsp : AstNodeExpr
 public:
-    AstInsideRange(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstInsideRange(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_InsideRange(fl) {
         this->lhsp(lhsp);
         this->rhsp(rhsp);
@@ -1079,7 +1249,7 @@ public:
     string emitC() override { V3ERROR_NA_RETURN(""); }
     bool cleanOut() const override { return false; }  // NA
     // Create AstAnd(AstGte(...), AstLte(...))
-    AstNode* newAndFromInside(AstNode* exprp, AstNode* lhsp, AstNode* rhsp);
+    AstNodeExpr* newAndFromInside(AstNodeExpr* exprp, AstNodeExpr* lhsp, AstNodeExpr* rhsp);
 };
 class AstLambdaArgRef final : public AstNodeExpr {
     // Lambda argument usage
@@ -1104,18 +1274,18 @@ public:
     bool index() const { return m_index; }
 };
 class AstMemberSel final : public AstNodeExpr {
-    // @astgen op1 := fromp : AstNode
+    // @astgen op1 := fromp : AstNodeExpr
     // Don't need the class we are extracting from, as the "fromp()"'s datatype can get us to it
     string m_name;
     AstVar* m_varp = nullptr;  // Post link, variable within class that is target of selection
 public:
-    AstMemberSel(FileLine* fl, AstNode* fromp, VFlagChildDType, const string& name)
+    AstMemberSel(FileLine* fl, AstNodeExpr* fromp, VFlagChildDType, const string& name)
         : ASTGEN_SUPER_MemberSel(fl)
         , m_name{name} {
         this->fromp(fromp);
         dtypep(nullptr);  // V3Width will resolve
     }
-    AstMemberSel(FileLine* fl, AstNode* fromp, AstNodeDType* dtp)
+    AstMemberSel(FileLine* fl, AstNodeExpr* fromp, AstNodeDType* dtp)
         : ASTGEN_SUPER_MemberSel(fl)
         , m_name{dtp->name()} {
         this->fromp(fromp);
@@ -1136,9 +1306,9 @@ public:
 };
 class AstNewCopy final : public AstNodeExpr {
     // New as shallow copy
-    // @astgen op1 := rhsp : AstNode
+    // @astgen op1 := rhsp : AstNodeExpr
 public:
-    AstNewCopy(FileLine* fl, AstNode* rhsp)
+    AstNewCopy(FileLine* fl, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_NewCopy(fl) {
         dtypeFrom(rhsp);  // otherwise V3Width will resolve
         this->rhsp(rhsp);
@@ -1152,10 +1322,10 @@ public:
 };
 class AstNewDynamic final : public AstNodeExpr {
     // New for dynamic array
-    // @astgen op1 := sizep : AstNode
-    // @astgen op2 := rhsp : Optional[AstNode]
+    // @astgen op1 := sizep : AstNodeExpr
+    // @astgen op2 := rhsp : Optional[AstNodeExpr]
 public:
-    AstNewDynamic(FileLine* fl, AstNode* sizep, AstNode* rhsp)
+    AstNewDynamic(FileLine* fl, AstNodeExpr* sizep, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_NewDynamic(fl) {
         dtypeFrom(rhsp);  // otherwise V3Width will resolve
         this->sizep(sizep);
@@ -1204,11 +1374,11 @@ public:
 };
 class AstPast final : public AstNodeExpr {
     // Verilog $past
-    // @astgen op1 := exprp : AstNode
+    // @astgen op1 := exprp : AstNodeExpr
     // @astgen op2 := ticksp : Optional[AstNode]
     // @astgen op3 := sentreep : Optional[AstSenTree]
 public:
-    AstPast(FileLine* fl, AstNode* exprp, AstNode* ticksp)
+    AstPast(FileLine* fl, AstNodeExpr* exprp, AstNode* ticksp)
         : ASTGEN_SUPER_Past(fl) {
         this->exprp(exprp);
         this->ticksp(ticksp);
@@ -1226,13 +1396,13 @@ class AstPatMember final : public AstNodeExpr {
     // Parents: AstPattern
     // Children: expression, AstPattern, replication count
     // Expression to assign or another AstPattern (list if replicated)
-    // @astgen op1 := lhssp : List[AstNode]
+    // @astgen op1 := lhssp : List[AstNodeExpr]
     // @astgen op2 := keyp : Optional[AstNode]
-    // @astgen op3 := repp : Optional[AstNode]  // replication count, or nullptr for count 1
+    // @astgen op3 := repp : Optional[AstNodeExpr]  // replication count, or nullptr for count 1
     bool m_default = false;
 
 public:
-    AstPatMember(FileLine* fl, AstNode* lhssp, AstNode* keyp, AstNode* repp)
+    AstPatMember(FileLine* fl, AstNodeExpr* lhssp, AstNode* keyp, AstNodeExpr* repp)
         : ASTGEN_SUPER_PatMember(fl) {
         this->addLhssp(lhssp);
         this->keyp(keyp);
@@ -1312,10 +1482,10 @@ public:
 };
 class AstRose final : public AstNodeExpr {
     // Verilog $rose
-    // @astgen op1 := exprp : AstNode
+    // @astgen op1 := exprp : AstNodeExpr
     // @astgen op2 := sentreep : Optional[AstSenTree]
 public:
-    AstRose(FileLine* fl, AstNode* exprp)
+    AstRose(FileLine* fl, AstNodeExpr* exprp)
         : ASTGEN_SUPER_Rose(fl) {
         this->exprp(exprp);
     }
@@ -1330,7 +1500,7 @@ public:
 class AstSFormatF final : public AstNodeExpr {
     // Convert format to string, generally under an AstDisplay or AstSFormat
     // Also used as "real" function for /*verilator sformat*/ functions
-    // @astgen op1 := exprsp : List[AstNode]
+    // @astgen op1 := exprsp : List[AstNodeExpr]
     // @astgen op2 := scopeNamep : Optional[AstScopeName]
     string m_text;
     const bool m_hidden;  // Under display, etc
@@ -1339,7 +1509,7 @@ class AstSFormatF final : public AstNodeExpr {
     VTimescale m_timeunit;  // Parent module time unit
 public:
     class NoFormat {};
-    AstSFormatF(FileLine* fl, const string& text, bool hidden, AstNode* exprsp,
+    AstSFormatF(FileLine* fl, const string& text, bool hidden, AstNodeExpr* exprsp,
                 char missingArgChar = 'd')
         : ASTGEN_SUPER_SFormatF(fl)
         , m_text{text}
@@ -1349,7 +1519,7 @@ public:
         dtypeSetString();
         addExprsp(exprsp);
     }
-    AstSFormatF(FileLine* fl, NoFormat, AstNode* exprsp, char missingArgChar = 'd',
+    AstSFormatF(FileLine* fl, NoFormat, AstNodeExpr* exprsp, char missingArgChar = 'd',
                 bool hidden = true)
         : ASTGEN_SUPER_SFormatF(fl)
         , m_text{""}
@@ -1412,7 +1582,7 @@ public:
 };
 class AstSampled final : public AstNodeExpr {
     // Verilog $sampled
-    // @astgen op1 := exprp : AstNode
+    // @astgen op1 := exprp : AstNode // AstNodeExpr or AstPropSpec
 public:
     AstSampled(FileLine* fl, AstNode* exprp)
         : ASTGEN_SUPER_Sampled(fl) {
@@ -1468,13 +1638,33 @@ public:
     void dpiExport(bool flag) { m_dpiExport = flag; }
     bool forFormat() const { return m_forFormat; }
 };
+class AstSelLoopVars final : public AstNodeExpr {
+    // Parser only concept "[id, id, id]" for a foreach statement
+    // Unlike normal selects elements is a list
+    // TODO: Should not be an AstNodeExpr, model foreach better
+    // @astgen op1 := fromp : AstNodeExpr
+    // @astgen op2 := elementsp : List[AstNode]
+public:
+    AstSelLoopVars(FileLine* fl, AstNodeExpr* fromp, AstNode* elementsp)
+        : ASTGEN_SUPER_SelLoopVars(fl) {
+        this->fromp(fromp);
+        this->addElementsp(elementsp);
+    }
+    ASTGEN_MEMBERS_AstSelLoopVars;
+    bool same(const AstNode* /*samep*/) const override { return true; }
+    bool maybePointedTo() const override { return false; }
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
 class AstSetAssoc final : public AstNodeExpr {
     // Set an assoc array element and return object, '{}
     // @astgen op1 := lhsp : AstNode
     // @astgen op2 := keyp : Optional[AstNode]
-    // @astgen op3 := valuep : AstNode
+    // @astgen op3 := valuep : AstNodeExpr
 public:
-    AstSetAssoc(FileLine* fl, AstNode* lhsp, AstNode* keyp, AstNode* valuep)
+    AstSetAssoc(FileLine* fl, AstNode* lhsp, AstNode* keyp, AstNodeExpr* valuep)
         : ASTGEN_SUPER_SetAssoc(fl) {
         this->lhsp(lhsp);
         this->keyp(keyp);
@@ -1492,9 +1682,9 @@ class AstSetWildcard final : public AstNodeExpr {
     // Set a wildcard assoc array element and return object, '{}
     // @astgen op1 := lhsp : AstNode
     // @astgen op2 := keyp : Optional[AstNode]
-    // @astgen op3 := valuep : AstNode
+    // @astgen op3 := valuep : AstNodeExpr
 public:
-    AstSetWildcard(FileLine* fl, AstNode* lhsp, AstNode* keyp, AstNode* valuep)
+    AstSetWildcard(FileLine* fl, AstNode* lhsp, AstNode* keyp, AstNodeExpr* valuep)
         : ASTGEN_SUPER_SetWildcard(fl) {
         this->lhsp(lhsp);
         this->keyp(keyp);
@@ -1510,10 +1700,10 @@ public:
 };
 class AstStable final : public AstNodeExpr {
     // Verilog $stable
-    // @astgen op1 := exprp : AstNode
+    // @astgen op1 := exprp : AstNodeExpr
     // @astgen op2 := sentreep : Optional[AstSenTree]
 public:
-    AstStable(FileLine* fl, AstNode* exprp)
+    AstStable(FileLine* fl, AstNodeExpr* exprp)
         : ASTGEN_SUPER_Stable(fl) {
         this->exprp(exprp);
     }
@@ -1651,8 +1841,7 @@ public:
 };
 class AstUCFunc final : public AstNodeExpr {
     // User's $c function
-    // Perhaps this should be an AstNodeListop; but there's only one list math right now
-    // @astgen op1 := exprsp : List[AstNode] // Expressions to print
+    // @astgen op1 := exprsp : List[AstNode] // Expressions to print (some are AstText)
 public:
     AstUCFunc(FileLine* fl, AstNode* exprsp)
         : ASTGEN_SUPER_UCFunc(fl) {
@@ -1722,15 +1911,45 @@ public:
     bool cleanOut() const override { return true; }
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
+class AstWith final : public AstNodeExpr {
+    // Used as argument to method, then to AstCMethodHard
+    // dtypep() contains the with lambda's return dtype
+    // Parents: funcref (similar to AstArg)
+    // Children: LambdaArgRef that declares the item variable
+    // Children: LambdaArgRef that declares the item.index variable
+    // Children: expression (equation establishing the with)
+    // @astgen op1 := indexArgRefp : AstLambdaArgRef
+    // @astgen op2 := valueArgRefp : AstLambdaArgRef
+    // @astgen op3 := exprp : AstNodeExpr
+public:
+    AstWith(FileLine* fl, AstLambdaArgRef* indexArgRefp, AstLambdaArgRef* valueArgRefp,
+            AstNodeExpr* exprp)
+        : ASTGEN_SUPER_With(fl) {
+        this->indexArgRefp(indexArgRefp);
+        this->valueArgRefp(valueArgRefp);
+        this->exprp(exprp);
+    }
+    ASTGEN_MEMBERS_AstWith;
+    bool same(const AstNode* /*samep*/) const override { return true; }
+    const char* broken() const override {
+        BROKEN_RTN(!indexArgRefp());  // varp needed to know lambda's arg dtype
+        BROKEN_RTN(!valueArgRefp());  // varp needed to know lambda's arg dtype
+        return nullptr;
+    }
+
+    string emitVerilog() override { V3ERROR_NA_RETURN(""); }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { V3ERROR_NA_RETURN(true); }
+};
 class AstWithParse final : public AstNodeExpr {
     // In early parse, FUNC(index) WITH equation-using-index
     // Replaced with AstWith
     // Parents: expr|stmt
     // Children: funcref, expr
     // @astgen op1 := funcrefp : AstNode
-    // @astgen op2 := exprp : Optional[AstNode]
+    // @astgen op2 := exprp : Optional[AstNodeExpr]
 public:
-    AstWithParse(FileLine* fl, AstNode* funcrefp, AstNode* exprp)
+    AstWithParse(FileLine* fl, AstNode* funcrefp, AstNodeExpr* exprp)
         : ASTGEN_SUPER_WithParse(fl) {
         this->funcrefp(funcrefp);
         this->exprp(exprp);
@@ -1749,12 +1968,12 @@ class AstBufIf1 final : public AstNodeBiop {
     // Note unlike the Verilog bufif1() UDP, this allows any width; each lhsp
     // bit enables respective rhsp bit
 public:
-    AstBufIf1(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstBufIf1(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_BufIf1(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstBufIf1;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstBufIf1{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -1775,14 +1994,16 @@ class AstCastDynamic final : public AstNodeBiop {
     // lhsp() is value (we are converting FROM) to match AstCCast etc, this
     // is opposite of $cast's order, because the first access is to the
     // value reading from.  Suggest use fromp()/top() instead of lhsp/rhsp().
+    // @astgen alias op1 := fromp
+    // @astgen alias op2 := top
 public:
-    AstCastDynamic(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstCastDynamic(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_CastDynamic(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstCastDynamic;
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         V3ERROR_NA;
     }
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstCastDynamic{fileline(), lhsp, rhsp};
     }
     string emitVerilog() override { return "%f$cast(%r, %l)"; }
@@ -1794,20 +2015,18 @@ public:
     bool sizeMattersRhs() const override { return false; }
     int instrCount() const override { return widthInstrs() * 20; }
     bool isPure() const override { return true; }
-    AstNode* fromp() const { return lhsp(); }
-    AstNode* top() const { return rhsp(); }
 };
 class AstCompareNN final : public AstNodeBiop {
     // Verilog str.compare() and str.icompare()
     const bool m_ignoreCase;  // True for str.icompare()
 public:
-    AstCompareNN(FileLine* fl, AstNode* lhsp, AstNode* rhsp, bool ignoreCase)
+    AstCompareNN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, bool ignoreCase)
         : ASTGEN_SUPER_CompareNN(fl, lhsp, rhsp)
         , m_ignoreCase{ignoreCase} {
         dtypeSetUInt32();
     }
     ASTGEN_MEMBERS_AstCompareNN;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstCompareNN{fileline(), lhsp, rhsp, m_ignoreCase};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -1830,7 +2049,7 @@ public:
 class AstConcat final : public AstNodeBiop {
     // If you're looking for {#{}}, see AstReplicate
 public:
-    AstConcat(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstConcat(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Concat(fl, lhsp, rhsp) {
         if (lhsp->dtypep() && rhsp->dtypep()) {
             dtypeSetLogicSized(lhsp->dtypep()->width() + rhsp->dtypep()->width(),
@@ -1838,7 +2057,7 @@ public:
         }
     }
     ASTGEN_MEMBERS_AstConcat;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstConcat{fileline(), lhsp, rhsp};
     }
     string emitVerilog() override { return "%f{%l, %k%r}"; }
@@ -1856,12 +2075,12 @@ public:
 class AstConcatN final : public AstNodeBiop {
     // String concatenate
 public:
-    AstConcatN(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstConcatN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_ConcatN(fl, lhsp, rhsp) {
         dtypeSetString();
     }
     ASTGEN_MEMBERS_AstConcatN;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstConcatN{fileline(), lhsp, rhsp};
     }
     string emitVerilog() override { return "%f{%l, %k%r}"; }
@@ -1879,12 +2098,12 @@ public:
 };
 class AstDiv final : public AstNodeBiop {
 public:
-    AstDiv(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstDiv(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Div(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstDiv;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstDiv{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -1901,12 +2120,12 @@ public:
 };
 class AstDivD final : public AstNodeBiop {
 public:
-    AstDivD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstDivD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_DivD(fl, lhsp, rhsp) {
         dtypeSetDouble();
     }
     ASTGEN_MEMBERS_AstDivD;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstDivD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -1925,12 +2144,12 @@ public:
 };
 class AstDivS final : public AstNodeBiop {
 public:
-    AstDivS(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstDivS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_DivS(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstDivS;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstDivS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -1949,16 +2168,16 @@ public:
 class AstEqWild final : public AstNodeBiop {
     // Note wildcard operator rhs differs from lhs
 public:
-    AstEqWild(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstEqWild(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_EqWild(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstEqWild;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstEqWild{fileline(), lhsp, rhsp};
     }
-    static AstNodeBiop* newTyped(FileLine* fl, AstNode* lhsp,
-                                 AstNode* rhsp);  // Return AstEqWild/AstEqD
+    // Return AstEqWild/AstEqD
+    static AstNodeBiop* newTyped(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp);
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opWildEq(lhs, rhs);
     }
@@ -1973,10 +2192,10 @@ public:
 };
 class AstFGetS final : public AstNodeBiop {
 public:
-    AstFGetS(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstFGetS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_FGetS(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstFGetS;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstFGetS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -1998,13 +2217,13 @@ public:
 };
 class AstFUngetC final : public AstNodeBiop {
 public:
-    AstFUngetC(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstFUngetC(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_FUngetC(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstFUngetC;
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         V3ERROR_NA;
     }
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstFUngetC{fileline(), lhsp, rhsp};
     }
     string emitVerilog() override { return "%f$ungetc(%r, %l)"; }
@@ -2025,12 +2244,12 @@ public:
 class AstGetcN final : public AstNodeBiop {
     // Verilog string.getc()
 public:
-    AstGetcN(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstGetcN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_GetcN(fl, lhsp, rhsp) {
         dtypeSetBitSized(8, VSigning::UNSIGNED);
     }
     ASTGEN_MEMBERS_AstGetcN;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstGetcN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2050,12 +2269,12 @@ class AstGetcRefN final : public AstNodeBiop {
     // Verilog string[#] on the left-hand-side of assignment
     // Spec says is of type byte (not string of single character)
 public:
-    AstGetcRefN(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstGetcRefN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_GetcRefN(fl, lhsp, rhsp) {
         dtypeSetBitSized(8, VSigning::UNSIGNED);
     }
     ASTGEN_MEMBERS_AstGetcRefN;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstGetcRefN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2072,12 +2291,12 @@ public:
 };
 class AstGt final : public AstNodeBiop {
 public:
-    AstGt(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstGt(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Gt(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstGt;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstGt{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2094,12 +2313,12 @@ public:
 };
 class AstGtD final : public AstNodeBiop {
 public:
-    AstGtD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstGtD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_GtD(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstGtD;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstGtD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2118,12 +2337,12 @@ public:
 };
 class AstGtN final : public AstNodeBiop {
 public:
-    AstGtN(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstGtN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_GtN(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstGtN;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstGtN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2142,12 +2361,12 @@ public:
 };
 class AstGtS final : public AstNodeBiop {
 public:
-    AstGtS(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstGtS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_GtS(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstGtS;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstGtS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2165,12 +2384,12 @@ public:
 };
 class AstGte final : public AstNodeBiop {
 public:
-    AstGte(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstGte(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Gte(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstGte;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstGte{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2187,12 +2406,12 @@ public:
 };
 class AstGteD final : public AstNodeBiop {
 public:
-    AstGteD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstGteD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_GteD(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstGteD;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstGteD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2211,12 +2430,12 @@ public:
 };
 class AstGteN final : public AstNodeBiop {
 public:
-    AstGteN(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstGteN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_GteN(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstGteN;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstGteN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2235,12 +2454,12 @@ public:
 };
 class AstGteS final : public AstNodeBiop {
 public:
-    AstGteS(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstGteS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_GteS(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstGteS;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstGteS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2258,12 +2477,12 @@ public:
 };
 class AstLogAnd final : public AstNodeBiop {
 public:
-    AstLogAnd(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstLogAnd(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_LogAnd(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstLogAnd;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstLogAnd{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2281,12 +2500,12 @@ public:
 };
 class AstLogIf final : public AstNodeBiop {
 public:
-    AstLogIf(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstLogIf(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_LogIf(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstLogIf;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstLogIf{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2309,12 +2528,12 @@ class AstLogOr final : public AstNodeBiop {
     // versus V3Const tracking it itself
     bool m_sideEffect = false;  // Has side effect, relies on short-circuiting
 public:
-    AstLogOr(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstLogOr(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_LogOr(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstLogOr;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstLogOr{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2340,12 +2559,12 @@ public:
 };
 class AstLt final : public AstNodeBiop {
 public:
-    AstLt(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstLt(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Lt(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstLt;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstLt{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2362,12 +2581,12 @@ public:
 };
 class AstLtD final : public AstNodeBiop {
 public:
-    AstLtD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstLtD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_LtD(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstLtD;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstLtD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2386,12 +2605,12 @@ public:
 };
 class AstLtN final : public AstNodeBiop {
 public:
-    AstLtN(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstLtN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_LtN(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstLtN;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstLtN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2410,12 +2629,12 @@ public:
 };
 class AstLtS final : public AstNodeBiop {
 public:
-    AstLtS(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstLtS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_LtS(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstLtS;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstLtS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2433,12 +2652,12 @@ public:
 };
 class AstLte final : public AstNodeBiop {
 public:
-    AstLte(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstLte(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Lte(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstLte;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstLte{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2455,12 +2674,12 @@ public:
 };
 class AstLteD final : public AstNodeBiop {
 public:
-    AstLteD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstLteD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_LteD(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstLteD;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstLteD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2479,12 +2698,12 @@ public:
 };
 class AstLteN final : public AstNodeBiop {
 public:
-    AstLteN(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstLteN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_LteN(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstLteN;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstLteN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2503,12 +2722,12 @@ public:
 };
 class AstLteS final : public AstNodeBiop {
 public:
-    AstLteS(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstLteS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_LteS(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstLteS;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstLteS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2526,12 +2745,12 @@ public:
 };
 class AstModDiv final : public AstNodeBiop {
 public:
-    AstModDiv(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstModDiv(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_ModDiv(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstModDiv;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstModDiv{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2548,12 +2767,12 @@ public:
 };
 class AstModDivS final : public AstNodeBiop {
 public:
-    AstModDivS(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstModDivS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_ModDivS(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstModDivS;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstModDivS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2571,12 +2790,12 @@ public:
 };
 class AstNeqWild final : public AstNodeBiop {
 public:
-    AstNeqWild(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstNeqWild(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_NeqWild(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstNeqWild;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstNeqWild{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2593,12 +2812,12 @@ public:
 };
 class AstPow final : public AstNodeBiop {
 public:
-    AstPow(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstPow(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Pow(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstPow;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstPow{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2616,12 +2835,12 @@ public:
 };
 class AstPowD final : public AstNodeBiop {
 public:
-    AstPowD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstPowD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_PowD(fl, lhsp, rhsp) {
         dtypeSetDouble();
     }
     ASTGEN_MEMBERS_AstPowD;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstPowD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2639,12 +2858,12 @@ public:
 };
 class AstPowSS final : public AstNodeBiop {
 public:
-    AstPowSS(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstPowSS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_PowSS(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstPowSS;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstPowSS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2663,12 +2882,12 @@ public:
 };
 class AstPowSU final : public AstNodeBiop {
 public:
-    AstPowSU(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstPowSU(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_PowSU(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstPowSU;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstPowSU{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2687,12 +2906,12 @@ public:
 };
 class AstPowUS final : public AstNodeBiop {
 public:
-    AstPowUS(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstPowUS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_PowUS(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstPowUS;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstPowUS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2715,7 +2934,7 @@ class AstReplicate final : public AstNodeBiop {
     // @astgen alias op1 := srcp
     // @astgen alias op2 := countp
 public:
-    AstReplicate(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstReplicate(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Replicate(fl, lhsp, rhsp) {
         if (lhsp) {
             if (const AstConst* const constp = VN_CAST(rhsp, Const)) {
@@ -2723,10 +2942,10 @@ public:
             }
         }
     }
-    AstReplicate(FileLine* fl, AstNode* lhsp, uint32_t repCount)
+    AstReplicate(FileLine* fl, AstNodeExpr* lhsp, uint32_t repCount)
         : AstReplicate{fl, lhsp, new AstConst{fl, repCount}} {}
     ASTGEN_MEMBERS_AstReplicate;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstReplicate{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2744,14 +2963,14 @@ public:
 class AstReplicateN final : public AstNodeBiop {
     // String replicate
 public:
-    AstReplicateN(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstReplicateN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_ReplicateN(fl, lhsp, rhsp) {
         dtypeSetString();
     }
-    AstReplicateN(FileLine* fl, AstNode* lhsp, uint32_t repCount)
+    AstReplicateN(FileLine* fl, AstNodeExpr* lhsp, uint32_t repCount)
         : AstReplicateN{fl, lhsp, new AstConst{fl, repCount}} {}
     ASTGEN_MEMBERS_AstReplicateN;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstReplicateN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2769,12 +2988,12 @@ public:
 };
 class AstShiftL final : public AstNodeBiop {
 public:
-    AstShiftL(FileLine* fl, AstNode* lhsp, AstNode* rhsp, int setwidth = 0)
+    AstShiftL(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, int setwidth = 0)
         : ASTGEN_SUPER_ShiftL(fl, lhsp, rhsp) {
         if (setwidth) dtypeSetLogicSized(setwidth, VSigning::UNSIGNED);
     }
     ASTGEN_MEMBERS_AstShiftL;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstShiftL{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2793,12 +3012,12 @@ public:
 };
 class AstShiftR final : public AstNodeBiop {
 public:
-    AstShiftR(FileLine* fl, AstNode* lhsp, AstNode* rhsp, int setwidth = 0)
+    AstShiftR(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, int setwidth = 0)
         : ASTGEN_SUPER_ShiftR(fl, lhsp, rhsp) {
         if (setwidth) dtypeSetLogicSized(setwidth, VSigning::UNSIGNED);
     }
     ASTGEN_MEMBERS_AstShiftR;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstShiftR{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2820,13 +3039,13 @@ class AstShiftRS final : public AstNodeBiop {
     // Shift right with sign extension, >>> operator
     // Output data type's width determines which bit is used for sign extension
 public:
-    AstShiftRS(FileLine* fl, AstNode* lhsp, AstNode* rhsp, int setwidth = 0)
+    AstShiftRS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, int setwidth = 0)
         : ASTGEN_SUPER_ShiftRS(fl, lhsp, rhsp) {
         // Important that widthMin be correct, as opExtend requires it after V3Expand
         if (setwidth) dtypeSetLogicSized(setwidth, VSigning::SIGNED);
     }
     ASTGEN_MEMBERS_AstShiftRS;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstShiftRS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2844,12 +3063,12 @@ public:
 };
 class AstSub final : public AstNodeBiop {
 public:
-    AstSub(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstSub(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Sub(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstSub;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstSub{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2866,12 +3085,12 @@ public:
 };
 class AstSubD final : public AstNodeBiop {
 public:
-    AstSubD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstSubD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_SubD(fl, lhsp, rhsp) {
         dtypeSetDouble();
     }
     ASTGEN_MEMBERS_AstSubD;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstSubD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2891,12 +3110,12 @@ public:
 class AstURandomRange final : public AstNodeBiop {
     // $urandom_range
 public:
-    AstURandomRange(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstURandomRange(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_URandomRange(fl, lhsp, rhsp) {
         dtypeSetUInt32();  // Says IEEE
     }
     ASTGEN_MEMBERS_AstURandomRange;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstURandomRange{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2917,16 +3136,16 @@ public:
 // === AstNodeBiCom ===
 class AstEq final : public AstNodeBiCom {
 public:
-    AstEq(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstEq(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Eq(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstEq;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstEq{fileline(), lhsp, rhsp};
     }
-    static AstNodeBiop* newTyped(FileLine* fl, AstNode* lhsp,
-                                 AstNode* rhsp);  // Return AstEq/AstEqD
+    // Return AstEq/AstEqD
+    static AstNodeBiop* newTyped(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp);
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
         out.opEq(lhs, rhs);
     }
@@ -2941,12 +3160,12 @@ public:
 };
 class AstEqCase final : public AstNodeBiCom {
 public:
-    AstEqCase(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstEqCase(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_EqCase(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstEqCase;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstEqCase{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2963,12 +3182,12 @@ public:
 };
 class AstEqD final : public AstNodeBiCom {
 public:
-    AstEqD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstEqD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_EqD(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstEqD;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstEqD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -2987,12 +3206,12 @@ public:
 };
 class AstEqN final : public AstNodeBiCom {
 public:
-    AstEqN(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstEqN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_EqN(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstEqN;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstEqN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3011,12 +3230,12 @@ public:
 };
 class AstLogEq final : public AstNodeBiCom {
 public:
-    AstLogEq(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstLogEq(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_LogEq(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstLogEq;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstLogEq{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3034,12 +3253,12 @@ public:
 };
 class AstNeq final : public AstNodeBiCom {
 public:
-    AstNeq(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstNeq(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Neq(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstNeq;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstNeq{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3056,12 +3275,12 @@ public:
 };
 class AstNeqCase final : public AstNodeBiCom {
 public:
-    AstNeqCase(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstNeqCase(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_NeqCase(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstNeqCase;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstNeqCase{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3078,12 +3297,12 @@ public:
 };
 class AstNeqD final : public AstNodeBiCom {
 public:
-    AstNeqD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstNeqD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_NeqD(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstNeqD;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstNeqD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3102,12 +3321,12 @@ public:
 };
 class AstNeqN final : public AstNodeBiCom {
 public:
-    AstNeqN(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstNeqN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_NeqN(fl, lhsp, rhsp) {
         dtypeSetBit();
     }
     ASTGEN_MEMBERS_AstNeqN;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstNeqN{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3128,12 +3347,12 @@ public:
 // === AstNodeBiComAsv ===
 class AstAdd final : public AstNodeBiComAsv {
 public:
-    AstAdd(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstAdd(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Add(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstAdd;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstAdd{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3150,12 +3369,12 @@ public:
 };
 class AstAddD final : public AstNodeBiComAsv {
 public:
-    AstAddD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstAddD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_AddD(fl, lhsp, rhsp) {
         dtypeSetDouble();
     }
     ASTGEN_MEMBERS_AstAddD;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstAddD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3174,12 +3393,12 @@ public:
 };
 class AstAnd final : public AstNodeBiComAsv {
 public:
-    AstAnd(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstAnd(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_And(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstAnd;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstAnd{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3196,12 +3415,12 @@ public:
 };
 class AstMul final : public AstNodeBiComAsv {
 public:
-    AstMul(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstMul(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Mul(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstMul;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstMul{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3219,12 +3438,12 @@ public:
 };
 class AstMulD final : public AstNodeBiComAsv {
 public:
-    AstMulD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstMulD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_MulD(fl, lhsp, rhsp) {
         dtypeSetDouble();
     }
     ASTGEN_MEMBERS_AstMulD;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstMulD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3243,12 +3462,12 @@ public:
 };
 class AstMulS final : public AstNodeBiComAsv {
 public:
-    AstMulS(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstMulS(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_MulS(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstMulS;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstMulS{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3268,12 +3487,12 @@ public:
 };
 class AstOr final : public AstNodeBiComAsv {
 public:
-    AstOr(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstOr(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Or(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstOr;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstOr{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3290,12 +3509,12 @@ public:
 };
 class AstXor final : public AstNodeBiComAsv {
 public:
-    AstXor(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstXor(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Xor(fl, lhsp, rhsp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstXor;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstXor{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3321,16 +3540,16 @@ class AstArraySel final : public AstNodeSel {
     }
 
 public:
-    AstArraySel(FileLine* fl, AstNode* fromp, AstNode* bitp)
+    AstArraySel(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* bitp)
         : ASTGEN_SUPER_ArraySel(fl, fromp, bitp) {
         init(fromp);
     }
-    AstArraySel(FileLine* fl, AstNode* fromp, int bit)
+    AstArraySel(FileLine* fl, AstNodeExpr* fromp, int bit)
         : ASTGEN_SUPER_ArraySel(fl, fromp, new AstConst(fl, bit)) {  // Need () constructor
         init(fromp);
     }
     ASTGEN_MEMBERS_AstArraySel;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstArraySel{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3360,12 +3579,12 @@ class AstAssocSel final : public AstNodeSel {
     }
 
 public:
-    AstAssocSel(FileLine* fl, AstNode* fromp, AstNode* bitp)
+    AstAssocSel(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* bitp)
         : ASTGEN_SUPER_AssocSel(fl, fromp, bitp) {
         init(fromp);
     }
     ASTGEN_MEMBERS_AstAssocSel;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstAssocSel{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3392,12 +3611,12 @@ class AstWildcardSel final : public AstNodeSel {
     }
 
 public:
-    AstWildcardSel(FileLine* fl, AstNode* fromp, AstNode* bitp)
+    AstWildcardSel(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* bitp)
         : ASTGEN_SUPER_WildcardSel(fl, fromp, bitp) {
         init(fromp);
     }
     ASTGEN_MEMBERS_AstWildcardSel;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstWildcardSel{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3418,12 +3637,12 @@ public:
 class AstWordSel final : public AstNodeSel {
     // Select a single word from a multi-word wide value
 public:
-    AstWordSel(FileLine* fl, AstNode* fromp, AstNode* bitp)
+    AstWordSel(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* bitp)
         : ASTGEN_SUPER_WordSel(fl, fromp, bitp) {
         dtypeSetUInt32();  // Always used on WData arrays so returns edata size
     }
     ASTGEN_MEMBERS_AstWordSel;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstWordSel{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& from, const V3Number& bit) override {
@@ -3445,10 +3664,10 @@ public:
 class AstStreamL final : public AstNodeStream {
     // Verilog {rhs{lhs}} - Note rhsp() is the slice size, not the lhsp()
 public:
-    AstStreamL(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstStreamL(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_StreamL(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstStreamL;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeStream* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstStreamL{fileline(), lhsp, rhsp};
     }
     string emitVerilog() override { return "%f{ << %r %k{%l} }"; }
@@ -3466,10 +3685,10 @@ public:
 class AstStreamR final : public AstNodeStream {
     // Verilog {rhs{lhs}} - Note rhsp() is the slice size, not the lhsp()
 public:
-    AstStreamR(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstStreamR(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_StreamR(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstStreamR;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeStream* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstStreamR{fileline(), lhsp, rhsp};
     }
     string emitVerilog() override { return "%f{ >> %r %k{%l} }"; }
@@ -3488,10 +3707,10 @@ public:
 // === AstNodeSystemBiop ===
 class AstAtan2D final : public AstNodeSystemBiop {
 public:
-    AstAtan2D(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstAtan2D(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Atan2D(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstAtan2D;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstAtan2D{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3502,10 +3721,10 @@ public:
 };
 class AstHypotD final : public AstNodeSystemBiop {
 public:
-    AstHypotD(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstHypotD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_HypotD(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstHypotD;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstHypotD{fileline(), lhsp, rhsp};
     }
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
@@ -3521,7 +3740,7 @@ class AstCCall final : public AstNodeCCall {
     string m_selfPointer;  // Output code object pointer (e.g.: 'this')
 
 public:
-    AstCCall(FileLine* fl, AstCFunc* funcp, AstNode* argsp = nullptr)
+    AstCCall(FileLine* fl, AstCFunc* funcp, AstNodeExpr* argsp = nullptr)
         : ASTGEN_SUPER_CCall(fl, funcp, argsp) {}
     ASTGEN_MEMBERS_AstCCall;
 
@@ -3531,9 +3750,9 @@ public:
 };
 class AstCMethodCall final : public AstNodeCCall {
     // C++ method call
-    // @astgen op1 := fromp : AstNode
+    // @astgen op1 := fromp : AstNodeExpr
 public:
-    AstCMethodCall(FileLine* fl, AstNode* fromp, AstCFunc* funcp, AstNode* argsp = nullptr)
+    AstCMethodCall(FileLine* fl, AstNodeExpr* fromp, AstCFunc* funcp, AstNodeExpr* argsp = nullptr)
         : ASTGEN_SUPER_CMethodCall(fl, funcp, argsp) {
         this->fromp(fromp);
     }
@@ -3547,7 +3766,7 @@ public:
 class AstCNew final : public AstNodeCCall {
     // C++ new() call
 public:
-    AstCNew(FileLine* fl, AstCFunc* funcp, AstNode* argsp = nullptr)
+    AstCNew(FileLine* fl, AstCFunc* funcp, AstNodeExpr* argsp = nullptr)
         : ASTGEN_SUPER_CNew(fl, funcp, argsp) {}
     ASTGEN_MEMBERS_AstCNew;
 };
@@ -3556,25 +3775,25 @@ public:
 class AstFuncRef final : public AstNodeFTaskRef {
     // A reference to a function
 public:
-    AstFuncRef(FileLine* fl, AstParseRef* namep, AstNode* pinsp)
+    AstFuncRef(FileLine* fl, AstParseRef* namep, AstNodeExpr* pinsp)
         : ASTGEN_SUPER_FuncRef(fl, (AstNode*)namep, pinsp) {}
-    AstFuncRef(FileLine* fl, const string& name, AstNode* pinsp)
+    AstFuncRef(FileLine* fl, const string& name, AstNodeExpr* pinsp)
         : ASTGEN_SUPER_FuncRef(fl, name, pinsp) {}
     ASTGEN_MEMBERS_AstFuncRef;
 };
 class AstMethodCall final : public AstNodeFTaskRef {
     // A reference to a member task (or function)
     // Don't need the class we are extracting from, as the "fromp()"'s datatype can get us to it
-    // @astgen op2 := fromp : AstNode
+    // @astgen op2 := fromp : AstNodeExpr
     //
 public:
-    AstMethodCall(FileLine* fl, AstNode* fromp, VFlagChildDType, const string& name,
-                  AstNode* pinsp)
+    AstMethodCall(FileLine* fl, AstNodeExpr* fromp, VFlagChildDType, const string& name,
+                  AstNodeExpr* pinsp)
         : ASTGEN_SUPER_MethodCall(fl, name, pinsp) {
         this->fromp(fromp);
         dtypep(nullptr);  // V3Width will resolve
     }
-    AstMethodCall(FileLine* fl, AstNode* fromp, const string& name, AstNode* pinsp)
+    AstMethodCall(FileLine* fl, AstNodeExpr* fromp, const string& name, AstNodeExpr* pinsp)
         : ASTGEN_SUPER_MethodCall(fl, name, pinsp) {
         this->fromp(fromp);
     }
@@ -3590,7 +3809,7 @@ class AstNew final : public AstNodeFTaskRef {
     // New as constructor
     // Don't need the class we are extracting from, as the "fromp()"'s datatype can get us to it
 public:
-    AstNew(FileLine* fl, AstNode* pinsp)
+    AstNew(FileLine* fl, AstNodeExpr* pinsp)
         : ASTGEN_SUPER_New(fl, "new", pinsp) {}
     ASTGEN_MEMBERS_AstNew;
     bool same(const AstNode* /*samep*/) const override { return true; }
@@ -3599,11 +3818,11 @@ public:
 class AstTaskRef final : public AstNodeFTaskRef {
     // A reference to a task
 public:
-    AstTaskRef(FileLine* fl, AstParseRef* namep, AstNode* pinsp)
+    AstTaskRef(FileLine* fl, AstParseRef* namep, AstNodeExpr* pinsp)
         : ASTGEN_SUPER_TaskRef(fl, (AstNode*)namep, pinsp) {
         dtypeSetVoid();
     }
-    AstTaskRef(FileLine* fl, const string& name, AstNode* pinsp)
+    AstTaskRef(FileLine* fl, const string& name, AstNodeExpr* pinsp)
         : ASTGEN_SUPER_TaskRef(fl, name, pinsp) {
         dtypeSetVoid();
     }
@@ -3614,55 +3833,56 @@ public:
 class AstSelBit final : public AstNodePreSel {
     // Single bit range extraction, perhaps with non-constant selection or array selection
     // Gets replaced during link with AstArraySel or AstSel
+    // @astgen alias op2 := bitp
 public:
-    AstSelBit(FileLine* fl, AstNode* fromp, AstNode* bitp)
+    AstSelBit(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* bitp)
         : ASTGEN_SUPER_SelBit(fl, fromp, bitp, nullptr) {
         UASSERT_OBJ(!v3Global.assertDTypesResolved(), this,
                     "not coded to create after dtypes resolved");
     }
     ASTGEN_MEMBERS_AstSelBit;
-    AstNode* bitp() const { return rhsp(); }
 };
 class AstSelExtract final : public AstNodePreSel {
     // Range extraction, gets replaced with AstSel
+    // @astgen alias op2 := leftp
+    // @astgen alias op3 := rightp
 public:
-    AstSelExtract(FileLine* fl, AstNode* fromp, AstNode* msbp, AstNode* lsbp)
+    AstSelExtract(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* msbp, AstNodeExpr* lsbp)
         : ASTGEN_SUPER_SelExtract(fl, fromp, msbp, lsbp) {}
     ASTGEN_MEMBERS_AstSelExtract;
-    AstNode* leftp() const { return rhsp(); }
-    AstNode* rightp() const { return thsp(); }
 };
 class AstSelMinus final : public AstNodePreSel {
     // -: range extraction, perhaps with non-constant selection
     // Gets replaced during link with AstSel
+    // @astgen alias op2 := bitp
+    // @astgen alias op3 := widtph
 public:
-    AstSelMinus(FileLine* fl, AstNode* fromp, AstNode* bitp, AstNode* widthp)
+    AstSelMinus(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* bitp, AstNodeExpr* widthp)
         : ASTGEN_SUPER_SelMinus(fl, fromp, bitp, widthp) {}
     ASTGEN_MEMBERS_AstSelMinus;
-    AstNode* bitp() const { return rhsp(); }
-    AstNode* widthp() const { return thsp(); }
 };
 class AstSelPlus final : public AstNodePreSel {
     // +: range extraction, perhaps with non-constant selection
     // Gets replaced during link with AstSel
+    // @astgen alias op2 := bitp
+    // @astgen alias op3 := widtph
 public:
-    AstSelPlus(FileLine* fl, AstNode* fromp, AstNode* bitp, AstNode* widthp)
+    AstSelPlus(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* bitp, AstNodeExpr* widthp)
         : ASTGEN_SUPER_SelPlus(fl, fromp, bitp, widthp) {}
     ASTGEN_MEMBERS_AstSelPlus;
-    AstNode* bitp() const { return rhsp(); }
-    AstNode* widthp() const { return thsp(); }
 };
 
 // === AstNodeQuadop ===
 class AstCountBits final : public AstNodeQuadop {
     // Number of bits set in vector
 public:
-    AstCountBits(FileLine* fl, AstNode* exprp, AstNode* ctrl1p)
+    AstCountBits(FileLine* fl, AstNodeExpr* exprp, AstNodeExpr* ctrl1p)
         : ASTGEN_SUPER_CountBits(fl, exprp, ctrl1p, ctrl1p->cloneTree(false),
                                  ctrl1p->cloneTree(false)) {}
-    AstCountBits(FileLine* fl, AstNode* exprp, AstNode* ctrl1p, AstNode* ctrl2p)
+    AstCountBits(FileLine* fl, AstNodeExpr* exprp, AstNodeExpr* ctrl1p, AstNodeExpr* ctrl2p)
         : ASTGEN_SUPER_CountBits(fl, exprp, ctrl1p, ctrl2p, ctrl2p->cloneTree(false)) {}
-    AstCountBits(FileLine* fl, AstNode* exprp, AstNode* ctrl1p, AstNode* ctrl2p, AstNode* ctrl3p)
+    AstCountBits(FileLine* fl, AstNodeExpr* exprp, AstNodeExpr* ctrl1p, AstNodeExpr* ctrl2p,
+                 AstNodeExpr* ctrl3p)
         : ASTGEN_SUPER_CountBits(fl, exprp, ctrl1p, ctrl2p, ctrl3p) {}
     ASTGEN_MEMBERS_AstCountBits;
     void numberOperate(V3Number& out, const V3Number& expr, const V3Number& ctrl1,
@@ -3732,7 +3952,7 @@ class AstPostAdd final : public AstNodeTriop {
     // Children: rhsp: tree with AstVarRef that is value to read before operation
     // Children: thsp: tree with AstVarRef LValue that is stored after operation
 public:
-    AstPostAdd(FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* thsp)
+    AstPostAdd(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, AstNodeExpr* thsp)
         : ASTGEN_SUPER_PostAdd(fl, lhsp, rhsp, thsp) {}
     ASTGEN_MEMBERS_AstPostAdd;
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs,
@@ -3756,7 +3976,7 @@ class AstPostSub final : public AstNodeTriop {
     // Children: rhsp: tree with AstVarRef that is value to read before operation
     // Children: thsp: tree with AstVarRef LValue that is stored after operation
 public:
-    AstPostSub(FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* thsp)
+    AstPostSub(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, AstNodeExpr* thsp)
         : ASTGEN_SUPER_PostSub(fl, lhsp, rhsp, thsp) {}
     ASTGEN_MEMBERS_AstPostSub;
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs,
@@ -3780,7 +4000,7 @@ class AstPreAdd final : public AstNodeTriop {
     // Children: rhsp: tree with AstVarRef that is value to read before operation
     // Children: thsp: tree with AstVarRef LValue that is stored after operation
 public:
-    AstPreAdd(FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* thsp)
+    AstPreAdd(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, AstNodeExpr* thsp)
         : ASTGEN_SUPER_PreAdd(fl, lhsp, rhsp, thsp) {}
     ASTGEN_MEMBERS_AstPreAdd;
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs,
@@ -3804,7 +4024,7 @@ class AstPreSub final : public AstNodeTriop {
     // Children: rhsp: tree with AstVarRef that is value to read before operation
     // Children: thsp: tree with AstVarRef LValue that is stored after operation
 public:
-    AstPreSub(FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* thsp)
+    AstPreSub(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, AstNodeExpr* thsp)
         : ASTGEN_SUPER_PreSub(fl, lhsp, rhsp, thsp) {}
     ASTGEN_MEMBERS_AstPreSub;
     void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs,
@@ -3825,7 +4045,7 @@ public:
 class AstPutcN final : public AstNodeTriop {
     // Verilog string.putc()
 public:
-    AstPutcN(FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* ths)
+    AstPutcN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, AstNodeExpr* ths)
         : ASTGEN_SUPER_PutcN(fl, lhsp, rhsp, ths) {
         dtypeSetString();
     }
@@ -3854,14 +4074,14 @@ class AstSel final : public AstNodeTriop {
     VNumRange m_declRange;  // Range of the 'from' array if isRanged() is set, else invalid
     int m_declElWidth;  // If a packed array, the number of bits per element
 public:
-    AstSel(FileLine* fl, AstNode* fromp, AstNode* lsbp, AstNode* widthp)
+    AstSel(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* lsbp, AstNodeExpr* widthp)
         : ASTGEN_SUPER_Sel(fl, fromp, lsbp, widthp)
         , m_declElWidth{1} {
         if (VN_IS(widthp, Const)) {
             dtypeSetLogicSized(VN_AS(widthp, Const)->toUInt(), VSigning::UNSIGNED);
         }
     }
-    AstSel(FileLine* fl, AstNode* fromp, int lsb, int bitwidth)
+    AstSel(FileLine* fl, AstNodeExpr* fromp, int lsb, int bitwidth)
         : ASTGEN_SUPER_Sel(fl, fromp, new AstConst(fl, lsb),  // Need () constructor
                            new AstConst(fl, bitwidth))  // Need () constructor
         , m_declElWidth{1} {
@@ -3902,7 +4122,7 @@ class AstSliceSel final : public AstNodeTriop {
     // @astgen alias op1 := fromp
     VNumRange m_declRange;  // Range of the 'from' array if isRanged() is set, else invalid
 public:
-    AstSliceSel(FileLine* fl, AstNode* fromp, const VNumRange& declRange)
+    AstSliceSel(FileLine* fl, AstNodeExpr* fromp, const VNumRange& declRange)
         : ASTGEN_SUPER_SliceSel(fl, fromp,
                                 new AstConst(fl, declRange.lo()),  // Need () constructor
                                 new AstConst(fl, declRange.elements()))  // Need () constructor
@@ -3932,7 +4152,7 @@ public:
 class AstSubstrN final : public AstNodeTriop {
     // Verilog string.substr()
 public:
-    AstSubstrN(FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* ths)
+    AstSubstrN(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, AstNodeExpr* ths)
         : ASTGEN_SUPER_SubstrN(fl, lhsp, rhsp, ths) {
         dtypeSetString();
     }
@@ -3958,20 +4178,20 @@ public:
 class AstCond final : public AstNodeCond {
     // Conditional ?: expressoin
 public:
-    AstCond(FileLine* fl, AstNode* condp, AstNode* thenp, AstNode* elsep)
+    AstCond(FileLine* fl, AstNodeExpr* condp, AstNodeExpr* thenp, AstNodeExpr* elsep)
         : ASTGEN_SUPER_Cond(fl, condp, thenp, elsep) {}
     ASTGEN_MEMBERS_AstCond;
-    AstNode* cloneType(AstNode* condp, AstNode* thenp, AstNode* elsep) override {
+    AstNodeExpr* cloneType(AstNodeExpr* condp, AstNodeExpr* thenp, AstNodeExpr* elsep) override {
         return new AstCond{fileline(), condp, thenp, elsep};
     }
 };
 class AstCondBound final : public AstNodeCond {
     // Conditional ?: expression, specially made for safety checking of array bounds
 public:
-    AstCondBound(FileLine* fl, AstNode* condp, AstNode* thenp, AstNode* elsep)
+    AstCondBound(FileLine* fl, AstNodeExpr* condp, AstNodeExpr* thenp, AstNodeExpr* elsep)
         : ASTGEN_SUPER_CondBound(fl, condp, thenp, elsep) {}
     ASTGEN_MEMBERS_AstCondBound;
-    AstNode* cloneType(AstNode* condp, AstNode* thenp, AstNode* elsep) override {
+    AstNodeExpr* cloneType(AstNodeExpr* condp, AstNodeExpr* thenp, AstNodeExpr* elsep) override {
         return new AstCondBound{fileline(), condp, thenp, elsep};
     }
 };
@@ -3985,7 +4205,7 @@ public:
 private:
     const FmtType m_fmt;  // Operation type
 public:
-    AstAtoN(FileLine* fl, AstNode* lhsp, FmtType fmt)
+    AstAtoN(FileLine* fl, AstNodeExpr* lhsp, FmtType fmt)
         : ASTGEN_SUPER_AtoN(fl, lhsp)
         , m_fmt{fmt} {
         fmt == ATOREAL ? dtypeSetDouble() : dtypeSetSigned32();
@@ -4020,7 +4240,7 @@ public:
 };
 class AstBitsToRealD final : public AstNodeUniop {
 public:
-    AstBitsToRealD(FileLine* fl, AstNode* lhsp)
+    AstBitsToRealD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_BitsToRealD(fl, lhsp) {
         dtypeSetDouble();
     }
@@ -4038,7 +4258,7 @@ class AstCAwait final : public AstNodeUniop {
     // @astgen alias op1 := exprp
     AstSenTree* m_sensesp;  // Sentree related to this await
 public:
-    AstCAwait(FileLine* fl, AstNode* exprp, AstSenTree* sensesp = nullptr)
+    AstCAwait(FileLine* fl, AstNodeExpr* exprp, AstSenTree* sensesp = nullptr)
         : ASTGEN_SUPER_CAwait(fl, exprp)
         , m_sensesp{sensesp} {}
     ASTGEN_MEMBERS_AstCAwait;
@@ -4060,7 +4280,7 @@ class AstCCast final : public AstNodeUniop {
     int m_size;
 
 public:
-    AstCCast(FileLine* fl, AstNode* lhsp, int setwidth, int minwidth = -1)
+    AstCCast(FileLine* fl, AstNodeExpr* lhsp, int setwidth, int minwidth = -1)
         : ASTGEN_SUPER_CCast(fl, lhsp) {
         m_size = setwidth;
         if (setwidth) {
@@ -4068,7 +4288,7 @@ public:
             dtypeSetLogicUnsized(setwidth, minwidth, VSigning::UNSIGNED);
         }
     }
-    AstCCast(FileLine* fl, AstNode* lhsp, AstNode* typeFromp)
+    AstCCast(FileLine* fl, AstNodeExpr* lhsp, AstNode* typeFromp)
         : ASTGEN_SUPER_CCast(fl, lhsp) {
         dtypeFrom(typeFromp);
         m_size = width();
@@ -4089,7 +4309,7 @@ public:
 };
 class AstCLog2 final : public AstNodeUniop {
 public:
-    AstCLog2(FileLine* fl, AstNode* lhsp)
+    AstCLog2(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_CLog2(fl, lhsp) {
         dtypeSetSigned32();
     }
@@ -4105,7 +4325,7 @@ public:
 class AstCountOnes final : public AstNodeUniop {
     // Number of bits set in vector
 public:
-    AstCountOnes(FileLine* fl, AstNode* lhsp)
+    AstCountOnes(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_CountOnes(fl, lhsp) {}
     ASTGEN_MEMBERS_AstCountOnes;
     void numberOperate(V3Number& out, const V3Number& lhs) override { out.opCountOnes(lhs); }
@@ -4119,7 +4339,7 @@ public:
 class AstCvtPackString final : public AstNodeUniop {
     // Convert to Verilator Packed String (aka verilog "string")
 public:
-    AstCvtPackString(FileLine* fl, AstNode* lhsp)
+    AstCvtPackString(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_CvtPackString(fl, lhsp) {
         dtypeSetString();
     }
@@ -4135,9 +4355,9 @@ public:
 class AstExtend final : public AstNodeUniop {
     // Expand a value into a wider entity by 0 extension.  Width is implied from nodep->width()
 public:
-    AstExtend(FileLine* fl, AstNode* lhsp)
+    AstExtend(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_Extend(fl, lhsp) {}
-    AstExtend(FileLine* fl, AstNode* lhsp, int width)
+    AstExtend(FileLine* fl, AstNodeExpr* lhsp, int width)
         : ASTGEN_SUPER_Extend(fl, lhsp) {
         dtypeSetLogicSized(width, VSigning::UNSIGNED);
     }
@@ -4155,9 +4375,9 @@ public:
 class AstExtendS final : public AstNodeUniop {
     // Expand a value into a wider entity by sign extension.  Width is implied from nodep->width()
 public:
-    AstExtendS(FileLine* fl, AstNode* lhsp)
+    AstExtendS(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_ExtendS(fl, lhsp) {}
-    AstExtendS(FileLine* fl, AstNode* lhsp, int width)
+    AstExtendS(FileLine* fl, AstNodeExpr* lhsp, int width)
         // Important that widthMin be correct, as opExtend requires it after V3Expand
         : ASTGEN_SUPER_ExtendS(fl, lhsp) {
         dtypeSetLogicSized(width, VSigning::UNSIGNED);
@@ -4178,7 +4398,7 @@ public:
 };
 class AstFEof final : public AstNodeUniop {
 public:
-    AstFEof(FileLine* fl, AstNode* lhsp)
+    AstFEof(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_FEof(fl, lhsp) {}
     ASTGEN_MEMBERS_AstFEof;
     void numberOperate(V3Number& out, const V3Number& lhs) override { V3ERROR_NA; }
@@ -4193,7 +4413,7 @@ public:
 };
 class AstFGetC final : public AstNodeUniop {
 public:
-    AstFGetC(FileLine* fl, AstNode* lhsp)
+    AstFGetC(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_FGetC(fl, lhsp) {}
     ASTGEN_MEMBERS_AstFGetC;
     void numberOperate(V3Number& out, const V3Number& lhs) override { V3ERROR_NA; }
@@ -4210,7 +4430,7 @@ public:
 class AstISToRD final : public AstNodeUniop {
     // $itor where lhs is signed
 public:
-    AstISToRD(FileLine* fl, AstNode* lhsp)
+    AstISToRD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_ISToRD(fl, lhsp) {
         dtypeSetDouble();
     }
@@ -4227,7 +4447,7 @@ public:
 class AstIToRD final : public AstNodeUniop {
     // $itor where lhs is unsigned
 public:
-    AstIToRD(FileLine* fl, AstNode* lhsp)
+    AstIToRD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_IToRD(fl, lhsp) {
         dtypeSetDouble();
     }
@@ -4243,7 +4463,7 @@ public:
 class AstIsUnbounded final : public AstNodeUniop {
     // True if is unmbounded ($)
 public:
-    AstIsUnbounded(FileLine* fl, AstNode* lhsp)
+    AstIsUnbounded(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_IsUnbounded(fl, lhsp) {
         dtypeSetBit();
     }
@@ -4261,7 +4481,7 @@ public:
 class AstIsUnknown final : public AstNodeUniop {
     // True if any unknown bits
 public:
-    AstIsUnknown(FileLine* fl, AstNode* lhsp)
+    AstIsUnknown(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_IsUnknown(fl, lhsp) {
         dtypeSetBit();
     }
@@ -4276,7 +4496,7 @@ public:
 class AstLenN final : public AstNodeUniop {
     // Length of a string
 public:
-    AstLenN(FileLine* fl, AstNode* lhsp)
+    AstLenN(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_LenN(fl, lhsp) {
         dtypeSetSigned32();
     }
@@ -4290,7 +4510,7 @@ public:
 };
 class AstLogNot final : public AstNodeUniop {
 public:
-    AstLogNot(FileLine* fl, AstNode* lhsp)
+    AstLogNot(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_LogNot(fl, lhsp) {
         dtypeSetBit();
     }
@@ -4305,7 +4525,7 @@ public:
 };
 class AstNegate final : public AstNodeUniop {
 public:
-    AstNegate(FileLine* fl, AstNode* lhsp)
+    AstNegate(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_Negate(fl, lhsp) {
         dtypeFrom(lhsp);
     }
@@ -4320,7 +4540,7 @@ public:
 };
 class AstNegateD final : public AstNodeUniop {
 public:
-    AstNegateD(FileLine* fl, AstNode* lhsp)
+    AstNegateD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_NegateD(fl, lhsp) {
         dtypeSetDouble();
     }
@@ -4337,7 +4557,7 @@ public:
 };
 class AstNot final : public AstNodeUniop {
 public:
-    AstNot(FileLine* fl, AstNode* lhsp)
+    AstNot(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_Not(fl, lhsp) {
         dtypeFrom(lhsp);
     }
@@ -4353,7 +4573,7 @@ public:
 class AstNullCheck final : public AstNodeUniop {
     // Return LHS after checking that LHS is non-null
 public:
-    AstNullCheck(FileLine* fl, AstNode* lhsp)
+    AstNullCheck(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_NullCheck(fl, lhsp) {
         dtypeFrom(lhsp);
     }
@@ -4371,7 +4591,7 @@ public:
 class AstOneHot final : public AstNodeUniop {
     // True if only single bit set in vector
 public:
-    AstOneHot(FileLine* fl, AstNode* lhsp)
+    AstOneHot(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_OneHot(fl, lhsp) {
         dtypeSetBit();
     }
@@ -4387,7 +4607,7 @@ public:
 class AstOneHot0 final : public AstNodeUniop {
     // True if only single bit, or no bits set in vector
 public:
-    AstOneHot0(FileLine* fl, AstNode* lhsp)
+    AstOneHot0(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_OneHot0(fl, lhsp) {
         dtypeSetBit();
     }
@@ -4403,7 +4623,7 @@ public:
 class AstRToIRoundS final : public AstNodeUniop {
     // Convert real to integer, with arbitrary sized output (not just "integer" format)
 public:
-    AstRToIRoundS(FileLine* fl, AstNode* lhsp)
+    AstRToIRoundS(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_RToIRoundS(fl, lhsp) {
         dtypeSetSigned32();
     }
@@ -4421,7 +4641,7 @@ public:
 class AstRToIS final : public AstNodeUniop {
     // $rtoi(lhs)
 public:
-    AstRToIS(FileLine* fl, AstNode* lhsp)
+    AstRToIS(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_RToIS(fl, lhsp) {
         dtypeSetSigned32();
     }
@@ -4436,7 +4656,7 @@ public:
 };
 class AstRealToBits final : public AstNodeUniop {
 public:
-    AstRealToBits(FileLine* fl, AstNode* lhsp)
+    AstRealToBits(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_RealToBits(fl, lhsp) {
         dtypeSetUInt64();
     }
@@ -4451,7 +4671,7 @@ public:
 };
 class AstRedAnd final : public AstNodeUniop {
 public:
-    AstRedAnd(FileLine* fl, AstNode* lhsp)
+    AstRedAnd(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_RedAnd(fl, lhsp) {
         dtypeSetBit();
     }
@@ -4465,7 +4685,7 @@ public:
 };
 class AstRedOr final : public AstNodeUniop {
 public:
-    AstRedOr(FileLine* fl, AstNode* lhsp)
+    AstRedOr(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_RedOr(fl, lhsp) {
         dtypeSetBit();
     }
@@ -4479,7 +4699,7 @@ public:
 };
 class AstRedXor final : public AstNodeUniop {
 public:
-    AstRedXor(FileLine* fl, AstNode* lhsp)
+    AstRedXor(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_RedXor(fl, lhsp) {
         dtypeSetBit();
     }
@@ -4498,7 +4718,7 @@ public:
 class AstSigned final : public AstNodeUniop {
     // $signed(lhs)
 public:
-    AstSigned(FileLine* fl, AstNode* lhsp)
+    AstSigned(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_Signed(fl, lhsp) {
         UASSERT_OBJ(!v3Global.assertDTypesResolved(), this,
                     "not coded to create after dtypes resolved");
@@ -4519,7 +4739,7 @@ class AstTimeImport final : public AstNodeUniop {
     // Take a constant that represents a time and needs conversion based on time units
     VTimescale m_timeunit;  // Parent module time unit
 public:
-    AstTimeImport(FileLine* fl, AstNode* lhsp)
+    AstTimeImport(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_TimeImport(fl, lhsp) {}
     ASTGEN_MEMBERS_AstTimeImport;
     void numberOperate(V3Number& out, const V3Number& lhs) override { V3ERROR_NA; }
@@ -4535,7 +4755,7 @@ public:
 class AstToLowerN final : public AstNodeUniop {
     // string.tolower()
 public:
-    AstToLowerN(FileLine* fl, AstNode* lhsp)
+    AstToLowerN(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_ToLowerN(fl, lhsp) {
         dtypeSetString();
     }
@@ -4550,7 +4770,7 @@ public:
 class AstToUpperN final : public AstNodeUniop {
     // string.toupper()
 public:
-    AstToUpperN(FileLine* fl, AstNode* lhsp)
+    AstToUpperN(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_ToUpperN(fl, lhsp) {
         dtypeSetString();
     }
@@ -4565,7 +4785,7 @@ public:
 class AstUnsigned final : public AstNodeUniop {
     // $unsigned(lhs)
 public:
-    AstUnsigned(FileLine* fl, AstNode* lhsp)
+    AstUnsigned(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_Unsigned(fl, lhsp) {
         UASSERT_OBJ(!v3Global.assertDTypesResolved(), this,
                     "not coded to create after dtypes resolved");
@@ -4586,7 +4806,7 @@ public:
 // === AstNodeSystemUniop ===
 class AstAcosD final : public AstNodeSystemUniop {
 public:
-    AstAcosD(FileLine* fl, AstNode* lhsp)
+    AstAcosD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_AcosD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstAcosD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4597,7 +4817,7 @@ public:
 };
 class AstAcoshD final : public AstNodeSystemUniop {
 public:
-    AstAcoshD(FileLine* fl, AstNode* lhsp)
+    AstAcoshD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_AcoshD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstAcoshD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4608,7 +4828,7 @@ public:
 };
 class AstAsinD final : public AstNodeSystemUniop {
 public:
-    AstAsinD(FileLine* fl, AstNode* lhsp)
+    AstAsinD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_AsinD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstAsinD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4619,7 +4839,7 @@ public:
 };
 class AstAsinhD final : public AstNodeSystemUniop {
 public:
-    AstAsinhD(FileLine* fl, AstNode* lhsp)
+    AstAsinhD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_AsinhD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstAsinhD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4630,7 +4850,7 @@ public:
 };
 class AstAtanD final : public AstNodeSystemUniop {
 public:
-    AstAtanD(FileLine* fl, AstNode* lhsp)
+    AstAtanD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_AtanD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstAtanD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4641,7 +4861,7 @@ public:
 };
 class AstAtanhD final : public AstNodeSystemUniop {
 public:
-    AstAtanhD(FileLine* fl, AstNode* lhsp)
+    AstAtanhD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_AtanhD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstAtanhD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4652,7 +4872,7 @@ public:
 };
 class AstCeilD final : public AstNodeSystemUniop {
 public:
-    AstCeilD(FileLine* fl, AstNode* lhsp)
+    AstCeilD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_CeilD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstCeilD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4663,7 +4883,7 @@ public:
 };
 class AstCosD final : public AstNodeSystemUniop {
 public:
-    AstCosD(FileLine* fl, AstNode* lhsp)
+    AstCosD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_CosD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstCosD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4674,7 +4894,7 @@ public:
 };
 class AstCoshD final : public AstNodeSystemUniop {
 public:
-    AstCoshD(FileLine* fl, AstNode* lhsp)
+    AstCoshD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_CoshD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstCoshD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4685,7 +4905,7 @@ public:
 };
 class AstExpD final : public AstNodeSystemUniop {
 public:
-    AstExpD(FileLine* fl, AstNode* lhsp)
+    AstExpD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_ExpD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstExpD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4696,7 +4916,7 @@ public:
 };
 class AstFloorD final : public AstNodeSystemUniop {
 public:
-    AstFloorD(FileLine* fl, AstNode* lhsp)
+    AstFloorD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_FloorD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstFloorD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4707,7 +4927,7 @@ public:
 };
 class AstLog10D final : public AstNodeSystemUniop {
 public:
-    AstLog10D(FileLine* fl, AstNode* lhsp)
+    AstLog10D(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_Log10D(fl, lhsp) {}
     ASTGEN_MEMBERS_AstLog10D;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4718,7 +4938,7 @@ public:
 };
 class AstLogD final : public AstNodeSystemUniop {
 public:
-    AstLogD(FileLine* fl, AstNode* lhsp)
+    AstLogD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_LogD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstLogD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4729,7 +4949,7 @@ public:
 };
 class AstSinD final : public AstNodeSystemUniop {
 public:
-    AstSinD(FileLine* fl, AstNode* lhsp)
+    AstSinD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_SinD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstSinD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4740,7 +4960,7 @@ public:
 };
 class AstSinhD final : public AstNodeSystemUniop {
 public:
-    AstSinhD(FileLine* fl, AstNode* lhsp)
+    AstSinhD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_SinhD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstSinhD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4751,7 +4971,7 @@ public:
 };
 class AstSqrtD final : public AstNodeSystemUniop {
 public:
-    AstSqrtD(FileLine* fl, AstNode* lhsp)
+    AstSqrtD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_SqrtD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstSqrtD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4762,7 +4982,7 @@ public:
 };
 class AstTanD final : public AstNodeSystemUniop {
 public:
-    AstTanD(FileLine* fl, AstNode* lhsp)
+    AstTanD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_TanD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstTanD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
@@ -4773,7 +4993,7 @@ public:
 };
 class AstTanhD final : public AstNodeSystemUniop {
 public:
-    AstTanhD(FileLine* fl, AstNode* lhsp)
+    AstTanhD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_TanhD(fl, lhsp) {}
     ASTGEN_MEMBERS_AstTanhD;
     void numberOperate(V3Number& out, const V3Number& lhs) override {
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index deb657f65..b5e164c4b 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -310,11 +310,11 @@ public:
 };
 class AstNodeAssign VL_NOT_FINAL : public AstNodeStmt {
     // Iteration is in order, and we want rhsp to be visited first (which is the execution order)
-    // @astgen op1 := rhsp : AstNode
-    // @astgen op2 := lhsp : AstNode
+    // @astgen op1 := rhsp : AstNodeExpr
+    // @astgen op2 := lhsp : AstNodeExpr
     // @astgen op3 := timingControlp : Optional[AstNode]
 protected:
-    AstNodeAssign(VNType t, FileLine* fl, AstNode* lhsp, AstNode* rhsp,
+    AstNodeAssign(VNType t, FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp,
                   AstNode* timingControlp = nullptr)
         : AstNodeStmt{t, fl} {
         this->rhsp(rhsp);
@@ -326,7 +326,7 @@ protected:
 public:
     ASTGEN_MEMBERS_AstNodeAssign;
     // Clone single node, just get same type back.
-    virtual AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) = 0;
+    virtual AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) = 0;
     bool hasDType() const override { return true; }
     virtual bool cleanRhs() const { return true; }
     int instrCount() const override { return widthInstrs(); }
@@ -336,11 +336,11 @@ public:
     virtual bool brokeLhsMustBeLvalue() const = 0;
 };
 class AstNodeCase VL_NOT_FINAL : public AstNodeStmt {
-    // @astgen op1 := exprp : AstNode // Condition (scurtinee) expression
+    // @astgen op1 := exprp : AstNodeExpr // Condition (scurtinee) expression
     // @astgen op2 := itemsp : List[AstCaseItem]
     // @astgen op3 := notParallelp : List[AstNode] // assertion code for non-full case's
 protected:
-    AstNodeCase(VNType t, FileLine* fl, AstNode* exprp, AstCaseItem* itemsp)
+    AstNodeCase(VNType t, FileLine* fl, AstNodeExpr* exprp, AstCaseItem* itemsp)
         : AstNodeStmt{t, fl} {
         this->exprp(exprp);
         this->addItemsp(itemsp);
@@ -377,11 +377,11 @@ public:
 };
 class AstNodeFor VL_NOT_FINAL : public AstNodeStmt {
     // @astgen op1 := initsp : List[AstNode]
-    // @astgen op2 := condp : AstNode
+    // @astgen op2 := condp : AstNodeExpr
     // @astgen op3 := incsp : List[AstNode]
     // @astgen op4 := stmtsp : List[AstNode]
 protected:
-    AstNodeFor(VNType t, FileLine* fl, AstNode* initsp, AstNode* condp, AstNode* incsp,
+    AstNodeFor(VNType t, FileLine* fl, AstNode* initsp, AstNodeExpr* condp, AstNode* incsp,
                AstNode* stmtsp)
         : AstNodeStmt{t, fl} {
         this->addInitsp(initsp);
@@ -397,14 +397,14 @@ public:
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
 class AstNodeIf VL_NOT_FINAL : public AstNodeStmt {
-    // @astgen op1 := condp : AstNode
+    // @astgen op1 := condp : AstNodeExpr
     // @astgen op2 := thensp : List[AstNode]
     // @astgen op3 := elsesp : List[AstNode]
 private:
     VBranchPred m_branchPred;  // Branch prediction as taken/untaken?
     bool m_isBoundsCheck;  // True if this if node is for assertion/bounds checking
 protected:
-    AstNodeIf(VNType t, FileLine* fl, AstNode* condp, AstNode* thensp, AstNode* elsesp)
+    AstNodeIf(VNType t, FileLine* fl, AstNodeExpr* condp, AstNode* thensp, AstNode* elsesp)
         : AstNodeStmt{t, fl} {
         this->condp(condp);
         this->addThensp(thensp);
@@ -427,15 +427,15 @@ public:
     }
 };
 class AstNodeReadWriteMem VL_NOT_FINAL : public AstNodeStmt {
-    // @astgen op1 := filenamep : AstNode
-    // @astgen op2 := memp : AstNode
-    // @astgen op3 := lsbp : Optional[AstNode]
-    // @astgen op4 := msbp : Optional[AstNode]
+    // @astgen op1 := filenamep : AstNodeExpr
+    // @astgen op2 := memp : AstNodeExpr
+    // @astgen op3 := lsbp : Optional[AstNodeExpr]
+    // @astgen op4 := msbp : Optional[AstNodeExpr]
 
     const bool m_isHex;  // readmemh, not readmemb
 public:
-    AstNodeReadWriteMem(VNType t, FileLine* fl, bool hex, AstNode* filenamep, AstNode* memp,
-                        AstNode* lsbp, AstNode* msbp)
+    AstNodeReadWriteMem(VNType t, FileLine* fl, bool hex, AstNodeExpr* filenamep,
+                        AstNodeExpr* memp, AstNodeExpr* lsbp, AstNodeExpr* msbp)
         : AstNodeStmt(t, fl)
         , m_isHex(hex) {
         this->filenamep(filenamep);
@@ -518,21 +518,6 @@ public:
     inline bool hasClocked() const;
     inline bool hasCombo() const;
 };
-class AstArg final : public AstNode {
-    // An argument to a function/task
-    // @astgen op1 := exprp : Optional[AstNode] // nullptr if omitted
-    string m_name;  // Pin name, or "" for number based interconnect
-public:
-    AstArg(FileLine* fl, const string& name, AstNode* exprp)
-        : ASTGEN_SUPER_Arg(fl)
-        , m_name{name} {
-        this->exprp(exprp);
-    }
-    ASTGEN_MEMBERS_AstArg;
-    string name() const override { return m_name; }  // * = Pin name, ""=go by number
-    void name(const string& name) override { m_name = name; }
-    bool emptyConnectNoNext() const { return !exprp() && name() == "" && !nextp(); }
-};
 class AstBind final : public AstNode {
     // Parents: MODULE
     // Children: CELL
@@ -718,10 +703,10 @@ public:
 };
 class AstCaseItem final : public AstNode {
     // Single item of a case statement
-    // @astgen op1 := condsp : List[AstNode]
+    // @astgen op1 := condsp : List[AstNodeExpr]
     // @astgen op2 := stmtsp : List[AstNode]
 public:
-    AstCaseItem(FileLine* fl, AstNode* condsp, AstNode* stmtsp)
+    AstCaseItem(FileLine* fl, AstNodeExpr* condsp, AstNode* stmtsp)
         : ASTGEN_SUPER_CaseItem(fl) {
         this->addCondsp(condsp);
         this->addStmtsp(stmtsp);
@@ -731,23 +716,6 @@ public:
     bool isDefault() const { return condsp() == nullptr; }
     bool isFirstInMyListOfStatements(AstNode* n) const override { return n == stmtsp(); }
 };
-class AstCastSize final : public AstNode {
-    // Cast to specific size; signed/twostate inherited from lower element per IEEE
-    // @astgen op1 := lhsp : AstNode
-    // @astgen op2 := rhsp : AstNode
-public:
-    AstCastSize(FileLine* fl, AstNode* lhsp, AstConst* rhsp)
-        : ASTGEN_SUPER_CastSize(fl) {
-        this->lhsp(lhsp);
-        this->rhsp(rhsp);
-    }
-    ASTGEN_MEMBERS_AstCastSize;
-    // No hasDType because widthing removes this node before the hasDType check
-    virtual string emitVerilog() { return "((%r)'(%l))"; }
-    virtual bool cleanOut() const { V3ERROR_NA_RETURN(true); }
-    virtual bool cleanLhs() const { return true; }
-    virtual bool sizeMattersLhs() const { return false; }
-};
 class AstCell final : public AstNode {
     // A instantiation cell or interface call (don't know which until link)
     // @astgen op1 := pinsp : List[AstPin] // List of port assignments
@@ -799,20 +767,6 @@ public:
     void recursive(bool flag) { m_recursive = flag; }
     bool recursive() const { return m_recursive; }
 };
-class AstCellArrayRef final : public AstNode {
-    // As-of-yet unlinkable reference into an array of cells
-    // @astgen op1 := selp : List[AstNode] // Select expression
-    string m_name;  // Array name
-public:
-    AstCellArrayRef(FileLine* fl, const string& name, AstNode* selp)
-        : ASTGEN_SUPER_CellArrayRef(fl)
-        , m_name{name} {
-        this->addSelp(selp);
-    }
-    ASTGEN_MEMBERS_AstCellArrayRef;
-    // ACCESSORS
-    string name() const override { return m_name; }  // * = Array name
-};
 class AstCellInline final : public AstNode {
     // A instantiation cell that was removed by inlining
     // For communication between V3Inline and V3LinkDot,
@@ -844,23 +798,6 @@ public:
     void timeunit(const VTimescale& flag) { m_timeunit = flag; }
     VTimescale timeunit() const { return m_timeunit; }
 };
-class AstCellRef final : public AstNode {
-    // As-of-yet unlinkable reference into a cell
-    // @astgen op1 := cellp : AstNode
-    // @astgen op2 := exprp : AstNode
-private:
-    string m_name;  // Cell name
-public:
-    AstCellRef(FileLine* fl, const string& name, AstNode* cellp, AstNode* exprp)
-        : ASTGEN_SUPER_CellRef(fl)
-        , m_name{name} {
-        this->cellp(cellp);
-        this->exprp(exprp);
-    }
-    ASTGEN_MEMBERS_AstCellRef;
-    // ACCESSORS
-    string name() const override { return m_name; }  // * = Array name
-};
 class AstClassExtends final : public AstNode {
     // Children: List of AstParseRef for packages/classes
     // during early parse, then moves to dtype
@@ -876,43 +813,6 @@ public:
     string verilogKwd() const override { return "extends"; }
     AstClass* classp() const;  // Class being extended (after link)
 };
-class AstClassOrPackageRef final : public AstNode {
-    // @astgen op1 := paramsp : List[AstPin]
-private:
-    string m_name;
-    // Node not NodeModule to appease some early parser usage
-    AstNode* m_classOrPackageNodep;  // Package hierarchy
-public:
-    AstClassOrPackageRef(FileLine* fl, const string& name, AstNode* classOrPackageNodep,
-                         AstPin* paramsp)
-        : ASTGEN_SUPER_ClassOrPackageRef(fl)
-        , m_name{name}
-        , m_classOrPackageNodep{classOrPackageNodep} {
-        this->addParamsp(paramsp);
-    }
-    ASTGEN_MEMBERS_AstClassOrPackageRef;
-    // METHODS
-    const char* broken() const override {
-        BROKEN_RTN(m_classOrPackageNodep && !m_classOrPackageNodep->brokeExists());
-        return nullptr;
-    }
-    void cloneRelink() override {
-        if (m_classOrPackageNodep && m_classOrPackageNodep->clonep()) {
-            m_classOrPackageNodep = m_classOrPackageNodep->clonep();
-        }
-    }
-    bool same(const AstNode* samep) const override {
-        return (m_classOrPackageNodep
-                == static_cast<const AstClassOrPackageRef*>(samep)->m_classOrPackageNodep);
-    }
-    void dump(std::ostream& str = std::cout) const override;
-    string name() const override { return m_name; }  // * = Var name
-    AstNode* classOrPackageNodep() const { return m_classOrPackageNodep; }
-    void classOrPackageNodep(AstNode* nodep) { m_classOrPackageNodep = nodep; }
-    AstNodeModule* classOrPackagep() const;
-    AstPackage* packagep() const { return VN_CAST(classOrPackageNodep(), Package); }
-    void classOrPackagep(AstNodeModule* nodep) { m_classOrPackageNodep = (AstNode*)nodep; }
-};
 class AstClocking final : public AstNode {
     // Set default clock region
     // Parents:  MODULE
@@ -934,7 +834,7 @@ class AstConstPool final : public AstNode {
     AstModule* const m_modp;  // The Module holding the Scope below ...
     AstScope* const m_scopep;  // Scope holding the constant variables
 
-    AstVarScope* createNewEntry(const string& name, AstNode* initp);
+    AstVarScope* createNewEntry(const string& name, AstNodeExpr* initp);
 
 public:
     explicit AstConstPool(FileLine* fl);
@@ -960,11 +860,11 @@ public:
 class AstDefParam final : public AstNode {
     // A defparam assignment
     // Parents: MODULE
-    // @astgen op1 := rhsp : AstNode
+    // @astgen op1 := rhsp : AstNodeExpr
     string m_name;  // Name of variable getting set
     string m_path;  // Dotted cellname to set parameter of
 public:
-    AstDefParam(FileLine* fl, const string& path, const string& name, AstNode* rhsp)
+    AstDefParam(FileLine* fl, const string& path, const string& name, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_DefParam(fl)
         , m_name{name}
         , m_path{path} {
@@ -1000,7 +900,7 @@ private:
     VDisplayType m_displayType;
 
 public:
-    inline AstElabDisplay(FileLine* fl, VDisplayType dispType, AstNode* exprsp);
+    inline AstElabDisplay(FileLine* fl, VDisplayType dispType, AstNodeExpr* exprsp);
     ASTGEN_MEMBERS_AstElabDisplay;
     const char* broken() const override {
         BROKEN_RTN(!fmtp());
@@ -1064,50 +964,14 @@ public:
     }
     ASTGEN_MEMBERS_AstImplicit;
 };
-class AstInitArray final : public AstNode {
-    // Set a var to a map of values
-    // The list of initsp() is not relevant
-    // If default is specified, the vector may be sparse, and not provide each value.
-    // Key values are C++ array style, with lo() at index 0
-    // Parents: ASTVAR::init()
-    // @astgen op1 := defaultp : Optional[AstNode] // Default, if sparse
-    // @astgen op2 := initsp : List[AstNode] // Initial value expressions
-    //
-public:
-    using KeyItemMap = std::map<uint64_t, AstInitItem*>;
-
-private:
-    KeyItemMap m_map;  // Node value for each array index
-public:
-    AstInitArray(FileLine* fl, AstNodeDType* newDTypep, AstNode* defaultp)
-        : ASTGEN_SUPER_InitArray(fl) {
-        dtypep(newDTypep);
-        this->defaultp(defaultp);
-    }
-    ASTGEN_MEMBERS_AstInitArray;
-    void dump(std::ostream& str) const override;
-    const char* broken() const override;
-    void cloneRelink() override;
-    bool hasDType() const override { return true; }
-    bool same(const AstNode* samep) const override {
-        // Only works if exact same children, instead should override comparison
-        // of children list, and instead use map-vs-map key/value compare
-        return m_map == static_cast<const AstInitArray*>(samep)->m_map;
-    }
-    void addValuep(AstNode* newp) { addIndexValuep(m_map.size(), newp); }
-    const KeyItemMap& map() const { return m_map; }
-    void addIndexValuep(uint64_t index, AstNode* newp);
-    AstNode* getIndexValuep(uint64_t index) const;
-    AstNode* getIndexDefaultedValuep(uint64_t index) const;
-};
 class AstInitItem final : public AstNode {
     // Container for a item in an init array
     // This container is present so that the value underneath may get replaced with a new nodep
     // and the upper AstInitArray's map will remain correct (pointing to this InitItem)
-    // @astgen op1 := valuep : AstNode
+    // @astgen op1 := valuep : AstNodeExpr
 public:
     // Parents: INITARRAY
-    AstInitItem(FileLine* fl, AstNode* valuep)
+    AstInitItem(FileLine* fl, AstNodeExpr* valuep)
         : ASTGEN_SUPER_InitItem(fl) {
         this->valuep(valuep);
     }
@@ -1317,7 +1181,7 @@ public:
 };
 class AstPin final : public AstNode {
     // A port or parameter assignment on an instantiaton
-    // @astgen op1 := exprp : Optional[AstNode] // Expression connected (nullptr if unconnected)
+    // @astgen op1 := exprp : Optional[AstNode] // NodeExpr or NodeDType (nullptr if unconnected)
 private:
     int m_pinNum;  // Pin number
     string m_name;  // Pin name, or "" for number based interconnect
@@ -1353,7 +1217,7 @@ public:
 };
 class AstPort final : public AstNode {
     // A port (in/out/inout) on a module
-    // @astgen op1 := exprp : Optional[AstNode] // Expression connected to port
+    // @astgen op1 := exprp : Optional[AstNodeExpr] // Expression connected to port
     const int m_pinNum;  // Pin number
     const string m_name;  // Name of pin
 public:
@@ -1385,10 +1249,10 @@ class AstPropSpec final : public AstNode {
     // Parents:  ASSERT|COVER (property)
     // Children: SENITEM, Properties
     // @astgen op1 := sensesp : Optional[AstSenItem]
-    // @astgen op2 := disablep : Optional[AstNode]
+    // @astgen op2 := disablep : Optional[AstNodeExpr]
     // @astgen op3 := propp : AstNode
 public:
-    AstPropSpec(FileLine* fl, AstSenItem* sensesp, AstNode* disablep, AstNode* propp)
+    AstPropSpec(FileLine* fl, AstSenItem* sensesp, AstNodeExpr* disablep, AstNode* propp)
         : ASTGEN_SUPER_PropSpec(fl) {
         this->sensesp(sensesp);
         this->disablep(disablep);
@@ -1400,12 +1264,12 @@ public:
     }  // Used under Cover, which expects a bool child
 };
 class AstPull final : public AstNode {
-    // @astgen op1 := lhsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
 
     const bool m_direction;
 
 public:
-    AstPull(FileLine* fl, AstNode* lhsp, bool direction)
+    AstPull(FileLine* fl, AstNodeExpr* lhsp, bool direction)
         : ASTGEN_SUPER_Pull(fl)
         , m_direction{direction} {
         this->lhsp(lhsp);
@@ -1455,24 +1319,9 @@ public:
     AstVarScope* createTemp(const string& name, AstNodeDType* dtypep);
     AstVarScope* createTempLike(const string& name, AstVarScope* vscp);
 };
-class AstSelLoopVars final : public AstNode {
-    // Parser only concept "[id, id, id]" for a foreach statement
-    // Unlike normal selects elements is a list
-    // @astgen op1 := fromp : AstNode
-    // @astgen op2 := elementsp : List[AstNode]
-public:
-    AstSelLoopVars(FileLine* fl, AstNode* fromp, AstNode* elementsp)
-        : ASTGEN_SUPER_SelLoopVars(fl) {
-        this->fromp(fromp);
-        this->addElementsp(elementsp);
-    }
-    ASTGEN_MEMBERS_AstSelLoopVars;
-    bool same(const AstNode* /*samep*/) const override { return true; }
-    bool maybePointedTo() const override { return false; }
-};
 class AstSenItem final : public AstNode {
     // Parents:  SENTREE
-    // @astgen op1 := sensp : Optional[AstNode] // Sensitivity expression
+    // @astgen op1 := sensp : Optional[AstNodeExpr] // Sensitivity expression
     VEdgeType m_edgeType;  // Edge type
 public:
     class Combo {};  // for constructor type-overload selection
@@ -1481,7 +1330,7 @@ public:
     class Initial {};  // for constructor type-overload selection
     class Final {};  // for constructor type-overload selection
     class Never {};  // for constructor type-overload selection
-    AstSenItem(FileLine* fl, VEdgeType edgeType, AstNode* senp)
+    AstSenItem(FileLine* fl, VEdgeType edgeType, AstNodeExpr* senp)
         : ASTGEN_SUPER_SenItem(fl)
         , m_edgeType{edgeType} {
         this->sensp(senp);
@@ -1695,7 +1544,7 @@ class AstVar final : public AstNode {
     // @astgen op2 := delayp : Optional[AstDelay] // Net delay
     // Initial value that never changes (static const), or constructor argument for
     // MTASKSTATE variables
-    // @astgen op3 := valuep : Optional[AstNode]
+    // @astgen op3 := valuep : Optional[AstNode] // May be a DType for type parameter defaults
     // @astgen op4 := attrsp : List[AstNode] // Attributes during early parse
 
     string m_name;  // Name of variable
@@ -2381,7 +2230,7 @@ public:
 class AstBracketRange final : public AstNodeRange {
     // Parser only concept "[lhsp]", a AstUnknownRange, QueueRange or Range,
     // unknown until lhsp type is determined
-    // @astgen op1 := elementsp : AstNode
+    // @astgen op1 := elementsp : AstNode // Expr or DType
 public:
     AstBracketRange(FileLine* fl, AstNode* elementsp)
         : ASTGEN_SUPER_BracketRange(fl) {
@@ -2397,10 +2246,10 @@ public:
 };
 class AstRange final : public AstNodeRange {
     // Range specification, for use under variables and cells
-    // @astgen op1 := leftp : AstNode
-    // @astgen op2 := rightp : AstNode
+    // @astgen op1 := leftp : AstNodeExpr
+    // @astgen op2 := rightp : AstNodeExpr
 public:
-    AstRange(FileLine* fl, AstNode* leftp, AstNode* rightp)
+    AstRange(FileLine* fl, AstNodeExpr* leftp, AstNodeExpr* rightp)
         : ASTGEN_SUPER_Range(fl) {
         this->leftp(leftp);
         this->rightp(rightp);
@@ -2490,9 +2339,9 @@ public:
 };
 class AstCReturn final : public AstNodeStmt {
     // C++ return from a function
-    // @astgen op1 := lhsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
 public:
-    AstCReturn(FileLine* fl, AstNode* lhsp)
+    AstCReturn(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_CReturn(fl) {
         this->lhsp(lhsp);
     }
@@ -2516,7 +2365,6 @@ public:
 };
 class AstComment final : public AstNodeStmt {
     // Some comment to put into the output stream
-    // Parents:  {statement list}
     const string m_name;  // Text of comment
     const bool m_showAt;  // Show "at <fileline>"
 public:
@@ -2541,9 +2389,6 @@ public:
 };
 class AstCoverDecl final : public AstNodeStmt {
     // Coverage analysis point declaration
-    // Parents:  {statement list}
-    // Children: none
-private:
     AstCoverDecl* m_dataDeclp = nullptr;  // [After V3CoverageJoin] Pointer to duplicate
                                           // declaration to get data from instead
     string m_page;
@@ -2597,9 +2442,6 @@ public:
 };
 class AstCoverInc final : public AstNodeStmt {
     // Coverage analysis point; increment coverage count
-    // Parents:  {statement list}
-    // Children: none
-private:
     AstCoverDecl* m_declp;  // [After V3Coverage] Pointer to declaration
 public:
     AstCoverInc(FileLine* fl, AstCoverDecl* declp)
@@ -2628,10 +2470,10 @@ class AstCoverToggle final : public AstNodeStmt {
     // Toggle analysis of given signal
     // Parents:  MODULE
     // @astgen op1 := incp : AstCoverInc
-    // @astgen op2 := origp : AstNode
-    // @astgen op3 := changep : AstNode
+    // @astgen op2 := origp : AstNodeExpr
+    // @astgen op3 := changep : AstNodeExpr
 public:
-    AstCoverToggle(FileLine* fl, AstCoverInc* incp, AstNode* origp, AstNode* changep)
+    AstCoverToggle(FileLine* fl, AstCoverInc* incp, AstNodeExpr* origp, AstNodeExpr* changep)
         : ASTGEN_SUPER_CoverToggle(fl) {
         this->incp(incp);
         this->origp(origp);
@@ -2649,10 +2491,10 @@ public:
 };
 class AstDelay final : public AstNodeStmt {
     // Delay statement
-    // @astgen op1 := lhsp : AstNode // Delay value
+    // @astgen op1 := lhsp : AstNodeExpr // Delay value
     // @astgen op2 := stmtsp : List[AstNode] // Statements under delay
 public:
-    AstDelay(FileLine* fl, AstNode* lhsp)
+    AstDelay(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_Delay(fl) {
         this->lhsp(lhsp);
     }
@@ -2661,7 +2503,6 @@ public:
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
 class AstDisable final : public AstNodeStmt {
-private:
     string m_name;  // Name of block
 public:
     AstDisable(FileLine* fl, const string& name)
@@ -2684,19 +2525,19 @@ public:
 class AstDisplay final : public AstNodeStmt {
     // Parents: stmtlist
     // @astgen op1 := fmtp : AstSFormatF
-    // @astgen op2 := filep : Optional[AstNode] // file (must be a VarRef)
+    // @astgen op2 := filep : Optional[AstNodeExpr] // file (must resolve to a VarRef)
 private:
     VDisplayType m_displayType;
 
 public:
-    AstDisplay(FileLine* fl, VDisplayType dispType, const string& text, AstNode* filep,
-               AstNode* exprsp, char missingArgChar = 'd')
+    AstDisplay(FileLine* fl, VDisplayType dispType, const string& text, AstNodeExpr* filep,
+               AstNodeExpr* exprsp, char missingArgChar = 'd')
         : ASTGEN_SUPER_Display(fl)
         , m_displayType{dispType} {
         this->fmtp(new AstSFormatF{fl, text, true, exprsp, missingArgChar});
         this->filep(filep);
     }
-    AstDisplay(FileLine* fl, VDisplayType dispType, AstNode* filep, AstNode* exprsp,
+    AstDisplay(FileLine* fl, VDisplayType dispType, AstNodeExpr* filep, AstNodeExpr* exprsp,
                char missingArgChar = 'd')
         : ASTGEN_SUPER_Display(fl)
         , m_displayType{dispType} {
@@ -2729,11 +2570,11 @@ public:
 };
 class AstDoWhile final : public AstNodeStmt {
     // @astgen op1 := precondsp : List[AstNode]
-    // @astgen op2 := condp : AstNode
+    // @astgen op2 := condp : AstNodeExpr
     // @astgen op3 := stmtsp : List[AstNode]
     // @astgen op4 := incsp : List[AstNode]
 public:
-    AstDoWhile(FileLine* fl, AstNode* conditionp, AstNode* stmtsp = nullptr,
+    AstDoWhile(FileLine* fl, AstNodeExpr* conditionp, AstNode* stmtsp = nullptr,
                AstNode* incsp = nullptr)
         : ASTGEN_SUPER_DoWhile(fl) {
         condp(conditionp);
@@ -2750,10 +2591,10 @@ public:
 class AstDumpCtl final : public AstNodeStmt {
     // $dumpon etc
     // Parents: expr
-    // @astgen op1 := exprp : Optional[AstNode] // Expression based on type of control statement
+    // @astgen op1 := exprp : Optional[AstNodeExpr] // Expression based on type of statement
     const VDumpCtlType m_ctlType;  // Type of operation
 public:
-    AstDumpCtl(FileLine* fl, VDumpCtlType ctlType, AstNode* exprp = nullptr)
+    AstDumpCtl(FileLine* fl, VDumpCtlType ctlType, AstNodeExpr* exprp = nullptr)
         : ASTGEN_SUPER_DumpCtl(fl)
         , m_ctlType{ctlType} {
         this->exprp(exprp);
@@ -2784,9 +2625,9 @@ public:
 };
 class AstFClose final : public AstNodeStmt {
     // Parents: stmtlist
-    // @astgen op1 := filep : AstNode // file (must be a VarRef)
+    // @astgen op1 := filep : AstNodeExpr // file (must be a VarRef)
 public:
-    AstFClose(FileLine* fl, AstNode* filep)
+    AstFClose(FileLine* fl, AstNodeExpr* filep)
         : ASTGEN_SUPER_FClose(fl) {
         this->filep(filep);
     }
@@ -2801,9 +2642,9 @@ public:
 };
 class AstFFlush final : public AstNodeStmt {
     // Parents: stmtlist
-    // @astgen op1 := filep : Optional[AstNode] // file (must be a VarRef)
+    // @astgen op1 := filep : Optional[AstNodeExpr] // file (must be a VarRef)
 public:
-    AstFFlush(FileLine* fl, AstNode* filep)
+    AstFFlush(FileLine* fl, AstNodeExpr* filep)
         : ASTGEN_SUPER_FFlush(fl) {
         this->filep(filep);
     }
@@ -2818,11 +2659,11 @@ public:
 };
 class AstFOpen final : public AstNodeStmt {
     // Although a system function in IEEE, here a statement which sets the file pointer (MCD)
-    // @astgen op1 := filep : AstNode
-    // @astgen op2 := filenamep : AstNode
-    // @astgen op3 := modep : AstNode
+    // @astgen op1 := filep : AstNodeExpr
+    // @astgen op2 := filenamep : AstNodeExpr
+    // @astgen op3 := modep : AstNodeExpr
 public:
-    AstFOpen(FileLine* fl, AstNode* filep, AstNode* filenamep, AstNode* modep)
+    AstFOpen(FileLine* fl, AstNodeExpr* filep, AstNodeExpr* filenamep, AstNodeExpr* modep)
         : ASTGEN_SUPER_FOpen(fl) {
         this->filep(filep);
         this->filenamep(filenamep);
@@ -2839,10 +2680,10 @@ public:
 };
 class AstFOpenMcd final : public AstNodeStmt {
     // Although a system function in IEEE, here a statement which sets the file pointer (MCD)
-    // @astgen op1 := filep : AstNode
-    // @astgen op2 := filenamep : AstNode
+    // @astgen op1 := filep : AstNodeExpr
+    // @astgen op2 := filenamep : AstNodeExpr
 public:
-    AstFOpenMcd(FileLine* fl, AstNode* filep, AstNode* filenamep)
+    AstFOpenMcd(FileLine* fl, AstNodeExpr* filep, AstNodeExpr* filenamep)
         : ASTGEN_SUPER_FOpenMcd(fl) {
         this->filep(filep);
         this->filenamep(filenamep);
@@ -2871,10 +2712,10 @@ public:
 };
 class AstFireEvent final : public AstNodeStmt {
     // '-> _' and '->> _' event trigger statements
-    // @astgen op1 := operandp : AstNode
+    // @astgen op1 := operandp : AstNodeExpr
     const bool m_delayed;  // Delayed (->>) vs non-delayed (->)
 public:
-    AstFireEvent(FileLine* fl, AstNode* operandp, bool delayed)
+    AstFireEvent(FileLine* fl, AstNodeExpr* operandp, bool delayed)
         : ASTGEN_SUPER_FireEvent(fl)
         , m_delayed{delayed} {
         this->operandp(operandp);
@@ -3026,19 +2867,19 @@ public:
 };
 class AstRelease final : public AstNodeStmt {
     // Procedural 'release' statement
-    // @astgen op1 := lhsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
 public:
-    AstRelease(FileLine* fl, AstNode* lhsp)
+    AstRelease(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_Release(fl) {
         this->lhsp(lhsp);
     }
     ASTGEN_MEMBERS_AstRelease;
 };
 class AstRepeat final : public AstNodeStmt {
-    // @astgen op1 := countp : AstNode
+    // @astgen op1 := countp : AstNodeExpr
     // @astgen op2 := stmtsp : List[AstNode]
 public:
-    AstRepeat(FileLine* fl, AstNode* countp, AstNode* stmtsp)
+    AstRepeat(FileLine* fl, AstNodeExpr* countp, AstNode* stmtsp)
         : ASTGEN_SUPER_Repeat(fl) {
         this->countp(countp);
         this->addStmtsp(stmtsp);
@@ -3050,9 +2891,9 @@ public:
     bool isFirstInMyListOfStatements(AstNode* n) const override { return n == stmtsp(); }
 };
 class AstReturn final : public AstNodeStmt {
-    // @astgen op1 := lhsp : Optional[AstNode]
+    // @astgen op1 := lhsp : Optional[AstNodeExpr]
 public:
-    explicit AstReturn(FileLine* fl, AstNode* lhsp = nullptr)
+    explicit AstReturn(FileLine* fl, AstNodeExpr* lhsp = nullptr)
         : ASTGEN_SUPER_Return(fl) {
         this->lhsp(lhsp);
     }
@@ -3065,15 +2906,15 @@ public:
 class AstSFormat final : public AstNodeStmt {
     // Parents: statement container
     // @astgen op1 := fmtp : AstSFormatF
-    // @astgen op2 := lhsp : AstNode
+    // @astgen op2 := lhsp : AstNodeExpr
 public:
-    AstSFormat(FileLine* fl, AstNode* lhsp, const string& text, AstNode* exprsp,
+    AstSFormat(FileLine* fl, AstNodeExpr* lhsp, const string& text, AstNodeExpr* exprsp,
                char missingArgChar = 'd')
         : ASTGEN_SUPER_SFormat(fl) {
         this->fmtp(new AstSFormatF{fl, text, true, exprsp, missingArgChar});
         this->lhsp(lhsp);
     }
-    AstSFormat(FileLine* fl, AstNode* lhsp, AstNode* exprsp, char missingArgChar = 'd')
+    AstSFormat(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* exprsp, char missingArgChar = 'd')
         : ASTGEN_SUPER_SFormat(fl) {
         this->fmtp(new AstSFormatF{fl, AstSFormatF::NoFormat(), exprsp, missingArgChar});
         this->lhsp(lhsp);
@@ -3130,10 +2971,11 @@ public:
     bool same(const AstNode* samep) const override { return fileline() == samep->fileline(); }
 };
 class AstSysFuncAsTask final : public AstNodeStmt {
+    // TODO: This is superseded by AstStmtExpr, remove
     // Call what is normally a system function (with a return) in a non-return context
-    // @astgen op1 := lhsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
 public:
-    AstSysFuncAsTask(FileLine* fl, AstNode* lhsp)
+    AstSysFuncAsTask(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_SysFuncAsTask(fl) {
         this->lhsp(lhsp);
     }
@@ -3148,9 +2990,9 @@ public:
 };
 class AstSystemT final : public AstNodeStmt {
     // $system used as task
-    // @astgen op1 := lhsp : AstNode
+    // @astgen op1 := lhsp : AstNodeExpr
 public:
-    AstSystemT(FileLine* fl, AstNode* lhsp)
+    AstSystemT(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_SystemT(fl) {
         this->lhsp(lhsp);
     }
@@ -3165,13 +3007,13 @@ public:
 };
 class AstTimeFormat final : public AstNodeStmt {
     // Parents: stmtlist
-    // @astgen op1 := unitsp : AstNode
-    // @astgen op2 := precisionp : AstNode
-    // @astgen op3 := suffixp : AstNode
-    // @astgen op4 := widthp : AstNode
+    // @astgen op1 := unitsp : AstNodeExpr
+    // @astgen op2 := precisionp : AstNodeExpr
+    // @astgen op3 := suffixp : AstNodeExpr
+    // @astgen op4 := widthp : AstNodeExpr
 public:
-    AstTimeFormat(FileLine* fl, AstNode* unitsp, AstNode* precisionp, AstNode* suffixp,
-                  AstNode* widthp)
+    AstTimeFormat(FileLine* fl, AstNodeExpr* unitsp, AstNodeExpr* precisionp, AstNodeExpr* suffixp,
+                  AstNodeExpr* widthp)
         : ASTGEN_SUPER_TimeFormat(fl) {
         this->unitsp(unitsp);
         this->precisionp(precisionp);
@@ -3191,7 +3033,7 @@ class AstTraceDecl final : public AstNodeStmt {
     // Separate from AstTraceInc; as a declaration can't be deleted
     // Parents:  {statement list}
     // Expression being traced - Moved to AstTraceInc by V3Trace
-    // @astgen op1 := valuep : Optional[AstNode]
+    // @astgen op1 := valuep : Optional[AstNodeExpr]
 private:
     uint32_t m_code = 0;  // Trace identifier code; converted to ASCII by trace routines
     const string m_showname;  // Name of variable
@@ -3204,7 +3046,7 @@ private:
 public:
     AstTraceDecl(FileLine* fl, const string& showname,
                  AstVar* varp,  // For input/output state etc
-                 AstNode* valuep, const VNumRange& bitRange, const VNumRange& arrayRange)
+                 AstNodeExpr* valuep, const VNumRange& bitRange, const VNumRange& arrayRange)
         : ASTGEN_SUPER_TraceDecl(fl)
         , m_showname{showname}
         , m_bitRange{bitRange}
@@ -3239,7 +3081,7 @@ public:
 class AstTraceInc final : public AstNodeStmt {
     // Trace point dump
     // @astgen op1 := precondsp : List[AstNode] // Statements to emit before this node
-    // @astgen op2 := valuep : AstNode // Expression being traced (from decl)
+    // @astgen op2 := valuep : AstNodeExpr // Expression being traced (from decl)
 
 private:
     AstTraceDecl* m_declp;  // Pointer to declaration
@@ -3300,7 +3142,7 @@ public:
 };
 class AstUCStmt final : public AstNodeStmt {
     // User $c statement
-    // @astgen op1 := exprsp : List[AstNode]
+    // @astgen op1 := exprsp : List[AstNode] // (some are AstText)
 public:
     AstUCStmt(FileLine* fl, AstNode* exprsp)
         : ASTGEN_SUPER_UCStmt(fl) {
@@ -3314,10 +3156,10 @@ public:
     bool same(const AstNode* /*samep*/) const override { return true; }
 };
 class AstWait final : public AstNodeStmt {
-    // @astgen op1 := condp : AstNode
+    // @astgen op1 := condp : AstNodeExpr
     // @astgen op2 := stmtsp : List[AstNode]
 public:
-    AstWait(FileLine* fl, AstNode* condp, AstNode* stmtsp)
+    AstWait(FileLine* fl, AstNodeExpr* condp, AstNode* stmtsp)
         : ASTGEN_SUPER_Wait(fl) {
         this->condp(condp);
         this->addStmtsp(stmtsp);
@@ -3335,11 +3177,11 @@ public:
 };
 class AstWhile final : public AstNodeStmt {
     // @astgen op1 := precondsp : List[AstNode]
-    // @astgen op2 := condp : AstNode
+    // @astgen op2 := condp : AstNodeExpr
     // @astgen op3 := stmtsp : List[AstNode]
     // @astgen op4 := incsp : List[AstNode]
 public:
-    AstWhile(FileLine* fl, AstNode* condp, AstNode* stmtsp = nullptr, AstNode* incsp = nullptr)
+    AstWhile(FileLine* fl, AstNodeExpr* condp, AstNode* stmtsp = nullptr, AstNode* incsp = nullptr)
         : ASTGEN_SUPER_While(fl) {
         this->condp(condp);
         this->addStmtsp(stmtsp);
@@ -3355,43 +3197,17 @@ public:
     void addNextStmt(AstNode* newp, AstNode* belowp) override;
     bool isFirstInMyListOfStatements(AstNode* n) const override { return n == stmtsp(); }
 };
-class AstWith final : public AstNodeStmt {
-    // Used as argument to method, then to AstCMethodHard
-    // dtypep() contains the with lambda's return dtype
-    // Parents: funcref (similar to AstArg)
-    // Children: LambdaArgRef that declares the item variable
-    // Children: LambdaArgRef that declares the item.index variable
-    // Children: expression (equation establishing the with)
-    // @astgen op1 := indexArgRefp : AstLambdaArgRef
-    // @astgen op2 := valueArgRefp : AstLambdaArgRef
-    // @astgen op3 := exprp : AstNode
-public:
-    AstWith(FileLine* fl, AstLambdaArgRef* indexArgRefp, AstLambdaArgRef* valueArgRefp,
-            AstNode* exprp)
-        : ASTGEN_SUPER_With(fl) {
-        this->indexArgRefp(indexArgRefp);
-        this->valueArgRefp(valueArgRefp);
-        this->exprp(exprp);
-    }
-    ASTGEN_MEMBERS_AstWith;
-    bool same(const AstNode* /*samep*/) const override { return true; }
-    bool hasDType() const override { return true; }
-    const char* broken() const override {
-        BROKEN_RTN(!indexArgRefp());  // varp needed to know lambda's arg dtype
-        BROKEN_RTN(!valueArgRefp());  // varp needed to know lambda's arg dtype
-        return nullptr;
-    }
-};
 
 // === AstNodeAssign ===
 class AstAssign final : public AstNodeAssign {
 public:
-    AstAssign(FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* timingControlp = nullptr)
+    AstAssign(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp,
+              AstNode* timingControlp = nullptr)
         : ASTGEN_SUPER_Assign(fl, lhsp, rhsp, timingControlp) {
         dtypeFrom(lhsp);
     }
     ASTGEN_MEMBERS_AstAssign;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         AstNode* const controlp = timingControlp() ? timingControlp()->cloneTree(false) : nullptr;
         return new AstAssign{fileline(), lhsp, rhsp, controlp};
     }
@@ -3402,17 +3218,20 @@ class AstAssignAlias final : public AstNodeAssign {
     // If both sides are wires, there's no LHS vs RHS,
 public:
     AstAssignAlias(FileLine* fl, AstVarRef* lhsp, AstVarRef* rhsp)
-        : ASTGEN_SUPER_AssignAlias(fl, (AstNode*)lhsp, (AstNode*)rhsp) {}
+        : ASTGEN_SUPER_AssignAlias(fl, (AstNodeExpr*)lhsp, (AstNodeExpr*)rhsp) {}
     ASTGEN_MEMBERS_AstAssignAlias;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override { V3ERROR_NA_RETURN(nullptr); }
+    AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
+        V3ERROR_NA_RETURN(nullptr);
+    }
     bool brokeLhsMustBeLvalue() const override { return false; }
 };
 class AstAssignDly final : public AstNodeAssign {
 public:
-    AstAssignDly(FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* timingControlp = nullptr)
+    AstAssignDly(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp,
+                 AstNode* timingControlp = nullptr)
         : ASTGEN_SUPER_AssignDly(fl, lhsp, rhsp, timingControlp) {}
     ASTGEN_MEMBERS_AstAssignDly;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         AstNode* const controlp = timingControlp() ? timingControlp()->cloneTree(false) : nullptr;
         return new AstAssignDly{fileline(), lhsp, rhsp, controlp};
     }
@@ -3423,10 +3242,10 @@ public:
 class AstAssignForce final : public AstNodeAssign {
     // Procedural 'force' statement
 public:
-    AstAssignForce(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstAssignForce(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_AssignForce(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstAssignForce;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstAssignForce{fileline(), lhsp, rhsp};
     }
     bool brokeLhsMustBeLvalue() const override { return true; }
@@ -3434,10 +3253,10 @@ public:
 class AstAssignPost final : public AstNodeAssign {
     // Like Assign, but predelayed assignment requiring special order handling
 public:
-    AstAssignPost(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstAssignPost(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_AssignPost(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstAssignPost;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstAssignPost{fileline(), lhsp, rhsp};
     }
     bool brokeLhsMustBeLvalue() const override { return true; }
@@ -3445,10 +3264,10 @@ public:
 class AstAssignPre final : public AstNodeAssign {
     // Like Assign, but predelayed assignment requiring special order handling
 public:
-    AstAssignPre(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstAssignPre(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_AssignPre(fl, lhsp, rhsp) {}
     ASTGEN_MEMBERS_AstAssignPre;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstAssignPre{fileline(), lhsp, rhsp};
     }
     bool brokeLhsMustBeLvalue() const override { return true; }
@@ -3456,12 +3275,12 @@ public:
 class AstAssignVarScope final : public AstNodeAssign {
     // Assign two VarScopes to each other
 public:
-    AstAssignVarScope(FileLine* fl, AstNode* lhsp, AstNode* rhsp)
+    AstAssignVarScope(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_AssignVarScope(fl, lhsp, rhsp) {
         dtypeFrom(rhsp);
     }
     ASTGEN_MEMBERS_AstAssignVarScope;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         return new AstAssignVarScope{fileline(), lhsp, rhsp};
     }
     bool brokeLhsMustBeLvalue() const override { return false; }
@@ -3470,10 +3289,11 @@ class AstAssignW final : public AstNodeAssign {
     // Like assign, but wire/assign's in verilog, the only setting of the specified variable
     // @astgen op4 := strengthSpecp : Optional[AstStrengthSpec]
 public:
-    AstAssignW(FileLine* fl, AstNode* lhsp, AstNode* rhsp, AstNode* timingControlp = nullptr)
+    AstAssignW(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp,
+               AstNode* timingControlp = nullptr)
         : ASTGEN_SUPER_AssignW(fl, lhsp, rhsp, timingControlp) {}
     ASTGEN_MEMBERS_AstAssignW;
-    AstNode* cloneType(AstNode* lhsp, AstNode* rhsp) override {
+    AstNodeAssign* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
         AstNode* const controlp = timingControlp() ? timingControlp()->cloneTree(false) : nullptr;
         return new AstAssignW{fileline(), lhsp, rhsp, controlp};
     }
@@ -3489,8 +3309,6 @@ public:
 // === AstNodeCase ===
 class AstCase final : public AstNodeCase {
     // Case statement
-    // Parents:  {statement list}
-private:
     VCaseType m_casex;  // 0=case, 1=casex, 2=casez
     bool m_fullPragma = false;  // Synthesis full_case
     bool m_parallelPragma = false;  // Synthesis parallel_case
@@ -3498,7 +3316,7 @@ private:
     bool m_unique0Pragma = false;  // unique0 case
     bool m_priorityPragma = false;  // priority case
 public:
-    AstCase(FileLine* fl, VCaseType casex, AstNode* exprp, AstCaseItem* itemsp)
+    AstCase(FileLine* fl, VCaseType casex, AstNodeExpr* exprp, AstCaseItem* itemsp)
         : ASTGEN_SUPER_Case(fl, exprp, itemsp)
         , m_casex{casex} {}
     ASTGEN_MEMBERS_AstCase;
@@ -3524,9 +3342,8 @@ public:
 };
 class AstGenCase final : public AstNodeCase {
     // Generate Case statement
-    // Parents:  {statement list}
 public:
-    AstGenCase(FileLine* fl, AstNode* exprp, AstCaseItem* itemsp)
+    AstGenCase(FileLine* fl, AstNodeExpr* exprp, AstCaseItem* itemsp)
         : ASTGEN_SUPER_GenCase(fl, exprp, itemsp) {}
     ASTGEN_MEMBERS_AstGenCase;
 };
@@ -3572,7 +3389,7 @@ public:
 // === AstNodeFor ===
 class AstGenFor final : public AstNodeFor {
 public:
-    AstGenFor(FileLine* fl, AstNode* initsp, AstNode* condp, AstNode* incsp, AstNode* stmtsp)
+    AstGenFor(FileLine* fl, AstNode* initsp, AstNodeExpr* condp, AstNode* incsp, AstNode* stmtsp)
         : ASTGEN_SUPER_GenFor(fl, initsp, condp, incsp, stmtsp) {}
     ASTGEN_MEMBERS_AstGenFor;
 };
@@ -3580,7 +3397,7 @@ public:
 // === AstNodeIf ===
 class AstGenIf final : public AstNodeIf {
 public:
-    AstGenIf(FileLine* fl, AstNode* condp, AstNode* thensp, AstNode* elsesp)
+    AstGenIf(FileLine* fl, AstNodeExpr* condp, AstNode* thensp, AstNode* elsesp)
         : ASTGEN_SUPER_GenIf(fl, condp, thensp, elsesp) {}
     ASTGEN_MEMBERS_AstGenIf;
 };
@@ -3590,7 +3407,7 @@ private:
     bool m_unique0Pragma = false;  // unique0 case
     bool m_priorityPragma = false;  // priority case
 public:
-    AstIf(FileLine* fl, AstNode* condp, AstNode* thensp = nullptr, AstNode* elsesp = nullptr)
+    AstIf(FileLine* fl, AstNodeExpr* condp, AstNode* thensp = nullptr, AstNode* elsesp = nullptr)
         : ASTGEN_SUPER_If(fl, condp, thensp, elsesp) {}
     ASTGEN_MEMBERS_AstIf;
     bool uniquePragma() const { return m_uniquePragma; }
@@ -3604,8 +3421,8 @@ public:
 // === AstNodeReadWriteMem ===
 class AstReadMem final : public AstNodeReadWriteMem {
 public:
-    AstReadMem(FileLine* fl, bool hex, AstNode* filenamep, AstNode* memp, AstNode* lsbp,
-               AstNode* msbp)
+    AstReadMem(FileLine* fl, bool hex, AstNodeExpr* filenamep, AstNodeExpr* memp,
+               AstNodeExpr* lsbp, AstNodeExpr* msbp)
         : ASTGEN_SUPER_ReadMem(fl, hex, filenamep, memp, lsbp, msbp) {}
     ASTGEN_MEMBERS_AstReadMem;
     string verilogKwd() const override { return (isHex() ? "$readmemh" : "$readmemb"); }
@@ -3613,8 +3430,8 @@ public:
 };
 class AstWriteMem final : public AstNodeReadWriteMem {
 public:
-    AstWriteMem(FileLine* fl, bool hex, AstNode* filenamep, AstNode* memp, AstNode* lsbp,
-                AstNode* msbp)
+    AstWriteMem(FileLine* fl, bool hex, AstNodeExpr* filenamep, AstNodeExpr* memp,
+                AstNodeExpr* lsbp, AstNodeExpr* msbp)
         : ASTGEN_SUPER_WriteMem(fl, hex, filenamep, memp, lsbp, msbp) {}
     ASTGEN_MEMBERS_AstWriteMem;
     string verilogKwd() const override { return (isHex() ? "$writememh" : "$writememb"); }
diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index c3083a152..9c84cdb2d 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -252,7 +252,7 @@ int AstNodeUOrStructDType::widthAlignBytes() const {
     }
 }
 
-AstNodeBiop* AstEq::newTyped(FileLine* fl, AstNode* lhsp, AstNode* rhsp) {
+AstNodeBiop* AstEq::newTyped(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp) {
     if (lhsp->isString() && rhsp->isString()) {
         return new AstEqN(fl, lhsp, rhsp);
     } else if (lhsp->isDouble() && rhsp->isDouble()) {
@@ -262,7 +262,7 @@ AstNodeBiop* AstEq::newTyped(FileLine* fl, AstNode* lhsp, AstNode* rhsp) {
     }
 }
 
-AstNodeBiop* AstEqWild::newTyped(FileLine* fl, AstNode* lhsp, AstNode* rhsp) {
+AstNodeBiop* AstEqWild::newTyped(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp) {
     if (lhsp->isString() && rhsp->isString()) {
         return new AstEqN(fl, lhsp, rhsp);
     } else if (lhsp->isDouble() && rhsp->isDouble()) {
@@ -279,13 +279,13 @@ AstExecGraph::AstExecGraph(FileLine* fileline, const string& name)
 
 AstExecGraph::~AstExecGraph() { VL_DO_DANGLING(delete m_depGraphp, m_depGraphp); }
 
-AstNode* AstInsideRange::newAndFromInside(AstNode* exprp, AstNode* lhsp, AstNode* rhsp) {
-    AstNode* const ap = new AstGte(fileline(), exprp->cloneTree(true), lhsp);
-    AstNode* const bp = new AstLte(fileline(), exprp->cloneTree(true), rhsp);
+AstNodeExpr* AstInsideRange::newAndFromInside(AstNodeExpr* exprp, AstNodeExpr* lhsp,
+                                              AstNodeExpr* rhsp) {
+    AstNodeExpr* const ap = new AstGte{fileline(), exprp->cloneTree(true), lhsp};
+    AstNodeExpr* const bp = new AstLte{fileline(), exprp->cloneTree(true), rhsp};
     ap->fileline()->modifyWarnOff(V3ErrorCode::UNSIGNED, true);
     bp->fileline()->modifyWarnOff(V3ErrorCode::CMPCONST, true);
-    AstNode* const newp = new AstAnd(fileline(), ap, bp);
-    return newp;
+    return new AstAnd(fileline(), ap, bp);
 }
 
 AstConst* AstConst::parseParamLiteral(FileLine* fl, const string& literal) {
@@ -1122,7 +1122,7 @@ const char* AstConstPool::broken() const {
     return nullptr;
 }
 
-AstVarScope* AstConstPool::createNewEntry(const string& name, AstNode* initp) {
+AstVarScope* AstConstPool::createNewEntry(const string& name, AstNodeExpr* initp) {
     FileLine* const fl = initp->fileline();
     AstVar* const varp = new AstVar(fl, VVarType::MODULETEMP, name, initp->dtypep());
     varp->isConst(true);
@@ -1575,7 +1575,7 @@ void AstInitArray::cloneRelink() {
         if (it->second->clonep()) it->second = it->second->clonep();
     }
 }
-void AstInitArray::addIndexValuep(uint64_t index, AstNode* newp) {
+void AstInitArray::addIndexValuep(uint64_t index, AstNodeExpr* newp) {
     const auto it = m_map.find(index);
     if (it != m_map.end()) {
         it->second->valuep(newp);
@@ -1585,7 +1585,7 @@ void AstInitArray::addIndexValuep(uint64_t index, AstNode* newp) {
         addInitsp(itemp);
     }
 }
-AstNode* AstInitArray::getIndexValuep(uint64_t index) const {
+AstNodeExpr* AstInitArray::getIndexValuep(uint64_t index) const {
     const auto it = m_map.find(index);
     if (it == m_map.end()) {
         return nullptr;
@@ -1593,8 +1593,8 @@ AstNode* AstInitArray::getIndexValuep(uint64_t index) const {
         return it->second->valuep();
     }
 }
-AstNode* AstInitArray::getIndexDefaultedValuep(uint64_t index) const {
-    AstNode* valuep = getIndexValuep(index);
+AstNodeExpr* AstInitArray::getIndexDefaultedValuep(uint64_t index) const {
+    AstNodeExpr* valuep = getIndexValuep(index);
     if (!valuep) valuep = defaultp();
     return valuep;
 }
@@ -2302,8 +2302,8 @@ void AstCUse::dump(std::ostream& str) const {
 
 AstAlways* AstAssignW::convertToAlways() {
     const bool hasTimingControl = isTimingControl();
-    AstNode* const lhs1p = lhsp()->unlinkFrBack();
-    AstNode* const rhs1p = rhsp()->unlinkFrBack();
+    AstNodeExpr* const lhs1p = lhsp()->unlinkFrBack();
+    AstNodeExpr* const rhs1p = rhsp()->unlinkFrBack();
     AstNode* const controlp = timingControlp() ? timingControlp()->unlinkFrBack() : nullptr;
     FileLine* const flp = fileline();
     AstNode* bodysp = new AstAssign{flp, lhs1p, rhs1p, controlp};
diff --git a/src/V3CCtors.cpp b/src/V3CCtors.cpp
index f1e5b1bca..585c23a19 100644
--- a/src/V3CCtors.cpp
+++ b/src/V3CCtors.cpp
@@ -152,7 +152,7 @@ void V3CCtors::evalAsserts() {
                         AstVarRef* const vrefp
                             = new AstVarRef{varp->fileline(), varp, VAccess::READ};
                         vrefp->selfPointer("this");
-                        AstNode* newp = vrefp;
+                        AstNodeExpr* newp = vrefp;
                         if (varp->isWide()) {
                             newp = new AstWordSel{
                                 varp->fileline(), newp,
@@ -167,8 +167,7 @@ void V3CCtors::evalAsserts() {
                             new AstCStmt{varp->fileline(), "Verilated::overWidthError(\""
                                                                + varp->prettyName() + "\");"}};
                         ifp->branchPred(VBranchPred::BP_UNLIKELY);
-                        newp = ifp;
-                        funcp->addStmtsp(newp);
+                        funcp->addStmtsp(ifp);
                     }
                 }
             }
diff --git a/src/V3Case.cpp b/src/V3Case.cpp
index 258f76e0d..1537a14ee 100644
--- a/src/V3Case.cpp
+++ b/src/V3Case.cpp
@@ -250,7 +250,7 @@ private:
         return true;  // All is fine
     }
 
-    AstNode* replaceCaseFastRecurse(AstNode* cexprp, int msb, uint32_t upperValue) {
+    AstNode* replaceCaseFastRecurse(AstNodeExpr* cexprp, int msb, uint32_t upperValue) {
         if (msb < 0) {
             // There's no space for a IF.  We know upperValue is thus down to a specific
             // exact value, so just return the tree value
@@ -290,9 +290,9 @@ private:
             // V3Number nummask (cexprp, cexprp->width(), (1UL<<msb));
             // AstNode* and1p = new AstAnd(cexprp->fileline(), cexprp->cloneTree(false),
             //                            new AstConst(cexprp->fileline(), nummask));
-            AstNode* const and1p
+            AstNodeExpr* const and1p
                 = new AstSel(cexprp->fileline(), cexprp->cloneTree(false), msb, 1);
-            AstNode* const eqp
+            AstNodeExpr* const eqp
                 = new AstNeq(cexprp->fileline(), new AstConst(cexprp->fileline(), 0), and1p);
             AstIf* const ifp = new AstIf(cexprp->fileline(), eqp, tree1p, tree0p);
             ifp->user3(1);  // So we don't bother to clone it
@@ -304,7 +304,7 @@ private:
         // CASEx(cexpr,....
         // ->  tree of IF(msb,  IF(msb-1, 11, 10)
         //                      IF(msb-1, 01, 00))
-        AstNode* const cexprp = nodep->exprp()->unlinkFrBack();
+        AstNodeExpr* const cexprp = nodep->exprp()->unlinkFrBack();
 
         if (debug() >= 9) {  // LCOV_EXCL_START
             for (uint32_t i = 0; i < (1UL << m_caseWidth); ++i) {
@@ -337,7 +337,7 @@ private:
         // ->  IF((cexpr==icond1),istmts1,
         //                       IF((EQ (AND MASK cexpr) (AND MASK icond1)
         //                              ,istmts2, istmts3
-        AstNode* const cexprp = nodep->exprp()->unlinkFrBack();
+        AstNodeExpr* const cexprp = nodep->exprp()->unlinkFrBack();
         // We'll do this in two stages.  First stage, convert the conditions to
         // the appropriate IF AND terms.
         if (debug() >= 9) nodep->dumpTree(cout, "    _comp_IN:   ");
@@ -350,13 +350,13 @@ private:
                 hadDefault = true;
             } else {
                 // Expressioned clause
-                AstNode* icondNextp = nullptr;
-                AstNode* ifexprp = nullptr;  // If expression to test
-                for (AstNode* icondp = itemp->condsp(); icondp; icondp = icondNextp) {
-                    icondNextp = icondp->nextp();
+                AstNodeExpr* icondNextp = nullptr;
+                AstNodeExpr* ifexprp = nullptr;  // If expression to test
+                for (AstNodeExpr* icondp = itemp->condsp(); icondp; icondp = icondNextp) {
+                    icondNextp = VN_AS(icondp->nextp(), NodeExpr);
                     icondp->unlinkFrBack();
 
-                    AstNode* condp = nullptr;  // Default is to use and1p/and2p
+                    AstNodeExpr* condp = nullptr;  // Default is to use and1p/and2p
                     AstConst* const iconstp = VN_CAST(icondp, Const);
                     if (iconstp && neverItem(nodep, iconstp)) {
                         // X in casez can't ever be executed
@@ -375,10 +375,10 @@ private:
                         nummask.opBitsNonX(iconstp->num());
                         V3Number numval(itemp, iconstp->width());
                         numval.opBitsOne(iconstp->num());
-                        AstNode* const and1p
+                        AstNodeExpr* const and1p
                             = new AstAnd(itemp->fileline(), cexprp->cloneTree(false),
                                          new AstConst(itemp->fileline(), nummask));
-                        AstNode* const and2p = new AstAnd(
+                        AstNodeExpr* const and2p = new AstAnd(
                             itemp->fileline(), new AstConst(itemp->fileline(), numval),
                             new AstConst(itemp->fileline(), nummask));
                         VL_DO_DANGLING(icondp->deleteTree(), icondp);
@@ -386,8 +386,8 @@ private:
                         condp = AstEq::newTyped(itemp->fileline(), and1p, and2p);
                     } else {
                         // Not a caseX mask, we can build CASEEQ(cexpr icond)
-                        AstNode* const and1p = cexprp->cloneTree(false);
-                        AstNode* const and2p = icondp;
+                        AstNodeExpr* const and1p = cexprp->cloneTree(false);
+                        AstNodeExpr* const and2p = icondp;
                         condp = AstEq::newTyped(itemp->fileline(), and1p, and2p);
                     }
                     if (!ifexprp) {
@@ -423,7 +423,7 @@ private:
             AstNode* const istmtsp = itemp->stmtsp();  // Maybe null -- no action.
             if (istmtsp) istmtsp->unlinkFrBackWithNext();
             // Expressioned clause
-            AstNode* const ifexprp = itemp->condsp()->unlinkFrBack();
+            AstNodeExpr* const ifexprp = itemp->condsp()->unlinkFrBack();
             {  // Prepare for next group
                 if (++depth > CASE_ENCODER_GROUP_DEPTH) depth = 1;
                 if (depth == 1) {  // First group or starting new group
@@ -436,13 +436,13 @@ private:
                     }
                     groupnextp = newp;
                 } else {  // Continue group, modify if condition to OR in this new condition
-                    AstNode* const condp = groupnextp->condp()->unlinkFrBack();
+                    AstNodeExpr* const condp = groupnextp->condp()->unlinkFrBack();
                     groupnextp->condp(
                         new AstOr(ifexprp->fileline(), condp, ifexprp->cloneTree(true)));
                 }
             }
             {  // Make the new lower IF and attach in the tree
-                AstNode* itemexprp = ifexprp;
+                AstNodeExpr* itemexprp = ifexprp;
                 VL_DANGLING(ifexprp);
                 if (depth == CASE_ENCODER_GROUP_DEPTH) {  // End of group - can skip the condition
                     VL_DO_DANGLING(itemexprp->deleteTree(), itemexprp);
diff --git a/src/V3Cast.cpp b/src/V3Cast.cpp
index 0db4e7578..89563eb5c 100644
--- a/src/V3Cast.cpp
+++ b/src/V3Cast.cpp
@@ -63,7 +63,7 @@ private:
 
     // METHODS
 
-    void insertCast(AstNode* nodep, int needsize) {  // We'll insert ABOVE passed node
+    void insertCast(AstNodeExpr* nodep, int needsize) {  // We'll insert ABOVE passed node
         UINFO(4, "  NeedCast " << nodep << endl);
         VNRelinker relinkHandle;
         nodep->unlinkFrBack(&relinkHandle);
@@ -87,7 +87,7 @@ private:
             return VL_IDATASIZE;
         }
     }
-    void ensureCast(AstNode* nodep) {
+    void ensureCast(AstNodeExpr* nodep) {
         if (castSize(nodep->backp()) != castSize(nodep) || !nodep->user1()) {
             insertCast(nodep, castSize(nodep->backp()));
         }
@@ -101,13 +101,12 @@ private:
             insertCast(nodep->lhsp(), VL_IDATASIZE);
         }
     }
-    void ensureNullChecked(AstNode* nodep) {
+    void ensureNullChecked(AstNodeExpr* nodep) {
         // TODO optimize to track null checked values and avoid where possible
         if (!VN_IS(nodep->backp(), NullCheck)) {
             VNRelinker relinkHandle;
             nodep->unlinkFrBack(&relinkHandle);
-            AstNode* const newp = new AstNullCheck{nodep->fileline(), nodep};
-            relinkHandle.relink(newp);
+            relinkHandle.relink(new AstNullCheck{nodep->fileline(), nodep});
         }
     }
 
diff --git a/src/V3Clean.cpp b/src/V3Clean.cpp
index db31e87fb..626a1d9ca 100644
--- a/src/V3Clean.cpp
+++ b/src/V3Clean.cpp
@@ -121,7 +121,7 @@ private:
     }
 
     // Operate on nodes
-    void insertClean(AstNode* nodep) {  // We'll insert ABOVE passed node
+    void insertClean(AstNodeExpr* nodep) {  // We'll insert ABOVE passed node
         UINFO(4, "  NeedClean " << nodep << endl);
         VNRelinker relinkHandle;
         nodep->unlinkFrBack(&relinkHandle);
@@ -134,14 +134,14 @@ private:
         cleanp->dtypeFrom(nodep);  // Otherwise the AND normally picks LHS
         relinkHandle.relink(cleanp);
     }
-    void ensureClean(AstNode* nodep) {
+    void ensureClean(AstNodeExpr* nodep) {
         computeCppWidth(nodep);
         if (!isClean(nodep)) insertClean(nodep);
     }
-    void ensureCleanAndNext(AstNode* nodep) {
+    void ensureCleanAndNext(AstNodeExpr* nodep) {
         // Editing list, careful looping!
-        for (AstNode* exprp = nodep; exprp;) {
-            AstNode* const nextp = exprp->nextp();
+        for (AstNodeExpr* exprp = nodep; exprp;) {
+            AstNodeExpr* const nextp = VN_AS(exprp->nextp(), NodeExpr);
             ensureClean(exprp);
             exprp = nextp;
         }
@@ -237,7 +237,9 @@ private:
         setClean(nodep, false);
         // We always clean, as we don't trust those pesky users.
         if (!VN_IS(nodep->backp(), And)) insertClean(nodep);
-        ensureCleanAndNext(nodep->exprsp());
+        for (AstNode* argp = nodep->exprsp(); argp; argp = argp->nextp()) {
+            if (AstNodeExpr* const exprp = VN_CAST(argp, NodeExpr)) ensureClean(exprp);
+        }
     }
     void visit(AstTraceDecl* nodep) override {
         // No cleaning, or would loose pointer to enum
@@ -277,7 +279,9 @@ private:
     }
     void visit(AstUCStmt* nodep) override {
         iterateChildren(nodep);
-        ensureCleanAndNext(nodep->exprsp());
+        for (AstNode* argp = nodep->exprsp(); argp; argp = argp->nextp()) {
+            if (AstNodeExpr* const exprp = VN_CAST(argp, NodeExpr)) ensureClean(exprp);
+        }
     }
     void visit(AstNodeCCall* nodep) override {
         iterateChildren(nodep);
diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp
index 501e42098..07e088140 100644
--- a/src/V3Clock.cpp
+++ b/src/V3Clock.cpp
@@ -46,11 +46,11 @@ VL_DEFINE_DEBUG_FUNCTIONS;
 class ConvertWriteRefsToRead final : public VNVisitor {
 private:
     // MEMBERS
-    AstNode* m_result = nullptr;
+    AstNodeExpr* m_result = nullptr;
 
     // CONSTRUCTORS
-    explicit ConvertWriteRefsToRead(AstNode* nodep) {
-        m_result = iterateSubtreeReturnEdits(nodep);
+    explicit ConvertWriteRefsToRead(AstNodeExpr* nodep) {
+        m_result = VN_AS(iterateSubtreeReturnEdits(nodep), NodeExpr);
     }
 
     // VISITORS
@@ -65,7 +65,7 @@ private:
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
-    static AstNode* main(AstNode* nodep) { return ConvertWriteRefsToRead(nodep).m_result; }
+    static AstNodeExpr* main(AstNodeExpr* nodep) { return ConvertWriteRefsToRead(nodep).m_result; }
 };
 
 //######################################################################
@@ -82,11 +82,11 @@ private:
 
     // METHODS
 
-    AstNode* createSenseEquation(AstSenItem* nodesp) {
-        AstNode* senEqnp = nullptr;
+    AstNodeExpr* createSenseEquation(AstSenItem* nodesp) {
+        AstNodeExpr* senEqnp = nullptr;
         for (AstSenItem* senp = nodesp; senp; senp = VN_AS(senp->nextp(), SenItem)) {
             UASSERT_OBJ(senp->edgeType() == VEdgeType::ET_TRUE, senp, "Should have been lowered");
-            AstNode* const senOnep = senp->sensp()->cloneTree(false);
+            AstNodeExpr* const senOnep = senp->sensp()->cloneTree(false);
             senEqnp = senEqnp ? new AstOr{senp->fileline(), senEqnp, senOnep} : senOnep;
         }
         return senEqnp;
@@ -111,7 +111,7 @@ private:
         return newvscp;
     }
     AstIf* makeActiveIf(AstSenTree* sensesp) {
-        AstNode* const senEqnp = createSenseEquation(sensesp->sensesp());
+        AstNodeExpr* const senEqnp = createSenseEquation(sensesp->sensesp());
         UASSERT_OBJ(senEqnp, sensesp, "No sense equation, shouldn't be in sequent activation.");
         AstIf* const newifp = new AstIf{sensesp->fileline(), senEqnp};
         return newifp;
@@ -126,9 +126,9 @@ private:
         // COVERTOGGLE(INC, ORIG, CHANGE) ->
         //   IF(ORIG ^ CHANGE) { INC; CHANGE = ORIG; }
         AstNode* const incp = nodep->incp()->unlinkFrBack();
-        AstNode* const origp = nodep->origp()->unlinkFrBack();
-        AstNode* const changeWrp = nodep->changep()->unlinkFrBack();
-        AstNode* const changeRdp = ConvertWriteRefsToRead::main(changeWrp->cloneTree(false));
+        AstNodeExpr* const origp = nodep->origp()->unlinkFrBack();
+        AstNodeExpr* const changeWrp = nodep->changep()->unlinkFrBack();
+        AstNodeExpr* const changeRdp = ConvertWriteRefsToRead::main(changeWrp->cloneTree(false));
         AstIf* const newp
             = new AstIf{nodep->fileline(), new AstXor{nodep->fileline(), origp, changeRdp}, incp};
         // We could add another IF to detect posedges, and only increment if so.
diff --git a/src/V3Common.cpp b/src/V3Common.cpp
index 9df1abc8a..a421c49f5 100644
--- a/src/V3Common.cpp
+++ b/src/V3Common.cpp
@@ -42,7 +42,8 @@ static void makeVlToString(AstClass* nodep) {
     funcp->isConst(false);
     funcp->isStatic(false);
     funcp->protect(false);
-    AstNode* const exprp = new AstCExpr{nodep->fileline(), "obj ? obj->to_string() : \"null\"", 0};
+    AstNodeExpr* const exprp
+        = new AstCExpr{nodep->fileline(), "obj ? obj->to_string() : \"null\"", 0};
     exprp->dtypeSetString();
     funcp->addStmtsp(new AstCReturn{nodep->fileline(), exprp});
     nodep->addStmtsp(funcp);
@@ -55,7 +56,7 @@ static void makeVlToString(AstIface* nodep) {
     funcp->isConst(false);
     funcp->isStatic(false);
     funcp->protect(false);
-    AstNode* const exprp = new AstCExpr{nodep->fileline(), "obj ? obj->name() : \"null\"", 0};
+    AstNodeExpr* const exprp = new AstCExpr{nodep->fileline(), "obj ? obj->name() : \"null\"", 0};
     exprp->dtypeSetString();
     funcp->addStmtsp(new AstCReturn{nodep->fileline(), exprp});
     nodep->addStmtsp(funcp);
@@ -65,7 +66,7 @@ static void makeToString(AstClass* nodep) {
     funcp->isConst(true);
     funcp->isStatic(false);
     funcp->protect(false);
-    AstNode* const exprp
+    AstCExpr* const exprp
         = new AstCExpr{nodep->fileline(), R"(std::string{"'{"} + to_string_middle() + "}")", 0};
     exprp->dtypeSetString();
     funcp->addStmtsp(new AstCReturn{nodep->fileline(), exprp});
diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 08ad3272d..173666099 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -80,7 +80,7 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
 
     // Holds a node to be added as a term in the reduction tree, it's equivalent op count, and a
     // bool indicating if the term is clean (0/1 value, or if the top bits might be dirty)
-    using ResultTerm = std::tuple<AstNode*, unsigned, bool>;
+    using ResultTerm = std::tuple<AstNodeExpr*, unsigned, bool>;
 
     class LeafInfo final {  // Leaf node (either AstConst or AstVarRef)
         // MEMBERS
@@ -243,7 +243,7 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
             FileLine* const fl = m_refp->fileline();
 
             // Get the term we are referencing (the WordSel, if wide, otherwise just the VarRef)
-            AstNode* srcp = VN_CAST(m_refp->backp(), WordSel);
+            AstNodeExpr* srcp = VN_CAST(m_refp->backp(), WordSel);
             if (!srcp) srcp = m_refp;
             srcp = srcp->cloneTree(false);
 
@@ -260,7 +260,7 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
             UASSERT(maskVal != 0, "Should have been recognized as having const 0 result");
 
             // Parts of the return value
-            AstNode* resultp = srcp;  // The tree for this term
+            AstNodeExpr* resultp = srcp;  // The tree for this term
             unsigned ops = 0;  // Number of ops in this term
             bool clean = false;  // Whether the term is clean (has value 0 or 1)
 
@@ -344,9 +344,9 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
     unsigned m_ops;  // Number of operations such as And, Or, Xor, Sel...
     int m_lsb = 0;  // Current LSB
     LeafInfo* m_leafp = nullptr;  // AstConst or AstVarRef that currently looking for
-    const AstNode* const m_rootp;  // Root of this AST subtree
+    const AstNodeExpr* const m_rootp;  // Root of this AST subtree
 
-    std::vector<std::pair<AstNode*, FrozenNodeInfo>>
+    std::vector<std::pair<AstNodeExpr*, FrozenNodeInfo>>
         m_frozenNodes;  // Nodes that cannot be optimized
     std::vector<BitPolarityEntry> m_bitPolarities;  // Polarity of bits found during iterate()
     std::vector<std::unique_ptr<VarInfo>> m_varInfos;  // VarInfo for each variable, [0] is nullptr
@@ -529,7 +529,7 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
                 Restorer restorer{*this};
                 LeafInfo leafInfo{m_lsb};
                 m_leafp = &leafInfo;
-                AstNode* opp = right ? nodep->rhsp() : nodep->lhsp();
+                AstNodeExpr* opp = right ? nodep->rhsp() : nodep->lhsp();
                 const bool origFailed = m_failed;
                 iterate(opp);
                 if (leafInfo.constp() || m_failed) {
@@ -625,7 +625,7 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
     }
 
     // CONSTRUCTORS
-    ConstBitOpTreeVisitor(AstNode* nodep, unsigned externalOps)
+    ConstBitOpTreeVisitor(AstNodeExpr* nodep, unsigned externalOps)
         : m_ops{externalOps}
         , m_rootp{nodep} {
         // Fill nullptr at [0] because AstVarScope::user4 is 0 by default
@@ -656,8 +656,8 @@ public:
     // (3'b000 != (3'b011 & v)) | v[2]  => 3'b000 != (3'b111 & v)
     // Reduction ops are transformed in the same way.
     // &{v[0], v[1]} => 2'b11 == (2'b11 & v)
-    static AstNode* simplify(AstNode* nodep, int resultWidth, unsigned externalOps,
-                             VDouble0& reduction) {
+    static AstNodeExpr* simplify(AstNodeExpr* nodep, int resultWidth, unsigned externalOps,
+                                 VDouble0& reduction) {
         UASSERT_OBJ(1 <= resultWidth && resultWidth <= 64, nodep, "resultWidth out of range");
 
         // Walk tree, gathering all terms referenced in expression
@@ -673,7 +673,7 @@ public:
         // whether we have clean/dirty terms. visitor.m_varInfos appears in deterministic order,
         // so the optimized tree is deterministic as well.
 
-        std::vector<AstNode*> termps;
+        std::vector<AstNodeExpr*> termps;
         termps.reserve(visitor.m_varInfos.size() - 1);
         unsigned resultOps = 0;
         bool hasCleanTerm = false;
@@ -683,7 +683,7 @@ public:
             if (!v) continue;  // Skip nullptr at m_varInfos[0]
             if (v->hasConstResult()) {
                 // If a constant term is known, we can either drop it or the whole tree is constant
-                AstNode* resultp = nullptr;
+                AstNodeExpr* resultp = nullptr;
                 if (v->getConstResult()) {
                     UASSERT_OBJ(visitor.isOrTree(), nodep,
                                 "Only OR tree can yield known 1 result");
@@ -715,10 +715,11 @@ public:
             }
         }
 
-        std::map<FrozenNodeInfo, std::vector<AstNode*>> frozenNodes;  // Group by FrozenNodeInfo
+        // Group by FrozenNodeInfo
+        std::map<FrozenNodeInfo, std::vector<AstNodeExpr*>> frozenNodes;
         // Check if frozen terms are clean or not
         for (const auto& frozenInfo : visitor.m_frozenNodes) {
-            AstNode* const termp = frozenInfo.first;
+            AstNodeExpr* const termp = frozenInfo.first;
             // Comparison operators are clean
             if ((VN_IS(termp, Eq) || VN_IS(termp, Neq) || VN_IS(termp, Lt) || VN_IS(termp, Lte)
                  || VN_IS(termp, Gt) || VN_IS(termp, Gte))
@@ -752,8 +753,8 @@ public:
 
         if (debug() >= 9) {  // LCOV_EXCL_START
             cout << "Bitop tree considered: " << endl;
-            for (AstNode* const termp : termps) termp->dumpTree("Reduced term: ");
-            for (const std::pair<AstNode*, FrozenNodeInfo>& termp : visitor.m_frozenNodes) {
+            for (AstNodeExpr* const termp : termps) termp->dumpTree("Reduced term: ");
+            for (const std::pair<AstNodeExpr*, FrozenNodeInfo>& termp : visitor.m_frozenNodes) {
                 termp.first->dumpTree("Frozen term with lsb " + std::to_string(termp.second.m_lsb)
                                       + " polarity " + std::to_string(termp.second.m_polarity)
                                       + ": ");
@@ -767,8 +768,8 @@ public:
         // (all of which were zeroes)
         if (termps.empty() && visitor.m_frozenNodes.empty()) {
             reduction += visitor.m_ops;
-            AstNode* const resultp = needsFlip ? new AstConst{fl, AstConst::BitTrue{}}
-                                               : new AstConst{fl, AstConst::BitFalse{}};
+            AstNodeExpr* const resultp = needsFlip ? new AstConst{fl, AstConst::BitTrue{}}
+                                                   : new AstConst{fl, AstConst::BitFalse{}};
             resultp->dtypeChgWidth(resultWidth, 1);
             return resultp;
         }
@@ -783,7 +784,7 @@ public:
         reduction += visitor.m_ops - resultOps;
 
         // Reduction op to combine terms
-        const auto reduce = [&visitor, fl](AstNode* lhsp, AstNode* rhsp) -> AstNode* {
+        const auto reduce = [&visitor, fl](AstNodeExpr* lhsp, AstNodeExpr* rhsp) -> AstNodeExpr* {
             if (!lhsp) return rhsp;
             if (visitor.isAndTree()) {
                 return new AstAnd{fl, lhsp, rhsp};
@@ -795,15 +796,15 @@ public:
         };
 
         // Compute result by reducing all terms
-        AstNode* resultp = nullptr;
-        for (AstNode* const termp : termps) {  //
+        AstNodeExpr* resultp = nullptr;
+        for (AstNodeExpr* const termp : termps) {  //
             resultp = reduce(resultp, termp);
         }
         // Add any frozen terms to the reduction
         for (auto&& nodes : frozenNodes) {
             // nodes.second has same lsb and polarity
-            AstNode* termp = nullptr;
-            for (AstNode* const itemp : nodes.second) {
+            AstNodeExpr* termp = nullptr;
+            for (AstNodeExpr* const itemp : nodes.second) {
                 termp = reduce(termp, itemp->unlinkFrBack());
             }
             if (nodes.first.m_lsb > 0) {  // LSB is not 0, so shiftR
@@ -961,7 +962,7 @@ private:
         // When bool is casted to int, the value is either 0 or 1
         AstConst* const constp = VN_AS(andp->lhsp(), Const);
         UASSERT_OBJ(constp && constp->isOne(), andp->lhsp(), "TRREEOPC must meet this condition");
-        AstNode* const rhsp = andp->rhsp();
+        AstNodeExpr* const rhsp = andp->rhsp();
         AstCCast* ccastp = nullptr;
         const auto isEqOrNeq
             = [](AstNode* nodep) -> bool { return VN_IS(nodep, Eq) || VN_IS(nodep, Neq); };
@@ -999,7 +1000,7 @@ private:
         // Someday we'll sort the biops completely and this can be simplified
         // This often results from our simplified clock generation:
         // if (rst) ... else if (enable)... -> OR(rst,AND(!rst,enable))
-        AstNode* ap;
+        AstNodeExpr* ap;
         AstNodeBiop* andp;
         if (VN_IS(nodep->lhsp(), And)) {
             andp = VN_AS(nodep->lhsp(), And);
@@ -1011,7 +1012,7 @@ private:
             return false;
         }
         const AstNodeUniop* notp;
-        AstNode* cp;
+        AstNodeExpr* cp;
         if (VN_IS(andp->lhsp(), Not)) {
             notp = VN_AS(andp->lhsp(), Not);
             cp = andp->rhsp();
@@ -1021,7 +1022,7 @@ private:
         } else {
             return false;
         }
-        AstNode* const bp = notp->lhsp();
+        AstNodeExpr* const bp = notp->lhsp();
         if (!operandsSame(ap, bp)) return false;
         // Do it
         cp->unlinkFrBack();
@@ -1140,7 +1141,7 @@ private:
         return false;
     }
 
-    bool matchBitOpTree(AstNode* nodep) {
+    bool matchBitOpTree(AstNodeExpr* nodep) {
         if (nodep->widthMin() != 1) return false;
         if (!v3Global.opt.fConstBitOpTree()) return false;
 
@@ -1277,8 +1278,8 @@ private:
               && nodep->lsbConst() == 0))
             return false;
         if (debug() >= 9) nodep->dumpTree(cout, "SEL(BI)-in:");
-        AstNode* const bilhsp = bip->lhsp()->unlinkFrBack();
-        AstNode* const birhsp = bip->rhsp()->unlinkFrBack();
+        AstNodeExpr* const bilhsp = bip->lhsp()->unlinkFrBack();
+        AstNodeExpr* const birhsp = bip->rhsp()->unlinkFrBack();
         bip->lhsp(new AstSel(nodep->fileline(), bilhsp, 0, nodep->widthConst()));
         bip->rhsp(new AstSel(nodep->fileline(), birhsp, 0, nodep->widthConst()));
         if (debug() >= 9) bip->dumpTree(cout, "SEL(BI)-ou:");
@@ -1294,7 +1295,7 @@ private:
               && VN_IS(nodep->widthp(), Const))) {
             return false;
         }
-        AstNode* const ap = shiftp->lhsp();
+        AstNodeExpr* const ap = shiftp->lhsp();
         AstConst* const bp = VN_AS(shiftp->rhsp(), Const);
         AstConst* const lp = VN_AS(nodep->lsbp(), Const);
         if (bp->isWide() || bp->num().isFourState() || bp->num().isNegative() || lp->isWide()
@@ -1321,7 +1322,7 @@ private:
         // would be incorrect. See also operandBiExtendConst
         AstExtend* const extendp = VN_CAST(nodep->rhsp(), Extend);
         if (!extendp) return false;
-        AstNode* const smallerp = extendp->lhsp();
+        AstNodeExpr* const smallerp = extendp->lhsp();
         const int subsize = smallerp->width();
         AstConst* const constp = VN_CAST(nodep->lhsp(), Const);
         if (!constp) return false;
@@ -1477,7 +1478,7 @@ private:
         const int rend = (rstart->toSInt() + rwidth->toSInt());
         return (rend == lstart->toSInt());
     }
-    bool ifMergeAdjacent(AstNode* lhsp, AstNode* rhsp) {
+    bool ifMergeAdjacent(AstNodeExpr* lhsp, AstNodeExpr* rhsp) {
         // called by concatmergeable to determine if {lhsp, rhsp} make sense
         if (!v3Global.opt.fAssemble()) return false;  // opt disabled
         // two same varref
@@ -1514,7 +1515,7 @@ private:
         if (rend == rfromp->width() && lstart->toSInt() == 0) return true;
         return false;
     }
-    bool concatMergeable(const AstNode* lhsp, const AstNode* rhsp, unsigned depth) {
+    bool concatMergeable(const AstNodeExpr* lhsp, const AstNodeExpr* rhsp, unsigned depth) {
         // determine if {a OP b, c OP d} => {a, c} OP {b, d} is advantageous
         if (!v3Global.opt.fAssemble()) return false;  // opt disabled
         if (lhsp->type() != rhsp->type()) return false;
@@ -1575,7 +1576,7 @@ private:
         VL_DO_DANGLING(replaceNum(nodep, val), nodep);
     }
     void replaceZero(AstNode* nodep) { VL_DO_DANGLING(replaceNum(nodep, 0), nodep); }
-    void replaceZeroChkPure(AstNode* nodep, AstNode* checkp) {
+    void replaceZeroChkPure(AstNode* nodep, AstNodeExpr* checkp) {
         // For example, "0 * n" -> 0 if n has no side effects
         // Else strength reduce it to 0 & n.
         // If ever change the operation note AstAnd rule specially ignores this created pattern
@@ -1637,7 +1638,7 @@ private:
     // Replacement functions.
     // These all take a node and replace it with something else
 
-    void replaceWChild(AstNode* nodep, AstNode* childp) {
+    void replaceWChild(AstNode* nodep, AstNodeExpr* childp) {
         // NODE(..., CHILD(...)) -> CHILD(...)
         childp->unlinkFrBackWithNext();
         // If replacing a SEL for example, the data type comes from the parent (is less wide).
@@ -1646,7 +1647,7 @@ private:
         nodep->replaceWith(childp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
-    void replaceWChildBool(AstNode* nodep, AstNode* childp) {
+    void replaceWChildBool(AstNode* nodep, AstNodeExpr* childp) {
         // NODE(..., CHILD(...)) -> REDOR(CHILD(...))
         childp->unlinkFrBack();
         if (childp->width1()) {
@@ -1688,10 +1689,10 @@ private:
         // BIASV(CONSTa, BIASV(CONSTb, c)) -> BIASV( BIASV_CONSTED(a,b), c)
         // BIASV(SAMEa,  BIASV(SAMEb, c))  -> BIASV( BIASV(SAMEa,SAMEb), c)
         // nodep->dumpTree(cout, "  repAsvConst_old: ");
-        AstNode* const ap = nodep->lhsp();
+        AstNodeExpr* const ap = nodep->lhsp();
         AstNodeBiop* const rp = VN_AS(nodep->rhsp(), NodeBiop);
-        AstNode* const bp = rp->lhsp();
-        AstNode* const cp = rp->rhsp();
+        AstNodeExpr* const bp = rp->lhsp();
+        AstNodeExpr* const cp = rp->rhsp();
         ap->unlinkFrBack();
         bp->unlinkFrBack();
         cp->unlinkFrBack();
@@ -1706,9 +1707,9 @@ private:
     void replaceAsvLUp(AstNodeBiop* nodep) {
         // BIASV(BIASV(CONSTll,lr),r) -> BIASV(CONSTll,BIASV(lr,r))
         AstNodeBiop* const lp = VN_AS(nodep->lhsp()->unlinkFrBack(), NodeBiop);
-        AstNode* const llp = lp->lhsp()->unlinkFrBack();
-        AstNode* const lrp = lp->rhsp()->unlinkFrBack();
-        AstNode* const rp = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* const llp = lp->lhsp()->unlinkFrBack();
+        AstNodeExpr* const lrp = lp->rhsp()->unlinkFrBack();
+        AstNodeExpr* const rp = nodep->rhsp()->unlinkFrBack();
         nodep->lhsp(llp);
         nodep->rhsp(lp);
         lp->lhsp(lrp);
@@ -1717,10 +1718,10 @@ private:
     }
     void replaceAsvRUp(AstNodeBiop* nodep) {
         // BIASV(l,BIASV(CONSTrl,rr)) -> BIASV(CONSTrl,BIASV(l,rr))
-        AstNode* const lp = nodep->lhsp()->unlinkFrBack();
+        AstNodeExpr* const lp = nodep->lhsp()->unlinkFrBack();
         AstNodeBiop* const rp = VN_AS(nodep->rhsp()->unlinkFrBack(), NodeBiop);
-        AstNode* const rlp = rp->lhsp()->unlinkFrBack();
-        AstNode* const rrp = rp->rhsp()->unlinkFrBack();
+        AstNodeExpr* const rlp = rp->lhsp()->unlinkFrBack();
+        AstNodeExpr* const rrp = rp->rhsp()->unlinkFrBack();
         nodep->lhsp(rlp);
         nodep->rhsp(rp);
         rp->lhsp(lp);
@@ -1733,11 +1734,11 @@ private:
         // nodep ^lp  ^llp   ^lrp  ^rp  ^rlp       ^rrp
         // (Or/And may also be reversed)
         AstNodeBiop* const lp = VN_AS(nodep->lhsp()->unlinkFrBack(), NodeBiop);
-        AstNode* const llp = lp->lhsp()->unlinkFrBack();
-        AstNode* const lrp = lp->rhsp()->unlinkFrBack();
+        AstNodeExpr* const llp = lp->lhsp()->unlinkFrBack();
+        AstNodeExpr* const lrp = lp->rhsp()->unlinkFrBack();
         AstNodeBiop* const rp = VN_AS(nodep->rhsp()->unlinkFrBack(), NodeBiop);
-        AstNode* const rlp = rp->lhsp()->unlinkFrBack();
-        AstNode* const rrp = rp->rhsp()->unlinkFrBack();
+        AstNodeExpr* const rlp = rp->lhsp()->unlinkFrBack();
+        AstNodeExpr* const rrp = rp->rhsp()->unlinkFrBack();
         nodep->replaceWith(lp);
         if (operandsSame(llp, rlp)) {
             lp->lhsp(llp);
@@ -1764,11 +1765,11 @@ private:
         // Or(Shift(ll,CONSTlr),Shift(rl,CONSTrr==lr)) -> Shift(Or(ll,rl),CONSTlr)
         // (Or/And may also be reversed)
         AstNodeBiop* const lp = VN_AS(nodep->lhsp()->unlinkFrBack(), NodeBiop);
-        AstNode* const llp = lp->lhsp()->unlinkFrBack();
-        AstNode* const lrp = lp->rhsp()->unlinkFrBack();
+        AstNodeExpr* const llp = lp->lhsp()->unlinkFrBack();
+        AstNodeExpr* const lrp = lp->rhsp()->unlinkFrBack();
         AstNodeBiop* const rp = VN_AS(nodep->rhsp()->unlinkFrBack(), NodeBiop);
-        AstNode* const rlp = rp->lhsp()->unlinkFrBack();
-        AstNode* const rrp = rp->rhsp()->unlinkFrBack();
+        AstNodeExpr* const rlp = rp->lhsp()->unlinkFrBack();
+        AstNodeExpr* const rrp = rp->rhsp()->unlinkFrBack();
         nodep->replaceWith(lp);
         lp->lhsp(nodep);
         lp->rhsp(lrp);
@@ -1803,10 +1804,10 @@ private:
     void replaceConcatMerge(AstConcat* nodep) {
         AstNodeBiop* const lp = VN_AS(nodep->lhsp(), NodeBiop);
         AstNodeBiop* const rp = VN_AS(nodep->rhsp(), NodeBiop);
-        AstNode* const llp = lp->lhsp()->cloneTree(false);
-        AstNode* const lrp = lp->rhsp()->cloneTree(false);
-        AstNode* const rlp = rp->lhsp()->cloneTree(false);
-        AstNode* const rrp = rp->rhsp()->cloneTree(false);
+        AstNodeExpr* const llp = lp->lhsp()->cloneTree(false);
+        AstNodeExpr* const lrp = lp->rhsp()->cloneTree(false);
+        AstNodeExpr* const rlp = rp->lhsp()->cloneTree(false);
+        AstNodeExpr* const rrp = rp->rhsp()->cloneTree(false);
         if (concatMergeable(lp, rp, 0)) {
             AstConcat* const newlp = new AstConcat(rlp->fileline(), llp, rlp);
             AstConcat* const newrp = new AstConcat(rrp->fileline(), lrp, rrp);
@@ -1824,21 +1825,21 @@ private:
             nodep->v3fatalSrc("tried to merge two Concat which are not adjacent");
         }
     }
-    void replaceExtend(AstNode* nodep, AstNode* arg0p) {
+    void replaceExtend(AstNode* nodep, AstNodeExpr* arg0p) {
         // -> EXTEND(nodep)
         // like a AstExtend{$rhsp}, but we need to set the width correctly from base node
         arg0p->unlinkFrBack();
-        AstNode* const newp
+        AstNodeExpr* const newp
             = (VN_IS(nodep, ExtendS)
-                   ? static_cast<AstNode*>(new AstExtendS{nodep->fileline(), arg0p})
-                   : static_cast<AstNode*>(new AstExtend{nodep->fileline(), arg0p}));
+                   ? static_cast<AstNodeExpr*>(new AstExtendS{nodep->fileline(), arg0p})
+                   : static_cast<AstNodeExpr*>(new AstExtend{nodep->fileline(), arg0p}));
         newp->dtypeFrom(nodep);
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
     void replacePowShift(AstNodeBiop* nodep) {  // Pow or PowS
         UINFO(5, "POW(2,b)->SHIFTL(1,b) " << nodep << endl);
-        AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
         AstShiftL* const newp
             = new AstShiftL(nodep->fileline(), new AstConst(nodep->fileline(), 1), rhsp);
         newp->dtypeFrom(nodep);
@@ -1849,7 +1850,7 @@ private:
     void replaceMulShift(AstMul* nodep) {  // Mul, but not MulS as not simple shift
         UINFO(5, "MUL(2^n,b)->SHIFTL(b,n) " << nodep << endl);
         const int amount = VN_AS(nodep->lhsp(), Const)->num().mostSetBitP1() - 1;  // 2^n->n+1
-        AstNode* const opp = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* const opp = nodep->rhsp()->unlinkFrBack();
         AstShiftL* const newp
             = new AstShiftL(nodep->fileline(), opp, new AstConst(nodep->fileline(), amount));
         newp->dtypeFrom(nodep);
@@ -1859,7 +1860,7 @@ private:
     void replaceDivShift(AstDiv* nodep) {  // Mul, but not MulS as not simple shift
         UINFO(5, "DIV(b,2^n)->SHIFTR(b,n) " << nodep << endl);
         const int amount = VN_AS(nodep->rhsp(), Const)->num().mostSetBitP1() - 1;  // 2^n->n+1
-        AstNode* const opp = nodep->lhsp()->unlinkFrBack();
+        AstNodeExpr* const opp = nodep->lhsp()->unlinkFrBack();
         AstShiftR* const newp
             = new AstShiftR(nodep->fileline(), opp, new AstConst(nodep->fileline(), amount));
         newp->dtypeFrom(nodep);
@@ -1871,7 +1872,7 @@ private:
         const int amount = VN_AS(nodep->rhsp(), Const)->num().mostSetBitP1() - 1;  // 2^n->n+1
         V3Number mask(nodep, nodep->width());
         mask.setMask(amount);
-        AstNode* const opp = nodep->lhsp()->unlinkFrBack();
+        AstNodeExpr* const opp = nodep->lhsp()->unlinkFrBack();
         AstAnd* const newp
             = new AstAnd(nodep->fileline(), opp, new AstConst(nodep->fileline(), mask));
         newp->dtypeFrom(nodep);
@@ -1884,9 +1885,9 @@ private:
         nodep->unlinkFrBack(&handle);
         AstNodeBiop* const lhsp = VN_AS(nodep->lhsp(), NodeBiop);
         lhsp->unlinkFrBack();
-        AstNode* const shiftp = nodep->rhsp()->unlinkFrBack();
-        AstNode* const ap = lhsp->lhsp()->unlinkFrBack();
-        AstNode* const bp = lhsp->rhsp()->unlinkFrBack();
+        AstNodeExpr* const shiftp = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* const ap = lhsp->lhsp()->unlinkFrBack();
+        AstNodeExpr* const bp = lhsp->rhsp()->unlinkFrBack();
         AstNodeBiop* const shift1p = nodep;
         AstNodeBiop* const shift2p = nodep->cloneTree(true);
         shift1p->lhsp(ap);
@@ -1904,9 +1905,9 @@ private:
         if (debug() >= 9) nodep->dumpTree(cout, "  repShiftShift_old: ");
         AstNodeBiop* const lhsp = VN_AS(nodep->lhsp(), NodeBiop);
         lhsp->unlinkFrBack();
-        AstNode* const ap = lhsp->lhsp()->unlinkFrBack();
-        AstNode* const shift1p = lhsp->rhsp()->unlinkFrBack();
-        AstNode* const shift2p = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* const ap = lhsp->lhsp()->unlinkFrBack();
+        AstNodeExpr* const shift1p = lhsp->rhsp()->unlinkFrBack();
+        AstNodeExpr* const shift2p = nodep->rhsp()->unlinkFrBack();
         // Shift1p and shift2p may have different sizes, both are
         // self-determined so sum with infinite width
         if (nodep->type() == lhsp->type()) {
@@ -1927,7 +1928,7 @@ private:
             const int newshift = shift1 + shift2;
             VL_DO_DANGLING(shift1p->deleteTree(), shift1p);
             VL_DO_DANGLING(shift2p->deleteTree(), shift2p);
-            AstNode* newp;
+            AstNodeExpr* newp;
             V3Number mask1(nodep, nodep->width());
             V3Number ones(nodep, nodep->width());
             ones.setMask(nodep->width());
@@ -1999,9 +2000,9 @@ private:
         UINFO(4, "                   && " << nextp << endl);
         // nodep->dumpTree(cout, "comb1: ");
         // nextp->dumpTree(cout, "comb2: ");
-        AstNode* const rhs1p = nodep->rhsp()->unlinkFrBack();
-        AstNode* const rhs2p = nextp->rhsp()->unlinkFrBack();
-        AstNode* newp;
+        AstNodeExpr* const rhs1p = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* const rhs2p = nextp->rhsp()->unlinkFrBack();
+        AstNodeAssign* newp;
         if (lsbFirstAssign) {
             newp = nodep->cloneType(new AstSel(sel1p->fileline(), varref1p->unlinkFrBack(),
                                                sel1p->lsbConst(), sel1p->width() + sel2p->width()),
@@ -2072,11 +2073,11 @@ private:
             }
             if (debug() >= 9) nodep->dumpTree(cout, "  Ass_old: ");
             // Unlink the stuff
-            AstNode* const lc1p = VN_AS(nodep->lhsp(), Concat)->lhsp()->unlinkFrBack();
-            AstNode* const lc2p = VN_AS(nodep->lhsp(), Concat)->rhsp()->unlinkFrBack();
-            AstNode* const conp = VN_AS(nodep->lhsp(), Concat)->unlinkFrBack();
-            AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
-            AstNode* const rhs2p = rhsp->cloneTree(false);
+            AstNodeExpr* const lc1p = VN_AS(nodep->lhsp(), Concat)->lhsp()->unlinkFrBack();
+            AstNodeExpr* const lc2p = VN_AS(nodep->lhsp(), Concat)->rhsp()->unlinkFrBack();
+            AstNodeExpr* const conp = VN_AS(nodep->lhsp(), Concat)->unlinkFrBack();
+            AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
+            AstNodeExpr* const rhs2p = rhsp->cloneTree(false);
             // Calc widths
             const int lsb2 = 0;
             const int msb2 = lsb2 + lc2p->width() - 1;
@@ -2090,8 +2091,8 @@ private:
             //*** Not cloneTree; just one node.
             AstNodeAssign* newp = nullptr;
             if (!need_temp) {
-                AstNodeAssign* const asn1ap = VN_AS(nodep->cloneType(lc1p, sel1p), NodeAssign);
-                AstNodeAssign* const asn2ap = VN_AS(nodep->cloneType(lc2p, sel2p), NodeAssign);
+                AstNodeAssign* const asn1ap = nodep->cloneType(lc1p, sel1p);
+                AstNodeAssign* const asn2ap = nodep->cloneType(lc2p, sel2p);
                 asn1ap->dtypeFrom(sel1p);
                 asn2ap->dtypeFrom(sel2p);
                 newp = AstNode::addNext(newp, asn1ap);
@@ -2103,29 +2104,21 @@ private:
                 // We could create just one temp variable, but we'll get better optimization
                 // if we make one per term.
                 AstVar* const temp1p
-                    = new AstVar(sel1p->fileline(), VVarType::BLOCKTEMP,
-                                 m_concswapNames.get(sel1p), VFlagLogicPacked(), msb1 - lsb1 + 1);
+                    = new AstVar{sel1p->fileline(), VVarType::BLOCKTEMP,
+                                 m_concswapNames.get(sel1p), VFlagLogicPacked(), msb1 - lsb1 + 1};
                 AstVar* const temp2p
-                    = new AstVar(sel2p->fileline(), VVarType::BLOCKTEMP,
-                                 m_concswapNames.get(sel2p), VFlagLogicPacked(), msb2 - lsb2 + 1);
+                    = new AstVar{sel2p->fileline(), VVarType::BLOCKTEMP,
+                                 m_concswapNames.get(sel2p), VFlagLogicPacked(), msb2 - lsb2 + 1};
                 m_modp->addStmtsp(temp1p);
                 m_modp->addStmtsp(temp2p);
-                AstNodeAssign* const asn1ap
-                    = VN_AS(nodep->cloneType(
-                                new AstVarRef(sel1p->fileline(), temp1p, VAccess::WRITE), sel1p),
-                            NodeAssign);
-                AstNodeAssign* const asn2ap
-                    = VN_AS(nodep->cloneType(
-                                new AstVarRef(sel2p->fileline(), temp2p, VAccess::WRITE), sel2p),
-                            NodeAssign);
-                AstNodeAssign* const asn1bp
-                    = VN_AS(nodep->cloneType(
-                                lc1p, new AstVarRef(sel1p->fileline(), temp1p, VAccess::READ)),
-                            NodeAssign);
-                AstNodeAssign* const asn2bp
-                    = VN_AS(nodep->cloneType(
-                                lc2p, new AstVarRef(sel2p->fileline(), temp2p, VAccess::READ)),
-                            NodeAssign);
+                AstNodeAssign* const asn1ap = nodep->cloneType(
+                    new AstVarRef{sel1p->fileline(), temp1p, VAccess::WRITE}, sel1p);
+                AstNodeAssign* const asn2ap = nodep->cloneType(
+                    new AstVarRef{sel2p->fileline(), temp2p, VAccess::WRITE}, sel2p);
+                AstNodeAssign* const asn1bp = nodep->cloneType(
+                    lc1p, new AstVarRef{sel1p->fileline(), temp1p, VAccess::READ});
+                AstNodeAssign* const asn2bp = nodep->cloneType(
+                    lc2p, new AstVarRef{sel2p->fileline(), temp2p, VAccess::READ});
                 asn1ap->dtypeFrom(temp1p);
                 asn1bp->dtypeFrom(temp1p);
                 asn2ap->dtypeFrom(temp2p);
@@ -2147,9 +2140,9 @@ private:
             // The right-streaming operator on rhs of assignment does not
             // change the order of bits. Eliminate stream but keep its lhsp
             // Unlink the stuff
-            AstNode* const srcp = VN_AS(nodep->rhsp(), StreamR)->lhsp()->unlinkFrBack();
+            AstNodeExpr* const srcp = VN_AS(nodep->rhsp(), StreamR)->lhsp()->unlinkFrBack();
             AstNode* const sizep = VN_AS(nodep->rhsp(), StreamR)->rhsp()->unlinkFrBack();
-            AstNode* const streamp = VN_AS(nodep->rhsp(), StreamR)->unlinkFrBack();
+            AstNodeExpr* const streamp = VN_AS(nodep->rhsp(), StreamR)->unlinkFrBack();
             nodep->rhsp(srcp);
             // Cleanup
             VL_DO_DANGLING(sizep->deleteTree(), sizep);
@@ -2161,9 +2154,9 @@ private:
             const int dWidth = VN_AS(nodep->lhsp(), StreamL)->lhsp()->width();
             const int sWidth = nodep->rhsp()->width();
             // Unlink the stuff
-            AstNode* const dstp = VN_AS(nodep->lhsp(), StreamL)->lhsp()->unlinkFrBack();
-            AstNode* streamp = VN_AS(nodep->lhsp(), StreamL)->unlinkFrBack();
-            AstNode* const srcp = nodep->rhsp()->unlinkFrBack();
+            AstNodeExpr* const dstp = VN_AS(nodep->lhsp(), StreamL)->lhsp()->unlinkFrBack();
+            AstNodeExpr* streamp = VN_AS(nodep->lhsp(), StreamL)->unlinkFrBack();
+            AstNodeExpr* const srcp = nodep->rhsp()->unlinkFrBack();
             // Connect the rhs to the stream operator and update its width
             VN_AS(streamp, StreamL)->lhsp(srcp);
             streamp->dtypeSetLogicUnsized(srcp->width(), srcp->widthMin(), VSigning::UNSIGNED);
@@ -2182,10 +2175,10 @@ private:
             const int dWidth = VN_AS(nodep->lhsp(), StreamR)->lhsp()->width();
             const int sWidth = nodep->rhsp()->width();
             // Unlink the stuff
-            AstNode* const dstp = VN_AS(nodep->lhsp(), StreamR)->lhsp()->unlinkFrBack();
+            AstNodeExpr* const dstp = VN_AS(nodep->lhsp(), StreamR)->lhsp()->unlinkFrBack();
             AstNode* const sizep = VN_AS(nodep->lhsp(), StreamR)->rhsp()->unlinkFrBack();
-            AstNode* const streamp = VN_AS(nodep->lhsp(), StreamR)->unlinkFrBack();
-            AstNode* srcp = nodep->rhsp()->unlinkFrBack();
+            AstNodeExpr* const streamp = VN_AS(nodep->lhsp(), StreamR)->unlinkFrBack();
+            AstNodeExpr* srcp = nodep->rhsp()->unlinkFrBack();
             if (sWidth > dWidth) {
                 srcp = new AstSel(streamp->fileline(), srcp, sWidth - dWidth, dWidth);
             }
@@ -2218,7 +2211,8 @@ private:
     void replaceBoolShift(AstNode* nodep) {
         if (debug() >= 9) nodep->dumpTree(cout, "  bshft_old: ");
         AstConst* const andConstp = VN_AS(VN_AS(nodep, And)->lhsp(), Const);
-        AstNode* const fromp = VN_AS(VN_AS(nodep, And)->rhsp(), ShiftR)->lhsp()->unlinkFrBack();
+        AstNodeExpr* const fromp
+            = VN_AS(VN_AS(nodep, And)->rhsp(), ShiftR)->lhsp()->unlinkFrBack();
         AstConst* const shiftConstp
             = VN_AS(VN_AS(VN_AS(nodep, And)->rhsp(), ShiftR)->rhsp(), Const);
         V3Number val(andConstp, andConstp->width());
@@ -2296,8 +2290,8 @@ private:
     void swapSides(AstNodeBiCom* nodep) {
         // COMMUTATIVE({a},CONST) -> COMMUTATIVE(CONST,{a})
         // This simplifies later optimizations
-        AstNode* const lhsp = nodep->lhsp()->unlinkFrBackWithNext();
-        AstNode* const rhsp = nodep->rhsp()->unlinkFrBackWithNext();
+        AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBackWithNext();
+        AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBackWithNext();
         nodep->lhsp(rhsp);
         nodep->rhsp(lhsp);
         iterate(nodep);  // Again?
@@ -2333,8 +2327,8 @@ private:
         const AstConcat* const bcConcp = VN_CAST(nodep->rhsp(), Concat);
         if (!abConcp && !bcConcp) return 0;
         if (bcConcp) {
-            AstNode* const ap = nodep->lhsp();
-            AstNode* const bp = bcConcp->lhsp();
+            AstNodeExpr* const ap = nodep->lhsp();
+            AstNodeExpr* const bp = bcConcp->lhsp();
             // If a+b == 32,64,96 etc, then we want to have a+b together on LHS
             if (VL_BITBIT_I(ap->width() + bp->width()) == 0) return 2;  // Transform 2: to abConc
         } else {  // abConcp
@@ -2352,11 +2346,11 @@ private:
         // like that, so on 32 bit boundaries, we'll do the opposite form.
         UINFO(4, "Move concat: " << nodep << endl);
         if (operandConcatMove(nodep) > 1) {
-            AstNode* const ap = nodep->lhsp()->unlinkFrBack();
+            AstNodeExpr* const ap = nodep->lhsp()->unlinkFrBack();
             AstConcat* const bcConcp = VN_AS(nodep->rhsp(), Concat);
             bcConcp->unlinkFrBack();
-            AstNode* const bp = bcConcp->lhsp()->unlinkFrBack();
-            AstNode* const cp = bcConcp->rhsp()->unlinkFrBack();
+            AstNodeExpr* const bp = bcConcp->lhsp()->unlinkFrBack();
+            AstNodeExpr* const cp = bcConcp->rhsp()->unlinkFrBack();
             AstConcat* const abConcp = new AstConcat(bcConcp->fileline(), ap, bp);
             nodep->lhsp(abConcp);
             nodep->rhsp(cp);
@@ -2367,9 +2361,9 @@ private:
         } else {
             AstConcat* const abConcp = VN_AS(nodep->lhsp(), Concat);
             abConcp->unlinkFrBack();
-            AstNode* const ap = abConcp->lhsp()->unlinkFrBack();
-            AstNode* const bp = abConcp->rhsp()->unlinkFrBack();
-            AstNode* const cp = nodep->rhsp()->unlinkFrBack();
+            AstNodeExpr* const ap = abConcp->lhsp()->unlinkFrBack();
+            AstNodeExpr* const bp = abConcp->rhsp()->unlinkFrBack();
+            AstNodeExpr* const cp = nodep->rhsp()->unlinkFrBack();
             AstConcat* const bcConcp = new AstConcat(abConcp->fileline(), bp, cp);
             nodep->lhsp(ap);
             nodep->rhsp(bcConcp);
@@ -2393,8 +2387,8 @@ private:
 
     void replaceLogEq(AstLogEq* nodep) {
         // LOGEQ(a,b) => AstLogAnd{AstLogOr{AstLogNot{a},b},AstLogOr{AstLogNot{b},a}}
-        AstNode* const lhsp = nodep->lhsp()->unlinkFrBack();
-        AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
+        AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
         // Do exactly as IEEE says, might result in extra terms, so in future may do differently
         AstLogAnd* const newp = new AstLogAnd(
             nodep->fileline(),
@@ -2410,13 +2404,13 @@ private:
     void replaceSelSel(AstSel* nodep) {
         // SEL(SEL({x},a,b),c,d) => SEL({x},a+c,d)
         AstSel* const belowp = VN_AS(nodep->fromp(), Sel);
-        AstNode* const fromp = belowp->fromp()->unlinkFrBack();
-        AstNode* const widthp = nodep->widthp()->unlinkFrBack();
-        AstNode* const lsb1p = nodep->lsbp()->unlinkFrBack();
-        AstNode* const lsb2p = belowp->lsbp()->unlinkFrBack();
+        AstNodeExpr* const fromp = belowp->fromp()->unlinkFrBack();
+        AstNodeExpr* const widthp = nodep->widthp()->unlinkFrBack();
+        AstNodeExpr* const lsb1p = nodep->lsbp()->unlinkFrBack();
+        AstNodeExpr* const lsb2p = belowp->lsbp()->unlinkFrBack();
         // Eliminate lower range
         UINFO(4, "Elim Lower range: " << nodep << endl);
-        AstNode* newlsbp;
+        AstNodeExpr* newlsbp;
         if (VN_IS(lsb1p, Const) && VN_IS(lsb2p, Const)) {
             newlsbp = new AstConst(lsb1p->fileline(),
                                    VN_AS(lsb1p, Const)->toUInt() + VN_AS(lsb2p, Const)->toUInt());
@@ -2427,13 +2421,13 @@ private:
             // potentially smaller lsb1p's width, but don't insert a redundant AstExtend.
             // Note that due to some sloppiness in earlier passes, lsb1p might actually be wider,
             // so extend to the wider type.
-            AstNode* const widep = lsb1p->width() > lsb2p->width() ? lsb1p : lsb2p;
-            AstNode* const lhsp = widep->width() > lsb2p->width()
-                                      ? new AstExtend{lsb2p->fileline(), lsb2p}
-                                      : lsb2p;
-            AstNode* const rhsp = widep->width() > lsb1p->width()
-                                      ? new AstExtend{lsb1p->fileline(), lsb1p}
-                                      : lsb1p;
+            AstNodeExpr* const widep = lsb1p->width() > lsb2p->width() ? lsb1p : lsb2p;
+            AstNodeExpr* const lhsp = widep->width() > lsb2p->width()
+                                          ? new AstExtend{lsb2p->fileline(), lsb2p}
+                                          : lsb2p;
+            AstNodeExpr* const rhsp = widep->width() > lsb1p->width()
+                                          ? new AstExtend{lsb1p->fileline(), lsb1p}
+                                          : lsb1p;
             lhsp->dtypeFrom(widep);
             rhsp->dtypeFrom(widep);
             newlsbp = new AstAdd{lsb1p->fileline(), lhsp, rhsp};
@@ -2447,8 +2441,8 @@ private:
     void replaceSelConcat(AstSel* nodep) {
         // SEL(CONCAT(a,b),c,d) => SEL(a or b, . .)
         AstConcat* const conp = VN_AS(nodep->fromp(), Concat);
-        AstNode* const conLhsp = conp->lhsp();
-        AstNode* const conRhsp = conp->rhsp();
+        AstNodeExpr* const conLhsp = conp->lhsp();
+        AstNodeExpr* const conRhsp = conp->rhsp();
         if (static_cast<int>(nodep->lsbConst()) >= conRhsp->width()) {
             conLhsp->unlinkFrBack();
             AstSel* const newp
@@ -2478,10 +2472,10 @@ private:
         // SEL(REPLICATE(from,rep),lsb,width) => SEL(from,0,width) as long
         // as SEL's width <= b's width
         AstReplicate* const repp = VN_AS(nodep->fromp(), Replicate);
-        AstNode* const fromp = repp->lhsp();
+        AstNodeExpr* const fromp = repp->lhsp();
         AstConst* const lsbp = VN_CAST(nodep->lsbp(), Const);
         if (!lsbp) return false;
-        AstNode* const widthp = nodep->widthp();
+        AstNodeExpr* const widthp = nodep->widthp();
         if (!VN_IS(widthp, Const)) return false;
         UASSERT_OBJ(fromp->width(), nodep, "Not widthed");
         if ((lsbp->toUInt() / fromp->width())
@@ -2502,7 +2496,7 @@ private:
     bool operandRepRep(AstReplicate* nodep) {
         // REPLICATE(REPLICATE2(from2,cnt2),cnt1) => REPLICATE(from2,(cnt1+cnt2))
         AstReplicate* const rep2p = VN_AS(nodep->lhsp(), Replicate);
-        AstNode* const from2p = rep2p->lhsp();
+        AstNodeExpr* const from2p = rep2p->lhsp();
         AstConst* const cnt1p = VN_CAST(nodep->rhsp(), Const);
         if (!cnt1p) return false;
         AstConst* const cnt2p = VN_CAST(rep2p->rhsp(), Const);
@@ -2523,9 +2517,9 @@ private:
         // CONCAT(REP(fromp,cnt1),fromp) -> REPLICATE(fromp,cnt1+1)
         // CONCAT(fromp,REP(fromp,cnt1)) -> REPLICATE(fromp,1+cnt1)
         // CONCAT(REP(fromp,cnt1),REP(fromp,cnt2)) -> REPLICATE(fromp,cnt1+cnt2)
-        AstNode* from1p = nodep->lhsp();
+        AstNodeExpr* from1p = nodep->lhsp();
         uint32_t cnt1 = 1;
-        AstNode* from2p = nodep->rhsp();
+        AstNodeExpr* from2p = nodep->rhsp();
         uint32_t cnt2 = 1;
         if (VN_IS(from1p, Replicate)) {
             AstConst* const cnt1p = VN_CAST(VN_CAST(from1p, Replicate)->rhsp(), Const);
@@ -2552,11 +2546,11 @@ private:
         // SEL(BUFIF1(a,b),1,bit) => BUFIF1(SEL(a,1,bit),SEL(b,1,bit))
         AstNodeBiop* const fromp = VN_AS(nodep->fromp()->unlinkFrBack(), NodeBiop);
         UASSERT_OBJ(fromp, nodep, "Called on non biop");
-        AstNode* const lsbp = nodep->lsbp()->unlinkFrBack();
-        AstNode* const widthp = nodep->widthp()->unlinkFrBack();
+        AstNodeExpr* const lsbp = nodep->lsbp()->unlinkFrBack();
+        AstNodeExpr* const widthp = nodep->widthp()->unlinkFrBack();
         //
-        AstNode* const bilhsp = fromp->lhsp()->unlinkFrBack();
-        AstNode* const birhsp = fromp->rhsp()->unlinkFrBack();
+        AstNodeExpr* const bilhsp = fromp->lhsp()->unlinkFrBack();
+        AstNodeExpr* const birhsp = fromp->rhsp()->unlinkFrBack();
         //
         fromp->lhsp(
             new AstSel(nodep->fileline(), bilhsp, lsbp->cloneTree(true), widthp->cloneTree(true)));
@@ -2569,10 +2563,10 @@ private:
         // SEL(NOT(a),1,bit) => NOT(SEL(a,bit))
         AstNodeUniop* const fromp = VN_AS(nodep->fromp()->unlinkFrBack(), NodeUniop);
         UASSERT_OBJ(fromp, nodep, "Called on non biop");
-        AstNode* const lsbp = nodep->lsbp()->unlinkFrBack();
-        AstNode* const widthp = nodep->widthp()->unlinkFrBack();
+        AstNodeExpr* const lsbp = nodep->lsbp()->unlinkFrBack();
+        AstNodeExpr* const widthp = nodep->widthp()->unlinkFrBack();
         //
-        AstNode* const bilhsp = fromp->lhsp()->unlinkFrBack();
+        AstNodeExpr* const bilhsp = fromp->lhsp()->unlinkFrBack();
         //
         fromp->lhsp(new AstSel(nodep->fileline(), bilhsp, lsbp, widthp));
         fromp->dtypeFrom(nodep);
@@ -2901,7 +2895,7 @@ private:
             // ASSIGNW (VARREF, const) -> INITIAL ( ASSIGN (VARREF, const) )
             UINFO(4, "constAssignW " << nodep << endl);
             // Make a initial assignment
-            AstNode* const exprp = nodep->rhsp()->unlinkFrBack();
+            AstNodeExpr* const exprp = nodep->rhsp()->unlinkFrBack();
             varrefp->unlinkFrBack();
             AstInitial* const newinitp = new AstInitial(
                 nodep->fileline(), new AstAssign(nodep->fileline(), varrefp, exprp));
@@ -2957,7 +2951,7 @@ private:
                 }
             } else if (!afterComment(nodep->thensp())) {
                 UINFO(4, "IF({x}) nullptr {...} => IF(NOT{x}}: " << nodep << endl);
-                AstNode* const condp = nodep->condp();
+                AstNodeExpr* const condp = nodep->condp();
                 AstNode* const elsesp = nodep->elsesp();
                 condp->unlinkFrBackWithNext();
                 elsesp->unlinkFrBackWithNext();
@@ -2971,7 +2965,7 @@ private:
                         || VN_IS(nodep->condp(), LogNot))
                        && nodep->thensp() && nodep->elsesp()) {
                 UINFO(4, "IF(NOT {x})  => IF(x) swapped if/else" << nodep << endl);
-                AstNode* const condp
+                AstNodeExpr* const condp
                     = VN_AS(nodep->condp(), NodeUniop)->lhsp()->unlinkFrBackWithNext();
                 AstNode* const thensp = nodep->thensp()->unlinkFrBackWithNext();
                 AstNode* const elsesp = nodep->elsesp()->unlinkFrBackWithNext();
@@ -2986,9 +2980,9 @@ private:
                 AstNodeAssign* const thensp = VN_AS(nodep->thensp(), NodeAssign);
                 AstNodeAssign* const elsesp = VN_AS(nodep->elsesp(), NodeAssign);
                 thensp->unlinkFrBack();
-                AstNode* const condp = nodep->condp()->unlinkFrBack();
-                AstNode* const truep = thensp->rhsp()->unlinkFrBack();
-                AstNode* const falsep = elsesp->rhsp()->unlinkFrBack();
+                AstNodeExpr* const condp = nodep->condp()->unlinkFrBack();
+                AstNodeExpr* const truep = thensp->rhsp()->unlinkFrBack();
+                AstNodeExpr* const falsep = elsesp->rhsp()->unlinkFrBack();
                 thensp->rhsp(new AstCond(truep->fileline(), condp, truep, falsep));
                 nodep->replaceWith(thensp);
                 VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -2997,9 +2991,9 @@ private:
                        && operandIfIf(nodep)) {
                 UINFO(9, "IF({a}) IF({b}) => IF({a} && {b})" << endl);
                 AstNodeIf* const lowerIfp = VN_AS(nodep->thensp(), NodeIf);
-                AstNode* const condp = nodep->condp()->unlinkFrBack();
+                AstNodeExpr* const condp = nodep->condp()->unlinkFrBack();
                 AstNode* const lowerThensp = lowerIfp->thensp()->unlinkFrBackWithNext();
-                AstNode* const lowerCondp = lowerIfp->condp()->unlinkFrBackWithNext();
+                AstNodeExpr* const lowerCondp = lowerIfp->condp()->unlinkFrBackWithNext();
                 nodep->condp(new AstLogAnd(lowerIfp->fileline(), condp, lowerCondp));
                 lowerIfp->replaceWith(lowerThensp);
                 VL_DO_DANGLING(lowerIfp->deleteTree(), lowerIfp);
@@ -3355,7 +3349,7 @@ private:
     // This visit function here must allow for short-circuiting.
     TREEOPS("AstCond {$lhsp.isZero}",           "replaceWIteratedThs(nodep)");
     TREEOPS("AstCond {$lhsp.isNeqZero}",        "replaceWIteratedRhs(nodep)");
-    TREEOP ("AstCond{$condp.castNot,       $thenp, $elsep}", "AstCond{$condp->op1p(), $elsep, $thenp}");
+    TREEOP ("AstCond{$condp.castNot,       $thenp, $elsep}", "AstCond{$condp->castNot()->lhsp(), $elsep, $thenp}");
     TREEOP ("AstNodeCond{$condp.width1, $thenp.width1,   $thenp.isAllOnes, $elsep}", "AstLogOr {$condp, $elsep}");  // a?1:b == a||b
     TREEOP ("AstNodeCond{$condp.width1, $thenp.width1,   $thenp,    $elsep.isZero}", "AstLogAnd{$condp, $thenp}");  // a?b:0 == a&&b
     TREEOP ("AstNodeCond{$condp.width1, $thenp.width1,   $thenp, $elsep.isAllOnes}", "AstLogOr {AstNot{$condp}, $thenp}");  // a?b:1 == ~a||b
@@ -3386,36 +3380,36 @@ private:
     TREEOP1("AstLt   {$lhsp.isAllOnes, $rhsp, $lhsp->width()==$rhsp->width()}",  "replaceNumLimited(nodep,0)");
     TREEOP1("AstGte  {$lhsp.isAllOnes, $rhsp, $lhsp->width()==$rhsp->width()}",  "replaceNumLimited(nodep,1)");
     // Two level bubble pushing
-    TREEOP ("AstNot   {$lhsp.castNot,  $lhsp->width()==VN_AS($lhsp,,Not)->lhsp()->width()}", "replaceWChild(nodep, $lhsp->op1p())");  // NOT(NOT(x))->x
-    TREEOP ("AstLogNot{$lhsp.castLogNot}",              "replaceWChild(nodep, $lhsp->op1p())");  // LOGNOT(LOGNOT(x))->x
-    TREEOPV("AstNot   {$lhsp.castEqCase, $lhsp.width1}","AstNeqCase{$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castEqCase}",              "AstNeqCase{$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castNeqCase, $lhsp.width1}","AstEqCase {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castNeqCase}",             "AstEqCase {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castEqWild, $lhsp.width1}","AstNeqWild{$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castEqWild}",              "AstNeqWild{$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castNeqWild, $lhsp.width1}","AstEqWild {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castNeqWild}",             "AstEqWild {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castEq, $lhsp.width1}",    "AstNeq {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castEq}",                  "AstNeq {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castNeq, $lhsp.width1}",   "AstEq  {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castNeq}",                 "AstEq  {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castLt, $lhsp.width1}",    "AstGte {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castLt}",                  "AstGte {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castLtS, $lhsp.width1}",   "AstGteS{$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castLtS}",                 "AstGteS{$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castLte, $lhsp.width1}",   "AstGt  {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castLte}",                 "AstGt  {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castLteS, $lhsp.width1}",  "AstGtS {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castLteS}",                "AstGtS {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castGt, $lhsp.width1}",    "AstLte {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castGt}",                  "AstLte {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castGtS, $lhsp.width1}",   "AstLteS{$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castGtS}",                 "AstLteS{$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castGte, $lhsp.width1}",   "AstLt  {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castGte}",                 "AstLt  {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOPV("AstNot   {$lhsp.castGteS, $lhsp.width1}",  "AstLtS {$lhsp->op1p(),$lhsp->op2p()}");
-    TREEOP ("AstLogNot{$lhsp.castGteS}",                "AstLtS {$lhsp->op1p(),$lhsp->op2p()}");
+    TREEOP ("AstNot   {$lhsp.castNot,  $lhsp->width()==VN_AS($lhsp,,Not)->lhsp()->width()}", "replaceWChild(nodep, $lhsp->castNot()->lhsp())");  // NOT(NOT(x))->x
+    TREEOP ("AstLogNot{$lhsp.castLogNot}",              "replaceWChild(nodep, $lhsp->castLogNot()->lhsp())");  // LOGNOT(LOGNOT(x))->x
+    TREEOPV("AstNot   {$lhsp.castEqCase, $lhsp.width1}","AstNeqCase{$lhsp->castEqCase()->lhsp(),$lhsp->castEqCase()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castEqCase}",              "AstNeqCase{$lhsp->castEqCase()->lhsp(),$lhsp->castEqCase()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castNeqCase, $lhsp.width1}","AstEqCase{$lhsp->castNeqCase()->lhsp(),$lhsp->castNeqCase()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castNeqCase}",             "AstEqCase {$lhsp->castNeqCase()->lhsp(),$lhsp->castNeqCase()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castEqWild, $lhsp.width1}","AstNeqWild{$lhsp->castEqWild()->lhsp(),$lhsp->castEqWild()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castEqWild}",              "AstNeqWild{$lhsp->castEqWild()->lhsp(),$lhsp->castEqWild()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castNeqWild, $lhsp.width1}","AstEqWild{$lhsp->castNeqWild()->lhsp(),$lhsp->castNeqWild()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castNeqWild}",             "AstEqWild {$lhsp->castNeqWild()->lhsp(),$lhsp->castNeqWild()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castEq, $lhsp.width1}",    "AstNeq {$lhsp->castEq()->lhsp(),$lhsp->castEq()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castEq}",                  "AstNeq {$lhsp->castEq()->lhsp(),$lhsp->castEq()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castNeq, $lhsp.width1}",   "AstEq  {$lhsp->castNeq()->lhsp(),$lhsp->castNeq()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castNeq}",                 "AstEq  {$lhsp->castNeq()->lhsp(),$lhsp->castNeq()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castLt, $lhsp.width1}",    "AstGte {$lhsp->castLt()->lhsp(),$lhsp->castLt()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castLt}",                  "AstGte {$lhsp->castLt()->lhsp(),$lhsp->castLt()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castLtS, $lhsp.width1}",   "AstGteS{$lhsp->castLtS()->lhsp(),$lhsp->castLtS()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castLtS}",                 "AstGteS{$lhsp->castLtS()->lhsp(),$lhsp->castLtS()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castLte, $lhsp.width1}",   "AstGt  {$lhsp->castLte()->lhsp(),$lhsp->castLte()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castLte}",                 "AstGt  {$lhsp->castLte()->lhsp(),$lhsp->castLte()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castLteS, $lhsp.width1}",  "AstGtS {$lhsp->castLteS()->lhsp(),$lhsp->castLteS()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castLteS}",                "AstGtS {$lhsp->castLteS()->lhsp(),$lhsp->castLteS()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castGt, $lhsp.width1}",    "AstLte {$lhsp->castGt()->lhsp(),$lhsp->castGt()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castGt}",                  "AstLte {$lhsp->castGt()->lhsp(),$lhsp->castGt()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castGtS, $lhsp.width1}",   "AstLteS{$lhsp->castGtS()->lhsp(),$lhsp->castGtS()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castGtS}",                 "AstLteS{$lhsp->castGtS()->lhsp(),$lhsp->castGtS()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castGte, $lhsp.width1}",   "AstLt  {$lhsp->castGte()->lhsp(),$lhsp->castGte()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castGte}",                 "AstLt  {$lhsp->castGte()->lhsp(),$lhsp->castGte()->rhsp()}");
+    TREEOPV("AstNot   {$lhsp.castGteS, $lhsp.width1}",  "AstLtS {$lhsp->castGteS()->lhsp(),$lhsp->castGteS()->rhsp()}");
+    TREEOP ("AstLogNot{$lhsp.castGteS}",                "AstLtS {$lhsp->castGteS()->lhsp(),$lhsp->castGteS()->rhsp()}");
     // Not common, but avoids compiler warnings about over shifting
     TREEOP ("AstShiftL{operandHugeShiftL(nodep)}",      "replaceZero(nodep)");
     TREEOP ("AstShiftR{operandHugeShiftR(nodep)}",      "replaceZero(nodep)");
diff --git a/src/V3Const.h b/src/V3Const.h
index ada396efd..8cabc60d6 100644
--- a/src/V3Const.h
+++ b/src/V3Const.h
@@ -20,14 +20,16 @@
 #include "config_build.h"
 #include "verilatedos.h"
 
-class AstNetlist;
-class AstNode;
+#include "V3Ast.h"
 
 //============================================================================
 
 class V3Const final {
 public:
     static AstNode* constifyParamsEdit(AstNode* nodep);
+    static AstNodeExpr* constifyParamsEdit(AstNodeExpr* exprp) {
+        return VN_AS(constifyParamsEdit(static_cast<AstNode*>(exprp)), NodeExpr);
+    }
     static AstNode* constifyGenerateParamsEdit(AstNode* nodep);
     // Only do constant pushing, without removing dead logic
     static void constifyAllLive(AstNetlist* nodep);
@@ -40,9 +42,15 @@ public:
     // Only the current node and lower
     // Return new node that may have replaced nodep
     static AstNode* constifyEditCpp(AstNode* nodep);
+    static AstNodeExpr* constifyEditCpp(AstNodeExpr* exprp) {
+        return VN_AS(constifyEditCpp(static_cast<AstNode*>(exprp)), NodeExpr);
+    }
     // Only the current node and lower
     // Return new node that may have replaced nodep
     static AstNode* constifyEdit(AstNode* nodep);
+    static AstNodeExpr* constifyEdit(AstNodeExpr* exprp) {
+        return VN_AS(constifyEdit(static_cast<AstNode*>(exprp)), NodeExpr);
+    }
     // Only the current node and lower, with special SenTree optimization
     // Return new node that may have replaced nodep
     static AstNode* constifyExpensiveEdit(AstNode* nodep);
diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp
index 5dfb2f878..bd9d68927 100644
--- a/src/V3Coverage.cpp
+++ b/src/V3Coverage.cpp
@@ -47,9 +47,9 @@ private:
 
     struct ToggleEnt {
         const string m_comment;  // Comment for coverage dump
-        AstNode* m_varRefp;  // How to get to this element
-        AstNode* m_chgRefp;  // How to get to this element
-        ToggleEnt(const string& comment, AstNode* vp, AstNode* cp)
+        AstNodeExpr* m_varRefp;  // How to get to this element
+        AstNodeExpr* m_chgRefp;  // How to get to this element
+        ToggleEnt(const string& comment, AstNodeExpr* vp, AstNodeExpr* cp)
             : m_comment{comment}
             , m_varRefp{vp}
             , m_chgRefp{cp} {}
diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp
index db5a07182..6418f7f20 100644
--- a/src/V3Delayed.cpp
+++ b/src/V3Delayed.cpp
@@ -215,12 +215,12 @@ private:
         }
     }
 
-    AstNode* createDlyOnSet(AstAssignDly* nodep, AstNode* lhsp) {
+    AstNodeExpr* createDlyOnSet(AstAssignDly* nodep, AstNodeExpr* lhsp) {
         // Create delayed assignment
         // See top of this file for transformation
         // Return the new LHS for the assignment, Null = unlink
         // Find selects
-        AstNode* newlhsp = nullptr;  // nullptr = unlink old assign
+        AstNodeExpr* newlhsp = nullptr;  // nullptr = unlink old assign
         const AstSel* bitselp = nullptr;
         AstArraySel* arrayselp = nullptr;
         AstVarRef* varrefp = nullptr;
@@ -242,10 +242,10 @@ private:
             UINFO(4, "AssignDlyOnSet: " << nodep << endl);
         }
         //=== Dimensions: __Vdlyvdim__
-        std::deque<AstNode*> dimvalp;  // Assignment value for each dimension of assignment
+        std::deque<AstNodeExpr*> dimvalp;  // Assignment value for each dimension of assignment
         AstNode* dimselp = arrayselp;
         for (; VN_IS(dimselp, ArraySel); dimselp = VN_AS(dimselp, ArraySel)->fromp()) {
-            AstNode* const valp = VN_AS(dimselp, ArraySel)->bitp()->unlinkFrBack();
+            AstNodeExpr* const valp = VN_AS(dimselp, ArraySel)->bitp()->unlinkFrBack();
             dimvalp.push_front(valp);
         }
         if (dimselp) varrefp = VN_AS(dimselp, VarRef);
@@ -255,9 +255,9 @@ private:
         const AstVar* const oldvarp = varrefp->varp();
         const int modVecNum = m_scopeVecMap[varrefp->varScopep()]++;
         //
-        std::deque<AstNode*> dimreadps;  // Read value for each dimension of assignment
+        std::deque<AstNodeExpr*> dimreadps;  // Read value for each dimension of assignment
         for (unsigned dimension = 0; dimension < dimvalp.size(); dimension++) {
-            AstNode* const dimp = dimvalp[dimension];
+            AstNodeExpr* const dimp = dimvalp[dimension];
             if (VN_IS(dimp, Const)) {  // bit = const, can just use it
                 dimreadps.push_front(dimp);
             } else {
@@ -274,9 +274,9 @@ private:
         }
         //
         //=== Bitselect: __Vdlyvlsb__
-        AstNode* bitreadp = nullptr;  // Code to read Vdlyvlsb
+        AstNodeExpr* bitreadp = nullptr;  // Code to read Vdlyvlsb
         if (bitselp) {
-            AstNode* const lsbvaluep = bitselp->lsbp()->unlinkFrBack();
+            AstNodeExpr* const lsbvaluep = bitselp->lsbp()->unlinkFrBack();
             if (VN_IS(bitselp->fromp(), Const)) {
                 // vlsb = constant, can just push constant into where we use it
                 bitreadp = lsbvaluep;
@@ -294,7 +294,7 @@ private:
         }
         //
         //=== Value: __Vdlyvval__
-        AstNode* valreadp;  // Code to read Vdlyvval
+        AstNodeExpr* valreadp;  // Code to read Vdlyvval
         if (VN_IS(nodep->rhsp(), Const)) {
             // vval = constant, can just push constant into where we use it
             valreadp = nodep->rhsp()->unlinkFrBack();
@@ -342,7 +342,7 @@ private:
         // This ensures that multiple assignments to the same memory will result
         // in correctly ordered code - the last assignment must be last.
         // It also has the nice side effect of assisting cache locality.
-        AstNode* selectsp = varrefp;
+        AstNodeExpr* selectsp = varrefp;
         for (int dimension = int(dimreadps.size()) - 1; dimension >= 0; --dimension) {
             selectsp = new AstArraySel(nodep->fileline(), selectsp, dimreadps[dimension]);
         }
@@ -519,8 +519,8 @@ private:
                              || (VN_IS(nodep->lhsp(), Sel)
                                  && VN_IS(VN_AS(nodep->lhsp(), Sel)->fromp(), ArraySel));
         if (m_procp->isSuspendable() || isArray) {
-            AstNode* const lhsp = nodep->lhsp();
-            AstNode* const newlhsp = createDlyOnSet(nodep, lhsp);
+            AstNodeExpr* const lhsp = nodep->lhsp();
+            AstNodeExpr* const newlhsp = createDlyOnSet(nodep, lhsp);
             if (m_inLoop && isArray) {
                 nodep->v3warn(BLKLOOPINIT, "Unsupported: Delayed assignment to array inside for "
                                            "loops (non-delayed is ok - see docs)");
diff --git a/src/V3Depth.cpp b/src/V3Depth.cpp
index fa1c31ea5..a9644165b 100644
--- a/src/V3Depth.cpp
+++ b/src/V3Depth.cpp
@@ -52,7 +52,7 @@ private:
 
     // METHODS
 
-    void createDeepTemp(AstNode* nodep) {
+    void createDeepTemp(AstNodeExpr* nodep) {
         UINFO(6, "  Deep  " << nodep << endl);
         // if (debug() >= 9) nodep->dumpTree(cout, "deep:");
         AstVar* const varp = new AstVar{nodep->fileline(), VVarType::STMTTEMP,
diff --git a/src/V3DfgDfgToAst.cpp b/src/V3DfgDfgToAst.cpp
index 315088dec..9075858d5 100644
--- a/src/V3DfgDfgToAst.cpp
+++ b/src/V3DfgDfgToAst.cpp
@@ -299,7 +299,7 @@ class DfgToAstVisitor final : DfgVisitor {
         });
     }
 
-    void addResultEquation(FileLine* flp, AstNode* lhsp, AstNode* rhsp) {
+    void addResultEquation(FileLine* flp, AstNodeExpr* lhsp, AstNodeExpr* rhsp) {
         m_modp->addStmtsp(new AstAssignW{flp, lhsp, rhsp});
         ++m_ctx.m_resultEquations;
     }
diff --git a/src/V3Expand.cpp b/src/V3Expand.cpp
index d67b05d5a..9bf955dde 100644
--- a/src/V3Expand.cpp
+++ b/src/V3Expand.cpp
@@ -92,17 +92,19 @@ private:
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
-    static AstNode* newWordAssign(AstNodeAssign* placep, int word, AstNode* lhsp, AstNode* rhsp) {
+    static AstNode* newWordAssign(AstNodeAssign* placep, int word, AstNodeExpr* lhsp,
+                                  AstNodeExpr* rhsp) {
         FileLine* const fl = placep->fileline();
         return new AstAssign{fl,
                              new AstWordSel{fl, lhsp->cloneTree(true),
                                             new AstConst{fl, static_cast<uint32_t>(word)}},
                              rhsp};
     }
-    static void addWordAssign(AstNodeAssign* placep, int word, AstNode* lhsp, AstNode* rhsp) {
+    static void addWordAssign(AstNodeAssign* placep, int word, AstNodeExpr* lhsp,
+                              AstNodeExpr* rhsp) {
         insertBefore(placep, newWordAssign(placep, word, lhsp, rhsp));
     }
-    static void addWordAssign(AstNodeAssign* placep, int word, AstNode* rhsp) {
+    static void addWordAssign(AstNodeAssign* placep, int word, AstNodeExpr* rhsp) {
         addWordAssign(placep, word, placep->lhsp(), rhsp);
     }
 
@@ -117,7 +119,7 @@ private:
         if (nodep->op4p()) fixCloneLvalue(nodep->op4p());
     }
 
-    static AstNode* newAstWordSelClone(AstNode* nodep, int word) {
+    static AstNodeExpr* newAstWordSelClone(AstNodeExpr* nodep, int word) {
         // Get the specified word number from a wide array
         // Or, if it's a long/quad, do appropriate conversion to wide
         // Concat may pass negative word numbers, that means it wants a zero
@@ -126,11 +128,11 @@ private:
             return new AstWordSel{fl, nodep->cloneTree(true),
                                   new AstConst{fl, static_cast<uint32_t>(word)}};
         } else if (nodep->isQuad() && word == 0) {
-            AstNode* const quadfromp = nodep->cloneTree(true);
+            AstNodeExpr* const quadfromp = nodep->cloneTree(true);
             quadfromp->dtypeSetBitUnsized(VL_QUADSIZE, quadfromp->widthMin(), VSigning::UNSIGNED);
             return new AstCCast{fl, quadfromp, VL_EDATASIZE};
         } else if (nodep->isQuad() && word == 1) {
-            AstNode* const quadfromp = nodep->cloneTree(true);
+            AstNodeExpr* const quadfromp = nodep->cloneTree(true);
             quadfromp->dtypeSetBitUnsized(VL_QUADSIZE, quadfromp->widthMin(), VSigning::UNSIGNED);
             return new AstCCast{
                 fl, new AstShiftR{fl, quadfromp, new AstConst{fl, VL_EDATASIZE}, VL_EDATASIZE},
@@ -142,16 +144,16 @@ private:
         }
     }
 
-    static AstNode* newWordGrabShift(FileLine* fl, int word, AstNode* lhsp, int shift) {
+    static AstNodeExpr* newWordGrabShift(FileLine* fl, int word, AstNodeExpr* lhsp, int shift) {
         // Extract the expression to grab the value for the specified word, if it's the shift
         // of shift bits from lhsp
-        AstNode* newp;
+        AstNodeExpr* newp;
         // Negative word numbers requested for lhs when it's "before" what we want.
         // We get a 0 then.
         const int othword = word - shift / VL_EDATASIZE;
-        AstNode* const llowp = newAstWordSelClone(lhsp, othword);
+        AstNodeExpr* const llowp = newAstWordSelClone(lhsp, othword);
         if (const int loffset = VL_BITBIT_E(shift)) {
-            AstNode* const lhip = newAstWordSelClone(lhsp, othword - 1);
+            AstNodeExpr* const lhip = newAstWordSelClone(lhsp, othword - 1);
             const int nbitsonright = VL_EDATASIZE - loffset;  // bits that end up in lword
             newp = new AstOr{
                 fl,
@@ -170,8 +172,8 @@ private:
         return newp;
     }
 
-    static AstNode* newWordSel(FileLine* fl, AstNode* fromp, AstNode* lsbp,
-                               uint32_t wordOffset = 0) {
+    static AstNodeExpr* newWordSel(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* lsbp,
+                                   uint32_t wordOffset = 0) {
         // Return equation to get the VL_BITWORD of a constant or non-constant
         UASSERT_OBJ(fromp->isWide(), fromp, "Only need AstWordSel on wide from's");
         if (wordOffset >= static_cast<uint32_t>(fromp->widthWords())) {
@@ -181,7 +183,7 @@ private:
             // AstCondBound is protecting above this node.
             return new AstConst{fl, AstConst::SizedEData(), 0};
         } else {
-            AstNode* wordp;
+            AstNodeExpr* wordp;
             FileLine* const lfl = lsbp->fileline();
             if (VN_IS(lsbp, Const)) {
                 wordp = new AstConst{lfl, wordOffset + VL_BITWORD_E(VN_AS(lsbp, Const)->toUInt())};
@@ -197,7 +199,7 @@ private:
         }
     }
 
-    static AstNode* dropCondBound(AstNode* nodep) {
+    static AstNodeExpr* dropCondBound(AstNodeExpr* nodep) {
         // Experimental only...
         //  If there's a CONDBOUND safety to keep arrays in bounds,
         //  we're going to AND it to a value that always fits inside a
@@ -208,7 +210,7 @@ private:
         return nodep;
     }
 
-    static AstNode* newSelBitBit(AstNode* lsbp) {
+    static AstNodeExpr* newSelBitBit(AstNodeExpr* lsbp) {
         // Return equation to get the VL_BITBIT of a constant or non-constant
         FileLine* const fl = lsbp->fileline();
         if (VN_IS(lsbp, Const)) {
@@ -320,8 +322,8 @@ private:
         if (nodep->isWide()) {
             // See under ASSIGN(EXTEND)
         } else {
-            AstNode* const lhsp = nodep->lhsp()->unlinkFrBack();
-            AstNode* newp = lhsp;
+            AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
+            AstNodeExpr* newp = lhsp;
             if (nodep->isQuad()) {
                 if (lhsp->isQuad()) {
                     lhsp->dtypeFrom(nodep);  // Just mark it, else nop
@@ -359,28 +361,29 @@ private:
             FileLine* const nfl = nodep->fileline();
             FileLine* const lfl = nodep->lsbp()->fileline();
             FileLine* const ffl = nodep->fromp()->fileline();
-            AstNode* lowwordp = newWordSel(ffl, nodep->fromp()->cloneTree(true), nodep->lsbp());
+            AstNodeExpr* lowwordp
+                = newWordSel(ffl, nodep->fromp()->cloneTree(true), nodep->lsbp());
             if (nodep->isQuad() && !lowwordp->isQuad()) {
                 lowwordp = new AstCCast{nfl, lowwordp, nodep};
             }
-            AstNode* const lowp
+            AstNodeExpr* const lowp
                 = new AstShiftR{nfl, lowwordp, newSelBitBit(nodep->lsbp()), nodep->width()};
             // If > 1 bit, we might be crossing the word boundary
-            AstNode* midp = nullptr;
+            AstNodeExpr* midp = nullptr;
             if (nodep->widthConst() > 1) {
                 const uint32_t midMsbOffset
                     = std::min<uint32_t>(nodep->widthConst(), VL_EDATASIZE) - 1;
-                AstNode* const midMsbp = new AstAdd{lfl, new AstConst{lfl, midMsbOffset},
-                                                    nodep->lsbp()->cloneTree(false)};
-                AstNode* midwordp =  // SEL(from,[midwordnum])
+                AstNodeExpr* const midMsbp = new AstAdd{lfl, new AstConst{lfl, midMsbOffset},
+                                                        nodep->lsbp()->cloneTree(false)};
+                AstNodeExpr* midwordp =  // SEL(from,[midwordnum])
                     newWordSel(ffl, nodep->fromp()->cloneTree(true), midMsbp, 0);
                 // newWordSel clones the index, so delete it
                 VL_DO_DANGLING(midMsbp->deleteTree(), midMsbp);
                 if (nodep->isQuad() && !midwordp->isQuad()) {
                     midwordp = new AstCCast{nfl, midwordp, nodep};
                 }
-                AstNode* const midshiftp = new AstSub{lfl, new AstConst{lfl, VL_EDATASIZE},
-                                                      newSelBitBit(nodep->lsbp())};
+                AstNodeExpr* const midshiftp = new AstSub{lfl, new AstConst{lfl, VL_EDATASIZE},
+                                                          newSelBitBit(nodep->lsbp())};
                 // If we're selecting bit zero, then all 32 bits in the mid word
                 // get shifted << by 32 bits, so ignore them.
                 const V3Number zero{nodep, longOrQuadWidth(nodep)};
@@ -395,19 +398,19 @@ private:
                     new AstShiftL{nfl, midwordp, midshiftp, nodep->width()}};
             }
             // If > 32 bits, we might be crossing the second word boundary
-            AstNode* hip = nullptr;
+            AstNodeExpr* hip = nullptr;
             if (nodep->widthConst() > VL_EDATASIZE) {
                 const uint32_t hiMsbOffset = nodep->widthConst() - 1;
-                AstNode* const hiMsbp = new AstAdd{lfl, new AstConst{lfl, hiMsbOffset},
-                                                   nodep->lsbp()->cloneTree(false)};
-                AstNode* hiwordp =  // SEL(from,[hiwordnum])
+                AstNodeExpr* const hiMsbp = new AstAdd{lfl, new AstConst{lfl, hiMsbOffset},
+                                                       nodep->lsbp()->cloneTree(false)};
+                AstNodeExpr* hiwordp =  // SEL(from,[hiwordnum])
                     newWordSel(ffl, nodep->fromp()->cloneTree(true), hiMsbp);
                 // newWordSel clones the index, so delete it
                 VL_DO_DANGLING(hiMsbp->deleteTree(), hiMsbp);
                 if (nodep->isQuad() && !hiwordp->isQuad()) {
                     hiwordp = new AstCCast{nfl, hiwordp, nodep};
                 }
-                AstNode* const hishiftp = new AstCond{
+                AstNodeExpr* const hishiftp = new AstCond{
                     nfl,
                     // lsb % VL_EDATASIZE == 0 ?
                     new AstEq{nfl, new AstConst{nfl, 0}, newSelBitBit(nodep->lsbp())},
@@ -418,7 +421,7 @@ private:
                 hip = new AstShiftL{nfl, hiwordp, hishiftp, nodep->width()};
             }
 
-            AstNode* newp = lowp;
+            AstNodeExpr* newp = lowp;
             if (midp) newp = new AstOr{nfl, midp, newp};
             if (hip) newp = new AstOr{nfl, hip, newp};
             newp->dtypeFrom(nodep);
@@ -426,11 +429,11 @@ private:
         } else {  // Long/Quad from Long/Quad
             UINFO(8, "    SEL->SHIFT " << nodep << endl);
             FileLine* const fl = nodep->fileline();
-            AstNode* fromp = nodep->fromp()->unlinkFrBack();
-            AstNode* const lsbp = nodep->lsbp()->unlinkFrBack();
+            AstNodeExpr* fromp = nodep->fromp()->unlinkFrBack();
+            AstNodeExpr* const lsbp = nodep->lsbp()->unlinkFrBack();
             if (nodep->isQuad() && !fromp->isQuad()) { fromp = new AstCCast{fl, fromp, nodep}; }
             // {large}>>32 requires 64-bit shift operation; then cast
-            AstNode* newp = new AstShiftR{fl, fromp, dropCondBound(lsbp), fromp->width()};
+            AstNodeExpr* newp = new AstShiftR{fl, fromp, dropCondBound(lsbp), fromp->width()};
             newp->dtypeFrom(fromp);
             if (!nodep->isQuad() && fromp->isQuad()) { newp = new AstCCast{fl, newp, nodep}; }
             newp->dtypeFrom(nodep);
@@ -456,21 +459,21 @@ private:
             FileLine* const lfl = rhsp->lsbp()->fileline();
             for (int w = 0; w < nodep->widthWords(); ++w) {
                 // Grab lowest bits
-                AstNode* const lowwordp
+                AstNodeExpr* const lowwordp
                     = newWordSel(rfl, rhsp->fromp()->cloneTree(true), rhsp->lsbp(), w);
-                AstNode* const lowp
+                AstNodeExpr* const lowp
                     = new AstShiftR{rfl, lowwordp, newSelBitBit(rhsp->lsbp()), VL_EDATASIZE};
                 // Upper bits
                 const V3Number zero{nodep, VL_EDATASIZE, 0};
-                AstNode* const midwordp =  // SEL(from,[1+wordnum])
+                AstNodeExpr* const midwordp =  // SEL(from,[1+wordnum])
                     newWordSel(ffl, rhsp->fromp()->cloneTree(true), rhsp->lsbp(), w + 1);
-                AstNode* const midshiftp
+                AstNodeExpr* const midshiftp
                     = new AstSub{lfl, new AstConst{lfl, VL_EDATASIZE}, newSelBitBit(rhsp->lsbp())};
-                AstNode* const midmayp = new AstShiftL{rfl, midwordp, midshiftp, VL_EDATASIZE};
-                AstNode* const midp = new AstCond{
+                AstNodeExpr* const midmayp = new AstShiftL{rfl, midwordp, midshiftp, VL_EDATASIZE};
+                AstNodeExpr* const midp = new AstCond{
                     rfl, new AstEq{rfl, new AstConst{rfl, 0}, newSelBitBit(rhsp->lsbp())},
                     new AstConst{rfl, zero}, midmayp};
-                AstNode* const newp = new AstOr{nfl, midp, lowp};
+                AstNodeExpr* const newp = new AstOr{nfl, midp, lowp};
                 addWordAssign(nodep, w, newp);
             }
             return true;
@@ -491,8 +494,8 @@ private:
         if (VN_IS(lhsp->lsbp(), Const)) {
             // The code should work without this constant test, but it won't
             // constify as nicely as we'd like.
-            AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
-            AstNode* const destp = lhsp->fromp()->unlinkFrBack();
+            AstNodeExpr* rhsp = nodep->rhsp()->unlinkFrBack();
+            AstNodeExpr* const destp = lhsp->fromp()->unlinkFrBack();
             const int lsb = lhsp->lsbConst();
             const int msb = lhsp->msbConst();
             V3Number maskset{nodep, destp->widthMin()};
@@ -504,7 +507,7 @@ private:
                 for (int w = 0; w < destp->widthWords(); ++w) {
                     if (w >= VL_BITWORD_E(lsb) && w <= VL_BITWORD_E(msb)) {
                         // else we would just be setting it to the same exact value
-                        AstNode* oldvalp = newAstWordSelClone(destp, w);
+                        AstNodeExpr* oldvalp = newAstWordSelClone(destp, w);
                         fixCloneLvalue(oldvalp);
                         if (!ones) {
                             oldvalp = new AstAnd{
@@ -514,7 +517,7 @@ private:
                         }
 
                         // Appropriate word of new value to insert:
-                        AstNode* newp = newWordGrabShift(lfl, w, rhsp, lsb);
+                        AstNodeExpr* newp = newWordGrabShift(lfl, w, rhsp, lsb);
 
                         // Apply cleaning at the top word of the destination
                         // (no cleaning to do if dst's width is a whole number
@@ -524,7 +527,7 @@ private:
                             cleanmask.setMask(VL_BITBIT_E(destp->widthMin()));
                             newp = new AstAnd{lfl, newp, new AstConst{lfl, cleanmask}};
                         }
-                        AstNode* const orp
+                        AstNodeExpr* const orp
                             = V3Const::constifyEditCpp(new AstOr{lfl, oldvalp, newp});
                         addWordAssign(nodep, w, destp, orp);
                     }
@@ -534,7 +537,7 @@ private:
             } else {
                 UINFO(8, "    ASSIGNSEL(const,narrow) " << nodep << endl);
                 if (destp->isQuad() && !rhsp->isQuad()) { rhsp = new AstCCast{nfl, rhsp, nodep}; }
-                AstNode* oldvalp = destp->cloneTree(true);
+                AstNodeExpr* oldvalp = destp->cloneTree(true);
                 fixCloneLvalue(oldvalp);
                 if (!ones) { oldvalp = new AstAnd{lfl, new AstConst{lfl, maskold}, oldvalp}; }
 
@@ -543,20 +546,21 @@ private:
                 // valid range of nodep which we apply to the new shifted RHS.
                 V3Number cleanmask{nodep, destp->widthMin()};
                 cleanmask.setMask(destp->widthMin());
-                AstNode* const shifted = new AstShiftL{
+                AstNodeExpr* const shifted = new AstShiftL{
                     lfl, rhsp, new AstConst{lfl, static_cast<uint32_t>(lsb)}, destp->width()};
-                AstNode* const cleaned = new AstAnd{lfl, shifted, new AstConst{lfl, cleanmask}};
-                AstNode* const orp = V3Const::constifyEditCpp(new AstOr{lfl, oldvalp, cleaned});
-                AstNode* newp = new AstAssign{nfl, destp, orp};
-                insertBefore(nodep, newp);
+                AstNodeExpr* const cleaned
+                    = new AstAnd{lfl, shifted, new AstConst{lfl, cleanmask}};
+                AstNodeExpr* const orp
+                    = V3Const::constifyEditCpp(new AstOr{lfl, oldvalp, cleaned});
+                insertBefore(nodep, new AstAssign{nfl, destp, orp});
             }
             return true;
         } else {  // non-const select offset
             if (destwide && lhsp->widthConst() == 1) {
                 UINFO(8, "    ASSIGNSEL(varlsb,wide,1bit) " << nodep << endl);
-                AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
-                AstNode* const destp = lhsp->fromp()->unlinkFrBack();
-                AstNode* oldvalp = newWordSel(lfl, destp->cloneTree(true), lhsp->lsbp());
+                AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
+                AstNodeExpr* const destp = lhsp->fromp()->unlinkFrBack();
+                AstNodeExpr* oldvalp = newWordSel(lfl, destp->cloneTree(true), lhsp->lsbp());
                 fixCloneLvalue(oldvalp);
                 if (!ones) {
                     oldvalp = new AstAnd{
@@ -570,8 +574,8 @@ private:
                         oldvalp};
                 }
                 // Restrict the shift amount to 0-31, see bug804.
-                AstNode* const shiftp = new AstAnd{nfl, lhsp->lsbp()->cloneTree(true),
-                                                   new AstConst{nfl, VL_EDATASIZE - 1}};
+                AstNodeExpr* const shiftp = new AstAnd{nfl, lhsp->lsbp()->cloneTree(true),
+                                                       new AstConst{nfl, VL_EDATASIZE - 1}};
                 AstNode* const newp = new AstAssign{
                     nfl, newWordSel(nfl, destp, lhsp->lsbp()),
                     new AstOr{lfl, oldvalp, new AstShiftL{lfl, rhsp, shiftp, VL_EDATASIZE}}};
@@ -592,9 +596,9 @@ private:
             } else {
                 UINFO(8, "    ASSIGNSEL(varlsb,narrow) " << nodep << endl);
                 // nodep->dumpTree(cout, "-  old: ");
-                AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
-                AstNode* const destp = lhsp->fromp()->unlinkFrBack();
-                AstNode* oldvalp = destp->cloneTree(true);
+                AstNodeExpr* rhsp = nodep->rhsp()->unlinkFrBack();
+                AstNodeExpr* const destp = lhsp->fromp()->unlinkFrBack();
+                AstNodeExpr* oldvalp = destp->cloneTree(true);
                 fixCloneLvalue(oldvalp);
 
                 V3Number maskwidth{nodep, destp->widthMin()};
@@ -609,7 +613,7 @@ private:
                                                  lhsp->lsbp()->cloneTree(true), destp->width()}},
                         oldvalp};
                 }
-                AstNode* newp
+                AstNodeExpr* newp
                     = new AstShiftL{lfl, rhsp, lhsp->lsbp()->cloneTree(true), destp->width()};
                 // Apply cleaning to the new value being inserted.  Mask is
                 // slightly wider than necessary to avoid an AND with all ones
@@ -621,9 +625,7 @@ private:
                     newp = new AstAnd{lfl, newp, new AstConst{lfl, cleanmask}};
                 }
 
-                newp = new AstAssign{nfl, destp, new AstOr{lfl, oldvalp, newp}};
-                // newp->dumpTree(cout, "-  new: ");
-                insertBefore(nodep, newp);
+                insertBefore(nodep, new AstAssign{nfl, destp, new AstOr{lfl, oldvalp, newp}});
                 return true;
             }
         }
@@ -637,12 +639,12 @@ private:
         } else {
             UINFO(8, "    CONCAT " << nodep << endl);
             FileLine* const fl = nodep->fileline();
-            AstNode* lhsp = nodep->lhsp()->unlinkFrBack();
-            AstNode* rhsp = nodep->rhsp()->unlinkFrBack();
+            AstNodeExpr* lhsp = nodep->lhsp()->unlinkFrBack();
+            AstNodeExpr* rhsp = nodep->rhsp()->unlinkFrBack();
             const uint32_t rhsshift = rhsp->widthMin();
             if (nodep->isQuad() && !lhsp->isQuad()) { lhsp = new AstCCast{fl, lhsp, nodep}; }
             if (nodep->isQuad() && !rhsp->isQuad()) { rhsp = new AstCCast{fl, rhsp, nodep}; }
-            AstNode* const newp = new AstOr{
+            AstNodeExpr* const newp = new AstOr{
                 fl, new AstShiftL{fl, lhsp, new AstConst{fl, rhsshift}, nodep->width()}, rhsp};
             newp->dtypeFrom(nodep);  // Unsigned
             VL_DO_DANGLING(replaceWithDelete(nodep, newp), nodep);
@@ -673,8 +675,8 @@ private:
             // See under ASSIGN(WIDE)
         } else {
             FileLine* const fl = nodep->fileline();
-            AstNode* lhsp = nodep->lhsp()->unlinkFrBack();
-            AstNode* newp;
+            AstNodeExpr* lhsp = nodep->lhsp()->unlinkFrBack();
+            AstNodeExpr* newp;
             const int lhswidth = lhsp->widthMin();
             if (lhswidth == 1) {
                 UINFO(8, "    REPLICATE(w1) " << nodep << endl);
@@ -707,13 +709,13 @@ private:
         UINFO(8, "    Wordize ASSIGN(REPLICATE) " << nodep << endl);
         if (!doExpand(rhsp)) return false;
         FileLine* const fl = nodep->fileline();
-        AstNode* const lhsp = rhsp->lhsp();
+        AstNodeExpr* const lhsp = rhsp->lhsp();
         const int lhswidth = lhsp->widthMin();
         const AstConst* const constp = VN_AS(rhsp->rhsp(), Const);
         UASSERT_OBJ(constp, rhsp, "Replication value isn't a constant.  Checked earlier!");
         const uint32_t times = constp->toUInt();
         for (int w = 0; w < rhsp->widthWords(); ++w) {
-            AstNode* newp;
+            AstNodeExpr* newp;
             if (lhswidth == 1) {
                 newp = new AstNegate{fl, lhsp->cloneTree(true)};
                 // Replicate always unsigned
@@ -737,10 +739,10 @@ private:
             UINFO(8, "    Wordize EQ/NEQ " << nodep << endl);
             // -> (0=={or{for each_word{WORDSEL(lhs,#)^WORDSEL(rhs,#)}}}
             FileLine* const fl = nodep->fileline();
-            AstNode* newp = nullptr;
+            AstNodeExpr* newp = nullptr;
             for (int w = 0; w < nodep->lhsp()->widthWords(); ++w) {
-                AstNode* const eqp = new AstXor{fl, newAstWordSelClone(nodep->lhsp(), w),
-                                                newAstWordSelClone(nodep->rhsp(), w)};
+                AstNodeExpr* const eqp = new AstXor{fl, newAstWordSelClone(nodep->lhsp(), w),
+                                                    newAstWordSelClone(nodep->rhsp(), w)};
                 newp = newp ? new AstOr{fl, newp, eqp} : eqp;
             }
             if (VN_IS(nodep, Neq)) {
@@ -761,17 +763,17 @@ private:
         if (nodep->lhsp()->isWide()) {
             UINFO(8, "    Wordize REDOR " << nodep << endl);
             // -> (0!={or{for each_word{WORDSEL(lhs,#)}}}
-            AstNode* newp = nullptr;
+            AstNodeExpr* newp = nullptr;
             for (int w = 0; w < nodep->lhsp()->widthWords(); ++w) {
-                AstNode* const eqp = newAstWordSelClone(nodep->lhsp(), w);
+                AstNodeExpr* const eqp = newAstWordSelClone(nodep->lhsp(), w);
                 newp = newp ? new AstOr{fl, newp, eqp} : eqp;
             }
             newp = new AstNeq{fl, new AstConst{fl, AstConst::SizedEData(), 0}, newp};
             VL_DO_DANGLING(replaceWithDelete(nodep, newp), nodep);
         } else {
             UINFO(8, "    REDOR->EQ " << nodep << endl);
-            AstNode* const lhsp = nodep->lhsp()->unlinkFrBack();
-            AstNode* const newp = new AstNeq{
+            AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
+            AstNodeExpr* const newp = new AstNeq{
                 fl, new AstConst{fl, AstConst::WidthedValue(), longOrQuadWidth(nodep), 0}, lhsp};
             VL_DO_DANGLING(replaceWithDelete(nodep, newp), nodep);
         }
@@ -783,9 +785,9 @@ private:
         if (nodep->lhsp()->isWide()) {
             UINFO(8, "    Wordize REDAND " << nodep << endl);
             // -> (0!={and{for each_word{WORDSEL(lhs,#)}}}
-            AstNode* newp = nullptr;
+            AstNodeExpr* newp = nullptr;
             for (int w = 0; w < nodep->lhsp()->widthWords(); ++w) {
-                AstNode* eqp = newAstWordSelClone(nodep->lhsp(), w);
+                AstNodeExpr* eqp = newAstWordSelClone(nodep->lhsp(), w);
                 if (w == nodep->lhsp()->widthWords() - 1) {
                     // Rather than doing a (slowish) ==##, we OR in the
                     // bits that aren't part of the mask
@@ -801,8 +803,8 @@ private:
             VL_DO_DANGLING(replaceWithDelete(nodep, newp), nodep);
         } else {
             UINFO(8, "    REDAND->EQ " << nodep << endl);
-            AstNode* const lhsp = nodep->lhsp()->unlinkFrBack();
-            AstNode* const newp = new AstEq{fl, new AstConst{fl, wordMask(lhsp)}, lhsp};
+            AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
+            AstNodeExpr* const newp = new AstEq{fl, new AstConst{fl, wordMask(lhsp)}, lhsp};
             VL_DO_DANGLING(replaceWithDelete(nodep, newp), nodep);
         }
     }
@@ -813,9 +815,9 @@ private:
             UINFO(8, "    Wordize REDXOR " << nodep << endl);
             // -> (0!={redxor{for each_word{XOR(WORDSEL(lhs,#))}}}
             FileLine* const fl = nodep->fileline();
-            AstNode* newp = nullptr;
+            AstNodeExpr* newp = nullptr;
             for (int w = 0; w < nodep->lhsp()->widthWords(); ++w) {
-                AstNode* const eqp = newAstWordSelClone(nodep->lhsp(), w);
+                AstNodeExpr* const eqp = newAstWordSelClone(nodep->lhsp(), w);
                 newp = newp ? new AstXor{fl, newp, eqp} : eqp;
             }
             newp = new AstRedXor{fl, newp};
diff --git a/src/V3Force.cpp b/src/V3Force.cpp
index 3c3b1c5de..84cdc972b 100644
--- a/src/V3Force.cpp
+++ b/src/V3Force.cpp
@@ -174,8 +174,8 @@ class ForceConvertVisitor final : public VNVisitor {
         pushDeletep(nodep);
 
         FileLine* const flp = nodep->fileline();
-        AstNode* const lhsp = nodep->lhsp();  // The LValue we are forcing
-        AstNode* const rhsp = nodep->rhsp();  // The value we are forcing it to
+        AstNodeExpr* const lhsp = nodep->lhsp();  // The LValue we are forcing
+        AstNodeExpr* const rhsp = nodep->rhsp();  // The value we are forcing it to
 
         // Set corresponding enable signals to ones
         V3Number ones{lhsp, lhsp->width()};
@@ -210,7 +210,7 @@ class ForceConvertVisitor final : public VNVisitor {
         pushDeletep(nodep);
 
         FileLine* const flp = nodep->fileline();
-        AstNode* const lhsp = nodep->lhsp();  // The LValue we are releasing
+        AstNodeExpr* const lhsp = nodep->lhsp();  // The LValue we are releasing
 
         // Set corresponding enable signals to zero
         V3Number zero{lhsp, lhsp->width()};
diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp
index 2de50c0b6..47ca87e48 100644
--- a/src/V3Inst.cpp
+++ b/src/V3Inst.cpp
@@ -70,14 +70,14 @@ private:
         // Use user1p on the PIN to indicate we created an assign for this pin
         if (!nodep->user1SetOnce()) {
             // Make an ASSIGNW (expr, pin)
-            AstNode* const exprp = nodep->exprp()->cloneTree(false);
+            AstNodeExpr* const exprp = VN_AS(nodep->exprp(), NodeExpr)->cloneTree(false);
             UASSERT_OBJ(exprp->width() == nodep->modVarp()->width(), nodep,
                         "Width mismatch, should have been handled in pinReconnectSimple");
             if (nodep->modVarp()->isInoutish()) {
                 nodep->v3fatalSrc("Unsupported: Verilator is a 2-state simulator");
             } else if (nodep->modVarp()->isWritable()) {
-                AstNode* const rhsp = new AstVarXRef(exprp->fileline(), nodep->modVarp(),
-                                                     m_cellp->name(), VAccess::READ);
+                AstNodeExpr* const rhsp = new AstVarXRef(exprp->fileline(), nodep->modVarp(),
+                                                         m_cellp->name(), VAccess::READ);
                 AstAssignW* const assp = new AstAssignW(exprp->fileline(), exprp, rhsp);
                 m_cellp->addNextHere(assp);
             } else if (nodep->modVarp()->isNonOutput()) {
@@ -97,8 +97,8 @@ private:
                                IfaceRefDType))) {
                 // Create an AstAssignVarScope for Vars to Cells so we can
                 // link with their scope later
-                AstNode* const lhsp = new AstVarXRef(exprp->fileline(), nodep->modVarp(),
-                                                     m_cellp->name(), VAccess::READ);
+                AstNodeExpr* const lhsp = new AstVarXRef(exprp->fileline(), nodep->modVarp(),
+                                                         m_cellp->name(), VAccess::READ);
                 const AstVarRef* const refp = VN_CAST(exprp, VarRef);
                 const AstVarXRef* const xrefp = VN_CAST(exprp, VarXRef);
                 UASSERT_OBJ(refp || xrefp, exprp,
@@ -334,7 +334,7 @@ private:
                 const int arraySelNum = rangep->littleEndian()
                                             ? (rangep->elementsConst() - 1 - m_instSelNum)
                                             : m_instSelNum;
-                AstNode* exprp = nodep->exprp()->unlinkFrBack();
+                AstNodeExpr* exprp = VN_AS(nodep->exprp(), NodeExpr)->unlinkFrBack();
                 exprp = new AstArraySel(exprp->fileline(), exprp, arraySelNum);
                 nodep->exprp(exprp);
             } else if (expwidth == modwidth) {
@@ -348,7 +348,7 @@ private:
                                                           << m_cellRangep->leftConst() << ":"
                                                           << m_cellRangep->rightConst() << "]");
                 }
-                AstNode* exprp = nodep->exprp()->unlinkFrBack();
+                AstNodeExpr* exprp = VN_AS(nodep->exprp(), NodeExpr)->unlinkFrBack();
                 const bool inputPin = nodep->modVarp()->isNonOutput();
                 if (!inputPin
                     && !VN_IS(exprp, VarRef)
@@ -489,10 +489,10 @@ class InstStatic final {
 private:
     InstStatic() = default;  // Static class
 
-    static AstNode* extendOrSel(FileLine* fl, AstNode* rhsp, AstNode* cmpWidthp) {
+    static AstNodeExpr* extendOrSel(FileLine* fl, AstNodeExpr* rhsp, AstNode* cmpWidthp) {
         if (cmpWidthp->width() > rhsp->width()) {
-            rhsp = (rhsp->isSigned() ? static_cast<AstNode*>(new AstExtendS{fl, rhsp})
-                                     : static_cast<AstNode*>(new AstExtend{fl, rhsp}));
+            rhsp = (rhsp->isSigned() ? static_cast<AstNodeExpr*>(new AstExtendS{fl, rhsp})
+                                     : static_cast<AstNodeExpr*>(new AstExtend{fl, rhsp}));
             // Need proper widthMin, which may differ from AstSel created above
             rhsp->dtypeFrom(cmpWidthp);
         } else if (cmpWidthp->width() < rhsp->width()) {
@@ -553,7 +553,7 @@ public:
             // Make a new temp wire
             // if (1 || debug() >= 9) pinp->dumpTree(cout, "-in_pin:");
             V3Inst::checkOutputShort(pinp);
-            AstNode* const pinexprp = pinp->exprp()->unlinkFrBack();
+            AstNodeExpr* const pinexprp = VN_AS(pinp->exprp(), NodeExpr)->unlinkFrBack();
             const string newvarname
                 = (string(pinVarp->isWritable() ? "__Vcellout" : "__Vcellinp")
                    // Prevent name conflict if both tri & non-tri add signals
@@ -568,12 +568,12 @@ public:
                                     " direct one-to-one connection (without any expression)");
             } else if (pinVarp->isWritable()) {
                 // See also V3Inst
-                AstNode* rhsp = new AstVarRef(pinp->fileline(), newvarp, VAccess::READ);
+                AstNodeExpr* rhsp = new AstVarRef(pinp->fileline(), newvarp, VAccess::READ);
                 UINFO(5, "pinRecon width " << pinVarp->width() << " >? " << rhsp->width() << " >? "
                                            << pinexprp->width() << endl);
                 rhsp = extendOrSel(pinp->fileline(), rhsp, pinVarp);
                 pinp->exprp(new AstVarRef(newvarp->fileline(), newvarp, VAccess::WRITE));
-                AstNode* const rhsSelp = extendOrSel(pinp->fileline(), rhsp, pinexprp);
+                AstNodeExpr* const rhsSelp = extendOrSel(pinp->fileline(), rhsp, pinexprp);
                 assignp = new AstAssignW(pinp->fileline(), pinexprp, rhsSelp);
             } else {
                 // V3 width should have range/extended to make the widths correct
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index e80ac901a..bfc1c33e8 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1223,7 +1223,7 @@ class LinkDotFindVisitor final : public VNVisitor {
                     // new value.
                     if (v3Global.opt.hasParameter(nodep->name())) {
                         const string svalue = v3Global.opt.parameter(nodep->name());
-                        if (AstNode* const valuep
+                        if (AstConst* const valuep
                             = AstConst::parseParamLiteral(nodep->fileline(), svalue)) {
                             UINFO(9, "       replace parameter " << nodep << endl);
                             UINFO(9, "       with " << valuep << endl);
@@ -1366,7 +1366,7 @@ class LinkDotFindVisitor final : public VNVisitor {
             // DOT(x, SELLOOPVARS(var, loops)) -> SELLOOPVARS(DOT(x, var), loops)
             if (AstDot* const dotp = VN_CAST(nodep->arrayp(), Dot)) {
                 if (AstSelLoopVars* const loopvarsp = VN_CAST(dotp->rhsp(), SelLoopVars)) {
-                    AstNode* const fromp = loopvarsp->fromp()->unlinkFrBack();
+                    AstNodeExpr* const fromp = loopvarsp->fromp()->unlinkFrBack();
                     loopvarsp->unlinkFrBack();
                     dotp->replaceWith(loopvarsp);
                     dotp->rhsp(fromp);
@@ -1540,7 +1540,7 @@ private:
         if (!cellp) {
             nodep->v3error("In defparam, instance " << nodep->path() << " never declared");
         } else {
-            AstNode* const exprp = nodep->rhsp()->unlinkFrBack();
+            AstNodeExpr* const exprp = nodep->rhsp()->unlinkFrBack();
             UINFO(9, "Defparam cell " << nodep->path() << "." << nodep->name() << " attach-to "
                                       << cellp << "  <= " << exprp << endl);
             // Don't need to check the name of the defparam exists.  V3Param does.
@@ -2295,7 +2295,7 @@ private:
                 nodep->replaceWith(newp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
             } else {  // Dot midpoint
-                AstNode* newp = nodep->rhsp()->unlinkFrBack();
+                AstNodeExpr* newp = nodep->rhsp()->unlinkFrBack();
                 if (m_ds.m_unresolved) {
                     AstCellRef* const crp = new AstCellRef(nodep->fileline(), nodep->name(),
                                                            nodep->lhsp()->unlinkFrBack(), newp);
@@ -2358,8 +2358,8 @@ private:
             return;
         } else if (m_ds.m_dotPos == DP_MEMBER) {
             // Found a Var, everything following is membership.  {scope}.{var}.HERE {member}
-            AstNode* const varEtcp = m_ds.m_dotp->lhsp()->unlinkFrBack();
-            AstNode* const newp
+            AstNodeExpr* const varEtcp = m_ds.m_dotp->lhsp()->unlinkFrBack();
+            AstNodeExpr* const newp
                 = new AstMemberSel(nodep->fileline(), varEtcp, VFlagChildDType(), nodep->name());
             if (m_ds.m_dotErr) {
                 nodep->unlinkFrBack();  // Avoid circular node loop on errors
@@ -2545,7 +2545,8 @@ private:
                     m_ds.m_dotPos = DP_SCOPE;
                     UINFO(9, " modport -> iface varref " << foundp->nodep() << endl);
                     // We lose the modport name here, so we cannot detect mismatched modports.
-                    AstNode* newp = new AstVarRef{nodep->fileline(), ifaceRefVarp, VAccess::READ};
+                    AstNodeExpr* newp
+                        = new AstVarRef{nodep->fileline(), ifaceRefVarp, VAccess::READ};
                     auto* const cellarrayrefp = VN_CAST(m_ds.m_unlinkedScopep, CellArrayRef);
                     if (cellarrayrefp) {
                         // iface[vec].modport became CellArrayRef(iface, lsb)
@@ -2811,8 +2812,8 @@ private:
         } else if (m_ds.m_dotp && m_ds.m_dotPos == DP_MEMBER) {
             // Found a Var, everything following is method call.
             // {scope}.{var}.HERE {method} ( ARGS )
-            AstNode* const varEtcp = m_ds.m_dotp->lhsp()->unlinkFrBack();
-            AstNode* argsp = nullptr;
+            AstNodeExpr* const varEtcp = m_ds.m_dotp->lhsp()->unlinkFrBack();
+            AstNodeExpr* argsp = nullptr;
             if (nodep->pinsp()) argsp = nodep->pinsp()->unlinkFrBackWithNext();
             AstNode* const newp = new AstMethodCall(nodep->fileline(), varEtcp, VFlagChildDType(),
                                                     nodep->name(), argsp);
@@ -2965,7 +2966,7 @@ private:
             }
         }
         if (m_ds.m_unresolved && m_ds.m_dotPos == DP_SCOPE) {
-            AstNode* const exprp = nodep->bitp()->unlinkFrBack();
+            AstNodeExpr* const exprp = nodep->bitp()->unlinkFrBack();
             AstCellArrayRef* const newp
                 = new AstCellArrayRef(nodep->fileline(), nodep->fromp()->name(), exprp);
             nodep->replaceWith(newp);
diff --git a/src/V3LinkInc.cpp b/src/V3LinkInc.cpp
index d4b486e67..d6b152881 100644
--- a/src/V3LinkInc.cpp
+++ b/src/V3LinkInc.cpp
@@ -205,8 +205,8 @@ private:
         UASSERT_OBJ(nodep, constp, "Expecting CONST");
         AstConst* const newconstp = constp->cloneTree(true);
 
-        AstNode* const storetop = nodep->thsp();
-        AstNode* const valuep = nodep->rhsp();
+        AstNodeExpr* const storetop = nodep->thsp();
+        AstNodeExpr* const valuep = nodep->rhsp();
 
         storetop->unlinkFrBack();
         valuep->unlinkFrBack();
@@ -247,7 +247,7 @@ private:
         insertBeforeStmt(nodep, varp);
 
         // Define what operation will we be doing
-        AstNode* operp;
+        AstNodeExpr* operp;
         if (VN_IS(nodep, PostSub) || VN_IS(nodep, PreSub)) {
             operp = new AstSub(fl, new AstVarRef(fl, varrefp->varp(), VAccess::READ), newconstp);
         } else {
diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp
index ae38c8fd5..173b90e92 100644
--- a/src/V3LinkJump.cpp
+++ b/src/V3LinkJump.cpp
@@ -159,7 +159,7 @@ private:
         // So later optimizations don't need to deal with them,
         //    REPEAT(count,body) -> loop=count,WHILE(loop>0) { body, loop-- }
         // Note var can be signed or unsigned based on original number.
-        AstNode* const countp = nodep->countp()->unlinkFrBackWithNext();
+        AstNodeExpr* const countp = nodep->countp()->unlinkFrBackWithNext();
         const string name = string("__Vrepeat") + cvtToStr(m_modRepeatNum++);
         // Spec says value is integral, if negative is ignored
         AstVar* const varp
@@ -172,8 +172,8 @@ private:
             nodep->fileline(), new AstVarRef(nodep->fileline(), varp, VAccess::WRITE),
             new AstSub(nodep->fileline(), new AstVarRef(nodep->fileline(), varp, VAccess::READ),
                        new AstConst(nodep->fileline(), 1)));
-        AstNode* const zerosp = new AstConst(nodep->fileline(), AstConst::Signed32(), 0);
-        AstNode* const condp = new AstGtS(
+        AstNodeExpr* const zerosp = new AstConst(nodep->fileline(), AstConst::Signed32(), 0);
+        AstNodeExpr* const condp = new AstGtS(
             nodep->fileline(), new AstVarRef(nodep->fileline(), varp, VAccess::READ), zerosp);
         AstNode* const bodysp = nodep->stmtsp();
         if (bodysp) bodysp->unlinkFrBackWithNext();
@@ -210,7 +210,7 @@ private:
             m_loopInc = true;
             iterateAndNextNull(nodep->incsp());
         }
-        AstNode* const condp = nodep->condp() ? nodep->condp()->unlinkFrBack() : nullptr;
+        AstNodeExpr* const condp = nodep->condp() ? nodep->condp()->unlinkFrBack() : nullptr;
         AstNode* const bodyp = nodep->stmtsp() ? nodep->stmtsp()->unlinkFrBack() : nullptr;
         AstNode* const incsp = nodep->incsp() ? nodep->incsp()->unlinkFrBack() : nullptr;
         AstWhile* const whilep = new AstWhile{nodep->fileline(), condp, bodyp, incsp};
diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index 4c8411869..ce569c707 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -181,7 +181,7 @@ private:
             FileLine* const flp = nodep->fileline();
             for (int i = left; i != (right + increment); i += increment, offset_from_init++) {
                 const string name = nodep->name() + cvtToStr(i);
-                AstNode* valuep = nullptr;
+                AstNodeExpr* valuep = nullptr;
                 if (nodep->valuep()) {
                     valuep
                         = new AstAdd(flp, nodep->valuep()->cloneTree(true),
@@ -266,7 +266,7 @@ private:
                 newfl->warnOff(V3ErrorCode::PROCASSWIRE, true);
                 auto* const assp
                     = new AstAssign(newfl, new AstVarRef(newfl, nodep->name(), VAccess::WRITE),
-                                    nodep->valuep()->unlinkFrBack());
+                                    VN_AS(nodep->valuep()->unlinkFrBack(), NodeExpr));
                 if (nodep->lifetime().isAutomatic()) {
                     nodep->addNextHere(new AstInitialAutomatic{newfl, assp});
                 } else {
@@ -274,9 +274,9 @@ private:
                 }
             }  // 4. Under blocks, it's an initial value to be under an assign
             else {
-                nodep->addNextHere(new AstAssign(fl,
-                                                 new AstVarRef(fl, nodep->name(), VAccess::WRITE),
-                                                 nodep->valuep()->unlinkFrBack()));
+                nodep->addNextHere(
+                    new AstAssign(fl, new AstVarRef(fl, nodep->name(), VAccess::WRITE),
+                                  VN_AS(nodep->valuep()->unlinkFrBack(), NodeExpr)));
             }
         }
         if (nodep->isIfaceRef() && !nodep->isIfaceParent() && !v3Global.opt.topIfacesSupported()) {
diff --git a/src/V3MergeCond.cpp b/src/V3MergeCond.cpp
index fea4cae5e..ebffc3150 100644
--- a/src/V3MergeCond.cpp
+++ b/src/V3MergeCond.cpp
@@ -136,7 +136,7 @@ bool areDisjoint(const std::set<const AstVar*>& a, const std::set<const AstVar*>
 // Structure containing information required for code motion/merging
 
 struct StmtProperties {
-    AstNode* m_condp = nullptr;  // The condition expression, if a conditional node
+    AstNodeExpr* m_condp = nullptr;  // The condition expression, if a conditional node
     std::set<const AstVar*> m_rdVars;  // Variables read by this statement
     std::set<const AstVar*> m_wrVars;  // Variables writen by this statement
     bool m_isFence = false;  // Nothing should move across this statement, nor should it be merged
@@ -178,8 +178,8 @@ class CodeMotionAnalysisVisitor final : public VNVisitor {
     StmtProperties* m_propsp = nullptr;  // StmtProperties structure of current AstNodeStmt
 
     // Extract condition expression from a megeable conditional statement, if any
-    static AstNode* extractCondition(const AstNodeStmt* nodep) {
-        AstNode* conditionp = nullptr;
+    static AstNodeExpr* extractCondition(const AstNodeStmt* nodep) {
+        AstNodeExpr* conditionp = nullptr;
         if (const AstNodeAssign* const assignp = VN_CAST(nodep, NodeAssign)) {
             if (AstNodeCond* const conditionalp = extractCondFromRhs(assignp->rhsp())) {
                 conditionp = conditionalp->condp();
@@ -199,7 +199,7 @@ class CodeMotionAnalysisVisitor final : public VNVisitor {
         m_propsp = &m_stmtProperties(nodep);
 
         // Extract condition from statement
-        if (AstNode* const condp = extractCondition(nodep)) {
+        if (AstNodeExpr* const condp = extractCondition(nodep)) {
             // Remember condition node. We always need this as it is used in the later
             // traversal.
             m_propsp->m_condp = condp;
@@ -447,7 +447,7 @@ private:
     VDouble0 m_statLongestList;  // Statistic tracking
 
     AstNode* m_mgFirstp = nullptr;  // First node in merged sequence
-    AstNode* m_mgCondp = nullptr;  // The condition of the first node
+    AstNodeExpr* m_mgCondp = nullptr;  // The condition of the first node
     const AstNode* m_mgLastp = nullptr;  // Last node in merged sequence
     const AstNode* m_mgNextp = nullptr;  // Next node in list being examined
     uint32_t m_listLenght = 0;  // Length of current list
@@ -578,10 +578,10 @@ private:
     // Apply (1'b1 & _) cleaning mask if necessary. This is required because this pass is after
     // V3Clean, and sometimes we have an AstAnd with a 1-bit condition on one side, but a more
     // than 1-bit value on the other side, so we need to keep only the LSB.
-    static AstNode* maskLsb(AstNode* nodep) {
+    static AstNodeExpr* maskLsb(AstNodeExpr* nodep) {
         if (yieldsOneOrZero(nodep)) return nodep;
         // Otherwise apply masking
-        AstNode* const maskp = new AstConst{nodep->fileline(), AstConst::BitTrue()};
+        AstConst* const maskp = new AstConst{nodep->fileline(), AstConst::BitTrue()};
         // Mask on left, as conventional
         return new AstAnd{nodep->fileline(), maskp, nodep};
     }
@@ -589,11 +589,11 @@ private:
     // Fold the RHS expression of an assignment assuming the given condition state.
     // Unlink bits from the RHS which is only used once, and can be reused (is an unomdified
     // sub-tree). What remains of the RHS is expected to be deleted by the caller.
-    AstNode* foldAndUnlink(AstNode* rhsp, bool condTrue) {
+    AstNodeExpr* foldAndUnlink(AstNodeExpr* rhsp, bool condTrue) {
         if (rhsp->sameTree(m_mgCondp)) {
             return new AstConst{rhsp->fileline(), AstConst::BitTrue{}, condTrue};
         } else if (const AstNodeCond* const condp = extractCondFromRhs(rhsp)) {
-            AstNode* const resp
+            AstNodeExpr* const resp
                 = condTrue ? condp->thenp()->unlinkFrBack() : condp->elsep()->unlinkFrBack();
             if (condp == rhsp) return resp;
             if (const AstAnd* const andp = VN_CAST(rhsp, And)) {
@@ -671,7 +671,7 @@ private:
                 ++m_statMergedItems;
                 if (AstNodeAssign* const assignp = VN_CAST(currp, NodeAssign)) {
                     // Unlink RHS and clone to get the 2 assignments (reusing assignp)
-                    AstNode* const rhsp = assignp->rhsp()->unlinkFrBack();
+                    AstNodeExpr* const rhsp = assignp->rhsp()->unlinkFrBack();
                     AstNodeAssign* const thenp = assignp;
                     AstNodeAssign* const elsep = assignp->cloneTree(false);
                     // Construct the new RHSs and add to branches
@@ -739,7 +739,7 @@ private:
         return false;
     }
 
-    bool addToList(AstNodeStmt* nodep, AstNode* condp) {
+    bool addToList(AstNodeStmt* nodep, AstNodeExpr* condp) {
         // Set up head of new list if node is first in list
         if (!m_mgFirstp) {
             UASSERT_OBJ(condp, nodep, "Cannot start new list without condition");
@@ -825,7 +825,7 @@ private:
 
     // VISITORS
     void visit(AstNodeAssign* nodep) override {
-        if (AstNode* const condp = (*m_stmtPropertiesp)(nodep).m_condp) {
+        if (AstNodeExpr* const condp = (*m_stmtPropertiesp)(nodep).m_condp) {
             // Check if mergeable
             if (!checkOrMakeMergeable(nodep)) return;
             // Close potentially incompatible pending merge
diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp
index 2c1c31e47..2d2b5d977 100644
--- a/src/V3ParseGrammar.cpp
+++ b/src/V3ParseGrammar.cpp
@@ -69,14 +69,14 @@ void V3ParseImp::parserClear() {
 //======================================================================
 // V3ParseGrammar functions requiring bison state
 
-AstArg* V3ParseGrammar::argWrapList(AstNode* nodep) {
+AstArg* V3ParseGrammar::argWrapList(AstNodeExpr* nodep) {
     // Convert list of expressions to list of arguments
     if (!nodep) return nullptr;
     AstArg* outp = nullptr;
     AstBegin* const tempp = new AstBegin{nodep->fileline(), "[EditWrapper]", nodep};
     while (nodep) {
-        AstNode* const nextp = nodep->nextp();
-        AstNode* const exprp = nodep->unlinkFrBack();
+        AstNodeExpr* const nextp = VN_AS(nodep->nextp(), NodeExpr);
+        AstNodeExpr* const exprp = nodep->unlinkFrBack();
         nodep = nextp;
         outp = AstNode::addNext(outp, new AstArg{exprp->fileline(), "", exprp});
     }
diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp
index d38eff5e3..4c0883036 100644
--- a/src/V3Premit.cpp
+++ b/src/V3Premit.cpp
@@ -69,7 +69,7 @@ private:
         return (VN_IS(nodep->lhsp(), VarRef) && !AstVar::scVarRecurse(nodep->lhsp())
                 && VN_IS(nodep->rhsp(), Const));
     }
-    void checkNode(AstNode* nodep) {
+    void checkNode(AstNodeExpr* nodep) {
         // Consider adding a temp for this expression.
         // We need to avoid adding temps to the following:
         //   ASSIGN(x, *here*)
@@ -116,7 +116,7 @@ private:
         }
     }
 
-    void createDeepTemp(AstNode* nodep, bool noSubst) {
+    void createDeepTemp(AstNodeExpr* nodep, bool noSubst) {
         if (nodep->user1SetOnce()) return;  // Only add another assignment for this node
 
         VNRelinker relinker;
@@ -236,7 +236,7 @@ private:
                 && nodep->width() < (1LL << nodep->rhsp()->widthMin())) {
                 VNRelinker replaceHandle;
                 nodep->unlinkFrBack(&replaceHandle);
-                AstNode* constzerop;
+                AstNodeExpr* constzerop;
                 const int m1value
                     = nodep->widthMin() - 1;  // Constant of width-1; not changing dtype width
                 if (nodep->signedFlavor()) {
@@ -253,7 +253,7 @@ private:
                 }
                 constzerop->dtypeFrom(nodep);  // unsigned
 
-                AstNode* const constwidthp
+                AstNodeExpr* const constwidthp
                     = new AstConst(nodep->fileline(), AstConst::WidthedValue(),
                                    nodep->rhsp()->widthMin(), m1value);
                 constwidthp->dtypeFrom(nodep->rhsp());  // unsigned
@@ -352,8 +352,9 @@ private:
                 // There's another display next; we can just wait to flush
             } else {
                 UINFO(4, "Autoflush " << nodep << endl);
-                nodep->addNextHere(new AstFFlush(nodep->fileline(),
-                                                 AstNode::cloneTreeNull(nodep->filep(), true)));
+                nodep->addNextHere(
+                    new AstFFlush{nodep->fileline(),
+                                  VN_AS(AstNode::cloneTreeNull(nodep->filep(), true), NodeExpr)});
             }
         }
     }
@@ -361,7 +362,7 @@ private:
         iterateChildren(nodep);
         // Any strings sent to a display must be var of string data type,
         // to avoid passing a pointer to a temporary.
-        for (AstNode* expp = nodep->exprsp(); expp; expp = expp->nextp()) {
+        for (AstNodeExpr* expp = nodep->exprsp(); expp; expp = VN_AS(expp->nextp(), NodeExpr)) {
             if (expp->dtypep()->basicp() && expp->dtypep()->basicp()->isString()
                 && !VN_IS(expp, VarRef)) {
                 createDeepTemp(expp, true);
diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index 99ade5062..a7e1bcc77 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -184,7 +184,7 @@ private:
                     = new AstVarRef{fl, enumValueTabp(enumDtp), VAccess::READ};
                 tabRefp->classOrPackagep(v3Global.rootp()->dollarUnitPkgAddp());
                 AstRand* const randp = new AstRand{fl, nullptr, false};
-                AstNode* const moddivp = new AstModDiv{
+                AstNodeExpr* const moddivp = new AstModDiv{
                     fl, randp, new AstConst{fl, static_cast<uint32_t>(enumDtp->itemCount())}};
                 randp->dtypep(varrefp->findBasicDType(VBasicDTypeKwd::UINT32));
                 moddivp->dtypep(enumDtp);
@@ -296,7 +296,7 @@ private:
 
         for (AstCaseItem* itemp = nodep->itemsp(); itemp;
              itemp = VN_AS(itemp->nextp(), CaseItem)) {
-            AstNode* const condp = itemp->condsp()->unlinkFrBack();
+            AstNodeExpr* const condp = itemp->condsp()->unlinkFrBack();
             sump
                 = new AstAdd{condp->fileline(), sump, new AstExtend{itemp->fileline(), condp, 64}};
             AstNode* const stmtsp
@@ -318,7 +318,7 @@ private:
         ifsp->addElsesp(dispp);
 
         AstNode* newp = randVarp;
-        AstNode* randp = new AstRand{fl, nullptr, false};
+        AstNodeExpr* randp = new AstRand{fl, nullptr, false};
         randp->dtypeSetUInt64();
         newp->addNext(new AstAssign{fl, new AstVarRef{fl, randVarp, VAccess::WRITE},
                                     new AstAdd{fl, new AstConst{fl, AstConst::Unsized64{}, 1},
diff --git a/src/V3Reloop.cpp b/src/V3Reloop.cpp
index 00d3bfc68..80d9d38ce 100644
--- a/src/V3Reloop.cpp
+++ b/src/V3Reloop.cpp
@@ -107,8 +107,8 @@ private:
 
                 AstNode* const initp = new AstAssign(fl, new AstVarRef(fl, itp, VAccess::WRITE),
                                                      new AstConst(fl, m_mgIndexLo));
-                AstNode* const condp = new AstLte(fl, new AstVarRef(fl, itp, VAccess::READ),
-                                                  new AstConst(fl, m_mgIndexHi));
+                AstNodeExpr* const condp = new AstLte(fl, new AstVarRef(fl, itp, VAccess::READ),
+                                                      new AstConst(fl, m_mgIndexHi));
                 AstNode* const incp = new AstAssign(
                     fl, new AstVarRef(fl, itp, VAccess::WRITE),
                     new AstAdd(fl, new AstConst(fl, 1), new AstVarRef(fl, itp, VAccess::READ)));
@@ -118,15 +118,15 @@ private:
                 whilep->addStmtsp(bodyp);
 
                 // Replace constant index with new loop index
-                AstNode* const offsetp
+                AstNodeExpr* const offsetp
                     = m_mgOffset == 0 ? nullptr : new AstConst(fl, std::abs(m_mgOffset));
-                AstNode* const lbitp = m_mgSelLp->bitp();
-                AstNode* const lvrefp = new AstVarRef(fl, itp, VAccess::READ);
+                AstNodeExpr* const lbitp = m_mgSelLp->bitp();
+                AstNodeExpr* const lvrefp = new AstVarRef(fl, itp, VAccess::READ);
                 lbitp->replaceWith(m_mgOffset > 0 ? new AstAdd(fl, lvrefp, offsetp) : lvrefp);
                 VL_DO_DANGLING(lbitp->deleteTree(), lbitp);
                 if (m_mgSelRp) {  // else constant and no replace
-                    AstNode* const rbitp = m_mgSelRp->bitp();
-                    AstNode* const rvrefp = new AstVarRef(fl, itp, VAccess::READ);
+                    AstNodeExpr* const rbitp = m_mgSelRp->bitp();
+                    AstNodeExpr* const rvrefp = new AstVarRef(fl, itp, VAccess::READ);
                     rbitp->replaceWith(m_mgOffset < 0 ? new AstAdd(fl, rvrefp, offsetp) : rvrefp);
                     VL_DO_DANGLING(rbitp->deleteTree(), lbitp);
                 }
diff --git a/src/V3SenExprBuilder.h b/src/V3SenExprBuilder.h
index 81e189d83..2634bbeec 100644
--- a/src/V3SenExprBuilder.h
+++ b/src/V3SenExprBuilder.h
@@ -64,7 +64,7 @@ class SenExprBuilder final {
     }
 
     // METHODS
-    AstNode* getCurr(AstNode* exprp) {
+    AstNodeExpr* getCurr(AstNodeExpr* exprp) {
         // For simple expressions like varrefs or selects, just use them directly
         if (isSimpleExpr(exprp)) return exprp->cloneTree(false);
 
@@ -89,7 +89,7 @@ class SenExprBuilder final {
         }
         return new AstVarRef{flp, currp, VAccess::READ};
     }
-    AstVarScope* getPrev(AstNode* exprp) {
+    AstVarScope* getPrev(AstNodeExpr* exprp) {
         FileLine* const flp = exprp->fileline();
         const auto rdCurr = [=]() { return getCurr(exprp); };
 
@@ -150,9 +150,9 @@ class SenExprBuilder final {
         return prevp;
     }
 
-    std::pair<AstNode*, bool> createTerm(AstSenItem* senItemp) {
+    std::pair<AstNodeExpr*, bool> createTerm(AstSenItem* senItemp) {
         FileLine* const flp = senItemp->fileline();
-        AstNode* const senp = senItemp->sensp();
+        AstNodeExpr* const senp = senItemp->sensp();
 
         const auto currp = [=]() { return getCurr(senp); };
         const auto prevp = [=]() { return new AstVarRef{flp, getPrev(senp), VAccess::READ}; };
@@ -215,14 +215,14 @@ class SenExprBuilder final {
 public:
     // Returns the expression computing the trigger, and a bool indicating that
     // this trigger should be fired on the first evaluation (at initialization)
-    std::pair<AstNode*, bool> build(const AstSenTree* senTreep) {
+    std::pair<AstNodeExpr*, bool> build(const AstSenTree* senTreep) {
         FileLine* const flp = senTreep->fileline();
-        AstNode* resultp = nullptr;
+        AstNodeExpr* resultp = nullptr;
         bool firedAtInitialization = false;
         for (AstSenItem* senItemp = senTreep->sensesp(); senItemp;
              senItemp = VN_AS(senItemp->nextp(), SenItem)) {
             const auto& pair = createTerm(senItemp);
-            if (AstNode* const termp = pair.first) {
+            if (AstNodeExpr* const termp = pair.first) {
                 resultp = resultp ? new AstOr{flp, resultp, termp} : termp;
                 firedAtInitialization |= pair.second;
             }
diff --git a/src/V3Simulate.h b/src/V3Simulate.h
index 788d5e696..a60b5b35a 100644
--- a/src/V3Simulate.h
+++ b/src/V3Simulate.h
@@ -191,7 +191,7 @@ public:
                 for (V3TaskConnects::iterator conIt = tconnects->begin();
                      conIt != tconnects->end(); ++conIt) {
                     AstVar* const portp = conIt->first;
-                    AstNode* const pinp = conIt->second->exprp();
+                    AstNodeExpr* const pinp = conIt->second->exprp();
                     AstNodeDType* const dtypep = pinp->dtypep();
                     if (AstConst* const valp = fetchConstNull(pinp)) {
                         stack << "\n           " << portp->prettyName() << " = "
@@ -248,26 +248,26 @@ private:
     }
 
 public:
-    void newValue(AstNode* nodep, const AstNode* valuep) {
+    void newValue(AstNode* nodep, const AstNodeExpr* valuep) {
         if (const AstConst* const constp = VN_CAST(valuep, Const)) {
             newConst(nodep)->num().opAssign(constp->num());
         } else if (fetchValueNull(nodep) != valuep) {
             // const_cast, as clonep() is set on valuep, but nothing should care
-            setValue(nodep, newTrackedClone(const_cast<AstNode*>(valuep)));
+            setValue(nodep, newTrackedClone(const_cast<AstNodeExpr*>(valuep)));
         }
     }
-    void newOutValue(AstNode* nodep, const AstNode* valuep) {
+    void newOutValue(AstNode* nodep, const AstNodeExpr* valuep) {
         if (const AstConst* const constp = VN_CAST(valuep, Const)) {
             newOutConst(nodep)->num().opAssign(constp->num());
         } else if (fetchOutValueNull(nodep) != valuep) {
             // const_cast, as clonep() is set on valuep, but nothing should care
-            setOutValue(nodep, newTrackedClone(const_cast<AstNode*>(valuep)));
+            setOutValue(nodep, newTrackedClone(const_cast<AstNodeExpr*>(valuep)));
         }
     }
 
 private:
-    AstNode* newTrackedClone(AstNode* nodep) {
-        AstNode* const newp = nodep->cloneTree(false);
+    AstNodeExpr* newTrackedClone(AstNodeExpr* nodep) {
+        AstNodeExpr* const newp = nodep->cloneTree(false);
         m_reclaimValuesp.push_back(newp);
         return newp;
     }
@@ -293,16 +293,16 @@ private:
     }
 
 public:
-    AstNode* fetchValueNull(AstNode* nodep) { return nodep->user3p(); }
+    AstNodeExpr* fetchValueNull(AstNode* nodep) { return VN_AS(nodep->user3p(), NodeExpr); }
 
 private:
-    AstNode* fetchOutValueNull(AstNode* nodep) { return nodep->user2p(); }
+    AstNodeExpr* fetchOutValueNull(AstNode* nodep) { return VN_AS(nodep->user2p(), NodeExpr); }
     AstConst* fetchConstNull(AstNode* nodep) { return VN_CAST(fetchValueNull(nodep), Const); }
     AstConst* fetchOutConstNull(AstNode* nodep) {
         return VN_CAST(fetchOutValueNull(nodep), Const);
     }
-    AstNode* fetchValue(AstNode* nodep) {
-        AstNode* const valuep = fetchValueNull(nodep);
+    AstNodeExpr* fetchValue(AstNode* nodep) {
+        AstNodeExpr* const valuep = fetchValueNull(nodep);
         UASSERT_OBJ(valuep, nodep, "No value found for node.");
         // UINFO(9, "     fetch val " << *valuep << " on " << nodep << endl);
         return valuep;
@@ -332,12 +332,12 @@ public:
     }
 
 private:
-    void setValue(AstNode* nodep, const AstNode* valuep) {
+    void setValue(AstNode* nodep, const AstNodeExpr* valuep) {
         UASSERT_OBJ(valuep, nodep, "Simulate setting null value");
         UINFO(9, "     set val " << valuep->name() << " on " << nodep << endl);
         nodep->user3p((void*)valuep);
     }
-    void setOutValue(AstNode* nodep, const AstNode* valuep) {
+    void setOutValue(AstNode* nodep, const AstNodeExpr* valuep) {
         UASSERT_OBJ(valuep, nodep, "Simulate setting null value");
         UINFO(9, "     set oval " << valuep->name() << " on " << nodep << endl);
         nodep->user2p((void*)valuep);
@@ -386,7 +386,7 @@ private:
         // True to jump over this node - all visitors must call this up front
         return (m_jumpp && m_jumpp->labelp() != nodep);
     }
-    void assignOutValue(AstNodeAssign* nodep, AstNode* vscp, const AstNode* valuep) {
+    void assignOutValue(AstNodeAssign* nodep, AstNode* vscp, const AstNodeExpr* valuep) {
         if (VN_IS(nodep, AssignDly)) {
             // Don't do setValue, as value isn't yet visible to following statements
             newOutValue(vscp, valuep);
@@ -443,10 +443,10 @@ private:
                 }
                 vscp->user1(vscp->user1() | VU_RV);
                 const bool isConst = nodep->varp()->isParam() && nodep->varp()->valuep();
-                AstNode* const valuep
+                AstNodeExpr* const valuep
                     = isConst ? fetchValueNull(nodep->varp()->valuep()) : nullptr;
-                if (isConst
-                    && valuep) {  // Propagate PARAM constants for constant function analysis
+                // Propagate PARAM constants for constant function analysis
+                if (isConst && valuep) {
                     if (!m_checkOnly && optimizable()) newValue(vscp, valuep);
                 } else {
                     if (m_checkOnly) varRefCb(nodep);
@@ -458,7 +458,7 @@ private:
                         "LHS varref should be handled in AstAssign visitor.");
             {
                 // Return simulation value - copy by reference instead of value for speed
-                AstNode* valuep = fetchValueNull(vscp);
+                AstNodeExpr* valuep = fetchValueNull(vscp);
                 if (!valuep) {
                     if (m_params) {
                         clearOptimizable(
@@ -697,7 +697,7 @@ private:
                 m_reclaimValuesp.push_back(initp);
             }
             const uint32_t index = fetchConst(selp->bitp())->toUInt();
-            AstNode* const valuep = newTrackedClone(fetchValue(nodep->rhsp()));
+            AstNodeExpr* const valuep = newTrackedClone(fetchValue(nodep->rhsp()));
             UINFO(9, "     set val[" << index << "] = " << valuep << endl);
             // Values are in the "real" tree under the InitArray so can eventually extract it,
             // Not in the usual setValue (pointed to by user2/3p)
@@ -803,7 +803,7 @@ private:
         if (AstInitArray* const initp = VN_CAST(fetchValueNull(nodep->fromp()), InitArray)) {
             AstConst* const indexp = fetchConst(nodep->bitp());
             const uint32_t offset = indexp->num().toUInt();
-            AstNode* const itemp = initp->getIndexDefaultedValuep(offset);
+            AstNodeExpr* const itemp = initp->getIndexDefaultedValuep(offset);
             if (!itemp) {
                 clearOptimizable(nodep, "Array initialization has too few elements, need element "
                                             + cvtToStr(offset));
diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp
index 6cab91c4f..0c027e5fe 100644
--- a/src/V3Slice.cpp
+++ b/src/V3Slice.cpp
@@ -60,7 +60,7 @@ class SliceVisitor final : public VNVisitor {
     bool m_assignError = false;  // True if the current assign already has an error
 
     // METHODS
-    AstNode* cloneAndSel(AstNode* nodep, int elements, int offset) {
+    AstNodeExpr* cloneAndSel(AstNode* nodep, int elements, int offset) {
         // Insert an ArraySel, except for a few special cases
         const AstUnpackArrayDType* const arrayp
             = VN_CAST(nodep->dtypep()->skipRefp(), UnpackArrayDType);
@@ -73,7 +73,8 @@ class SliceVisitor final : public VNVisitor {
                 V3Error::incErrors();  // Otherwise might infinite loop
             }
             m_assignError = true;
-            return nodep->cloneTree(false);  // Likely will cause downstream errors
+            // Likely will cause downstream errors
+            return VN_AS(nodep, NodeExpr)->cloneTree(false);
         }
         if (arrayp->rangep()->elementsConst() != elements) {
             if (!m_assignError) {
@@ -85,19 +86,18 @@ class SliceVisitor final : public VNVisitor {
             elements = 1;
             offset = 0;
         }
-        AstNode* newp;
+        AstNodeExpr* newp;
         if (const AstInitArray* const initp = VN_CAST(nodep, InitArray)) {
             UINFO(9, "  cloneInitArray(" << elements << "," << offset << ") " << nodep << endl);
             const int leOffset = !arrayp->rangep()->littleEndian()
                                      ? arrayp->rangep()->elementsConst() - 1 - offset
                                      : offset;
-            AstNode* itemp = initp->getIndexDefaultedValuep(leOffset);
+            AstNodeExpr* const itemp = initp->getIndexDefaultedValuep(leOffset);
             if (!itemp) {
                 nodep->v3error("Array initialization has too few elements, need element "
                                << offset);
-                itemp = initp->initsp();
             }
-            newp = itemp->cloneTree(false);
+            newp = itemp ? itemp->cloneTree(false) : new AstConst{nodep->fileline(), 0};
         } else if (AstNodeCond* const snodep = VN_CAST(nodep, NodeCond)) {
             UINFO(9, "  cloneCond(" << elements << "," << offset << ") " << nodep << endl);
             return snodep->cloneType(snodep->condp()->cloneTree(false),
@@ -116,14 +116,16 @@ class SliceVisitor final : public VNVisitor {
             const int leOffset = !arrayp->rangep()->littleEndian()
                                      ? arrayp->rangep()->elementsConst() - 1 - offset
                                      : offset;
-            newp = new AstArraySel{nodep->fileline(), nodep->cloneTree(false), leOffset};
+            newp = new AstArraySel{nodep->fileline(), VN_AS(nodep, NodeExpr)->cloneTree(false),
+                                   leOffset};
         } else {
             if (!m_assignError) {
                 nodep->v3error(nodep->prettyTypeName()
                                << " unexpected in assignment to unpacked array");
             }
             m_assignError = true;
-            newp = nodep->cloneTree(false);  // Likely will cause downstream errors
+            // Likely will cause downstream errors
+            newp = VN_AS(nodep, NodeExpr)->cloneTree(false);
         }
         return newp;
     }
@@ -143,9 +145,8 @@ class SliceVisitor final : public VNVisitor {
                 const int elements = arrayp->rangep()->elementsConst();
                 for (int offset = 0; offset < elements; ++offset) {
                     AstNodeAssign* const newp
-                        = VN_AS(nodep->cloneType(cloneAndSel(nodep->lhsp(), elements, offset),
-                                                 cloneAndSel(nodep->rhsp(), elements, offset)),
-                                NodeAssign);
+                        = nodep->cloneType(cloneAndSel(nodep->lhsp(), elements, offset),
+                                           cloneAndSel(nodep->rhsp(), elements, offset));
                     if (debug() >= 9) newp->dumpTree(cout, "-new ");
                     newlistp = AstNode::addNext(newlistp, newp);
                 }
diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp
index 1b90d3384..f2eca4fac 100644
--- a/src/V3SplitVar.cpp
+++ b/src/V3SplitVar.cpp
@@ -132,7 +132,7 @@ struct SplitVarImpl {
     //  AstNodeModule::user1()  -> Block number counter for generating unique names
     const VNUser1InUse m_user1InUse;  // Only used in SplitUnpackedVarVisitor
 
-    static AstNodeAssign* newAssign(FileLine* fileline, AstNode* lhsp, AstNode* rhsp,
+    static AstNodeAssign* newAssign(FileLine* fileline, AstNodeExpr* lhsp, AstNodeExpr* rhsp,
                                     const AstVar* varp) {
         if (varp->isFuncLocal() || varp->isFuncReturn()) {
             return new AstAssign{fileline, lhsp, rhsp};
@@ -621,9 +621,9 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
             = (context && VN_IS(context, NodeFTaskRef)) || (assignp && VN_IS(assignp, Assign));
 
         for (int i = 0; i < dtypep->elementsConst(); ++i) {
-            AstNode* lhsp
+            AstNodeExpr* lhsp
                 = newVarRef(fl, vars.at(start_idx + i), lvalue ? VAccess::WRITE : VAccess::READ);
-            AstNode* rhsp = new AstArraySel{
+            AstNodeExpr* rhsp = new AstArraySel{
                 fl, newVarRef(fl, varp, !lvalue ? VAccess::WRITE : VAccess::READ), i};
             AstNode* const refp = lhsp;
             UINFO(9, "Creating assign idx:" << i << " + " << start_idx << "\n");
@@ -655,12 +655,12 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
         const bool lvalue = varp->direction().isWritable();
         FileLine* const fl = varp->fileline();
         for (size_t i = 0; i < vars.size(); ++i) {
-            AstNode* const nodes[] = {
+            AstNodeExpr* const nodes[] = {
                 new AstArraySel{fl, newVarRef(fl, varp, lvalue ? VAccess::WRITE : VAccess::READ),
                                 static_cast<int>(i)},
                 newVarRef(fl, vars.at(i), !lvalue ? VAccess::WRITE : VAccess::READ)};
-            AstNode* const lhsp = nodes[lvalue ? 0 : 1];
-            AstNode* const rhsp = nodes[lvalue ? 1 : 0];
+            AstNodeExpr* const lhsp = nodes[lvalue ? 0 : 1];
+            AstNodeExpr* const rhsp = nodes[lvalue ? 1 : 0];
             AstNodeAssign* const assignp = newAssign(fl, lhsp, rhsp, varp);
             if (insertp) {
                 if (lvalue) {  // Just after writing to the temporary variable
@@ -1025,8 +1025,8 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
     // Extract necessary bit range from a newly created variable to meet ref
-    static AstNode* extractBits(const PackedVarRefEntry& ref, const SplitNewVar& var,
-                                const VAccess access) {
+    static AstNodeExpr* extractBits(const PackedVarRefEntry& ref, const SplitNewVar& var,
+                                    const VAccess access) {
         FileLine* const fl = ref.nodep()->fileline();
         AstVarRef* const refp = new AstVarRef{fl, var.varp(), access};
         if (ref.lsb() <= var.lsb() && var.msb() <= ref.msb()) {  // Use the entire bits
@@ -1049,10 +1049,10 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
         const bool in = portp->isReadOnly();
         FileLine* const fl = portp->fileline();
         for (const SplitNewVar& var : vars) {
-            AstNode* rhsp
+            AstNodeExpr* rhsp
                 = new AstSel{fl, new AstVarRef{fl, portp, !in ? VAccess::WRITE : VAccess::READ},
                              var.lsb(), var.bitwidth()};
-            AstNode* lhsp = new AstVarRef{fl, var.varp(), in ? VAccess::WRITE : VAccess::READ};
+            AstNodeExpr* lhsp = new AstVarRef{fl, var.varp(), in ? VAccess::WRITE : VAccess::READ};
             if (!in) std::swap(lhsp, rhsp);
             AstNodeAssign* const assignp = newAssign(fl, lhsp, rhsp, portp);
             if (insertp) {
@@ -1134,9 +1134,10 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
                             new AstVarRef{senitemp->fileline(), varit->varp(), VAccess::READ}};
                         senitemp->addNextHere(prevp);
                     } else {
-                        AstNode* const bitsp
+                        AstNodeExpr* const bitsp
                             = extractBits(ref, *varit, lvalue ? VAccess::WRITE : VAccess::READ);
-                        prevp = new AstConcat{ref.nodep()->fileline(), bitsp, prevp};
+                        prevp = new AstConcat{ref.nodep()->fileline(), bitsp,
+                                              VN_AS(prevp, NodeExpr)};
                     }
                 }
                 // If varp is an argument of task/func, need to update temporary var
@@ -1174,8 +1175,8 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
                     connectPortAndVar(vars, varp, nullptr);
             } else if (varp->isTrace()) {
                 // Let's reuse the original variable for tracing
-                AstNode* rhsp = new AstVarRef{vars.front().varp()->fileline(), vars.front().varp(),
-                                              VAccess::READ};
+                AstNodeExpr* rhsp = new AstVarRef{vars.front().varp()->fileline(),
+                                                  vars.front().varp(), VAccess::READ};
                 FileLine* const fl = varp->fileline();
                 for (size_t i = 1; i < vars.size(); ++i) {
                     rhsp = new AstConcat{fl, new AstVarRef{fl, vars[i].varp(), VAccess::READ},
diff --git a/src/V3Subst.cpp b/src/V3Subst.cpp
index 34fa8951e..04535e9a2 100644
--- a/src/V3Subst.cpp
+++ b/src/V3Subst.cpp
@@ -119,7 +119,7 @@ public:
         m_wordUse = true;
     }
     // ACCESSORS
-    AstNode* substWhole(AstNode* errp) {
+    AstNodeExpr* substWhole(AstNode* errp) {
         if (!m_varp->isWide() && !m_whole.m_complex && m_whole.m_assignp && !m_wordAssign) {
             const AstNodeAssign* const assp = m_whole.m_assignp;
             UASSERT_OBJ(assp, errp, "Reading whole that was never assigned");
@@ -129,7 +129,7 @@ public:
         }
     }
     // Return what to substitute given word number for
-    AstNode* substWord(AstNode* errp, int word) {
+    AstNodeExpr* substWord(AstNode* errp, int word) {
         if (!m_whole.m_complex && !m_whole.m_assignp && !m_words[word].m_complex) {
             const AstNodeAssign* const assp = getWordAssignp(word);
             UASSERT_OBJ(assp, errp, "Reading a word that was never assigned, or bad word #");
@@ -287,9 +287,9 @@ private:
         }
         if (!hit) iterate(nodep->lhsp());
     }
-    void replaceSubstEtc(AstNode* nodep, AstNode* substp) {
+    void replaceSubstEtc(AstNode* nodep, AstNodeExpr* substp) {
         if (debug() > 5) nodep->dumpTree(cout, "  substw_old: ");
-        AstNode* newp = substp->cloneTree(true);
+        AstNodeExpr* newp = substp->cloneTree(true);
         if (!nodep->isQuad() && newp->isQuad()) {
             newp = new AstCCast{newp->fileline(), newp, nodep};
         }
@@ -308,7 +308,7 @@ private:
             const int word = constp->toUInt();
             UINFO(8, " USEword" << word << " " << varrefp << endl);
             SubstVarEntry* const entryp = getEntryp(varrefp);
-            if (AstNode* const substp = entryp->substWord(nodep, word)) {
+            if (AstNodeExpr* const substp = entryp->substWord(nodep, word)) {
                 // Check that the RHS hasn't changed value since we recorded it.
                 const SubstUseVisitor visitor{substp, entryp->getWordStep(word)};
                 if (visitor.ok()) {
@@ -335,7 +335,7 @@ private:
             if (nodep->access().isWriteOrRW()) {
                 UINFO(8, " ASSIGNcpx " << nodep << endl);
                 entryp->assignComplex();
-            } else if (AstNode* const substp = entryp->substWhole(nodep)) {
+            } else if (AstNodeExpr* const substp = entryp->substWhole(nodep)) {
                 // Check that the RHS hasn't changed value since we recorded it.
                 const SubstUseVisitor visitor{substp, entryp->getWholeStep()};
                 if (visitor.ok()) {
diff --git a/src/V3Table.cpp b/src/V3Table.cpp
index 8ace9f4f3..0db7f1aba 100644
--- a/src/V3Table.cpp
+++ b/src/V3Table.cpp
@@ -336,7 +336,7 @@ private:
     AstNode* createLookupInput(FileLine* fl, AstVarScope* indexVscp) {
         // Concat inputs into a single temp variable (inside always)
         // First var in inVars becomes the LSB of the concat
-        AstNode* concatp = nullptr;
+        AstNodeExpr* concatp = nullptr;
         for (AstVarScope* invscp : m_inVarps) {
             AstVarRef* const refp = new AstVarRef{fl, invscp, VAccess::READ};
             if (concatp) {
@@ -359,8 +359,8 @@ private:
                              AstVarScope* outputAssignedTableVscp) {
         FileLine* const fl = nodep->fileline();
         for (TableOutputVar& tov : m_outVarps) {
-            AstNode* const alhsp = new AstVarRef{fl, tov.varScopep(), VAccess::WRITE};
-            AstNode* const arhsp = select(fl, tov.tabeVarScopep(), indexVscp);
+            AstNodeExpr* const alhsp = new AstVarRef{fl, tov.varScopep(), VAccess::WRITE};
+            AstNodeExpr* const arhsp = select(fl, tov.tabeVarScopep(), indexVscp);
             AstNode* outsetp = m_assignDly
                                    ? static_cast<AstNode*>(new AstAssignDly{fl, alhsp, arhsp})
                                    : static_cast<AstNode*>(new AstAssign{fl, alhsp, arhsp});
@@ -369,7 +369,7 @@ private:
             if (tov.mayBeUnassigned()) {
                 V3Number outputChgMask{nodep, static_cast<int>(m_outVarps.size()), 0};
                 outputChgMask.setBit(tov.ord(), 1);
-                AstNode* const condp
+                AstNodeExpr* const condp
                     = new AstAnd{fl, select(fl, outputAssignedTableVscp, indexVscp),
                                  new AstConst{fl, outputChgMask}};
                 outsetp = new AstIf{fl, condp, outsetp};
diff --git a/src/V3Task.cpp b/src/V3Task.cpp
index 59aaca246..3c30da6d7 100644
--- a/src/V3Task.cpp
+++ b/src/V3Task.cpp
@@ -435,7 +435,7 @@ private:
         for (const auto& itr : tconnects) {
             AstVar* const portp = itr.first;
             AstArg* const argp = itr.second;
-            AstNode* const pinp = argp->exprp();
+            AstNodeExpr* const pinp = argp->exprp();
             portp->unlinkFrBack();
             pushDeletep(portp);  // Remove it from the clone (not original)
             if (!pinp) {
@@ -564,7 +564,7 @@ private:
         const V3TaskConnects tconnects = V3Task::taskConnects(refp, refp->taskp()->stmtsp());
         for (const auto& itr : tconnects) {
             AstVar* const portp = itr.first;
-            AstNode* const pinp = itr.second->exprp();
+            AstNodeExpr* const pinp = itr.second->exprp();
             if (!pinp) {
                 // Too few arguments in function call
             } else {
@@ -615,7 +615,7 @@ private:
 
         if (refp->taskp()->dpiContext()) {
             // __Vscopep
-            AstNode* const snp = refp->scopeNamep()->unlinkFrBack();
+            AstScopeName* const snp = refp->scopeNamep()->unlinkFrBack();
             UASSERT_OBJ(snp, refp, "Missing scoping context");
             ccallp->addArgsp(snp);
             // __Vfilenamep
@@ -630,7 +630,7 @@ private:
         for (AstNode* pinp = refp->pinsp(); pinp; pinp = nextpinp) {
             nextpinp = pinp->nextp();
             // Move pin to the CCall, removing all Arg's
-            AstNode* const exprp = VN_AS(pinp, Arg)->exprp();
+            AstNodeExpr* const exprp = VN_AS(pinp, Arg)->exprp();
             exprp->unlinkFrBack();
             ccallp->addArgsp(exprp);
         }
@@ -721,7 +721,7 @@ private:
         AstNode* newp = nullptr;
         const int widthWords = portp->basicp()->widthWords();
         for (int i = 0; i < total; ++i) {
-            AstNode* srcp = new AstVarRef(portvscp->fileline(), portvscp, VAccess::WRITE);
+            AstNodeExpr* srcp = new AstVarRef(portvscp->fileline(), portvscp, VAccess::WRITE);
             // extract a scalar from multi-dimensional array (internal format)
             for (auto&& dimStride : dimStrides) {
                 const size_t dimIdx = (i / dimStride.second) % dimStride.first->elementsConst();
@@ -744,7 +744,7 @@ private:
                     from += "[" + cvtToStr(i * coef) + "]";
                 }
                 from += ket;
-                AstNode* const rhsp = new AstSel(
+                AstNodeExpr* const rhsp = new AstSel(
                     portp->fileline(), new AstCExpr(portp->fileline(), from, cwidth, false), 0,
                     portp->width());
                 stmtp = new AstAssign(portp->fileline(), srcp, rhsp);
@@ -1629,7 +1629,7 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp)
     for (int i = 0; i < tpinnum; ++i) {
         AstVar* const portp = tconnects[i].first;
         if (!tconnects[i].second || !tconnects[i].second->exprp()) {
-            AstNode* newvaluep = nullptr;
+            AstNodeExpr* newvaluep = nullptr;
             if (!portp->valuep()) {
                 nodep->v3error("Missing argument on non-defaulted argument "
                                << portp->prettyNameQ() << " in function call to "
@@ -1639,7 +1639,7 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp)
                 // The default value for this port might be a constant
                 // expression that hasn't been folded yet. Try folding it
                 // now; we don't have much to lose if it fails.
-                newvaluep = V3Const::constifyParamsEdit(portp->valuep());
+                newvaluep = V3Const::constifyParamsEdit(VN_AS(portp->valuep(), NodeExpr));
                 if (!VN_IS(newvaluep, Const)) {
                     // Problem otherwise is we might have a varref, task
                     // call, or something else that only makes sense in the
@@ -1653,7 +1653,7 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp)
                     newvaluep = newvaluep->cloneTree(true);
                 }
             } else {
-                newvaluep = portp->valuep()->cloneTree(true);
+                newvaluep = VN_AS(portp->valuep(), NodeExpr)->cloneTree(true);
             }
             // To avoid problems with callee needing to know to deleteTree
             // or not, we make this into a pin
diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp
index 30eb3d410..3a3ac25f0 100644
--- a/src/V3Timing.cpp
+++ b/src/V3Timing.cpp
@@ -91,7 +91,7 @@ private:
     //                                                            to this sentree
     //  Ast{NodeProcedure,CFunc,Begin}::user2()  -> bool.         Set true if process/task is
     //                                                            suspendable
-    //  AstSenTree::user2()                      -> AstText*.     Debug info passed to the
+    //  AstSenTree::user2()                      -> AstCExpr*.    Debug info passed to the
     //                                                            timing schedulers
     //  Ast{NodeProcedure,CFunc,Begin}::user3()  -> DependencyVertex*.  Vertex in m_depGraph
     const VNUser1InUse m_user1InUse;
@@ -286,24 +286,29 @@ private:
         return VN_AS(sensesp->user1p(), VarScope);
     }
     // Creates a string describing the sentree
-    AstText* createEventDescription(AstSenTree* const sensesp) const {
+    AstCExpr* createEventDescription(AstSenTree* const sensesp) const {
         if (!sensesp->user2p()) {
             std::stringstream ss;
             ss << '"';
             V3EmitV::verilogForTree(sensesp, ss);
             ss << '"';
-            auto* const commentp = new AstText{sensesp->fileline(), ss.str()};
+            auto* const commentp = new AstCExpr{sensesp->fileline(), ss.str(), 0};
+            commentp->dtypeSetString();
             sensesp->user2p(commentp);
             return commentp;
         }
-        return VN_AS(sensesp->user2p(), Text)->cloneTree(false);
+        return VN_AS(sensesp->user2p(), CExpr)->cloneTree(false);
     }
     // Adds debug info to a hardcoded method call
     void addDebugInfo(AstCMethodHard* const methodp) const {
         if (v3Global.opt.protectIds()) return;
         FileLine* const flp = methodp->fileline();
-        methodp->addPinsp(new AstText{flp, '"' + flp->filename() + '"'});
-        methodp->addPinsp(new AstText{flp, cvtToStr(flp->lineno())});
+        AstCExpr* const ap = new AstCExpr{flp, '"' + flp->filename() + '"', 0};
+        ap->dtypeSetString();
+        methodp->addPinsp(ap);
+        AstCExpr* const bp = new AstCExpr{flp, cvtToStr(flp->lineno()), 0};
+        bp->dtypeSetString();
+        methodp->addPinsp(bp);
     }
     // Adds debug info to a trigSched.trigger() call
     void addEventDebugInfo(AstCMethodHard* const methodp, AstSenTree* const sensesp) const {
@@ -491,7 +496,7 @@ private:
     }
     void visit(AstDelay* nodep) override {
         FileLine* const flp = nodep->fileline();
-        AstNode* valuep = V3Const::constifyEdit(nodep->lhsp()->unlinkFrBack());
+        AstNodeExpr* valuep = V3Const::constifyEdit(nodep->lhsp()->unlinkFrBack());
         auto* const constp = VN_CAST(valuep, Const);
         if (constp && constp->isZero()) {
             nodep->v3warn(ZERODLY, "Unsupported: #0 delays do not schedule process resumption in "
@@ -632,7 +637,8 @@ private:
         // do that. These intra-assignment vars will later be passed to forked processes by value.
         AstNode* const insertBeforep = VN_IS(m_procp, CFunc) ? controlp : nullptr;
         // Function for replacing values with intermediate variables
-        const auto replaceWithIntermediate = [&](AstNode* const valuep, const std::string& name) {
+        const auto replaceWithIntermediate = [&](AstNodeExpr* const valuep,
+                                                 const std::string& name) {
             AstVarScope* const newvscp = createTemp(flp, name, valuep->dtypep(), insertBeforep);
             valuep->replaceWith(new AstVarRef{flp, newvscp, VAccess::READ});
             controlp->addHereThisAsNext(
@@ -665,7 +671,7 @@ private:
         // TODO: Find a way to do this without introducing this var. Perhaps make
         // V3SchedAcyclic recognize awaits and prevent it from treating this kind of logic as
         // cyclic
-        AstNode* const lhsp = nodep->lhsp()->unlinkFrBack();
+        AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
         std::string varname;
         if (auto* const refp = VN_CAST(lhsp, VarRef)) {
             varname = m_contAssignVarNames.get(refp->name());
@@ -696,7 +702,7 @@ private:
         FileLine* const flp = nodep->fileline();
         AstNode* const stmtsp = nodep->stmtsp();
         if (stmtsp) stmtsp->unlinkFrBackWithNext();
-        AstNode* const condp = V3Const::constifyEdit(nodep->condp()->unlinkFrBack());
+        AstNodeExpr* const condp = V3Const::constifyEdit(nodep->condp()->unlinkFrBack());
         auto* const constp = VN_CAST(condp, Const);
         if (constp) {
             condp->v3warn(WAITCONST, "Wait statement condition is constant");
diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp
index aaf13244a..d1f5353d9 100644
--- a/src/V3Trace.cpp
+++ b/src/V3Trace.cpp
@@ -421,7 +421,7 @@ private:
         graphSimplify(false);
     }
 
-    AstNode* selectActivity(FileLine* flp, uint32_t acode, const VAccess& access) {
+    AstNodeExpr* selectActivity(FileLine* flp, uint32_t acode, const VAccess& access) {
         return new AstArraySel(flp, new AstVarRef(flp, m_activityVscp, access), acode);
     }
 
@@ -667,12 +667,12 @@ private:
                 if (!prevActSet || actSet != *prevActSet) {
                     FileLine* const flp = m_topScopep->fileline();
                     const bool always = actSet.count(TraceActivityVertex::ACTIVITY_ALWAYS) != 0;
-                    AstNode* condp = nullptr;
+                    AstNodeExpr* condp = nullptr;
                     if (always) {
                         condp = new AstConst(flp, 1);  // Always true, will be folded later
                     } else {
                         for (const uint32_t actCode : actSet) {
-                            AstNode* const selp = selectActivity(flp, actCode, VAccess::READ);
+                            AstNodeExpr* const selp = selectActivity(flp, actCode, VAccess::READ);
                             condp = condp ? new AstOr(flp, condp, selp) : selp;
                         }
                     }
diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp
index b8a5615e6..449abf60f 100644
--- a/src/V3TraceDecl.cpp
+++ b/src/V3TraceDecl.cpp
@@ -128,7 +128,7 @@ private:
     };
     std::vector<Signal> m_signals;  // Signals under current scope
     AstVarScope* m_traVscp = nullptr;  // Current AstVarScope we are constructing AstTraceDecls for
-    AstNode* m_traValuep = nullptr;  // Value expression for current signal
+    AstNodeExpr* m_traValuep = nullptr;  // Value expression for current signal
     string m_traName;  // Name component for current signal
 
     VDouble0 m_statSigs;  // Statistic tracking
diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp
index d5dda0f54..3c1b9e255 100644
--- a/src/V3Tristate.cpp
+++ b/src/V3Tristate.cpp
@@ -465,7 +465,7 @@ class TristateVisitor final : public TristateBaseVisitor {
         AstConst* const newp = new AstConst{nodep->fileline(), num};
         return newp;
     }
-    AstNode* getEnp(AstNode* nodep) {
+    AstNodeExpr* getEnp(AstNode* nodep) {
         if (nodep->user1p()) {
             if (AstVarRef* const refp = VN_CAST(nodep, VarRef)) {
                 if (refp->varp()->isIO()) {
@@ -480,7 +480,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             nodep->user1p(newAllZerosOrOnes(nodep, true));
         }
         // Otherwise return the previous output enable
-        return nodep->user1p();
+        return VN_AS(nodep->user1p(), NodeExpr);
     }
     AstVar* getCreateEnVarp(AstVar* invarp) {
         // Return the master __en for the specified input variable
@@ -501,7 +501,7 @@ class TristateVisitor final : public TristateBaseVisitor {
         numz0.opNot(numz);  // Z->0, else 1
         return new AstConst{fl, numz0};
     }
-    AstNode* getEnExprBasedOnOriginalp(AstNode* const nodep) {
+    AstNodeExpr* getEnExprBasedOnOriginalp(AstNodeExpr* const nodep) {
         if (AstVarRef* const varrefp = VN_CAST(nodep, VarRef)) {
             return new AstVarRef{varrefp->fileline(), getCreateEnVarp(varrefp->varp()),
                                  VAccess::READ};
@@ -514,17 +514,17 @@ class TristateVisitor final : public TristateBaseVisitor {
             // whole extend.
 
             // Unlink lhsp before copying to save unnecessary copy of lhsp
-            AstNode* const lhsp = extendp->lhsp()->unlinkFrBack();
+            AstNodeExpr* const lhsp = extendp->lhsp()->unlinkFrBack();
             AstExtend* const enExtendp = extendp->cloneTree(false);
             extendp->lhsp(lhsp);
-            AstNode* const enLhsp = getEnExprBasedOnOriginalp(lhsp);
+            AstNodeExpr* const enLhsp = getEnExprBasedOnOriginalp(lhsp);
             enExtendp->lhsp(new AstNot{enLhsp->fileline(), enLhsp});
             return new AstNot{enExtendp->fileline(), enExtendp};
         } else if (AstSel* const selp = VN_CAST(nodep, Sel)) {
-            AstNode* const fromp = selp->fromp()->unlinkFrBack();
+            AstNodeExpr* const fromp = selp->fromp()->unlinkFrBack();
             AstSel* const enSelp = selp->cloneTree(false);
             selp->fromp(fromp);
-            AstNode* const enFromp = getEnExprBasedOnOriginalp(fromp);
+            AstNodeExpr* const enFromp = getEnExprBasedOnOriginalp(fromp);
             enSelp->fromp(enFromp);
             return enSelp;
         } else {
@@ -566,10 +566,10 @@ class TristateVisitor final : public TristateBaseVisitor {
         }
     }
 
-    AstNode* newEnableDeposit(AstSel* selp, AstNode* enp) {
+    AstNodeExpr* newEnableDeposit(AstSel* selp, AstNodeExpr* enp) {
         // Form a "deposit" instruction for given enable, using existing select as a template.
         // Would be nicer if we made this a new AST type
-        AstNode* const newp = new AstShiftL(
+        AstNodeExpr* const newp = new AstShiftL(
             selp->fileline(), new AstExtend(selp->fileline(), enp, selp->fromp()->width()),
             selp->lsbp()->cloneTree(false), selp->fromp()->width());
         return newp;
@@ -659,8 +659,8 @@ class TristateVisitor final : public TristateBaseVisitor {
         // For each driver seperate variables (normal and __en) are created and initialized with
         // values. In case of normal variable, the original expression is reused. Their values are
         // aggregated using | to form one expression, which are assigned to varp end envarp.
-        AstNode* orp = nullptr;
-        AstNode* enp = nullptr;
+        AstNodeExpr* orp = nullptr;
+        AstNodeExpr* enp = nullptr;
 
         for (auto it = beginStrength; it != endStrength; it++) {
             AstVarRef* refp = it->m_varrefp;
@@ -689,14 +689,14 @@ class TristateVisitor final : public TristateBaseVisitor {
             nodep->addStmtsp(enLhspAssignp);
 
             // now append this driver to the driver logic.
-            AstNode* const ref1p = new AstVarRef{refp->fileline(), newLhsp, VAccess::READ};
-            AstNode* const ref2p = new AstVarRef{refp->fileline(), newEnLhsp, VAccess::READ};
-            AstNode* const andp = new AstAnd{refp->fileline(), ref1p, ref2p};
+            AstNodeExpr* const ref1p = new AstVarRef{refp->fileline(), newLhsp, VAccess::READ};
+            AstNodeExpr* const ref2p = new AstVarRef{refp->fileline(), newEnLhsp, VAccess::READ};
+            AstNodeExpr* const andp = new AstAnd{refp->fileline(), ref1p, ref2p};
 
             // or this to the others
             orp = (!orp) ? andp : new AstOr{refp->fileline(), orp, andp};
 
-            AstNode* const ref3p = new AstVarRef{refp->fileline(), newEnLhsp, VAccess::READ};
+            AstNodeExpr* const ref3p = new AstVarRef{refp->fileline(), newEnLhsp, VAccess::READ};
             enp = (!enp) ? ref3p : new AstOr{ref3p->fileline(), enp, ref3p};
         }
         AstNode* const assp = new AstAssignW{
@@ -742,8 +742,8 @@ class TristateVisitor final : public TristateBaseVisitor {
             envarp = VN_AS(invarp->user1p(), Var);  // From CASEEQ, foo === 1'bz
         }
 
-        AstNode* orp = nullptr;
-        AstNode* enp = nullptr;
+        AstNodeExpr* orp = nullptr;
+        AstNodeExpr* enp = nullptr;
         const int w = lhsp->width();
 
         std::sort(refsp->begin(), refsp->end(),
@@ -774,7 +774,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             aggregateTriSameStrength(nodep, varStrengthp, enVarStrengthp, beginStrength,
                                      endStrength);
 
-            AstNode* exprCurrentStrengthp;
+            AstNodeExpr* exprCurrentStrengthp;
             if (enp) {
                 // If weaker driver should be overwritten by a stronger, replace its value with z
                 exprCurrentStrengthp
@@ -785,7 +785,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             }
             orp = (!orp) ? exprCurrentStrengthp : new AstOr{fl, orp, exprCurrentStrengthp};
 
-            AstNode* enVarStrengthRefp = new AstVarRef{fl, enVarStrengthp, VAccess::READ};
+            AstNodeExpr* enVarStrengthRefp = new AstVarRef{fl, enVarStrengthp, VAccess::READ};
 
             enp = (!enp) ? enVarStrengthRefp : new AstOr{fl, enp, enVarStrengthRefp};
 
@@ -798,7 +798,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             const AstPull* const pullp = static_cast<AstPull*>(lhsp->user3p());
             bool pull1 = pullp && pullp->direction() == 1;  // Else default is down
 
-            AstNode* undrivenp;
+            AstNodeExpr* undrivenp;
             if (envarp) {
                 undrivenp = new AstNot{envarp->fileline(),
                                        new AstVarRef{envarp->fileline(), envarp, VAccess::READ}};
@@ -1033,20 +1033,20 @@ class TristateVisitor final : public TristateBaseVisitor {
             // expression 1 or 2 have an output enable '__en' signal. If the
             // condition has an enable, not sure what to do, so generate an
             // error.
-            AstNode* const condp = nodep->condp();
+            AstNodeExpr* const condp = nodep->condp();
             if (condp->user1p()) {
                 condp->v3warn(E_UNSUPPORTED, "Unsupported: don't know how to deal with "
                                              "tristate logic in the conditional expression");
             }
-            AstNode* const thenp = nodep->thenp();
-            AstNode* const elsep = nodep->elsep();
+            AstNodeExpr* const thenp = nodep->thenp();
+            AstNodeExpr* const elsep = nodep->elsep();
             if (thenp->user1p() || elsep->user1p()) {  // else no tristates
                 m_tgraph.didProcess(nodep);
-                AstNode* const en1p = getEnp(thenp);
-                AstNode* const en2p = getEnp(elsep);
+                AstNodeExpr* const en1p = getEnp(thenp);
+                AstNodeExpr* const en2p = getEnp(elsep);
                 // The output enable of a cond is a cond of the output enable of the
                 // two expressions with the same conditional.
-                AstNode* const enp
+                AstNodeExpr* const enp
                     = new AstCond(nodep->fileline(), condp->cloneTree(false), en1p, en2p);
                 UINFO(9, "       newcond " << enp << endl);
                 nodep->user1p(enp);  // propagate up COND(lhsp->enable, rhsp->enable)
@@ -1069,7 +1069,8 @@ class TristateVisitor final : public TristateBaseVisitor {
                 UINFO(9, dbgState() << nodep << endl);
                 if (nodep->user1p()) {
                     // Form a "deposit" instruction.  Would be nicer if we made this a new AST type
-                    AstNode* const newp = newEnableDeposit(nodep, nodep->user1p());
+                    AstNodeExpr* const newp
+                        = newEnableDeposit(nodep, VN_AS(nodep->user1p(), NodeExpr));
                     nodep->fromp()->user1p(newp);  // Push to varref (etc)
                     if (debug() >= 9) newp->dumpTree(cout, "-assign-sel; ");
                     m_tgraph.didProcess(nodep);
@@ -1083,8 +1084,8 @@ class TristateVisitor final : public TristateBaseVisitor {
                                                      << nodep->prettyTypeName());
                 }
                 if (nodep->fromp()->user1p()) {  // SEL(VARREF, lsb)
-                    AstNode* const en1p = getEnp(nodep->fromp());
-                    AstNode* const enp
+                    AstNodeExpr* const en1p = getEnp(nodep->fromp());
+                    AstNodeExpr* const enp
                         = new AstSel(nodep->fileline(), en1p, nodep->lsbp()->cloneTree(true),
                                      nodep->widthp()->cloneTree(true));
                     UINFO(9, "       newsel " << enp << endl);
@@ -1110,7 +1111,7 @@ class TristateVisitor final : public TristateBaseVisitor {
                 UINFO(9, dbgState() << nodep << endl);
                 if (nodep->user1p()) {
                     // Each half of the concat gets a select of the enable expression
-                    AstNode* const enp = nodep->user1p();
+                    AstNodeExpr* const enp = VN_AS(nodep->user1p(), NodeExpr);
                     nodep->user1p(nullptr);
                     nodep->lhsp()->user1p(new AstSel(nodep->fileline(), enp->cloneTree(true),
                                                      nodep->rhsp()->width(),
@@ -1125,13 +1126,13 @@ class TristateVisitor final : public TristateBaseVisitor {
                 UINFO(9, dbgState() << nodep << endl);
                 // Generate the new output enable signal, just as a concat
                 // identical to the data concat
-                AstNode* const expr1p = nodep->lhsp();
-                AstNode* const expr2p = nodep->rhsp();
+                AstNodeExpr* const expr1p = nodep->lhsp();
+                AstNodeExpr* const expr2p = nodep->rhsp();
                 if (expr1p->user1p() || expr2p->user1p()) {  // else no tristates
                     m_tgraph.didProcess(nodep);
-                    AstNode* const en1p = getEnp(expr1p);
-                    AstNode* const en2p = getEnp(expr2p);
-                    AstNode* const enp = new AstConcat(nodep->fileline(), en1p, en2p);
+                    AstNodeExpr* const en1p = getEnp(expr1p);
+                    AstNodeExpr* const en2p = getEnp(expr2p);
+                    AstNodeExpr* const enp = new AstConcat(nodep->fileline(), en1p, en2p);
                     UINFO(9, "       newconc " << enp << endl);
                     nodep->user1p(enp);  // propagate up CONCAT(lhsp->enable, rhsp->enable)
                     expr1p->user1p(nullptr);
@@ -1156,10 +1157,10 @@ class TristateVisitor final : public TristateBaseVisitor {
                 return;
             }
             m_tgraph.didProcess(nodep);
-            AstNode* const expr1p = nodep->lhsp()->unlinkFrBack();
-            AstNode* const expr2p = nodep->rhsp()->unlinkFrBack();
-            AstNode* enp;
-            if (AstNode* const en2p = expr2p->user1p()) {
+            AstNodeExpr* const expr1p = nodep->lhsp()->unlinkFrBack();
+            AstNodeExpr* const expr2p = nodep->rhsp()->unlinkFrBack();
+            AstNodeExpr* enp;
+            if (AstNodeExpr* const en2p = VN_AS(expr2p->user1p(), NodeExpr)) {
                 enp = new AstAnd(nodep->fileline(), expr1p, en2p);
             } else {
                 enp = expr1p;
@@ -1199,22 +1200,22 @@ class TristateVisitor final : public TristateBaseVisitor {
             // have to define what is means to OR 1'bz with other
             // expressions. Here I take the approach that when one expression
             // is 0, that is passes the other.
-            AstNode* const expr1p = nodep->lhsp();
-            AstNode* const expr2p = nodep->rhsp();
+            AstNodeExpr* const expr1p = nodep->lhsp();
+            AstNodeExpr* const expr2p = nodep->rhsp();
             if (!expr1p->user1p() && !expr2p->user1p()) {
                 return;  // no tristates in either expression, so nothing to do
             }
             m_tgraph.didProcess(nodep);
-            AstNode* const en1p = getEnp(expr1p);
-            AstNode* const en2p = getEnp(expr2p);
-            AstNode* subexpr1p = expr1p->cloneTree(false);
-            AstNode* subexpr2p = expr2p->cloneTree(false);
+            AstNodeExpr* const en1p = getEnp(expr1p);
+            AstNodeExpr* const en2p = getEnp(expr2p);
+            AstNodeExpr* subexpr1p = expr1p->cloneTree(false);
+            AstNodeExpr* subexpr2p = expr2p->cloneTree(false);
             if (isAnd) {
                 subexpr1p = new AstNot(nodep->fileline(), subexpr1p);
                 subexpr2p = new AstNot(nodep->fileline(), subexpr2p);
             }
             // calc new output enable
-            AstNode* const enp = new AstOr(
+            AstNodeExpr* const enp = new AstOr(
                 nodep->fileline(), new AstAnd(nodep->fileline(), en1p, en2p),
                 new AstOr(nodep->fileline(),
                           new AstAnd(nodep->fileline(), en1p->cloneTree(false), subexpr1p),
@@ -1301,12 +1302,12 @@ class TristateVisitor final : public TristateBaseVisitor {
             AstConst* const constp = VN_CAST(nodep->lhsp(), Const);
             if (constp && constp->user1p()) {
                 // 3'b1z0 -> ((3'b101 == in__en) && (3'b100 == in))
-                AstNode* const rhsp = nodep->rhsp();
+                AstNodeExpr* const rhsp = nodep->rhsp();
                 rhsp->unlinkFrBack();
                 FileLine* const fl = nodep->fileline();
-                AstNode* enRhsp;
+                AstNodeExpr* enRhsp;
                 if (rhsp->user1p()) {
-                    enRhsp = rhsp->user1p();
+                    enRhsp = VN_AS(rhsp->user1p(), NodeExpr);
                     rhsp->user1p(nullptr);
                 } else {
                     enRhsp = getEnExprBasedOnOriginalp(rhsp);
@@ -1315,7 +1316,7 @@ class TristateVisitor final : public TristateBaseVisitor {
                     = VN_AS(constp->user1p(), Const)
                           ->num();  // visit(AstConst) already split into en/ones
                 const V3Number& oneIfEnOne = constp->num();
-                AstNode* newp
+                AstNodeExpr* newp
                     = new AstLogAnd{fl, new AstEq{fl, new AstConst{fl, oneIfEn}, enRhsp},
                                     // Keep the caseeq if there are X's present
                                     new AstEqCase{fl, new AstConst{fl, oneIfEnOne}, rhsp}};
@@ -1328,11 +1329,12 @@ class TristateVisitor final : public TristateBaseVisitor {
             } else if (constp && nodep->rhsp()->user1p()) {
                 FileLine* const fl = nodep->fileline();
                 constp->unlinkFrBack();
-                AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
-                AstNode* newp = new AstLogAnd{
-                    fl, new AstEq{fl, newAllZerosOrOnes(constp, false), rhsp->user1p()},
-                    // Keep the caseeq if there are X's present
-                    new AstEqCase{fl, constp, rhsp}};
+                AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
+                AstNodeExpr* newp = new AstLogAnd{fl,
+                                                  new AstEq{fl, newAllZerosOrOnes(constp, false),
+                                                            VN_AS(rhsp->user1p(), NodeExpr)},
+                                                  // Keep the caseeq if there are X's present
+                                                  new AstEqCase{fl, constp, rhsp}};
                 if (neq) newp = new AstLogNot{fl, newp};
                 rhsp->user1p(nullptr);
                 UINFO(9, "       newceq " << newp << endl);
@@ -1376,7 +1378,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             if (!dropop[1]) iterateAndNextNull(nodep->thsp());
             if (!dropop[2]) iterateAndNextNull(nodep->fhsp());
         } else {
-            AstNode* nonXp = nullptr;
+            AstNodeExpr* nonXp = nullptr;
             if (!dropop[0]) {
                 nonXp = nodep->rhsp();
             } else if (!dropop[1]) {
@@ -1400,7 +1402,7 @@ class TristateVisitor final : public TristateBaseVisitor {
                 UINFO(4, " COUNTBITS('z)-> " << nodep << endl);
                 VNRelinker relinkHandle;
                 nodep->unlinkFrBack(&relinkHandle);
-                AstNode* newp = new AstCountOnes(
+                AstNodeExpr* newp = new AstCountOnes(
                     nodep->fileline(), new AstVarRef(nodep->fileline(), envarp, VAccess::READ));
                 if (nonXp) {  // Need to still count '0 or '1 or 'x's
                     if (dropop[0]) {
@@ -1545,7 +1547,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             // Therefore, create the enable, output and separate input pin,
             // then pinReconnectSimple all
             // Create the output enable pin, connect to new signal
-            AstNode* enrefp;
+            AstNodeExpr* enrefp;
             {
                 AstVar* const enVarp = new AstVar(nodep->fileline(), VVarType::MODULETEMP,
                                                   nodep->name() + "__en" + cvtToStr(m_unique++),
@@ -1580,8 +1582,8 @@ class TristateVisitor final : public TristateBaseVisitor {
                                                      << nodep->prettyNameQ());
                 }
             } else {
-                AstNode* const outexprp
-                    = nodep->exprp()->cloneTree(false);  // Note has lvalue() set
+                AstNodeExpr* const outexprp
+                    = VN_AS(nodep->exprp(), NodeExpr)->cloneTree(false);  // Note has lvalue() set
                 outpinp = new AstPin(nodep->fileline(), nodep->pinNum(),
                                      outModVarp->name(),  // should be {var}"__out"
                                      outexprp);
diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp
index abd550ea5..8d768dedb 100644
--- a/src/V3Unknown.cpp
+++ b/src/V3Unknown.cpp
@@ -68,7 +68,7 @@ private:
 
     // METHODS
 
-    void replaceBoundLvalue(AstNode* nodep, AstNode* condp) {
+    void replaceBoundLvalue(AstNodeExpr* nodep, AstNodeExpr* condp) {
         // Spec says a out-of-range LHS SEL results in a NOP.
         // This is a PITA.  We could:
         //  1. IF(...) around an ASSIGN,
@@ -101,11 +101,11 @@ private:
             m_assigndlyp->replaceWith(newp);
             VL_DO_CLEAR(pushDeletep(m_assigndlyp), m_assigndlyp = nullptr);
         }
-        AstNode* prep = nodep;
+        AstNodeExpr* prep = nodep;
 
         // Scan back to put the condlvalue above all selects (IE top of the lvalue)
         while (VN_IS(prep->backp(), NodeSel) || VN_IS(prep->backp(), Sel)) {
-            prep = prep->backp();
+            prep = VN_AS(prep->backp(), NodeExpr);
         }
         FileLine* const fl = nodep->fileline();
         VL_DANGLING(nodep);  // Zap it so we don't use it by mistake - use prep
@@ -115,8 +115,8 @@ private:
         if (const AstIf* const ifp = VN_AS(prep->user2p(), If)) {
             UASSERT_OBJ(!needDly, prep, "Should have already converted to non-delay");
             VNRelinker replaceHandle;
-            AstNode* const earliercondp = ifp->condp()->unlinkFrBack(&replaceHandle);
-            AstNode* const newp = new AstLogAnd(condp->fileline(), condp, earliercondp);
+            AstNodeExpr* const earliercondp = ifp->condp()->unlinkFrBack(&replaceHandle);
+            AstNodeExpr* const newp = new AstLogAnd(condp->fileline(), condp, earliercondp);
             UINFO(4, "Edit BOUNDLVALUE " << newp << endl);
             replaceHandle.relink(newp);
         } else {
@@ -207,9 +207,9 @@ private:
             VL_DO_DANGLING(V3Const::constifyEdit(nodep), nodep);
             return;
         } else {
-            AstNode* const lhsp = nodep->lhsp()->unlinkFrBack();
-            AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
-            AstNode* newp;
+            AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
+            AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
+            AstNodeExpr* newp;
             // If we got ==1'bx it can never be true (but 1'bx==1'bx can be!)
             if (((VN_IS(lhsp, Const) && VN_AS(lhsp, Const)->num().isFourState())
                  || (VN_IS(rhsp, Const) && VN_AS(rhsp, Const)->num().isFourState()))) {
@@ -239,9 +239,9 @@ private:
             VL_DO_DANGLING(V3Const::constifyEdit(nodep), nodep);
             return;
         } else {
-            AstNode* const lhsp = nodep->lhsp()->unlinkFrBack();
-            AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
-            AstNode* newp;
+            AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
+            AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
+            AstNodeExpr* newp;
             if (!VN_IS(rhsp, Const)) {
                 nodep->v3warn(E_UNSUPPORTED, "Unsupported: RHS of ==? or !=? must be "
                                              "constant to be synthesizable");  // Says spec.
@@ -253,9 +253,9 @@ private:
                 nummask.opBitsNonX(VN_AS(rhsp, Const)->num());
                 V3Number numval(rhsp, rhsp->width());
                 numval.opBitsOne(VN_AS(rhsp, Const)->num());
-                AstNode* const and1p = new AstAnd(nodep->fileline(), lhsp,
-                                                  new AstConst(nodep->fileline(), nummask));
-                AstNode* const and2p = new AstConst(nodep->fileline(), numval);
+                AstNodeExpr* const and1p = new AstAnd(nodep->fileline(), lhsp,
+                                                      new AstConst(nodep->fileline(), nummask));
+                AstNodeExpr* const and2p = new AstConst(nodep->fileline(), numval);
                 if (VN_IS(nodep, EqWild)) {
                     newp = new AstEq(nodep->fileline(), and1p, and2p);
                 } else {
@@ -290,7 +290,7 @@ private:
         dropop[2] = VN_IS(nodep->fhsp(), Const) && VN_AS(nodep->fhsp(), Const)->num().isAnyX();
         UINFO(4, " COUNTBITS(" << dropop[0] << dropop[1] << dropop[2] << " " << nodep << endl);
 
-        AstNode* nonXp = nullptr;
+        AstNodeExpr* nonXp = nullptr;
         if (!dropop[0]) {
             nonXp = nodep->rhsp();
         } else if (!dropop[1]) {
@@ -394,10 +394,11 @@ private:
             if (debug() >= 9) nodep->dumpTree(cout, "sel_old: ");
 
             // If (maxmsb >= selected), we're in bound
-            AstNode* condp = new AstGte(nodep->fileline(),
-                                        new AstConst(nodep->fileline(), AstConst::WidthedValue(),
-                                                     nodep->lsbp()->width(), maxmsb),
-                                        nodep->lsbp()->cloneTree(false));
+            AstNodeExpr* condp
+                = new AstGte(nodep->fileline(),
+                             new AstConst(nodep->fileline(), AstConst::WidthedValue(),
+                                          nodep->lsbp()->width(), maxmsb),
+                             nodep->lsbp()->cloneTree(false));
             // See if the condition is constant true (e.g. always in bound due to constant select)
             // Note below has null backp(); the Edit function knows how to deal with that.
             condp = V3Const::constifyEdit(condp);
@@ -452,10 +453,11 @@ private:
             if (debug() >= 9) nodep->dumpTree(cout, "arraysel_old: ");
 
             // See if the condition is constant true
-            AstNode* condp = new AstGte(nodep->fileline(),
-                                        new AstConst(nodep->fileline(), AstConst::WidthedValue(),
-                                                     nodep->bitp()->width(), declElements - 1),
-                                        nodep->bitp()->cloneTree(false));
+            AstNodeExpr* condp
+                = new AstGte(nodep->fileline(),
+                             new AstConst(nodep->fileline(), AstConst::WidthedValue(),
+                                          nodep->bitp()->width(), declElements - 1),
+                             nodep->bitp()->cloneTree(false));
             // Note below has null backp(); the Edit function knows how to deal with that.
             condp = V3Const::constifyEdit(condp);
             if (condp->isOne()) {
@@ -483,8 +485,8 @@ private:
             } else if (!lvalue) {  // Mid-multidimension read, just use zero
                 // ARRAYSEL(...) -> ARRAYSEL(COND(LT(bit<maxbit), bit, 0))
                 VNRelinker replaceHandle;
-                AstNode* const bitp = nodep->bitp()->unlinkFrBack(&replaceHandle);
-                AstNode* const newp = new AstCondBound(
+                AstNodeExpr* const bitp = nodep->bitp()->unlinkFrBack(&replaceHandle);
+                AstNodeExpr* const newp = new AstCondBound(
                     bitp->fileline(), condp, bitp,
                     new AstConst(bitp->fileline(), AstConst::WidthedValue(), bitp->width(), 0));
                 // Added X's, tristate them too
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 176f8c00e..f59ea4cea 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -770,22 +770,10 @@ private:
             iterateCheckSizedSelf(nodep, "LHS", nodep->lhsp(), SELF, BOTH);
             iterateCheckSizedSelf(nodep, "RHS", nodep->rhsp(), SELF, BOTH);
             V3Const::constifyParamsEdit(nodep->rhsp());  // rhsp may change
-            const AstConst* const constp = VN_CAST(nodep->rhsp(), Const);
-            AstBasicDType* const basicp = VN_CAST(nodep->rhsp(), BasicDType);
-            if (!constp && !basicp) {
-                nodep->v3error("Slice size isn't a constant or basic data type.");
-                return;
-            }
-            if (basicp) {  // Convert data type to a constant size
-                AstConst* const newp = new AstConst(basicp->fileline(), basicp->width());
-                nodep->rhsp()->replaceWith(newp);
-                pushDeletep(basicp);
+            if (const AstConst* const constp = VN_CAST(nodep->rhsp(), Const)) {
+                if (constp->toUInt() == 0) nodep->v3error("Slice size cannot be zero.");
             } else {
-                const uint32_t sliceSize = constp->toUInt();
-                if (!sliceSize) {
-                    nodep->v3error("Slice size cannot be zero.");
-                    return;
-                }
+                nodep->v3error("Slice size isn't a constant or basic data type.");
             }
             nodep->dtypeSetLogicUnsized(nodep->lhsp()->width(), nodep->lhsp()->widthMin(),
                                         VSigning::UNSIGNED);
@@ -1444,8 +1432,8 @@ private:
             if (VN_IS(dtypep, QueueDType)) {
                 switch (nodep->attrType()) {
                 case VAttrType::DIM_SIZE: {
-                    AstNode* const newp = new AstCMethodHard(
-                        nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size");
+                    AstNodeExpr* const fromp = VN_AS(nodep->fromp()->unlinkFrBack(), NodeExpr);
+                    AstNode* const newp = new AstCMethodHard{nodep->fileline(), fromp, "size"};
                     newp->dtypeSetSigned32();
                     newp->didWidth(true);
                     newp->protect(false);
@@ -1462,8 +1450,9 @@ private:
                 }
                 case VAttrType::DIM_RIGHT:
                 case VAttrType::DIM_HIGH: {
-                    AstNode* const sizep = new AstCMethodHard(
-                        nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size");
+                    AstNodeExpr* const fromp = VN_AS(nodep->fromp()->unlinkFrBack(), NodeExpr);
+                    AstNodeExpr* const sizep
+                        = new AstCMethodHard{nodep->fileline(), fromp, "size"};
                     sizep->dtypeSetSigned32();
                     sizep->didWidth(true);
                     sizep->protect(false);
@@ -1475,7 +1464,7 @@ private:
                     break;
                 }
                 case VAttrType::DIM_INCREMENT: {
-                    AstNode* const newp
+                    AstNodeExpr* const newp
                         = new AstConst(nodep->fileline(), AstConst::Signed32(), -1);
                     nodep->replaceWith(newp);
                     VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -1493,9 +1482,9 @@ private:
                 if (!nodep->dimp() || msbdim < 1) {
                     if (VN_IS(dtypep, BasicDType) && dtypep->basicp()->isString()) {
                         // IEEE undocumented but $bits(string) must give length(string) * 8
+                        AstNodeExpr* const fromp = VN_AS(nodep->fromp()->unlinkFrBack(), NodeExpr);
                         AstNode* const newp = new AstShiftL{
-                            nodep->fileline(),
-                            new AstLenN{nodep->fileline(), nodep->fromp()->unlinkFrBack()},
+                            nodep->fileline(), new AstLenN{nodep->fileline(), fromp},
                             new AstConst{nodep->fileline(), 3},  // * 8
                             32};
                         nodep->replaceWith(newp);
@@ -1516,8 +1505,8 @@ private:
                 } else {  // Need a runtime lookup table.  Yuk.
                     UASSERT_OBJ(nodep->fromp() && dtypep, nodep, "Unsized expression");
                     AstVar* const varp = dimensionVarp(dtypep, nodep->attrType(), msbdim);
-                    AstNode* const dimp = nodep->dimp()->unlinkFrBack();
-                    AstNode* const newp
+                    AstNodeExpr* const dimp = nodep->dimp()->unlinkFrBack();
+                    AstNodeExpr* const newp
                         = new AstArraySel{nodep->fileline(), newVarRefDollarUnit(varp), dimp};
                     nodep->replaceWith(newp);
                     VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -1610,7 +1599,7 @@ private:
             newp = new AstUnpackArrayDType(
                 nodep->fileline(), VFlagChildDType(), childp,
                 new AstRange(nodep->fileline(), new AstConst(elementsp->fileline(), 0),
-                             new AstSub(elementsp->fileline(), elementsp,
+                             new AstSub(elementsp->fileline(), VN_AS(elementsp, NodeExpr),
                                         new AstConst(elementsp->fileline(), 1))));
         }
         nodep->replaceWith(newp);
@@ -1769,7 +1758,7 @@ private:
             UASSERT_OBJ(enumDtp, nodep, "$cast determined as enum, but not enum type");
             const uint64_t maxval = enumMaxValue(nodep, enumDtp);
             const bool assoc = maxval > ENUM_LOOKUP_BITS;
-            AstNode* testp = nullptr;
+            AstNodeExpr* testp = nullptr;
             FileLine* const fl_novalue = new FileLine{fl};
             fl_novalue->warnOff(V3ErrorCode::ENUMVALUE, true);
             if (assoc) {
@@ -1881,7 +1870,7 @@ private:
             // For now, replace it ASAP, so widthing can propagate easily
             // The cast may change signing, but we don't know the sign yet.  Make it so.
             // Note we don't sign fromp() that would make the algorithm O(n^2) if lots of casting.
-            AstNode* newp = nullptr;
+            AstNodeExpr* newp = nullptr;
             if (bad) {
             } else if (const AstBasicDType* const basicp = toDtp->basicp()) {
                 if (!basicp->isDouble() && !fromDtp->isDouble()) {
@@ -1942,10 +1931,9 @@ private:
     void visit(AstCastSize* nodep) override {
         // IEEE: Signedness of result is same as self-determined signedness
         // However, the result is same as BITSEL, so we do not sign extend the LHS
-        UASSERT_OBJ(VN_IS(nodep->rhsp(), Const), nodep, "Unsupported: Non-const cast of size");
         // if (debug()) nodep->dumpTree(cout, "  CastSizePre: ");
         if (m_vup->prelim()) {
-            int width = VN_AS(nodep->rhsp(), Const)->toSInt();
+            int width = nodep->rhsp()->toSInt();
             if (width < 1) {
                 nodep->v3error("Size-changing cast to zero or negative size");
                 width = 1;
@@ -1996,7 +1984,8 @@ private:
                        : nodep->findBitDType(width, width, underDtp->numeric()));
             nodep->dtypep(outDtp);
             // We ignore warnings as that is sort of the point of a cast
-            widthCheckSized(nodep, "Cast expr", underp, outDtp, EXTEND_EXP, false);
+            widthCheckSized(nodep, "Cast expr", VN_AS(underp, NodeExpr), outDtp, EXTEND_EXP,
+                            false);
             VL_DANGLING(underp);
         }
     }
@@ -2403,10 +2392,10 @@ private:
         nodep->dtypeSetBit();
         if (debug() >= 9) nodep->dumpTree(cout, "-inside-in: ");
         // Now rip out the inside and replace with simple math
-        AstNode* newp = nullptr;
-        for (AstNode *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) {
-            nextip = itemp->nextp();  // Will be unlinking
-            AstNode* inewp;
+        AstNodeExpr* newp = nullptr;
+        for (AstNodeExpr *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) {
+            nextip = VN_AS(itemp->nextp(), NodeExpr);  // Will be unlinking
+            AstNodeExpr* inewp;
             const AstNodeDType* const itemDtp = itemp->dtypep()->skipRefp();
             if (AstInsideRange* const irangep = VN_CAST(itemp, InsideRange)) {
                 // Similar logic in V3Case
@@ -2878,7 +2867,7 @@ private:
         } else if (nodep->name() == "exists") {  // function int exists(input index)
             // IEEE really should have made this a "bit" return
             methodOkArguments(nodep, 1, 1);
-            AstNode* const index_exprp = methodCallWildcardIndexExpr(nodep, adtypep);
+            AstNodeExpr* const index_exprp = methodCallWildcardIndexExpr(nodep, adtypep);
             newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), "exists",
                                       index_exprp->unlinkFrBack()};
             newp->dtypeSetSigned32();
@@ -2891,7 +2880,7 @@ private:
                                           "clear"};
                 newp->dtypeSetVoid();
             } else {
-                AstNode* const index_exprp = methodCallWildcardIndexExpr(nodep, adtypep);
+                AstNodeExpr* const index_exprp = methodCallWildcardIndexExpr(nodep, adtypep);
                 newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                           "erase", index_exprp->unlinkFrBack()};
                 newp->dtypeSetVoid();
@@ -2954,7 +2943,7 @@ private:
                    || nodep->name() == "next"  //
                    || nodep->name() == "prev") {
             methodOkArguments(nodep, 1, 1);
-            AstNode* const index_exprp = methodCallAssocIndexExpr(nodep, adtypep);
+            AstNodeExpr* const index_exprp = methodCallAssocIndexExpr(nodep, adtypep);
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name(),  // first/last/next/prev
                                       index_exprp->unlinkFrBack());
@@ -2963,7 +2952,7 @@ private:
         } else if (nodep->name() == "exists") {  // function int exists(input index)
             // IEEE really should have made this a "bit" return
             methodOkArguments(nodep, 1, 1);
-            AstNode* const index_exprp = methodCallAssocIndexExpr(nodep, adtypep);
+            AstNodeExpr* const index_exprp = methodCallAssocIndexExpr(nodep, adtypep);
             newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "exists",
                                       index_exprp->unlinkFrBack());
             newp->dtypeSetSigned32();
@@ -2976,7 +2965,7 @@ private:
                                           "clear");
                 newp->dtypeSetVoid();
             } else {
-                AstNode* const index_exprp = methodCallAssocIndexExpr(nodep, adtypep);
+                AstNodeExpr* const index_exprp = methodCallAssocIndexExpr(nodep, adtypep);
                 newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                           "erase", index_exprp->unlinkFrBack());
                 newp->dtypeSetVoid();
@@ -3039,14 +3028,15 @@ private:
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         }
     }
-    AstNode* methodCallAssocIndexExpr(AstMethodCall* nodep, AstAssocArrayDType* adtypep) {
+    AstNodeExpr* methodCallAssocIndexExpr(AstMethodCall* nodep, AstAssocArrayDType* adtypep) {
         AstNode* const index_exprp = VN_CAST(nodep->pinsp(), Arg)->exprp();
         iterateCheck(nodep, "index", index_exprp, CONTEXT_DET, FINAL, adtypep->keyDTypep(),
                      EXTEND_EXP);
         VL_DANGLING(index_exprp);  // May have been edited
         return VN_AS(nodep->pinsp(), Arg)->exprp();
     }
-    AstNode* methodCallWildcardIndexExpr(AstMethodCall* nodep, AstWildcardArrayDType* adtypep) {
+    AstNodeExpr* methodCallWildcardIndexExpr(AstMethodCall* nodep,
+                                             AstWildcardArrayDType* adtypep) {
         AstNode* const index_exprp = VN_CAST(nodep->pinsp(), Arg)->exprp();
         iterateCheck(nodep, "index", index_exprp, CONTEXT_DET, FINAL, adtypep->findStringDType(),
                      EXTEND_EXP);
@@ -3172,7 +3162,7 @@ private:
                                           "clear");
                 newp->dtypeSetVoid();
             } else {
-                AstNode* const index_exprp = methodCallQueueIndexExpr(nodep);
+                AstNodeExpr* const index_exprp = methodCallQueueIndexExpr(nodep);
                 if (index_exprp->isZero()) {  // delete(0) is a pop_front
                     newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                               "pop_front");
@@ -3187,7 +3177,7 @@ private:
         } else if (nodep->name() == "insert") {
             methodOkArguments(nodep, 2, 2);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
-            AstNode* const index_exprp = methodCallQueueIndexExpr(nodep);
+            AstNodeExpr* const index_exprp = methodCallQueueIndexExpr(nodep);
             AstArg* const argp = VN_AS(nodep->pinsp()->nextp(), Arg);
             iterateCheckTyped(nodep, "insert value", argp->exprp(), adtypep->subDTypep(), BOTH);
             if (index_exprp->isZero()) {  // insert(0, ...) is a push_front
@@ -3285,7 +3275,7 @@ private:
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         }
     }
-    AstNode* methodCallQueueIndexExpr(AstMethodCall* nodep) {
+    AstNodeExpr* methodCallQueueIndexExpr(AstMethodCall* nodep) {
         AstNode* const index_exprp = VN_AS(nodep->pinsp(), Arg)->exprp();
         iterateCheckSigned32(nodep, "index", index_exprp, BOTH);
         VL_DANGLING(index_exprp);  // May have been edited
@@ -3304,7 +3294,7 @@ private:
                 = VN_CAST(classp->findMember(nodep->name()), NodeFTask)) {
                 userIterate(ftaskp, nullptr);
                 if (ftaskp->lifetime().isStatic()) {
-                    AstNode* argsp = nullptr;
+                    AstNodeExpr* argsp = nullptr;
                     if (nodep->pinsp()) argsp = nodep->pinsp()->unlinkFrBackWithNext();
                     AstNodeFTaskRef* newp = nullptr;
                     if (VN_IS(ftaskp, Task)) {
@@ -3369,10 +3359,10 @@ private:
         if (methodId) {
             methodOkArguments(nodep, 0, 0);
             FileLine* const fl = nodep->fileline();
-            AstNode* newp = nullptr;
+            AstNodeExpr* newp = nullptr;
             for (int i = 0; i < adtypep->elementsConst(); ++i) {
-                AstNode* const arrayRef = nodep->fromp()->cloneTree(false);
-                AstNode* const selector = new AstArraySel(fl, arrayRef, i);
+                AstNodeExpr* const arrayRef = nodep->fromp()->cloneTree(false);
+                AstNodeExpr* const selector = new AstArraySel(fl, arrayRef, i);
                 if (!newp) {
                     newp = selector;
                 } else {
@@ -3446,8 +3436,8 @@ private:
             const bool ignoreCase = nodep->name()[0] == 'i';
             methodOkArguments(nodep, 1, 1);
             AstArg* const argp = VN_AS(nodep->pinsp(), Arg);
-            AstNode* const lhs = nodep->fromp()->unlinkFrBack();
-            AstNode* const rhs = argp->exprp()->unlinkFrBack();
+            AstNodeExpr* const lhs = nodep->fromp()->unlinkFrBack();
+            AstNodeExpr* const rhs = argp->exprp()->unlinkFrBack();
             AstNode* const newp = new AstCompareNN(nodep->fileline(), lhs, rhs, ignoreCase);
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -3456,8 +3446,8 @@ private:
             AstArg* const arg0p = VN_AS(nodep->pinsp(), Arg);
             AstArg* const arg1p = VN_AS(arg0p->nextp(), Arg);
             AstNodeVarRef* const fromp = VN_AS(nodep->fromp()->unlinkFrBack(), VarRef);
-            AstNode* const rhsp = arg0p->exprp()->unlinkFrBack();
-            AstNode* const thsp = arg1p->exprp()->unlinkFrBack();
+            AstNodeExpr* const rhsp = arg0p->exprp()->unlinkFrBack();
+            AstNodeExpr* const thsp = arg1p->exprp()->unlinkFrBack();
             AstVarRef* const varrefp
                 = new AstVarRef(nodep->fileline(), fromp->varp(), VAccess::READ);
             AstNode* const newp = new AstAssign(
@@ -3468,19 +3458,19 @@ private:
         } else if (nodep->name() == "getc") {
             methodOkArguments(nodep, 1, 1);
             AstArg* const arg0p = VN_AS(nodep->pinsp(), Arg);
-            AstNode* const lhsp = nodep->fromp()->unlinkFrBack();
-            AstNode* const rhsp = arg0p->exprp()->unlinkFrBack();
-            AstNode* const newp = new AstGetcN(nodep->fileline(), lhsp, rhsp);
+            AstNodeExpr* const lhsp = nodep->fromp()->unlinkFrBack();
+            AstNodeExpr* const rhsp = arg0p->exprp()->unlinkFrBack();
+            AstNodeExpr* const newp = new AstGetcN(nodep->fileline(), lhsp, rhsp);
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else if (nodep->name() == "substr") {
             methodOkArguments(nodep, 2, 2);
             AstArg* const arg0p = VN_AS(nodep->pinsp(), Arg);
             AstArg* const arg1p = VN_AS(arg0p->nextp(), Arg);
-            AstNode* const lhsp = nodep->fromp()->unlinkFrBack();
-            AstNode* const rhsp = arg0p->exprp()->unlinkFrBack();
-            AstNode* const thsp = arg1p->exprp()->unlinkFrBack();
-            AstNode* const newp = new AstSubstrN(nodep->fileline(), lhsp, rhsp, thsp);
+            AstNodeExpr* const lhsp = nodep->fromp()->unlinkFrBack();
+            AstNodeExpr* const rhsp = arg0p->exprp()->unlinkFrBack();
+            AstNodeExpr* const thsp = arg1p->exprp()->unlinkFrBack();
+            AstNodeExpr* const newp = new AstSubstrN(nodep->fileline(), lhsp, rhsp, thsp);
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else if (nodep->name() == "atobin" || nodep->name() == "atohex"
@@ -3628,7 +3618,7 @@ private:
                     // So detach, add next and reattach
                     VNRelinker relinkHandle;
                     patp->unlinkFrBack(&relinkHandle);
-                    while (AstNode* const movep = patp->lhssp()->nextp()) {
+                    while (AstNodeExpr* const movep = VN_AS(patp->lhssp()->nextp(), NodeExpr)) {
                         movep->unlinkFrBack();  // Not unlinkFrBackWithNext, just one
                         AstNode* newkeyp = nullptr;
                         if (patp->keyp()) newkeyp = patp->keyp()->cloneTree(true);
@@ -3743,7 +3733,7 @@ private:
                 if (patp) patp = VN_AS(patp->nextp(), PatMember);
             }
         }
-        AstNode* newp = nullptr;
+        AstNodeExpr* newp = nullptr;
         for (AstMemberDType* memp = vdtypep->membersp(); memp;
              memp = VN_AS(memp->nextp(), MemberDType)) {
             const auto it = patmap.find(memp);
@@ -3773,9 +3763,9 @@ private:
         VL_DO_DANGLING(pushDeletep(nodep), nodep);  // Deletes defaultp also, if present
     }
 
-    AstNode* nestedvalueConcat_patternUOrStruct(AstNodeUOrStructDType* memp_vdtypep,
-                                                AstPatMember* defaultp, AstNode* newp,
-                                                AstPattern* nodep, DTypeMap dtypemap) {
+    AstNodeExpr* nestedvalueConcat_patternUOrStruct(AstNodeUOrStructDType* memp_vdtypep,
+                                                    AstPatMember* defaultp, AstNodeExpr* newp,
+                                                    AstPattern* nodep, DTypeMap dtypemap) {
         AstPatMember* patp = nullptr;
         for (AstMemberDType* memp_nested = memp_vdtypep->membersp(); memp_nested;
              memp_nested = VN_AS(memp_nested->nextp(), MemberDType)) {
@@ -3816,11 +3806,11 @@ private:
         return patp;
     }
 
-    AstNode* valueConcat_patternUOrStruct(AstPatMember* patp, AstNode* newp, AstMemberDType* memp,
-                                          AstPattern* nodep) {
+    AstNodeExpr* valueConcat_patternUOrStruct(AstPatMember* patp, AstNodeExpr* newp,
+                                              AstMemberDType* memp, AstPattern* nodep) {
         if (patp) {
             patp->dtypep(memp);
-            AstNode* const valuep = patternMemberValueIterate(patp);
+            AstNodeExpr* const valuep = patternMemberValueIterate(patp);
             if (!newp) {
                 newp = valuep;
             } else {
@@ -3858,11 +3848,11 @@ private:
             if (patp) {
                 // Don't want the RHS an array
                 patp->dtypep(arrayDtp->subDTypep());
-                AstNode* const valuep = patternMemberValueIterate(patp);
+                AstNodeExpr* const valuep = patternMemberValueIterate(patp);
                 if (VN_IS(arrayDtp, UnpackArrayDType)) {
                     if (!newp) {
                         AstInitArray* const newap
-                            = new AstInitArray(nodep->fileline(), arrayDtp, nullptr);
+                            = new AstInitArray{nodep->fileline(), arrayDtp, nullptr};
                         newp = newap;
                     }
                     VN_AS(newp, InitArray)->addIndexValuep(ent - range.lo(), valuep);
@@ -3870,7 +3860,8 @@ private:
                     if (!newp) {
                         newp = valuep;
                     } else {
-                        AstConcat* const concatp = new AstConcat(patp->fileline(), newp, valuep);
+                        AstConcat* const concatp
+                            = new AstConcat{patp->fileline(), VN_AS(newp, NodeExpr), valuep};
                         newp = concatp;
                         newp->dtypeSetLogicSized(concatp->lhsp()->width()
                                                      + concatp->rhsp()->width(),
@@ -3892,12 +3883,12 @@ private:
     void patternAssoc(AstPattern* nodep, AstAssocArrayDType* arrayDtp, AstPatMember* defaultp) {
         AstNode* defaultValuep = nullptr;
         if (defaultp) defaultValuep = defaultp->lhssp()->unlinkFrBack();
-        AstNode* newp = new AstConsAssoc(nodep->fileline(), defaultValuep);
+        AstNodeExpr* newp = new AstConsAssoc(nodep->fileline(), defaultValuep);
         newp->dtypeFrom(arrayDtp);
         for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
              patp = VN_AS(patp->nextp(), PatMember)) {
             patp->dtypep(arrayDtp->subDTypep());
-            AstNode* const valuep = patternMemberValueIterate(patp);
+            AstNodeExpr* const valuep = patternMemberValueIterate(patp);
             AstNode* const keyp = patp->keyp();
             auto* const newap
                 = new AstSetAssoc(nodep->fileline(), newp, keyp->unlinkFrBack(), valuep);
@@ -3917,7 +3908,7 @@ private:
         for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
              patp = VN_AS(patp->nextp(), PatMember)) {
             patp->dtypep(arrayDtp->subDTypep());
-            AstNode* const valuep = patternMemberValueIterate(patp);
+            AstNodeExpr* const valuep = patternMemberValueIterate(patp);
             AstNode* const keyp = patp->keyp();
             auto* const newap
                 = new AstSetWildcard{nodep->fileline(), newp, keyp->unlinkFrBack(), valuep};
@@ -3934,7 +3925,7 @@ private:
         for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
              patp = VN_AS(patp->nextp(), PatMember)) {
             patp->dtypep(arrayp->subDTypep());
-            AstNode* const valuep = patternMemberValueIterate(patp);
+            AstNodeExpr* const valuep = patternMemberValueIterate(patp);
             auto* const newap = new AstConsDynArray(nodep->fileline(), valuep, newp);
             newap->dtypeFrom(arrayp);
             newp = newap;
@@ -3949,7 +3940,7 @@ private:
         for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
              patp = VN_AS(patp->nextp(), PatMember)) {
             patp->dtypep(arrayp->subDTypep());
-            AstNode* const valuep = patternMemberValueIterate(patp);
+            AstNodeExpr* const valuep = patternMemberValueIterate(patp);
             auto* const newap = new AstConsQueue(nodep->fileline(), valuep, newp);
             newap->dtypeFrom(arrayp);
             newp = newap;
@@ -3963,7 +3954,7 @@ private:
         const VNumRange range = bdtypep->declRange();
         PatVecMap patmap = patVectorMap(nodep, range);
         UINFO(9, "ent " << range.hi() << " to " << range.lo() << endl);
-        AstNode* newp = nullptr;
+        AstNodeExpr* newp = nullptr;
         for (int ent = range.hi(); ent >= range.lo(); --ent) {
             AstPatMember* newpatp = nullptr;
             AstPatMember* patp = nullptr;
@@ -3983,7 +3974,7 @@ private:
                 // Determine initial values
                 vdtypep = nodep->findBitDType();
                 patp->dtypep(vdtypep);
-                AstNode* const valuep = patternMemberValueIterate(patp);
+                AstNodeExpr* const valuep = patternMemberValueIterate(patp);
                 {  // Packed. Convert to concat for now.
                     if (!newp) {
                         newp = valuep;
@@ -4007,15 +3998,15 @@ private:
         // if (debug() >= 9) newp->dumpTree("-apat-out: ");
         VL_DO_DANGLING(pushDeletep(nodep), nodep);  // Deletes defaultp also, if present
     }
-    AstNode* patternMemberValueIterate(AstPatMember* patp) {
+    AstNodeExpr* patternMemberValueIterate(AstPatMember* patp) {
         // Determine values - might be another InitArray
         userIterate(patp, WidthVP(patp->dtypep(), BOTH).p());
         // Convert to InitArray or constify immediately
-        AstNode* valuep = patp->lhssp()->unlinkFrBack();
+        AstNodeExpr* valuep = patp->lhssp()->unlinkFrBack();
         if (VN_IS(valuep, Const)) {
             // Forming a AstConcat will cause problems with
             // unsized (uncommitted sized) constants
-            if (AstNode* const newp
+            if (AstConst* const newp
                 = WidthCommitVisitor::newIfConstCommitSize(VN_AS(valuep, Const))) {
                 VL_DO_DANGLING(pushDeletep(valuep), valuep);
                 valuep = newp;
@@ -4179,7 +4170,7 @@ private:
         UASSERT_OBJ(loopsp, nodep, "No loop variables under foreach");
         // if (debug()) nodep->dumpTree(cout, "-foreach-old: ");
         userIterateAndNext(loopsp->fromp(), WidthVP(SELF, BOTH).p());
-        AstNode* const fromp = loopsp->fromp();
+        AstNodeExpr* const fromp = loopsp->fromp();
         UASSERT_OBJ(fromp->dtypep(), fromp, "Missing data type");
         AstNodeDType* fromDtp = fromp->dtypep()->skipRefp();
         // Split into for loop
@@ -4248,10 +4239,11 @@ private:
                     sizep->dtypeSetSigned32();
                     sizep->didWidth(true);
                     sizep->protect(false);
-                    AstNode* const condp
+                    AstNodeExpr* const condp
                         = new AstLt{fl, new AstVarRef{fl, varp, VAccess::READ}, sizep};
-                    AstNode* const incp = new AstAdd{fl, new AstConst{fl, AstConst::Signed32{}, 1},
-                                                     new AstVarRef{fl, varp, VAccess::READ}};
+                    AstNodeExpr* const incp
+                        = new AstAdd{fl, new AstConst{fl, AstConst::Signed32{}, 1},
+                                     new AstVarRef{fl, varp, VAccess::READ}};
                     loopp = createForeachLoop(nodep, bodyPointp, varp, leftp, condp, incp);
                 }
                 // Prep for next
@@ -4267,10 +4259,10 @@ private:
                 AstVar* const first_varp = new AstVar{
                     fl, VVarType::BLOCKTEMP, varp->name() + "__Vfirst", VFlagBitPacked{}, 1};
                 first_varp->usedLoopIdx(true);
-                AstNode* const firstp = new AstMethodCall{
+                AstNodeExpr* const firstp = new AstMethodCall{
                     fl, fromp->cloneTree(false), "first",
                     new AstArg{fl, "", new AstVarRef{fl, varp, VAccess::READWRITE}}};
-                AstNode* const nextp = new AstMethodCall{
+                AstNodeExpr* const nextp = new AstMethodCall{
                     fl, fromp->cloneTree(false), "next",
                     new AstArg{fl, "", new AstVarRef{fl, varp, VAccess::READWRITE}}};
                 AstNode* const first_clearp
@@ -4322,10 +4314,10 @@ private:
     AstNode* createForeachLoopRanged(AstForeach* nodep, AstNode* bodysp, AstVar* varp,
                                      const VNumRange& declRange) {
         FileLine* const fl = varp->fileline();
-        auto* const leftp = new AstConst{fl, AstConst::Signed32{}, declRange.left()};
-        auto* const rightp = new AstConst{fl, AstConst::Signed32{}, declRange.right()};
-        AstNode* condp;
-        AstNode* incp;
+        AstNodeExpr* const leftp = new AstConst{fl, AstConst::Signed32{}, declRange.left()};
+        AstNodeExpr* const rightp = new AstConst{fl, AstConst::Signed32{}, declRange.right()};
+        AstNodeExpr* condp;
+        AstNodeExpr* incp;
         if (declRange.left() < declRange.right()) {
             condp = new AstLte{fl, new AstVarRef{fl, varp, VAccess::READ}, rightp};
             incp = new AstAdd{fl, new AstConst{fl, AstConst::Signed32{}, 1},
@@ -4337,8 +4329,8 @@ private:
         }
         return createForeachLoop(nodep, bodysp, varp, leftp, condp, incp);
     }
-    AstNode* createForeachLoop(AstForeach* nodep, AstNode* bodysp, AstVar* varp, AstNode* leftp,
-                               AstNode* condp, AstNode* incp) {
+    AstNode* createForeachLoop(AstForeach* nodep, AstNode* bodysp, AstVar* varp,
+                               AstNodeExpr* leftp, AstNodeExpr* condp, AstNodeExpr* incp) {
         FileLine* const fl = varp->fileline();
         auto* const whilep = new AstWhile{
             fl, condp, bodysp, new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE}, incp}};
@@ -4454,7 +4446,7 @@ private:
         UINFO(9, "  Display in " << nodep->text() << endl);
         string newFormat;
         bool inPct = false;
-        AstNode* argp = nodep->exprsp();
+        AstNodeExpr* argp = nodep->exprsp();
         const string txt = nodep->text();
         string fmt;
         for (char ch : txt) {
@@ -4472,7 +4464,7 @@ private:
                 case 'l': break;  // %m - auto insert "library"
                 case 'd': {  // Convert decimal to either 'd' or '#'
                     if (argp) {
-                        AstNode* const nextp = argp->nextp();
+                        AstNodeExpr* const nextp = VN_AS(argp->nextp(), NodeExpr);
                         if (argp->isDouble()) {
                             spliceCvtS(argp, true, 64);
                             ch = '~';
@@ -4501,14 +4493,18 @@ private:
                         newFormat += "%@";
                         VNRelinker handle;
                         argp->unlinkFrBack(&handle);
-                        AstCExpr* const newp
-                            = new AstCExpr(nodep->fileline(), "VL_TO_STRING(", 0, true);
+                        FileLine* const flp = nodep->fileline();
+                        AstCExpr* const newp = new AstCExpr{flp, nullptr};
+                        newp->addExprsp(new AstText{flp, "VL_TO_STRING(", true});
                         newp->addExprsp(argp);
-                        newp->addExprsp(new AstText(nodep->fileline(), ")", true));
+                        newp->addExprsp(new AstText{flp, ")", true});
                         newp->dtypeSetString();
                         newp->pure(true);
                         newp->protect(false);
                         handle.relink(newp);
+                        // Set argp to what we replaced it with, as we will keep processing the
+                        // next argument.
+                        argp = newp;
                     } else {
                         added = true;
                         if (fmt == "%0") {
@@ -4517,19 +4513,19 @@ private:
                             newFormat += "%d";
                         }
                     }
-                    if (argp) argp = argp->nextp();
+                    if (argp) argp = VN_AS(argp->nextp(), NodeExpr);
                     break;
                 }
                 case 's': {  // Convert string to pack string
                     if (argp && argp->dtypep()->basicp()->isString()) {  // Convert it
                         ch = '@';
                     }
-                    if (argp) argp = argp->nextp();
+                    if (argp) argp = VN_AS(argp->nextp(), NodeExpr);
                     break;
                 }
                 case 't': {  // Convert decimal time to realtime
                     if (argp) {
-                        AstNode* const nextp = argp->nextp();
+                        AstNodeExpr* const nextp = VN_AS(argp->nextp(), NodeExpr);
                         if (argp->isDouble()) ch = '^';  // Convert it
                         if (nodep->timeunit().isNone()) {
                             nodep->v3fatalSrc("display %t has no time units");
@@ -4541,7 +4537,7 @@ private:
                 case 'f':  // FALLTHRU
                 case 'g': {
                     if (argp) {
-                        AstNode* const nextp = argp->nextp();
+                        AstNodeExpr* const nextp = VN_AS(argp->nextp(), NodeExpr);
                         if (!argp->isDouble()) {
                             iterateCheckReal(nodep, "Display argument", argp, BOTH);
                         }
@@ -4559,11 +4555,11 @@ private:
                     } else {
                         ch = nodep->missingArgChar();
                     }
-                    if (argp) argp = argp->nextp();
+                    if (argp) argp = VN_AS(argp->nextp(), NodeExpr);
                     break;
                 }
                 default: {  // Most operators, just move to next argument
-                    if (argp) argp = argp->nextp();
+                    if (argp) argp = VN_AS(argp->nextp(), NodeExpr);
                     break;
                 }
                 }  // switch
@@ -5124,7 +5120,7 @@ private:
             for (const auto& tconnect : tconnects) {
                 const AstVar* const portp = tconnect.first;
                 AstArg* const argp = tconnect.second;
-                AstNode* pinp = argp->exprp();
+                AstNodeExpr* pinp = argp->exprp();
                 if (!pinp) continue;  // Argument error we'll find later
                 // Prelim may cause the node to get replaced; we've lost our
                 // pointer, so need to iterate separately later
@@ -5133,11 +5129,10 @@ private:
                     UINFO(4, "   sformat via metacomment: " << nodep << endl);
                     VNRelinker handle;
                     argp->unlinkFrBackWithNext(&handle);  // Format + additional args, if any
-                    AstNode* argsp = nullptr;
+                    AstNodeExpr* argsp = nullptr;
                     while (AstArg* const nextargp = VN_AS(argp->nextp(), Arg)) {
-                        argsp = AstNode::addNext(
-                            argsp, nextargp->exprp()
-                                       ->unlinkFrBackWithNext());  // Expression goes to SFormatF
+                        // Expression goes to SFormatF
+                        argsp = argsp->addNext(nextargp->exprp()->unlinkFrBackWithNext());
                         nextargp->unlinkFrBack()->deleteTree();  // Remove the call's Arg wrapper
                     }
                     string format;
@@ -5167,7 +5162,7 @@ private:
                     UINFO(4, "   Add CvtPackString: " << pinp << endl);
                     VNRelinker handle;
                     pinp->unlinkFrBack(&handle);  // No next, that's the next pin
-                    AstNode* const newp = new AstCvtPackString(pinp->fileline(), pinp);
+                    AstNodeExpr* const newp = new AstCvtPackString(pinp->fileline(), pinp);
                     handle.relink(newp);
                     pinp = newp;
                 }
@@ -5181,7 +5176,7 @@ private:
             for (const auto& tconnect : tconnects) {
                 AstVar* const portp = tconnect.first;
                 const AstArg* const argp = tconnect.second;
-                AstNode* const pinp = argp->exprp();
+                AstNodeExpr* const pinp = argp->exprp();
                 if (!pinp) continue;  // Argument error we'll find later
                 // Change data types based on above accept completion
                 if (nodep->taskp()->dpiImport()) checkUnpackedArrayArgs(portp, pinp);
@@ -5194,7 +5189,7 @@ private:
             for (const auto& tconnect : tconnects) {
                 const AstVar* const portp = tconnect.first;
                 const AstArg* const argp = tconnect.second;
-                AstNode* const pinp = argp->exprp();
+                AstNodeExpr* const pinp = argp->exprp();
                 if (!pinp) continue;  // Argument error we'll find later
                 // Do PRELIM again, because above accept may have exited early
                 // due to node replacement
@@ -5827,7 +5822,7 @@ private:
         return false;
     }
 
-    void fixWidthExtend(AstNode* nodep, AstNodeDType* expDTypep, ExtendRule extendRule) {
+    void fixWidthExtend(AstNodeExpr* nodep, AstNodeDType* expDTypep, ExtendRule extendRule) {
         // Fix the width mismatch by extending or truncating bits
         // *ONLY* call this from checkWidth()
         // Truncation is rarer, but can occur:  parameter [3:0] FOO = 64'h12312;
@@ -5848,7 +5843,7 @@ private:
             V3Number num(nodep, expWidth);
             num.opAssign(constp->num());
             num.isSigned(false);
-            AstNode* const newp = new AstConst(nodep->fileline(), num);
+            AstNodeExpr* const newp = new AstConst(nodep->fileline(), num);
             constp->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(constp), constp);
             VL_DANGLING(nodep);
@@ -5857,7 +5852,7 @@ private:
             // Trunc - Extract
             VNRelinker linker;
             nodep->unlinkFrBack(&linker);
-            AstNode* const newp = new AstSel(nodep->fileline(), nodep, 0, expWidth);
+            AstNodeExpr* const newp = new AstSel(nodep->fileline(), nodep, 0, expWidth);
             newp->didWidth(true);  // Don't replace dtype with unsigned
             linker.relink(newp);
             nodep = newp;
@@ -5872,9 +5867,9 @@ private:
             case EXTEND_LHS: doSigned = nodep->isSigned(); break;
             default: nodep->v3fatalSrc("bad case");
             }
-            AstNode* const newp
-                = (doSigned ? static_cast<AstNode*>(new AstExtendS{nodep->fileline(), nodep})
-                            : static_cast<AstNode*>(new AstExtend{nodep->fileline(), nodep}));
+            AstNodeExpr* const newp
+                = (doSigned ? static_cast<AstNodeExpr*>(new AstExtendS{nodep->fileline(), nodep})
+                            : static_cast<AstNodeExpr*>(new AstExtend{nodep->fileline(), nodep}));
             linker.relink(newp);
             nodep = newp;
         }
@@ -5882,14 +5877,14 @@ private:
             // For AstVar init() among others
             // TODO do all to-real and to-integer conversions in this function
             // rather than in callers
-            AstNode* const newp = spliceCvtD(nodep);
+            AstNodeExpr* const newp = spliceCvtD(nodep);
             nodep = newp;
         }
         nodep->dtypeFrom(expDTypep);
         UINFO(4, "             _new: " << nodep << endl);
     }
 
-    void fixWidthReduce(AstNode* nodep) {
+    void fixWidthReduce(AstNodeExpr* nodep) {
         // Fix the width mismatch by adding a reduction OR operator
         // IF (A(CONSTwide)) becomes  IF (A(CONSTreduced))
         // IF (A(somewide))  becomes  IF (A(REDOR(somewide)))
@@ -5902,7 +5897,7 @@ private:
             V3Number num(nodep, expWidth);
             num.opRedOr(constp->num());
             num.isSigned(expSigned);
-            AstNode* const newp = new AstConst(nodep->fileline(), num);
+            AstNodeExpr* const newp = new AstConst(nodep->fileline(), num);
             constp->replaceWith(newp);
             VL_DO_DANGLING(constp->deleteTree(), constp);
             VL_DANGLING(nodep);
@@ -5910,7 +5905,7 @@ private:
         } else {
             VNRelinker linker;
             nodep->unlinkFrBack(&linker);
-            AstNode* const newp = new AstRedOr(nodep->fileline(), nodep);
+            AstNodeExpr* const newp = new AstRedOr(nodep->fileline(), nodep);
             linker.relink(newp);
             nodep = newp;
         }
@@ -5918,14 +5913,14 @@ private:
         UINFO(4, "             _new: " << nodep << endl);
     }
 
-    bool fixAutoExtend(AstNode*& nodepr, int expWidth) {
+    bool fixAutoExtend(AstNodeExpr*& nodepr, int expWidth) {
         // For SystemVerilog '0,'1,'x,'z, autoextend and don't warn
         if (AstConst* const constp = VN_CAST(nodepr, Const)) {
             if (constp->num().autoExtend() && !constp->num().sized() && constp->width() == 1) {
                 // Make it the proper size.  Careful of proper extension of 0's/1's
                 V3Number num(constp, expWidth);
                 num.opRepl(constp->num(), expWidth);  // {width{'1}}
-                AstNode* const newp = new AstConst(constp->fileline(), num);
+                AstNodeExpr* const newp = new AstConst(constp->fileline(), num);
                 // Spec says always unsigned with proper width
                 if (debug() > 4) constp->dumpTree(cout, "  fixAutoExtend_old: ");
                 if (debug() > 4) newp->dumpTree(cout, "               _new: ");
@@ -5943,7 +5938,7 @@ private:
                                           << expWidth << " bits: " << constp->prettyName());
                 V3Number num(constp, expWidth);
                 num.opExtendXZ(constp->num(), constp->width());
-                AstNode* const newp = new AstConst(constp->fileline(), num);
+                AstNodeExpr* const newp = new AstConst(constp->fileline(), num);
                 // Spec says always unsigned with proper width
                 if (debug() > 4) constp->dumpTree(cout, "  fixUnszExtend_old: ");
                 if (debug() > 4) newp->dumpTree(cout, "               _new: ");
@@ -6037,7 +6032,7 @@ private:
         if (stage & PRELIM) {
             underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, PRELIM).p());
         }
-        underp = checkCvtUS(underp);
+        underp = VN_IS(underp, NodeExpr) ? checkCvtUS(VN_AS(underp, NodeExpr)) : underp;
         AstNodeDType* const expDTypep = underp->dtypep();
         underp = iterateCheck(nodep, side, underp, SELF, FINAL, expDTypep, EXTEND_EXP);
         if (underp) {}  // cppcheck
@@ -6076,14 +6071,14 @@ private:
             VNRelinker linker;
             underp->unlinkFrBack(&linker);
             AstNode* const newp
-                = new AstNeqD(nodep->fileline(), underp,
+                = new AstNeqD(nodep->fileline(), VN_AS(underp, NodeExpr),
                               new AstConst(nodep->fileline(), AstConst::RealDouble(), 0.0));
             linker.relink(newp);
         } else if (VN_IS(underVDTypep, ClassRefDType)
                    || (VN_IS(underVDTypep, BasicDType)
                        && VN_AS(underVDTypep, BasicDType)->keyword() == VBasicDTypeKwd::CHANDLE)) {
             // Allow warning-free "if (handle)"
-            VL_DO_DANGLING(fixWidthReduce(underp), underp);  // Changed
+            VL_DO_DANGLING(fixWidthReduce(VN_AS(underp, NodeExpr)), underp);  // Changed
         } else if (!underVDTypep->basicp()) {
             nodep->v3error("Logical operator " << nodep->prettyTypeName()
                                                << " expects a non-complex data type on the "
@@ -6105,7 +6100,7 @@ private:
                                                      : "")
                                              << " bits.");
                 }
-                VL_DO_DANGLING(fixWidthReduce(underp), underp);  // Changed
+                VL_DO_DANGLING(fixWidthReduce(VN_AS(underp, NodeExpr)), underp);  // Changed
             }
         }
     }
@@ -6131,17 +6126,17 @@ private:
         } else if (expDTypep->isDouble() && !underp->isDouble()) {
             AstNode* const oldp
                 = underp;  // Need FINAL on children; otherwise splice would block it
-            underp = spliceCvtD(underp);
+            underp = spliceCvtD(VN_AS(underp, NodeExpr));
             underp = userIterateSubtreeReturnEdits(oldp, WidthVP(SELF, FINAL).p());
         } else if (!expDTypep->isDouble() && underp->isDouble()) {
             AstNode* const oldp
                 = underp;  // Need FINAL on children; otherwise splice would block it
-            underp = spliceCvtS(underp, true, expDTypep->width());  // Round RHS
+            underp = spliceCvtS(VN_AS(underp, NodeExpr), true, expDTypep->width());  // Round RHS
             underp = userIterateSubtreeReturnEdits(oldp, WidthVP(SELF, FINAL).p());
         } else if (expDTypep->isString() && !underp->dtypep()->isString()) {
             AstNode* const oldp
                 = underp;  // Need FINAL on children; otherwise splice would block it
-            underp = spliceCvtString(underp);
+            underp = spliceCvtString(VN_AS(underp, NodeExpr));
             underp = userIterateSubtreeReturnEdits(oldp, WidthVP(SELF, FINAL).p());
         } else {
             const AstBasicDType* const expBasicp = expDTypep->basicp();
@@ -6185,7 +6180,8 @@ private:
                 }
                 // Note the check uses the expected size, not the child's subDTypep as we want the
                 // child node's width to end up correct for the assignment (etc)
-                widthCheckSized(nodep, side, underp, expDTypep, extendRule, warnOn);
+                widthCheckSized(nodep, side, VN_AS(underp, NodeExpr), expDTypep, extendRule,
+                                warnOn);
             } else if (!VN_IS(expDTypep->skipRefp(), IfaceRefDType)
                        && VN_IS(underp->dtypep()->skipRefp(), IfaceRefDType)) {
                 underp->v3error(ucfirst(nodep->prettyOperatorName())
@@ -6226,9 +6222,10 @@ private:
         return underp;
     }
 
-    void widthCheckSized(AstNode* nodep, const char* side,
-                         AstNode* underp,  // Node to be checked or have typecast added in front of
-                         AstNodeDType* expDTypep, ExtendRule extendRule, bool warnOn = true) {
+    void
+    widthCheckSized(AstNode* nodep, const char* side,
+                    AstNodeExpr* underp,  // Node to be checked or have typecast added in front of
+                    AstNodeDType* expDTypep, ExtendRule extendRule, bool warnOn = true) {
         // Issue warnings on sized number width mismatches, then do appropriate size extension
         // Generally iterateCheck is what is wanted instead of this
         // UINFO(9,"wchk "<<side<<endl<<"  "<<nodep<<endl<<"  "<<underp<<endl<<"  e="<<expDTypep<<"
@@ -6305,7 +6302,7 @@ private:
     //----------------------------------------------------------------------
     // SIGNED/DOUBLE METHODS
 
-    AstNode* checkCvtUS(AstNode* nodep) {
+    AstNodeExpr* checkCvtUS(AstNodeExpr* nodep) {
         if (nodep && nodep->isDouble()) {
             nodep->v3error("Expected integral (non-" << nodep->dtypep()->prettyDTypeName()
                                                      << ") input to "
@@ -6315,14 +6312,14 @@ private:
         return nodep;
     }
 
-    AstNode* spliceCvtD(AstNode* nodep) {
+    AstNodeExpr* spliceCvtD(AstNodeExpr* nodep) {
         // For integer used in REAL context, convert to real
         // We don't warn here, "2.0 * 2" is common and reasonable
         if (nodep && !nodep->dtypep()->skipRefp()->isDouble()) {
             UINFO(6, "   spliceCvtD: " << nodep << endl);
             VNRelinker linker;
             nodep->unlinkFrBack(&linker);
-            AstNode* newp;
+            AstNodeExpr* newp;
             if (nodep->dtypep()->skipRefp()->isSigned()) {
                 newp = new AstISToRD(nodep->fileline(), nodep);
             } else {
@@ -6334,7 +6331,7 @@ private:
             return nodep;
         }
     }
-    AstNode* spliceCvtS(AstNode* nodep, bool warnOn, int width) {
+    AstNodeExpr* spliceCvtS(AstNodeExpr* nodep, bool warnOn, int width) {
         // IEEE-2012 11.8.1: Signed: Type coercion creates signed
         // 11.8.2: Argument to convert is self-determined
         if (nodep && nodep->dtypep()->skipRefp()->isDouble()) {
@@ -6352,7 +6349,7 @@ private:
                 }
             }
             if (warnOn) nodep->v3warn(REALCVT, "Implicit conversion of real to integer");
-            AstNode* const newp = new AstRToIRoundS(nodep->fileline(), nodep);
+            AstNodeExpr* const newp = new AstRToIRoundS(nodep->fileline(), nodep);
             linker.relink(newp);
             newp->dtypeSetBitSized(width, VSigning::SIGNED);
             return newp;
@@ -6360,14 +6357,14 @@ private:
             return nodep;
         }
     }
-    AstNode* spliceCvtString(AstNode* nodep) {
+    AstNodeExpr* spliceCvtString(AstNodeExpr* nodep) {
         // IEEE-2012 11.8.1: Signed: Type coercion creates signed
         // 11.8.2: Argument to convert is self-determined
         if (nodep && !(nodep->dtypep()->basicp() && nodep->dtypep()->basicp()->isString())) {
             UINFO(6, "   spliceCvtString: " << nodep << endl);
             VNRelinker linker;
             nodep->unlinkFrBack(&linker);
-            AstNode* const newp = new AstCvtPackString(nodep->fileline(), nodep);
+            AstNodeExpr* const newp = new AstCvtPackString(nodep->fileline(), nodep);
             linker.relink(newp);
             return newp;
         } else {
@@ -6393,8 +6390,8 @@ private:
         default: break;
         }
         FileLine* const fl = nodep->fileline();
-        AstNode* const lhsp = nodep->lhsp()->unlinkFrBack();
-        AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
+        AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
         AstNodeBiop* newp = nullptr;
         switch (nodep->type()) {
         case VNType::atGt: newp = new AstGtS(fl, lhsp, rhsp); break;
@@ -6428,8 +6425,8 @@ private:
         // Return new node or nullptr if nothing
         if (nodep->doubleFlavor()) return nullptr;
         FileLine* const fl = nodep->fileline();
-        AstNode* const lhsp = nodep->lhsp()->unlinkFrBack();
-        AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
+        AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
         AstNodeBiop* newp = nullptr;
         // No width change on output;...                // All below have bool or double outputs
         switch (nodep->type()) {
@@ -6467,8 +6464,8 @@ private:
         // Return new node or nullptr if nothing
         if (nodep->stringFlavor()) return nullptr;
         FileLine* const fl = nodep->fileline();
-        AstNode* const lhsp = nodep->lhsp()->unlinkFrBack();
-        AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
+        AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
         AstNodeBiop* newp = nullptr;
         // No width change on output;...                // All below have bool or double outputs
         switch (nodep->type()) {
@@ -6499,7 +6496,7 @@ private:
         // Return new node or nullptr if nothing
         if (nodep->doubleFlavor()) return nullptr;
         FileLine* const fl = nodep->fileline();
-        AstNode* const lhsp = nodep->lhsp()->unlinkFrBack();
+        AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
         AstNodeUniop* newp = nullptr;
         switch (nodep->type()) {
         case VNType::atNegate: newp = new AstNegateD(fl, lhsp); break;
@@ -6744,7 +6741,7 @@ private:
 
         // Find valid values and populate
         UASSERT_OBJ(nodep->itemsp(), nodep, "enum without items");
-        std::map<uint64_t, AstNode*> values;
+        std::map<uint64_t, AstNodeExpr*> values;
         {
             AstEnumItem* const firstp = nodep->itemsp();
             const AstEnumItem* prevp = firstp;  // Prev must start with last item
@@ -6942,7 +6939,7 @@ private:
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         }
     }
-    AstNode* newVarRefDollarUnit(AstVar* nodep) {
+    AstVarRef* newVarRefDollarUnit(AstVar* nodep) {
         AstVarRef* const varrefp = new AstVarRef{nodep->fileline(), nodep, VAccess::READ};
         varrefp->classOrPackagep(v3Global.rootp()->dollarUnitPkgAddp());
         return varrefp;
diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp
index 4b02ad87d..42bed398f 100644
--- a/src/V3WidthSel.cpp
+++ b/src/V3WidthSel.cpp
@@ -116,7 +116,7 @@ private:
         return FromData(errp, ddtypep, fromRange);
     }
 
-    AstNode* newSubNeg(AstNode* lhsp, int32_t rhs) {
+    AstNodeExpr* newSubNeg(AstNodeExpr* lhsp, int32_t rhs) {
         // Return lhs-rhs, but if rhs is negative use an add, so we won't
         // have to deal with signed math and related 32bit sign extension problems
         if (rhs == 0) {
@@ -126,17 +126,16 @@ private:
             V3Number num(lhsp, lhsp->width());
             num.opSub(VN_AS(lhsp, Const)->num(), V3Number(lhsp, 32, rhs));
             num.isSigned(lhsp->isSigned());
-            AstNode* const newp = new AstConst(lhsp->fileline(), num);
-            return newp;
+            return new AstConst(lhsp->fileline(), num);
         } else if (rhs > 0) {
-            AstNode* const newp
+            AstNodeExpr* const newp
                 = new AstSub(lhsp->fileline(), lhsp,
                              new AstConst(lhsp->fileline(), AstConst::Unsized32(), rhs));
             // We must make sure sub gets sign of original value, not from the constant
             newp->dtypeFrom(lhsp);
             return newp;
         } else {  // rhs < 0;
-            AstNode* const newp
+            AstNodeExpr* const newp
                 = new AstAdd(lhsp->fileline(), lhsp,
                              new AstConst(lhsp->fileline(), AstConst::Unsized32(), -rhs));
             // We must make sure sub gets sign of original value, not from the constant
@@ -144,16 +143,16 @@ private:
             return newp;
         }
     }
-    AstNode* newSubNeg(int32_t lhs, AstNode* rhsp) {
+    AstNodeExpr* newSubNeg(int32_t lhs, AstNodeExpr* rhsp) {
         // Return lhs-rhs
         // We must make sure sub gets sign of original value
-        AstNode* const newp = new AstSub(
+        AstNodeExpr* const newp = new AstSub(
             rhsp->fileline(), new AstConst(rhsp->fileline(), AstConst::Unsized32(), lhs), rhsp);
         newp->dtypeFrom(rhsp);  // Important as AstSub default is lhs's sign
         return newp;
     }
 
-    AstNode* newSubLsbOf(AstNode* underp, const VNumRange& fromRange) {
+    AstNodeExpr* newSubLsbOf(AstNodeExpr* underp, const VNumRange& fromRange) {
         // Account for a variable's LSB in bit selections
         // Will likely become SUB(underp, lsb_of_signal).
         // Don't report WIDTH warnings etc here, as may be inside a
@@ -165,12 +164,10 @@ private:
         } else {
             if (fromRange.littleEndian()) {
                 // reg [1:3] was swapped to [3:1] (lsbEndianedp==3) and needs a SUB(3,under)
-                AstNode* const newp = newSubNeg(fromRange.hi(), underp);
-                return newp;
+                return newSubNeg(fromRange.hi(), underp);
             } else {
                 // reg [3:1] needs a SUB(under,1)
-                AstNode* const newp = newSubNeg(underp, fromRange.lo());
-                return newp;
+                return newSubNeg(underp, fromRange.lo());
             }
         }
     }
@@ -209,8 +206,8 @@ private:
         UINFO(6, "SELBIT " << nodep << endl);
         if (debug() >= 9) nodep->backp()->dumpTree(cout, "--SELBT0: ");
         // lhsp/rhsp do not need to be constant
-        AstNode* const fromp = nodep->fromp()->unlinkFrBack();
-        AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();  // bit we're extracting
+        AstNodeExpr* const fromp = nodep->fromp()->unlinkFrBack();
+        AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();  // bit we're extracting
         if (debug() >= 9) nodep->dumpTree(cout, "--SELBT2: ");
         const FromData fromdata = fromDataForArray(nodep, fromp);
         AstNodeDType* const ddtypep = fromdata.m_dtypep;
@@ -218,7 +215,7 @@ private:
         UINFO(6, "  ddtypep " << ddtypep << endl);
         if (const AstUnpackArrayDType* const adtypep = VN_CAST(ddtypep, UnpackArrayDType)) {
             // SELBIT(array, index) -> ARRAYSEL(array, index)
-            AstNode* subp = rhsp;
+            AstNodeExpr* subp = rhsp;
             if (fromRange.lo() != 0 || fromRange.hi() < 0) {
                 subp = newSubNeg(subp, fromRange.lo());
             }
@@ -229,7 +226,7 @@ private:
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (const AstPackArrayDType* const adtypep = VN_CAST(ddtypep, PackArrayDType)) {
             // SELBIT(array, index) -> SEL(array, index*width-of-subindex, width-of-subindex)
-            AstNode* subp = rhsp;
+            AstNodeExpr* subp = rhsp;
             if (fromRange.littleEndian()) {
                 subp = newSubNeg(fromRange.hi(), subp);
             } else {
@@ -253,7 +250,7 @@ private:
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (const AstAssocArrayDType* const adtypep = VN_CAST(ddtypep, AssocArrayDType)) {
             // SELBIT(array, index) -> ASSOCSEL(array, index)
-            AstNode* const subp = rhsp;
+            AstNodeExpr* const subp = rhsp;
             AstAssocSel* const newp = new AstAssocSel(nodep->fileline(), fromp, subp);
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off array reference
             if (debug() >= 9) newp->dumpTree(cout, "--SELBTn: ");
@@ -262,7 +259,7 @@ private:
         } else if (const AstWildcardArrayDType* const adtypep
                    = VN_CAST(ddtypep, WildcardArrayDType)) {
             // SELBIT(array, index) -> WILDCARDSEL(array, index)
-            AstNode* const subp = rhsp;
+            AstNodeExpr* const subp = rhsp;
             AstWildcardSel* const newp = new AstWildcardSel{nodep->fileline(), fromp, subp};
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off array reference
             if (debug() >= 9) newp->dumpTree(cout, "--SELBTn: ");
@@ -270,7 +267,7 @@ private:
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (const AstDynArrayDType* const adtypep = VN_CAST(ddtypep, DynArrayDType)) {
             // SELBIT(array, index) -> CMETHODCALL(queue, "at", index)
-            AstNode* const subp = rhsp;
+            AstNodeExpr* const subp = rhsp;
             AstCMethodHard* const newp = new AstCMethodHard(nodep->fileline(), fromp, "at", subp);
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off queue reference
             if (debug() >= 9) newp->dumpTree(cout, "--SELBTq: ");
@@ -278,7 +275,7 @@ private:
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (const AstQueueDType* const adtypep = VN_CAST(ddtypep, QueueDType)) {
             // SELBIT(array, index) -> CMETHODCALL(queue, "at", index)
-            AstNode* const subp = rhsp;
+            AstNodeExpr* const subp = rhsp;
             AstCMethodHard* const newp = new AstCMethodHard(nodep->fileline(), fromp, "at", subp);
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off queue reference
             if (debug() >= 9) newp->dumpTree(cout, "--SELBTq: ");
@@ -291,7 +288,7 @@ private:
                 nodep->v3warn(E_UNSUPPORTED,
                               "Unsupported: String array operation on non-variable");
             }
-            AstNode* newp;
+            AstNodeExpr* newp;
             if (varrefp && varrefp->access().isReadOnly()) {
                 newp = new AstGetcN(nodep->fileline(), fromp, rhsp);
             } else {
@@ -345,9 +342,9 @@ private:
                                "First value of [a:b] isn't a constant, maybe you want +: or -:");
         checkConstantOrReplace(nodep->rightp(),
                                "Second value of [a:b] isn't a constant, maybe you want +: or -:");
-        AstNode* const fromp = nodep->fromp()->unlinkFrBack();
-        AstNode* const msbp = nodep->rhsp()->unlinkFrBack();
-        AstNode* const lsbp = nodep->thsp()->unlinkFrBack();
+        AstNodeExpr* const fromp = nodep->fromp()->unlinkFrBack();
+        AstNodeExpr* const msbp = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* const lsbp = nodep->thsp()->unlinkFrBack();
         int32_t msb = VN_AS(msbp, Const)->toSInt();
         int32_t lsb = VN_AS(lsbp, Const)->toSInt();
         const int32_t elem = (msb > lsb) ? (msb - lsb + 1) : (lsb - msb + 1);
@@ -424,7 +421,7 @@ private:
                 msb = lsb;
                 lsb = x;
             }
-            AstNode* const widthp
+            AstNodeExpr* const widthp
                 = new AstConst(msbp->fileline(),
                                AstConst::Unsized32(),  // Unsized so width from user
                                msb + 1 - lsb);
@@ -447,7 +444,7 @@ private:
                 msb = lsb;
                 lsb = x;
             }
-            AstNode* const widthp
+            AstNodeExpr* const widthp
                 = new AstConst(msbp->fileline(),
                                AstConst::Unsized32(),  // Unsized so width from user
                                msb + 1 - lsb);
@@ -493,9 +490,9 @@ private:
         checkConstantOrReplace(nodep->thsp(), "Width of :+ or :- bit extract isn't a constant");
         if (debug() >= 9) nodep->dumpTree(cout, "--SELPM3: ");
         // Now replace it with an AstSel
-        AstNode* const fromp = nodep->fromp()->unlinkFrBack();
-        AstNode* const rhsp = nodep->rhsp()->unlinkFrBack();
-        AstNode* const widthp = nodep->thsp()->unlinkFrBack();
+        AstNodeExpr* const fromp = nodep->fromp()->unlinkFrBack();
+        AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
+        AstNodeExpr* const widthp = nodep->thsp()->unlinkFrBack();
         warnTri(rhsp);
         const int width = VN_AS(widthp, Const)->toSInt();
         if (width > (1 << 28)) {
@@ -536,13 +533,13 @@ private:
                    || (VN_IS(ddtypep, NodeUOrStructDType)
                        && VN_AS(ddtypep, NodeUOrStructDType)->packedUnsup())) {
             int elwidth = 1;
-            AstNode* newwidthp = widthp;
+            AstNodeExpr* newwidthp = widthp;
             if (const AstPackArrayDType* const adtypep = VN_CAST(ddtypep, PackArrayDType)) {
                 elwidth = adtypep->width() / fromRange.elements();
                 newwidthp
                     = new AstConst(nodep->fileline(), AstConst::Unsized32(), width * elwidth);
             }
-            AstNode* newlsbp = nullptr;
+            AstNodeExpr* newlsbp = nullptr;
             if (VN_IS(nodep, SelPlus)) {
                 if (fromRange.littleEndian()) {
                     // SELPLUS(from,lsb,width) -> SEL(from, (vector_msb-width+1)-sel, width)
diff --git a/src/astgen b/src/astgen
index acbb4575e..6d656117f 100755
--- a/src/astgen
+++ b/src/astgen
@@ -425,9 +425,10 @@ class Cpt:
                               key=lambda val: self._exec_syms[val]):
                 argnp = self._exec_syms[sym]
                 arg = self.add_nodep(sym)
-                out += "AstNode* " + argnp + " = " + arg + "->unlinkFrBack();\n"
+                out += "AstNodeExpr* " + argnp + " = " + arg + "->unlinkFrBack();\n"
 
-            out += "AstNode* newp = " + self._exec_new_recurse(aref) + ";\n"
+            out += "AstNodeExpr* newp = " + self._exec_new_recurse(
+                aref) + ";\n"
             out += "nodep->replaceWith(newp);"
             out += "VL_DO_DANGLING(nodep->deleteTree(), nodep);"
         elif func == "NEVER":
@@ -918,12 +919,18 @@ def write_ast_macros(filename):
         for node in AstNodeList:
             fh.write("#define ASTGEN_MEMBERS_Ast{t} \\\n".format(t=node.name))
             emitBlock('''\
-            static Ast{t}* cloneTreeNull(Ast{t}* nodep, bool cloneNextLink) {{
-                return nodep ? nodep->cloneTree(cloneNextLink) : nullptr;
+            Ast{t}* unlinkFrBack(VNRelinker* linkerp = nullptr) {{
+                return static_cast<Ast{t}*>(AstNode::unlinkFrBack(linkerp));
+            }}
+            Ast{t}* unlinkFrBackWithNext(VNRelinker* linkerp = nullptr) {{
+                return static_cast<Ast{t}*>(AstNode::unlinkFrBackWithNext(linkerp));
             }}
             Ast{t}* cloneTree(bool cloneNext) {{
                 return static_cast<Ast{t}*>(AstNode::cloneTree(cloneNext));
             }}
+            static Ast{t}* cloneTreeNull(Ast{t}* nodep, bool cloneNextLink) {{
+                return nodep ? nodep->cloneTree(cloneNextLink) : nullptr;
+            }}
             Ast{t}* clonep() const VL_MT_SAFE {{ return static_cast<Ast{t}*>(AstNode::clonep()); }}
             Ast{t}* addNext(Ast{t}* nodep) {{ return static_cast<Ast{t}*>(AstNode::addNext(this, nodep)); }}
             ''',
diff --git a/src/verilog.y b/src/verilog.y
index 930683c25..3958341cc 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -112,7 +112,7 @@ public:
     }
 
     // METHODS
-    AstArg* argWrapList(AstNode* nodep);
+    AstArg* argWrapList(AstNodeExpr* nodep);
     bool allTracingOn(FileLine* fl) {
         return v3Global.opt.trace() && m_tracingParse && fl->tracingOn();
     }
@@ -155,7 +155,7 @@ public:
         AstNode::addNext<AstNode, AstNode>(nodep, new AstStop(fileline, true));
         return nodep;
     }
-    AstNode* createGatePin(AstNode* exprp) {
+    AstNodeExpr* createGatePin(AstNodeExpr* exprp) {
         AstRange* const rangep = m_gateRangep;
         if (!rangep) {
             return exprp;
@@ -2238,7 +2238,7 @@ enumNameRangeE<rangep>:          // IEEE: second part of enum_name_declaration
                         { $$ = new AstRange{$1, $2, $4}; }
         ;
 
-enumNameStartE<nodep>:          // IEEE: third part of enum_name_declaration
+enumNameStartE<nodeExprp>:      // IEEE: third part of enum_name_declaration
                 /* empty */                             { $$ = nullptr; }
         |       '=' constExpr                           { $$ = $2; }
         ;
@@ -2790,7 +2790,7 @@ delay_control<delayp>:   //== IEEE: delay_control
                         { $$ = new AstDelay{$<fl>1, $3}; RISEFALLDLYUNSUP($3); DEL($5); DEL($7); }
         ;
 
-delay_value<nodep>:             // ==IEEE:delay_value
+delay_value<nodeExprp>:         // ==IEEE:delay_value
         //                      // IEEE: ps_identifier
                 packageClassScopeE varRefBase           { $$ = AstDot::newIfPkg($<fl>2, $1, $2); }
         |       yaINTNUM                                { $$ = new AstConst($<fl>1, *$1); }
@@ -2798,11 +2798,11 @@ delay_value<nodep>:             // ==IEEE:delay_value
         |       timeNumAdjusted                         { $$ = $1; }
         ;
 
-delayExpr<nodep>:
+delayExpr<nodeExprp>:
                 expr                                    { $$ = $1; }
         ;
 
-minTypMax<nodep>:               // IEEE: mintypmax_expression and constant_mintypmax_expression
+minTypMax<nodeExprp>:           // IEEE: mintypmax_expression and constant_mintypmax_expression
                 delayExpr                               { $$ = $1; }
         |       delayExpr ':' delayExpr ':' delayExpr   { $$ = $3; MINTYPMAXDLYUNSUP($3); DEL($1); DEL($5); }
         ;
@@ -3312,20 +3312,24 @@ statement_item<nodep>:          // IEEE: statement_item
                           FileLine* const newfl = new FileLine{$$->fileline()};
                           newfl->warnOff(V3ErrorCode::IGNOREDRETURN, true);
                           $$->fileline(newfl);
-                          if (AstNodeExpr* const exprp = VN_CAST($$, NodeExpr)) $$ = exprp->makeStmt(); }
+                          $$ = VN_AS($$, NodeExpr)->makeStmt(); }
         |       yVOID yP_TICK '(' expr '.' task_subroutine_callNoMethod ')' ';'
                         { $$ = new AstDot{$5, false, $4, $6};
                           FileLine* const newfl = new FileLine{$6->fileline()};
                           newfl->warnOff(V3ErrorCode::IGNOREDRETURN, true);
                           $6->fileline(newfl);
-                          if (AstNodeExpr* const exprp = VN_CAST($$, NodeExpr)) $$ = exprp->makeStmt(); }
+                          $$ = VN_AS($$, NodeExpr)->makeStmt(); }
+        |       yVOID yP_TICK '(' system_t_call ')' ';'
+                        { $$ = $4;
+                          FileLine* const newfl = new FileLine{$$->fileline()};
+                          newfl->warnOff(V3ErrorCode::IGNOREDRETURN, true);
+                          $$->fileline(newfl); }
         //                      // Expr included here to resolve our not knowing what is a method call
         //                      // Expr here must result in a subroutine_call
-        |       task_subroutine_callNoMethod ';'
-                        { $$ = $1;
-                          if (AstNodeExpr* const exprp = VN_CAST($$, NodeExpr)) $$ = exprp->makeStmt(); }
+        |       task_subroutine_callNoMethod ';'        { $$ = $1->makeStmt(); }
         //UNSUP fexpr '.' array_methodNoRoot ';'        { UNSUP }
         |       fexpr '.' task_subroutine_callNoMethod ';'      { $$ = (new AstDot{$<fl>2, false, $1, $3})->makeStmt(); }
+        |       system_t_call ';'                       { $$ = $1; }
         //UNSUP fexprScope ';'                          { UNSUP }
         //                      // Not here in IEEE; from class_constructor_declaration
         //                      // Because we've joined class_constructor_declaration into generic functions
@@ -3496,14 +3500,14 @@ finc_or_dec_expression<nodeExprp>:  // ==IEEE: inc_or_dec_expression
 //UNSUP         BISONPRE_COPY(inc_or_dec_expression,{s/~l~/pev_/g})     // {copied}
 //UNSUP ;
 
-class_new<nodep>:               // ==IEEE: class_new
+class_new<nodeExprp>:           // ==IEEE: class_new
         //                      // Special precence so (...) doesn't match expr
                 yNEW__ETC                               { $$ = new AstNew($1,  nullptr); }
         |       yNEW__ETC expr                          { $$ = new AstNewCopy($1, $2); }
         |       yNEW__PAREN '(' list_of_argumentsE ')'  { $$ = new AstNew($1, $3); }
         ;
 
-dynamic_array_new<nodep>:       // ==IEEE: dynamic_array_new
+dynamic_array_new<nodeExprp>:   // ==IEEE: dynamic_array_new
                 yNEW__ETC '[' expr ']'                  { $$ = new AstNewDynamic($1, $3, nullptr); }
         |       yNEW__ETC '[' expr ']' '(' expr ')'     { $$ = new AstNewDynamic($1, $3, $6); }
         ;
@@ -3569,16 +3573,16 @@ rand_case_itemList<caseItemp>:       // IEEE: { rand_case_item + ... }
         |       rand_case_itemList expr colon stmtBlock         { $$ = $1->addNext(new AstCaseItem{$3, $2, $4}); }
         ;
 
-open_range_list<nodep>:         // ==IEEE: open_range_list + open_value_range
+open_range_list<nodeExprp>:     // ==IEEE: open_range_list + open_value_range
                 open_value_range                        { $$ = $1; }
         |       open_range_list ',' open_value_range    { $$ = $1->addNext($3); }
         ;
 
-open_value_range<nodep>:        // ==IEEE: open_value_range
+open_value_range<nodeExprp>:    // ==IEEE: open_value_range
                 value_range                             { $$ = $1; }
         ;
 
-value_range<nodep>:             // ==IEEE: value_range
+value_range<nodeExprp>:         // ==IEEE: value_range
                 expr                                    { $$ = $1; }
         |       '[' expr ':' expr ']'                   { $$ = new AstInsideRange($1, $2, $4); }
         ;
@@ -3588,7 +3592,7 @@ value_range<nodep>:             // ==IEEE: value_range
 //UNSUP |       '[' cgexpr ':' cgexpr ']'               { }
 //UNSUP ;
 
-caseCondList<nodep>:            // IEEE: part of case_item
+caseCondList<nodeExprp>:        // IEEE: part of case_item
                 expr                                    { $$ = $1; }
         |       caseCondList ',' expr                   { $$ = $1->addNext($3); }
         ;
@@ -3752,14 +3756,13 @@ funcRef<nodeExprp>:             // IEEE: part of tf_call
         //UNSUP: idDotted is really just id to allow dotted method calls
         ;
 
-task_subroutine_callNoMethod<nodep>:    // function_subroutine_callNoMethod (as task)
+task_subroutine_callNoMethod<nodeExprp>:    // function_subroutine_callNoMethod (as task)
         //                      // IEEE: tf_call
                 taskRef                                 { $$ = $1; }
         //                      // funcref below not task ref to avoid conflict, must later handle either
         |       funcRef yWITH__PAREN '(' expr ')'       { $$ = new AstWithParse{$2, $1, $4}; }
         //                      // can call as method and yWITH without parenthesis
         |       id yWITH__PAREN '(' expr ')'            { $$ = new AstWithParse{$2, new AstFuncRef{$<fl>1, *$1, nullptr}, $4}; }
-        |       system_t_call                           { $$ = $1; }
         //                      // IEEE: method_call requires a "." so is in expr
         //                      // IEEE: ['std::'] not needed, as normal std package resolution will find it
         //                      // IEEE: randomize_call
@@ -3785,9 +3788,11 @@ function_subroutine_callNoMethod<nodeExprp>:        // IEEE: function_subroutine
         |       funcRef yWITH__CUR '{' '}'              { $$ = new AstWithParse{$2, $1, nullptr}; }
         ;
 
-system_t_call<nodep>:           // IEEE: system_tf_call (as task)
+system_t_call<nodeStmtp>:       // IEEE: system_tf_call (as task)
         //
-                yaD_PLI systemDpiArgsE                  { $$ = new AstTaskRef($<fl>1, *$1, $2); VN_CAST($$, TaskRef)->pli(true); }
+                yaD_PLI systemDpiArgsE                  { AstTaskRef* const refp = new AstTaskRef{$<fl>1, *$1, $2};
+                                                          refp->pli(true);
+                                                          $$ = refp->makeStmt(); }
         //
         |       yD_DUMPPORTS '(' idDotted ',' expr ')'  { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::FILE, $5); DEL($3);
                                                           $$->addNext(new AstDumpCtl($<fl>1, VDumpCtlType::VARS,
@@ -3928,7 +3933,7 @@ system_f_call<nodeExprp>:           // IEEE: system_tf_call (as func)
         |       system_f_call_or_t                      { $$ = $1; }
         ;
 
-systemDpiArgsE<nodep>:          // IEEE: part of system_if_call for aruments of $dpi call
+systemDpiArgsE<argp>:           // IEEE: part of system_if_call for aruments of $dpi call
                 parenE                                  { $$ = nullptr; }
         |       '(' exprList ')'                        { $$ = GRAMMARP->argWrapList($2); }
         ;
@@ -4088,7 +4093,7 @@ exprOrDataType<nodep>:          // expr | data_type: combined to prevent conflic
 //UNSUP |       exprOrDataTypeList ',' exprOrDataType   { $$ = addNextNull($1, $3); }
 //UNSUP ;
 
-list_of_argumentsE<nodep>:      // IEEE: [list_of_arguments]
+list_of_argumentsE<nodeExprp>:  // IEEE: [list_of_arguments]
                 argsDottedList                          { $$ = $1; }
         |       argsExprListE
                         { if (VN_IS($1, Arg) && VN_CAST($1, Arg)->emptyConnectNoNext()) {
@@ -4325,7 +4330,7 @@ array_methodNoRoot<nodeFTaskRefp>:
         |       yUNIQUE                                 { $$ = new AstFuncRef($1, "unique", nullptr); }
         ;
 
-array_methodWith<nodep>:
+array_methodWith<nodeExprp>:
                 array_methodNoRoot parenE               { $$ = $1; }
         |       array_methodNoRoot parenE yWITH__PAREN '(' expr ')'
                         { $$ = new AstWithParse{$3, $1, $5}; }
@@ -4390,7 +4395,7 @@ dpi_tf_TraceInitE<cbool>:       // Verilator extension
 // ~p~ means this is a (p)arenthetized expression
 //     it will get replaced by "", or "s"equence
 
-exprEqE<nodep>:                 // IEEE: optional '=' expression (part of param_assignment)
+exprEqE<nodeExprp>:             // IEEE: optional '=' expression (part of param_assignment)
         //                      // constant_param_expression: '$' is in expr
                 /*empty*/                               { $$ = nullptr; }
         |       '=' expr                                { $$ = $2; }
@@ -4766,12 +4771,12 @@ commaVRDListE<nodep>:
         |       ',' vrdList                             { $$ = $2; }
         ;
 
-argsExprList<nodep>:            // IEEE: part of list_of_arguments (used where ,, isn't legal)
+argsExprList<nodeExprp>:        // IEEE: part of list_of_arguments (used where ,, isn't legal)
                 expr                                    { $$ = $1; }
         |       argsExprList ',' expr                   { $$ = $1->addNext($3); }
         ;
 
-argsExprListE<nodep>:           // IEEE: part of list_of_arguments
+argsExprListE<nodeExprp>:       // IEEE: part of list_of_arguments
                 argsExprOneE                            { $$ = $1; }
         |       argsExprListE ',' argsExprOneE          { $$ = $1->addNext($3); }
         ;
@@ -4781,7 +4786,7 @@ argsExprListE<nodep>:           // IEEE: part of list_of_arguments
 //UNSUP |       pev_argsExprListE ',' pev_argsExprOneE  { $$ = addNextNull($1, $3); }
 //UNSUP ;
 
-argsExprOneE<nodep>:            // IEEE: part of list_of_arguments
+argsExprOneE<nodeExprp>:        // IEEE: part of list_of_arguments
                 /*empty*/                               { $$ = new AstArg(CRELINE(), "", nullptr); }
         |       expr                                    { $$ = new AstArg($1->fileline(), "", $1); }
         ;
@@ -4791,7 +4796,7 @@ argsExprOneE<nodep>:            // IEEE: part of list_of_arguments
 //UNSUP |       pev_expr                                { $$ = $1; }
 //UNSUP ;
 
-argsDottedList<nodep>:          // IEEE: part of list_of_arguments
+argsDottedList<nodeExprp>:      // IEEE: part of list_of_arguments
                 argsDotted                              { $$ = $1; }
         |       argsDottedList ',' argsDotted           { $$ = addNextNull($1, $3); }
         ;
@@ -4801,7 +4806,7 @@ argsDottedList<nodep>:          // IEEE: part of list_of_arguments
 //UNSUP |       pev_argsDottedList ',' pev_argsDotted   { $$ = addNextNull($1, $3); }
 //UNSUP ;
 
-argsDotted<nodep>:              // IEEE: part of list_of_arguments
+argsDotted<nodeExprp>:          // IEEE: part of list_of_arguments
                 '.' idAny '(' ')'                       { $$ = new AstArg($<fl>2, *$2, nullptr); }
         |       '.' idAny '(' expr ')'                  { $$ = new AstArg($<fl>2, *$2, $4); }
         ;
@@ -4811,7 +4816,7 @@ argsDotted<nodep>:              // IEEE: part of list_of_arguments
 //UNSUP |       '.' idAny '(' pev_expr ')'              { $$ = new AstArg($<fl>2, *$2, $4); }
 //UNSUP ;
 
-streaming_concatenation<nodeExprp>: // ==IEEE: streaming_concatenation
+streaming_concatenation<nodeStreamp>: // ==IEEE: streaming_concatenation
         //                      // Need to disambiguate {<< expr-{ ... expr-} stream_concat }
         //                      // From                 {<< stream-{ ... stream-} }
         //                      // Likewise simple_type's idScoped from constExpr's idScope
@@ -4824,12 +4829,16 @@ streaming_concatenation<nodeExprp>: // ==IEEE: streaming_concatenation
         |       '{' yP_SRIGHT stream_concatenation '}'
                         { $$ = new AstStreamR($2, $3, new AstConst($2, 1)); }
         |       '{' yP_SLEFT  stream_expressionOrDataType stream_concatenation '}'
-                        { $$ = new AstStreamL($2, $4, $3); }
+                        { AstNodeExpr* const bitsp = VN_IS($3, NodeExpr) ? VN_AS($3, NodeExpr)
+                                                                         : new AstAttrOf{$1, VAttrType::DIM_BITS, $3};
+                          $$ = new AstStreamL($2, $4, bitsp); }
         |       '{' yP_SRIGHT stream_expressionOrDataType stream_concatenation '}'
-                        { $$ = new AstStreamR($2, $4, $3); }
+                        { AstNodeExpr* const bitsp = VN_IS($3, NodeExpr) ? VN_AS($3, NodeExpr)
+                                                                          : new AstAttrOf{$1, VAttrType::DIM_BITS, $3};
+                          $$ = new AstStreamR($2, $4, bitsp); }
         ;
 
-stream_concatenation<nodep>:    // ==IEEE: stream_concatenation
+stream_concatenation<nodeExprp>:    // ==IEEE: stream_concatenation
         //                      // '{' { stream_expression } '}'
                 '{' cateList '}'                        { $$ = $2; }
         ;
@@ -5017,24 +5026,24 @@ gateFront<nodep>:
         |       gateRangeE '('                          { $$ = $1; $<fl>$ = $<fl>2; }
         ;
 
-gateAndPinList<nodep>:
+gateAndPinList<nodeExprp>:
                 gatePinExpr                             { $$ = $1; }
         |       gateAndPinList ',' gatePinExpr          { $$ = new AstAnd($2,$1,$3); }
         ;
-gateOrPinList<nodep>:
+gateOrPinList<nodeExprp>:
                 gatePinExpr                             { $$ = $1; }
         |       gateOrPinList ',' gatePinExpr           { $$ = new AstOr($2,$1,$3); }
         ;
-gateXorPinList<nodep>:
+gateXorPinList<nodeExprp>:
                 gatePinExpr                             { $$ = $1; }
         |       gateXorPinList ',' gatePinExpr          { $$ = new AstXor($2,$1,$3); }
         ;
-gateUnsupPinList<nodep>:
+gateUnsupPinList<nodeExprp>:
                 gatePinExpr                             { $$ = $1; }
         |       gateUnsupPinList ',' gatePinExpr        { $$ = $1->addNext($3); }
         ;
 
-gatePinExpr<nodep>:
+gatePinExpr<nodeExprp>:
                 expr                                    { $$ = GRAMMARP->createGatePin($1); }
         ;
 
@@ -5188,7 +5197,7 @@ idClassSel<nodeExprp>:                      // Misc Ref to dotted, and/or arraye
         |       packageClassScope idDotted              { $$ = new AstDot($<fl>2, true, $1, $2); }
         ;
 
-idClassSelForeach<nodep>:
+idClassSelForeach<nodeExprp>:
                 idDottedForeach                         { $$ = $1; }
         //                      // IEEE: [ implicit_class_handle . | package_scope ] hierarchical_variable_identifier select
         |       yTHIS '.' idDottedForeach
@@ -5206,7 +5215,7 @@ idDotted<nodeExprp>:
         |       idDottedMore                            { $$ = $1; }
         ;
 
-idDottedForeach<nodep>:
+idDottedForeach<nodeExprp>:
                 yD_ROOT '.' idDottedMoreForeach
                         { $$ = new AstDot($2, false, new AstParseRef($<fl>1, VParseRefExp::PX_ROOT, "$root"), $3); }
         |       idDottedMoreForeach                     { $$ = $1; }
@@ -5217,7 +5226,7 @@ idDottedMore<nodeExprp>:
         |       idDottedMore '.' idArrayed              { $$ = new AstDot($2, false, $1, $3); }
         ;
 
-idDottedMoreForeach<nodep>:
+idDottedMoreForeach<nodeExprp>:
                 idArrayedForeach                        { $$ = $1; }
         |       idDottedMoreForeach '.' idArrayedForeach        { $$ = new AstDot($2, false, $1, $3); }
         ;
@@ -5238,7 +5247,7 @@ idArrayed<nodeExprp>:               // IEEE: id + select
         |       idArrayed '[' expr yP_MINUSCOLON constExpr ']'  { $$ = new AstSelMinus($2, $1, $3, $5); }
         ;
 
-idArrayedForeach<nodep>:        // IEEE: id + select (under foreach expression)
+idArrayedForeach<nodeExprp>:    // IEEE: id + select (under foreach expression)
                 id
                         { $$ = new AstParseRef($<fl>1, VParseRefExp::PX_TEXT, *$1, nullptr, nullptr); }
         //                      // IEEE: id + part_select_range/constant_part_select_range
@@ -5607,7 +5616,7 @@ sequence_formal_typeNoDt<nodeDTypep>:  // ==IEEE: sequence_formal_type (w/o data
 //UNSUP |       sexpr ';'                               { $$ = $1; }
 //UNSUP ;
 
-property_spec<nodep>:                   // IEEE: property_spec
+property_spec<propSpecp>:               // IEEE: property_spec
         //UNSUP: This rule has been super-specialized to what is supported now
         //UNSUP remove below
                 '@' '(' senitemEdge ')' yDISABLE yIFF '(' expr ')' pexpr
@@ -5686,7 +5695,7 @@ property_spec<nodep>:                   // IEEE: property_spec
 //UNSUP |       BISONPRE_COPY_ONCE(expr,{s/~l~/pev_/g; s/~p~/pev_/g; s/~noPar__IGNORE~/yP_PAR__IGNORE /g; })    // {copied}
 //UNSUP ;
 
-pexpr<nodep>:  // IEEE: property_expr  (The name pexpr is important as regexps just add an "p" to expr.)
+pexpr<nodeExprp>:  // IEEE: property_expr  (The name pexpr is important as regexps just add an "p" to expr.)
         //UNSUP: This rule has been super-specialized to what is supported now
         //UNSUP remove below
         //
@@ -5701,7 +5710,7 @@ pexpr<nodep>:  // IEEE: property_expr  (The name pexpr is important as regexps j
         |       expr                                    { $$ = $1; }
         ;
 
-complex_pexpr<nodep>:  // IEEE: part of property_expr, see comments there
+complex_pexpr<nodeExprp>:  // IEEE: part of property_expr, see comments there
                 expr yP_ORMINUSGT pexpr                 { $$ = new AstLogOr($2, new AstLogNot($2, $1), $3); }
         |       expr yP_OREQGT pexpr                    { $$ = new AstImplication($2, $1, $3); }
         |       yNOT pexpr %prec prNEGATION             { $$ = new AstLogNot{$1, $2}; }
@@ -6406,7 +6415,7 @@ packageClassScopeNoId<nodep>:   // IEEE: [package_scope] not followed by yaID
                 packageClassScope                       { $$ = $1; $<scp>$ = $<scp>1; SYMP->nextId(nullptr); }
         ;
 
-packageClassScopeE<nodep>:      // IEEE: [package_scope]
+packageClassScopeE<nodeExprp>:  // IEEE: [package_scope]
         //                      // IMPORTANT: The lexer will parse the following ID to be in the found package
         //                      //     if not needed must use packageClassScopeNoId
         //                      // TODO: To support classes should return generic type, not packagep
@@ -6415,7 +6424,7 @@ packageClassScopeE<nodep>:      // IEEE: [package_scope]
         |       packageClassScope                       { $$ = $1; $<scp>$ = $<scp>1; }
         ;
 
-packageClassScope<nodep>:       // IEEE: class_scope
+packageClassScope<nodeExprp>:   // IEEE: class_scope
         //                      // IEEE: "class_type yP_COLONCOLON"
         //                      // IMPORTANT: The lexer will parse the following ID to be in the found package
         //                      //     if not needed must use packageClassScopeNoId
@@ -6428,7 +6437,7 @@ packageClassScope<nodep>:       // IEEE: class_scope
                         { $$ = new AstDot($2, true, $1, $3); $<scp>$ = $<scp>3; }
         ;
 
-packageClassScopeList<nodep>:   // IEEE: class_type: "id [ parameter_value_assignment ]" but allow yaID__aTYPE
+packageClassScopeList<nodeExprp>:   // IEEE: class_type: "id [ parameter_value_assignment ]" but allow yaID__aTYPE
         //                      // Or IEEE: [package_scope]
         //                      // IMPORTANT: The lexer will parse the following ID to be in the found package
         //                      //     if not needed must use packageClassScopeNoId
@@ -6439,7 +6448,7 @@ packageClassScopeList<nodep>:   // IEEE: class_type: "id [ parameter_value_assig
                         { $$ = new AstDot($<fl>2, true, $1, $2); $<scp>$ = $<scp>2; }
         ;
 
-packageClassScopeItem<nodep>:   // IEEE: package_scope or [package_scope]::[class_scope]
+packageClassScopeItem<nodeExprp>:   // IEEE: package_scope or [package_scope]::[class_scope]
         //                      // IMPORTANT: The lexer will parse the following ID to be in the found package
         //                      //     if not needed must use packageClassScopeNoId
         //                      // IEEE: class_type: "id [ parameter_value_assignment ]" but allow yaID__aTYPE
@@ -6455,7 +6464,7 @@ packageClassScopeItem<nodep>:   // IEEE: package_scope or [package_scope]::[clas
                         { $$ = new AstClassOrPackageRef($<fl>1, *$1, $<scp>1, $2); $<scp>$ = $<scp>1; }
         ;
 
-dollarUnitNextId<nodep>:        // $unit
+dollarUnitNextId<nodeExprp>:    // $unit
         //                      // IMPORTANT: The lexer will parse the following ID to be in the found package
         //                      //     if not needed must use packageClassScopeNoId
         //                      // Must call nextId without any additional tokens following
@@ -6464,7 +6473,7 @@ dollarUnitNextId<nodep>:        // $unit
                           SYMP->nextId(PARSEP->rootp()); }
         ;
 
-localNextId<nodep>:             // local
+localNextId<nodeExprp>:         // local
         //                      // IMPORTANT: The lexer will parse the following ID to be in the found package
         //                      //     if not needed must use packageClassScopeNoId
         //                      // Must call nextId without any additional tokens following
diff --git a/test_regress/t/t_stream_bad.out b/test_regress/t/t_stream_bad.out
new file mode 100644
index 000000000..d374c004f
--- /dev/null
+++ b/test_regress/t/t_stream_bad.out
@@ -0,0 +1,15 @@
+%Error: t/t_stream_bad.v:12:32: Expecting expression to be constant, but can't convert a RAND to constant.
+                              : ... In instance t
+   12 |    initial packed_data_32 = {<<$random{byte_in}};
+      |                                ^~~~~~~
+%Error: t/t_stream_bad.v:12:30: Slice size isn't a constant or basic data type.
+                              : ... In instance t
+   12 |    initial packed_data_32 = {<<$random{byte_in}};
+      |                              ^~
+%Warning-WIDTH: t/t_stream_bad.v:12:27: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
+                                      : ... In instance t
+   12 |    initial packed_data_32 = {<<$random{byte_in}};
+      |                           ^
+                ... For warning description see https://verilator.org/warn/WIDTH?v=latest
+                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
+%Error: Exiting due to
diff --git a/test_regress/t/t_stream_bad.pl b/test_regress/t/t_stream_bad.pl
new file mode 100755
index 000000000..a29ead0ed
--- /dev/null
+++ b/test_regress/t/t_stream_bad.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_stream_bad.v b/test_regress/t/t_stream_bad.v
new file mode 100644
index 000000000..c93398145
--- /dev/null
+++ b/test_regress/t/t_stream_bad.v
@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Geza Lore.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   logic [31:0] packed_data_32;
+   byte          byte_in[4];
+
+   initial packed_data_32 = {<<$random{byte_in}};
+
+endmodule
diff --git a/test_regress/t/t_stream_integer_type.out b/test_regress/t/t_stream_integer_type.out
index 59b6a116d..96728e3ee 100644
--- a/test_regress/t/t_stream_integer_type.out
+++ b/test_regress/t/t_stream_integer_type.out
@@ -72,63 +72,115 @@
                                                 : ... In instance t
   136 |          {<<32{reg_out}}      = v_packed_data_128;
       |                               ^
-%Error: t/t_stream_integer_type.v:150:33: Operator STREAML expected non-datatype RHS but 'byte' is a datatype.
-                                        : ... In instance t
-  150 |          packed_data_32    = {<<byte{byte_in}};
-      |                                 ^~~~
 %Warning-WIDTH: t/t_stream_integer_type.v:150:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
                                                 : ... In instance t
   150 |          packed_data_32    = {<<byte{byte_in}};
       |                            ^
-%Error: t/t_stream_integer_type.v:151:33: Operator STREAML expected non-datatype RHS but 'shortint' is a datatype.
-                                        : ... In instance t
-  151 |          packed_data_64    = {<<shortint{shortint_in}};
-      |                                 ^~~~~~~~
 %Warning-WIDTH: t/t_stream_integer_type.v:151:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits.
                                                 : ... In instance t
   151 |          packed_data_64    = {<<shortint{shortint_in}};
       |                            ^
-%Error: t/t_stream_integer_type.v:152:33: Operator STREAML expected non-datatype RHS but 'int' is a datatype.
-                                        : ... In instance t
-  152 |          packed_data_128   = {<<int{int_in}};
-      |                                 ^~~
 %Warning-WIDTH: t/t_stream_integer_type.v:152:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
                                                 : ... In instance t
   152 |          packed_data_128   = {<<int{int_in}};
       |                            ^
-%Error: t/t_stream_integer_type.v:153:33: Operator STREAML expected non-datatype RHS but 'integer' is a datatype.
-                                        : ... In instance t
-  153 |          packed_data_128_i = {<<integer{integer_in}};
-      |                                 ^~~~~~~
 %Warning-WIDTH: t/t_stream_integer_type.v:153:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
                                                 : ... In instance t
   153 |          packed_data_128_i = {<<integer{integer_in}};
       |                            ^
-%Error: t/t_stream_integer_type.v:154:33: Operator STREAML expected non-datatype RHS but 'longint' is a datatype.
-                                        : ... In instance t
-  154 |          packed_data_256   = {<<longint{longint_in}};
-      |                                 ^~~~~~~
 %Warning-WIDTH: t/t_stream_integer_type.v:154:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits.
                                                 : ... In instance t
   154 |          packed_data_256   = {<<longint{longint_in}};
       |                            ^
-%Error: t/t_stream_integer_type.v:155:33: Operator STREAML expected non-datatype RHS but 'time' is a datatype.
-                                        : ... In instance t
-  155 |          packed_time_256   = {<<time{time_in}};
-      |                                 ^~~~
 %Warning-WIDTH: t/t_stream_integer_type.v:155:28: Operator ASSIGN expects 256 bits on the Assign RHS, but Assign RHS's STREAML generates 64 bits.
                                                 : ... In instance t
   155 |          packed_time_256   = {<<time{time_in}};
       |                            ^
-%Error: t/t_stream_integer_type.v:156:33: Operator STREAML expected non-datatype RHS but 'test_byte' is a datatype.
-                                        : ... In instance t
-  156 |          v_packed_data_32  = {<<test_byte{bit_in}};
-      |                                 ^~~~~~~~~
-%Error: t/t_stream_integer_type.v:156:31: Slice size isn't a constant or basic data type.
-                                        : ... In instance t
-  156 |          v_packed_data_32  = {<<test_byte{bit_in}};
-      |                               ^~
-%Error: Internal Error: t/t_stream_integer_type.v:156:28: ../V3Width.cpp:#: Node has no type
-                                                        : ... In instance t
+%Warning-WIDTH: t/t_stream_integer_type.v:156:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's STREAML generates 8 bits.
+                                                : ... In instance t
   156 |          v_packed_data_32  = {<<test_byte{bit_in}};
       |                            ^
+%Warning-WIDTH: t/t_stream_integer_type.v:157:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits.
+                                                : ... In instance t
+  157 |          v_packed_data_64  = {<<test_short{logic_in}};
+      |                            ^
+%Warning-WIDTH: t/t_stream_integer_type.v:158:28: Operator ASSIGN expects 128 bits on the Assign RHS, but Assign RHS's STREAML generates 32 bits.
+                                                : ... In instance t
+  158 |          v_packed_data_128 = {<<test_word{reg_in}};
+      |                            ^
+%Warning-WIDTH: t/t_stream_integer_type.v:160:37: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_32' generates 32 bits.
+                                                : ... In instance t
+  160 |          {<<byte{byte_out}}         = packed_data_32;
+      |                                     ^
+%Warning-WIDTH: t/t_stream_integer_type.v:161:37: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_64' generates 64 bits.
+                                                : ... In instance t
+  161 |          {<<shortint{shortint_out}} = packed_data_64;
+      |                                     ^
+%Warning-WIDTH: t/t_stream_integer_type.v:162:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128' generates 128 bits.
+                                                : ... In instance t
+  162 |          {<<int{int_out}}           = packed_data_128;
+      |                                     ^
+%Warning-WIDTH: t/t_stream_integer_type.v:163:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_128_i' generates 128 bits.
+                                                : ... In instance t
+  163 |          {<<integer{integer_out}}   = packed_data_128_i;
+      |                                     ^
+%Warning-WIDTH: t/t_stream_integer_type.v:164:37: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_data_256' generates 256 bits.
+                                                : ... In instance t
+  164 |          {<<longint{longint_out}}   = packed_data_256;
+      |                                     ^
+%Warning-WIDTH: t/t_stream_integer_type.v:165:37: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'packed_time_256' generates 256 bits.
+                                                : ... In instance t
+  165 |          {<<time{time_out}}         = packed_time_256;
+      |                                     ^
+%Warning-WIDTH: t/t_stream_integer_type.v:166:37: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_32' generates 32 bits.
+                                                : ... In instance t
+  166 |          {<<test_byte{bit_out}}     = v_packed_data_32;
+      |                                     ^
+%Warning-WIDTH: t/t_stream_integer_type.v:167:37: Operator ASSIGN expects 16 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_64' generates 64 bits.
+                                                : ... In instance t
+  167 |          {<<test_short{logic_out}}  = v_packed_data_64;
+      |                                     ^
+%Warning-WIDTH: t/t_stream_integer_type.v:168:37: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's VARREF 'v_packed_data_128' generates 128 bits.
+                                                : ... In instance t
+  168 |          {<<test_word{reg_out}}     = v_packed_data_128;
+      |                                     ^
+%Error: t/t_stream_integer_type.v:128:11: SEL is not an unpacked array, but is in an unpacked array context
+  128 |          {<<8{byte_out}}      = packed_data_32;
+      |           ^~
+%Error: t/t_stream_integer_type.v:129:11: SEL is not an unpacked array, but is in an unpacked array context
+  129 |          {<<16{shortint_out}} = packed_data_64;
+      |           ^~
+%Error: t/t_stream_integer_type.v:130:11: SEL is not an unpacked array, but is in an unpacked array context
+  130 |          {<<32{int_out}}      = packed_data_128;
+      |           ^~
+%Error: t/t_stream_integer_type.v:131:11: SEL is not an unpacked array, but is in an unpacked array context
+  131 |          {<<32{integer_out}}  = packed_data_128_i;
+      |           ^~
+%Error: t/t_stream_integer_type.v:132:11: SEL is not an unpacked array, but is in an unpacked array context
+  132 |          {<<64{longint_out}}  = packed_data_256;
+      |           ^~
+%Error: t/t_stream_integer_type.v:133:11: SEL is not an unpacked array, but is in an unpacked array context
+  133 |          {<<64{time_out}}     = packed_time_256;
+      |           ^~
+%Error: t/t_stream_integer_type.v:134:11: SEL is not an unpacked array, but is in an unpacked array context
+  134 |          {<<8{bit_out}}       = v_packed_data_32;
+      |           ^~
+%Error: t/t_stream_integer_type.v:135:11: SEL is not an unpacked array, but is in an unpacked array context
+  135 |          {<<16{logic_out}}    = v_packed_data_64;
+      |           ^~
+%Error: t/t_stream_integer_type.v:136:11: SEL is not an unpacked array, but is in an unpacked array context
+  136 |          {<<32{reg_out}}      = v_packed_data_128;
+      |           ^~
+%Error: t/t_stream_integer_type.v:160:11: SEL is not an unpacked array, but is in an unpacked array context
+  160 |          {<<byte{byte_out}}         = packed_data_32;
+      |           ^~
+%Error: t/t_stream_integer_type.v:161:11: SEL is not an unpacked array, but is in an unpacked array context
+  161 |          {<<shortint{shortint_out}} = packed_data_64;
+      |           ^~
+%Error: t/t_stream_integer_type.v:162:11: SEL is not an unpacked array, but is in an unpacked array context
+  162 |          {<<int{int_out}}           = packed_data_128;
+      |           ^~
+%Error: t/t_stream_integer_type.v:163:11: SEL is not an unpacked array, but is in an unpacked array context
+  163 |          {<<integer{integer_out}}   = packed_data_128_i;
+      |           ^~
+%Error: Exiting due to

From 25f970eac22727894cda76338728c45260e29e6b Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 20 Nov 2022 15:06:49 -0500
Subject: [PATCH 075/156] Internals: Fix constructor style.

---
 src/V3AssertPre.cpp    | 34 +++++++++++++--------------
 src/V3AstInlines.h     |  2 +-
 src/V3AstNodeOther.h   | 12 +++++-----
 src/V3AstNodes.cpp     | 52 +++++++++++++++++++++---------------------
 src/V3CCtors.cpp       |  2 +-
 src/V3Cdc.cpp          | 22 +++++++++---------
 src/V3Clean.cpp        |  4 ++--
 src/V3Clock.cpp        |  2 +-
 src/V3Coverage.cpp     | 14 ++++++------
 src/V3Expand.cpp       | 22 +++++++++---------
 src/V3LinkCells.cpp    | 44 +++++++++++++++++------------------
 src/V3LinkInc.cpp      | 16 ++++++-------
 src/V3LinkJump.cpp     | 40 ++++++++++++++++----------------
 src/V3LinkParse.cpp    | 22 +++++++++---------
 src/V3MergeCond.cpp    |  6 ++---
 src/V3ParseGrammar.cpp |  4 ++--
 src/V3Premit.cpp       | 24 +++++++++----------
 src/V3Reloop.cpp       | 24 +++++++++----------
 src/V3Simulate.h       |  2 +-
 src/V3Split.cpp        | 32 +++++++++++++-------------
 src/V3SplitVar.cpp     | 16 ++++++-------
 src/V3Table.cpp        |  4 ++--
 src/V3Timing.cpp       |  2 +-
 23 files changed, 201 insertions(+), 201 deletions(-)

diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp
index 43d5f6e32..ac851beac 100644
--- a/src/V3AssertPre.cpp
+++ b/src/V3AssertPre.cpp
@@ -59,9 +59,9 @@ private:
         if (!senip) senip = m_seniAlwaysp;
         if (!senip) {
             nodep->v3warn(E_UNSUPPORTED, "Unsupported: Unclocked assertion");
-            newp = new AstSenTree(nodep->fileline(), nullptr);
+            newp = new AstSenTree{nodep->fileline(), nullptr};
         } else {
-            newp = new AstSenTree(nodep->fileline(), senip->cloneTree(true));
+            newp = new AstSenTree{nodep->fileline(), senip->cloneTree(true)};
         }
         return newp;
     }
@@ -171,10 +171,10 @@ private:
         iterateChildren(nodep);
         FileLine* const fl = nodep->fileline();
         AstNodeExpr* exprp = nodep->exprp()->unlinkFrBack();
-        if (exprp->width() > 1) exprp = new AstSel(fl, exprp, 0, 1);
-        AstNodeExpr* const past = new AstPast(fl, exprp, nullptr);
+        if (exprp->width() > 1) exprp = new AstSel{fl, exprp, 0, 1};
+        AstNodeExpr* const past = new AstPast{fl, exprp, nullptr};
         past->dtypeFrom(exprp);
-        exprp = new AstAnd(fl, past, new AstNot(fl, exprp->cloneTree(false)));
+        exprp = new AstAnd{fl, past, new AstNot{fl, exprp->cloneTree(false)}};
         exprp->dtypeSetBit();
         nodep->replaceWith(exprp);
         nodep->sentreep(newSenTree(nodep));
@@ -190,10 +190,10 @@ private:
         iterateChildren(nodep);
         FileLine* const fl = nodep->fileline();
         AstNodeExpr* exprp = nodep->exprp()->unlinkFrBack();
-        if (exprp->width() > 1) exprp = new AstSel(fl, exprp, 0, 1);
-        AstNodeExpr* const past = new AstPast(fl, exprp, nullptr);
+        if (exprp->width() > 1) exprp = new AstSel{fl, exprp, 0, 1};
+        AstNodeExpr* const past = new AstPast{fl, exprp, nullptr};
         past->dtypeFrom(exprp);
-        exprp = new AstAnd(fl, new AstNot(fl, past), exprp->cloneTree(false));
+        exprp = new AstAnd{fl, new AstNot{fl, past}, exprp->cloneTree(false)};
         exprp->dtypeSetBit();
         nodep->replaceWith(exprp);
         nodep->sentreep(newSenTree(nodep));
@@ -204,9 +204,9 @@ private:
         iterateChildren(nodep);
         FileLine* const fl = nodep->fileline();
         AstNodeExpr* exprp = nodep->exprp()->unlinkFrBack();
-        AstNodeExpr* const past = new AstPast(fl, exprp, nullptr);
+        AstNodeExpr* const past = new AstPast{fl, exprp, nullptr};
         past->dtypeFrom(exprp);
-        exprp = new AstEq(fl, past, exprp->cloneTree(false));
+        exprp = new AstEq{fl, past, exprp->cloneTree(false)};
         exprp->dtypeSetBit();
         nodep->replaceWith(exprp);
         nodep->sentreep(newSenTree(nodep));
@@ -220,11 +220,11 @@ private:
         AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
         AstNodeExpr* lhsp = nodep->lhsp()->unlinkFrBack();
 
-        if (m_disablep) lhsp = new AstAnd(fl, new AstNot(fl, m_disablep), lhsp);
+        if (m_disablep) lhsp = new AstAnd{fl, new AstNot{fl, m_disablep}, lhsp};
 
-        AstNodeExpr* const past = new AstPast(fl, lhsp, nullptr);
+        AstNodeExpr* const past = new AstPast{fl, lhsp, nullptr};
         past->dtypeFrom(lhsp);
-        AstNodeExpr* const exprp = new AstOr(fl, new AstNot(fl, past), rhsp);
+        AstNodeExpr* const exprp = new AstOr{fl, new AstNot{fl, past}, rhsp};
         exprp->dtypeSetBit();
         nodep->replaceWith(exprp);
         nodep->sentreep(newSenTree(nodep));
@@ -242,11 +242,11 @@ private:
         if (AstNodeExpr* const disablep = nodep->disablep()) {
             m_disablep = disablep->cloneTree(false);
             if (VN_IS(nodep->backp(), Cover)) {
-                blockp = new AstAnd(disablep->fileline(),
-                                    new AstNot(disablep->fileline(), disablep->unlinkFrBack()),
-                                    blockp);
+                blockp = new AstAnd{disablep->fileline(),
+                                    new AstNot{disablep->fileline(), disablep->unlinkFrBack()},
+                                    blockp};
             } else {
-                blockp = new AstOr(disablep->fileline(), disablep->unlinkFrBack(), blockp);
+                blockp = new AstOr{disablep->fileline(), disablep->unlinkFrBack(), blockp};
             }
         }
         // Unlink and just keep a pointer to it, convert to sentree as needed
diff --git a/src/V3AstInlines.h b/src/V3AstInlines.h
index c4f574412..745fee3f3 100644
--- a/src/V3AstInlines.h
+++ b/src/V3AstInlines.h
@@ -132,7 +132,7 @@ bool AstActive::hasCombo() const { return m_sensesp->hasCombo(); }
 
 AstElabDisplay::AstElabDisplay(FileLine* fl, VDisplayType dispType, AstNodeExpr* exprsp)
     : ASTGEN_SUPER_ElabDisplay(fl) {
-    addFmtp(new AstSFormatF{fl, AstSFormatF::NoFormat(), exprsp});
+    addFmtp(new AstSFormatF{fl, AstSFormatF::NoFormat{}, exprsp});
     m_displayType = dispType;
 }
 
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index b5e164c4b..6725d14c4 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -436,7 +436,7 @@ class AstNodeReadWriteMem VL_NOT_FINAL : public AstNodeStmt {
 public:
     AstNodeReadWriteMem(VNType t, FileLine* fl, bool hex, AstNodeExpr* filenamep,
                         AstNodeExpr* memp, AstNodeExpr* lsbp, AstNodeExpr* msbp)
-        : AstNodeStmt(t, fl)
+        : AstNodeStmt{t, fl}
         , m_isHex(hex) {
         this->filenamep(filenamep);
         this->memp(memp);
@@ -480,8 +480,8 @@ private:
     bool m_tracking;  // When emit, it's ok to parse the string to do indentation
 public:
     AstNodeSimpleText(VNType t, FileLine* fl, const string& textp, bool tracking = false)
-        : AstNodeText(t, fl, textp)
-        , m_tracking(tracking) {}
+        : AstNodeText{t, fl, textp}
+        , m_tracking{tracking} {}
     ASTGEN_MEMBERS_AstNodeSimpleText;
     void tracking(bool flag) { m_tracking = flag; }
     bool tracking() const { return m_tracking; }
@@ -2541,7 +2541,7 @@ public:
                char missingArgChar = 'd')
         : ASTGEN_SUPER_Display(fl)
         , m_displayType{dispType} {
-        this->fmtp(new AstSFormatF{fl, AstSFormatF::NoFormat(), exprsp, missingArgChar});
+        this->fmtp(new AstSFormatF{fl, AstSFormatF::NoFormat{}, exprsp, missingArgChar});
         this->filep(filep);
     }
     ASTGEN_MEMBERS_AstDisplay;
@@ -2916,7 +2916,7 @@ public:
     }
     AstSFormat(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* exprsp, char missingArgChar = 'd')
         : ASTGEN_SUPER_SFormat(fl) {
-        this->fmtp(new AstSFormatF{fl, AstSFormatF::NoFormat(), exprsp, missingArgChar});
+        this->fmtp(new AstSFormatF{fl, AstSFormatF::NoFormat{}, exprsp, missingArgChar});
         this->lhsp(lhsp);
     }
     ASTGEN_MEMBERS_AstSFormat;
@@ -3507,7 +3507,7 @@ public:
     void commas(bool flag) { m_commas = flag; }
     bool commas() const { return m_commas; }
     void addText(FileLine* fl, const string& textp, bool tracking = false) {
-        addNodesp(new AstText(fl, textp, tracking));
+        addNodesp(new AstText{fl, textp, tracking});
     }
 };
 
diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index 9c84cdb2d..9ebf80b50 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -254,21 +254,21 @@ int AstNodeUOrStructDType::widthAlignBytes() const {
 
 AstNodeBiop* AstEq::newTyped(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp) {
     if (lhsp->isString() && rhsp->isString()) {
-        return new AstEqN(fl, lhsp, rhsp);
+        return new AstEqN{fl, lhsp, rhsp};
     } else if (lhsp->isDouble() && rhsp->isDouble()) {
-        return new AstEqD(fl, lhsp, rhsp);
+        return new AstEqD{fl, lhsp, rhsp};
     } else {
-        return new AstEq(fl, lhsp, rhsp);
+        return new AstEq{fl, lhsp, rhsp};
     }
 }
 
 AstNodeBiop* AstEqWild::newTyped(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp) {
     if (lhsp->isString() && rhsp->isString()) {
-        return new AstEqN(fl, lhsp, rhsp);
+        return new AstEqN{fl, lhsp, rhsp};
     } else if (lhsp->isDouble() && rhsp->isDouble()) {
-        return new AstEqD(fl, lhsp, rhsp);
+        return new AstEqD{fl, lhsp, rhsp};
     } else {
-        return new AstEqWild(fl, lhsp, rhsp);
+        return new AstEqWild{fl, lhsp, rhsp};
     }
 }
 
@@ -285,7 +285,7 @@ AstNodeExpr* AstInsideRange::newAndFromInside(AstNodeExpr* exprp, AstNodeExpr* l
     AstNodeExpr* const bp = new AstLte{fileline(), exprp->cloneTree(true), rhsp};
     ap->fileline()->modifyWarnOff(V3ErrorCode::UNSIGNED, true);
     bp->fileline()->modifyWarnOff(V3ErrorCode::CMPCONST, true);
-    return new AstAnd(fileline(), ap, bp);
+    return new AstAnd{fileline(), ap, bp};
 }
 
 AstConst* AstConst::parseParamLiteral(FileLine* fl, const string& literal) {
@@ -293,11 +293,11 @@ AstConst* AstConst::parseParamLiteral(FileLine* fl, const string& literal) {
     if (literal[0] == '"') {
         // This is a string
         const string v = literal.substr(1, literal.find('"', 1) - 1);
-        return new AstConst(fl, AstConst::VerilogStringLiteral(), v);
+        return new AstConst{fl, AstConst::VerilogStringLiteral{}, v};
     } else if (literal.find_first_of(".eEpP") != string::npos) {
         // This may be a real
         const double v = VString::parseDouble(literal, &success);
-        if (success) return new AstConst(fl, AstConst::RealDouble(), v);
+        if (success) return new AstConst{fl, AstConst::RealDouble{}, v};
     }
     if (!success) {
         // This is either an integer or an error
@@ -310,18 +310,18 @@ AstConst* AstConst::parseParamLiteral(FileLine* fl, const string& literal) {
         char* endp;
         const int v = strtol(literal.c_str(), &endp, 0);
         if ((v != 0) && (endp[0] == 0)) {  // C literal
-            return new AstConst(fl, AstConst::Signed32(), v);
+            return new AstConst{fl, AstConst::Signed32{}, v};
         } else {  // Try a Verilog literal (fatals if not)
-            return new AstConst(fl, AstConst::StringToParse(), literal.c_str());
+            return new AstConst{fl, AstConst::StringToParse{}, literal.c_str()};
         }
     }
     return nullptr;
 }
 
 AstNetlist::AstNetlist()
-    : ASTGEN_SUPER_Netlist(new FileLine(FileLine::builtInFilename()))
-    , m_typeTablep{new AstTypeTable(fileline())}
-    , m_constPoolp{new AstConstPool(fileline())} {
+    : ASTGEN_SUPER_Netlist(new FileLine{FileLine::builtInFilename()})
+    , m_typeTablep{new AstTypeTable{fileline()}}
+    , m_constPoolp{new AstConstPool{fileline()}} {
     addMiscsp(m_typeTablep);
     addMiscsp(m_constPoolp);
 }
@@ -1047,7 +1047,7 @@ AstVoidDType* AstTypeTable::findVoidDType(FileLine* fl) {
 
 AstQueueDType* AstTypeTable::findQueueIndexDType(FileLine* fl) {
     if (VL_UNLIKELY(!m_queueIndexp)) {
-        AstQueueDType* const newp = new AstQueueDType(fl, AstNode::findUInt32DType(), nullptr);
+        AstQueueDType* const newp = new AstQueueDType{fl, AstNode::findUInt32DType(), nullptr};
         addTypesp(newp);
         m_queueIndexp = newp;
     }
@@ -1057,7 +1057,7 @@ AstQueueDType* AstTypeTable::findQueueIndexDType(FileLine* fl) {
 AstBasicDType* AstTypeTable::findBasicDType(FileLine* fl, VBasicDTypeKwd kwd) {
     if (m_basicps[kwd]) return m_basicps[kwd];
     //
-    AstBasicDType* const new1p = new AstBasicDType(fl, kwd);
+    AstBasicDType* const new1p = new AstBasicDType{fl, kwd};
     // Because the detailed map doesn't update this map,
     // check the detailed map for this same node
     // Also adds this new node to the detailed map
@@ -1074,7 +1074,7 @@ AstBasicDType* AstTypeTable::findBasicDType(FileLine* fl, VBasicDTypeKwd kwd) {
 
 AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd, int width,
                                                int widthMin, VSigning numeric) {
-    AstBasicDType* const new1p = new AstBasicDType(fl, kwd, numeric, width, widthMin);
+    AstBasicDType* const new1p = new AstBasicDType{fl, kwd, numeric, width, widthMin};
     AstBasicDType* const newp = findInsertSameDType(new1p);
     if (newp != new1p) {
         VL_DO_DANGLING(new1p->deleteTree(), new1p);
@@ -1087,7 +1087,7 @@ AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd,
 AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd,
                                                const VNumRange& range, int widthMin,
                                                VSigning numeric) {
-    AstBasicDType* const new1p = new AstBasicDType(fl, kwd, numeric, range, widthMin);
+    AstBasicDType* const new1p = new AstBasicDType{fl, kwd, numeric, range, widthMin};
     AstBasicDType* const newp = findInsertSameDType(new1p);
     if (newp != new1p) {
         VL_DO_DANGLING(new1p->deleteTree(), new1p);
@@ -1098,8 +1098,8 @@ AstBasicDType* AstTypeTable::findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd,
 }
 
 AstBasicDType* AstTypeTable::findInsertSameDType(AstBasicDType* nodep) {
-    const VBasicTypeKey key(nodep->width(), nodep->widthMin(), nodep->numeric(), nodep->keyword(),
-                            nodep->nrange());
+    const VBasicTypeKey key{nodep->width(), nodep->widthMin(), nodep->numeric(), nodep->keyword(),
+                            nodep->nrange()};
     DetailedMap& mapr = m_detailedMap;
     const auto it = mapr.find(key);
     if (it != mapr.end()) return it->second;
@@ -1111,8 +1111,8 @@ AstBasicDType* AstTypeTable::findInsertSameDType(AstBasicDType* nodep) {
 
 AstConstPool::AstConstPool(FileLine* fl)
     : ASTGEN_SUPER_ConstPool(fl)
-    , m_modp{new AstModule(fl, "@CONST-POOL@")}
-    , m_scopep{new AstScope(fl, m_modp, "@CONST-POOL@", nullptr, nullptr)} {
+    , m_modp{new AstModule{fl, "@CONST-POOL@"}}
+    , m_scopep{new AstScope{fl, m_modp, "@CONST-POOL@", nullptr, nullptr}} {
     this->modulep(m_modp);
     m_modp->addStmtsp(m_scopep);
 }
@@ -1124,12 +1124,12 @@ const char* AstConstPool::broken() const {
 
 AstVarScope* AstConstPool::createNewEntry(const string& name, AstNodeExpr* initp) {
     FileLine* const fl = initp->fileline();
-    AstVar* const varp = new AstVar(fl, VVarType::MODULETEMP, name, initp->dtypep());
+    AstVar* const varp = new AstVar{fl, VVarType::MODULETEMP, name, initp->dtypep()};
     varp->isConst(true);
     varp->isStatic(true);
     varp->valuep(initp->cloneTree(false));
     m_modp->addStmtsp(varp);
-    AstVarScope* const varScopep = new AstVarScope(fl, m_scopep, varp);
+    AstVarScope* const varScopep = new AstVarScope{fl, m_scopep, varp};
     m_scopep->addVarsp(varScopep);
     return varScopep;
 }
@@ -1580,7 +1580,7 @@ void AstInitArray::addIndexValuep(uint64_t index, AstNodeExpr* newp) {
     if (it != m_map.end()) {
         it->second->valuep(newp);
     } else {
-        AstInitItem* const itemp = new AstInitItem(fileline(), newp);
+        AstInitItem* const itemp = new AstInitItem{fileline(), newp};
         m_map.emplace(index, itemp);
         addInitsp(itemp);
     }
@@ -1870,7 +1870,7 @@ const char* AstNetlist::broken() const {
 }
 AstPackage* AstNetlist::dollarUnitPkgAddp() {
     if (!m_dollarUnitPkgp) {
-        m_dollarUnitPkgp = new AstPackage(fileline(), AstPackage::dollarUnitName());
+        m_dollarUnitPkgp = new AstPackage{fileline(), AstPackage::dollarUnitName()};
         // packages are always libraries; don't want to make them a "top"
         m_dollarUnitPkgp->inLibrary(true);
         m_dollarUnitPkgp->modTrace(false);  // may reconsider later
diff --git a/src/V3CCtors.cpp b/src/V3CCtors.cpp
index 585c23a19..3f9bce6ed 100644
--- a/src/V3CCtors.cpp
+++ b/src/V3CCtors.cpp
@@ -160,7 +160,7 @@ void V3CCtors::evalAsserts() {
                         }
                         const uint64_t value = VL_MASK_Q(storedWidth) & ~VL_MASK_Q(lastWordWidth);
                         newp = new AstAnd{varp->fileline(), newp,
-                                          new AstConst(varp->fileline(), AstConst::WidthedValue(),
+                                          new AstConst(varp->fileline(), AstConst::WidthedValue{},
                                                        storedWidth, value)};
                         AstNodeIf* const ifp = new AstIf{
                             varp->fileline(), newp,
diff --git a/src/V3Cdc.cpp b/src/V3Cdc.cpp
index b47dc53d3..177689093 100644
--- a/src/V3Cdc.cpp
+++ b/src/V3Cdc.cpp
@@ -239,7 +239,7 @@ private:
         if (m_scopep) {
             VL_RESTORER(m_logicVertexp);
             UINFO(4, "   STMT " << nodep << endl);
-            m_logicVertexp = new CdcLogicVertex(&m_graph, m_scopep, nodep, m_domainp);
+            m_logicVertexp = new CdcLogicVertex{&m_graph, m_scopep, nodep, m_domainp};
             if (m_domainp && m_domainp->hasClocked()) {  // To/from a flop
                 m_logicVertexp->isFlop(true);
                 m_logicVertexp->srcDomainp(m_domainp);
@@ -260,18 +260,18 @@ private:
         CdcVarVertex* vertexp = reinterpret_cast<CdcVarVertex*>(varscp->user1p());
         if (!vertexp) {
             UINFO(6, "New vertex " << varscp << endl);
-            vertexp = new CdcVarVertex(&m_graph, m_scopep, varscp);
+            vertexp = new CdcVarVertex{&m_graph, m_scopep, varscp};
             varscp->user1p(vertexp);
             if (varscp->varp()->isUsedClock()) {}
             if (varscp->varp()->isPrimaryIO()) {
                 // Create IO vertex - note it's relative to the pointed to var, not where we are
                 // now This allows reporting to easily print the input statement
                 CdcLogicVertex* const ioVertexp
-                    = new CdcLogicVertex(&m_graph, varscp->scopep(), varscp->varp(), nullptr);
+                    = new CdcLogicVertex{&m_graph, varscp->scopep(), varscp->varp(), nullptr};
                 if (varscp->varp()->isWritable()) {
-                    new V3GraphEdge(&m_graph, vertexp, ioVertexp, 1);
+                    new V3GraphEdge{&m_graph, vertexp, ioVertexp, 1};
                 } else {
-                    new V3GraphEdge(&m_graph, ioVertexp, vertexp, 1);
+                    new V3GraphEdge{&m_graph, ioVertexp, vertexp, 1};
                 }
             }
         }
@@ -466,7 +466,7 @@ private:
         } else {
             V3EmitV::verilogPrefixedTree(nodep, *m_ofp, prefix + " +- ", filelineWidth(),
                                          vertexp->srcDomainp(), true);
-            if (debug()) { CdcDumpVisitor visitor(nodep, m_ofp, front + "DBG: "); }
+            if (debug()) { CdcDumpVisitor{nodep, m_ofp, front + "DBG: "}; }
         }
 
         nextsep = " | ";
@@ -564,8 +564,8 @@ private:
             // If primary I/O, give it domain of the input
             const AstVar* const varp = vvertexp->varScp()->varp();
             if (varp->isPrimaryIO() && varp->isNonOutput() && !traceDests) {
-                senouts.insert(new AstSenTree(
-                    varp->fileline(), new AstSenItem(varp->fileline(), AstSenItem::Combo())));
+                senouts.insert(new AstSenTree{
+                    varp->fileline(), new AstSenItem{varp->fileline(), AstSenItem::Combo{}}});
             }
         }
 
@@ -662,7 +662,7 @@ private:
             // Weight of CDC_WEIGHT_ASYNC to indicate feeds async (for reporting)
             // When simplify we'll take the MAX weight
             if (nodep->access().isWriteOrRW()) {
-                new V3GraphEdge(&m_graph, m_logicVertexp, varvertexp, 1);
+                new V3GraphEdge{&m_graph, m_logicVertexp, varvertexp, 1};
                 if (m_inDly) {
                     varvertexp->fromFlop(true);
                     varvertexp->srcDomainp(m_domainp);
@@ -671,10 +671,10 @@ private:
             } else {
                 if (varvertexp->cntAsyncRst()) {
                     // UINFO(9," edgeasync "<<varvertexp->name()<<" to "<<m_logicVertexp<<endl);
-                    new V3GraphEdge(&m_graph, varvertexp, m_logicVertexp, CDC_WEIGHT_ASYNC);
+                    new V3GraphEdge{&m_graph, varvertexp, m_logicVertexp, CDC_WEIGHT_ASYNC};
                 } else {
                     // UINFO(9," edgena    "<<varvertexp->name()<<" to "<<m_logicVertexp<<endl);
-                    new V3GraphEdge(&m_graph, varvertexp, m_logicVertexp, 1);
+                    new V3GraphEdge{&m_graph, varvertexp, m_logicVertexp, 1};
                 }
             }
         }
diff --git a/src/V3Clean.cpp b/src/V3Clean.cpp
index 626a1d9ca..c7190e401 100644
--- a/src/V3Clean.cpp
+++ b/src/V3Clean.cpp
@@ -127,10 +127,10 @@ private:
         nodep->unlinkFrBack(&relinkHandle);
         //
         computeCppWidth(nodep);
-        V3Number mask(nodep, cppWidth(nodep));
+        V3Number mask{nodep, cppWidth(nodep)};
         mask.setMask(nodep->widthMin());
         AstNode* const cleanp
-            = new AstAnd(nodep->fileline(), new AstConst(nodep->fileline(), mask), nodep);
+            = new AstAnd{nodep->fileline(), new AstConst{nodep->fileline(), mask}, nodep};
         cleanp->dtypeFrom(nodep);  // Otherwise the AND normally picks LHS
         relinkHandle.relink(cleanp);
     }
diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp
index 07e088140..68d9326b6 100644
--- a/src/V3Clock.cpp
+++ b/src/V3Clock.cpp
@@ -65,7 +65,7 @@ private:
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
 
 public:
-    static AstNodeExpr* main(AstNodeExpr* nodep) { return ConvertWriteRefsToRead(nodep).m_result; }
+    static AstNodeExpr* main(AstNodeExpr* nodep) { return ConvertWriteRefsToRead{nodep}.m_result; }
 };
 
 //######################################################################
diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp
index bd9d68927..173b87725 100644
--- a/src/V3Coverage.cpp
+++ b/src/V3Coverage.cpp
@@ -118,7 +118,7 @@ private:
         // Someday the user might be allowed to specify a different page suffix
         const string page = page_prefix + "/" + m_modp->prettyName();
 
-        AstCoverDecl* const declp = new AstCoverDecl(fl, page, comment, linescov, offset);
+        AstCoverDecl* const declp = new AstCoverDecl{fl, page, comment, linescov, offset};
         declp->hier(hier);
         m_modp->addStmtsp(declp);
         UINFO(9, "new " << declp << endl);
@@ -132,10 +132,10 @@ private:
             varp->trace(true);
             m_modp->addStmtsp(varp);
             UINFO(5, "New coverage trace: " << varp << endl);
-            AstAssign* const assp = new AstAssign(
-                incp->fileline(), new AstVarRef(incp->fileline(), varp, VAccess::WRITE),
-                new AstAdd(incp->fileline(), new AstVarRef(incp->fileline(), varp, VAccess::READ),
-                           new AstConst(incp->fileline(), AstConst::WidthedValue(), 32, 1)));
+            AstAssign* const assp = new AstAssign{
+                incp->fileline(), new AstVarRef{incp->fileline(), varp, VAccess::WRITE},
+                new AstAdd{incp->fileline(), new AstVarRef{incp->fileline(), varp, VAccess::READ},
+                           new AstConst{incp->fileline(), AstConst::WidthedValue{}, 32, 1}}};
             AstNode::addNext<AstNode, AstNode>(incp, assp);
         }
         return incp;
@@ -301,11 +301,11 @@ private:
     }
 
     void toggleVarBottom(const ToggleEnt& above, const AstVar* varp) {
-        AstCoverToggle* const newp = new AstCoverToggle(
+        AstCoverToggle* const newp = new AstCoverToggle{
             varp->fileline(),
             newCoverInc(varp->fileline(), "", "v_toggle", varp->name() + above.m_comment, "", 0,
                         ""),
-            above.m_varRefp->cloneTree(true), above.m_chgRefp->cloneTree(true));
+            above.m_varRefp->cloneTree(true), above.m_chgRefp->cloneTree(true)};
         m_modp->addStmtsp(newp);
     }
 
diff --git a/src/V3Expand.cpp b/src/V3Expand.cpp
index 9bf955dde..93147f5cf 100644
--- a/src/V3Expand.cpp
+++ b/src/V3Expand.cpp
@@ -71,7 +71,7 @@ private:
         return (nodep->width() + (VL_EDATASIZE - 1)) & ~(VL_EDATASIZE - 1);
     }
     static V3Number notWideMask(AstNode* nodep) {
-        return V3Number(nodep, VL_EDATASIZE, ~VL_MASK_E(nodep->widthMin()));
+        return V3Number{nodep, VL_EDATASIZE, ~VL_MASK_E(nodep->widthMin())};
     }
     static V3Number wordMask(AstNode* nodep) {
         if (nodep->isWide()) {
@@ -157,11 +157,11 @@ private:
             const int nbitsonright = VL_EDATASIZE - loffset;  // bits that end up in lword
             newp = new AstOr{
                 fl,
-                new AstAnd{fl, new AstConst{fl, AstConst::SizedEData(), VL_MASK_E(loffset)},
+                new AstAnd{fl, new AstConst{fl, AstConst::SizedEData{}, VL_MASK_E(loffset)},
                            new AstShiftR{fl, lhip,
                                          new AstConst{fl, static_cast<uint32_t>(nbitsonright)},
                                          VL_EDATASIZE}},
-                new AstAnd{fl, new AstConst{fl, AstConst::SizedEData(), ~VL_MASK_E(loffset)},
+                new AstAnd{fl, new AstConst{fl, AstConst::SizedEData{}, ~VL_MASK_E(loffset)},
                            new AstShiftL{fl, llowp,
                                          new AstConst{fl, static_cast<uint32_t>(loffset)},
                                          VL_EDATASIZE}}};
@@ -181,7 +181,7 @@ private:
             // Squash before C++ to avoid getting a C++ compiler warning
             // (even though code would be unreachable as presumably a
             // AstCondBound is protecting above this node.
-            return new AstConst{fl, AstConst::SizedEData(), 0};
+            return new AstConst{fl, AstConst::SizedEData{}, 0};
         } else {
             AstNodeExpr* wordp;
             FileLine* const lfl = lsbp->fileline();
@@ -234,7 +234,7 @@ private:
         FileLine* const fl = nodep->fileline();
         for (int w = 0; w < nodep->widthWords(); ++w) {
             addWordAssign(nodep, w,
-                          new AstConst{fl, AstConst::SizedEData(), rhsp->num().edataWord(w)});
+                          new AstConst{fl, AstConst::SizedEData{}, rhsp->num().edataWord(w)});
         }
         return true;
     }
@@ -512,7 +512,7 @@ private:
                         if (!ones) {
                             oldvalp = new AstAnd{
                                 lfl,
-                                new AstConst{lfl, AstConst::SizedEData(), maskold.edataWord(w)},
+                                new AstConst{lfl, AstConst::SizedEData{}, maskold.edataWord(w)},
                                 oldvalp};
                         }
 
@@ -746,9 +746,9 @@ private:
                 newp = newp ? new AstOr{fl, newp, eqp} : eqp;
             }
             if (VN_IS(nodep, Neq)) {
-                newp = new AstNeq{fl, new AstConst{fl, AstConst::SizedEData(), 0}, newp};
+                newp = new AstNeq{fl, new AstConst{fl, AstConst::SizedEData{}, 0}, newp};
             } else {
-                newp = new AstEq{fl, new AstConst{fl, AstConst::SizedEData(), 0}, newp};
+                newp = new AstEq{fl, new AstConst{fl, AstConst::SizedEData{}, 0}, newp};
             }
             VL_DO_DANGLING(replaceWithDelete(nodep, newp), nodep);
         }
@@ -768,13 +768,13 @@ private:
                 AstNodeExpr* const eqp = newAstWordSelClone(nodep->lhsp(), w);
                 newp = newp ? new AstOr{fl, newp, eqp} : eqp;
             }
-            newp = new AstNeq{fl, new AstConst{fl, AstConst::SizedEData(), 0}, newp};
+            newp = new AstNeq{fl, new AstConst{fl, AstConst::SizedEData{}, 0}, newp};
             VL_DO_DANGLING(replaceWithDelete(nodep, newp), nodep);
         } else {
             UINFO(8, "    REDOR->EQ " << nodep << endl);
             AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
             AstNodeExpr* const newp = new AstNeq{
-                fl, new AstConst{fl, AstConst::WidthedValue(), longOrQuadWidth(nodep), 0}, lhsp};
+                fl, new AstConst{fl, AstConst::WidthedValue{}, longOrQuadWidth(nodep), 0}, lhsp};
             VL_DO_DANGLING(replaceWithDelete(nodep, newp), nodep);
         }
     }
@@ -798,7 +798,7 @@ private:
                 }
                 newp = newp ? new AstAnd{fl, newp, eqp} : eqp;
             }
-            newp = new AstEq{fl, new AstConst{fl, AstConst::SizedEData(), VL_MASK_E(VL_EDATASIZE)},
+            newp = new AstEq{fl, new AstConst{fl, AstConst::SizedEData{}, VL_MASK_E(VL_EDATASIZE)},
                              newp};
             VL_DO_DANGLING(replaceWithDelete(nodep, newp), nodep);
         } else {
diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp
index e22497eb9..e5e2cb1f9 100644
--- a/src/V3LinkCells.cpp
+++ b/src/V3LinkCells.cpp
@@ -123,7 +123,7 @@ private:
     // METHODS
     V3GraphVertex* vertex(AstNodeModule* nodep) {
         // Return corresponding vertex for this module
-        if (!nodep->user1p()) nodep->user1p(new LinkCellsVertex(&m_graph, nodep));
+        if (!nodep->user1p()) nodep->user1p(new LinkCellsVertex{&m_graph, nodep});
         return nodep->user1u().toGraphVertex();
     }
 
@@ -143,7 +143,7 @@ private:
             // If file not found, make AstNotFoundModule, rather than error out.
             // We'll throw the error when we know the module will really be needed.
             const string prettyName = AstNode::prettyName(modName);
-            V3Parse parser(v3Global.rootp(), m_filterp, m_parseSymp);
+            V3Parse parser{v3Global.rootp(), m_filterp, m_parseSymp};
             // true below -> other simulators treat modules in link-found files as library cells
             parser.parseFile(nodep->fileline(), prettyName, true, "");
             V3Error::abortIfErrors();
@@ -218,8 +218,8 @@ private:
                                                : !topMatch) {  // Any non-specified module is lower
                 // Put under a fake vertex so that the graph ranking won't indicate
                 // this is a top level module
-                if (!m_libVertexp) m_libVertexp = new LibraryVertex(&m_graph);
-                new V3GraphEdge(&m_graph, m_libVertexp, vertex(nodep), 1, false);
+                if (!m_libVertexp) m_libVertexp = new LibraryVertex{&m_graph};
+                new V3GraphEdge{&m_graph, m_libVertexp, vertex(nodep), 1, false};
             }
             // Note AstBind also has iteration on cells
             iterateChildren(nodep);
@@ -236,7 +236,7 @@ private:
         if (modp) {
             if (VN_IS(modp, Iface)) {
                 // Track module depths, so can sort list from parent down to children
-                new V3GraphEdge(&m_graph, vertex(m_modp), vertex(modp), 1, false);
+                new V3GraphEdge{&m_graph, vertex(m_modp), vertex(modp), 1, false};
                 if (!nodep->cellp()) nodep->ifacep(VN_AS(modp, Iface));
             } else if (VN_IS(modp, NotFoundModule)) {  // Will error out later
             } else {
@@ -250,7 +250,7 @@ private:
         // Package Import: We need to do the package before the use of a package
         iterateChildren(nodep);
         UASSERT_OBJ(nodep->packagep(), nodep, "Unlinked package");  // Parser should set packagep
-        new V3GraphEdge(&m_graph, vertex(m_modp), vertex(nodep->packagep()), 1, false);
+        new V3GraphEdge{&m_graph, vertex(m_modp), vertex(nodep->packagep()), 1, false};
     }
 
     void visit(AstBind* nodep) override {
@@ -322,8 +322,8 @@ private:
                             // user1 etc will retain its pre-clone value
                             cellmodp->user2p(otherModp);
                             v3Global.rootp()->addModulesp(otherModp);
-                            new V3GraphEdge(&m_graph, vertex(cellmodp), vertex(otherModp), 1,
-                                            false);
+                            new V3GraphEdge{&m_graph, vertex(cellmodp), vertex(otherModp), 1,
+                                            false};
                         }
                         cellmodp = otherModp;
                         nodep->modp(cellmodp);
@@ -336,7 +336,7 @@ private:
                 } else {  // Non-recursive
                     // Track module depths, so can sort list from parent down to children
                     nodep->modp(cellmodp);
-                    new V3GraphEdge(&m_graph, vertex(m_modp), vertex(cellmodp), 1, false);
+                    new V3GraphEdge{&m_graph, vertex(m_modp), vertex(cellmodp), 1, false};
                 }
             }
         }
@@ -400,17 +400,17 @@ private:
                         if (pinStar) {
                             UINFO(9, "    need .* PORT  " << portp << endl);
                             // Create any not already connected
-                            AstPin* const newp = new AstPin(
+                            AstPin* const newp = new AstPin{
                                 nodep->fileline(), 0, portp->name(),
-                                new AstParseRef(nodep->fileline(), VParseRefExp::PX_TEXT,
-                                                portp->name(), nullptr, nullptr));
+                                new AstParseRef{nodep->fileline(), VParseRefExp::PX_TEXT,
+                                                portp->name(), nullptr, nullptr}};
                             newp->svImplicit(true);
                             nodep->addPinsp(newp);
                         } else {  // warn on the CELL that needs it, not the port
                             nodep->v3warn(PINMISSING,
                                           "Cell has missing pin: " << portp->prettyNameQ());
                             AstPin* const newp
-                                = new AstPin(nodep->fileline(), 0, portp->name(), nullptr);
+                                = new AstPin{nodep->fileline(), 0, portp->name(), nullptr};
                             nodep->addPinsp(newp);
                         }
                     }
@@ -427,21 +427,21 @@ private:
             if (!nodep->hasIfaceVar()) {
                 const string varName
                     = nodep->name() + "__Viftop";  // V3LinkDot looks for this naming
-                AstIfaceRefDType* const idtypep = new AstIfaceRefDType(
-                    nodep->fileline(), nodep->name(), nodep->modp()->name());
+                AstIfaceRefDType* const idtypep = new AstIfaceRefDType{
+                    nodep->fileline(), nodep->name(), nodep->modp()->name()};
                 idtypep->ifacep(nullptr);  // cellp overrides
                 // In the case of arrayed interfaces, we replace cellp when de-arraying in V3Inst
                 idtypep->cellp(nodep);  // Only set when real parent cell known.
                 AstVar* varp;
                 if (nodep->rangep()) {
                     AstNodeArrayDType* const arrp
-                        = new AstUnpackArrayDType(nodep->fileline(), VFlagChildDType(), idtypep,
-                                                  nodep->rangep()->cloneTree(true));
-                    varp = new AstVar(nodep->fileline(), VVarType::IFACEREF, varName,
-                                      VFlagChildDType(), arrp);
+                        = new AstUnpackArrayDType{nodep->fileline(), VFlagChildDType{}, idtypep,
+                                                  nodep->rangep()->cloneTree(true)};
+                    varp = new AstVar{nodep->fileline(), VVarType::IFACEREF, varName,
+                                      VFlagChildDType{}, arrp};
                 } else {
-                    varp = new AstVar(nodep->fileline(), VVarType::IFACEREF, varName,
-                                      VFlagChildDType(), idtypep);
+                    varp = new AstVar{nodep->fileline(), VVarType::IFACEREF, varName,
+                                      VFlagChildDType{}, idtypep};
                 }
                 varp->isIfaceParent(true);
                 nodep->addNextHere(varp);
@@ -504,7 +504,7 @@ private:
                 nodep->unlinkFrBack();
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
             } else if (!foundp) {
-                m_mods.rootp()->insert(nodep->name(), new VSymEnt(&m_mods, nodep));
+                m_mods.rootp()->insert(nodep->name(), new VSymEnt{&m_mods, nodep});
             }
         }
         // if (debug() >= 9) m_mods.dump(cout, "-syms: ");
diff --git a/src/V3LinkInc.cpp b/src/V3LinkInc.cpp
index d6b152881..6f4970486 100644
--- a/src/V3LinkInc.cpp
+++ b/src/V3LinkInc.cpp
@@ -213,11 +213,11 @@ private:
 
         AstAssign* assignp;
         if (VN_IS(nodep, PreSub) || VN_IS(nodep, PostSub)) {
-            assignp = new AstAssign(nodep->fileline(), storetop,
-                                    new AstSub(nodep->fileline(), valuep, newconstp));
+            assignp = new AstAssign{nodep->fileline(), storetop,
+                                    new AstSub{nodep->fileline(), valuep, newconstp}};
         } else {
-            assignp = new AstAssign(nodep->fileline(), storetop,
-                                    new AstAdd(nodep->fileline(), valuep, newconstp));
+            assignp = new AstAssign{nodep->fileline(), storetop,
+                                    new AstAdd{nodep->fileline(), valuep, newconstp}};
         }
         nodep->replaceWith(assignp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -239,8 +239,8 @@ private:
         // Prepare a temporary variable
         FileLine* const fl = backp->fileline();
         const string name = string("__Vincrement") + cvtToStr(++m_modIncrementsNum);
-        AstVar* const varp = new AstVar(fl, VVarType::BLOCKTEMP, name, VFlagChildDType(),
-                                        varrefp->varp()->subDTypep()->cloneTree(true));
+        AstVar* const varp = new AstVar{fl, VVarType::BLOCKTEMP, name, VFlagChildDType{},
+                                        varrefp->varp()->subDTypep()->cloneTree(true)};
         if (m_ftaskp) varp->funcLocal(true);
 
         // Declare the variable
@@ -249,9 +249,9 @@ private:
         // Define what operation will we be doing
         AstNodeExpr* operp;
         if (VN_IS(nodep, PostSub) || VN_IS(nodep, PreSub)) {
-            operp = new AstSub(fl, new AstVarRef(fl, varrefp->varp(), VAccess::READ), newconstp);
+            operp = new AstSub{fl, new AstVarRef{fl, varrefp->varp(), VAccess::READ}, newconstp};
         } else {
-            operp = new AstAdd(fl, new AstVarRef(fl, varrefp->varp(), VAccess::READ), newconstp);
+            operp = new AstAdd{fl, new AstVarRef{fl, varrefp->varp(), VAccess::READ}, newconstp};
         }
 
         if (VN_IS(nodep, PreAdd) || VN_IS(nodep, PreSub)) {
diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp
index 173b90e92..a614834f6 100644
--- a/src/V3LinkJump.cpp
+++ b/src/V3LinkJump.cpp
@@ -105,8 +105,8 @@ private:
         if (VN_IS(underp, JumpLabel)) {
             return VN_AS(underp, JumpLabel);
         } else {  // Move underp stuff to be under a new label
-            AstJumpBlock* const blockp = new AstJumpBlock(nodep->fileline(), nullptr);
-            AstJumpLabel* const labelp = new AstJumpLabel(nodep->fileline(), blockp);
+            AstJumpBlock* const blockp = new AstJumpBlock{nodep->fileline(), nullptr};
+            AstJumpLabel* const labelp = new AstJumpLabel{nodep->fileline(), blockp};
             blockp->labelp(labelp);
 
             VNRelinker repHandle;
@@ -163,21 +163,21 @@ private:
         const string name = string("__Vrepeat") + cvtToStr(m_modRepeatNum++);
         // Spec says value is integral, if negative is ignored
         AstVar* const varp
-            = new AstVar(nodep->fileline(), VVarType::BLOCKTEMP, name, nodep->findSigned32DType());
+            = new AstVar{nodep->fileline(), VVarType::BLOCKTEMP, name, nodep->findSigned32DType()};
         varp->usedLoopIdx(true);
         m_modp->addStmtsp(varp);
-        AstNode* initsp = new AstAssign(
-            nodep->fileline(), new AstVarRef(nodep->fileline(), varp, VAccess::WRITE), countp);
-        AstNode* const decp = new AstAssign(
-            nodep->fileline(), new AstVarRef(nodep->fileline(), varp, VAccess::WRITE),
-            new AstSub(nodep->fileline(), new AstVarRef(nodep->fileline(), varp, VAccess::READ),
-                       new AstConst(nodep->fileline(), 1)));
-        AstNodeExpr* const zerosp = new AstConst(nodep->fileline(), AstConst::Signed32(), 0);
-        AstNodeExpr* const condp = new AstGtS(
-            nodep->fileline(), new AstVarRef(nodep->fileline(), varp, VAccess::READ), zerosp);
+        AstNode* initsp = new AstAssign{
+            nodep->fileline(), new AstVarRef{nodep->fileline(), varp, VAccess::WRITE}, countp};
+        AstNode* const decp = new AstAssign{
+            nodep->fileline(), new AstVarRef{nodep->fileline(), varp, VAccess::WRITE},
+            new AstSub{nodep->fileline(), new AstVarRef{nodep->fileline(), varp, VAccess::READ},
+                       new AstConst{nodep->fileline(), 1}}};
+        AstNodeExpr* const zerosp = new AstConst{nodep->fileline(), AstConst::Signed32{}, 0};
+        AstNodeExpr* const condp = new AstGtS{
+            nodep->fileline(), new AstVarRef{nodep->fileline(), varp, VAccess::READ}, zerosp};
         AstNode* const bodysp = nodep->stmtsp();
         if (bodysp) bodysp->unlinkFrBackWithNext();
-        AstNode* newp = new AstWhile(nodep->fileline(), condp, bodysp, decp);
+        AstNode* newp = new AstWhile{nodep->fileline(), condp, bodysp, decp};
         initsp = initsp->addNext(newp);
         newp = initsp;
         nodep->replaceWith(newp);
@@ -241,14 +241,14 @@ private:
         } else {
             if (funcp && nodep->lhsp()) {
                 // Set output variable to return value
-                nodep->addHereThisAsNext(new AstAssign(
+                nodep->addHereThisAsNext(new AstAssign{
                     nodep->fileline(),
-                    new AstVarRef(nodep->fileline(), VN_AS(funcp->fvarp(), Var), VAccess::WRITE),
-                    nodep->lhsp()->unlinkFrBackWithNext()));
+                    new AstVarRef{nodep->fileline(), VN_AS(funcp->fvarp(), Var), VAccess::WRITE},
+                    nodep->lhsp()->unlinkFrBackWithNext()});
             }
             // Jump to the end of the function call
             AstJumpLabel* const labelp = findAddLabel(m_ftaskp, false);
-            nodep->addHereThisAsNext(new AstJumpGo(nodep->fileline(), labelp));
+            nodep->addHereThisAsNext(new AstJumpGo{nodep->fileline(), labelp});
         }
         nodep->unlinkFrBack();
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
@@ -260,7 +260,7 @@ private:
         } else {
             // Jump to the end of the loop
             AstJumpLabel* const labelp = findAddLabel(m_loopp, false);
-            nodep->addNextHere(new AstJumpGo(nodep->fileline(), labelp));
+            nodep->addNextHere(new AstJumpGo{nodep->fileline(), labelp});
         }
         nodep->unlinkFrBack();
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
@@ -273,7 +273,7 @@ private:
             // Jump to the end of this iteration
             // If a "for" loop then need to still do the post-loop increment
             AstJumpLabel* const labelp = findAddLabel(m_loopp, true);
-            nodep->addNextHere(new AstJumpGo(nodep->fileline(), labelp));
+            nodep->addNextHere(new AstJumpGo{nodep->fileline(), labelp});
         }
         nodep->unlinkFrBack();
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
@@ -295,7 +295,7 @@ private:
         } else if (AstBegin* const beginp = VN_CAST(blockp, Begin)) {
             // Jump to the end of the named block
             AstJumpLabel* const labelp = findAddLabel(beginp, false);
-            nodep->addNextHere(new AstJumpGo(nodep->fileline(), labelp));
+            nodep->addNextHere(new AstJumpGo{nodep->fileline(), labelp});
         } else {
             nodep->v3warn(E_UNSUPPORTED, "Unsupported: disable fork");
         }
diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index ce569c707..127d472a3 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -184,8 +184,8 @@ private:
                 AstNodeExpr* valuep = nullptr;
                 if (nodep->valuep()) {
                     valuep
-                        = new AstAdd(flp, nodep->valuep()->cloneTree(true),
-                                     new AstConst(flp, AstConst::Unsized32(), offset_from_init));
+                        = new AstAdd{flp, nodep->valuep()->cloneTree(true),
+                                     new AstConst(flp, AstConst::Unsized32{}, offset_from_init)};
                 }
                 addp = AstNode::addNext(addp, new AstEnumItem{flp, name, nullptr, valuep});
             }
@@ -262,11 +262,11 @@ private:
                // AstInitial
             else if (m_valueModp) {
                 // Making an AstAssign (vs AstAssignW) to a wire is an error, suppress it
-                FileLine* const newfl = new FileLine(fl);
+                FileLine* const newfl = new FileLine{fl};
                 newfl->warnOff(V3ErrorCode::PROCASSWIRE, true);
                 auto* const assp
-                    = new AstAssign(newfl, new AstVarRef(newfl, nodep->name(), VAccess::WRITE),
-                                    VN_AS(nodep->valuep()->unlinkFrBack(), NodeExpr));
+                    = new AstAssign{newfl, new AstVarRef{newfl, nodep->name(), VAccess::WRITE},
+                                    VN_AS(nodep->valuep()->unlinkFrBack(), NodeExpr)};
                 if (nodep->lifetime().isAutomatic()) {
                     nodep->addNextHere(new AstInitialAutomatic{newfl, assp});
                 } else {
@@ -275,8 +275,8 @@ private:
             }  // 4. Under blocks, it's an initial value to be under an assign
             else {
                 nodep->addNextHere(
-                    new AstAssign(fl, new AstVarRef(fl, nodep->name(), VAccess::WRITE),
-                                  VN_AS(nodep->valuep()->unlinkFrBack(), NodeExpr)));
+                    new AstAssign{fl, new AstVarRef{fl, nodep->name(), VAccess::WRITE},
+                                  VN_AS(nodep->valuep()->unlinkFrBack(), NodeExpr)});
             }
         }
         if (nodep->isIfaceRef() && !nodep->isIfaceParent() && !v3Global.opt.topIfacesSupported()) {
@@ -371,7 +371,7 @@ private:
             // but someday we may be more general
             const bool lvalue = m_varp->isSigUserRWPublic();
             nodep->addStmtsp(
-                new AstVarRef(nodep->fileline(), m_varp, lvalue ? VAccess::WRITE : VAccess::READ));
+                new AstVarRef{nodep->fileline(), m_varp, lvalue ? VAccess::WRITE : VAccess::READ});
         }
     }
 
@@ -405,14 +405,14 @@ private:
                 VL_DO_DANGLING(nodep->deleteTree(), nodep);
                 return;
             } else {
-                defp = new AstTypedef(nodep->fileline(), nodep->name(), nullptr, VFlagChildDType(),
-                                      dtypep);
+                defp = new AstTypedef{nodep->fileline(), nodep->name(), nullptr, VFlagChildDType{},
+                                      dtypep};
                 m_implTypedef.insert(
                     std::make_pair(std::make_pair(nodep->containerp(), defp->name()), defp));
                 backp->addNextHere(defp);
             }
         }
-        nodep->replaceWith(new AstRefDType(nodep->fileline(), defp->name()));
+        nodep->replaceWith(new AstRefDType{nodep->fileline(), defp->name()});
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
 
diff --git a/src/V3MergeCond.cpp b/src/V3MergeCond.cpp
index ebffc3150..31760c61a 100644
--- a/src/V3MergeCond.cpp
+++ b/src/V3MergeCond.cpp
@@ -581,7 +581,7 @@ private:
     static AstNodeExpr* maskLsb(AstNodeExpr* nodep) {
         if (yieldsOneOrZero(nodep)) return nodep;
         // Otherwise apply masking
-        AstConst* const maskp = new AstConst{nodep->fileline(), AstConst::BitTrue()};
+        AstConst* const maskp = new AstConst{nodep->fileline(), AstConst::BitTrue{}};
         // Mask on left, as conventional
         return new AstAnd{nodep->fileline(), maskp, nodep};
     }
@@ -603,12 +603,12 @@ private:
         } else if (const AstAnd* const andp = VN_CAST(rhsp, And)) {
             if (andp->lhsp()->sameTree(m_mgCondp)) {
                 return condTrue ? maskLsb(andp->rhsp()->unlinkFrBack())
-                                : new AstConst{rhsp->fileline(), AstConst::BitFalse()};
+                                : new AstConst{rhsp->fileline(), AstConst::BitFalse{}};
             } else {
                 UASSERT_OBJ(andp->rhsp()->sameTree(m_mgCondp), rhsp,
                             "AstAnd doesn't hold condition expression");
                 return condTrue ? maskLsb(andp->lhsp()->unlinkFrBack())
-                                : new AstConst{rhsp->fileline(), AstConst::BitFalse()};
+                                : new AstConst{rhsp->fileline(), AstConst::BitFalse{}};
             }
         } else if (VN_IS(rhsp, ArraySel) || VN_IS(rhsp, WordSel) || VN_IS(rhsp, VarRef)
                    || VN_IS(rhsp, Const)) {
diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp
index 2d2b5d977..a0e4977db 100644
--- a/src/V3ParseGrammar.cpp
+++ b/src/V3ParseGrammar.cpp
@@ -127,11 +127,11 @@ AstNodeDType* V3ParseGrammar::createArray(AstNodeDType* basep, AstNodeRange* nra
             AstRange* const rangep = VN_CAST(nrangep, Range);
             if (rangep && isPacked) {
                 arrayp
-                    = new AstPackArrayDType{rangep->fileline(), VFlagChildDType(), arrayp, rangep};
+                    = new AstPackArrayDType{rangep->fileline(), VFlagChildDType{}, arrayp, rangep};
             } else if (rangep
                        && (VN_IS(rangep->leftp(), Unbounded)
                            || VN_IS(rangep->rightp(), Unbounded))) {
-                arrayp = new AstQueueDType{nrangep->fileline(), VFlagChildDType(), arrayp,
+                arrayp = new AstQueueDType{nrangep->fileline(), VFlagChildDType{}, arrayp,
                                            rangep->rightp()->cloneTree(true)};
             } else if (rangep) {
                 arrayp = new AstUnpackArrayDType{rangep->fileline(), VFlagChildDType{}, arrayp,
diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp
index 4c0883036..58c756b17 100644
--- a/src/V3Premit.cpp
+++ b/src/V3Premit.cpp
@@ -137,17 +137,17 @@ private:
             ++m_extractedToConstPool;
         } else {
             // Keep as local temporary. Name based on hash of node for output stability.
-            varp = new AstVar(fl, VVarType::STMTTEMP, m_tempNames.get(nodep), nodep->dtypep());
+            varp = new AstVar{fl, VVarType::STMTTEMP, m_tempNames.get(nodep), nodep->dtypep()};
             m_cfuncp->addInitsp(varp);
             // Put assignment before the referencing statement
-            insertBeforeStmt(new AstAssign(fl, new AstVarRef(fl, varp, VAccess::WRITE), nodep));
+            insertBeforeStmt(new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE}, nodep});
         }
 
         // Do not remove VarRefs to this in V3Const
         if (noSubst) varp->noSubst(true);
 
         // Replace node with VarRef to new Var
-        relinker.relink(new AstVarRef(fl, varp, VAccess::READ));
+        relinker.relink(new AstVarRef{fl, varp, VAccess::READ});
     }
 
     // VISITORS
@@ -243,24 +243,24 @@ private:
                     // Then over shifting gives the sign bit, not all zeros
                     // Note *NOT* clean output -- just like normal shift!
                     // Create equivalent of VL_SIGNONES_(node_width)
-                    constzerop = new AstNegate(
+                    constzerop = new AstNegate{
                         nodep->fileline(),
-                        new AstShiftR(nodep->fileline(), nodep->lhsp()->cloneTree(false),
-                                      new AstConst(nodep->fileline(), m1value), nodep->width()));
+                        new AstShiftR{nodep->fileline(), nodep->lhsp()->cloneTree(false),
+                                      new AstConst(nodep->fileline(), m1value), nodep->width()}};
                 } else {
-                    constzerop = new AstConst(nodep->fileline(), AstConst::WidthedValue(),
-                                              nodep->width(), 0);
+                    constzerop = new AstConst{nodep->fileline(), AstConst::WidthedValue{},
+                                              nodep->width(), 0};
                 }
                 constzerop->dtypeFrom(nodep);  // unsigned
 
                 AstNodeExpr* const constwidthp
-                    = new AstConst(nodep->fileline(), AstConst::WidthedValue(),
+                    = new AstConst(nodep->fileline(), AstConst::WidthedValue{},
                                    nodep->rhsp()->widthMin(), m1value);
                 constwidthp->dtypeFrom(nodep->rhsp());  // unsigned
-                AstCond* const newp = new AstCond(
+                AstCond* const newp = new AstCond{
                     nodep->fileline(),
-                    new AstGte(nodep->fileline(), constwidthp, nodep->rhsp()->cloneTree(false)),
-                    nodep, constzerop);
+                    new AstGte{nodep->fileline(), constwidthp, nodep->rhsp()->cloneTree(false)},
+                    nodep, constzerop};
                 replaceHandle.relink(newp);
             }
         }
diff --git a/src/V3Reloop.cpp b/src/V3Reloop.cpp
index 80d9d38ce..75108c134 100644
--- a/src/V3Reloop.cpp
+++ b/src/V3Reloop.cpp
@@ -105,14 +105,14 @@ private:
                     m_mgIndexHi -= m_mgOffset;
                 }
 
-                AstNode* const initp = new AstAssign(fl, new AstVarRef(fl, itp, VAccess::WRITE),
-                                                     new AstConst(fl, m_mgIndexLo));
-                AstNodeExpr* const condp = new AstLte(fl, new AstVarRef(fl, itp, VAccess::READ),
-                                                      new AstConst(fl, m_mgIndexHi));
-                AstNode* const incp = new AstAssign(
-                    fl, new AstVarRef(fl, itp, VAccess::WRITE),
-                    new AstAdd(fl, new AstConst(fl, 1), new AstVarRef(fl, itp, VAccess::READ)));
-                AstWhile* const whilep = new AstWhile(fl, condp, nullptr, incp);
+                AstNode* const initp = new AstAssign{fl, new AstVarRef{fl, itp, VAccess::WRITE},
+                                                     new AstConst{fl, m_mgIndexLo}};
+                AstNodeExpr* const condp = new AstLte{fl, new AstVarRef{fl, itp, VAccess::READ},
+                                                      new AstConst{fl, m_mgIndexHi}};
+                AstNode* const incp = new AstAssign{
+                    fl, new AstVarRef{fl, itp, VAccess::WRITE},
+                    new AstAdd{fl, new AstConst{fl, 1}, new AstVarRef{fl, itp, VAccess::READ}}};
+                AstWhile* const whilep = new AstWhile{fl, condp, nullptr, incp};
                 initp->addNext(whilep);
                 bodyp->replaceWith(initp);
                 whilep->addStmtsp(bodyp);
@@ -121,13 +121,13 @@ private:
                 AstNodeExpr* const offsetp
                     = m_mgOffset == 0 ? nullptr : new AstConst(fl, std::abs(m_mgOffset));
                 AstNodeExpr* const lbitp = m_mgSelLp->bitp();
-                AstNodeExpr* const lvrefp = new AstVarRef(fl, itp, VAccess::READ);
-                lbitp->replaceWith(m_mgOffset > 0 ? new AstAdd(fl, lvrefp, offsetp) : lvrefp);
+                AstNodeExpr* const lvrefp = new AstVarRef{fl, itp, VAccess::READ};
+                lbitp->replaceWith(m_mgOffset > 0 ? new AstAdd{fl, lvrefp, offsetp} : lvrefp);
                 VL_DO_DANGLING(lbitp->deleteTree(), lbitp);
                 if (m_mgSelRp) {  // else constant and no replace
                     AstNodeExpr* const rbitp = m_mgSelRp->bitp();
-                    AstNodeExpr* const rvrefp = new AstVarRef(fl, itp, VAccess::READ);
-                    rbitp->replaceWith(m_mgOffset < 0 ? new AstAdd(fl, rvrefp, offsetp) : rvrefp);
+                    AstNodeExpr* const rvrefp = new AstVarRef{fl, itp, VAccess::READ};
+                    rbitp->replaceWith(m_mgOffset < 0 ? new AstAdd{fl, rvrefp, offsetp} : rvrefp);
                     VL_DO_DANGLING(rbitp->deleteTree(), lbitp);
                 }
                 if (debug() >= 9) initp->dumpTree(cout, "-new: ");
diff --git a/src/V3Simulate.h b/src/V3Simulate.h
index a60b5b35a..08eefad33 100644
--- a/src/V3Simulate.h
+++ b/src/V3Simulate.h
@@ -1025,7 +1025,7 @@ private:
                 if (!m_checkOnly && optimizable()) newValue(portp, fetchValue(pinp));
             }
         }
-        SimStackNode stackNode(nodep, &tconnects);
+        SimStackNode stackNode{nodep, &tconnects};
         // cppcheck-suppress danglingLifetime
         m_callStack.push_back(&stackNode);
         // Clear output variable
diff --git a/src/V3Split.cpp b/src/V3Split.cpp
index a27d1f62c..9eca2f8ca 100644
--- a/src/V3Split.cpp
+++ b/src/V3Split.cpp
@@ -282,17 +282,17 @@ private:
         // This ensures $display's and such remain in proper order
         // We don't prevent splitting out other non-pli statements, however.
         if (!m_pliVertexp) {
-            m_pliVertexp = new SplitPliVertex(&m_graph, nodep);  // m_graph.clear() will delete it
+            m_pliVertexp = new SplitPliVertex{&m_graph, nodep};  // m_graph.clear() will delete it
         }
         for (const auto& vtxp : m_stmtStackps) {
             // Both ways...
-            new SplitScorebdEdge(&m_graph, vtxp, m_pliVertexp);
-            new SplitScorebdEdge(&m_graph, m_pliVertexp, vtxp);
+            new SplitScorebdEdge{&m_graph, vtxp, m_pliVertexp};
+            new SplitScorebdEdge{&m_graph, m_pliVertexp, vtxp};
         }
     }
     void scoreboardPushStmt(AstNode* nodep) {
         // UINFO(9, "    push " << nodep << endl);
-        SplitLogicVertex* const vertexp = new SplitLogicVertex(&m_graph, nodep);
+        SplitLogicVertex* const vertexp = new SplitLogicVertex{&m_graph, nodep};
         m_stmtStackps.push_back(vertexp);
         UASSERT_OBJ(!nodep->user3p(), nodep, "user3p should not be used; cleared in processBlock");
         nodep->user3p(vertexp);
@@ -370,7 +370,7 @@ protected:
 
                 // Create vertexes for variable
                 if (!vscp->user1p()) {
-                    SplitVarStdVertex* const vstdp = new SplitVarStdVertex(&m_graph, vscp);
+                    SplitVarStdVertex* const vstdp = new SplitVarStdVertex{&m_graph, vscp};
                     vscp->user1p(vstdp);
                 }
                 SplitVarStdVertex* const vstdp
@@ -381,15 +381,15 @@ protected:
                     UINFO(4, "     VARREFDLY: " << nodep << endl);
                     // Delayed variable is different from non-delayed variable
                     if (!vscp->user2p()) {
-                        SplitVarPostVertex* const vpostp = new SplitVarPostVertex(&m_graph, vscp);
+                        SplitVarPostVertex* const vpostp = new SplitVarPostVertex{&m_graph, vscp};
                         vscp->user2p(vpostp);
-                        new SplitPostEdge(&m_graph, vstdp, vpostp);
+                        new SplitPostEdge{&m_graph, vstdp, vpostp};
                     }
                     SplitVarPostVertex* const vpostp
                         = reinterpret_cast<SplitVarPostVertex*>(vscp->user2p());
                     // Add edges
                     for (SplitLogicVertex* vxp : m_stmtStackps) {
-                        new SplitLVEdge(&m_graph, vpostp, vxp);
+                        new SplitLVEdge{&m_graph, vpostp, vxp};
                     }
                 } else {  // Nondelayed assignment
                     if (nodep->access().isWriteOrRW()) {
@@ -397,7 +397,7 @@ protected:
                         // with all consumers of the signal
                         UINFO(4, "     VARREFLV: " << nodep << endl);
                         for (SplitLogicVertex* ivxp : m_stmtStackps) {
-                            new SplitLVEdge(&m_graph, vstdp, ivxp);
+                            new SplitLVEdge{&m_graph, vstdp, ivxp};
                         }
                     } else {
                         UINFO(4, "     VARREF:   " << nodep << endl);
@@ -446,7 +446,7 @@ public:
     // METHODS
 protected:
     void makeRvalueEdges(SplitVarStdVertex* vstdp) override {
-        for (SplitLogicVertex* vxp : m_stmtStackps) new SplitRVEdge(&m_graph, vxp, vstdp);
+        for (SplitLogicVertex* vxp : m_stmtStackps) new SplitRVEdge{&m_graph, vxp, vstdp};
     }
 
     void cleanupBlockGraph(AstNode* nodep) {
@@ -503,7 +503,7 @@ protected:
             const uint32_t color = vvertexp->color();
             UASSERT_OBJ(color, nextp, "No node color assigned");
             if (lastOfColor[color]) {
-                new SplitStrictEdge(&m_graph, lastOfColor[color], vvertexp);
+                new SplitStrictEdge{&m_graph, lastOfColor[color], vvertexp};
             }
             lastOfColor[color] = vvertexp;
         }
@@ -709,7 +709,7 @@ public:
             // We don't need to clone m_origAlwaysp->sensesp() here;
             // V3Activate already moved it to a parent node.
             AstAlways* const alwaysp
-                = new AstAlways(m_origAlwaysp->fileline(), VAlwaysKwd::ALWAYS, nullptr, nullptr);
+                = new AstAlways{m_origAlwaysp->fileline(), VAlwaysKwd::ALWAYS, nullptr, nullptr};
             // Put a placeholder node into stmtp to track our position.
             // We'll strip these out after the blocks are fully cloned.
             AstSplitPlaceholder* const placeholderp = makePlaceholderp();
@@ -725,7 +725,7 @@ public:
 
 protected:
     AstSplitPlaceholder* makePlaceholderp() {
-        return new AstSplitPlaceholder(m_origAlwaysp->fileline());
+        return new AstSplitPlaceholder{m_origAlwaysp->fileline()};
     }
 
     void visit(AstNode* nodep) override {
@@ -759,8 +759,8 @@ protected:
             // Clone this if into its set of split blocks
             AstSplitPlaceholder* const if_placeholderp = makePlaceholderp();
             AstSplitPlaceholder* const else_placeholderp = makePlaceholderp();
-            AstIf* const clonep = new AstIf(nodep->fileline(), nodep->condp()->cloneTree(true),
-                                            if_placeholderp, else_placeholderp);
+            AstIf* const clonep = new AstIf{nodep->fileline(), nodep->condp()->cloneTree(true),
+                                            if_placeholderp, else_placeholderp};
             const AstIf* const origp = VN_CAST(nodep, If);
             if (origp) {
                 // Preserve pragmas from unique if's
@@ -881,7 +881,7 @@ protected:
         for (auto it = m_stmtStackps.cbegin(); it != m_stmtStackps.cend(); ++it) {
             const AstNodeIf* const ifNodep = VN_CAST((*it)->nodep(), NodeIf);
             if (ifNodep && (m_curIfConditional != ifNodep)) continue;
-            new SplitRVEdge(&m_graph, *it, vstdp);
+            new SplitRVEdge{&m_graph, *it, vstdp};
         }
     }
 
diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp
index f2eca4fac..dfece3f3c 100644
--- a/src/V3SplitVar.cpp
+++ b/src/V3SplitVar.cpp
@@ -328,14 +328,14 @@ public:
     }
     // Register the location where a variable is used.
     bool tryAdd(AstNode* context, AstVarRef* refp, AstArraySel* selp, int idx, bool ftask) {
-        return addCore(refp, UnpackRef(context, selp, idx, refp->access(), ftask));
+        return addCore(refp, UnpackRef{context, selp, idx, refp->access(), ftask});
     }
     bool tryAdd(AstNode* context, AstVarRef* refp, AstSliceSel* selp, int msb, int lsb,
                 bool ftask) {
-        return addCore(refp, UnpackRef(context, selp, msb, lsb, refp->access(), ftask));
+        return addCore(refp, UnpackRef{context, selp, msb, lsb, refp->access(), ftask});
     }
     bool tryAdd(AstNode* context, AstVarRef* refp, bool ftask) {
-        return addCore(refp, UnpackRef(context, refp, ftask));
+        return addCore(refp, UnpackRef{context, refp, ftask});
     }
 
     // Remove a variable from the list to split
@@ -943,7 +943,7 @@ public:
             }
             UASSERT(refcount >= 0, "refcounut must not be negative");
             if (bitwidth == 0 || refcount == 0) continue;  // Vacant region
-            plan.emplace_back(SplitNewVar(points[i].first, bitwidth));
+            plan.emplace_back(SplitNewVar{points[i].first, bitwidth});
         }
 
         return plan;
@@ -965,7 +965,7 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
             warnNoSplit(nodep, nodep, reason);
             nodep->attrSplitVar(false);
         } else {  // Finally find a good candidate
-            const bool inserted = m_refs.insert(std::make_pair(nodep, PackedVarRef(nodep))).second;
+            const bool inserted = m_refs.insert(std::make_pair(nodep, PackedVarRef{nodep})).second;
             if (inserted) UINFO(3, nodep->prettyNameQ() << " is added to candidate list.\n");
         }
     }
@@ -978,7 +978,7 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
         UASSERT_OBJ(!nodep->classOrPackagep(), nodep,
                     "variable in package must have been dropped beforehand.");
         const AstBasicDType* const basicp = refit->second.basicp();
-        refit->second.append(PackedVarRefEntry(nodep, basicp->lo(), varp->width()),
+        refit->second.append(PackedVarRefEntry{nodep, basicp->lo(), varp->width()},
                              nodep->access());
         UINFO(5, varp->prettyName()
                      << " Entire bit of [" << basicp->lo() << "+:" << varp->width() << "] \n");
@@ -1080,11 +1080,11 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
             AstBasicDType* dtypep;
             switch (basicp->keyword()) {
             case VBasicDTypeKwd::BIT:
-                dtypep = new AstBasicDType{varp->subDTypep()->fileline(), VFlagBitPacked(),
+                dtypep = new AstBasicDType{varp->subDTypep()->fileline(), VFlagBitPacked{},
                                            newvar.bitwidth()};
                 break;
             case VBasicDTypeKwd::LOGIC:
-                dtypep = new AstBasicDType{varp->subDTypep()->fileline(), VFlagLogicPacked(),
+                dtypep = new AstBasicDType{varp->subDTypep()->fileline(), VFlagLogicPacked{},
                                            newvar.bitwidth()};
                 break;
             default: UASSERT_OBJ(false, basicp, "Only bit and logic are allowed");
diff --git a/src/V3Table.cpp b/src/V3Table.cpp
index 0db7f1aba..7269ab9df 100644
--- a/src/V3Table.cpp
+++ b/src/V3Table.cpp
@@ -100,8 +100,8 @@ public:
         v3Global.rootp()->typeTablep()->addTypesp(tableDTypep);
         // Create table initializer (with default value 0)
         AstConst* const defaultp = elemDType->isString()
-                                       ? new AstConst{m_fl, AstConst::String(), ""}
-                                       : new AstConst{m_fl, AstConst::WidthedValue(), width, 0};
+                                       ? new AstConst{m_fl, AstConst::String{}, ""}
+                                       : new AstConst{m_fl, AstConst::WidthedValue{}, width, 0};
         m_initp = new AstInitArray{m_fl, tableDTypep, defaultp};
     }
 
diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp
index 3a3ac25f0..eb76178f8 100644
--- a/src/V3Timing.cpp
+++ b/src/V3Timing.cpp
@@ -510,7 +510,7 @@ private:
                                 new AstConst{flp, AstConst::RealDouble{}, m_timescaleFactor}}};
             } else {
                 valuep = new AstMul{flp, valuep,
-                                    new AstConst{flp, AstConst::Unsized64(),
+                                    new AstConst{flp, AstConst::Unsized64{},
                                                  static_cast<uint64_t>(m_timescaleFactor)}};
             }
         }

From f44cd9cd48af6521472ffa720fb53c3d6475dfbb Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 20 Nov 2022 17:40:38 -0500
Subject: [PATCH 076/156] Internals: Fix constructor style.

---
 src/V3Case.cpp      |  42 +++++++--------
 src/V3Delayed.cpp   |  56 ++++++++++----------
 src/V3Gate.cpp      |  30 +++++------
 src/V3Inst.cpp      |  50 +++++++++---------
 src/V3LinkDot.cpp   | 113 ++++++++++++++++++++--------------------
 src/V3Partition.cpp |  72 +++++++++++++-------------
 src/V3Task.cpp      | 122 ++++++++++++++++++++++----------------------
 src/V3Trace.cpp     |  80 ++++++++++++++---------------
 src/V3Tristate.cpp  |  90 ++++++++++++++++----------------
 src/V3Unknown.cpp   |  92 ++++++++++++++++-----------------
 10 files changed, 373 insertions(+), 374 deletions(-)

diff --git a/src/V3Case.cpp b/src/V3Case.cpp
index 1537a14ee..d2cf2e666 100644
--- a/src/V3Case.cpp
+++ b/src/V3Case.cpp
@@ -176,10 +176,10 @@ private:
                 if (neverItem(nodep, iconstp)) {
                     // X in casez can't ever be executed
                 } else {
-                    V3Number nummask(itemp, iconstp->width());
+                    V3Number nummask{itemp, iconstp->width()};
                     nummask.opBitsNonX(iconstp->num());
                     const uint32_t mask = nummask.toUInt();
-                    V3Number numval(itemp, iconstp->width());
+                    V3Number numval{itemp, iconstp->width()};
                     numval.opBitsOne(iconstp->num());
                     const uint32_t val = numval.toUInt();
 
@@ -291,10 +291,10 @@ private:
             // AstNode* and1p = new AstAnd(cexprp->fileline(), cexprp->cloneTree(false),
             //                            new AstConst(cexprp->fileline(), nummask));
             AstNodeExpr* const and1p
-                = new AstSel(cexprp->fileline(), cexprp->cloneTree(false), msb, 1);
+                = new AstSel{cexprp->fileline(), cexprp->cloneTree(false), msb, 1};
             AstNodeExpr* const eqp
-                = new AstNeq(cexprp->fileline(), new AstConst(cexprp->fileline(), 0), and1p);
-            AstIf* const ifp = new AstIf(cexprp->fileline(), eqp, tree1p, tree0p);
+                = new AstNeq{cexprp->fileline(), new AstConst{cexprp->fileline(), 0}, and1p};
+            AstIf* const ifp = new AstIf{cexprp->fileline(), eqp, tree1p, tree0p};
             ifp->user3(1);  // So we don't bother to clone it
             return ifp;
         }
@@ -346,7 +346,7 @@ private:
              itemp = VN_AS(itemp->nextp(), CaseItem)) {
             if (!itemp->condsp()) {
                 // Default clause.  Just make true, we'll optimize it away later
-                itemp->addCondsp(new AstConst(itemp->fileline(), AstConst::BitTrue()));
+                itemp->addCondsp(new AstConst{itemp->fileline(), AstConst::BitTrue{}});
                 hadDefault = true;
             } else {
                 // Expressioned clause
@@ -364,23 +364,23 @@ private:
                         VL_DANGLING(iconstp);
                         // For simplicity, make expression that is not equal, and let later
                         // optimizations remove it
-                        condp = new AstConst(itemp->fileline(), AstConst::BitFalse());
+                        condp = new AstConst{itemp->fileline(), AstConst::BitFalse{}};
                     } else if (AstInsideRange* const irangep = VN_CAST(icondp, InsideRange)) {
                         // Similar logic in V3Width::visit(AstInside)
                         condp = irangep->newAndFromInside(cexprp, irangep->lhsp()->unlinkFrBack(),
                                                           irangep->rhsp()->unlinkFrBack());
                     } else if (iconstp && iconstp->num().isFourState()
                                && (nodep->casex() || nodep->casez() || nodep->caseInside())) {
-                        V3Number nummask(itemp, iconstp->width());
+                        V3Number nummask{itemp, iconstp->width()};
                         nummask.opBitsNonX(iconstp->num());
-                        V3Number numval(itemp, iconstp->width());
+                        V3Number numval{itemp, iconstp->width()};
                         numval.opBitsOne(iconstp->num());
                         AstNodeExpr* const and1p
-                            = new AstAnd(itemp->fileline(), cexprp->cloneTree(false),
-                                         new AstConst(itemp->fileline(), nummask));
-                        AstNodeExpr* const and2p = new AstAnd(
-                            itemp->fileline(), new AstConst(itemp->fileline(), numval),
-                            new AstConst(itemp->fileline(), nummask));
+                            = new AstAnd{itemp->fileline(), cexprp->cloneTree(false),
+                                         new AstConst{itemp->fileline(), nummask}};
+                        AstNodeExpr* const and2p = new AstAnd{
+                            itemp->fileline(), new AstConst{itemp->fileline(), numval},
+                            new AstConst{itemp->fileline(), nummask}};
                         VL_DO_DANGLING(icondp->deleteTree(), icondp);
                         VL_DANGLING(iconstp);
                         condp = AstEq::newTyped(itemp->fileline(), and1p, and2p);
@@ -393,7 +393,7 @@ private:
                     if (!ifexprp) {
                         ifexprp = condp;
                     } else {
-                        ifexprp = new AstLogOr(itemp->fileline(), ifexprp, condp);
+                        ifexprp = new AstLogOr{itemp->fileline(), ifexprp, condp};
                     }
                 }
                 // Replace expression in tree
@@ -404,8 +404,8 @@ private:
         if (!hadDefault) {
             // If there was no default, add a empty one, this greatly simplifies below code
             // and constant propagation will just eliminate it for us later.
-            nodep->addItemsp(new AstCaseItem(
-                nodep->fileline(), new AstConst(nodep->fileline(), AstConst::BitTrue()), nullptr));
+            nodep->addItemsp(new AstCaseItem{
+                nodep->fileline(), new AstConst{nodep->fileline(), AstConst::BitTrue{}}, nullptr});
         }
         if (debug() >= 9) nodep->dumpTree(cout, "    _comp_COND: ");
         // Now build the IF statement tree
@@ -428,7 +428,7 @@ private:
                 if (++depth > CASE_ENCODER_GROUP_DEPTH) depth = 1;
                 if (depth == 1) {  // First group or starting new group
                     itemnextp = nullptr;
-                    AstIf* const newp = new AstIf(itemp->fileline(), ifexprp->cloneTree(true));
+                    AstIf* const newp = new AstIf{itemp->fileline(), ifexprp->cloneTree(true)};
                     if (groupnextp) {
                         groupnextp->addElsesp(newp);
                     } else {
@@ -438,7 +438,7 @@ private:
                 } else {  // Continue group, modify if condition to OR in this new condition
                     AstNodeExpr* const condp = groupnextp->condp()->unlinkFrBack();
                     groupnextp->condp(
-                        new AstOr(ifexprp->fileline(), condp, ifexprp->cloneTree(true)));
+                        new AstOr{ifexprp->fileline(), condp, ifexprp->cloneTree(true)});
                 }
             }
             {  // Make the new lower IF and attach in the tree
@@ -446,9 +446,9 @@ private:
                 VL_DANGLING(ifexprp);
                 if (depth == CASE_ENCODER_GROUP_DEPTH) {  // End of group - can skip the condition
                     VL_DO_DANGLING(itemexprp->deleteTree(), itemexprp);
-                    itemexprp = new AstConst(itemp->fileline(), AstConst::BitTrue());
+                    itemexprp = new AstConst{itemp->fileline(), AstConst::BitTrue{}};
                 }
-                AstIf* const newp = new AstIf(itemp->fileline(), itemexprp, istmtsp);
+                AstIf* const newp = new AstIf{itemp->fileline(), itemexprp, istmtsp};
                 if (itemnextp) {
                     itemnextp->addElsesp(newp);
                 } else {
diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp
index 6418f7f20..ee78c41c5 100644
--- a/src/V3Delayed.cpp
+++ b/src/V3Delayed.cpp
@@ -156,28 +156,28 @@ private:
             varp = it->second;
         } else {
             if (newdtypep) {
-                varp = new AstVar(oldvarscp->fileline(), VVarType::BLOCKTEMP, name, newdtypep);
+                varp = new AstVar{oldvarscp->fileline(), VVarType::BLOCKTEMP, name, newdtypep};
             } else if (width == 0) {
-                varp = new AstVar(oldvarscp->fileline(), VVarType::BLOCKTEMP, name,
-                                  oldvarscp->varp());
+                varp = new AstVar{oldvarscp->fileline(), VVarType::BLOCKTEMP, name,
+                                  oldvarscp->varp()};
                 varp->dtypeFrom(oldvarscp);
             } else {  // Used for vset and dimensions, so can zero init
-                varp = new AstVar(oldvarscp->fileline(), VVarType::BLOCKTEMP, name,
-                                  VFlagBitPacked(), width);
+                varp = new AstVar{oldvarscp->fileline(), VVarType::BLOCKTEMP, name,
+                                  VFlagBitPacked{}, width};
             }
             addmodp->addStmtsp(varp);
             m_modVarMap.emplace(std::make_pair(addmodp, name), varp);
         }
 
         AstVarScope* const varscp
-            = new AstVarScope(oldvarscp->fileline(), oldvarscp->scopep(), varp);
+            = new AstVarScope{oldvarscp->fileline(), oldvarscp->scopep(), varp};
         oldvarscp->scopep()->addVarsp(varscp);
         return varscp;
     }
 
     AstActive* createActive(AstNode* varrefp) {
         AstActive* const newactp
-            = new AstActive(varrefp->fileline(), "sequentdly", m_activep->sensesp());
+            = new AstActive{varrefp->fileline(), "sequentdly", m_activep->sensesp()};
         // Was addNext(), but addNextHere() avoids a linear search.
         m_activep->addNextHere(newactp);
         return newactp;
@@ -204,7 +204,7 @@ private:
             // Make a new sensitivity list, which is the combination of both blocks
             AstSenItem* const sena = m_activep->sensesp()->sensesp()->cloneTree(true);
             AstSenItem* const senb = oldactivep->sensesp()->sensesp()->cloneTree(true);
-            AstSenTree* const treep = new AstSenTree(m_activep->fileline(), sena);
+            AstSenTree* const treep = new AstSenTree{m_activep->fileline(), sena};
             if (senb) treep->addSensesp(senb);
             if (AstSenTree* const storep = oldactivep->sensesStorep()) {
                 storep->unlinkFrBack();
@@ -265,11 +265,11 @@ private:
                                            + oldvarp->shortName() + "__v" + cvtToStr(modVecNum));
                 AstVarScope* const bitvscp
                     = createVarSc(varrefp->varScopep(), bitvarname, dimp->width(), nullptr);
-                AstAssign* const bitassignp = new AstAssign(
-                    nodep->fileline(), new AstVarRef(nodep->fileline(), bitvscp, VAccess::WRITE),
-                    dimp);
+                AstAssign* const bitassignp = new AstAssign{
+                    nodep->fileline(), new AstVarRef{nodep->fileline(), bitvscp, VAccess::WRITE},
+                    dimp};
                 nodep->addNextHere(bitassignp);
-                dimreadps.push_front(new AstVarRef(nodep->fileline(), bitvscp, VAccess::READ));
+                dimreadps.push_front(new AstVarRef{nodep->fileline(), bitvscp, VAccess::READ});
             }
         }
         //
@@ -285,11 +285,11 @@ private:
                                            + cvtToStr(modVecNum));
                 AstVarScope* const bitvscp
                     = createVarSc(varrefp->varScopep(), bitvarname, lsbvaluep->width(), nullptr);
-                AstAssign* const bitassignp = new AstAssign(
-                    nodep->fileline(), new AstVarRef(nodep->fileline(), bitvscp, VAccess::WRITE),
-                    lsbvaluep);
+                AstAssign* const bitassignp = new AstAssign{
+                    nodep->fileline(), new AstVarRef{nodep->fileline(), bitvscp, VAccess::WRITE},
+                    lsbvaluep};
                 nodep->addNextHere(bitassignp);
-                bitreadp = new AstVarRef(nodep->fileline(), bitvscp, VAccess::READ);
+                bitreadp = new AstVarRef{nodep->fileline(), bitvscp, VAccess::READ};
             }
         }
         //
@@ -303,8 +303,8 @@ private:
                 = (string("__Vdlyvval__") + oldvarp->shortName() + "__v" + cvtToStr(modVecNum));
             AstVarScope* const valvscp
                 = createVarSc(varrefp->varScopep(), valvarname, 0, nodep->rhsp()->dtypep());
-            newlhsp = new AstVarRef(nodep->fileline(), valvscp, VAccess::WRITE);
-            valreadp = new AstVarRef(nodep->fileline(), valvscp, VAccess::READ);
+            newlhsp = new AstVarRef{nodep->fileline(), valvscp, VAccess::WRITE};
+            valreadp = new AstVarRef{nodep->fileline(), valvscp, VAccess::READ};
         }
         //
         //=== Setting/not setting boolean: __Vdlyvset__
@@ -328,9 +328,9 @@ private:
                     nodep->fileline(), new AstVarRef{nodep->fileline(), setvscp, VAccess::WRITE},
                     new AstConst{nodep->fileline(), 0}};
             }
-            AstAssign* const setassignp = new AstAssign(
-                nodep->fileline(), new AstVarRef(nodep->fileline(), setvscp, VAccess::WRITE),
-                new AstConst(nodep->fileline(), AstConst::BitTrue()));
+            AstAssign* const setassignp = new AstAssign{
+                nodep->fileline(), new AstVarRef{nodep->fileline(), setvscp, VAccess::WRITE},
+                new AstConst{nodep->fileline(), AstConst::BitTrue{}}};
             nodep->addNextHere(setassignp);
         }
         if (m_nextDlyp) {  // Tell next assigndly it can share the variable
@@ -344,11 +344,11 @@ private:
         // It also has the nice side effect of assisting cache locality.
         AstNodeExpr* selectsp = varrefp;
         for (int dimension = int(dimreadps.size()) - 1; dimension >= 0; --dimension) {
-            selectsp = new AstArraySel(nodep->fileline(), selectsp, dimreadps[dimension]);
+            selectsp = new AstArraySel{nodep->fileline(), selectsp, dimreadps[dimension]};
         }
         if (bitselp) {
-            selectsp = new AstSel(nodep->fileline(), selectsp, bitreadp,
-                                  bitselp->widthp()->cloneTree(false));
+            selectsp = new AstSel{nodep->fileline(), selectsp, bitreadp,
+                                  bitselp->widthp()->cloneTree(false)};
         }
         // Build "IF (changeit) ...
         UINFO(9, "   For " << setvscp << endl);
@@ -392,14 +392,14 @@ private:
             UASSERT_OBJ(postLogicp, nodep,
                         "Delayed assignment misoptimized; prev var found w/o associated IF");
         } else {
-            postLogicp = new AstIf(nodep->fileline(),
-                                   new AstVarRef(nodep->fileline(), setvscp, VAccess::READ));
+            postLogicp = new AstIf{nodep->fileline(),
+                                   new AstVarRef{nodep->fileline(), setvscp, VAccess::READ}};
             UINFO(9, "     Created " << postLogicp << endl);
             finalp->addStmtsp(postLogicp);
             finalp->user3p(setvscp);  // Remember IF's vset variable
             finalp->user4p(postLogicp);  // and the associated IF, as we may be able to reuse it
         }
-        postLogicp->addThensp(new AstAssign(nodep->fileline(), selectsp, valreadp));
+        postLogicp->addThensp(new AstAssign{nodep->fileline(), selectsp, valreadp});
         if (m_procp->isSuspendable()) {
             FileLine* const flp = nodep->fileline();
             postLogicp->addThensp(new AstAssign{flp, new AstVarRef{flp, setvscp, VAccess::WRITE},
@@ -579,7 +579,7 @@ private:
                     newactp->addStmtsp(postp);
                 }
                 AstVarRef* const newrefp
-                    = new AstVarRef(nodep->fileline(), dlyvscp, VAccess::WRITE);
+                    = new AstVarRef{nodep->fileline(), dlyvscp, VAccess::WRITE};
                 newrefp->user2(true);  // No reason to do it again
                 nodep->replaceWith(newrefp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp
index 628465602..618c6ed3b 100644
--- a/src/V3Gate.cpp
+++ b/src/V3Gate.cpp
@@ -349,7 +349,7 @@ private:
         if (m_scopep) {
             UINFO(5, "   STMT " << nodep << endl);
             // m_activep is null under AstCFunc's, that's ok.
-            m_logicVertexp = new GateLogicVertex(&m_graph, m_scopep, nodep, m_activep, m_inSlow);
+            m_logicVertexp = new GateLogicVertex{&m_graph, m_scopep, nodep, m_activep, m_inSlow};
             if (nonReducibleReason) {
                 m_logicVertexp->clearReducibleAndDedupable(nonReducibleReason);
             } else if (!m_activeReducible) {
@@ -368,7 +368,7 @@ private:
         GateVarVertex* vertexp = reinterpret_cast<GateVarVertex*>(varscp->user1p());
         if (!vertexp) {
             UINFO(6, "New vertex " << varscp << endl);
-            vertexp = new GateVarVertex(&m_graph, m_scopep, varscp);
+            vertexp = new GateVarVertex{&m_graph, m_scopep, varscp};
             varscp->user1p(vertexp);
             if (varscp->varp()->isSigPublic()) {
                 // Public signals shouldn't be changed, pli code might be messing with them
@@ -493,10 +493,10 @@ private:
             // We use weight of one; if we ref the var more than once, when we simplify,
             // the weight will increase
             if (nodep->access().isWriteOrRW()) {
-                new V3GraphEdge(&m_graph, m_logicVertexp, vvertexp, 1);
+                new V3GraphEdge{&m_graph, m_logicVertexp, vvertexp, 1};
             }
             if (nodep->access().isReadOrRW()) {
-                new V3GraphEdge(&m_graph, vvertexp, m_logicVertexp, 1);
+                new V3GraphEdge{&m_graph, vvertexp, m_logicVertexp, 1};
             }
         }
     }
@@ -638,7 +638,7 @@ void GateVisitor::optimizeSignals(bool allowMultiIn) {
                 for (AstNodeVarRef* const refp : rhsVarRefs) {
                     AstVarScope* const newvarscp = refp->varScopep();
                     GateVarVertex* const varvertexp = makeVarVertex(newvarscp);
-                    new V3GraphEdge(&m_graph, varvertexp, consumeVertexp, 1);
+                    new V3GraphEdge{&m_graph, varvertexp, consumeVertexp, 1};
                     // Propagate clock attribute onto generating node
                     varvertexp->propagateAttrClocksFrom(vvertexp);
                 }
@@ -1177,8 +1177,8 @@ private:
         const AstConst* const cwidth = VN_CAST(cur->widthp(), Const);
         if (!pstart || !pwidth || !cstart || !cwidth) return nullptr;  // too complicated
         if (cur->lsbConst() + cur->widthConst() == pre->lsbConst()) {
-            return new AstSel(curVarRefp->fileline(), curVarRefp->cloneTree(false),
-                              cur->lsbConst(), pre->widthConst() + cur->widthConst());
+            return new AstSel{curVarRefp->fileline(), curVarRefp->cloneTree(false),
+                              cur->lsbConst(), pre->widthConst() + cur->widthConst()};
         } else {
             return nullptr;
         }
@@ -1218,9 +1218,9 @@ private:
                             preselp->replaceWith(newselp);
                             VL_DO_DANGLING(preselp->deleteTree(), preselp);
                             // create new rhs for pre assignment
-                            AstNode* const newrhsp = new AstConcat(
+                            AstNode* const newrhsp = new AstConcat{
                                 m_assignp->rhsp()->fileline(), m_assignp->rhsp()->cloneTree(false),
-                                assignp->rhsp()->cloneTree(false));
+                                assignp->rhsp()->cloneTree(false)};
                             AstNode* const oldrhsp = m_assignp->rhsp();
                             oldrhsp->replaceWith(newrhsp);
                             VL_DO_DANGLING(oldrhsp->deleteTree(), oldrhsp);
@@ -1240,7 +1240,7 @@ private:
                                         ledgep = ledgep->inNextp();
                                         GateEitherVertex* const fromvp
                                             = static_cast<GateEitherVertex*>(oedgep->fromp());
-                                        new V3GraphEdge(m_graphp, fromvp, m_logicvp, 1);
+                                        new V3GraphEdge{m_graphp, fromvp, m_logicvp, 1};
                                         VL_DO_DANGLING(oedgep->unlinkDelete(), oedgep);
                                     }
                                 }
@@ -1369,7 +1369,7 @@ private:
             m_total_seen_clk_vectors++;
         }
         const GateClkDecompState* const currState = reinterpret_cast<GateClkDecompState*>(vu.c());
-        GateClkDecompState nextState(currState->m_offset, vsp);
+        GateClkDecompState nextState{currState->m_offset, vsp};
         vvertexp->iterateCurrentOutEdges(*this, VNUser{&nextState});
         if (vsp->varp()->width() > 1) --m_seen_clk_vectors;
         vsp->user2(false);
@@ -1424,17 +1424,17 @@ private:
                     UINFO(9, "CLK DECOMP Connecting - " << assignp->lhsp() << endl);
                     UINFO(9, "                   to - " << m_clk_vsp << endl);
                     AstNode* const rhsp = assignp->rhsp();
-                    rhsp->replaceWith(new AstVarRef(rhsp->fileline(), m_clk_vsp, VAccess::READ));
+                    rhsp->replaceWith(new AstVarRef{rhsp->fileline(), m_clk_vsp, VAccess::READ});
                     while (V3GraphEdge* const edgep = lvertexp->inBeginp()) {
                         VL_DO_DANGLING(edgep->unlinkDelete(), edgep);
                     }
-                    new V3GraphEdge(m_graphp, m_clk_vvertexp, lvertexp, 1);
+                    new V3GraphEdge{m_graphp, m_clk_vvertexp, lvertexp, 1};
                     m_total_decomposed_clk_vectors++;
                 }
             } else {
                 return VNUser{0};
             }
-            GateClkDecompState nextState(clk_offset, currState->m_last_vsp);
+            GateClkDecompState nextState{clk_offset, currState->m_last_vsp};
             return lvertexp->iterateCurrentOutEdges(*this, VNUser{&nextState});
         }
         return VNUser{0};
@@ -1453,7 +1453,7 @@ public:
         m_seen_clk_vectors = 0;
         m_clk_vsp = vvertexp->varScp();
         m_clk_vvertexp = vvertexp;
-        GateClkDecompState nextState(0, m_clk_vsp);
+        GateClkDecompState nextState{0, m_clk_vsp};
         vvertexp->accept(*this, VNUser{&nextState});
     }
 };
diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp
index 47ca87e48..11ceaec21 100644
--- a/src/V3Inst.cpp
+++ b/src/V3Inst.cpp
@@ -76,18 +76,18 @@ private:
             if (nodep->modVarp()->isInoutish()) {
                 nodep->v3fatalSrc("Unsupported: Verilator is a 2-state simulator");
             } else if (nodep->modVarp()->isWritable()) {
-                AstNodeExpr* const rhsp = new AstVarXRef(exprp->fileline(), nodep->modVarp(),
-                                                         m_cellp->name(), VAccess::READ);
-                AstAssignW* const assp = new AstAssignW(exprp->fileline(), exprp, rhsp);
+                AstNodeExpr* const rhsp = new AstVarXRef{exprp->fileline(), nodep->modVarp(),
+                                                         m_cellp->name(), VAccess::READ};
+                AstAssignW* const assp = new AstAssignW{exprp->fileline(), exprp, rhsp};
                 m_cellp->addNextHere(assp);
             } else if (nodep->modVarp()->isNonOutput()) {
                 // Don't bother moving constants now,
                 // we'll be pushing the const down to the cell soon enough.
                 AstNode* const assp
-                    = new AstAssignW(exprp->fileline(),
-                                     new AstVarXRef(exprp->fileline(), nodep->modVarp(),
-                                                    m_cellp->name(), VAccess::WRITE),
-                                     exprp);
+                    = new AstAssignW{exprp->fileline(),
+                                     new AstVarXRef{exprp->fileline(), nodep->modVarp(),
+                                                    m_cellp->name(), VAccess::WRITE},
+                                     exprp};
                 m_cellp->addNextHere(assp);
                 if (debug() >= 9) assp->dumpTree(cout, "     _new: ");
             } else if (nodep->modVarp()->isIfaceRef()
@@ -97,14 +97,14 @@ private:
                                IfaceRefDType))) {
                 // Create an AstAssignVarScope for Vars to Cells so we can
                 // link with their scope later
-                AstNodeExpr* const lhsp = new AstVarXRef(exprp->fileline(), nodep->modVarp(),
-                                                         m_cellp->name(), VAccess::READ);
+                AstNodeExpr* const lhsp = new AstVarXRef{exprp->fileline(), nodep->modVarp(),
+                                                         m_cellp->name(), VAccess::READ};
                 const AstVarRef* const refp = VN_CAST(exprp, VarRef);
                 const AstVarXRef* const xrefp = VN_CAST(exprp, VarXRef);
                 UASSERT_OBJ(refp || xrefp, exprp,
                             "Interfaces: Pin is not connected to a VarRef or VarXRef");
                 AstAssignVarScope* const assp
-                    = new AstAssignVarScope(exprp->fileline(), lhsp, exprp);
+                    = new AstAssignVarScope{exprp->fileline(), lhsp, exprp};
                 m_cellp->addNextHere(assp);
             } else {
                 nodep->v3error("Assigned pin is neither input nor output");
@@ -335,7 +335,7 @@ private:
                                             ? (rangep->elementsConst() - 1 - m_instSelNum)
                                             : m_instSelNum;
                 AstNodeExpr* exprp = VN_AS(nodep->exprp(), NodeExpr)->unlinkFrBack();
-                exprp = new AstArraySel(exprp->fileline(), exprp, arraySelNum);
+                exprp = new AstArraySel{exprp->fileline(), exprp, arraySelNum};
                 nodep->exprp(exprp);
             } else if (expwidth == modwidth) {
                 // NOP: Arrayed instants: widths match so connect to each instance
@@ -358,7 +358,7 @@ private:
                                                  "with output connections to non-wires.");
                     // Note spec allows more complicated matches such as slices and such
                 }
-                exprp = new AstSel(exprp->fileline(), exprp, modwidth * m_instSelNum, modwidth);
+                exprp = new AstSel{exprp->fileline(), exprp, modwidth * m_instSelNum, modwidth};
                 nodep->exprp(exprp);
             } else {
                 nodep->v3fatalSrc("Width mismatch; V3Width should have errored out.");
@@ -382,9 +382,9 @@ private:
                     arrselp->lhsp()->v3error("Unsupported: interface slices");
                 const AstVarRef* const varrefp = VN_CAST(arrselp->lhsp(), VarRef);
                 UASSERT_OBJ(varrefp, arrselp, "No interface varref under array");
-                AstVarXRef* const newp = new AstVarXRef(
+                AstVarXRef* const newp = new AstVarXRef{
                     nodep->fileline(), varrefp->name() + "__BRA__" + index + "__KET__", "",
-                    VAccess::WRITE);
+                    VAccess::WRITE};
                 newp->dtypep(nodep->modVarp()->dtypep());
                 newp->classOrPackagep(varrefp->classOrPackagep());
                 arrselp->addNextHere(newp);
@@ -453,7 +453,7 @@ private:
 
                 const string newname = varrefp->name() + "__BRA__" + cvtToStr(expr_i) + "__KET__";
                 AstVarXRef* const newVarXRefp
-                    = new AstVarXRef(nodep->fileline(), newname, "", VAccess::WRITE);
+                    = new AstVarXRef{nodep->fileline(), newname, "", VAccess::WRITE};
                 newVarXRefp->varp(newp->modVarp());
                 newp->exprp()->unlinkFrBack()->deleteTree();
                 newp->exprp(newVarXRefp);
@@ -517,10 +517,10 @@ public:
             // otherwise done
             if (pinVarp->direction() == VDirection::INPUT
                 && cellp->modp()->unconnectedDrive().isSetTrue()) {
-                pinp->exprp(new AstConst(pinp->fileline(), AstConst::StringToParse(), "'1"));
+                pinp->exprp(new AstConst{pinp->fileline(), AstConst::StringToParse{}, "'1"});
             } else if (pinVarp->direction() == VDirection::INPUT
                        && cellp->modp()->unconnectedDrive().isSetFalse()) {
-                pinp->exprp(new AstConst(pinp->fileline(), AstConst::StringToParse(), "'0"));
+                pinp->exprp(new AstConst{pinp->fileline(), AstConst::StringToParse{}, "'0"});
             } else {
                 return nullptr;
             }
@@ -559,7 +559,7 @@ public:
                    // Prevent name conflict if both tri & non-tri add signals
                    + (forTristate ? "t" : "") + "__" + cellp->name() + "__" + pinp->name());
             AstVar* const newvarp
-                = new AstVar(pinVarp->fileline(), VVarType::MODULETEMP, newvarname, pinVarp);
+                = new AstVar{pinVarp->fileline(), VVarType::MODULETEMP, newvarname, pinVarp};
             // Important to add statement next to cell, in case there is a
             // generate with same named cell
             cellp->addNextHere(newvarp);
@@ -568,19 +568,19 @@ public:
                                     " direct one-to-one connection (without any expression)");
             } else if (pinVarp->isWritable()) {
                 // See also V3Inst
-                AstNodeExpr* rhsp = new AstVarRef(pinp->fileline(), newvarp, VAccess::READ);
+                AstNodeExpr* rhsp = new AstVarRef{pinp->fileline(), newvarp, VAccess::READ};
                 UINFO(5, "pinRecon width " << pinVarp->width() << " >? " << rhsp->width() << " >? "
                                            << pinexprp->width() << endl);
                 rhsp = extendOrSel(pinp->fileline(), rhsp, pinVarp);
-                pinp->exprp(new AstVarRef(newvarp->fileline(), newvarp, VAccess::WRITE));
+                pinp->exprp(new AstVarRef{newvarp->fileline(), newvarp, VAccess::WRITE});
                 AstNodeExpr* const rhsSelp = extendOrSel(pinp->fileline(), rhsp, pinexprp);
-                assignp = new AstAssignW(pinp->fileline(), pinexprp, rhsSelp);
+                assignp = new AstAssignW{pinp->fileline(), pinexprp, rhsSelp};
             } else {
                 // V3 width should have range/extended to make the widths correct
-                assignp = new AstAssignW(pinp->fileline(),
-                                         new AstVarRef(pinp->fileline(), newvarp, VAccess::WRITE),
-                                         pinexprp);
-                pinp->exprp(new AstVarRef(pinexprp->fileline(), newvarp, VAccess::READ));
+                assignp = new AstAssignW{pinp->fileline(),
+                                         new AstVarRef{pinp->fileline(), newvarp, VAccess::WRITE},
+                                         pinexprp};
+                pinp->exprp(new AstVarRef{pinexprp->fileline(), newvarp, VAccess::READ});
             }
             if (assignp) cellp->addNextHere(assignp);
             // if (debug()) pinp->dumpTree(cout, "-  out:");
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index bfc1c33e8..8bfa0fae8 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -289,7 +289,7 @@ public:
     }
     void insertDUnit(AstNetlist* nodep) {
         // $unit on top scope
-        VSymEnt* const symp = new VSymEnt(&m_syms, nodep);
+        VSymEnt* const symp = new VSymEnt{&m_syms, nodep};
         UINFO(9, "      INSERTdunit se" << cvtToHex(symp) << endl);
         symp->parentp(rootEntp());  // Needed so backward search can find name of top module
         symp->fallbackp(nullptr);
@@ -300,7 +300,7 @@ public:
     }
     VSymEnt* insertTopCell(AstNodeModule* nodep, const string& scopename) {
         // Only called on the module at the very top of the hierarchy
-        VSymEnt* const symp = new VSymEnt(&m_syms, nodep);
+        VSymEnt* const symp = new VSymEnt{&m_syms, nodep};
         UINFO(9,
               "      INSERTtop se" << cvtToHex(symp) << "  " << scopename << " " << nodep << endl);
         symp->parentp(rootEntp());  // Needed so backward search can find name of top module
@@ -327,7 +327,7 @@ public:
     VSymEnt* insertCell(VSymEnt* abovep, VSymEnt* modSymp, AstCell* nodep,
                         const string& scopename) {
         UASSERT_OBJ(abovep, nodep, "Null symbol table inserting node");
-        VSymEnt* const symp = new VSymEnt(&m_syms, nodep);
+        VSymEnt* const symp = new VSymEnt{&m_syms, nodep};
         UINFO(9, "      INSERTcel se" << cvtToHex(symp) << "  " << scopename << " above=se"
                                       << cvtToHex(abovep) << " mods=se" << cvtToHex(modSymp)
                                       << " node=" << nodep << endl);
@@ -355,7 +355,7 @@ public:
         // A fake point in the hierarchy, corresponding to an inlined module
         // This references to another Sym, and eventually resolves to a module with a prefix
         UASSERT_OBJ(abovep, nodep, "Null symbol table inserting node");
-        VSymEnt* const symp = new VSymEnt(&m_syms, nodep);
+        VSymEnt* const symp = new VSymEnt{&m_syms, nodep};
         UINFO(9, "      INSERTinl se" << cvtToHex(symp) << "  " << basename << " above=se"
                                       << cvtToHex(abovep) << " mods=se" << cvtToHex(modSymp)
                                       << " node=" << nodep << endl);
@@ -378,7 +378,7 @@ public:
         // Note we fallback to the symbol table of the parent, as we want to find variables there
         // However, cells walk the graph, so cells will appear under the begin/ftask itself
         UASSERT_OBJ(abovep, nodep, "Null symbol table inserting node");
-        VSymEnt* const symp = new VSymEnt(&m_syms, nodep);
+        VSymEnt* const symp = new VSymEnt{&m_syms, nodep};
         UINFO(9, "      INSERTblk se" << cvtToHex(symp) << "  above=se" << cvtToHex(abovep)
                                       << " pkg=" << cvtToHex(classOrPackagep) << "  node=" << nodep
                                       << endl);
@@ -394,7 +394,7 @@ public:
     VSymEnt* insertSym(VSymEnt* abovep, const string& name, AstNode* nodep,
                        AstNodeModule* classOrPackagep) {
         UASSERT_OBJ(abovep, nodep, "Null symbol table inserting node");
-        VSymEnt* const symp = new VSymEnt(&m_syms, nodep);
+        VSymEnt* const symp = new VSymEnt{&m_syms, nodep};
         UINFO(9, "      INSERTsym se" << cvtToHex(symp) << "  name='" << name << "' above=se"
                                       << cvtToHex(abovep) << " pkg=" << cvtToHex(classOrPackagep)
                                       << "  node=" << nodep << endl);
@@ -503,7 +503,7 @@ public:
                 }
                 if (!ok) {
                     const string suggest = suggestSymFallback(ifaceSymp, ifacerefp->modportName(),
-                                                              LinkNodeMatcherModport());
+                                                              LinkNodeMatcherModport{});
                     ifacerefp->modportFileline()->v3error(
                         "Modport not found under interface "
                         << ifacerefp->prettyNameQ(ifacerefp->ifaceName()) << ": "
@@ -753,7 +753,7 @@ class LinkDotFindVisitor final : public VNVisitor {
 
     // METHODS
     void makeImplicitNew(AstClass* nodep) {
-        AstFunc* const newp = new AstFunc(nodep->fileline(), "new", nullptr, nullptr);
+        AstFunc* const newp = new AstFunc{nodep->fileline(), "new", nullptr, nullptr};
         newp->isConstructor(true);
         nodep->addMembersp(newp);
         UINFO(8, "Made implicit new for " << nodep->name() << ": " << nodep << endl);
@@ -1103,11 +1103,11 @@ class LinkDotFindVisitor final : public VNVisitor {
                 if (dtypep) {
                     dtypep->unlinkFrBack();
                 } else {
-                    dtypep = new AstBasicDType(nodep->fileline(), VBasicDTypeKwd::LOGIC);
+                    dtypep = new AstBasicDType{nodep->fileline(), VBasicDTypeKwd::LOGIC};
                 }
                 AstVar* const newvarp
-                    = new AstVar(nodep->fileline(), VVarType::VAR, nodep->name(),
-                                 VFlagChildDType{}, dtypep);  // Not dtype resolved yet
+                    = new AstVar{nodep->fileline(), VVarType::VAR, nodep->name(),
+                                 VFlagChildDType{}, dtypep};  // Not dtype resolved yet
                 newvarp->direction(VDirection::OUTPUT);
                 newvarp->lifetime(VLifetime::AUTOMATIC);
                 newvarp->funcReturn(true);
@@ -1180,7 +1180,7 @@ class LinkDotFindVisitor final : public VNVisitor {
                         findvarp->fileline()->modifyStateInherit(nodep->fileline());
                         if (nodep->getChildDTypep()->numeric().isSigned()
                             && !findvarp->getChildDTypep()->numeric().isSigned()) {
-                            findvarp->getChildDTypep()->numeric(VSigning(true));
+                            findvarp->getChildDTypep()->numeric(VSigning{true});
                         }
                         AstBasicDType* const bdtypep
                             = VN_CAST(findvarp->childDTypep(), BasicDType);
@@ -1424,10 +1424,10 @@ class LinkDotFindVisitor final : public VNVisitor {
         }
         // Type depends on the method used, let V3Width figure it out later
         if (nodep->exprp()) {  // Else empty expression and pretend no "with"
-            const auto indexArgRefp = new AstLambdaArgRef(argFl, name + "__DOT__index", true);
-            const auto valueArgRefp = new AstLambdaArgRef(argFl, name, false);
-            const auto newp = new AstWith(nodep->fileline(), indexArgRefp, valueArgRefp,
-                                          nodep->exprp()->unlinkFrBackWithNext());
+            const auto indexArgRefp = new AstLambdaArgRef{argFl, name + "__DOT__index", true};
+            const auto valueArgRefp = new AstLambdaArgRef{argFl, name, false};
+            const auto newp = new AstWith{nodep->fileline(), indexArgRefp, valueArgRefp,
+                                          nodep->exprp()->unlinkFrBackWithNext()};
             funcrefp->addPinsp(newp);
         }
         nodep->replaceWith(funcrefp->unlinkFrBack());
@@ -1544,9 +1544,9 @@ private:
             UINFO(9, "Defparam cell " << nodep->path() << "." << nodep->name() << " attach-to "
                                       << cellp << "  <= " << exprp << endl);
             // Don't need to check the name of the defparam exists.  V3Param does.
-            AstPin* const pinp = new AstPin(nodep->fileline(),
+            AstPin* const pinp = new AstPin{nodep->fileline(),
                                             -1,  // Pin# not relevant
-                                            nodep->name(), exprp);
+                                            nodep->name(), exprp};
             cellp->addParamsp(pinp);
         }
         VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
@@ -1985,7 +1985,7 @@ private:
             if (!noWarn) {
                 if (nodep->fileline()->warnIsOff(V3ErrorCode::I_DEF_NETTYPE_WIRE)) {
                     const string suggest = m_statep->suggestSymFallback(moduleSymp, nodep->name(),
-                                                                        LinkNodeMatcherVar());
+                                                                        LinkNodeMatcherVar{});
                     nodep->v3error("Signal definition not found, and implicit disabled with "
                                    "`default_nettype: "
                                    << nodep->prettyNameQ() << '\n'
@@ -1996,15 +1996,15 @@ private:
                 // as there could be thousands of these suppressed in large netlists
                 else if (!nodep->fileline()->warnIsOff(V3ErrorCode::IMPLICIT)) {
                     const string suggest = m_statep->suggestSymFallback(moduleSymp, nodep->name(),
-                                                                        LinkNodeMatcherVar());
+                                                                        LinkNodeMatcherVar{});
                     nodep->v3warn(IMPLICIT,
                                   "Signal definition not found, creating implicitly: "
                                       << nodep->prettyNameQ() << '\n'
                                       << (suggest.empty() ? "" : nodep->warnMore() + suggest));
                 }
             }
-            AstVar* const newp = new AstVar(nodep->fileline(), VVarType::WIRE, nodep->name(),
-                                            VFlagLogicPacked{}, 1);
+            AstVar* const newp = new AstVar{nodep->fileline(), VVarType::WIRE, nodep->name(),
+                                            VFlagLogicPacked{}, 1};
             newp->trace(modp->modTrace());
             nodep->varp(newp);
             modp->addStmtsp(newp);
@@ -2184,9 +2184,9 @@ private:
                 }
                 const string suggest
                     = (nodep->param() ? m_statep->suggestSymFlat(m_pinSymp, nodep->name(),
-                                                                 LinkNodeMatcherVarParam())
+                                                                 LinkNodeMatcherVarParam{})
                                       : m_statep->suggestSymFlat(m_pinSymp, nodep->name(),
-                                                                 LinkNodeMatcherVarIO()));
+                                                                 LinkNodeMatcherVarIO{}));
                 nodep->v3warn(PINNOTFOUND,
                               ucfirst(whatp)
                                   << " not found: " << nodep->prettyNameQ() << '\n'
@@ -2286,7 +2286,7 @@ private:
             if (start) {
                 AstNode* newp;
                 if (m_ds.m_dotErr) {
-                    newp = new AstConst(nodep->fileline(), AstConst::BitFalse());
+                    newp = new AstConst{nodep->fileline(), AstConst::BitFalse{}};
                 } else {
                     // RHS is what we're left with
                     newp = nodep->rhsp()->unlinkFrBack();
@@ -2297,8 +2297,8 @@ private:
             } else {  // Dot midpoint
                 AstNodeExpr* newp = nodep->rhsp()->unlinkFrBack();
                 if (m_ds.m_unresolved) {
-                    AstCellRef* const crp = new AstCellRef(nodep->fileline(), nodep->name(),
-                                                           nodep->lhsp()->unlinkFrBack(), newp);
+                    AstCellRef* const crp = new AstCellRef{nodep->fileline(), nodep->name(),
+                                                           nodep->lhsp()->unlinkFrBack(), newp};
                     newp = crp;
                 }
                 nodep->replaceWith(newp);
@@ -2351,8 +2351,8 @@ private:
             && nodep->name() == "index") {
             // 'with' statement's 'item.index'
             iterateChildren(nodep);
-            const auto newp = new AstLambdaArgRef(
-                nodep->fileline(), m_ds.m_unlinkedScopep->name() + "__DOT__index", true);
+            const auto newp = new AstLambdaArgRef{
+                nodep->fileline(), m_ds.m_unlinkedScopep->name() + "__DOT__index", true};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
             return;
@@ -2360,7 +2360,7 @@ private:
             // Found a Var, everything following is membership.  {scope}.{var}.HERE {member}
             AstNodeExpr* const varEtcp = m_ds.m_dotp->lhsp()->unlinkFrBack();
             AstNodeExpr* const newp
-                = new AstMemberSel(nodep->fileline(), varEtcp, VFlagChildDType(), nodep->name());
+                = new AstMemberSel{nodep->fileline(), varEtcp, VFlagChildDType{}, nodep->name()};
             if (m_ds.m_dotErr) {
                 nodep->unlinkFrBack();  // Avoid circular node loop on errors
             } else {
@@ -2462,15 +2462,15 @@ private:
                     m_ds.m_dotSymp = m_statep->getNodeSym(ifacerefp->ifaceViaCellp());
                     m_ds.m_dotPos = DP_SCOPE;
                     ok = true;
-                    AstNode* const newp = new AstVarRef(nodep->fileline(), varp, VAccess::READ);
+                    AstNode* const newp = new AstVarRef{nodep->fileline(), varp, VAccess::READ};
                     nodep->replaceWith(newp);
                     VL_DO_DANGLING(pushDeletep(nodep), nodep);
                 } else if (allowVar) {
                     AstNode* newp;
                     if (m_ds.m_dotText != "") {
                         AstVarXRef* const refp
-                            = new AstVarXRef(nodep->fileline(), nodep->name(), m_ds.m_dotText,
-                                             VAccess::READ);  // lvalue'ness computed later
+                            = new AstVarXRef{nodep->fileline(), nodep->name(), m_ds.m_dotText,
+                                             VAccess::READ};  // lvalue'ness computed later
                         refp->varp(varp);
                         if (varp->attrSplitVar()) {
                             refp->v3warn(
@@ -2490,8 +2490,8 @@ private:
                                 refp->dotted(dotted.substr(0, pos));
                                 newp = refp;
                             } else {
-                                newp = new AstUnlinkedRef(nodep->fileline(), refp, refp->name(),
-                                                          m_ds.m_unlinkedScopep->unlinkFrBack());
+                                newp = new AstUnlinkedRef{nodep->fileline(), refp, refp->name(),
+                                                          m_ds.m_unlinkedScopep->unlinkFrBack()};
                                 m_ds.m_unlinkedScopep = nullptr;
                                 m_ds.m_unresolved = false;
                             }
@@ -2499,9 +2499,8 @@ private:
                             newp = refp;
                         }
                     } else {
-                        AstVarRef* const refp
-                            = new AstVarRef(nodep->fileline(), varp,
-                                            VAccess::READ);  // lvalue'ness computed later
+                        AstVarRef* const refp = new AstVarRef{
+                            nodep->fileline(), varp, VAccess::READ};  // lvalue'ness computed later
                         refp->classOrPackagep(foundp->classOrPackagep());
                         newp = refp;
                     }
@@ -2552,8 +2551,8 @@ private:
                         // iface[vec].modport became CellArrayRef(iface, lsb)
                         // Convert back to SelBit(iface, lsb)
                         UINFO(9, " Array modport to SelBit " << cellarrayrefp << endl);
-                        newp = new AstSelBit(cellarrayrefp->fileline(), newp,
-                                             cellarrayrefp->selp()->unlinkFrBack());
+                        newp = new AstSelBit{cellarrayrefp->fileline(), newp,
+                                             cellarrayrefp->selp()->unlinkFrBack()};
                         newp->user3(true);  // Don't process again
                         VL_DO_DANGLING(cellarrayrefp->unlinkFrBack(), cellarrayrefp);
                         m_ds.m_unlinkedScopep = nullptr;
@@ -2564,7 +2563,7 @@ private:
             } else if (AstEnumItem* const valuep = VN_CAST(foundp->nodep(), EnumItem)) {
                 if (allowVar) {
                     AstNode* const newp
-                        = new AstEnumItemRef(nodep->fileline(), valuep, foundp->classOrPackagep());
+                        = new AstEnumItemRef{nodep->fileline(), valuep, foundp->classOrPackagep()};
                     nodep->replaceWith(newp);
                     VL_DO_DANGLING(pushDeletep(nodep), nodep);
                     ok = true;
@@ -2574,7 +2573,7 @@ private:
                        = VN_CAST(foundp->nodep(), LambdaArgRef)) {
                 if (allowVar) {
                     AstNode* const newp
-                        = new AstLambdaArgRef(nodep->fileline(), argrefp->name(), false);
+                        = new AstLambdaArgRef{nodep->fileline(), argrefp->name(), false};
                     nodep->replaceWith(newp);
                     VL_DO_DANGLING(pushDeletep(nodep), nodep);
                     ok = true;
@@ -2618,7 +2617,7 @@ private:
                     // Create if implicit, and also if error (so only complain once)
                     // Else if a scope is allowed, making a signal won't help error cascade
                     AstVarRef* const newp
-                        = new AstVarRef(nodep->fileline(), nodep->name(), VAccess::READ);
+                        = new AstVarRef{nodep->fileline(), nodep->name(), VAccess::READ};
                     nodep->replaceWith(newp);
                     VL_DO_DANGLING(pushDeletep(nodep), nodep);
                     createImplicitVar(m_curSymp, newp, m_modp, m_modSymp, err);
@@ -2718,7 +2717,7 @@ private:
                 if (!m_statep->forPrearray() && !m_statep->forScopeCreation()) {
                     if (VN_IS(nodep->dtypep(), IfaceRefDType)) {
                         AstVarRef* const newrefp
-                            = new AstVarRef(nodep->fileline(), nodep->varp(), nodep->access());
+                            = new AstVarRef{nodep->fileline(), nodep->varp(), nodep->access()};
                         nodep->replaceWith(newrefp);
                         VL_DO_DANGLING(nodep->deleteTree(), nodep);
                     }
@@ -2743,7 +2742,7 @@ private:
                     nodep->varScopep(vscp);
                     UINFO(7, "         Resolved " << nodep << endl);  // Also prints taskp
                     AstVarRef* const newvscp
-                        = new AstVarRef(nodep->fileline(), vscp, nodep->access());
+                        = new AstVarRef{nodep->fileline(), vscp, nodep->access()};
                     nodep->replaceWith(newvscp);
                     VL_DO_DANGLING(nodep->deleteTree(), nodep);
                     UINFO(9, "         new " << newvscp << endl);  // Also prints taskp
@@ -2800,8 +2799,8 @@ private:
                 AstNodeFTaskRef* const newftaskp = nodep->cloneTree(false);
                 newftaskp->dotted(m_ds.m_dotText);
                 AstNode* const newp
-                    = new AstUnlinkedRef(nodep->fileline(), newftaskp, nodep->name(),
-                                         m_ds.m_unlinkedScopep->unlinkFrBack());
+                    = new AstUnlinkedRef{nodep->fileline(), newftaskp, nodep->name(),
+                                         m_ds.m_unlinkedScopep->unlinkFrBack()};
                 m_ds.m_unlinkedScopep = nullptr;
                 m_ds.m_unresolved = false;
                 nodep->replaceWith(newp);
@@ -2815,8 +2814,8 @@ private:
             AstNodeExpr* const varEtcp = m_ds.m_dotp->lhsp()->unlinkFrBack();
             AstNodeExpr* argsp = nullptr;
             if (nodep->pinsp()) argsp = nodep->pinsp()->unlinkFrBackWithNext();
-            AstNode* const newp = new AstMethodCall(nodep->fileline(), varEtcp, VFlagChildDType(),
-                                                    nodep->name(), argsp);
+            AstNode* const newp = new AstMethodCall{nodep->fileline(), varEtcp, VFlagChildDType{},
+                                                    nodep->name(), argsp};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
             return;
@@ -2897,8 +2896,8 @@ private:
                         if (v3Global.opt.bboxSys()) {
                             AstNode* newp;
                             if (VN_IS(nodep, FuncRef)) {
-                                newp = new AstConst(nodep->fileline(), AstConst::StringToParse(),
-                                                    "'0");
+                                newp = new AstConst{nodep->fileline(), AstConst::StringToParse{},
+                                                    "'0"};
                             } else {
                                 AstNode* outp = nullptr;
                                 while (nodep->pinsp()) {
@@ -2910,7 +2909,7 @@ private:
                                     }
                                     outp = AstNode::addNext(outp, addp);
                                 }
-                                newp = new AstSysIgnore(nodep->fileline(), outp);
+                                newp = new AstSysIgnore{nodep->fileline(), outp};
                                 newp->dtypep(nodep->dtypep());
                             }
                             nodep->replaceWith(newp);
@@ -2922,14 +2921,14 @@ private:
                         }
                     } else {
                         const string suggest = m_statep->suggestSymFallback(
-                            dotSymp, nodep->name(), LinkNodeMatcherFTask());
+                            dotSymp, nodep->name(), LinkNodeMatcherFTask{});
                         nodep->v3error("Can't find definition of task/function: "
                                        << nodep->prettyNameQ() << '\n'
                                        << (suggest.empty() ? "" : nodep->warnMore() + suggest));
                     }
                 } else {
                     const string suggest = m_statep->suggestSymFallback(dotSymp, nodep->name(),
-                                                                        LinkNodeMatcherFTask());
+                                                                        LinkNodeMatcherFTask{});
                     nodep->v3error("Can't find definition of "
                                    << AstNode::prettyNameQ(baddot) << " in dotted task/function: '"
                                    << nodep->dotted() + "." + nodep->prettyName() << "'\n"
@@ -2968,7 +2967,7 @@ private:
         if (m_ds.m_unresolved && m_ds.m_dotPos == DP_SCOPE) {
             AstNodeExpr* const exprp = nodep->bitp()->unlinkFrBack();
             AstCellArrayRef* const newp
-                = new AstCellArrayRef(nodep->fileline(), nodep->fromp()->name(), exprp);
+                = new AstCellArrayRef{nodep->fileline(), nodep->fromp()->name(), exprp};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         }
@@ -3123,8 +3122,8 @@ private:
                 AstNode* const itemp = it->second->nodep();
                 if (!nodep->findMember(it->first)) {
                     if (AstEnumItem* const aitemp = VN_CAST(itemp, EnumItem)) {
-                        AstEnumItemRef* const newp = new AstEnumItemRef(
-                            aitemp->fileline(), aitemp, it->second->classOrPackagep());
+                        AstEnumItemRef* const newp = new AstEnumItemRef{
+                            aitemp->fileline(), aitemp, it->second->classOrPackagep()};
                         UINFO(8, "Class import noderef '" << it->first << "' " << newp << endl);
                         nodep->addMembersp(newp);
                     }
diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp
index 18744fffc..a49b98f7f 100644
--- a/src/V3Partition.cpp
+++ b/src/V3Partition.cpp
@@ -769,7 +769,7 @@ public:
         // For each node, record the critical path cost from the start
         // of the graph through the end of the node.
         std::unordered_map<const V3GraphVertex*, uint32_t> critPaths;
-        GraphStreamUnordered serialize(m_graphp);
+        GraphStreamUnordered serialize{m_graphp};
         for (const V3GraphVertex* vertexp; (vertexp = serialize.nextp());) {
             ++m_vertexCount;
             uint32_t cpCostToHere = 0;
@@ -1110,7 +1110,7 @@ private:
     }
 
 public:
-    static void selfTest() { PartPropagateCpSelfTest().go(); }
+    static void selfTest() { PartPropagateCpSelfTest{}.go(); }
 };
 
 // Merge edges from a LogicMtask.
@@ -1731,9 +1731,9 @@ private:
         V3Graph mtasks;
         LogicMTask* lastp = nullptr;
         for (unsigned i = 0; i < chain_len; ++i) {
-            LogicMTask* const mtp = new LogicMTask(&mtasks, nullptr);
+            LogicMTask* const mtp = new LogicMTask{&mtasks, nullptr};
             mtp->setCost(1);
-            if (lastp) new MTaskEdge(&mtasks, lastp, mtp, 1);
+            if (lastp) new MTaskEdge{&mtasks, lastp, mtp, 1};
             lastp = mtp;
         }
         partInitCriticalPaths(&mtasks);
@@ -1741,12 +1741,12 @@ private:
         // Since slowAsserts mode is *expected* to cause N^2 runtime, and the
         // intent of this test is to demonstrate better-than-N^2 runtime, disable
         // slowAsserts.
-        PartContraction ec(&mtasks,
+        PartContraction ec{&mtasks,
                            // Any CP limit >chain_len should work:
-                           chain_len * 2, false /* slowAsserts */);
+                           chain_len * 2, false /* slowAsserts */};
         ec.go();
 
-        PartParallelismEst check(&mtasks);
+        PartParallelismEst check{&mtasks};
         check.traverse();
 
         const uint64_t endUsecs = V3Os::timeUsecs();
@@ -1780,26 +1780,26 @@ private:
     static void selfTestX() {
         // NOTE: To get a dot file run with --debugi-V3Partition 4 or more.
         V3Graph mtasks;
-        LogicMTask* const centerp = new LogicMTask(&mtasks, nullptr);
+        LogicMTask* const centerp = new LogicMTask{&mtasks, nullptr};
         centerp->setCost(1);
         unsigned i;
         for (i = 0; i < 50; ++i) {
-            LogicMTask* const mtp = new LogicMTask(&mtasks, nullptr);
+            LogicMTask* const mtp = new LogicMTask{&mtasks, nullptr};
             mtp->setCost(1);
             // Edge from every input -> centerp
-            new MTaskEdge(&mtasks, mtp, centerp, 1);
+            new MTaskEdge{&mtasks, mtp, centerp, 1};
         }
         for (i = 0; i < 50; ++i) {
-            LogicMTask* const mtp = new LogicMTask(&mtasks, nullptr);
+            LogicMTask* const mtp = new LogicMTask{&mtasks, nullptr};
             mtp->setCost(1);
             // Edge from centerp -> every output
-            new MTaskEdge(&mtasks, centerp, mtp, 1);
+            new MTaskEdge{&mtasks, centerp, mtp, 1};
         }
 
         partInitCriticalPaths(&mtasks);
-        PartContraction(&mtasks, 20, true).go();
+        PartContraction{&mtasks, 20, true}.go();
 
-        PartParallelismEst check(&mtasks);
+        PartParallelismEst check{&mtasks};
         check.traverse();
 
         // Checking exact values here is maybe overly precise.  What we're
@@ -2033,7 +2033,7 @@ public:
         // Rank the graph. DGS is faster than V3GraphAlg's recursive rank, and also allows us to
         // set up the OrderLogicVertex -> LogicMTask map at the same time.
         {
-            GraphStreamUnordered serialize(m_mtasksp);
+            GraphStreamUnordered serialize{m_mtasksp};
             while (LogicMTask* const mtaskp
                    = const_cast<LogicMTask*>(static_cast<const LogicMTask*>(serialize.nextp()))) {
                 // Compute and assign rank
@@ -2382,7 +2382,7 @@ public:
     // Pack an MTasks from given graph into m_nThreads threads, return the schedule.
     const ThreadSchedule pack(const V3Graph& mtaskGraph) {
         // The result
-        ThreadSchedule schedule(m_nThreads);
+        ThreadSchedule schedule{m_nThreads};
 
         // Time each thread is occupied until
         std::vector<uint32_t> busyUntil(m_nThreads, 0);
@@ -2475,22 +2475,22 @@ public:
     // SELF TEST
     static void selfTest() {
         V3Graph graph;
-        ExecMTask* const t0 = new ExecMTask(&graph, nullptr, 0);
+        ExecMTask* const t0 = new ExecMTask{&graph, nullptr, 0};
         t0->cost(1000);
         t0->priority(1100);
-        ExecMTask* const t1 = new ExecMTask(&graph, nullptr, 1);
+        ExecMTask* const t1 = new ExecMTask{&graph, nullptr, 1};
         t1->cost(100);
         t1->priority(100);
-        ExecMTask* const t2 = new ExecMTask(&graph, nullptr, 2);
+        ExecMTask* const t2 = new ExecMTask{&graph, nullptr, 2};
         t2->cost(100);
         t2->priority(100);
 
-        new V3GraphEdge(&graph, t0, t1, 1);
-        new V3GraphEdge(&graph, t0, t2, 1);
+        new V3GraphEdge{&graph, t0, t1, 1};
+        new V3GraphEdge{&graph, t0, t2, 1};
 
-        PartPackMTasks packer(2,  // Threads
+        PartPackMTasks packer{2,  // Threads
                               3,  // Sandbag numerator
-                              10);  // Sandbag denom
+                              10};  // Sandbag denom
         const ThreadSchedule& schedule = packer.pack(graph);
 
         UASSERT_SELFTEST(size_t, schedule.threads.size(), 2);
@@ -2748,7 +2748,7 @@ void V3Partition::go(V3Graph* mtasksp) {
 
     // Merge nodes that could present data hazards; see comment within.
     {
-        PartFixDataHazards(m_orderGraphp, mtasksp).go();
+        PartFixDataHazards{m_orderGraphp, mtasksp}.go();
         V3Partition::debugMTaskGraphStats(mtasksp, "hazards");
         hashGraphDebug(mtasksp, "mtasksp after fixDataHazards()");
     }
@@ -2791,10 +2791,10 @@ void V3Partition::go(V3Graph* mtasksp) {
     // Some tests disable this, hence the test on threadsCoarsen().
     // Coarsening is always enabled in production.
     if (v3Global.opt.threadsCoarsen()) {
-        PartContraction(mtasksp, cpLimit,
+        PartContraction{mtasksp, cpLimit,
                         // --debugPartition is used by tests
                         // to enable slow assertions.
-                        v3Global.opt.debugPartition())
+                        v3Global.opt.debugPartition()}
             .go();
         V3Partition::debugMTaskGraphStats(mtasksp, "contraction");
     }
@@ -3011,7 +3011,7 @@ static void finalizeCosts(V3Graph* execMTaskGraphp) {
             UINFO(6, "Removing zero-cost " << mtp->name() << endl);
             for (V3GraphEdge* inp = mtp->inBeginp(); inp; inp = inp->inNextp()) {
                 for (V3GraphEdge* outp = mtp->outBeginp(); outp; outp = outp->outNextp()) {
-                    new V3GraphEdge(execMTaskGraphp, inp->fromp(), outp->top(), 1);
+                    new V3GraphEdge{execMTaskGraphp, inp->fromp(), outp->top(), 1};
                 }
             }
             VL_DO_DANGLING(mtp->unlinkDelete(execMTaskGraphp), mtp);
@@ -3052,7 +3052,7 @@ static void addMTaskToFunction(const ThreadSchedule& schedule, const uint32_t th
 
     // Helper function to make the code a bit more legible
     const auto addStrStmt = [=](const string& stmt) -> void {  //
-        funcp->addStmtsp(new AstCStmt(fl, stmt));
+        funcp->addStmtsp(new AstCStmt{fl, stmt});
     };
 
     if (const uint32_t nDependencies = schedule.crossThreadDependencies(mtaskp)) {
@@ -3061,8 +3061,8 @@ static void addMTaskToFunction(const ThreadSchedule& schedule, const uint32_t th
         const string name = "__Vm_mtaskstate_" + cvtToStr(mtaskp->id());
         AstBasicDType* const mtaskStateDtypep
             = v3Global.rootp()->typeTablep()->findBasicDType(fl, VBasicDTypeKwd::MTASKSTATE);
-        AstVar* const varp = new AstVar(fl, VVarType::MODULETEMP, name, mtaskStateDtypep);
-        varp->valuep(new AstConst(fl, nDependencies));
+        AstVar* const varp = new AstVar{fl, VVarType::MODULETEMP, name, mtaskStateDtypep};
+        varp->valuep(new AstConst{fl, nDependencies});
         varp->protect(false);  // Do not protect as we still have references in AstText
         modp->addStmtsp(varp);
         // For now, reference is still via text bashing
@@ -3124,7 +3124,7 @@ static const std::vector<AstCFunc*> createThreadFunctions(const ThreadSchedule&
         if (thread.empty()) continue;
         const uint32_t threadId = schedule.threadId(thread.front());
         const string name{"__Vthread__" + tag + "__" + cvtToStr(threadId)};
-        AstCFunc* const funcp = new AstCFunc(fl, name, nullptr, "void");
+        AstCFunc* const funcp = new AstCFunc{fl, name, nullptr, "void"};
         modp->addStmtsp(funcp);
         funcps.push_back(funcp);
         funcp->isStatic(true);  // Uses void self pointer, so static and hand rolled
@@ -3166,10 +3166,10 @@ static void addThreadStartToExecGraph(AstExecGraph* const execGraphp,
 
     // Add thread function invocations to execGraph
     const auto addStrStmt = [=](const string& stmt) -> void {  //
-        execGraphp->addStmtsp(new AstCStmt(fl, stmt));
+        execGraphp->addStmtsp(new AstCStmt{fl, stmt});
     };
     const auto addTextStmt = [=](const string& text) -> void {
-        execGraphp->addStmtsp(new AstText(fl, text, /* tracking: */ true));
+        execGraphp->addStmtsp(new AstText{fl, text, /* tracking: */ true});
     };
 
     addStrStmt("vlSymsp->__Vm_even_cycle__" + tag + " = !vlSymsp->__Vm_even_cycle__" + tag
@@ -3181,11 +3181,11 @@ static void addThreadStartToExecGraph(AstExecGraph* const execGraphp,
         if (i != last) {
             // The first N-1 will run on the thread pool.
             addTextStmt("vlSymsp->__Vm_threadPoolp->workerp(" + cvtToStr(i) + ")->addTask(");
-            execGraphp->addStmtsp(new AstAddrOfCFunc(fl, funcp));
+            execGraphp->addStmtsp(new AstAddrOfCFunc{fl, funcp});
             addTextStmt(", vlSelf, vlSymsp->__Vm_even_cycle__" + tag + ");\n");
         } else {
             // The last will run on the main thread.
-            AstCCall* const callp = new AstCCall(fl, funcp);
+            AstCCall* const callp = new AstCCall{fl, funcp};
             callp->dtypeSetVoid();
             callp->argTypes("vlSelf, vlSymsp->__Vm_even_cycle__" + tag);
             execGraphp->addStmtsp(callp->makeStmt());
@@ -3203,7 +3203,7 @@ static void implementExecGraph(AstExecGraph* const execGraphp) {
 
     // Schedule the mtasks: statically associate each mtask with a thread,
     // and determine the order in which each thread will runs its mtasks.
-    const ThreadSchedule& schedule = PartPackMTasks().pack(*execGraphp->depGraphp());
+    const ThreadSchedule& schedule = PartPackMTasks{}.pack(*execGraphp->depGraphp());
 
     // Create a function to be run by each thread. Note this moves all AstMTaskBody nodes form the
     // AstExecGrap into the AstCFunc created
diff --git a/src/V3Task.cpp b/src/V3Task.cpp
index 3c30da6d7..c8d0ef3fb 100644
--- a/src/V3Task.cpp
+++ b/src/V3Task.cpp
@@ -163,7 +163,7 @@ private:
         }
     }
     TaskFTaskVertex* getFTaskVertex(AstNodeFTask* nodep) {
-        if (!nodep->user4p()) nodep->user4p(new TaskFTaskVertex(&m_callGraph, nodep));
+        if (!nodep->user4p()) nodep->user4p(new TaskFTaskVertex{&m_callGraph, nodep});
         return static_cast<TaskFTaskVertex*>(nodep->user4u().toGraphVertex());
     }
 
@@ -204,7 +204,7 @@ private:
         }
         // We make multiple edges if a task is called multiple times from another task.
         UASSERT_OBJ(nodep->taskp(), nodep, "Unlinked task");
-        new TaskEdge(&m_callGraph, m_curVxp, getFTaskVertex(nodep->taskp()));
+        new TaskEdge{&m_callGraph, m_curVxp, getFTaskVertex(nodep->taskp())};
     }
     void visit(AstNodeFTask* nodep) override {
         UINFO(9, "  TASK " << nodep << endl);
@@ -276,7 +276,7 @@ private:
 public:
     // CONSTRUCTORS
     explicit TaskStateVisitor(AstNetlist* nodep) {
-        m_curVxp = new TaskCodeVertex(&m_callGraph);
+        m_curVxp = new TaskCodeVertex{&m_callGraph};
         AstNode::user3ClearTree();
         AstNode::user4ClearTree();
         //
@@ -369,20 +369,20 @@ private:
     // METHODS
 
     AstVarScope* createFuncVar(AstCFunc* funcp, const string& name, AstVar* examplep) {
-        AstVar* const newvarp = new AstVar(funcp->fileline(), VVarType::BLOCKTEMP, name, examplep);
+        AstVar* const newvarp = new AstVar{funcp->fileline(), VVarType::BLOCKTEMP, name, examplep};
         newvarp->funcLocal(true);
         funcp->addInitsp(newvarp);
-        AstVarScope* const newvscp = new AstVarScope(funcp->fileline(), m_scopep, newvarp);
+        AstVarScope* const newvscp = new AstVarScope{funcp->fileline(), m_scopep, newvarp};
         m_scopep->addVarsp(newvscp);
         return newvscp;
     }
     AstVarScope* createInputVar(AstCFunc* funcp, const string& name, VBasicDTypeKwd kwd) {
         AstVar* const newvarp
-            = new AstVar(funcp->fileline(), VVarType::BLOCKTEMP, name, funcp->findBasicDType(kwd));
+            = new AstVar{funcp->fileline(), VVarType::BLOCKTEMP, name, funcp->findBasicDType(kwd)};
         newvarp->funcLocal(true);
         newvarp->direction(VDirection::INPUT);
         funcp->addArgsp(newvarp);
-        AstVarScope* const newvscp = new AstVarScope(funcp->fileline(), m_scopep, newvarp);
+        AstVarScope* const newvscp = new AstVarScope{funcp->fileline(), m_scopep, newvarp};
         m_scopep->addVarsp(newvscp);
         return newvscp;
     }
@@ -425,7 +425,7 @@ private:
         AstNode* const newbodysp
             = AstNode::cloneTreeNull(refp->taskp()->stmtsp(), true);  // Maybe nullptr
         AstNode* const beginp
-            = new AstComment(refp->fileline(), string("Function: ") + refp->name(), true);
+            = new AstComment{refp->fileline(), string("Function: ") + refp->name(), true};
         if (newbodysp) beginp->addNext(newbodysp);
         if (debug() >= 9) beginp->dumpTreeAndNext(cout, "-newbegi:");
         //
@@ -478,9 +478,9 @@ private:
                     AstVarScope* const tempvscp
                         = createVarScope(portp, namePrefix + "__" + portp->shortName());
                     portp->user2p(tempvscp);
-                    AstAssign* const assp = new AstAssign(
+                    AstAssign* const assp = new AstAssign{
                         pinp->fileline(), pinp,
-                        new AstVarRef(tempvscp->fileline(), tempvscp, VAccess::READ));
+                        new AstVarRef{tempvscp->fileline(), tempvscp, VAccess::READ}};
                     assp->fileline()->modifyWarnOff(V3ErrorCode::BLKSEQ,
                                                     true);  // Ok if in <= block
                     // Put assignment BEHIND of all other statements
@@ -490,9 +490,9 @@ private:
                     AstVarScope* const inVscp
                         = createVarScope(portp, namePrefix + "__" + portp->shortName());
                     portp->user2p(inVscp);
-                    AstAssign* const assp = new AstAssign(
+                    AstAssign* const assp = new AstAssign{
                         pinp->fileline(),
-                        new AstVarRef(inVscp->fileline(), inVscp, VAccess::WRITE), pinp);
+                        new AstVarRef{inVscp->fileline(), inVscp, VAccess::WRITE}, pinp};
                     assp->fileline()->modifyWarnOff(V3ErrorCode::BLKSEQ,
                                                     true);  // Ok if in <= block
                     // Put assignment in FRONT of all other statements
@@ -542,20 +542,20 @@ private:
         UASSERT_OBJ(cfuncp, refp, "No non-inline task associated with this task call?");
         //
         AstNode* const beginp
-            = new AstComment(refp->fileline(), string("Function: ") + refp->name(), true);
+            = new AstComment{refp->fileline(), string("Function: ") + refp->name(), true};
         AstNodeCCall* ccallp;
         if (VN_IS(refp, New)) {
-            AstCNew* const cnewp = new AstCNew(refp->fileline(), cfuncp);
+            AstCNew* const cnewp = new AstCNew{refp->fileline(), cfuncp};
             cnewp->dtypep(refp->dtypep());
             ccallp = cnewp;
             // Parent AstNew will replace with this CNew
             cnewpr = cnewp;
         } else if (const AstMethodCall* const mrefp = VN_CAST(refp, MethodCall)) {
-            ccallp = new AstCMethodCall(refp->fileline(), mrefp->fromp()->unlinkFrBack(), cfuncp);
+            ccallp = new AstCMethodCall{refp->fileline(), mrefp->fromp()->unlinkFrBack(), cfuncp};
             ccallp->dtypeSetVoid();
             beginp->addNext(ccallp->makeStmt());
         } else {
-            ccallp = new AstCCall(refp->fileline(), cfuncp);
+            ccallp = new AstCCall{refp->fileline(), cfuncp};
             ccallp->dtypeSetVoid();
             beginp->addNext(ccallp->makeStmt());
         }
@@ -598,10 +598,10 @@ private:
                     AstVarScope* const newvscp
                         = createVarScope(portp, namePrefix + "__" + portp->shortName());
                     portp->user2p(newvscp);
-                    pinp->replaceWith(new AstVarRef(newvscp->fileline(), newvscp, VAccess::WRITE));
-                    AstAssign* const assp = new AstAssign(
+                    pinp->replaceWith(new AstVarRef{newvscp->fileline(), newvscp, VAccess::WRITE});
+                    AstAssign* const assp = new AstAssign{
                         pinp->fileline(), pinp,
-                        new AstVarRef(newvscp->fileline(), newvscp, VAccess::READ));
+                        new AstVarRef{newvscp->fileline(), newvscp, VAccess::READ}};
                     assp->fileline()->modifyWarnOff(V3ErrorCode::BLKSEQ,
                                                     true);  // Ok if in <= block
                     // Put assignment BEHIND of all other statements
@@ -619,8 +619,8 @@ private:
             UASSERT_OBJ(snp, refp, "Missing scoping context");
             ccallp->addArgsp(snp);
             // __Vfilenamep
-            ccallp->addArgsp(new AstCExpr(refp->fileline(),
-                                          "\"" + refp->fileline()->filename() + "\"", 64, true));
+            ccallp->addArgsp(new AstCExpr{refp->fileline(),
+                                          "\"" + refp->fileline()->filename() + "\"", 64, true});
             // __Vlineno
             ccallp->addArgsp(new AstConst(refp->fileline(), refp->fileline()->lineno()));
         }
@@ -635,7 +635,7 @@ private:
             ccallp->addArgsp(exprp);
         }
 
-        if (outvscp) ccallp->addArgsp(new AstVarRef(refp->fileline(), outvscp, VAccess::WRITE));
+        if (outvscp) ccallp->addArgsp(new AstVarRef{refp->fileline(), outvscp, VAccess::WRITE});
 
         if (debug() >= 9) beginp->dumpTreeAndNext(cout, "-nitask: ");
         return beginp;
@@ -668,7 +668,7 @@ private:
 
     static AstNode* createDpiTemp(AstVar* portp, const string& suffix) {
         const string stmt = portp->dpiTmpVarType(portp->name() + suffix) + ";\n";
-        return new AstCStmt(portp->fileline(), stmt);
+        return new AstCStmt{portp->fileline(), stmt};
     }
 
     void unlinkAndClone(AstNodeFTask* funcp, AstNode* nodep, bool withNext) {
@@ -692,7 +692,7 @@ private:
     static AstNode* createAssignInternalToDpi(AstVar* portp, bool isPtr, const string& frSuffix,
                                               const string& toSuffix) {
         const string stmt = V3Task::assignInternalToDpi(portp, isPtr, frSuffix, toSuffix);
-        return new AstCStmt(portp->fileline(), stmt);
+        return new AstCStmt{portp->fileline(), stmt};
     }
 
     AstNode* createAssignDpiToInternal(AstVarScope* portvscp, const string& frName) {
@@ -721,7 +721,7 @@ private:
         AstNode* newp = nullptr;
         const int widthWords = portp->basicp()->widthWords();
         for (int i = 0; i < total; ++i) {
-            AstNodeExpr* srcp = new AstVarRef(portvscp->fileline(), portvscp, VAccess::WRITE);
+            AstNodeExpr* srcp = new AstVarRef{portvscp->fileline(), portvscp, VAccess::WRITE};
             // extract a scalar from multi-dimensional array (internal format)
             for (auto&& dimStride : dimStrides) {
                 const size_t dimIdx = (i / dimStride.second) % dimStride.first->elementsConst();
@@ -730,12 +730,12 @@ private:
             AstNode* stmtp = nullptr;
             // extract a scalar from DPI temporary var that is scalar or 1D array
             if (useSetWSvlv) {
-                AstNode* const linesp = new AstText(portvscp->fileline(), frstmt + ket);
+                AstNode* const linesp = new AstText{portvscp->fileline(), frstmt + ket};
                 linesp->addNext(srcp);
                 linesp->addNext(
-                    new AstText(portvscp->fileline(),
-                                "," + frName + " + " + cvtToStr(i * widthWords) + ");\n"));
-                stmtp = new AstCStmt(portvscp->fileline(), linesp);
+                    new AstText{portvscp->fileline(),
+                                "," + frName + " + " + cvtToStr(i * widthWords) + ");\n"});
+                stmtp = new AstCStmt{portvscp->fileline(), linesp};
             } else {
                 string from = frstmt;
                 if (!dimStrides.empty()) {
@@ -744,10 +744,10 @@ private:
                     from += "[" + cvtToStr(i * coef) + "]";
                 }
                 from += ket;
-                AstNodeExpr* const rhsp = new AstSel(
-                    portp->fileline(), new AstCExpr(portp->fileline(), from, cwidth, false), 0,
-                    portp->width());
-                stmtp = new AstAssign(portp->fileline(), srcp, rhsp);
+                AstNodeExpr* const rhsp = new AstSel{
+                    portp->fileline(), new AstCExpr{portp->fileline(), from, cwidth, false}, 0,
+                    portp->width()};
+                stmtp = new AstAssign{portp->fileline(), srcp, rhsp};
             }
             if (i > 0) {
                 newp->addNext(stmtp);
@@ -760,8 +760,8 @@ private:
 
     AstCFunc* makeDpiExportDispatcher(AstNodeFTask* nodep, AstVar* rtnvarp) {
         const char* const tmpSuffixp = V3Task::dpiTemporaryVarSuffix();
-        AstCFunc* const funcp = new AstCFunc(nodep->fileline(), nodep->cname(), m_scopep,
-                                             (rtnvarp ? rtnvarp->dpiArgType(true, true) : ""));
+        AstCFunc* const funcp = new AstCFunc{nodep->fileline(), nodep->cname(), m_scopep,
+                                             (rtnvarp ? rtnvarp->dpiArgType(true, true) : "")};
         funcp->dpiExportDispatcher(true);
         funcp->dpiContext(nodep->dpiContext());
         funcp->dontCombine(true);
@@ -797,7 +797,7 @@ private:
                     + ")(VerilatedScope::exportFind(__Vscopep, __Vfuncnum));\n";  // Can't use
                                                                                   // static_cast
             // If __Vcb is null the exportFind function throws and error
-            funcp->addStmtsp(new AstCStmt(nodep->fileline(), stmt));
+            funcp->addStmtsp(new AstCStmt{nodep->fileline(), stmt});
         }
 
         // Convert input/inout DPI arguments to Internal types
@@ -812,7 +812,7 @@ private:
                     // SAME CODE BELOW
                     args += ", ";
                     if (args != "") {
-                        argnodesp = argnodesp->addNext(new AstText(portp->fileline(), args, true));
+                        argnodesp = argnodesp->addNext(new AstText{portp->fileline(), args, true});
                         args = "";
                     }
                     AstVarScope* const outvscp
@@ -821,8 +821,8 @@ private:
                     outvscp->varp()->protect(false);
                     portp->protect(false);
                     AstVarRef* const refp
-                        = new AstVarRef(portp->fileline(), outvscp,
-                                        portp->isWritable() ? VAccess::WRITE : VAccess::READ);
+                        = new AstVarRef{portp->fileline(), outvscp,
+                                        portp->isWritable() ? VAccess::WRITE : VAccess::READ};
                     argnodesp = argnodesp->addNext(refp);
 
                     if (portp->isNonOutput()) {
@@ -843,14 +843,14 @@ private:
             // SAME CODE ABOVE
             args += ", ";
             if (args != "") {
-                argnodesp = argnodesp->addNext(new AstText(portp->fileline(), args, true));
+                argnodesp = argnodesp->addNext(new AstText{portp->fileline(), args, true});
                 args = "";
             }
             AstVarScope* const outvscp = createFuncVar(funcp, portp->name() + tmpSuffixp, portp);
             // No information exposure; is already visible in import/export func template
             outvscp->varp()->protect(false);
-            AstVarRef* const refp = new AstVarRef(
-                portp->fileline(), outvscp, portp->isWritable() ? VAccess::WRITE : VAccess::READ);
+            AstVarRef* const refp = new AstVarRef{
+                portp->fileline(), outvscp, portp->isWritable() ? VAccess::WRITE : VAccess::READ};
             argnodesp = argnodesp->addNext(refp);
         }
 
@@ -858,10 +858,10 @@ private:
             // Add the variables referenced as VarRef's so that lifetime analysis
             // doesn't rip up the variables on us
             args += ");\n";
-            AstCStmt* const newp = new AstCStmt(nodep->fileline(), "(*__Vcb)(");
+            AstCStmt* const newp = new AstCStmt{nodep->fileline(), "(*__Vcb)("};
             newp->addExprsp(argnodesp);
             VL_DANGLING(argnodesp);
-            newp->addExprsp(new AstText(nodep->fileline(), args, true));
+            newp->addExprsp(new AstText{nodep->fileline(), args, true});
             funcp->addStmtsp(newp);
         }
 
@@ -879,7 +879,7 @@ private:
             funcp->addStmtsp(createAssignInternalToDpi(rtnvarp, false, tmpSuffixp, ""));
             string stmt = "return " + rtnvarp->name();
             stmt += rtnvarp->basicp()->isDpiPrimitive() ? ";\n" : "[0];\n";
-            funcp->addStmtsp(new AstCStmt(nodep->fileline(), stmt));
+            funcp->addStmtsp(new AstCStmt{nodep->fileline(), stmt});
         }
         makePortList(nodep, funcp);
         return funcp;
@@ -894,7 +894,7 @@ private:
         const string rtnType = rtnvarp            ? rtnvarp->dpiArgType(true, true)
                                : nodep->dpiTask() ? "int"
                                                   : "";
-        AstCFunc* const funcp = new AstCFunc(nodep->fileline(), nodep->cname(), m_scopep, rtnType);
+        AstCFunc* const funcp = new AstCFunc{nodep->fileline(), nodep->cname(), m_scopep, rtnType};
         funcp->dpiContext(nodep->dpiContext());
         funcp->dpiImportPrototype(true);
         funcp->dontCombine(true);
@@ -997,7 +997,7 @@ private:
                         // At least put them into the module's CTOR as static?
                         const string propName = portp->name() + "__Vopenprops";
                         const string propCode = portp->vlPropDecl(propName);
-                        cfuncp->addStmtsp(new AstCStmt(portp->fileline(), propCode));
+                        cfuncp->addStmtsp(new AstCStmt{portp->fileline(), propCode});
                         //
                         // At runtime we need the svOpenArrayHandle to
                         // point to this task & thread's data, in addition
@@ -1007,7 +1007,7 @@ private:
                             = ("VerilatedDpiOpenVar "
                                // NOLINTNEXTLINE(performance-inefficient-string-concatenation)
                                + name + " (&" + propName + ", &" + portp->name() + ");\n");
-                        cfuncp->addStmtsp(new AstCStmt(portp->fileline(), varCode));
+                        cfuncp->addStmtsp(new AstCStmt{portp->fileline(), varCode});
                         args += "&" + name;
                     } else {
                         if (portp->isWritable() && portp->basicp()->isDpiPrimitive()) {
@@ -1029,7 +1029,7 @@ private:
         // Store context, if needed
         if (nodep->dpiContext()) {
             const string stmt = "Verilated::dpiContext(__Vscopep, __Vfilenamep, __Vlineno);\n";
-            cfuncp->addStmtsp(new AstCStmt(nodep->fileline(), stmt));
+            cfuncp->addStmtsp(new AstCStmt{nodep->fileline(), stmt});
         }
 
         {  // Call the imported function
@@ -1038,9 +1038,9 @@ private:
                 string stmt = rtnvscp->varp()->name();
                 stmt += tmpSuffixp;
                 stmt += rtnvscp->varp()->basicp()->isDpiPrimitive() ? " = " : "[0] = ";
-                cfuncp->addStmtsp(new AstText(nodep->fileline(), stmt, /* tracking: */ true));
+                cfuncp->addStmtsp(new AstText{nodep->fileline(), stmt, /* tracking: */ true});
             }
-            AstCCall* const callp = new AstCCall(nodep->fileline(), dpiFuncp);
+            AstCCall* const callp = new AstCCall{nodep->fileline(), dpiFuncp};
             callp->dtypeSetVoid();
             callp->argTypes(args);
             cfuncp->addStmtsp(callp->makeStmt());
@@ -1139,7 +1139,7 @@ private:
 
         AstVarScope* rtnvscp = nullptr;
         if (rtnvarp) {
-            rtnvscp = new AstVarScope(rtnvarp->fileline(), m_scopep, rtnvarp);
+            rtnvscp = new AstVarScope{rtnvarp->fileline(), m_scopep, rtnvarp};
             m_scopep->addVarsp(rtnvscp);
             rtnvarp->user2p(rtnvscp);
         }
@@ -1157,9 +1157,9 @@ private:
         string suffix;  // So, make them unique
         if (!nodep->taskPublic() && !nodep->classMethod()) suffix = "_" + m_scopep->nameDotless();
         const string name = ((nodep->name() == "new") ? "new" : prefix + nodep->name() + suffix);
-        AstCFunc* const cfuncp = new AstCFunc(
+        AstCFunc* const cfuncp = new AstCFunc{
             nodep->fileline(), name, m_scopep,
-            ((nodep->taskPublic() && rtnvarp) ? rtnvarp->cPubArgType(true, true) : ""));
+            ((nodep->taskPublic() && rtnvarp) ? rtnvarp->cPubArgType(true, true) : "")};
         // It's ok to combine imports because this is just a wrapper;
         // duplicate wrappers can get merged.
         cfuncp->dontCombine(!nodep->dpiImport());
@@ -1192,7 +1192,7 @@ private:
             cfuncp->argTypes(EmitCBaseVisitor::symClassVar());
             if (cfuncp->name() == "new") {
                 const string stmt = VIdProtect::protect("_ctor_var_reset") + "(vlSymsp);\n";
-                cfuncp->addInitsp(new AstCStmt(nodep->fileline(), stmt));
+                cfuncp->addInitsp(new AstCStmt{nodep->fileline(), stmt});
             }
         }
         if (nodep->dpiContext()) {
@@ -1267,8 +1267,8 @@ private:
 
         // Return statement
         if (rtnvscp && nodep->taskPublic()) {
-            cfuncp->addFinalsp(new AstCReturn(
-                rtnvscp->fileline(), new AstVarRef(rtnvscp->fileline(), rtnvscp, VAccess::READ)));
+            cfuncp->addFinalsp(new AstCReturn{
+                rtnvscp->fileline(), new AstVarRef{rtnvscp->fileline(), rtnvscp, VAccess::READ}});
         }
         // Replace variable refs
         relink(cfuncp);
@@ -1412,7 +1412,7 @@ private:
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else if (!VN_IS(nodep->backp(), StmtExpr)) {
             UASSERT_OBJ(nodep->taskp()->isFunction(), nodep, "func reference to non-function");
-            AstVarRef* const outrefp = new AstVarRef(nodep->fileline(), outvscp, VAccess::READ);
+            AstVarRef* const outrefp = new AstVarRef{nodep->fileline(), outvscp, VAccess::READ};
             nodep->replaceWith(outrefp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else {
@@ -1634,7 +1634,7 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp)
                 nodep->v3error("Missing argument on non-defaulted argument "
                                << portp->prettyNameQ() << " in function call to "
                                << nodep->taskp()->prettyTypeName());
-                newvaluep = new AstConst(nodep->fileline(), AstConst::Unsized32(), 0);
+                newvaluep = new AstConst{nodep->fileline(), AstConst::Unsized32{}, 0};
             } else if (!VN_IS(portp->valuep(), Const)) {
                 // The default value for this port might be a constant
                 // expression that hasn't been folded yet. Try folding it
@@ -1648,7 +1648,7 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp)
                                   "Unsupported: Non-constant default value in missing argument "
                                       << portp->prettyNameQ() << " in function call to "
                                       << nodep->taskp()->prettyTypeName());
-                    newvaluep = new AstConst(nodep->fileline(), AstConst::Unsized32(), 0);
+                    newvaluep = new AstConst{nodep->fileline(), AstConst::Unsized32{}, 0};
                 } else {
                     newvaluep = newvaluep->cloneTree(true);
                 }
@@ -1658,7 +1658,7 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp)
             // To avoid problems with callee needing to know to deleteTree
             // or not, we make this into a pin
             UINFO(9, "Default pin for " << portp << endl);
-            AstArg* const newp = new AstArg(nodep->fileline(), portp->name(), newvaluep);
+            AstArg* const newp = new AstArg{nodep->fileline(), portp->name(), newvaluep};
             if (tconnects[i].second) {  // Have a "nullptr" pin already defined for it
                 VL_DO_CLEAR(tconnects[i].second->unlinkFrBack()->deleteTree(),
                             tconnects[i].second = nullptr);
diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp
index d1f5353d9..ec9d3fa6a 100644
--- a/src/V3Trace.cpp
+++ b/src/V3Trace.cpp
@@ -413,7 +413,7 @@ private:
             // equation is heuristic.
             if (complexity <= actSet.size() * 2) {
                 for (; head != it; ++head) {
-                    new V3GraphEdge(&m_graph, m_alwaysVtxp, head->second, 1);
+                    new V3GraphEdge{&m_graph, m_alwaysVtxp, head->second, 1};
                 }
             }
         }
@@ -422,13 +422,13 @@ private:
     }
 
     AstNodeExpr* selectActivity(FileLine* flp, uint32_t acode, const VAccess& access) {
-        return new AstArraySel(flp, new AstVarRef(flp, m_activityVscp, access), acode);
+        return new AstArraySel(flp, new AstVarRef{flp, m_activityVscp, access}, acode);
     }
 
     void addActivitySetter(AstNode* insertp, uint32_t code) {
         FileLine* const fl = insertp->fileline();
-        AstAssign* const setterp = new AstAssign(fl, selectActivity(fl, code, VAccess::WRITE),
-                                                 new AstConst(fl, AstConst::BitTrue()));
+        AstAssign* const setterp = new AstAssign{fl, selectActivity(fl, code, VAccess::WRITE),
+                                                 new AstConst{fl, AstConst::BitTrue{}}};
         if (AstStmtExpr* const stmtp = VN_CAST(insertp, StmtExpr)) {
             stmtp->addNextHere(setterp);
         } else if (AstCFunc* const funcp = VN_CAST(insertp, CFunc)) {
@@ -459,12 +459,12 @@ private:
         v3Global.rootp()->typeTablep()->addTypesp(newScalarDtp);
         AstRange* const newArange
             = new AstRange{flp, VNumRange{static_cast<int>(m_activityNumber) - 1, 0}};
-        AstNodeDType* const newArrDtp = new AstUnpackArrayDType(flp, newScalarDtp, newArange);
+        AstNodeDType* const newArrDtp = new AstUnpackArrayDType{flp, newScalarDtp, newArange};
         v3Global.rootp()->typeTablep()->addTypesp(newArrDtp);
         AstVar* const newvarp
-            = new AstVar(flp, VVarType::MODULETEMP, "__Vm_traceActivity", newArrDtp);
+            = new AstVar{flp, VVarType::MODULETEMP, "__Vm_traceActivity", newArrDtp};
         m_topModp->addStmtsp(newvarp);
-        AstVarScope* const newvscp = new AstVarScope(flp, m_topScopep, newvarp);
+        AstVarScope* const newvscp = new AstVarScope{flp, m_topScopep, newvarp};
         m_topScopep->addVarsp(newvscp);
         m_activityVscp = newvscp;
 
@@ -495,7 +495,7 @@ private:
                                                   : "trace_chg_sub_";
 
         FileLine* const flp = m_topScopep->fileline();
-        AstCFunc* const funcp = new AstCFunc(flp, baseName + cvtToStr(funcNump++), m_topScopep);
+        AstCFunc* const funcp = new AstCFunc{flp, baseName + cvtToStr(funcNump++), m_topScopep};
         funcp->isTrace(true);
         funcp->dontCombine(true);
         funcp->isLoose(true);
@@ -504,7 +504,7 @@ private:
         // Add it to top scope
         m_topScopep->addBlocksp(funcp);
         const auto addInitStr = [funcp, flp](const string& str) -> void {
-            funcp->addInitsp(new AstCStmt(flp, str));
+            funcp->addInitsp(new AstCStmt{flp, str});
         };
         if (isTopFunc) {
             // Top functions
@@ -519,13 +519,13 @@ private:
             }
             // Register function
             if (full) {
-                m_regFuncp->addStmtsp(new AstText(flp, "tracep->addFullCb(", true));
+                m_regFuncp->addStmtsp(new AstText{flp, "tracep->addFullCb(", true});
             } else {
-                m_regFuncp->addStmtsp(new AstText(flp, "tracep->addChgCb(", true));
+                m_regFuncp->addStmtsp(new AstText{flp, "tracep->addChgCb(", true});
             }
-            m_regFuncp->addStmtsp(new AstAddrOfCFunc(flp, funcp));
-            m_regFuncp->addStmtsp(new AstText(flp, ", vlSelf", true));
-            m_regFuncp->addStmtsp(new AstText(flp, ");\n", true));
+            m_regFuncp->addStmtsp(new AstAddrOfCFunc{flp, funcp});
+            m_regFuncp->addStmtsp(new AstText{flp, ", vlSelf", true});
+            m_regFuncp->addStmtsp(new AstText{flp, ");\n", true});
         } else {
             // Sub functions
             funcp->argTypes(v3Global.opt.traceClassBase()
@@ -551,7 +551,7 @@ private:
                 }
             }
             // Add call to top function
-            AstCCall* const callp = new AstCCall(funcp->fileline(), funcp);
+            AstCCall* const callp = new AstCCall{funcp->fileline(), funcp};
             callp->dtypeSetVoid();
             callp->argTypes("bufp");
             topFuncp->addStmtsp(callp->makeStmt());
@@ -609,7 +609,7 @@ private:
 
                     // Add TraceInc node
                     AstTraceInc* const incp
-                        = new AstTraceInc(declp->fileline(), declp, /* full: */ true);
+                        = new AstTraceInc{declp->fileline(), declp, /* full: */ true};
                     subFuncp->addStmtsp(incp);
                     subStmts += incp->nodeCount();
 
@@ -669,14 +669,14 @@ private:
                     const bool always = actSet.count(TraceActivityVertex::ACTIVITY_ALWAYS) != 0;
                     AstNodeExpr* condp = nullptr;
                     if (always) {
-                        condp = new AstConst(flp, 1);  // Always true, will be folded later
+                        condp = new AstConst{flp, 1};  // Always true, will be folded later
                     } else {
                         for (const uint32_t actCode : actSet) {
                             AstNodeExpr* const selp = selectActivity(flp, actCode, VAccess::READ);
-                            condp = condp ? new AstOr(flp, condp, selp) : selp;
+                            condp = condp ? new AstOr{flp, condp, selp} : selp;
                         }
                     }
-                    ifp = new AstIf(flp, condp);
+                    ifp = new AstIf{flp, condp};
                     if (!always) ifp->branchPred(VBranchPred::BP_UNLIKELY);
                     subFuncp->addStmtsp(ifp);
                     subStmts += ifp->nodeCount();
@@ -685,7 +685,7 @@ private:
 
                 // Add TraceInc node
                 AstTraceInc* const incp
-                    = new AstTraceInc(declp->fileline(), declp, /* full: */ false, baseCode);
+                    = new AstTraceInc{declp->fileline(), declp, /* full: */ false, baseCode};
                 ifp->addThensp(incp);
                 subStmts += incp->nodeCount();
 
@@ -701,7 +701,7 @@ private:
 
     void createCleanupFunction() {
         FileLine* const fl = m_topScopep->fileline();
-        AstCFunc* const cleanupFuncp = new AstCFunc(fl, "trace_cleanup", m_topScopep);
+        AstCFunc* const cleanupFuncp = new AstCFunc{fl, "trace_cleanup", m_topScopep};
         cleanupFuncp->argTypes("void* voidSelf, " + v3Global.opt.traceClassBase()
                                + "* /*unused*/");
         cleanupFuncp->isTrace(true);
@@ -709,22 +709,22 @@ private:
         cleanupFuncp->isStatic(true);
         cleanupFuncp->isLoose(true);
         m_topScopep->addBlocksp(cleanupFuncp);
-        cleanupFuncp->addInitsp(new AstCStmt(fl, voidSelfAssign(m_topModp)));
-        cleanupFuncp->addInitsp(new AstCStmt(fl, symClassAssign()));
+        cleanupFuncp->addInitsp(new AstCStmt{fl, voidSelfAssign(m_topModp)});
+        cleanupFuncp->addInitsp(new AstCStmt{fl, symClassAssign()});
 
         // Register it
-        m_regFuncp->addStmtsp(new AstText(fl, "tracep->addCleanupCb(", true));
-        m_regFuncp->addStmtsp(new AstAddrOfCFunc(fl, cleanupFuncp));
-        m_regFuncp->addStmtsp(new AstText(fl, ", vlSelf);\n", true));
+        m_regFuncp->addStmtsp(new AstText{fl, "tracep->addCleanupCb(", true});
+        m_regFuncp->addStmtsp(new AstAddrOfCFunc{fl, cleanupFuncp});
+        m_regFuncp->addStmtsp(new AstText{fl, ", vlSelf);\n", true});
 
         // Clear global activity flag
-        cleanupFuncp->addStmtsp(
-            new AstCStmt(m_topScopep->fileline(), string("vlSymsp->__Vm_activity = false;\n")));
+        cleanupFuncp->addStmtsp(new AstCStmt{m_topScopep->fileline(),
+                                             std::string{"vlSymsp->__Vm_activity = false;\n"}});
 
         // Clear fine grained activity flags
         for (uint32_t i = 0; i < m_activityNumber; ++i) {
-            AstNode* const clrp = new AstAssign(fl, selectActivity(fl, i, VAccess::WRITE),
-                                                new AstConst(fl, AstConst::BitFalse()));
+            AstNode* const clrp = new AstAssign{fl, selectActivity(fl, i, VAccess::WRITE),
+                                                new AstConst{fl, AstConst::BitFalse{}}};
             cleanupFuncp->addStmtsp(clrp);
         }
     }
@@ -759,7 +759,7 @@ private:
         // last value vector is more compact
 
         // Create the trace registration function
-        m_regFuncp = new AstCFunc(m_topScopep->fileline(), "trace_register", m_topScopep);
+        m_regFuncp = new AstCFunc{m_topScopep->fileline(), "trace_register", m_topScopep};
         m_regFuncp->argTypes(v3Global.opt.traceClassBase() + "* tracep");
         m_regFuncp->isTrace(true);
         m_regFuncp->slow(true);
@@ -789,7 +789,7 @@ private:
         TraceCFuncVertex* vertexp
             = dynamic_cast<TraceCFuncVertex*>(nodep->user1u().toGraphVertex());
         if (!vertexp) {
-            vertexp = new TraceCFuncVertex(&m_graph, nodep);
+            vertexp = new TraceCFuncVertex{&m_graph, nodep};
             nodep->user1p(vertexp);
         }
         return vertexp;
@@ -798,7 +798,7 @@ private:
         TraceActivityVertex* vertexp
             = dynamic_cast<TraceActivityVertex*>(nodep->user3u().toGraphVertex());
         if (!vertexp) {
-            vertexp = new TraceActivityVertex(&m_graph, nodep, slow);
+            vertexp = new TraceActivityVertex{&m_graph, nodep, slow};
             nodep->user3p(vertexp);
         }
         vertexp->slow(slow);
@@ -840,7 +840,7 @@ private:
                             UINFO(8, "     SubCCALL " << ccallp << endl);
                             V3GraphVertex* const ccallFuncVtxp = getCFuncVertexp(ccallp->funcp());
                             activityVtxp->slow(ccallp->funcp()->slow());
-                            new V3GraphEdge(&m_graph, activityVtxp, ccallFuncVtxp, 1);
+                            new V3GraphEdge{&m_graph, activityVtxp, ccallFuncVtxp, 1};
                         }
                     }
                 }
@@ -858,7 +858,7 @@ private:
                 // Cannot treat a coroutine as slow, it may be resumed later
                 const bool slow = nodep->slow() && !nodep->isCoroutine();
                 V3GraphVertex* const activityVtxp = getActivityVertexp(nodep, slow);
-                new V3GraphEdge(&m_graph, activityVtxp, funcVtxp, 1);
+                new V3GraphEdge{&m_graph, activityVtxp, funcVtxp, 1};
             }
         }
         VL_RESTORER(m_cfuncp);
@@ -870,7 +870,7 @@ private:
     void visit(AstTraceDecl* nodep) override {
         UINFO(8, "   TRACE " << nodep << endl);
         if (!m_finding) {
-            V3GraphVertex* const vertexp = new TraceTraceVertex(&m_graph, nodep);
+            V3GraphVertex* const vertexp = new TraceTraceVertex{&m_graph, nodep};
             nodep->user1p(vertexp);
 
             UASSERT_OBJ(m_cfuncp, nodep, "Trace not under func");
@@ -885,21 +885,21 @@ private:
             UASSERT_OBJ(nodep->access().isReadOnly(), nodep, "Lvalue in trace?  Should be const.");
             V3GraphVertex* varVtxp = nodep->varScopep()->user1u().toGraphVertex();
             if (!varVtxp) {
-                varVtxp = new TraceVarVertex(&m_graph, nodep->varScopep());
+                varVtxp = new TraceVarVertex{&m_graph, nodep->varScopep()};
                 nodep->varScopep()->user1p(varVtxp);
             }
             V3GraphVertex* const traceVtxp = m_tracep->user1u().toGraphVertex();
-            new V3GraphEdge(&m_graph, varVtxp, traceVtxp, 1);
+            new V3GraphEdge{&m_graph, varVtxp, traceVtxp, 1};
             if (nodep->varp()->isPrimaryInish()  // Always need to trace primary inputs
                 || nodep->varp()->isSigPublic()) {  // Or ones user can change
-                new V3GraphEdge(&m_graph, m_alwaysVtxp, traceVtxp, 1);
+                new V3GraphEdge{&m_graph, m_alwaysVtxp, traceVtxp, 1};
             }
         } else if (m_cfuncp && m_finding && nodep->access().isWriteOrRW()) {
             UASSERT_OBJ(nodep->varScopep(), nodep, "No var scope?");
             V3GraphVertex* const funcVtxp = getCFuncVertexp(m_cfuncp);
             V3GraphVertex* const varVtxp = nodep->varScopep()->user1u().toGraphVertex();
             if (varVtxp) {  // else we're not tracing this signal
-                new V3GraphEdge(&m_graph, funcVtxp, varVtxp, 1);
+                new V3GraphEdge{&m_graph, funcVtxp, varVtxp, 1};
             }
         }
     }
diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp
index 3c1b9e255..be5db5f0a 100644
--- a/src/V3Tristate.cpp
+++ b/src/V3Tristate.cpp
@@ -205,7 +205,7 @@ private:
         TristateVertex* vertexp = reinterpret_cast<TristateVertex*>(nodep->user5p());
         if (!vertexp) {
             UINFO(6, "         New vertex " << nodep << endl);
-            vertexp = new TristateVertex(&m_graph, nodep);
+            vertexp = new TristateVertex{&m_graph, nodep};
             nodep->user5p(vertexp);
         }
         return vertexp;
@@ -297,7 +297,7 @@ public:
         if (dumpGraph() >= 9) m_graph.dumpDotFilePrefixed("tri_pos__" + nodep->name());
     }
     void associate(AstNode* fromp, AstNode* top) {
-        new V3GraphEdge(&m_graph, makeVertex(fromp), makeVertex(top), 1);
+        new V3GraphEdge{&m_graph, makeVertex(fromp), makeVertex(top), 1};
     }
     void deleteVerticesFromSubtreeRecurse(AstNode* nodep) {
         if (!nodep) return;
@@ -485,8 +485,8 @@ class TristateVisitor final : public TristateBaseVisitor {
     AstVar* getCreateEnVarp(AstVar* invarp) {
         // Return the master __en for the specified input variable
         if (!invarp->user1p()) {
-            AstVar* const newp = new AstVar(invarp->fileline(), VVarType::MODULETEMP,
-                                            invarp->name() + "__en", invarp);
+            AstVar* const newp = new AstVar{invarp->fileline(), VVarType::MODULETEMP,
+                                            invarp->name() + "__en", invarp};
             UINFO(9, "       newenv " << newp << endl);
             modAddStmtp(invarp, newp);
             invarp->user1p(newp);  // find envar given invarp
@@ -537,8 +537,8 @@ class TristateVisitor final : public TristateBaseVisitor {
     AstVar* getCreateOutVarp(AstVar* invarp) {
         // Return the master __out for the specified input variable
         if (!invarp->user4p()) {
-            AstVar* const newp = new AstVar(invarp->fileline(), VVarType::MODULETEMP,
-                                            invarp->name() + "__out", invarp);
+            AstVar* const newp = new AstVar{invarp->fileline(), VVarType::MODULETEMP,
+                                            invarp->name() + "__out", invarp};
             UINFO(9, "       newout " << newp << endl);
             modAddStmtp(invarp, newp);
             invarp->user4p(newp);  // find outvar given invarp
@@ -546,8 +546,8 @@ class TristateVisitor final : public TristateBaseVisitor {
         return VN_AS(invarp->user4p(), Var);
     }
     AstVar* getCreateUnconnVarp(AstNode* fromp, AstNodeDType* dtypep) {
-        AstVar* const newp = new AstVar(fromp->fileline(), VVarType::MODULETEMP,
-                                        "__Vtriunconn" + cvtToStr(m_unique++), dtypep);
+        AstVar* const newp = new AstVar{fromp->fileline(), VVarType::MODULETEMP,
+                                        "__Vtriunconn" + cvtToStr(m_unique++), dtypep};
         UINFO(9, "       newunc " << newp << endl);
         modAddStmtp(newp, newp);
         return newp;
@@ -569,9 +569,9 @@ class TristateVisitor final : public TristateBaseVisitor {
     AstNodeExpr* newEnableDeposit(AstSel* selp, AstNodeExpr* enp) {
         // Form a "deposit" instruction for given enable, using existing select as a template.
         // Would be nicer if we made this a new AST type
-        AstNodeExpr* const newp = new AstShiftL(
-            selp->fileline(), new AstExtend(selp->fileline(), enp, selp->fromp()->width()),
-            selp->lsbp()->cloneTree(false), selp->fromp()->width());
+        AstNodeExpr* const newp = new AstShiftL{
+            selp->fileline(), new AstExtend{selp->fileline(), enp, selp->fromp()->width()},
+            selp->lsbp()->cloneTree(false), selp->fromp()->width()};
         return newp;
     }
 
@@ -622,8 +622,8 @@ class TristateVisitor final : public TristateBaseVisitor {
                     UINFO(8, "  Adding driver to var " << varp << endl);
                     AstConst* const constp = newAllZerosOrOnes(varp, false);
                     AstVarRef* const varrefp
-                        = new AstVarRef(varp->fileline(), varp, VAccess::WRITE);
-                    AstNode* const newp = new AstAssignW(varp->fileline(), varrefp, constp);
+                        = new AstVarRef{varp->fileline(), varp, VAccess::WRITE};
+                    AstNode* const newp = new AstAssignW{varp->fileline(), varrefp, constp};
                     UINFO(9, "       newoev " << newp << endl);
                     varrefp->user1p(newAllZerosOrOnes(varp, false));
                     nodep->addStmtsp(newp);
@@ -993,7 +993,7 @@ class TristateVisitor final : public TristateBaseVisitor {
                 // due to the pinReconnectSimple call in visit AstPin.
                 // We can ignore the output override by making a temporary
                 AstVar* const varp = getCreateUnconnVarp(nodep, nodep->dtypep());
-                AstNode* const newp = new AstVarRef(nodep->fileline(), varp, VAccess::WRITE);
+                AstNode* const newp = new AstVarRef{nodep->fileline(), varp, VAccess::WRITE};
                 UINFO(9, " const->" << newp << endl);
                 nodep->replaceWith(newp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
@@ -1047,7 +1047,7 @@ class TristateVisitor final : public TristateBaseVisitor {
                 // The output enable of a cond is a cond of the output enable of the
                 // two expressions with the same conditional.
                 AstNodeExpr* const enp
-                    = new AstCond(nodep->fileline(), condp->cloneTree(false), en1p, en2p);
+                    = new AstCond{nodep->fileline(), condp->cloneTree(false), en1p, en2p};
                 UINFO(9, "       newcond " << enp << endl);
                 nodep->user1p(enp);  // propagate up COND(lhsp->enable, rhsp->enable)
                 thenp->user1p(nullptr);
@@ -1086,8 +1086,8 @@ class TristateVisitor final : public TristateBaseVisitor {
                 if (nodep->fromp()->user1p()) {  // SEL(VARREF, lsb)
                     AstNodeExpr* const en1p = getEnp(nodep->fromp());
                     AstNodeExpr* const enp
-                        = new AstSel(nodep->fileline(), en1p, nodep->lsbp()->cloneTree(true),
-                                     nodep->widthp()->cloneTree(true));
+                        = new AstSel{nodep->fileline(), en1p, nodep->lsbp()->cloneTree(true),
+                                     nodep->widthp()->cloneTree(true)};
                     UINFO(9, "       newsel " << enp << endl);
                     nodep->user1p(enp);  // propagate up SEL(fromp->enable, value)
                     m_tgraph.didProcess(nodep);
@@ -1113,11 +1113,11 @@ class TristateVisitor final : public TristateBaseVisitor {
                     // Each half of the concat gets a select of the enable expression
                     AstNodeExpr* const enp = VN_AS(nodep->user1p(), NodeExpr);
                     nodep->user1p(nullptr);
-                    nodep->lhsp()->user1p(new AstSel(nodep->fileline(), enp->cloneTree(true),
+                    nodep->lhsp()->user1p(new AstSel{nodep->fileline(), enp->cloneTree(true),
                                                      nodep->rhsp()->width(),
-                                                     nodep->lhsp()->width()));
+                                                     nodep->lhsp()->width()});
                     nodep->rhsp()->user1p(
-                        new AstSel(nodep->fileline(), enp, 0, nodep->rhsp()->width()));
+                        new AstSel{nodep->fileline(), enp, 0, nodep->rhsp()->width()});
                     m_tgraph.didProcess(nodep);
                 }
                 iterateChildren(nodep);
@@ -1132,7 +1132,7 @@ class TristateVisitor final : public TristateBaseVisitor {
                     m_tgraph.didProcess(nodep);
                     AstNodeExpr* const en1p = getEnp(expr1p);
                     AstNodeExpr* const en2p = getEnp(expr2p);
-                    AstNodeExpr* const enp = new AstConcat(nodep->fileline(), en1p, en2p);
+                    AstNodeExpr* const enp = new AstConcat{nodep->fileline(), en1p, en2p};
                     UINFO(9, "       newconc " << enp << endl);
                     nodep->user1p(enp);  // propagate up CONCAT(lhsp->enable, rhsp->enable)
                     expr1p->user1p(nullptr);
@@ -1161,7 +1161,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             AstNodeExpr* const expr2p = nodep->rhsp()->unlinkFrBack();
             AstNodeExpr* enp;
             if (AstNodeExpr* const en2p = VN_AS(expr2p->user1p(), NodeExpr)) {
-                enp = new AstAnd(nodep->fileline(), expr1p, en2p);
+                enp = new AstAnd{nodep->fileline(), expr1p, en2p};
             } else {
                 enp = expr1p;
             }
@@ -1211,15 +1211,15 @@ class TristateVisitor final : public TristateBaseVisitor {
             AstNodeExpr* subexpr1p = expr1p->cloneTree(false);
             AstNodeExpr* subexpr2p = expr2p->cloneTree(false);
             if (isAnd) {
-                subexpr1p = new AstNot(nodep->fileline(), subexpr1p);
-                subexpr2p = new AstNot(nodep->fileline(), subexpr2p);
+                subexpr1p = new AstNot{nodep->fileline(), subexpr1p};
+                subexpr2p = new AstNot{nodep->fileline(), subexpr2p};
             }
             // calc new output enable
-            AstNodeExpr* const enp = new AstOr(
-                nodep->fileline(), new AstAnd(nodep->fileline(), en1p, en2p),
-                new AstOr(nodep->fileline(),
-                          new AstAnd(nodep->fileline(), en1p->cloneTree(false), subexpr1p),
-                          new AstAnd(nodep->fileline(), en2p->cloneTree(false), subexpr2p)));
+            AstNodeExpr* const enp = new AstOr{
+                nodep->fileline(), new AstAnd{nodep->fileline(), en1p, en2p},
+                new AstOr{nodep->fileline(),
+                          new AstAnd{nodep->fileline(), en1p->cloneTree(false), subexpr1p},
+                          new AstAnd{nodep->fileline(), en2p->cloneTree(false), subexpr2p}}};
             UINFO(9, "       neweqn " << enp << endl);
             nodep->user1p(enp);
             expr1p->user1p(nullptr);
@@ -1402,8 +1402,8 @@ class TristateVisitor final : public TristateBaseVisitor {
                 UINFO(4, " COUNTBITS('z)-> " << nodep << endl);
                 VNRelinker relinkHandle;
                 nodep->unlinkFrBack(&relinkHandle);
-                AstNodeExpr* newp = new AstCountOnes(
-                    nodep->fileline(), new AstVarRef(nodep->fileline(), envarp, VAccess::READ));
+                AstNodeExpr* newp = new AstCountOnes{
+                    nodep->fileline(), new AstVarRef{nodep->fileline(), envarp, VAccess::READ}};
                 if (nonXp) {  // Need to still count '0 or '1 or 'x's
                     if (dropop[0]) {
                         nodep->rhsp()->unlinkFrBack()->deleteTree();
@@ -1417,7 +1417,7 @@ class TristateVisitor final : public TristateBaseVisitor {
                         nodep->fhsp()->unlinkFrBack()->deleteTree();
                         nodep->fhsp(nonXp->cloneTree(true));
                     }
-                    newp = new AstAdd(nodep->fileline(), nodep, newp);
+                    newp = new AstAdd{nodep->fileline(), nodep, newp};
                 }
                 if (debug() >= 9) newp->dumpTree(cout, "-countout: ");
                 relinkHandle.relink(newp);
@@ -1527,11 +1527,11 @@ class TristateVisitor final : public TristateBaseVisitor {
             if (!nodep->exprp()) {  // No-connect; covert to empty connection
                 UINFO(5, "Unconnected pin terminate " << nodep << endl);
                 AstVar* const ucVarp = getCreateUnconnVarp(nodep, nodep->modVarp()->dtypep());
-                nodep->exprp(new AstVarRef(nodep->fileline(), ucVarp,
+                nodep->exprp(new AstVarRef{nodep->fileline(), ucVarp,
                                            // We converted, so use declaration output state
                                            nodep->modVarp()->declDirection().isWritable()
                                                ? VAccess::WRITE
-                                               : VAccess::READ));
+                                               : VAccess::READ});
                 m_tgraph.setTristate(ucVarp);
                 // We don't need a driver on the wire; the lack of one will default to tristate
             } else if (inDeclProcessing) {  // Not an input that was a converted tristate
@@ -1549,9 +1549,9 @@ class TristateVisitor final : public TristateBaseVisitor {
             // Create the output enable pin, connect to new signal
             AstNodeExpr* enrefp;
             {
-                AstVar* const enVarp = new AstVar(nodep->fileline(), VVarType::MODULETEMP,
+                AstVar* const enVarp = new AstVar{nodep->fileline(), VVarType::MODULETEMP,
                                                   nodep->name() + "__en" + cvtToStr(m_unique++),
-                                                  VFlagBitPacked(), enModVarp->width());
+                                                  VFlagBitPacked{}, enModVarp->width()};
                 if (inDeclProcessing) {  // __en(from-resolver-const) or __en(from-resolver-wire)
                     enModVarp->varType2In();
                 } else {
@@ -1559,15 +1559,15 @@ class TristateVisitor final : public TristateBaseVisitor {
                 }
                 UINFO(9, "       newenv " << enVarp << endl);
                 AstPin* const enpinp
-                    = new AstPin(nodep->fileline(), nodep->pinNum(),
+                    = new AstPin{nodep->fileline(), nodep->pinNum(),
                                  enModVarp->name(),  // should be {var}"__en"
-                                 new AstVarRef(nodep->fileline(), enVarp, VAccess::WRITE));
+                                 new AstVarRef{nodep->fileline(), enVarp, VAccess::WRITE}};
                 enpinp->modVarp(enModVarp);
                 UINFO(9, "       newpin " << enpinp << endl);
                 enpinp->user2(U2_BOTH);  // don't iterate the pin later
                 nodep->addNextHere(enpinp);
                 m_modp->addStmtsp(enVarp);
-                enrefp = new AstVarRef(nodep->fileline(), enVarp, VAccess::READ);
+                enrefp = new AstVarRef{nodep->fileline(), enVarp, VAccess::READ};
                 UINFO(9, "       newvrf " << enrefp << endl);
                 if (debug() >= 9) enpinp->dumpTree(cout, "-pin-ena: ");
             }
@@ -1584,9 +1584,9 @@ class TristateVisitor final : public TristateBaseVisitor {
             } else {
                 AstNodeExpr* const outexprp
                     = VN_AS(nodep->exprp(), NodeExpr)->cloneTree(false);  // Note has lvalue() set
-                outpinp = new AstPin(nodep->fileline(), nodep->pinNum(),
+                outpinp = new AstPin{nodep->fileline(), nodep->pinNum(),
                                      outModVarp->name(),  // should be {var}"__out"
-                                     outexprp);
+                                     outexprp};
                 outpinp->modVarp(outModVarp);
                 UINFO(9, "       newpin " << outpinp << endl);
                 outpinp->user2(U2_BOTH);  // don't iterate the pin later
@@ -1695,7 +1695,7 @@ class TristateVisitor final : public TristateBaseVisitor {
                 // Then propagate the enable from the original variable
                 UINFO(9, "     Ref-to-tri " << nodep << endl);
                 AstVar* const enVarp = getCreateEnVarp(nodep->varp());
-                nodep->user1p(new AstVarRef(nodep->fileline(), enVarp, VAccess::READ));
+                nodep->user1p(new AstVarRef{nodep->fileline(), enVarp, VAccess::READ});
             }
             if (m_alhs) {}  // NOP; user1() already passed down from assignment
         }
@@ -1709,9 +1709,9 @@ class TristateVisitor final : public TristateBaseVisitor {
             if (nodep->user2() & U2_GRAPHING) return;  // Already processed
             nodep->user2(U2_GRAPHING);
             if (nodep->isPulldown() || nodep->isPullup()) {
-                AstNode* const newp = new AstPull(
-                    nodep->fileline(), new AstVarRef(nodep->fileline(), nodep, VAccess::WRITE),
-                    nodep->isPullup());
+                AstNode* const newp = new AstPull{
+                    nodep->fileline(), new AstVarRef{nodep->fileline(), nodep, VAccess::WRITE},
+                    nodep->isPullup()};
                 UINFO(9, "       newpul " << newp << endl);
                 nodep->addNextHere(newp);
                 // We'll iterate on the new AstPull later
diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp
index 8d768dedb..55d7e63ab 100644
--- a/src/V3Unknown.cpp
+++ b/src/V3Unknown.cpp
@@ -95,9 +95,9 @@ private:
         if (m_assigndlyp) {
             // Delayed assignments become normal assignments,
             // then the temp created becomes the delayed assignment
-            AstNode* const newp = new AstAssign(m_assigndlyp->fileline(),
+            AstNode* const newp = new AstAssign{m_assigndlyp->fileline(),
                                                 m_assigndlyp->lhsp()->unlinkFrBackWithNext(),
-                                                m_assigndlyp->rhsp()->unlinkFrBackWithNext());
+                                                m_assigndlyp->rhsp()->unlinkFrBackWithNext()};
             m_assigndlyp->replaceWith(newp);
             VL_DO_CLEAR(pushDeletep(m_assigndlyp), m_assigndlyp = nullptr);
         }
@@ -116,23 +116,23 @@ private:
             UASSERT_OBJ(!needDly, prep, "Should have already converted to non-delay");
             VNRelinker replaceHandle;
             AstNodeExpr* const earliercondp = ifp->condp()->unlinkFrBack(&replaceHandle);
-            AstNodeExpr* const newp = new AstLogAnd(condp->fileline(), condp, earliercondp);
+            AstNodeExpr* const newp = new AstLogAnd{condp->fileline(), condp, earliercondp};
             UINFO(4, "Edit BOUNDLVALUE " << newp << endl);
             replaceHandle.relink(newp);
         } else {
             AstVar* const varp
-                = new AstVar(fl, VVarType::MODULETEMP, m_lvboundNames.get(prep), prep->dtypep());
+                = new AstVar{fl, VVarType::MODULETEMP, m_lvboundNames.get(prep), prep->dtypep()};
             m_modp->addStmtsp(varp);
             AstNode* const abovep = prep->backp();  // Grab above point before we replace 'prep'
-            prep->replaceWith(new AstVarRef(fl, varp, VAccess::WRITE));
+            prep->replaceWith(new AstVarRef{fl, varp, VAccess::WRITE});
             if (m_timingControlp) m_timingControlp->unlinkFrBack();
-            AstIf* const newp = new AstIf(
+            AstIf* const newp = new AstIf{
                 fl, condp,
                 (needDly
                      ? static_cast<AstNode*>(new AstAssignDly{
                          fl, prep, new AstVarRef{fl, varp, VAccess::READ}, m_timingControlp})
                      : static_cast<AstNode*>(new AstAssign{
-                         fl, prep, new AstVarRef{fl, varp, VAccess::READ}, m_timingControlp})));
+                         fl, prep, new AstVarRef{fl, varp, VAccess::READ}, m_timingControlp}))};
             newp->branchPred(VBranchPred::BP_LIKELY);
             newp->isBoundsCheck(true);
             if (debug() >= 9) newp->dumpTree(cout, "     _new: ");
@@ -213,15 +213,15 @@ private:
             // If we got ==1'bx it can never be true (but 1'bx==1'bx can be!)
             if (((VN_IS(lhsp, Const) && VN_AS(lhsp, Const)->num().isFourState())
                  || (VN_IS(rhsp, Const) && VN_AS(rhsp, Const)->num().isFourState()))) {
-                newp = new AstConst(nodep->fileline(), AstConst::WidthedValue(), 1,
+                newp = new AstConst(nodep->fileline(), AstConst::WidthedValue{}, 1,
                                     (VN_IS(nodep, EqCase) ? 0 : 1));
                 VL_DO_DANGLING(lhsp->deleteTree(), lhsp);
                 VL_DO_DANGLING(rhsp->deleteTree(), rhsp);
             } else {
                 if (VN_IS(nodep, EqCase)) {
-                    newp = new AstEq(nodep->fileline(), lhsp, rhsp);
+                    newp = new AstEq{nodep->fileline(), lhsp, rhsp};
                 } else {
-                    newp = new AstNeq(nodep->fileline(), lhsp, rhsp);
+                    newp = new AstNeq{nodep->fileline(), lhsp, rhsp};
                 }
             }
             nodep->replaceWith(newp);
@@ -246,20 +246,20 @@ private:
                 nodep->v3warn(E_UNSUPPORTED, "Unsupported: RHS of ==? or !=? must be "
                                              "constant to be synthesizable");  // Says spec.
                 // Replace with anything that won't cause more errors
-                newp = new AstEq(nodep->fileline(), lhsp, rhsp);
+                newp = new AstEq{nodep->fileline(), lhsp, rhsp};
             } else {
                 // X or Z's become mask, ala case statements.
-                V3Number nummask(rhsp, rhsp->width());
+                V3Number nummask{rhsp, rhsp->width()};
                 nummask.opBitsNonX(VN_AS(rhsp, Const)->num());
-                V3Number numval(rhsp, rhsp->width());
+                V3Number numval{rhsp, rhsp->width()};
                 numval.opBitsOne(VN_AS(rhsp, Const)->num());
-                AstNodeExpr* const and1p = new AstAnd(nodep->fileline(), lhsp,
-                                                      new AstConst(nodep->fileline(), nummask));
-                AstNodeExpr* const and2p = new AstConst(nodep->fileline(), numval);
+                AstNodeExpr* const and1p = new AstAnd{nodep->fileline(), lhsp,
+                                                      new AstConst{nodep->fileline(), nummask}};
+                AstNodeExpr* const and2p = new AstConst{nodep->fileline(), numval};
                 if (VN_IS(nodep, EqWild)) {
-                    newp = new AstEq(nodep->fileline(), and1p, and2p);
+                    newp = new AstEq{nodep->fileline(), and1p, and2p};
                 } else {
-                    newp = new AstNeq(nodep->fileline(), and1p, and2p);
+                    newp = new AstNeq{nodep->fileline(), and1p, and2p};
                 }
                 VL_DO_DANGLING(rhsp->deleteTree(), rhsp);
             }
@@ -278,7 +278,7 @@ private:
         iterateChildren(nodep);
         // Ahh, we're two state, so this is easy
         UINFO(4, " ISUNKNOWN->0 " << nodep << endl);
-        AstConst* const newp = new AstConst(nodep->fileline(), AstConst::BitFalse());
+        AstConst* const newp = new AstConst{nodep->fileline(), AstConst::BitFalse{}};
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
@@ -299,7 +299,7 @@ private:
             nonXp = nodep->fhsp();
         } else {  // Was all X-s
             UINFO(4, " COUNTBITS('x)->0 " << nodep << endl);
-            AstConst* const newp = new AstConst(nodep->fileline(), AstConst::BitFalse());
+            AstConst* const newp = new AstConst{nodep->fileline(), AstConst::BitFalse{}};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
             return;
@@ -325,19 +325,19 @@ private:
             // CONST(num) -> VARREF(newvarp)
             //          -> VAR(newvarp)
             //          -> INITIAL(VARREF(newvarp, OR(num_No_Xs,AND(random,num_1s_Where_X))
-            V3Number numb1(nodep, nodep->width());
+            V3Number numb1{nodep, nodep->width()};
             numb1.opBitsOne(nodep->num());
-            V3Number numbx(nodep, nodep->width());
+            V3Number numbx{nodep, nodep->width()};
             numbx.opBitsXZ(nodep->num());
             if (!m_allowXUnique || v3Global.opt.xAssign() != "unique") {
                 // All X bits just become 0; fastest simulation, but not nice
-                V3Number numnew(nodep, numb1.width());
+                V3Number numnew{nodep, numb1.width()};
                 if (v3Global.opt.xAssign() == "1") {
                     numnew.opOr(numb1, numbx);
                 } else {
                     numnew.opAssign(numb1);
                 }
-                AstConst* const newp = new AstConst(nodep->fileline(), numnew);
+                AstConst* const newp = new AstConst{nodep->fileline(), numnew};
                 nodep->replaceWith(newp);
                 VL_DO_DANGLING(nodep->deleteTree(), nodep);
                 UINFO(4, "   -> " << newp << endl);
@@ -353,18 +353,18 @@ private:
                 VNRelinker replaceHandle;
                 nodep->unlinkFrBack(&replaceHandle);
                 AstNodeVarRef* const newref1p
-                    = new AstVarRef(nodep->fileline(), newvarp, VAccess::READ);
+                    = new AstVarRef{nodep->fileline(), newvarp, VAccess::READ};
                 replaceHandle.relink(newref1p);  // Replace const with varref
-                AstInitial* const newinitp = new AstInitial(
+                AstInitial* const newinitp = new AstInitial{
                     nodep->fileline(),
-                    new AstAssign(
+                    new AstAssign{
                         nodep->fileline(),
-                        new AstVarRef(nodep->fileline(), newvarp, VAccess::WRITE),
-                        new AstOr(nodep->fileline(), new AstConst(nodep->fileline(), numb1),
-                                  new AstAnd(nodep->fileline(),
-                                             new AstConst(nodep->fileline(), numbx),
-                                             new AstRand(nodep->fileline(), AstRand::Reset{},
-                                                         nodep->dtypep(), true)))));
+                        new AstVarRef{nodep->fileline(), newvarp, VAccess::WRITE},
+                        new AstOr{nodep->fileline(), new AstConst{nodep->fileline(), numb1},
+                                  new AstAnd{nodep->fileline(),
+                                             new AstConst{nodep->fileline(), numbx},
+                                             new AstRand{nodep->fileline(), AstRand::Reset{},
+                                                         nodep->dtypep(), true}}}}};
                 // Add inits in front of other statement.
                 // In the future, we should stuff the initp into the module's constructor.
                 AstNode* const afterp = m_modp->stmtsp()->unlinkFrBackWithNext();
@@ -395,10 +395,10 @@ private:
 
             // If (maxmsb >= selected), we're in bound
             AstNodeExpr* condp
-                = new AstGte(nodep->fileline(),
+                = new AstGte{nodep->fileline(),
                              new AstConst(nodep->fileline(), AstConst::WidthedValue(),
                                           nodep->lsbp()->width(), maxmsb),
-                             nodep->lsbp()->cloneTree(false));
+                             nodep->lsbp()->cloneTree(false)};
             // See if the condition is constant true (e.g. always in bound due to constant select)
             // Note below has null backp(); the Edit function knows how to deal with that.
             condp = V3Const::constifyEdit(condp);
@@ -409,10 +409,10 @@ private:
                 // SEL(...) -> COND(LTE(bit<=maxmsb), ARRAYSEL(...), {width{1'bx}})
                 VNRelinker replaceHandle;
                 nodep->unlinkFrBack(&replaceHandle);
-                V3Number xnum(nodep, nodep->width());
+                V3Number xnum{nodep, nodep->width()};
                 xnum.setAllBitsX();
-                AstNode* const newp = new AstCondBound(nodep->fileline(), condp, nodep,
-                                                       new AstConst(nodep->fileline(), xnum));
+                AstNode* const newp = new AstCondBound{nodep->fileline(), condp, nodep,
+                                                       new AstConst{nodep->fileline(), xnum}};
                 if (debug() >= 9) newp->dumpTree(cout, "        _new: ");
                 // Link in conditional
                 replaceHandle.relink(newp);
@@ -454,10 +454,10 @@ private:
 
             // See if the condition is constant true
             AstNodeExpr* condp
-                = new AstGte(nodep->fileline(),
-                             new AstConst(nodep->fileline(), AstConst::WidthedValue(),
+                = new AstGte{nodep->fileline(),
+                             new AstConst(nodep->fileline(), AstConst::WidthedValue{},
                                           nodep->bitp()->width(), declElements - 1),
-                             nodep->bitp()->cloneTree(false));
+                             nodep->bitp()->cloneTree(false)};
             // Note below has null backp(); the Edit function knows how to deal with that.
             condp = V3Const::constifyEdit(condp);
             if (condp->isOne()) {
@@ -469,14 +469,14 @@ private:
                 // ARRAYSEL(...) -> COND(LT(bit<maxbit), ARRAYSEL(...), {width{1'bx}})
                 VNRelinker replaceHandle;
                 nodep->unlinkFrBack(&replaceHandle);
-                V3Number xnum(nodep, nodep->width());
+                V3Number xnum{nodep, nodep->width()};
                 if (nodep->isString()) {
                     xnum = V3Number{V3Number::String{}, nodep, ""};
                 } else {
                     xnum.setAllBitsX();
                 }
-                AstNode* const newp = new AstCondBound(nodep->fileline(), condp, nodep,
-                                                       new AstConst(nodep->fileline(), xnum));
+                AstNode* const newp = new AstCondBound{nodep->fileline(), condp, nodep,
+                                                       new AstConst{nodep->fileline(), xnum}};
                 if (debug() >= 9) newp->dumpTree(cout, "        _new: ");
                 // Link in conditional, can blow away temp xor
                 replaceHandle.relink(newp);
@@ -486,9 +486,9 @@ private:
                 // ARRAYSEL(...) -> ARRAYSEL(COND(LT(bit<maxbit), bit, 0))
                 VNRelinker replaceHandle;
                 AstNodeExpr* const bitp = nodep->bitp()->unlinkFrBack(&replaceHandle);
-                AstNodeExpr* const newp = new AstCondBound(
+                AstNodeExpr* const newp = new AstCondBound{
                     bitp->fileline(), condp, bitp,
-                    new AstConst(bitp->fileline(), AstConst::WidthedValue(), bitp->width(), 0));
+                    new AstConst{bitp->fileline(), AstConst::WidthedValue{}, bitp->width(), 0}};
                 // Added X's, tristate them too
                 if (debug() >= 9) newp->dumpTree(cout, "        _new: ");
                 replaceHandle.relink(newp);

From 2eed4452adeaf6619782b54934337289450df16c Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 20 Nov 2022 20:13:55 -0500
Subject: [PATCH 077/156] Internals: Fix constructor style.

---
 src/V3Const.cpp    | 176 +++++------
 src/V3Width.cpp    | 716 ++++++++++++++++++++++-----------------------
 src/V3WidthSel.cpp |  90 +++---
 src/verilog.y      |  65 ++--
 4 files changed, 523 insertions(+), 524 deletions(-)

diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 173666099..000b31dab 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -1050,9 +1050,9 @@ private:
                                                                                      << endl);
         AstNodeCond* const newp = static_cast<AstNodeCond*>(condp->cloneType(
             condp->condp()->unlinkFrBack(),
-            new AstAnd(nodep->fileline(), maskp->cloneTree(false), condp->thenp()->unlinkFrBack()),
-            new AstAnd(nodep->fileline(), maskp->cloneTree(false),
-                       condp->elsep()->unlinkFrBack())));
+            new AstAnd{nodep->fileline(), maskp->cloneTree(false), condp->thenp()->unlinkFrBack()},
+            new AstAnd{nodep->fileline(), maskp->cloneTree(false),
+                       condp->elsep()->unlinkFrBack()}));
         newp->dtypeFrom(nodep);
         newp->thenp()->dtypeFrom(nodep);  // As And might have been to change widths
         newp->elsep()->dtypeFrom(nodep);
@@ -1087,7 +1087,7 @@ private:
 
         if (orLIsRedundant && orRIsRedundant) {
             nodep->replaceWith(
-                new AstConst(nodep->fileline(), AstConst::DTyped{}, nodep->dtypep()));
+                new AstConst{nodep->fileline(), AstConst::DTyped{}, nodep->dtypep()});
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
             return true;
         } else if (orLIsRedundant) {
@@ -1124,15 +1124,15 @@ private:
         if (const AstShiftR* const shiftp = VN_CAST(nodep->rhsp(), ShiftR)) {
             if (const AstConst* const scp = VN_CAST(shiftp->rhsp(), Const)) {
                 // Check if mask is full over the non-zero bits
-                V3Number maskLo(nodep, nodep->width());
+                V3Number maskLo{nodep, nodep->width()};
                 maskLo.setMask(nodep->width() - scp->num().toUInt());
                 return checkMask(maskLo);
             }
         } else if (const AstShiftL* const shiftp = VN_CAST(nodep->rhsp(), ShiftL)) {
             if (const AstConst* const scp = VN_CAST(shiftp->rhsp(), Const)) {
                 // Check if mask is full over the non-zero bits
-                V3Number maskLo(nodep, nodep->width());
-                V3Number maskHi(nodep, nodep->width());
+                V3Number maskLo{nodep, nodep->width()};
+                V3Number maskHi{nodep, nodep->width()};
                 maskLo.setMask(nodep->width() - scp->num().toUInt());
                 maskHi.opShiftL(maskLo, scp->num());
                 return checkMask(maskHi);
@@ -1280,8 +1280,8 @@ private:
         if (debug() >= 9) nodep->dumpTree(cout, "SEL(BI)-in:");
         AstNodeExpr* const bilhsp = bip->lhsp()->unlinkFrBack();
         AstNodeExpr* const birhsp = bip->rhsp()->unlinkFrBack();
-        bip->lhsp(new AstSel(nodep->fileline(), bilhsp, 0, nodep->widthConst()));
-        bip->rhsp(new AstSel(nodep->fileline(), birhsp, 0, nodep->widthConst()));
+        bip->lhsp(new AstSel{nodep->fileline(), bilhsp, 0, nodep->widthConst()});
+        bip->rhsp(new AstSel{nodep->fileline(), birhsp, 0, nodep->widthConst()});
         if (debug() >= 9) bip->dumpTree(cout, "SEL(BI)-ou:");
         VL_DO_DANGLING(replaceWChild(nodep, bip), nodep);
         return true;
@@ -1308,7 +1308,7 @@ private:
         UINFO(9, "SEL(SHIFTR(a,b),l,w) -> SEL(a,l+b,w)\n");
         if (debug() >= 9) nodep->dumpTree(cout, "SEL(SH)-in:");
         AstSel* const newp
-            = new AstSel(nodep->fileline(), ap->unlinkFrBack(), newLsb, nodep->widthConst());
+            = new AstSel{nodep->fileline(), ap->unlinkFrBack(), newLsb, nodep->widthConst()};
         newp->dtypeFrom(nodep);
         if (debug() >= 9) newp->dumpTree(cout, "SEL(SH)-ou:");
         VL_DO_DANGLING(nodep->replaceWith(newp), nodep);
@@ -1334,9 +1334,9 @@ private:
         nodep->rhsp(smallerp);
 
         constp->unlinkFrBack();
-        V3Number num(constp, subsize);
+        V3Number num{constp, subsize};
         num.opAssign(constp->num());
-        nodep->lhsp(new AstConst(constp->fileline(), num));
+        nodep->lhsp(new AstConst{constp->fileline(), num});
         VL_DO_DANGLING(constp->deleteTree(), constp);
         if (debug() >= 9) nodep->dumpTree(cout, "BI(EXTEND)-ou:");
         return true;
@@ -1487,13 +1487,13 @@ private:
         const AstSel* rselp = VN_CAST(rhsp, Sel);
         // a[i:0] a
         if (lselp && !rselp && rhsp->sameGateTree(lselp->fromp()))
-            rselp = new AstSel(rhsp->fileline(), rhsp->cloneTree(false), 0, rhsp->width());
+            rselp = new AstSel{rhsp->fileline(), rhsp->cloneTree(false), 0, rhsp->width()};
         // a[i:j] {a[j-1:k], b}
         if (lselp && !rselp && VN_IS(rhsp, Concat))
             return ifMergeAdjacent(lhsp, VN_CAST(rhsp, Concat)->lhsp());
         // a a[msb:j]
         if (rselp && !lselp && lhsp->sameGateTree(rselp->fromp()))
-            lselp = new AstSel(lhsp->fileline(), lhsp->cloneTree(false), 0, lhsp->width());
+            lselp = new AstSel{lhsp->fileline(), lhsp->cloneTree(false), 0, lhsp->width()};
         // {b, a[j:k]} a[k-1:i]
         if (rselp && !lselp && VN_IS(lhsp, Concat))
             return ifMergeAdjacent(VN_CAST(lhsp, Concat)->rhsp(), rhsp);
@@ -1551,7 +1551,7 @@ private:
         UASSERT(oldp, "Null old");
         UASSERT_OBJ(!(VN_IS(oldp, Const) && !VN_AS(oldp, Const)->num().isFourState()), oldp,
                     "Already constant??");
-        AstNode* const newp = new AstConst(oldp->fileline(), num);
+        AstNode* const newp = new AstConst{oldp->fileline(), num};
         newp->dtypeFrom(oldp);
         if (debug() > 5) oldp->dumpTree(cout, "  const_old: ");
         if (debug() > 5) newp->dumpTree(cout, "       _new: ");
@@ -1559,7 +1559,7 @@ private:
         VL_DO_DANGLING(oldp->deleteTree(), oldp);
     }
     void replaceNum(AstNode* nodep, uint32_t val) {
-        V3Number num(nodep, nodep->width(), val);
+        V3Number num{nodep, nodep->width(), val};
         VL_DO_DANGLING(replaceNum(nodep, num), nodep);
     }
     void replaceNumSigned(AstNodeBiop* nodep, uint32_t val) {
@@ -1583,33 +1583,33 @@ private:
         if (isTPure(checkp)) {
             VL_DO_DANGLING(replaceNum(nodep, 0), nodep);
         } else {
-            AstNode* const newp = new AstAnd(nodep->fileline(), new AstConst(nodep->fileline(), 0),
-                                             checkp->unlinkFrBack());
+            AstNode* const newp = new AstAnd{nodep->fileline(), new AstConst{nodep->fileline(), 0},
+                                             checkp->unlinkFrBack()};
             newp->dtypeFrom(nodep);
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         }
     }
     void replaceAllOnes(AstNode* nodep) {
-        V3Number ones(nodep, nodep->width(), 0);
+        V3Number ones{nodep, nodep->width(), 0};
         ones.setMask(nodep->width());
         VL_DO_DANGLING(replaceNum(nodep, ones), nodep);
     }
     void replaceConst(AstNodeUniop* nodep) {
-        V3Number num(nodep, nodep->width());
+        V3Number num{nodep, nodep->width()};
         nodep->numberOperate(num, VN_AS(nodep->lhsp(), Const)->num());
         UINFO(4, "UNICONST -> " << num << endl);
         VL_DO_DANGLING(replaceNum(nodep, num), nodep);
     }
     void replaceConst(AstNodeBiop* nodep) {
-        V3Number num(nodep, nodep->width());
+        V3Number num{nodep, nodep->width()};
         nodep->numberOperate(num, VN_AS(nodep->lhsp(), Const)->num(),
                              VN_AS(nodep->rhsp(), Const)->num());
         UINFO(4, "BICONST -> " << num << endl);
         VL_DO_DANGLING(replaceNum(nodep, num), nodep);
     }
     void replaceConst(AstNodeTriop* nodep) {
-        V3Number num(nodep, nodep->width());
+        V3Number num{nodep, nodep->width()};
         nodep->numberOperate(num, VN_AS(nodep->lhsp(), Const)->num(),
                              VN_AS(nodep->rhsp(), Const)->num(),
                              VN_AS(nodep->thsp(), Const)->num());
@@ -1617,7 +1617,7 @@ private:
         VL_DO_DANGLING(replaceNum(nodep, num), nodep);
     }
     void replaceConst(AstNodeQuadop* nodep) {
-        V3Number num(nodep, nodep->width());
+        V3Number num{nodep, nodep->width()};
         nodep->numberOperate(
             num, VN_AS(nodep->lhsp(), Const)->num(), VN_AS(nodep->rhsp(), Const)->num(),
             VN_AS(nodep->thsp(), Const)->num(), VN_AS(nodep->fhsp(), Const)->num());
@@ -1628,7 +1628,7 @@ private:
     void replaceConstString(AstNode* oldp, const string& num) {
         // Replace oldp node with a constant set to specified value
         UASSERT(oldp, "Null old");
-        AstNode* const newp = new AstConst(oldp->fileline(), AstConst::String(), num);
+        AstNode* const newp = new AstConst{oldp->fileline(), AstConst::String{}, num};
         if (debug() > 5) oldp->dumpTree(cout, "  const_old: ");
         if (debug() > 5) newp->dumpTree(cout, "       _new: ");
         oldp->replaceWith(newp);
@@ -1791,8 +1791,8 @@ private:
 
         UASSERT_OBJ((rstart + rwidth) == lstart, nodep,
                     "tried to merge two selects which are not adjacent");
-        AstSel* const newselp = new AstSel(
-            lselp->fromp()->fileline(), rselp->fromp()->cloneTree(false), rstart, lwidth + rwidth);
+        AstSel* const newselp = new AstSel{
+            lselp->fromp()->fileline(), rselp->fromp()->cloneTree(false), rstart, lwidth + rwidth};
         UINFO(5, "merged two adjacent sel " << lselp << " and " << rselp << " to one " << newselp
                                             << endl);
 
@@ -1809,8 +1809,8 @@ private:
         AstNodeExpr* const rlp = rp->lhsp()->cloneTree(false);
         AstNodeExpr* const rrp = rp->rhsp()->cloneTree(false);
         if (concatMergeable(lp, rp, 0)) {
-            AstConcat* const newlp = new AstConcat(rlp->fileline(), llp, rlp);
-            AstConcat* const newrp = new AstConcat(rrp->fileline(), lrp, rrp);
+            AstConcat* const newlp = new AstConcat{rlp->fileline(), llp, rlp};
+            AstConcat* const newrp = new AstConcat{rrp->fileline(), lrp, rrp};
             // use the lhs to replace the parent concat
             lp->lhsp()->replaceWith(newlp);
             lp->rhsp()->replaceWith(newrp);
@@ -1841,7 +1841,7 @@ private:
         UINFO(5, "POW(2,b)->SHIFTL(1,b) " << nodep << endl);
         AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
         AstShiftL* const newp
-            = new AstShiftL(nodep->fileline(), new AstConst(nodep->fileline(), 1), rhsp);
+            = new AstShiftL{nodep->fileline(), new AstConst{nodep->fileline(), 1}, rhsp};
         newp->dtypeFrom(nodep);
         newp->lhsp()->dtypeFrom(nodep);
         nodep->replaceWith(newp);
@@ -1852,7 +1852,7 @@ private:
         const int amount = VN_AS(nodep->lhsp(), Const)->num().mostSetBitP1() - 1;  // 2^n->n+1
         AstNodeExpr* const opp = nodep->rhsp()->unlinkFrBack();
         AstShiftL* const newp
-            = new AstShiftL(nodep->fileline(), opp, new AstConst(nodep->fileline(), amount));
+            = new AstShiftL{nodep->fileline(), opp, new AstConst(nodep->fileline(), amount)};
         newp->dtypeFrom(nodep);
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -1862,7 +1862,7 @@ private:
         const int amount = VN_AS(nodep->rhsp(), Const)->num().mostSetBitP1() - 1;  // 2^n->n+1
         AstNodeExpr* const opp = nodep->lhsp()->unlinkFrBack();
         AstShiftR* const newp
-            = new AstShiftR(nodep->fileline(), opp, new AstConst(nodep->fileline(), amount));
+            = new AstShiftR{nodep->fileline(), opp, new AstConst(nodep->fileline(), amount)};
         newp->dtypeFrom(nodep);
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -1870,11 +1870,11 @@ private:
     void replaceModAnd(AstModDiv* nodep) {  // Mod, but not ModS as not simple shift
         UINFO(5, "MOD(b,2^n)->AND(b,2^n-1) " << nodep << endl);
         const int amount = VN_AS(nodep->rhsp(), Const)->num().mostSetBitP1() - 1;  // 2^n->n+1
-        V3Number mask(nodep, nodep->width());
+        V3Number mask{nodep, nodep->width()};
         mask.setMask(amount);
         AstNodeExpr* const opp = nodep->lhsp()->unlinkFrBack();
         AstAnd* const newp
-            = new AstAnd(nodep->fileline(), opp, new AstConst(nodep->fileline(), mask));
+            = new AstAnd{nodep->fileline(), opp, new AstConst{nodep->fileline(), mask}};
         newp->dtypeFrom(nodep);
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -1929,29 +1929,29 @@ private:
             VL_DO_DANGLING(shift1p->deleteTree(), shift1p);
             VL_DO_DANGLING(shift2p->deleteTree(), shift2p);
             AstNodeExpr* newp;
-            V3Number mask1(nodep, nodep->width());
-            V3Number ones(nodep, nodep->width());
+            V3Number mask1{nodep, nodep->width()};
+            V3Number ones{nodep, nodep->width()};
             ones.setMask(nodep->width());
             if (shift1 < 0) {
                 mask1.opShiftR(ones, V3Number(nodep, VL_IDATASIZE, -shift1));
             } else {
                 mask1.opShiftL(ones, V3Number(nodep, VL_IDATASIZE, shift1));
             }
-            V3Number mask(nodep, nodep->width());
+            V3Number mask{nodep, nodep->width()};
             if (shift2 < 0) {
                 mask.opShiftR(mask1, V3Number(nodep, VL_IDATASIZE, -shift2));
             } else {
                 mask.opShiftL(mask1, V3Number(nodep, VL_IDATASIZE, shift2));
             }
             if (newshift < 0) {
-                newp = new AstShiftR(nodep->fileline(), ap,
-                                     new AstConst(nodep->fileline(), -newshift));
+                newp = new AstShiftR{nodep->fileline(), ap,
+                                     new AstConst(nodep->fileline(), -newshift)};
             } else {
-                newp = new AstShiftL(nodep->fileline(), ap,
-                                     new AstConst(nodep->fileline(), newshift));
+                newp = new AstShiftL{nodep->fileline(), ap,
+                                     new AstConst(nodep->fileline(), newshift)};
             }
             newp->dtypeFrom(nodep);
-            newp = new AstAnd(nodep->fileline(), newp, new AstConst(nodep->fileline(), mask));
+            newp = new AstAnd{nodep->fileline(), newp, new AstConst{nodep->fileline(), mask}};
             newp->dtypeFrom(nodep);
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -2004,13 +2004,13 @@ private:
         AstNodeExpr* const rhs2p = nextp->rhsp()->unlinkFrBack();
         AstNodeAssign* newp;
         if (lsbFirstAssign) {
-            newp = nodep->cloneType(new AstSel(sel1p->fileline(), varref1p->unlinkFrBack(),
-                                               sel1p->lsbConst(), sel1p->width() + sel2p->width()),
-                                    new AstConcat(rhs1p->fileline(), rhs2p, rhs1p));
+            newp = nodep->cloneType(new AstSel{sel1p->fileline(), varref1p->unlinkFrBack(),
+                                               sel1p->lsbConst(), sel1p->width() + sel2p->width()},
+                                    new AstConcat{rhs1p->fileline(), rhs2p, rhs1p});
         } else {
-            newp = nodep->cloneType(new AstSel(sel1p->fileline(), varref1p->unlinkFrBack(),
-                                               sel2p->lsbConst(), sel1p->width() + sel2p->width()),
-                                    new AstConcat(rhs1p->fileline(), rhs1p, rhs2p));
+            newp = nodep->cloneType(new AstSel{sel1p->fileline(), varref1p->unlinkFrBack(),
+                                               sel2p->lsbConst(), sel1p->width() + sel2p->width()},
+                                    new AstConcat{rhs1p->fileline(), rhs1p, rhs2p});
         }
         // pnewp->dumpTree(cout, "conew: ");
         nodep->replaceWith(newp);
@@ -2085,8 +2085,8 @@ private:
             const int msb1 = lsb1 + lc1p->width() - 1;
             UASSERT_OBJ(msb1 == (conp->width() - 1), nodep, "Width calc mismatch");
             // Form ranges
-            AstSel* const sel1p = new AstSel(conp->fileline(), rhsp, lsb1, msb1 - lsb1 + 1);
-            AstSel* const sel2p = new AstSel(conp->fileline(), rhs2p, lsb2, msb2 - lsb2 + 1);
+            AstSel* const sel1p = new AstSel{conp->fileline(), rhsp, lsb1, msb1 - lsb1 + 1};
+            AstSel* const sel2p = new AstSel{conp->fileline(), rhs2p, lsb2, msb2 - lsb2 + 1};
             // Make new assigns of same flavor as old one
             //*** Not cloneTree; just one node.
             AstNodeAssign* newp = nullptr;
@@ -2105,10 +2105,10 @@ private:
                 // if we make one per term.
                 AstVar* const temp1p
                     = new AstVar{sel1p->fileline(), VVarType::BLOCKTEMP,
-                                 m_concswapNames.get(sel1p), VFlagLogicPacked(), msb1 - lsb1 + 1};
+                                 m_concswapNames.get(sel1p), VFlagLogicPacked{}, msb1 - lsb1 + 1};
                 AstVar* const temp2p
                     = new AstVar{sel2p->fileline(), VVarType::BLOCKTEMP,
-                                 m_concswapNames.get(sel2p), VFlagLogicPacked(), msb2 - lsb2 + 1};
+                                 m_concswapNames.get(sel2p), VFlagLogicPacked{}, msb2 - lsb2 + 1};
                 m_modp->addStmtsp(temp1p);
                 m_modp->addStmtsp(temp2p);
                 AstNodeAssign* const asn1ap = nodep->cloneType(
@@ -2162,7 +2162,7 @@ private:
             streamp->dtypeSetLogicUnsized(srcp->width(), srcp->widthMin(), VSigning::UNSIGNED);
             // Shrink the RHS if necessary
             if (sWidth > dWidth) {
-                streamp = new AstSel(streamp->fileline(), streamp, sWidth - dWidth, dWidth);
+                streamp = new AstSel{streamp->fileline(), streamp, sWidth - dWidth, dWidth};
             }
             // Link the nodes back in
             nodep->lhsp(dstp);
@@ -2180,7 +2180,7 @@ private:
             AstNodeExpr* const streamp = VN_AS(nodep->lhsp(), StreamR)->unlinkFrBack();
             AstNodeExpr* srcp = nodep->rhsp()->unlinkFrBack();
             if (sWidth > dWidth) {
-                srcp = new AstSel(streamp->fileline(), srcp, sWidth - dWidth, dWidth);
+                srcp = new AstSel{streamp->fileline(), srcp, sWidth - dWidth, dWidth};
             }
             nodep->lhsp(dstp);
             nodep->rhsp(srcp);
@@ -2215,10 +2215,10 @@ private:
             = VN_AS(VN_AS(nodep, And)->rhsp(), ShiftR)->lhsp()->unlinkFrBack();
         AstConst* const shiftConstp
             = VN_AS(VN_AS(VN_AS(nodep, And)->rhsp(), ShiftR)->rhsp(), Const);
-        V3Number val(andConstp, andConstp->width());
+        V3Number val{andConstp, andConstp->width()};
         val.opShiftL(andConstp->num(), shiftConstp->num());
         AstAnd* const newp
-            = new AstAnd(nodep->fileline(), new AstConst(nodep->fileline(), val), fromp);
+            = new AstAnd{nodep->fileline(), new AstConst{nodep->fileline(), val}, fromp};
         // widthMin no longer applicable if different C-expanded width
         newp->dtypeSetLogicSized(nodep->width(), VSigning::UNSIGNED);
         nodep->replaceWith(newp);
@@ -2351,7 +2351,7 @@ private:
             bcConcp->unlinkFrBack();
             AstNodeExpr* const bp = bcConcp->lhsp()->unlinkFrBack();
             AstNodeExpr* const cp = bcConcp->rhsp()->unlinkFrBack();
-            AstConcat* const abConcp = new AstConcat(bcConcp->fileline(), ap, bp);
+            AstConcat* const abConcp = new AstConcat{bcConcp->fileline(), ap, bp};
             nodep->lhsp(abConcp);
             nodep->rhsp(cp);
             // If bp was a concat, then we have this exact same form again!
@@ -2364,7 +2364,7 @@ private:
             AstNodeExpr* const ap = abConcp->lhsp()->unlinkFrBack();
             AstNodeExpr* const bp = abConcp->rhsp()->unlinkFrBack();
             AstNodeExpr* const cp = nodep->rhsp()->unlinkFrBack();
-            AstConcat* const bcConcp = new AstConcat(abConcp->fileline(), bp, cp);
+            AstConcat* const bcConcp = new AstConcat{abConcp->fileline(), bp, cp};
             nodep->lhsp(ap);
             nodep->rhsp(bcConcp);
             if (operandConcatMove(bcConcp)) moveConcat(bcConcp);
@@ -2390,12 +2390,12 @@ private:
         AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
         AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
         // Do exactly as IEEE says, might result in extra terms, so in future may do differently
-        AstLogAnd* const newp = new AstLogAnd(
+        AstLogAnd* const newp = new AstLogAnd{
             nodep->fileline(),
-            new AstLogOr(nodep->fileline(), new AstLogNot(nodep->fileline(), lhsp), rhsp),
-            new AstLogOr(nodep->fileline(),
-                         new AstLogNot(nodep->fileline(), rhsp->cloneTree(false)),
-                         lhsp->cloneTree(false)));
+            new AstLogOr{nodep->fileline(), new AstLogNot{nodep->fileline(), lhsp}, rhsp},
+            new AstLogOr{nodep->fileline(),
+                         new AstLogNot{nodep->fileline(), rhsp->cloneTree(false)},
+                         lhsp->cloneTree(false)}};
         newp->dtypeFrom(nodep);
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -2412,8 +2412,8 @@ private:
         UINFO(4, "Elim Lower range: " << nodep << endl);
         AstNodeExpr* newlsbp;
         if (VN_IS(lsb1p, Const) && VN_IS(lsb2p, Const)) {
-            newlsbp = new AstConst(lsb1p->fileline(),
-                                   VN_AS(lsb1p, Const)->toUInt() + VN_AS(lsb2p, Const)->toUInt());
+            newlsbp = new AstConst{lsb1p->fileline(),
+                                   VN_AS(lsb1p, Const)->toUInt() + VN_AS(lsb2p, Const)->toUInt()};
             VL_DO_DANGLING(lsb1p->deleteTree(), lsb1p);
             VL_DO_DANGLING(lsb2p->deleteTree(), lsb2p);
         } else {
@@ -2433,7 +2433,7 @@ private:
             newlsbp = new AstAdd{lsb1p->fileline(), lhsp, rhsp};
             newlsbp->dtypeFrom(widep);
         }
-        AstSel* const newp = new AstSel(nodep->fileline(), fromp, newlsbp, widthp);
+        AstSel* const newp = new AstSel{nodep->fileline(), fromp, newlsbp, widthp};
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
@@ -2446,24 +2446,24 @@ private:
         if (static_cast<int>(nodep->lsbConst()) >= conRhsp->width()) {
             conLhsp->unlinkFrBack();
             AstSel* const newp
-                = new AstSel(nodep->fileline(), conLhsp, nodep->lsbConst() - conRhsp->width(),
-                             nodep->widthConst());
+                = new AstSel{nodep->fileline(), conLhsp, nodep->lsbConst() - conRhsp->width(),
+                             nodep->widthConst()};
             nodep->replaceWith(newp);
         } else if (static_cast<int>(nodep->msbConst()) < conRhsp->width()) {
             conRhsp->unlinkFrBack();
             AstSel* const newp
-                = new AstSel(nodep->fileline(), conRhsp, nodep->lsbConst(), nodep->widthConst());
+                = new AstSel{nodep->fileline(), conRhsp, nodep->lsbConst(), nodep->widthConst()};
             nodep->replaceWith(newp);
         } else {
             // Yuk, split between the two
             conRhsp->unlinkFrBack();
             conLhsp->unlinkFrBack();
             AstConcat* const newp
-                = new AstConcat(nodep->fileline(),
-                                new AstSel(nodep->fileline(), conLhsp, 0,
-                                           nodep->msbConst() - conRhsp->width() + 1),
-                                new AstSel(nodep->fileline(), conRhsp, nodep->lsbConst(),
-                                           conRhsp->width() - nodep->lsbConst()));
+                = new AstConcat{nodep->fileline(),
+                                new AstSel{nodep->fileline(), conLhsp, 0,
+                                           nodep->msbConst() - conRhsp->width() + 1},
+                                new AstSel{nodep->fileline(), conRhsp, nodep->lsbConst(),
+                                           conRhsp->width() - nodep->lsbConst()}};
             nodep->replaceWith(newp);
         }
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -2486,8 +2486,8 @@ private:
         fromp->unlinkFrBack();
         widthp->unlinkFrBack();
         AstSel* const newp
-            = new AstSel(nodep->fileline(), fromp,
-                         new AstConst(lsbp->fileline(), lsbp->toUInt() % fromp->width()), widthp);
+            = new AstSel{nodep->fileline(), fromp,
+                         new AstConst{lsbp->fileline(), lsbp->toUInt() % fromp->width()}, widthp};
         newp->dtypeFrom(nodep);
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -2506,7 +2506,7 @@ private:
         cnt1p->unlinkFrBack();
         cnt2p->unlinkFrBack();
         AstReplicate* const newp
-            = new AstReplicate(nodep->fileline(), from2p, cnt1p->toUInt() * cnt2p->toUInt());
+            = new AstReplicate{nodep->fileline(), from2p, cnt1p->toUInt() * cnt2p->toUInt()};
         newp->dtypeFrom(nodep);
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -2536,7 +2536,7 @@ private:
         if (!operandsSame(from1p, from2p)) return false;
         //
         from1p->unlinkFrBack();
-        AstReplicate* const newp = new AstReplicate(nodep->fileline(), from1p, cnt1 + cnt2);
+        AstReplicate* const newp = new AstReplicate{nodep->fileline(), from1p, cnt1 + cnt2};
         newp->dtypeFrom(nodep);
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -2553,8 +2553,8 @@ private:
         AstNodeExpr* const birhsp = fromp->rhsp()->unlinkFrBack();
         //
         fromp->lhsp(
-            new AstSel(nodep->fileline(), bilhsp, lsbp->cloneTree(true), widthp->cloneTree(true)));
-        fromp->rhsp(new AstSel(nodep->fileline(), birhsp, lsbp, widthp));
+            new AstSel{nodep->fileline(), bilhsp, lsbp->cloneTree(true), widthp->cloneTree(true)});
+        fromp->rhsp(new AstSel{nodep->fileline(), birhsp, lsbp, widthp});
         fromp->dtypeFrom(nodep);
         nodep->replaceWith(fromp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -2568,7 +2568,7 @@ private:
         //
         AstNodeExpr* const bilhsp = fromp->lhsp()->unlinkFrBack();
         //
-        fromp->lhsp(new AstSel(nodep->fileline(), bilhsp, lsbp, widthp));
+        fromp->lhsp(new AstSel{nodep->fileline(), bilhsp, lsbp, widthp});
         fromp->dtypeFrom(nodep);
         nodep->replaceWith(fromp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -2720,7 +2720,7 @@ private:
                     VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
                 }
             } else {  // Otherwise it may compute a result that needs to settle out
-                nodep->replaceWith(new AstSenItem(nodep->fileline(), AstSenItem::Combo()));
+                nodep->replaceWith(new AstSenItem{nodep->fileline(), AstSenItem::Combo{}});
                 VL_DO_DANGLING(nodep->deleteTree(), nodep);
             }
         } else if (m_doNConst && VN_IS(nodep->sensp(), Not)) {
@@ -2897,8 +2897,8 @@ private:
             // Make a initial assignment
             AstNodeExpr* const exprp = nodep->rhsp()->unlinkFrBack();
             varrefp->unlinkFrBack();
-            AstInitial* const newinitp = new AstInitial(
-                nodep->fileline(), new AstAssign(nodep->fileline(), varrefp, exprp));
+            AstInitial* const newinitp = new AstInitial{
+                nodep->fileline(), new AstAssign{nodep->fileline(), varrefp, exprp}};
             m_modp->addStmtsp(newinitp);
             VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
             // Set the initial value right in the variable so we can constant propagate
@@ -2958,8 +2958,8 @@ private:
                 if (nodep->thensp()) {  // Must have been comment
                     nodep->thensp()->unlinkFrBackWithNext()->deleteTree();
                 }
-                nodep->condp(new AstLogNot(condp->fileline(),
-                                           condp));  // LogNot, as C++ optimization also possible
+                nodep->condp(new AstLogNot{condp->fileline(),
+                                           condp});  // LogNot, as C++ optimization also possible
                 nodep->addThensp(elsesp);
             } else if (((VN_IS(nodep->condp(), Not) && nodep->condp()->width() == 1)
                         || VN_IS(nodep->condp(), LogNot))
@@ -2969,7 +2969,7 @@ private:
                     = VN_AS(nodep->condp(), NodeUniop)->lhsp()->unlinkFrBackWithNext();
                 AstNode* const thensp = nodep->thensp()->unlinkFrBackWithNext();
                 AstNode* const elsesp = nodep->elsesp()->unlinkFrBackWithNext();
-                AstIf* const ifp = new AstIf(nodep->fileline(), condp, elsesp, thensp);
+                AstIf* const ifp = new AstIf{nodep->fileline(), condp, elsesp, thensp};
                 ifp->branchPred(nodep->branchPred().invert());
                 nodep->replaceWith(ifp);
                 VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -2983,7 +2983,7 @@ private:
                 AstNodeExpr* const condp = nodep->condp()->unlinkFrBack();
                 AstNodeExpr* const truep = thensp->rhsp()->unlinkFrBack();
                 AstNodeExpr* const falsep = elsesp->rhsp()->unlinkFrBack();
-                thensp->rhsp(new AstCond(truep->fileline(), condp, truep, falsep));
+                thensp->rhsp(new AstCond{truep->fileline(), condp, truep, falsep});
                 nodep->replaceWith(thensp);
                 VL_DO_DANGLING(nodep->deleteTree(), nodep);
             } else if (false  // Disabled, as vpm assertions are faster
@@ -2994,7 +2994,7 @@ private:
                 AstNodeExpr* const condp = nodep->condp()->unlinkFrBack();
                 AstNode* const lowerThensp = lowerIfp->thensp()->unlinkFrBackWithNext();
                 AstNodeExpr* const lowerCondp = lowerIfp->condp()->unlinkFrBackWithNext();
-                nodep->condp(new AstLogAnd(lowerIfp->fileline(), condp, lowerCondp));
+                nodep->condp(new AstLogAnd{lowerIfp->fileline(), condp, lowerCondp});
                 lowerIfp->replaceWith(lowerThensp);
                 VL_DO_DANGLING(lowerIfp->deleteTree(), lowerIfp);
             } else if (operandBoolShift(nodep->condp())) {
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index f59ea4cea..f875fe300 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -449,7 +449,7 @@ private:
     void visit(AstTimePrecision* nodep) override { nodep->dtypeSetSigned32(); }
     void visit(AstTimeUnit* nodep) override {
         nodep->replaceWith(
-            new AstConst{nodep->fileline(), AstConst::Signed32(), nodep->timeunit().powerOfTen()});
+            new AstConst{nodep->fileline(), AstConst::Signed32{}, nodep->timeunit().powerOfTen()});
     }
     void visit(AstScopeName* nodep) override {
         nodep->dtypeSetUInt64();  // A pointer, but not that it matters
@@ -467,8 +467,8 @@ private:
             iterateCheckBool(nodep, "Conditional Test", nodep->condp(), BOTH);
             // Determine sub expression widths only relying on what's in the subops
             //  CONTEXT_DET determined, but need data type for pattern assignments
-            userIterateAndNext(nodep->thenp(), WidthVP(m_vup->dtypeNullp(), PRELIM).p());
-            userIterateAndNext(nodep->elsep(), WidthVP(m_vup->dtypeNullp(), PRELIM).p());
+            userIterateAndNext(nodep->thenp(), WidthVP{m_vup->dtypeNullp(), PRELIM}.p());
+            userIterateAndNext(nodep->elsep(), WidthVP{m_vup->dtypeNullp(), PRELIM}.p());
             // Calculate width of this expression.
             // First call (prelim()) m_vup->width() is probably zero, so we'll return
             //  the size of this subexpression only.
@@ -508,20 +508,20 @@ private:
         //   signed: Unsigned  (11.8.1)
         //   width: LHS + RHS
         AstNodeDType* const vdtypep = m_vup->dtypeNullSkipRefp();
-        userIterate(vdtypep, WidthVP(SELF, BOTH).p());
+        userIterate(vdtypep, WidthVP{SELF, BOTH}.p());
         // Conversions
         if (VN_IS(vdtypep, QueueDType)) {
             // Queue "element 0" is lhsp, so we need to swap arguments
-            auto* const newp = new AstConsQueue(nodep->fileline(), nodep->rhsp()->unlinkFrBack(),
-                                                nodep->lhsp()->unlinkFrBack());
+            auto* const newp = new AstConsQueue{nodep->fileline(), nodep->rhsp()->unlinkFrBack(),
+                                                nodep->lhsp()->unlinkFrBack()};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
             userIterateChildren(newp, m_vup);
             return;
         }
         if (VN_IS(vdtypep, DynArrayDType)) {
-            auto* const newp = new AstConsDynArray(
-                nodep->fileline(), nodep->rhsp()->unlinkFrBack(), nodep->lhsp()->unlinkFrBack());
+            auto* const newp = new AstConsDynArray{
+                nodep->fileline(), nodep->rhsp()->unlinkFrBack(), nodep->lhsp()->unlinkFrBack()};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
             userIterateChildren(newp, m_vup);
@@ -570,8 +570,8 @@ private:
         if (m_vup->final()) {
             if (nodep->lhsp()->isString() || nodep->rhsp()->isString()) {
                 AstNode* const newp
-                    = new AstConcatN(nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
-                                     nodep->rhsp()->unlinkFrBack());
+                    = new AstConcatN{nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
+                                     nodep->rhsp()->unlinkFrBack()};
                 nodep->replaceWith(newp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
                 return;
@@ -707,7 +707,7 @@ private:
                 }
                 // Don't iterate lhsp as SELF, the potential Concat below needs
                 // the adtypep passed down to recognize the QueueDType
-                userIterateAndNext(nodep->lhsp(), WidthVP(vdtypep, BOTH).p());
+                userIterateAndNext(nodep->lhsp(), WidthVP{vdtypep, BOTH}.p());
                 nodep->replaceWith(nodep->lhsp()->unlinkFrBack());
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
                 return;
@@ -719,8 +719,8 @@ private:
             iterateCheckSizedSelf(nodep, "LHS", nodep->lhsp(), SELF, BOTH);
             if (nodep->lhsp()->isString()) {
                 AstNode* const newp
-                    = new AstReplicateN(nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
-                                        nodep->rhsp()->unlinkFrBack());
+                    = new AstReplicateN{nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
+                                        nodep->rhsp()->unlinkFrBack()};
                 nodep->replaceWith(newp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
                 return;
@@ -820,8 +820,8 @@ private:
         UASSERT_OBJ(m_vup, nodep, "Select under an unexpected context");
         if (m_vup->prelim()) {
             if (debug() >= 9) nodep->dumpTree(cout, "-selWidth: ");
-            userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT_DET, PRELIM).p());
-            userIterateAndNext(nodep->lsbp(), WidthVP(SELF, PRELIM).p());
+            userIterateAndNext(nodep->fromp(), WidthVP{CONTEXT_DET, PRELIM}.p());
+            userIterateAndNext(nodep->lsbp(), WidthVP{SELF, PRELIM}.p());
             checkCvtUS(nodep->fromp());
             iterateCheckSizedSelf(nodep, "Select Width", nodep->widthp(), SELF, BOTH);
             iterateCheckSizedSelf(nodep, "Select LHS", nodep->lhsp(), SELF, BOTH);
@@ -841,7 +841,7 @@ private:
                 width = (nodep->lsbConst() - nodep->msbConst() + 1);
                 nodep->dtypeSetLogicSized(width, VSigning::UNSIGNED);
                 nodep->widthp()->replaceWith(new AstConst(nodep->widthp()->fileline(), width));
-                nodep->lsbp()->replaceWith(new AstConst(nodep->lsbp()->fileline(), 0));
+                nodep->lsbp()->replaceWith(new AstConst{nodep->lsbp()->fileline(), 0});
             }
             // We're extracting, so just make sure the expression is at least wide enough.
             if (nodep->fromp()->width() < width) {
@@ -870,8 +870,8 @@ private:
             const int selwidth = V3Number::log2b(frommsb + 1 - 1) + 1;  // Width to address a bit
             AstNodeDType* const selwidthDTypep
                 = nodep->findLogicDType(selwidth, selwidth, nodep->lsbp()->dtypep()->numeric());
-            userIterateAndNext(nodep->fromp(), WidthVP(SELF, FINAL).p());
-            userIterateAndNext(nodep->lsbp(), WidthVP(SELF, FINAL).p());
+            userIterateAndNext(nodep->fromp(), WidthVP{SELF, FINAL}.p());
+            userIterateAndNext(nodep->lsbp(), WidthVP{SELF, FINAL}.p());
             if (widthBad(nodep->lsbp(), selwidthDTypep) && nodep->lsbp()->width() != 32) {
                 if (!nodep->fileline()->warnIsOff(V3ErrorCode::WIDTH)) {
                     nodep->v3warn(WIDTH,
@@ -926,7 +926,7 @@ private:
         // LSB is self-determined (IEEE 2012 11.5.1)
         if (m_vup->prelim()) {
             iterateCheckSizedSelf(nodep, "Bit select", nodep->bitp(), SELF, BOTH);
-            userIterateAndNext(nodep->fromp(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->fromp(), WidthVP{SELF, BOTH}.p());
             //
             int frommsb;
             int fromlsb;
@@ -1021,7 +1021,7 @@ private:
     void visit(AstSliceSel* nodep) override {
         // Always creates as output an unpacked array
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->fromp(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->fromp(), WidthVP{SELF, BOTH}.p());
             //
             // Array indices are always constant
             const AstNodeDType* const fromDtp = nodep->fromp()->dtypep()->skipRefp();
@@ -1032,8 +1032,8 @@ private:
             }
             // Build new array Dtype based on the original's base type, but with new bounds
             AstNodeDType* const newDtp
-                = new AstUnpackArrayDType(nodep->fileline(), adtypep->subDTypep(),
-                                          new AstRange(nodep->fileline(), nodep->declRange()));
+                = new AstUnpackArrayDType{nodep->fileline(), adtypep->subDTypep(),
+                                          new AstRange{nodep->fileline(), nodep->declRange()}};
             v3Global.rootp()->typeTablep()->addTypesp(newDtp);
             nodep->dtypeFrom(newDtp);
 
@@ -1064,10 +1064,10 @@ private:
 
     void visit(AstSelBit* nodep) override {
         // Just a quick check as after V3Param these nodes instead are AstSel's
-        userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->thsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->attrp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->fromp(), WidthVP{CONTEXT_DET, PRELIM}.p());  // FINAL in AstSel
+        userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());  // FINAL in AstSel
+        userIterateAndNext(nodep->thsp(), WidthVP{CONTEXT_DET, PRELIM}.p());  // FINAL in AstSel
+        userIterateAndNext(nodep->attrp(), WidthVP{SELF, BOTH}.p());
         AstNode* const selp = V3Width::widthSelNoIterEdit(nodep);
         if (selp != nodep) {
             nodep = nullptr;
@@ -1078,10 +1078,10 @@ private:
     }
     void visit(AstSelExtract* nodep) override {
         // Just a quick check as after V3Param these nodes instead are AstSel's
-        userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->thsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->attrp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->fromp(), WidthVP{CONTEXT_DET, PRELIM}.p());  // FINAL in AstSel
+        userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());  // FINAL in AstSel
+        userIterateAndNext(nodep->thsp(), WidthVP{CONTEXT_DET, PRELIM}.p());  // FINAL in AstSel
+        userIterateAndNext(nodep->attrp(), WidthVP{SELF, BOTH}.p());
         AstNode* const selp = V3Width::widthSelNoIterEdit(nodep);
         if (selp != nodep) {
             nodep = nullptr;
@@ -1091,10 +1091,10 @@ private:
         nodep->v3fatalSrc("AstSelExtract should disappear after widthSel");
     }
     void visit(AstSelPlus* nodep) override {
-        userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->thsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->attrp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->fromp(), WidthVP{CONTEXT_DET, PRELIM}.p());  // FINAL in AstSel
+        userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());  // FINAL in AstSel
+        userIterateAndNext(nodep->thsp(), WidthVP{CONTEXT_DET, PRELIM}.p());  // FINAL in AstSel
+        userIterateAndNext(nodep->attrp(), WidthVP{SELF, BOTH}.p());
         AstNode* const selp = V3Width::widthSelNoIterEdit(nodep);
         if (selp != nodep) {
             nodep = nullptr;
@@ -1104,10 +1104,10 @@ private:
         nodep->v3fatalSrc("AstSelPlus should disappear after widthSel");
     }
     void visit(AstSelMinus* nodep) override {
-        userIterateAndNext(nodep->fromp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->thsp(), WidthVP(CONTEXT_DET, PRELIM).p());  // FINAL in AstSel
-        userIterateAndNext(nodep->attrp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->fromp(), WidthVP{CONTEXT_DET, PRELIM}.p());  // FINAL in AstSel
+        userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());  // FINAL in AstSel
+        userIterateAndNext(nodep->thsp(), WidthVP{CONTEXT_DET, PRELIM}.p());  // FINAL in AstSel
+        userIterateAndNext(nodep->attrp(), WidthVP{SELF, BOTH}.p());
         AstNode* const selp = V3Width::widthSelNoIterEdit(nodep);
         if (selp != nodep) {
             nodep = nullptr;
@@ -1223,8 +1223,8 @@ private:
         if (m_vup->prelim()) {
             nodep->dtypeSetUInt32();  // Says the spec
             AstNodeDType* const expDTypep = nodep->findUInt32DType();
-            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
-            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());
+            userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());
             iterateCheck(nodep, "LHS", nodep->lhsp(), SELF, FINAL, expDTypep, EXTEND_EXP);
             iterateCheck(nodep, "RHS", nodep->rhsp(), SELF, FINAL, expDTypep, EXTEND_EXP);
         }
@@ -1240,7 +1240,7 @@ private:
         if (const auto* const selp = VN_CAST(nodep->backp(), SelExtract)) {
             if (VN_IS(selp->fromp()->dtypep(), QueueDType)) {
                 nodep->replaceWith(
-                    new AstConst(nodep->fileline(), AstConst::Signed32(), 0x7FFFFFFF));
+                    new AstConst(nodep->fileline(), AstConst::Signed32{}, 0x7FFFFFFF));
                 VL_DO_DANGLING(nodep->deleteTree(), nodep);
                 return;
             }
@@ -1249,7 +1249,7 @@ private:
     }
     void visit(AstIsUnbounded* nodep) override {
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
             nodep->dtypeSetBit();
         }
     }
@@ -1258,7 +1258,7 @@ private:
         if (m_vup && m_vup->prelim()) {
             nodep->dtypeSetLogicUnsized(32, 1, VSigning::UNSIGNED);  // We don't care
             // All arguments seek their natural sizes
-            userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+            userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
         }
         if (m_vup->final()) {
             AstNodeDType* const expDTypep = m_vup->dtypeOverridep(nodep->dtypep());
@@ -1277,8 +1277,8 @@ private:
         // RHS is self-determined (IEEE)
         // Real if either side is real (as with AstAdd)
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
-            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());
+            userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());
             if (nodep->lhsp()->isDouble() || nodep->rhsp()->isDouble()) {
                 spliceCvtD(nodep->lhsp());
                 spliceCvtD(nodep->rhsp());
@@ -1298,14 +1298,14 @@ private:
             iterateCheck(nodep, "LHS", nodep->lhsp(), SELF, FINAL, nodep->dtypep(), EXTEND_EXP);
             AstNode* newp = nullptr;  // No change
             if (nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned()) {
-                newp = new AstPowSS(nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
-                                    nodep->rhsp()->unlinkFrBack());
+                newp = new AstPowSS{nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
+                                    nodep->rhsp()->unlinkFrBack()};
             } else if (nodep->lhsp()->isSigned() && !nodep->rhsp()->isSigned()) {
-                newp = new AstPowSU(nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
-                                    nodep->rhsp()->unlinkFrBack());
+                newp = new AstPowSU{nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
+                                    nodep->rhsp()->unlinkFrBack()};
             } else if (!nodep->lhsp()->isSigned() && nodep->rhsp()->isSigned()) {
-                newp = new AstPowUS(nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
-                                    nodep->rhsp()->unlinkFrBack());
+                newp = new AstPowUS{nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
+                                    nodep->rhsp()->unlinkFrBack()};
             }
             if (newp) {
                 newp->dtypeFrom(nodep);
@@ -1318,20 +1318,20 @@ private:
     void visit(AstPowSU* nodep) override {
         // POWSU/SS/US only created here, dtype already determined, so
         // nothing to do in this function
-        userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
-        userIterateAndNext(nodep->rhsp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
+        userIterateAndNext(nodep->rhsp(), WidthVP{SELF, BOTH}.p());
     }
     void visit(AstPowSS* nodep) override {
         // POWSU/SS/US only created here, dtype already determined, so
         // nothing to do in this function
-        userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
-        userIterateAndNext(nodep->rhsp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
+        userIterateAndNext(nodep->rhsp(), WidthVP{SELF, BOTH}.p());
     }
     void visit(AstPowUS* nodep) override {
         // POWSU/SS/US only created here, dtype already determined, so
         // nothing to do in this function
-        userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
-        userIterateAndNext(nodep->rhsp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
+        userIterateAndNext(nodep->rhsp(), WidthVP{SELF, BOTH}.p());
     }
     void visit(AstCountBits* nodep) override {
         if (m_vup->prelim()) {
@@ -1354,13 +1354,13 @@ private:
     }
     void visit(AstCvtPackString* nodep) override {
         // Opaque returns, so arbitrary
-        userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
         // Type set in constructor
     }
     void visit(AstTimeImport* nodep) override {
         // LHS is a real number in seconds
         // Need to round to time units and precision
-        userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
         const AstConst* const constp = VN_CAST(nodep->lhsp(), Const);
         if (!constp || !constp->isDouble()) nodep->v3fatalSrc("Times should be doubles");
         if (nodep->timeunit().isNone()) nodep->v3fatalSrc("$time import no units");
@@ -1368,7 +1368,7 @@ private:
         if (v3Global.rootp()->timeprecision().isNone()) nodep->v3fatalSrc("Never set precision?");
         time /= nodep->timeunit().multiplier();
         // IEEE claims you should round to time precision here, but no simulator seems to do this
-        AstConst* const newp = new AstConst(nodep->fileline(), AstConst::RealDouble(), time);
+        AstConst* const newp = new AstConst{nodep->fileline(), AstConst::RealDouble{}, time};
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
@@ -1400,8 +1400,8 @@ private:
     void visit(AstAttrOf* nodep) override {
         VL_RESTORER(m_attrp);
         m_attrp = nodep;
-        userIterateAndNext(nodep->fromp(), WidthVP(SELF, BOTH).p());
-        if (nodep->dimp()) userIterateAndNext(nodep->dimp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->fromp(), WidthVP{SELF, BOTH}.p());
+        if (nodep->dimp()) userIterateAndNext(nodep->dimp(), WidthVP{SELF, BOTH}.p());
         // Don't iterate children, don't want to lose VarRef.
         switch (nodep->attrType()) {
         case VAttrType::VAR_BASE:
@@ -1416,7 +1416,7 @@ private:
             const int val
                 = (nodep->attrType() == VAttrType::DIM_UNPK_DIMENSIONS ? dim.second
                                                                        : (dim.first + dim.second));
-            nodep->replaceWith(new AstConst(nodep->fileline(), AstConst::Signed32(), val));
+            nodep->replaceWith(new AstConst(nodep->fileline(), AstConst::Signed32{}, val));
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
             break;
         }
@@ -1443,7 +1443,7 @@ private:
                 }
                 case VAttrType::DIM_LEFT:
                 case VAttrType::DIM_LOW: {
-                    AstNode* const newp = new AstConst(nodep->fileline(), AstConst::Signed32(), 0);
+                    AstNode* const newp = new AstConst(nodep->fileline(), AstConst::Signed32{}, 0);
                     nodep->replaceWith(newp);
                     VL_DO_DANGLING(nodep->deleteTree(), nodep);
                     break;
@@ -1457,15 +1457,15 @@ private:
                     sizep->didWidth(true);
                     sizep->protect(false);
                     AstNode* const newp
-                        = new AstSub(nodep->fileline(), sizep,
-                                     new AstConst(nodep->fileline(), AstConst::Signed32(), 1));
+                        = new AstSub{nodep->fileline(), sizep,
+                                     new AstConst(nodep->fileline(), AstConst::Signed32{}, 1)};
                     nodep->replaceWith(newp);
                     VL_DO_DANGLING(nodep->deleteTree(), nodep);
                     break;
                 }
                 case VAttrType::DIM_INCREMENT: {
                     AstNodeExpr* const newp
-                        = new AstConst(nodep->fileline(), AstConst::Signed32(), -1);
+                        = new AstConst(nodep->fileline(), AstConst::Signed32{}, -1);
                     nodep->replaceWith(newp);
                     VL_DO_DANGLING(nodep->deleteTree(), nodep);
                     break;
@@ -1517,7 +1517,7 @@ private:
         case VAttrType::TYPENAME: {
             UASSERT_OBJ(nodep->fromp(), nodep, "Unprovided expression");
             const string result = nodep->fromp()->dtypep()->prettyDTypeName();
-            AstNode* const newp = new AstConst(nodep->fileline(), AstConst::String(), result);
+            AstNode* const newp = new AstConst{nodep->fileline(), AstConst::String{}, result};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
             break;
@@ -1533,7 +1533,7 @@ private:
     }
     void visit(AstPull* nodep) override {
         // May have select underneath, let seek natural size
-        userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+        userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
     }
     void visit(AstText* nodep) override {
         // Only used in CStmts which don't care....
@@ -1549,8 +1549,8 @@ private:
             if (basicp->implicit()) {
                 UASSERT_OBJ(basicp->width() <= 1, basicp,
                             "must be 1 bit but actually " << basicp->width() << " bits");
-                AstBasicDType* const newp = new AstBasicDType(
-                    basicp->fileline(), VBasicDTypeKwd::LOGIC, basicp->numeric());
+                AstBasicDType* const newp = new AstBasicDType{
+                    basicp->fileline(), VBasicDTypeKwd::LOGIC, basicp->numeric()};
                 newp->widthForce(1, 1);
                 basicp->replaceWith(newp);
                 VL_DO_DANGLING(pushDeletep(basicp), basicp);
@@ -1559,7 +1559,7 @@ private:
         // Iterate into subDTypep() to resolve that type and update pointer.
         nodep->refDTypep(iterateEditMoveDTypep(nodep, nodep->subDTypep()));
         // Cleanup array size
-        userIterateAndNext(nodep->rangep(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->rangep(), WidthVP{SELF, BOTH}.p());
         nodep->dtypep(nodep);  // The array itself, not subDtype
         if (auto* const adtypep = VN_CAST(nodep, UnpackArrayDType)) {
             // Historically array elements have width of the ref type not the full array
@@ -1582,7 +1582,7 @@ private:
     void visit(AstBracketArrayDType* nodep) override {
         // Type inserted only because parser didn't know elementsp() type
         // Resolve elementsp's type
-        userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+        userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
         // We must edit when dtype still under normal nodes and before type table
         // See notes in iterateEditMoveDTypep
         AstNodeDType* const childp = nodep->childDTypep();
@@ -1590,17 +1590,17 @@ private:
         AstNode* const elementsp = nodep->elementsp()->unlinkFrBack();
         AstNode* newp;
         if (VN_IS(elementsp, Unbounded)) {
-            newp = new AstQueueDType(nodep->fileline(), VFlagChildDType(), childp, nullptr);
+            newp = new AstQueueDType{nodep->fileline(), VFlagChildDType{}, childp, nullptr};
             VL_DO_DANGLING(elementsp->deleteTree(), elementsp);
         } else if (AstNodeDType* const keyp = VN_CAST(elementsp, NodeDType)) {
-            newp = new AstAssocArrayDType(nodep->fileline(), VFlagChildDType(), childp, keyp);
+            newp = new AstAssocArrayDType{nodep->fileline(), VFlagChildDType{}, childp, keyp};
         } else {
             // Must be expression that is constant, but we'll determine that later
-            newp = new AstUnpackArrayDType(
-                nodep->fileline(), VFlagChildDType(), childp,
-                new AstRange(nodep->fileline(), new AstConst(elementsp->fileline(), 0),
-                             new AstSub(elementsp->fileline(), VN_AS(elementsp, NodeExpr),
-                                        new AstConst(elementsp->fileline(), 1))));
+            newp = new AstUnpackArrayDType{
+                nodep->fileline(), VFlagChildDType{}, childp,
+                new AstRange{nodep->fileline(), new AstConst(elementsp->fileline(), 0),
+                             new AstSub{elementsp->fileline(), VN_AS(elementsp, NodeExpr),
+                                        new AstConst(elementsp->fileline(), 1)}}};
         }
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -1650,7 +1650,7 @@ private:
         if (nodep->didWidthAndSet()) return;  // This node is a dtype & not both PRELIMed+FINALed
         if (nodep->generic()) return;  // Already perfect
         if (nodep->rangep()) {
-            userIterateAndNext(nodep->rangep(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->rangep(), WidthVP{SELF, BOTH}.p());
             // Because this DType has a unique child range, we know it's not
             // pointed at by other nodes unless they are referencing this type.
             // Furthermore the width() calculation would return identical
@@ -1689,7 +1689,7 @@ private:
         nodep->doingWidth(true);
         if (nodep->typeofp()) {  // type(typeofp_expression)
             // Type comes from expression's type
-            userIterateAndNext(nodep->typeofp(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->typeofp(), WidthVP{SELF, BOTH}.p());
             AstNode* const typeofp = nodep->typeofp();
             nodep->typedefp(nullptr);
             nodep->refDTypep(typeofp->dtypep());
@@ -1740,7 +1740,7 @@ private:
     }
     void visit(AstCastDynamic* nodep) override {
         nodep->dtypeChgWidthSigned(32, 1, VSigning::SIGNED);  // Spec says integer return
-        userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+        userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
         AstNodeDType* const toDtp = nodep->top()->dtypep()->skipRefToEnump();
         AstNodeDType* const fromDtp = nodep->fromp()->dtypep()->skipRefToEnump();
         FileLine* const fl = nodep->fileline();
@@ -1823,7 +1823,7 @@ private:
         if (AstConst* const constp = VN_CAST(nodep->dtp(), Const)) {
             constp->unlinkFrBack();
             AstNode* const newp
-                = new AstCastSize(nodep->fileline(), nodep->lhsp()->unlinkFrBack(), constp);
+                = new AstCastSize{nodep->fileline(), nodep->lhsp()->unlinkFrBack(), constp};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
             userIterate(newp, m_vup);
@@ -1840,7 +1840,7 @@ private:
         if (m_vup->prelim()) {
             // if (debug()) nodep->dumpTree(cout, "  CastPre: ");
             // if (debug()) nodep->backp()->dumpTree(cout, "  CastPreUpUp: ");
-            userIterateAndNext(nodep->fromp(), WidthVP(SELF, PRELIM).p());
+            userIterateAndNext(nodep->fromp(), WidthVP{SELF, PRELIM}.p());
             AstNodeDType* const toDtp = nodep->dtypep()->skipRefToEnump();
             AstNodeDType* const fromDtp = nodep->fromp()->dtypep()->skipRefToEnump();
             const auto castable = computeCastable(toDtp, fromDtp, nodep->fromp());
@@ -1885,23 +1885,23 @@ private:
                 }
                 if (basicp->isDouble() && !nodep->fromp()->isDouble()) {
                     if (nodep->fromp()->isSigned()) {
-                        newp = new AstISToRD(nodep->fileline(), nodep->fromp()->unlinkFrBack());
+                        newp = new AstISToRD{nodep->fileline(), nodep->fromp()->unlinkFrBack()};
                     } else {
-                        newp = new AstIToRD(nodep->fileline(), nodep->fromp()->unlinkFrBack());
+                        newp = new AstIToRD{nodep->fileline(), nodep->fromp()->unlinkFrBack()};
                     }
                 } else if (!basicp->isDouble() && nodep->fromp()->isDouble()) {
                     if (basicp->isSigned()) {
                         newp
-                            = new AstRToIRoundS(nodep->fileline(), nodep->fromp()->unlinkFrBack());
+                            = new AstRToIRoundS{nodep->fileline(), nodep->fromp()->unlinkFrBack()};
                     } else {
-                        newp = new AstUnsigned(
+                        newp = new AstUnsigned{
                             nodep->fileline(),
-                            new AstRToIS(nodep->fileline(), nodep->fromp()->unlinkFrBack()));
+                            new AstRToIS{nodep->fileline(), nodep->fromp()->unlinkFrBack()}};
                     }
                 } else if (basicp->isSigned() && !nodep->fromp()->isSigned()) {
-                    newp = new AstSigned(nodep->fileline(), nodep->fromp()->unlinkFrBack());
+                    newp = new AstSigned{nodep->fileline(), nodep->fromp()->unlinkFrBack()};
                 } else if (!basicp->isSigned() && nodep->fromp()->isSigned()) {
-                    newp = new AstUnsigned(nodep->fileline(), nodep->fromp()->unlinkFrBack());
+                    newp = new AstUnsigned{nodep->fileline(), nodep->fromp()->unlinkFrBack()};
                 } else {
                     // Can just remove cast, but need extend placeholder
                     // so we can avoid warning message
@@ -1938,7 +1938,7 @@ private:
                 nodep->v3error("Size-changing cast to zero or negative size");
                 width = 1;
             }
-            userIterateAndNext(nodep->lhsp(), WidthVP(SELF, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{SELF, PRELIM}.p());
             castSized(nodep, nodep->lhsp(), width);  // lhsp may change
         }
         if (m_vup->final()) {
@@ -1999,7 +1999,7 @@ private:
             UASSERT_OBJ(nodep->valuep(), nodep, "circular, but without value");
             nodep->v3error("Variable's initial value is circular: " << nodep->prettyNameQ());
             pushDeletep(nodep->valuep()->unlinkFrBack());
-            nodep->valuep(new AstConst(nodep->fileline(), AstConst::BitTrue()));
+            nodep->valuep(new AstConst{nodep->fileline(), AstConst::BitTrue{}});
             nodep->dtypeFrom(nodep->valuep());
             nodep->didWidth(true);
             return;
@@ -2013,7 +2013,7 @@ private:
             if (!(m_ftaskp && m_ftaskp->dpiImport())) {
                 UINFO(9, "Unsized becomes dynamic array " << nodep << endl);
                 AstDynArrayDType* const newp
-                    = new AstDynArrayDType(unsizedp->fileline(), unsizedp->subDTypep());
+                    = new AstDynArrayDType{unsizedp->fileline(), unsizedp->subDTypep()};
                 nodep->dtypep(newp);
                 v3Global.rootp()->typeTablep()->addTypesp(newp);
             }
@@ -2025,7 +2025,7 @@ private:
         const bool implicitParam = nodep->isParam() && bdtypep && bdtypep->implicit();
         if (implicitParam) {
             if (nodep->valuep()) {
-                userIterateAndNext(nodep->valuep(), WidthVP(nodep->dtypep(), PRELIM).p());
+                userIterateAndNext(nodep->valuep(), WidthVP{nodep->dtypep(), PRELIM}.p());
                 UINFO(9, "implicitParamPRELIMIV " << nodep->valuep() << endl);
                 // Although nodep will get a different width for parameters
                 // just below, we want the init numbers to retain their
@@ -2093,7 +2093,7 @@ private:
         if (nodep->valuep() && !didchk) {
             // if (debug()) nodep->dumpTree(cout, "  final: ");
             // AstPattern requires assignments to pass datatype on PRELIM
-            userIterateAndNext(nodep->valuep(), WidthVP(nodep->dtypep(), PRELIM).p());
+            userIterateAndNext(nodep->valuep(), WidthVP{nodep->dtypep(), PRELIM}.p());
             iterateCheckAssign(nodep, "Initial value", nodep->valuep(), FINAL, nodep->dtypep());
         }
         UINFO(4, "varWidthed " << nodep << endl);
@@ -2146,7 +2146,7 @@ private:
         nodep->dtypep(nodep);
         nodep->widthFromSub(nodep->subDTypep());
         // Assign widths
-        userIterateAndNext(nodep->itemsp(), WidthVP(nodep->dtypep(), BOTH).p());
+        userIterateAndNext(nodep->itemsp(), WidthVP{nodep->dtypep(), BOTH}.p());
         // Assign missing values
         V3Number num(nodep, nodep->width(), 0);
         const V3Number one{nodep, nodep->width(), 1};
@@ -2179,7 +2179,7 @@ private:
                     itemp->v3error("Enum names without values only allowed on numeric types");
                     // as can't +1 to resolve them.
                 }
-                itemp->valuep(new AstConst(itemp->fileline(), num));
+                itemp->valuep(new AstConst{itemp->fileline(), num});
             }
 
             const AstConst* const constp = VN_AS(itemp->valuep(), Const);
@@ -2212,7 +2212,7 @@ private:
         nodep->dtypep(vdtypep);
         if (nodep->valuep()) {  // else the value will be assigned sequentially
             // Default type is int, but common to assign narrower values, so minwidth from value
-            userIterateAndNext(nodep->valuep(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->valuep(), WidthVP{CONTEXT_DET, PRELIM}.p());
             // Minwidth does not come from value, as spec says set based on parent
             // and if we keep minwidth we'll consider it unsized which is incorrect
             iterateCheck(nodep, "Enum value", nodep->valuep(), CONTEXT_DET, FINAL, nodep->dtypep(),
@@ -2253,7 +2253,7 @@ private:
         UASSERT_OBJ(vdtypep, nodep, "SetsAssoc requires assoc upper parent data type");
         if (m_vup->prelim()) {
             nodep->dtypeFrom(vdtypep);
-            userIterateAndNext(nodep->lhsp(), WidthVP(vdtypep, BOTH).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{vdtypep, BOTH}.p());
             iterateCheck(nodep, "key", nodep->keyp(), CONTEXT_DET, FINAL, vdtypep->keyDTypep(),
                          EXTEND_EXP);
             iterateCheck(nodep, "value", nodep->valuep(), CONTEXT_DET, FINAL, vdtypep->subDTypep(),
@@ -2290,8 +2290,8 @@ private:
         AstDynArrayDType* const vdtypep = VN_AS(m_vup->dtypep()->skipRefp(), DynArrayDType);
         UASSERT_OBJ(vdtypep, nodep, "ConsDynArray requires queue upper parent data type");
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(vdtypep, PRELIM).p());
-            userIterateAndNext(nodep->rhsp(), WidthVP(vdtypep, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{vdtypep, PRELIM}.p());
+            userIterateAndNext(nodep->rhsp(), WidthVP{vdtypep, PRELIM}.p());
             nodep->dtypeFrom(vdtypep);
         }
         if (m_vup->final()) {
@@ -2322,8 +2322,8 @@ private:
         AstQueueDType* const vdtypep = VN_AS(m_vup->dtypep()->skipRefp(), QueueDType);
         UASSERT_OBJ(vdtypep, nodep, "ConsQueue requires queue upper parent data type");
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(vdtypep, PRELIM).p());
-            userIterateAndNext(nodep->rhsp(), WidthVP(vdtypep, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{vdtypep, PRELIM}.p());
+            userIterateAndNext(nodep->rhsp(), WidthVP{vdtypep, PRELIM}.p());
             nodep->dtypeFrom(vdtypep);
         }
         if (m_vup->final()) {
@@ -2332,7 +2332,7 @@ private:
             if (nodep->lhsp()) {
                 if (VN_IS(nodep->lhsp()->dtypep(), QueueDType)
                     || VN_IS(nodep->lhsp(), ConsQueue)) {
-                    userIterateAndNext(nodep->lhsp(), WidthVP(vdtypep, FINAL).p());
+                    userIterateAndNext(nodep->lhsp(), WidthVP{vdtypep, FINAL}.p());
                 } else {
                     // Sub elements are not queues, but concats, must always pass concats down
                     iterateCheckTyped(nodep, "LHS", nodep->lhsp(), vdtypep->subDTypep(), FINAL);
@@ -2368,10 +2368,10 @@ private:
         }
     }
     void visit(AstInside* nodep) override {
-        userIterateAndNext(nodep->exprp(), WidthVP(CONTEXT_DET, PRELIM).p());
+        userIterateAndNext(nodep->exprp(), WidthVP{CONTEXT_DET, PRELIM}.p());
         for (AstNode *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) {
             nextip = itemp->nextp();  // iterate may cause the node to get replaced
-            VL_DO_DANGLING(userIterate(itemp, WidthVP(CONTEXT_DET, PRELIM).p()), itemp);
+            VL_DO_DANGLING(userIterate(itemp, WidthVP{CONTEXT_DET, PRELIM}.p()), itemp);
         }
         // Take width as maximum across all items
         int width = nodep->exprp()->width();
@@ -2413,16 +2413,16 @@ private:
                     "Inside operator not legal on non-unpacked arrays (IEEE 1800-2017 11.4.13)");
                 continue;
             } else {
-                inewp = new AstEqWild(itemp->fileline(), nodep->exprp()->cloneTree(true),
-                                      itemp->unlinkFrBack());
+                inewp = new AstEqWild{itemp->fileline(), nodep->exprp()->cloneTree(true),
+                                      itemp->unlinkFrBack()};
             }
             if (newp) {
-                newp = new AstOr(nodep->fileline(), newp, inewp);
+                newp = new AstOr{nodep->fileline(), newp, inewp};
             } else {
                 newp = inewp;
             }
         }
-        if (!newp) newp = new AstConst(nodep->fileline(), AstConst::BitFalse());
+        if (!newp) newp = new AstConst{nodep->fileline(), AstConst::BitFalse{}};
         if (debug() >= 9) newp->dumpTree(cout, "-inside-out: ");
         nodep->replaceWith(newp);
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
@@ -2522,7 +2522,7 @@ private:
     void visit(AstMemberSel* nodep) override {
         UINFO(5, "   MEMBERSEL " << nodep << endl);
         if (debug() >= 9) nodep->dumpTree("-mbs-in: ");
-        userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+        userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
         if (debug() >= 9) nodep->dumpTree("-mbs-ic: ");
         // Find the fromp dtype - should be a class
         if (!nodep->fromp()->dtypep()) nodep->fromp()->v3fatalSrc("Unlinked data type");
@@ -2570,8 +2570,8 @@ private:
                    || VN_IS(fromDtp, BasicDType)) {
             // Method call on enum without following parenthesis, e.g. "ENUM.next"
             // Convert this into a method call, and let that visitor figure out what to do next
-            AstNode* const newp = new AstMethodCall(
-                nodep->fileline(), nodep->fromp()->unlinkFrBack(), nodep->name(), nullptr);
+            AstNode* const newp = new AstMethodCall{
+                nodep->fileline(), nodep->fromp()->unlinkFrBack(), nodep->name(), nullptr};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
             userIterate(newp, m_vup);
@@ -2582,7 +2582,7 @@ private:
                            << nodep->fromp()->dtypep()->prettyTypeName() << "'");
         }
         // Error handling
-        nodep->replaceWith(new AstConst(nodep->fileline(), AstConst::BitFalse()));
+        nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}});
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
     }
     AstNode* memberSelClass(AstMemberSel* nodep, AstClassRefDType* adtypep) {
@@ -2638,8 +2638,8 @@ private:
                 UINFO(9, "   MEMBERSEL(attr) -> " << nodep << endl);
                 UINFO(9, "           dt-> " << nodep->dtypep() << endl);
             } else {
-                AstSel* const newp = new AstSel(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                                memberp->lsb(), memberp->width());
+                AstSel* const newp = new AstSel{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                                memberp->lsb(), memberp->width()};
                 // Must skip over the member to find the union; as the member may disappear later
                 newp->dtypep(memberp->subDTypep()->skipRefToEnump());
                 newp->didWidth(true);  // Don't replace dtype with basic type
@@ -2666,17 +2666,17 @@ private:
         if (nodep->didWidth()) return;
         if (debug() >= 9) nodep->dumpTree("-mts-in: ");
         // Should check types the method requires, but at present we don't do much
-        userIterate(nodep->fromp(), WidthVP(SELF, BOTH).p());
+        userIterate(nodep->fromp(), WidthVP{SELF, BOTH}.p());
         // Any AstWith is checked later when know types, in methodWithArgument
         for (AstArg* argp = VN_CAST(nodep->pinsp(), Arg); argp; argp = VN_AS(argp->nextp(), Arg)) {
-            if (argp->exprp()) userIterate(argp->exprp(), WidthVP(SELF, BOTH).p());
+            if (argp->exprp()) userIterate(argp->exprp(), WidthVP{SELF, BOTH}.p());
         }
         // Find the fromp dtype - should be a class
         UASSERT_OBJ(nodep->fromp() && nodep->fromp()->dtypep(), nodep, "Unsized expression");
         AstNodeDType* const fromDtp = nodep->fromp()->dtypep()->skipRefToEnump();
         AstBasicDType* const basicp = fromDtp ? fromDtp->basicp() : nullptr;
         UINFO(9, "     from dt " << fromDtp << endl);
-        userIterate(fromDtp, WidthVP(SELF, BOTH).p());
+        userIterate(fromDtp, WidthVP{SELF, BOTH}.p());
         if (AstEnumDType* const adtypep = VN_CAST(fromDtp, EnumDType)) {
             methodCallEnum(nodep, adtypep);
         } else if (AstAssocArrayDType* const adtypep = VN_CAST(fromDtp, AssocArrayDType)) {
@@ -2739,7 +2739,7 @@ private:
             // Adjust to required argument counts, very bogus, but avoids core dump
             for (; narg < minArg; ++narg) {
                 nodep->addPinsp(
-                    new AstArg(nodep->fileline(), "", new AstConst(nodep->fileline(), 0)));
+                    new AstArg{nodep->fileline(), "", new AstConst(nodep->fileline(), 0)});
             }
             for (; narg > maxArg; --narg) {
                 AstNode* argp = nodep->pinsp();
@@ -2762,11 +2762,11 @@ private:
             if (nodep->name() == "num") {
                 int items = 0;
                 for (AstNode* itemp = adtypep->itemsp(); itemp; itemp = itemp->nextp()) ++items;
-                newp = new AstConst(nodep->fileline(), AstConst::Signed32(), items);
+                newp = new AstConst(nodep->fileline(), AstConst::Signed32{}, items);
             } else if (nodep->name() == "first") {
                 const AstEnumItem* itemp = adtypep->itemsp();
                 if (!itemp) {
-                    newp = new AstConst(nodep->fileline(), AstConst::Signed32(),
+                    newp = new AstConst(nodep->fileline(), AstConst::Signed32{},
                                         0);  // Spec doesn't say what to do
                 } else {
                     newp = VN_AS(itemp->valuep()->cloneTree(false), Const);  // A const
@@ -2776,7 +2776,7 @@ private:
                 const AstEnumItem* itemp = adtypep->itemsp();
                 while (itemp && itemp->nextp()) itemp = VN_AS(itemp->nextp(), EnumItem);
                 if (!itemp) {
-                    newp = new AstConst(nodep->fileline(), AstConst::Signed32(),
+                    newp = new AstConst(nodep->fileline(), AstConst::Signed32{},
                                         0);  // Spec doesn't say what to do
                 } else {
                     newp = VN_AS(itemp->valuep()->cloneTree(false), Const);  // A const
@@ -2814,9 +2814,9 @@ private:
                 const uint32_t stepWidth
                     = VN_AS(VN_AS(nodep->pinsp(), Arg)->exprp(), Const)->toUInt();
                 AstConst* const constp = new AstConst(nodep->fileline(), stepWidth - 1);
-                AstArg* const argp = new AstArg(nodep->fileline(), "", constp);
+                AstArg* const argp = new AstArg{nodep->fileline(), "", constp};
                 AstMethodCall* const newp
-                    = new AstMethodCall(nodep->fileline(), clonep, nodep->name(), argp);
+                    = new AstMethodCall{nodep->fileline(), clonep, nodep->name(), argp};
                 nodep->replaceWith(newp);
                 VL_DO_DANGLING(nodep->deleteTree(), nodep);
                 return;
@@ -2833,12 +2833,12 @@ private:
             } else {
                 const int selwidth = V3Number::log2b(msbdim) + 1;  // Width to address a bit
                 AstVar* const varp = enumVarp(adtypep, attrType, false, (1ULL << selwidth) - 1);
-                AstNode* const newp = new AstArraySel(
+                AstNode* const newp = new AstArraySel{
                     nodep->fileline(), newVarRefDollarUnit(varp),
                     // Select in case widths are off due to msblen!=width
                     // We return "random" values if outside the range, which is fine
                     // as next/previous on illegal values just need something good out
-                    new AstSel(nodep->fileline(), nodep->fromp()->unlinkFrBack(), 0, selwidth));
+                    new AstSel{nodep->fileline(), nodep->fromp()->unlinkFrBack(), 0, selwidth}};
                 newp->dtypeFrom(adtypep);  // To prevent a later ENUMVALUE
                 nodep->replaceWith(newp);
             }
@@ -2935,8 +2935,8 @@ private:
         if (nodep->name() == "num"  // function int num()
             || nodep->name() == "size") {
             methodOkArguments(nodep, 0, 0);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      "size");  // So don't need num()
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      "size"};  // So don't need num()
             newp->dtypeSetSigned32();
         } else if (nodep->name() == "first"  // function int first(ref index)
                    || nodep->name() == "last"  //
@@ -2944,30 +2944,30 @@ private:
                    || nodep->name() == "prev") {
             methodOkArguments(nodep, 1, 1);
             AstNodeExpr* const index_exprp = methodCallAssocIndexExpr(nodep, adtypep);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
                                       nodep->name(),  // first/last/next/prev
-                                      index_exprp->unlinkFrBack());
+                                      index_exprp->unlinkFrBack()};
             newp->dtypeSetSigned32();
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "exists") {  // function int exists(input index)
             // IEEE really should have made this a "bit" return
             methodOkArguments(nodep, 1, 1);
             AstNodeExpr* const index_exprp = methodCallAssocIndexExpr(nodep, adtypep);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "exists",
-                                      index_exprp->unlinkFrBack());
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), "exists",
+                                      index_exprp->unlinkFrBack()};
             newp->dtypeSetSigned32();
             newp->pure(true);
         } else if (nodep->name() == "delete") {  // function void delete([input integer index])
             methodOkArguments(nodep, 0, 1);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
             if (!nodep->pinsp()) {
-                newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                          "clear");
+                newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                          "clear"};
                 newp->dtypeSetVoid();
             } else {
                 AstNodeExpr* const index_exprp = methodCallAssocIndexExpr(nodep, adtypep);
-                newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                          "erase", index_exprp->unlinkFrBack());
+                newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                          "erase", index_exprp->unlinkFrBack()};
                 newp->dtypeSetVoid();
             }
         } else if (nodep->name() == "sort" || nodep->name() == "rsort"
@@ -2981,16 +2981,16 @@ private:
                                                       adtypep->keyDTypep(), adtypep->subDTypep());
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      "r_" + nodep->name(), withp);
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      "r_" + nodep->name(), withp};
             newp->dtypeFrom(withp ? withp->dtypep() : adtypep->subDTypep());
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "min" || nodep->name() == "max" || nodep->name() == "unique"
                    || nodep->name() == "unique_index") {
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name());
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name()};
             if (nodep->name() == "unique_index") {
                 newp->dtypep(queueDTypeIndexedBy(adtypep->keyDTypep()));
             } else {
@@ -3003,8 +3003,8 @@ private:
                                                       adtypep->keyDTypep(), adtypep->subDTypep());
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name(), withp);
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name(), withp};
             newp->dtypeFrom(adtypep);
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "find_index" || nodep->name() == "find_first_index"
@@ -3013,8 +3013,8 @@ private:
                                                       adtypep->keyDTypep(), adtypep->subDTypep());
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name(), withp);
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name(), withp};
             newp->dtypep(queueDTypeIndexedBy(adtypep->keyDTypep()));
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else {
@@ -3061,16 +3061,16 @@ private:
         if (nodep->name() == "at") {  // Created internally for []
             methodOkArguments(nodep, 1, 1);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "at");
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), "at"};
             newp->dtypeFrom(adtypep->subDTypep());
         } else if (nodep->name() == "size") {
             methodOkArguments(nodep, 0, 0);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size");
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size"};
             newp->dtypeSetSigned32();
         } else if (nodep->name() == "delete") {  // function void delete()
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "clear");
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), "clear"};
             newp->dtypeSetVoid();
         } else if (nodep->name() == "and" || nodep->name() == "or" || nodep->name() == "xor"
                    || nodep->name() == "sum" || nodep->name() == "product") {
@@ -3080,8 +3080,8 @@ private:
                                      nodep->findUInt32DType(), adtypep->subDTypep());
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      "r_" + nodep->name(), withp);
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      "r_" + nodep->name(), withp};
             newp->dtypeFrom(adtypep->subDTypep());
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "reverse" || nodep->name() == "shuffle"
@@ -3093,15 +3093,15 @@ private:
             }
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name(), withp);
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name(), withp};
             newp->dtypeSetVoid();
         } else if (nodep->name() == "min" || nodep->name() == "max" || nodep->name() == "unique"
                    || nodep->name() == "unique_index") {
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name());
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name()};
             if (nodep->name() == "unique_index") {
                 newp->dtypep(newp->findQueueIndexDType());
             } else {
@@ -3115,8 +3115,8 @@ private:
                                      nodep->findUInt32DType(), adtypep->subDTypep());
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name(), withp);
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name(), withp};
             newp->dtypeFrom(adtypep);
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "find_index" || nodep->name() == "find_first_index"
@@ -3126,8 +3126,8 @@ private:
                                      nodep->findUInt32DType(), adtypep->subDTypep());
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name(), withp);
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name(), withp};
             newp->dtypep(newp->findQueueIndexDType());
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else {
@@ -3147,30 +3147,30 @@ private:
         if (nodep->name() == "at") {  // Created internally for []
             methodOkArguments(nodep, 1, 1);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "at");
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), "at"};
             newp->dtypeFrom(adtypep->subDTypep());
         } else if (nodep->name() == "num"  // function int num()
                    || nodep->name() == "size") {
             methodOkArguments(nodep, 0, 0);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size");
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), "size"};
             newp->dtypeSetSigned32();
         } else if (nodep->name() == "delete") {  // function void delete([input integer index])
             methodOkArguments(nodep, 0, 1);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
             if (!nodep->pinsp()) {
-                newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                          "clear");
+                newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                          "clear"};
                 newp->dtypeSetVoid();
             } else {
                 AstNodeExpr* const index_exprp = methodCallQueueIndexExpr(nodep);
                 if (index_exprp->isZero()) {  // delete(0) is a pop_front
-                    newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                              "pop_front");
+                    newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                              "pop_front"};
                     newp->dtypeFrom(adtypep->subDTypep());
                     newp->dtypeSetVoid();
                 } else {
-                    newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                              "erase", index_exprp->unlinkFrBack());
+                    newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                              "erase", index_exprp->unlinkFrBack()};
                     newp->dtypeSetVoid();
                 }
             }
@@ -3181,12 +3181,12 @@ private:
             AstArg* const argp = VN_AS(nodep->pinsp()->nextp(), Arg);
             iterateCheckTyped(nodep, "insert value", argp->exprp(), adtypep->subDTypep(), BOTH);
             if (index_exprp->isZero()) {  // insert(0, ...) is a push_front
-                newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                          "push_front", argp->exprp()->unlinkFrBack());
+                newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                          "push_front", argp->exprp()->unlinkFrBack()};
                 newp->dtypeSetVoid();
             } else {
-                newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                          nodep->name(), index_exprp->unlinkFrBack());
+                newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                          nodep->name(), index_exprp->unlinkFrBack()};
                 newp->addPinsp(argp->exprp()->unlinkFrBack());
                 newp->dtypeSetVoid();
             }
@@ -3194,8 +3194,8 @@ private:
             methodOkArguments(nodep, 0, 0);
             // Returns element, so method both consumes (reads) and modifies the queue
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READWRITE);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name());
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name()};
             newp->dtypeFrom(adtypep->subDTypep());
             if (nodep->isStandaloneBodyStmt()) newp->dtypeSetVoid();
         } else if (nodep->name() == "push_back" || nodep->name() == "push_front") {
@@ -3203,8 +3203,8 @@ private:
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
             AstArg* const argp = VN_AS(nodep->pinsp(), Arg);
             iterateCheckTyped(nodep, "push value", argp->exprp(), adtypep->subDTypep(), BOTH);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name(), argp->exprp()->unlinkFrBack());
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name(), argp->exprp()->unlinkFrBack()};
             newp->dtypeSetVoid();
         } else if (nodep->name() == "and" || nodep->name() == "or" || nodep->name() == "xor"
                    || nodep->name() == "sum" || nodep->name() == "product") {
@@ -3213,8 +3213,8 @@ private:
                                      nodep->findUInt32DType(), adtypep->subDTypep());
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      "r_" + nodep->name(), withp);
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      "r_" + nodep->name(), withp};
             newp->dtypeFrom(withp ? withp->dtypep() : adtypep->subDTypep());
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "reverse" || nodep->name() == "shuffle"
@@ -3226,15 +3226,15 @@ private:
             }
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::WRITE);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name(), withp);
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name(), withp};
             newp->dtypeSetVoid();
         } else if (nodep->name() == "min" || nodep->name() == "max" || nodep->name() == "unique"
                    || nodep->name() == "unique_index") {
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name());
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name()};
             if (nodep->name() == "unique_index") {
                 newp->dtypep(newp->findQueueIndexDType());
             } else {
@@ -3248,8 +3248,8 @@ private:
                                      nodep->findUInt32DType(), adtypep->subDTypep());
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name(), withp);
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name(), withp};
             newp->dtypeFrom(adtypep);
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else if (nodep->name() == "find_index" || nodep->name() == "find_first_index"
@@ -3259,8 +3259,8 @@ private:
                                      nodep->findUInt32DType(), adtypep->subDTypep());
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
-            newp = new AstCMethodHard(nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name(), withp);
+            newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
+                                      nodep->name(), withp};
             newp->dtypep(newp->findQueueIndexDType());
             if (!nodep->firstAbovep()) newp->dtypeSetVoid();
         } else {
@@ -3298,9 +3298,9 @@ private:
                     if (nodep->pinsp()) argsp = nodep->pinsp()->unlinkFrBackWithNext();
                     AstNodeFTaskRef* newp = nullptr;
                     if (VN_IS(ftaskp, Task)) {
-                        newp = new AstTaskRef(nodep->fileline(), ftaskp->name(), argsp);
+                        newp = new AstTaskRef{nodep->fileline(), ftaskp->name(), argsp};
                     } else {
-                        newp = new AstFuncRef(nodep->fileline(), ftaskp->name(), argsp);
+                        newp = new AstFuncRef{nodep->fileline(), ftaskp->name(), argsp};
                     }
                     newp->taskp(ftaskp);
                     newp->classOrPackagep(classp);
@@ -3362,16 +3362,16 @@ private:
             AstNodeExpr* newp = nullptr;
             for (int i = 0; i < adtypep->elementsConst(); ++i) {
                 AstNodeExpr* const arrayRef = nodep->fromp()->cloneTree(false);
-                AstNodeExpr* const selector = new AstArraySel(fl, arrayRef, i);
+                AstNodeExpr* const selector = new AstArraySel{fl, arrayRef, i};
                 if (!newp) {
                     newp = selector;
                 } else {
                     switch (methodId) {
-                    case ARRAY_OR: newp = new AstOr(fl, newp, selector); break;
-                    case ARRAY_AND: newp = new AstAnd(fl, newp, selector); break;
-                    case ARRAY_XOR: newp = new AstXor(fl, newp, selector); break;
-                    case ARRAY_SUM: newp = new AstAdd(fl, newp, selector); break;
-                    case ARRAY_PRODUCT: newp = new AstMul(fl, newp, selector); break;
+                    case ARRAY_OR: newp = new AstOr{fl, newp, selector}; break;
+                    case ARRAY_AND: newp = new AstAnd{fl, newp, selector}; break;
+                    case ARRAY_XOR: newp = new AstXor{fl, newp, selector}; break;
+                    case ARRAY_SUM: newp = new AstAdd{fl, newp, selector}; break;
+                    case ARRAY_PRODUCT: newp = new AstMul{fl, newp, selector}; break;
                     default: nodep->v3fatalSrc("bad case");
                     }
                 }
@@ -3402,7 +3402,7 @@ private:
         if (nodep->name() == "len") {
             // Constant value
             methodOkArguments(nodep, 0, 0);
-            AstNode* const newp = new AstLenN(nodep->fileline(), nodep->fromp()->unlinkFrBack());
+            AstNode* const newp = new AstLenN{nodep->fileline(), nodep->fromp()->unlinkFrBack()};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (nodep->name() == "itoa") {
@@ -3423,13 +3423,13 @@ private:
         } else if (nodep->name() == "tolower") {
             methodOkArguments(nodep, 0, 0);
             AstNode* const newp
-                = new AstToLowerN(nodep->fileline(), nodep->fromp()->unlinkFrBack());
+                = new AstToLowerN{nodep->fileline(), nodep->fromp()->unlinkFrBack()};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else if (nodep->name() == "toupper") {
             methodOkArguments(nodep, 0, 0);
             AstNode* const newp
-                = new AstToUpperN(nodep->fileline(), nodep->fromp()->unlinkFrBack());
+                = new AstToUpperN{nodep->fileline(), nodep->fromp()->unlinkFrBack()};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else if (nodep->name() == "compare" || nodep->name() == "icompare") {
@@ -3438,7 +3438,7 @@ private:
             AstArg* const argp = VN_AS(nodep->pinsp(), Arg);
             AstNodeExpr* const lhs = nodep->fromp()->unlinkFrBack();
             AstNodeExpr* const rhs = argp->exprp()->unlinkFrBack();
-            AstNode* const newp = new AstCompareNN(nodep->fileline(), lhs, rhs, ignoreCase);
+            AstNode* const newp = new AstCompareNN{nodep->fileline(), lhs, rhs, ignoreCase};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else if (nodep->name() == "putc") {
@@ -3449,9 +3449,9 @@ private:
             AstNodeExpr* const rhsp = arg0p->exprp()->unlinkFrBack();
             AstNodeExpr* const thsp = arg1p->exprp()->unlinkFrBack();
             AstVarRef* const varrefp
-                = new AstVarRef(nodep->fileline(), fromp->varp(), VAccess::READ);
-            AstNode* const newp = new AstAssign(
-                nodep->fileline(), fromp, new AstPutcN(nodep->fileline(), varrefp, rhsp, thsp));
+                = new AstVarRef{nodep->fileline(), fromp->varp(), VAccess::READ};
+            AstNode* const newp = new AstAssign{
+                nodep->fileline(), fromp, new AstPutcN{nodep->fileline(), varrefp, rhsp, thsp}};
             fromp->access(VAccess::WRITE);
             pushDeletep(nodep->backp());
             VL_DO_DANGLING(nodep->backp()->replaceWith(newp), nodep);
@@ -3460,7 +3460,7 @@ private:
             AstArg* const arg0p = VN_AS(nodep->pinsp(), Arg);
             AstNodeExpr* const lhsp = nodep->fromp()->unlinkFrBack();
             AstNodeExpr* const rhsp = arg0p->exprp()->unlinkFrBack();
-            AstNodeExpr* const newp = new AstGetcN(nodep->fileline(), lhsp, rhsp);
+            AstNodeExpr* const newp = new AstGetcN{nodep->fileline(), lhsp, rhsp};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else if (nodep->name() == "substr") {
@@ -3470,7 +3470,7 @@ private:
             AstNodeExpr* const lhsp = nodep->fromp()->unlinkFrBack();
             AstNodeExpr* const rhsp = arg0p->exprp()->unlinkFrBack();
             AstNodeExpr* const thsp = arg1p->exprp()->unlinkFrBack();
-            AstNodeExpr* const newp = new AstSubstrN(nodep->fileline(), lhsp, rhsp, thsp);
+            AstNodeExpr* const newp = new AstSubstrN{nodep->fileline(), lhsp, rhsp, thsp};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else if (nodep->name() == "atobin" || nodep->name() == "atohex"
@@ -3493,7 +3493,7 @@ private:
             }  // dummy assignment to suppress compiler warning
             methodOkArguments(nodep, 0, 0);
             AstNode* const newp
-                = new AstAtoN(nodep->fileline(), nodep->fromp()->unlinkFrBack(), fmt);
+                = new AstAtoN{nodep->fileline(), nodep->fromp()->unlinkFrBack(), fmt};
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else {
@@ -3506,7 +3506,7 @@ private:
         if (AstQueueDType* const queuep = m_queueDTypeIndexed[indexDTypep]) {
             return queuep;
         } else {
-            auto* const newp = new AstQueueDType(indexDTypep->fileline(), indexDTypep, nullptr);
+            auto* const newp = new AstQueueDType{indexDTypep->fileline(), indexDTypep, nullptr};
             v3Global.rootp()->typeTablep()->addTypesp(newp);
             m_queueDTypeIndexed[indexDTypep] = newp;
             return newp;
@@ -3547,7 +3547,7 @@ private:
             return;
         }
         nodep->dtypep(refp);
-        userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+        userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
         if (!similarDTypeRecurse(nodep->dtypep(), nodep->rhsp()->dtypep())) {
             nodep->rhsp()->v3error("New-as-copier passed different data type '"
                                    << nodep->dtypep()->prettyTypeName() << "' then expected '"
@@ -3623,7 +3623,7 @@ private:
                         AstNode* newkeyp = nullptr;
                         if (patp->keyp()) newkeyp = patp->keyp()->cloneTree(true);
                         AstPatMember* const newp
-                            = new AstPatMember(patp->fileline(), movep, newkeyp, nullptr);
+                            = new AstPatMember{patp->fileline(), movep, newkeyp, nullptr};
                         patp->addNext(newp);
                     }
                     relinkHandle.relink(patp);
@@ -3642,7 +3642,7 @@ private:
                 dtypep = vdtypep->subDTypep()->skipRefp();
             }
 
-            userIterate(dtypep, WidthVP(SELF, BOTH).p());
+            userIterate(dtypep, WidthVP{SELF, BOTH}.p());
 
             if (auto* const vdtypep = VN_CAST(dtypep, NodeUOrStructDType)) {
                 VL_DO_DANGLING(patternUOrStruct(nodep, vdtypep, defaultp), nodep);
@@ -3883,7 +3883,7 @@ private:
     void patternAssoc(AstPattern* nodep, AstAssocArrayDType* arrayDtp, AstPatMember* defaultp) {
         AstNode* defaultValuep = nullptr;
         if (defaultp) defaultValuep = defaultp->lhssp()->unlinkFrBack();
-        AstNodeExpr* newp = new AstConsAssoc(nodep->fileline(), defaultValuep);
+        AstNodeExpr* newp = new AstConsAssoc{nodep->fileline(), defaultValuep};
         newp->dtypeFrom(arrayDtp);
         for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
              patp = VN_AS(patp->nextp(), PatMember)) {
@@ -3891,7 +3891,7 @@ private:
             AstNodeExpr* const valuep = patternMemberValueIterate(patp);
             AstNode* const keyp = patp->keyp();
             auto* const newap
-                = new AstSetAssoc(nodep->fileline(), newp, keyp->unlinkFrBack(), valuep);
+                = new AstSetAssoc{nodep->fileline(), newp, keyp->unlinkFrBack(), valuep};
             newap->dtypeFrom(arrayDtp);
             newp = newap;
         }
@@ -3920,13 +3920,13 @@ private:
         VL_DO_DANGLING(pushDeletep(nodep), nodep);  // Deletes defaultp also, if present
     }
     void patternDynArray(AstPattern* nodep, AstDynArrayDType* arrayp, AstPatMember*) {
-        AstNode* newp = new AstConsDynArray(nodep->fileline());
+        AstNode* newp = new AstConsDynArray{nodep->fileline()};
         newp->dtypeFrom(arrayp);
         for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
              patp = VN_AS(patp->nextp(), PatMember)) {
             patp->dtypep(arrayp->subDTypep());
             AstNodeExpr* const valuep = patternMemberValueIterate(patp);
-            auto* const newap = new AstConsDynArray(nodep->fileline(), valuep, newp);
+            auto* const newap = new AstConsDynArray{nodep->fileline(), valuep, newp};
             newap->dtypeFrom(arrayp);
             newp = newap;
         }
@@ -3935,13 +3935,13 @@ private:
         VL_DO_DANGLING(pushDeletep(nodep), nodep);  // Deletes defaultp also, if present
     }
     void patternQueue(AstPattern* nodep, AstQueueDType* arrayp, AstPatMember*) {
-        AstNode* newp = new AstConsQueue(nodep->fileline());
+        AstNode* newp = new AstConsQueue{nodep->fileline()};
         newp->dtypeFrom(arrayp);
         for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
              patp = VN_AS(patp->nextp(), PatMember)) {
             patp->dtypep(arrayp->subDTypep());
             AstNodeExpr* const valuep = patternMemberValueIterate(patp);
-            auto* const newap = new AstConsQueue(nodep->fileline(), valuep, newp);
+            auto* const newap = new AstConsQueue{nodep->fileline(), valuep, newp};
             newap->dtypeFrom(arrayp);
             newp = newap;
         }
@@ -3979,7 +3979,7 @@ private:
                     if (!newp) {
                         newp = valuep;
                     } else {
-                        AstConcat* const concatp = new AstConcat(patp->fileline(), newp, valuep);
+                        AstConcat* const concatp = new AstConcat{patp->fileline(), newp, valuep};
                         newp = concatp;
                         newp->dtypeSetLogicSized(concatp->lhsp()->width()
                                                      + concatp->rhsp()->width(),
@@ -4023,7 +4023,7 @@ private:
         UASSERT_OBJ(!nodep->lhssp()->nextp(), nodep,
                     "PatMember value should be singular w/replicates removed");
         // Need to propagate assignment type downwards, even on prelim
-        userIterateChildren(nodep, WidthVP(nodep->dtypep(), PRELIM).p());
+        userIterateChildren(nodep, WidthVP{nodep->dtypep(), PRELIM}.p());
         iterateCheck(nodep, "Pattern value", nodep->lhssp(), ASSIGN, FINAL, vdtypep, EXTEND_LHS);
     }
     int visitPatMemberRep(AstPatMember* nodep) {
@@ -4069,13 +4069,13 @@ private:
         //    Width: MAX(expr, all items)
         //    Signed: Only if expr, and all items signed
         assertAtStatement(nodep);
-        userIterateAndNext(nodep->exprp(), WidthVP(CONTEXT_DET, PRELIM).p());
+        userIterateAndNext(nodep->exprp(), WidthVP{CONTEXT_DET, PRELIM}.p());
         for (AstCaseItem *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) {
             nextip = VN_AS(itemp->nextp(), CaseItem);  // Prelim may cause the node to get replaced
             if (!VN_IS(nodep, GenCase)) userIterateAndNext(itemp->stmtsp(), nullptr);
             for (AstNode *nextcp, *condp = itemp->condsp(); condp; condp = nextcp) {
                 nextcp = condp->nextp();  // Prelim may cause the node to get replaced
-                VL_DO_DANGLING(userIterate(condp, WidthVP(CONTEXT_DET, PRELIM).p()), condp);
+                VL_DO_DANGLING(userIterate(condp, WidthVP{CONTEXT_DET, PRELIM}.p()), condp);
             }
         }
 
@@ -4138,7 +4138,7 @@ private:
     }
     void visit(AstRepeat* nodep) override {
         assertAtStatement(nodep);
-        userIterateAndNext(nodep->countp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->countp(), WidthVP{SELF, BOTH}.p());
         userIterateAndNext(nodep->stmtsp(), nullptr);
     }
     void visit(AstWhile* nodep) override {
@@ -4169,7 +4169,7 @@ private:
         const AstSelLoopVars* const loopsp = VN_CAST(nodep->arrayp(), SelLoopVars);
         UASSERT_OBJ(loopsp, nodep, "No loop variables under foreach");
         // if (debug()) nodep->dumpTree(cout, "-foreach-old: ");
-        userIterateAndNext(loopsp->fromp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(loopsp->fromp(), WidthVP{SELF, BOTH}.p());
         AstNodeExpr* const fromp = loopsp->fromp();
         UASSERT_OBJ(fromp->dtypep(), fromp, "Missing data type");
         AstNodeDType* fromDtp = fromp->dtypep()->skipRefp();
@@ -4353,13 +4353,13 @@ private:
         // if (debug()) nodep->dumpTree(cout, "  AssignPre: ");
         {
             // if (debug()) nodep->dumpTree(cout, "-    assin:  ");
-            userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
             UASSERT_OBJ(nodep->lhsp()->dtypep(), nodep, "How can LHS be untyped?");
             UASSERT_OBJ(nodep->lhsp()->dtypep()->widthSized(), nodep, "How can LHS be unsized?");
             nodep->dtypeFrom(nodep->lhsp());
             //
             // AstPattern needs to know the proposed data type of the lhs, so pass on the prelim
-            userIterateAndNext(nodep->rhsp(), WidthVP(nodep->dtypep(), PRELIM).p());
+            userIterateAndNext(nodep->rhsp(), WidthVP{nodep->dtypep(), PRELIM}.p());
             //
             // if (debug()) nodep->dumpTree(cout, "-    assign: ");
             AstNodeDType* const lhsDTypep
@@ -4415,11 +4415,11 @@ private:
             UINFO(9, "= new[] -> .resize(): " << nodep);
             AstCMethodHard* newp;
             if (!dynp->rhsp()) {
-                newp = new AstCMethodHard(nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
-                                          "renew", dynp->sizep()->unlinkFrBack());
+                newp = new AstCMethodHard{nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
+                                          "renew", dynp->sizep()->unlinkFrBack()};
             } else {
-                newp = new AstCMethodHard(nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
-                                          "renew_copy", dynp->sizep()->unlinkFrBack());
+                newp = new AstCMethodHard{nodep->fileline(), nodep->lhsp()->unlinkFrBack(),
+                                          "renew_copy", dynp->sizep()->unlinkFrBack()};
                 newp->addPinsp(dynp->rhsp()->unlinkFrBack());
             }
             newp->didWidth(true);
@@ -4432,7 +4432,7 @@ private:
     }
 
     void visit(AstRelease* nodep) override {
-        userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
         UASSERT_OBJ(nodep->lhsp()->dtypep(), nodep, "How can LValue be untyped?");
         UASSERT_OBJ(nodep->lhsp()->dtypep()->widthSized(), nodep, "How can LValue be unsized?");
     }
@@ -4441,7 +4441,7 @@ private:
         // Excludes NodeDisplay, see below
         if (m_vup && !m_vup->prelim()) return;  // Can be called as statement or function
         // Just let all arguments seek their natural sizes
-        userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+        userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
         //
         UINFO(9, "  Display in " << nodep->text() << endl);
         string newFormat;
@@ -4578,12 +4578,12 @@ private:
         assertAtStatement(nodep);
         if (nodep->filep()) iterateCheckFileDesc(nodep, nodep->filep(), BOTH);
         // Just let all arguments seek their natural sizes
-        userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+        userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
     }
     void visit(AstElabDisplay* nodep) override {
         assertAtStatement(nodep);
         // Just let all arguments seek their natural sizes
-        userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+        userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
         if (!m_paramsOnly) {
             V3Const::constifyParamsEdit(nodep->fmtp());  // fmtp may change
             string text = nodep->fmtp()->text();
@@ -4601,19 +4601,19 @@ private:
     void visit(AstDumpCtl* nodep) override {
         assertAtStatement(nodep);
         // Just let all arguments seek their natural sizes
-        userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+        userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
     }
     void visit(AstFOpen* nodep) override {
         // Although a system function in IEEE, here a statement which sets the file pointer (MCD)
         assertAtStatement(nodep);
         iterateCheckFileDesc(nodep, nodep->filep(), BOTH);
-        userIterateAndNext(nodep->filenamep(), WidthVP(SELF, BOTH).p());
-        userIterateAndNext(nodep->modep(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->filenamep(), WidthVP{SELF, BOTH}.p());
+        userIterateAndNext(nodep->modep(), WidthVP{SELF, BOTH}.p());
     }
     void visit(AstFOpenMcd* nodep) override {
         assertAtStatement(nodep);
         iterateCheckFileDesc(nodep, nodep->filep(), BOTH);
-        userIterateAndNext(nodep->filenamep(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->filenamep(), WidthVP{SELF, BOTH}.p());
     }
     void visit(AstFClose* nodep) override {
         assertAtStatement(nodep);
@@ -4661,7 +4661,7 @@ private:
         if (m_vup->prelim()) {
             nodep->dtypeSetSigned32();  // Spec says integer return
             iterateCheckFileDesc(nodep, nodep->filep(), BOTH);
-            userIterateAndNext(nodep->strgp(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->strgp(), WidthVP{SELF, BOTH}.p());
         }
     }
     void visit(AstFUngetC* nodep) override {
@@ -4674,7 +4674,7 @@ private:
     void visit(AstFRead* nodep) override {
         if (m_vup->prelim()) {
             nodep->dtypeSetSigned32();  // Spec says integer return
-            userIterateAndNext(nodep->memp(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->memp(), WidthVP{SELF, BOTH}.p());
             iterateCheckFileDesc(nodep, nodep->filep(), BOTH);
             if (nodep->startp()) {
                 iterateCheckSigned32(nodep, "$fread start", nodep->startp(), BOTH);
@@ -4688,38 +4688,38 @@ private:
         if (m_vup->prelim()) {
             nodep->dtypeSetSigned32();  // Spec says integer return
             iterateCheckFileDesc(nodep, nodep->filep(), BOTH);
-            userIterateAndNext(nodep->exprsp(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->exprsp(), WidthVP{SELF, BOTH}.p());
         }
     }
     void visit(AstSScanF* nodep) override {
         if (m_vup->prelim()) {
             nodep->dtypeSetSigned32();  // Spec says integer return
-            userIterateAndNext(nodep->fromp(), WidthVP(SELF, BOTH).p());
-            userIterateAndNext(nodep->exprsp(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->fromp(), WidthVP{SELF, BOTH}.p());
+            userIterateAndNext(nodep->exprsp(), WidthVP{SELF, BOTH}.p());
         }
     }
     void visit(AstStackTraceF* nodep) override { nodep->dtypeSetString(); }
     void visit(AstSysIgnore* nodep) override {
-        userIterateAndNext(nodep->exprsp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->exprsp(), WidthVP{SELF, BOTH}.p());
     }
     void visit(AstSystemF* nodep) override {
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
             nodep->dtypeSetSigned32();  // Spec says integer return
         }
     }
     void visit(AstSysFuncAsTask* nodep) override {
         assertAtStatement(nodep);
-        userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
     }
     void visit(AstSystemT* nodep) override {
         assertAtStatement(nodep);
-        userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
     }
     void visit(AstNodeReadWriteMem* nodep) override {
         assertAtStatement(nodep);
-        userIterateAndNext(nodep->filenamep(), WidthVP(SELF, BOTH).p());
-        userIterateAndNext(nodep->memp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->filenamep(), WidthVP{SELF, BOTH}.p());
+        userIterateAndNext(nodep->memp(), WidthVP{SELF, BOTH}.p());
         const AstNodeDType* subp = nullptr;
         if (const AstAssocArrayDType* adtypep
             = VN_CAST(nodep->memp()->dtypep()->skipRefp(), AssocArrayDType)) {
@@ -4745,8 +4745,8 @@ private:
                                   "Unsupported: " << nodep->verilogKwd()
                                                   << " array values must be integral");
         }
-        userIterateAndNext(nodep->lsbp(), WidthVP(SELF, BOTH).p());
-        userIterateAndNext(nodep->msbp(), WidthVP(SELF, BOTH).p());
+        userIterateAndNext(nodep->lsbp(), WidthVP{SELF, BOTH}.p());
+        userIterateAndNext(nodep->msbp(), WidthVP{SELF, BOTH}.p());
     }
     void visit(AstTestPlusArgs* nodep) override {
         if (m_vup->prelim()) {
@@ -4756,8 +4756,8 @@ private:
     }
     void visit(AstValuePlusArgs* nodep) override {
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->searchp(), WidthVP(SELF, BOTH).p());
-            userIterateAndNext(nodep->outp(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->searchp(), WidthVP{SELF, BOTH}.p());
+            userIterateAndNext(nodep->outp(), WidthVP{SELF, BOTH}.p());
             nodep->dtypeChgWidthSigned(32, 1, VSigning::SIGNED);  // Spec says integer return
         }
     }
@@ -4771,7 +4771,7 @@ private:
     void visit(AstUCStmt* nodep) override {
         // Just let all arguments seek their natural sizes
         assertAtStatement(nodep);
-        userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+        userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
     }
     void visit(AstAssert* nodep) override {
         assertAtStatement(nodep);
@@ -4811,7 +4811,7 @@ private:
                     didWidth = true;
                 }
             }
-            if (!didWidth) userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+            if (!didWidth) userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
         } else if (!m_paramsOnly) {
             if (!nodep->modVarp()->didWidth()) {
                 // Var hasn't been widthed, so make it so.
@@ -4938,15 +4938,15 @@ private:
                                                   << nodep->modName() << "'");
                 v3Global.opt.filePathLookedMsg(nodep->modNameFileline(), nodep->modName());
             }
-            if (nodep->rangep()) userIterateAndNext(nodep->rangep(), WidthVP(SELF, BOTH).p());
+            if (nodep->rangep()) userIterateAndNext(nodep->rangep(), WidthVP{SELF, BOTH}.p());
             userIterateAndNext(nodep->pinsp(), nullptr);
         }
         userIterateAndNext(nodep->paramsp(), nullptr);
     }
     void visit(AstGatePin* nodep) override {
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->rangep(), WidthVP(SELF, BOTH).p());
-            userIterateAndNext(nodep->exprp(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->rangep(), WidthVP{SELF, BOTH}.p());
+            userIterateAndNext(nodep->exprp(), WidthVP{CONTEXT_DET, PRELIM}.p());
             nodep->dtypeFrom(nodep->rangep());
             // Very much like like an pin
             const AstNodeDType* const conDTypep = nodep->exprp()->dtypep();
@@ -5002,7 +5002,7 @@ private:
             nodep->dtypeSetBit();
         }
         WidthVP* vup = nullptr;
-        if (VN_IS(nodep, Property)) vup = WidthVP(SELF, BOTH).p();
+        if (VN_IS(nodep, Property)) vup = WidthVP{SELF, BOTH}.p();
         userIterateChildren(nodep, vup);
 
         nodep->didWidth(true);
@@ -5054,7 +5054,7 @@ private:
                 // Function hasn't been widthed, so make it so.
                 nodep->dtypeFrom(m_funcp->fvarp());
                 // AstPattern requires assignments to pass datatype on PRELIM
-                userIterateAndNext(nodep->lhsp(), WidthVP(nodep->dtypep(), PRELIM).p());
+                userIterateAndNext(nodep->lhsp(), WidthVP{nodep->dtypep(), PRELIM}.p());
                 iterateCheckAssign(nodep, "Return value", nodep->lhsp(), FINAL, nodep->dtypep());
             }
         }
@@ -5144,11 +5144,11 @@ private:
                     }
                     VL_DO_DANGLING(pushDeletep(argp), argp);
                     AstSFormatF* const newp
-                        = new AstSFormatF(nodep->fileline(), format, false, argsp);
+                        = new AstSFormatF{nodep->fileline(), format, false, argsp};
                     if (!newp->scopeNamep() && newp->formatScopeTracking()) {
                         newp->scopeNamep(new AstScopeName{newp->fileline(), true});
                     }
-                    handle.relink(new AstArg(newp->fileline(), "", newp));
+                    handle.relink(new AstArg{newp->fileline(), "", newp});
                     // Connection list is now incorrect (has extra args in it).
                     goto reloop;  // so exit early; next loop will correct it
                 }  //
@@ -5162,7 +5162,7 @@ private:
                     UINFO(4, "   Add CvtPackString: " << pinp << endl);
                     VNRelinker handle;
                     pinp->unlinkFrBack(&handle);  // No next, that's the next pin
-                    AstNodeExpr* const newp = new AstCvtPackString(pinp->fileline(), pinp);
+                    AstNodeExpr* const newp = new AstCvtPackString{pinp->fileline(), pinp};
                     handle.relink(newp);
                     pinp = newp;
                 }
@@ -5262,7 +5262,7 @@ private:
             nodep->replaceWith(new AstSenItem{rhsp->fileline(), nodep->edgeType(), rhsp});
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
         } else {
-            userIterateChildren(nodep, WidthVP(SELF, BOTH).p());
+            userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
             if (nodep->edgeType().anEdge() && nodep->sensp()->dtypep()->skipRefp()->isDouble()) {
                 nodep->sensp()->v3error(
                     "Edge event control not legal on real type (IEEE 1800-2017 6.12.1)");
@@ -5278,7 +5278,7 @@ private:
         }
         if (nodep->fileline()->timingOn()) {
             if (v3Global.opt.timing().isSetTrue()) {
-                userIterate(nodep->condp(), WidthVP(SELF, PRELIM).p());
+                userIterate(nodep->condp(), WidthVP{SELF, PRELIM}.p());
                 iterateNull(nodep->stmtsp());
                 return;
             } else if (v3Global.opt.timing().isSetFalse()) {
@@ -5307,9 +5307,9 @@ private:
             userIterateChildren(nodep->indexArgRefp(), nullptr);
             userIterateChildren(nodep->valueArgRefp(), nullptr);
             if (vdtypep) {
-                userIterateAndNext(nodep->exprp(), WidthVP(nodep->dtypep(), PRELIM).p());
+                userIterateAndNext(nodep->exprp(), WidthVP{nodep->dtypep(), PRELIM}.p());
             } else {  // 'sort with' allows arbitrary type
-                userIterateAndNext(nodep->exprp(), WidthVP(SELF, PRELIM).p());
+                userIterateAndNext(nodep->exprp(), WidthVP{SELF, PRELIM}.p());
             }
             nodep->dtypeFrom(nodep->exprp());
             iterateCheckAssign(nodep, "'with' return value", nodep->exprp(), FINAL,
@@ -5356,7 +5356,7 @@ private:
             nodep->dtypeSetDouble();
             AstNodeDType* const subDTypep = nodep->findLogicDType(64, 64, VSigning::UNSIGNED);
             // Self-determined operand
-            userIterateAndNext(nodep->lhsp(), WidthVP(SELF, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{SELF, PRELIM}.p());
             iterateCheck(nodep, "LHS", nodep->lhsp(), SELF, FINAL, subDTypep, EXTEND_EXP);
         }
     }
@@ -5366,10 +5366,10 @@ private:
         if (m_vup->prelim()) {  // First stage evaluation
             nodep->dtypeSetDouble();
             // Self-determined operand (TODO check if numeric type)
-            userIterateAndNext(nodep->lhsp(), WidthVP(SELF, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{SELF, PRELIM}.p());
             if (nodep->lhsp()->isSigned()) {
                 nodep->replaceWith(
-                    new AstISToRD(nodep->fileline(), nodep->lhsp()->unlinkFrBack()));
+                    new AstISToRD{nodep->fileline(), nodep->lhsp()->unlinkFrBack()});
                 VL_DO_DANGLING(nodep->deleteTree(), nodep);
             }
         }
@@ -5380,7 +5380,7 @@ private:
         if (m_vup->prelim()) {  // First stage evaluation
             nodep->dtypeSetDouble();
             // Self-determined operand (TODO check if numeric type)
-            userIterateAndNext(nodep->lhsp(), WidthVP(SELF, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{SELF, PRELIM}.p());
         }
     }
     void visit_Os32_Lr(AstNodeUniop* nodep) {
@@ -5451,7 +5451,7 @@ private:
         //   Width: 1 bit out
         //   Sign: unsigned out (11.8.1)
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(SELF, BOTH).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
             nodep->dtypeSetBit();
         }
     }
@@ -5470,8 +5470,8 @@ private:
         //   TODO: chandle/class handle/iface handle no relational compares
         UASSERT_OBJ(nodep->rhsp(), nodep, "For binary ops only!");
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
-            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());
+            userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());
             if (nodep->lhsp()->isDouble() || nodep->rhsp()->isDouble()) {
                 if (!realok) {
                     nodep->v3error("Real is illegal operand to ?== operator");
@@ -5572,7 +5572,7 @@ private:
         //    Widths: out width = lhs width
         UASSERT_OBJ(!nodep->op2p(), nodep, "For unary ops only!");
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());
             if (!real_ok) checkCvtUS(nodep->lhsp());
         }
         if (real_ok && nodep->lhsp()->isDouble()) {
@@ -5613,7 +5613,7 @@ private:
         //   TODO: Type: Two-state if input is two-state, else four-state
         UASSERT_OBJ(!nodep->op2p(), nodep, "For unary ops only!");
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(SELF, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{SELF, PRELIM}.p());
             checkCvtUS(nodep->lhsp());
             const int width = nodep->lhsp()->width();
             AstNodeDType* const expDTypep = nodep->findLogicDType(width, width, rs_out);
@@ -5641,7 +5641,7 @@ private:
         // See IEEE-2012 11.4.10 and Table 11-21.
         //   RHS is self-determined. RHS is always treated as unsigned, has no effect on result.
         if (m_vup->prelim()) {
-            userIterateAndNext(nodep->lhsp(), WidthVP(SELF, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{SELF, PRELIM}.p());
             checkCvtUS(nodep->lhsp());
             iterateCheckSizedSelf(nodep, "RHS", nodep->rhsp(), SELF, BOTH);
             nodep->dtypeFrom(nodep->lhsp());
@@ -5672,7 +5672,7 @@ private:
                     V3Number num(shiftp, 32, 0);
                     num.opAssign(shiftp->num());
                     AstNode* const shiftrhsp = nodep->rhsp();
-                    nodep->rhsp()->replaceWith(new AstConst(shiftrhsp->fileline(), num));
+                    nodep->rhsp()->replaceWith(new AstConst{shiftrhsp->fileline(), num});
                     VL_DO_DANGLING(shiftrhsp->deleteTree(), shiftrhsp);
                 }
             }
@@ -5692,8 +5692,8 @@ private:
         // to be the same for our operations.
         if (m_vup->prelim()) {  // First stage evaluation
             // Determine expression widths only relying on what's in the subops
-            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
-            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());
+            userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());
             checkCvtUS(nodep->lhsp());
             checkCvtUS(nodep->rhsp());
             const int width = std::max(nodep->lhsp()->width(), nodep->rhsp()->width());
@@ -5726,8 +5726,8 @@ private:
         // if (debug() >= 9) { UINFO(0,"-rus "<<m_vup<<endl); nodep->dumpTree(cout, "-rusin-"); }
         if (m_vup->prelim()) {  // First stage evaluation
             // Determine expression widths only relying on what's in the subops
-            userIterateAndNext(nodep->lhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
-            userIterateAndNext(nodep->rhsp(), WidthVP(CONTEXT_DET, PRELIM).p());
+            userIterateAndNext(nodep->lhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());
+            userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());
             if (!real_ok) {
                 checkCvtUS(nodep->lhsp());
                 checkCvtUS(nodep->rhsp());
@@ -5843,7 +5843,7 @@ private:
             V3Number num(nodep, expWidth);
             num.opAssign(constp->num());
             num.isSigned(false);
-            AstNodeExpr* const newp = new AstConst(nodep->fileline(), num);
+            AstNodeExpr* const newp = new AstConst{nodep->fileline(), num};
             constp->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(constp), constp);
             VL_DANGLING(nodep);
@@ -5852,7 +5852,7 @@ private:
             // Trunc - Extract
             VNRelinker linker;
             nodep->unlinkFrBack(&linker);
-            AstNodeExpr* const newp = new AstSel(nodep->fileline(), nodep, 0, expWidth);
+            AstNodeExpr* const newp = new AstSel{nodep->fileline(), nodep, 0, expWidth};
             newp->didWidth(true);  // Don't replace dtype with unsigned
             linker.relink(newp);
             nodep = newp;
@@ -5897,7 +5897,7 @@ private:
             V3Number num(nodep, expWidth);
             num.opRedOr(constp->num());
             num.isSigned(expSigned);
-            AstNodeExpr* const newp = new AstConst(nodep->fileline(), num);
+            AstNodeExpr* const newp = new AstConst{nodep->fileline(), num};
             constp->replaceWith(newp);
             VL_DO_DANGLING(constp->deleteTree(), constp);
             VL_DANGLING(nodep);
@@ -5905,7 +5905,7 @@ private:
         } else {
             VNRelinker linker;
             nodep->unlinkFrBack(&linker);
-            AstNodeExpr* const newp = new AstRedOr(nodep->fileline(), nodep);
+            AstNodeExpr* const newp = new AstRedOr{nodep->fileline(), nodep};
             linker.relink(newp);
             nodep = newp;
         }
@@ -5920,7 +5920,7 @@ private:
                 // Make it the proper size.  Careful of proper extension of 0's/1's
                 V3Number num(constp, expWidth);
                 num.opRepl(constp->num(), expWidth);  // {width{'1}}
-                AstNodeExpr* const newp = new AstConst(constp->fileline(), num);
+                AstNodeExpr* const newp = new AstConst{constp->fileline(), num};
                 // Spec says always unsigned with proper width
                 if (debug() > 4) constp->dumpTree(cout, "  fixAutoExtend_old: ");
                 if (debug() > 4) newp->dumpTree(cout, "               _new: ");
@@ -5938,7 +5938,7 @@ private:
                                           << expWidth << " bits: " << constp->prettyName());
                 V3Number num(constp, expWidth);
                 num.opExtendXZ(constp->num(), constp->width());
-                AstNodeExpr* const newp = new AstConst(constp->fileline(), num);
+                AstNodeExpr* const newp = new AstConst{constp->fileline(), num};
                 // Spec says always unsigned with proper width
                 if (debug() > 4) constp->dumpTree(cout, "  fixUnszExtend_old: ");
                 if (debug() > 4) newp->dumpTree(cout, "               _new: ");
@@ -5967,7 +5967,7 @@ private:
     void iterateCheckFileDesc(AstNode* nodep, AstNode* underp, Stage stage) {
         UASSERT_OBJ(stage == BOTH, nodep, "Bad call");
         // underp may change as a result of replacement
-        underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, PRELIM).p());
+        underp = userIterateSubtreeReturnEdits(underp, WidthVP{SELF, PRELIM}.p());
         AstNodeDType* const expDTypep = underp->findUInt32DType();
         underp
             = iterateCheck(nodep, "file_descriptor", underp, SELF, FINAL, expDTypep, EXTEND_EXP);
@@ -5977,7 +5977,7 @@ private:
         // Coerce child to signed32 if not already. Child is self-determined
         // underp may change as a result of replacement
         if (stage & PRELIM) {
-            underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, PRELIM).p());
+            underp = userIterateSubtreeReturnEdits(underp, WidthVP{SELF, PRELIM}.p());
         }
         if (stage & FINAL) {
             AstNodeDType* const expDTypep = nodep->findSigned32DType();
@@ -5993,7 +5993,7 @@ private:
         // otherwise self-determined was correct
         // underp may change as a result of replacement
         if (stage & PRELIM) {
-            underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, PRELIM).p());
+            underp = userIterateSubtreeReturnEdits(underp, WidthVP{SELF, PRELIM}.p());
         }
         if (stage & FINAL) {
             AstNodeDType* const expDTypep = nodep->findDoubleDType();
@@ -6003,7 +6003,7 @@ private:
     }
     void iterateCheckString(AstNode* nodep, const char* side, AstNode* underp, Stage stage) {
         if (stage & PRELIM) {
-            underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, PRELIM).p());
+            underp = userIterateSubtreeReturnEdits(underp, WidthVP{SELF, PRELIM}.p());
         }
         if (stage & FINAL) {
             AstNodeDType* const expDTypep = nodep->findStringDType();
@@ -6014,7 +6014,7 @@ private:
     void iterateCheckTyped(AstNode* nodep, const char* side, AstNode* underp,
                            AstNodeDType* expDTypep, Stage stage) {
         if (stage & PRELIM) {
-            underp = userIterateSubtreeReturnEdits(underp, WidthVP(expDTypep, PRELIM).p());
+            underp = userIterateSubtreeReturnEdits(underp, WidthVP{expDTypep, PRELIM}.p());
         }
         if (stage & FINAL) {
             underp = iterateCheck(nodep, side, underp, SELF, FINAL, expDTypep, EXTEND_EXP);
@@ -6030,7 +6030,7 @@ private:
         UASSERT_OBJ(stage == FINAL || stage == BOTH, nodep, "Bad call");
         // underp may change as a result of replacement
         if (stage & PRELIM) {
-            underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, PRELIM).p());
+            underp = userIterateSubtreeReturnEdits(underp, WidthVP{SELF, PRELIM}.p());
         }
         underp = VN_IS(underp, NodeExpr) ? checkCvtUS(VN_AS(underp, NodeExpr)) : underp;
         AstNodeDType* const expDTypep = underp->dtypep();
@@ -6060,7 +6060,7 @@ private:
         // stage is always BOTH so not passed as argument
         // underp may change as a result of replacement
         UASSERT_OBJ(underp, nodep, "Node has no type");
-        underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, BOTH).p());
+        underp = userIterateSubtreeReturnEdits(underp, WidthVP{SELF, BOTH}.p());
         UASSERT_OBJ(underp && underp->dtypep(), nodep,
                     "Node has no type");  // Perhaps forgot to do a prelim visit on it?
         //
@@ -6071,8 +6071,8 @@ private:
             VNRelinker linker;
             underp->unlinkFrBack(&linker);
             AstNode* const newp
-                = new AstNeqD(nodep->fileline(), VN_AS(underp, NodeExpr),
-                              new AstConst(nodep->fileline(), AstConst::RealDouble(), 0.0));
+                = new AstNeqD{nodep->fileline(), VN_AS(underp, NodeExpr),
+                              new AstConst{nodep->fileline(), AstConst::RealDouble{}, 0.0}};
             linker.relink(newp);
         } else if (VN_IS(underVDTypep, ClassRefDType)
                    || (VN_IS(underVDTypep, BasicDType)
@@ -6083,7 +6083,7 @@ private:
             nodep->v3error("Logical operator " << nodep->prettyTypeName()
                                                << " expects a non-complex data type on the "
                                                << side << ".");
-            underp->replaceWith(new AstConst(nodep->fileline(), AstConst::BitFalse()));
+            underp->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}});
             VL_DO_DANGLING(pushDeletep(underp), underp);
         } else {
             const bool bad = widthBad(underp, nodep->findBitDType());
@@ -6120,24 +6120,24 @@ private:
                             << " expected non-datatype " << side << " but '" << underp->name()
                             << "' is a datatype.");
         } else if (expDTypep == underp->dtypep()) {  // Perfect
-            underp = userIterateSubtreeReturnEdits(underp, WidthVP(expDTypep, FINAL).p());
+            underp = userIterateSubtreeReturnEdits(underp, WidthVP{expDTypep, FINAL}.p());
         } else if (expDTypep->isDouble() && underp->isDouble()) {  // Also good
-            underp = userIterateSubtreeReturnEdits(underp, WidthVP(expDTypep, FINAL).p());
+            underp = userIterateSubtreeReturnEdits(underp, WidthVP{expDTypep, FINAL}.p());
         } else if (expDTypep->isDouble() && !underp->isDouble()) {
             AstNode* const oldp
                 = underp;  // Need FINAL on children; otherwise splice would block it
             underp = spliceCvtD(VN_AS(underp, NodeExpr));
-            underp = userIterateSubtreeReturnEdits(oldp, WidthVP(SELF, FINAL).p());
+            underp = userIterateSubtreeReturnEdits(oldp, WidthVP{SELF, FINAL}.p());
         } else if (!expDTypep->isDouble() && underp->isDouble()) {
             AstNode* const oldp
                 = underp;  // Need FINAL on children; otherwise splice would block it
             underp = spliceCvtS(VN_AS(underp, NodeExpr), true, expDTypep->width());  // Round RHS
-            underp = userIterateSubtreeReturnEdits(oldp, WidthVP(SELF, FINAL).p());
+            underp = userIterateSubtreeReturnEdits(oldp, WidthVP{SELF, FINAL}.p());
         } else if (expDTypep->isString() && !underp->dtypep()->isString()) {
             AstNode* const oldp
                 = underp;  // Need FINAL on children; otherwise splice would block it
             underp = spliceCvtString(VN_AS(underp, NodeExpr));
-            underp = userIterateSubtreeReturnEdits(oldp, WidthVP(SELF, FINAL).p());
+            underp = userIterateSubtreeReturnEdits(oldp, WidthVP{SELF, FINAL}.p());
         } else {
             const AstBasicDType* const expBasicp = expDTypep->basicp();
             const AstBasicDType* const underBasicp = underp->dtypep()->basicp();
@@ -6162,7 +6162,7 @@ private:
                 // is e.g. an ADD, the ADD will auto-adjust to the proper data type
                 // or if another operation e.g. ATOI will not.
                 if (determ == SELF) {
-                    underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, FINAL).p());
+                    underp = userIterateSubtreeReturnEdits(underp, WidthVP{SELF, FINAL}.p());
                 } else if (determ == ASSIGN) {
                     // IEEE: Signedness is solely determined by the RHS
                     // (underp), not by the LHS (expDTypep)
@@ -6174,9 +6174,9 @@ private:
                             VSigning::fromBool(underp->isSigned()));
                         UINFO(9, "Assignment of opposite-signed RHS to LHS: " << nodep << endl);
                     }
-                    underp = userIterateSubtreeReturnEdits(underp, WidthVP(subDTypep, FINAL).p());
+                    underp = userIterateSubtreeReturnEdits(underp, WidthVP{subDTypep, FINAL}.p());
                 } else {
-                    underp = userIterateSubtreeReturnEdits(underp, WidthVP(subDTypep, FINAL).p());
+                    underp = userIterateSubtreeReturnEdits(underp, WidthVP{subDTypep, FINAL}.p());
                 }
                 // Note the check uses the expected size, not the child's subDTypep as we want the
                 // child node's width to end up correct for the assignment (etc)
@@ -6216,7 +6216,7 @@ private:
                 }
             } else {
                 // Hope it just works out (perhaps a cast will deal with it)
-                underp = userIterateSubtreeReturnEdits(underp, WidthVP(expDTypep, FINAL).p());
+                underp = userIterateSubtreeReturnEdits(underp, WidthVP{expDTypep, FINAL}.p());
             }
         }
         return underp;
@@ -6321,9 +6321,9 @@ private:
             nodep->unlinkFrBack(&linker);
             AstNodeExpr* newp;
             if (nodep->dtypep()->skipRefp()->isSigned()) {
-                newp = new AstISToRD(nodep->fileline(), nodep);
+                newp = new AstISToRD{nodep->fileline(), nodep};
             } else {
-                newp = new AstIToRD(nodep->fileline(), nodep);
+                newp = new AstIToRD{nodep->fileline(), nodep};
             }
             linker.relink(newp);
             return newp;
@@ -6349,7 +6349,7 @@ private:
                 }
             }
             if (warnOn) nodep->v3warn(REALCVT, "Implicit conversion of real to integer");
-            AstNodeExpr* const newp = new AstRToIRoundS(nodep->fileline(), nodep);
+            AstNodeExpr* const newp = new AstRToIRoundS{nodep->fileline(), nodep};
             linker.relink(newp);
             newp->dtypeSetBitSized(width, VSigning::SIGNED);
             return newp;
@@ -6364,7 +6364,7 @@ private:
             UINFO(6, "   spliceCvtString: " << nodep << endl);
             VNRelinker linker;
             nodep->unlinkFrBack(&linker);
-            AstNodeExpr* const newp = new AstCvtPackString(nodep->fileline(), nodep);
+            AstNodeExpr* const newp = new AstCvtPackString{nodep->fileline(), nodep};
             linker.relink(newp);
             return newp;
         } else {
@@ -6394,22 +6394,22 @@ private:
         AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
         AstNodeBiop* newp = nullptr;
         switch (nodep->type()) {
-        case VNType::atGt: newp = new AstGtS(fl, lhsp, rhsp); break;
-        case VNType::atGtS: newp = new AstGt(fl, lhsp, rhsp); break;
-        case VNType::atGte: newp = new AstGteS(fl, lhsp, rhsp); break;
-        case VNType::atGteS: newp = new AstGte(fl, lhsp, rhsp); break;
-        case VNType::atLt: newp = new AstLtS(fl, lhsp, rhsp); break;
-        case VNType::atLtS: newp = new AstLt(fl, lhsp, rhsp); break;
-        case VNType::atLte: newp = new AstLteS(fl, lhsp, rhsp); break;
-        case VNType::atLteS: newp = new AstLte(fl, lhsp, rhsp); break;
-        case VNType::atDiv: newp = new AstDivS(fl, lhsp, rhsp); break;
-        case VNType::atDivS: newp = new AstDiv(fl, lhsp, rhsp); break;
-        case VNType::atModDiv: newp = new AstModDivS(fl, lhsp, rhsp); break;
-        case VNType::atModDivS: newp = new AstModDiv(fl, lhsp, rhsp); break;
-        case VNType::atMul: newp = new AstMulS(fl, lhsp, rhsp); break;
-        case VNType::atMulS: newp = new AstMul(fl, lhsp, rhsp); break;
-        case VNType::atShiftR: newp = new AstShiftRS(fl, lhsp, rhsp); break;
-        case VNType::atShiftRS: newp = new AstShiftR(fl, lhsp, rhsp); break;
+        case VNType::atGt: newp = new AstGtS{fl, lhsp, rhsp}; break;
+        case VNType::atGtS: newp = new AstGt{fl, lhsp, rhsp}; break;
+        case VNType::atGte: newp = new AstGteS{fl, lhsp, rhsp}; break;
+        case VNType::atGteS: newp = new AstGte{fl, lhsp, rhsp}; break;
+        case VNType::atLt: newp = new AstLtS{fl, lhsp, rhsp}; break;
+        case VNType::atLtS: newp = new AstLt{fl, lhsp, rhsp}; break;
+        case VNType::atLte: newp = new AstLteS{fl, lhsp, rhsp}; break;
+        case VNType::atLteS: newp = new AstLte{fl, lhsp, rhsp}; break;
+        case VNType::atDiv: newp = new AstDivS{fl, lhsp, rhsp}; break;
+        case VNType::atDivS: newp = new AstDiv{fl, lhsp, rhsp}; break;
+        case VNType::atModDiv: newp = new AstModDivS{fl, lhsp, rhsp}; break;
+        case VNType::atModDivS: newp = new AstModDiv{fl, lhsp, rhsp}; break;
+        case VNType::atMul: newp = new AstMulS{fl, lhsp, rhsp}; break;
+        case VNType::atMulS: newp = new AstMul{fl, lhsp, rhsp}; break;
+        case VNType::atShiftR: newp = new AstShiftRS{fl, lhsp, rhsp}; break;
+        case VNType::atShiftRS: newp = new AstShiftR{fl, lhsp, rhsp}; break;
         default:  // LCOV_EXCL_LINE
             nodep->v3fatalSrc("Node needs sign change, but bad case: " << nodep);
             break;
@@ -6430,25 +6430,25 @@ private:
         AstNodeBiop* newp = nullptr;
         // No width change on output;...                // All below have bool or double outputs
         switch (nodep->type()) {
-        case VNType::atAdd: newp = new AstAddD(fl, lhsp, rhsp); break;
-        case VNType::atSub: newp = new AstSubD(fl, lhsp, rhsp); break;
-        case VNType::atPow: newp = new AstPowD(fl, lhsp, rhsp); break;
+        case VNType::atAdd: newp = new AstAddD{fl, lhsp, rhsp}; break;
+        case VNType::atSub: newp = new AstSubD{fl, lhsp, rhsp}; break;
+        case VNType::atPow: newp = new AstPowD{fl, lhsp, rhsp}; break;
         case VNType::atEq:
-        case VNType::atEqCase: newp = new AstEqD(fl, lhsp, rhsp); break;
+        case VNType::atEqCase: newp = new AstEqD{fl, lhsp, rhsp}; break;
         case VNType::atNeq:
-        case VNType::atNeqCase: newp = new AstNeqD(fl, lhsp, rhsp); break;
+        case VNType::atNeqCase: newp = new AstNeqD{fl, lhsp, rhsp}; break;
         case VNType::atGt:
-        case VNType::atGtS: newp = new AstGtD(fl, lhsp, rhsp); break;
+        case VNType::atGtS: newp = new AstGtD{fl, lhsp, rhsp}; break;
         case VNType::atGte:
-        case VNType::atGteS: newp = new AstGteD(fl, lhsp, rhsp); break;
+        case VNType::atGteS: newp = new AstGteD{fl, lhsp, rhsp}; break;
         case VNType::atLt:
-        case VNType::atLtS: newp = new AstLtD(fl, lhsp, rhsp); break;
+        case VNType::atLtS: newp = new AstLtD{fl, lhsp, rhsp}; break;
         case VNType::atLte:
-        case VNType::atLteS: newp = new AstLteD(fl, lhsp, rhsp); break;
+        case VNType::atLteS: newp = new AstLteD{fl, lhsp, rhsp}; break;
         case VNType::atDiv:
-        case VNType::atDivS: newp = new AstDivD(fl, lhsp, rhsp); break;
+        case VNType::atDivS: newp = new AstDivD{fl, lhsp, rhsp}; break;
         case VNType::atMul:
-        case VNType::atMulS: newp = new AstMulD(fl, lhsp, rhsp); break;
+        case VNType::atMulS: newp = new AstMulD{fl, lhsp, rhsp}; break;
         default:  // LCOV_EXCL_LINE
             nodep->v3fatalSrc("Node needs conversion to double, but bad case: " << nodep);
             break;
@@ -6470,17 +6470,17 @@ private:
         // No width change on output;...                // All below have bool or double outputs
         switch (nodep->type()) {
         case VNType::atEq:
-        case VNType::atEqCase: newp = new AstEqN(fl, lhsp, rhsp); break;
+        case VNType::atEqCase: newp = new AstEqN{fl, lhsp, rhsp}; break;
         case VNType::atNeq:
-        case VNType::atNeqCase: newp = new AstNeqN(fl, lhsp, rhsp); break;
+        case VNType::atNeqCase: newp = new AstNeqN{fl, lhsp, rhsp}; break;
         case VNType::atGt:
-        case VNType::atGtS: newp = new AstGtN(fl, lhsp, rhsp); break;
+        case VNType::atGtS: newp = new AstGtN{fl, lhsp, rhsp}; break;
         case VNType::atGte:
-        case VNType::atGteS: newp = new AstGteN(fl, lhsp, rhsp); break;
+        case VNType::atGteS: newp = new AstGteN{fl, lhsp, rhsp}; break;
         case VNType::atLt:
-        case VNType::atLtS: newp = new AstLtN(fl, lhsp, rhsp); break;
+        case VNType::atLtS: newp = new AstLtN{fl, lhsp, rhsp}; break;
         case VNType::atLte:
-        case VNType::atLteS: newp = new AstLteN(fl, lhsp, rhsp); break;
+        case VNType::atLteS: newp = new AstLteN{fl, lhsp, rhsp}; break;
         default:  // LCOV_EXCL_LINE
             nodep->v3fatalSrc("Node needs conversion to string, but bad case: " << nodep);
             break;
@@ -6499,7 +6499,7 @@ private:
         AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack();
         AstNodeUniop* newp = nullptr;
         switch (nodep->type()) {
-        case VNType::atNegate: newp = new AstNegateD(fl, lhsp); break;
+        case VNType::atNegate: newp = new AstNegateD{fl, lhsp}; break;
         default:  // LCOV_EXCL_LINE
             nodep->v3fatalSrc("Node needs conversion to double, but bad case: " << nodep);
             break;
@@ -6522,9 +6522,9 @@ private:
             return;
         }
         AstNodeVarRef* const fromp = VN_AS(nodep->fromp()->unlinkFrBack(), VarRef);
-        AstNode* const newp = new AstAssign(
+        AstNode* const newp = new AstAssign{
             nodep->fileline(), fromp,
-            new AstSFormatF(nodep->fileline(), format, false, argp->exprp()->unlinkFrBack()));
+            new AstSFormatF{nodep->fileline(), format, false, argp->exprp()->unlinkFrBack()}};
         fromp->access(VAccess::WRITE);
         pushDeletep(nodep->backp());
         VL_DO_DANGLING(nodep->backp()->replaceWith(newp), newp);
@@ -6639,7 +6639,7 @@ private:
         case VAttrType::DIM_SIZE: val = !declRange.ranged() ? 0 : declRange.elements(); break;
         default: nodep->v3fatalSrc("Missing DIM ATTR type case"); break;
         }
-        if (!valp) valp = new AstConst(fileline, AstConst::Signed32(), val);
+        if (!valp) valp = new AstConst{fileline, AstConst::Signed32{}, val};
         UINFO(9, " $dimension " << attrType.ascii() << "(" << cvtToHex(dtypep) << "," << dim
                                 << ")=" << valp << endl);
         return valp;
@@ -6649,14 +6649,14 @@ private:
         const auto pos = m_tableMap.find(std::make_pair(nodep, attrType));
         if (pos != m_tableMap.end()) return pos->second;
         AstNodeArrayDType* const vardtypep
-            = new AstUnpackArrayDType(nodep->fileline(), nodep->findSigned32DType(),
-                                      new AstRange(nodep->fileline(), msbdim, 0));
-        AstInitArray* const initp = new AstInitArray(nodep->fileline(), vardtypep, nullptr);
+            = new AstUnpackArrayDType{nodep->fileline(), nodep->findSigned32DType(),
+                                      new AstRange(nodep->fileline(), msbdim, 0)};
+        AstInitArray* const initp = new AstInitArray{nodep->fileline(), vardtypep, nullptr};
         v3Global.rootp()->typeTablep()->addTypesp(vardtypep);
-        AstVar* const varp = new AstVar(nodep->fileline(), VVarType::MODULETEMP,
+        AstVar* const varp = new AstVar{nodep->fileline(), VVarType::MODULETEMP,
                                         "__Vdimtab_" + VString::downcase(attrType.ascii())
                                             + cvtToStr(m_dtTables++),
-                                        vardtypep);
+                                        vardtypep};
         varp->isConst(true);
         varp->isStatic(true);
         varp->valuep(initp);
@@ -6716,12 +6716,12 @@ private:
             vardtypep = new AstUnpackArrayDType{nodep->fileline(), basep,
                                                 new AstRange(nodep->fileline(), msbdim, 0)};
         }
-        AstInitArray* const initp = new AstInitArray(nodep->fileline(), vardtypep, nullptr);
+        AstInitArray* const initp = new AstInitArray{nodep->fileline(), vardtypep, nullptr};
         v3Global.rootp()->typeTablep()->addTypesp(vardtypep);
-        AstVar* const varp = new AstVar(nodep->fileline(), VVarType::MODULETEMP,
+        AstVar* const varp = new AstVar{nodep->fileline(), VVarType::MODULETEMP,
                                         "__Venumtab_" + VString::downcase(attrType.ascii())
                                             + cvtToStr(m_dtTables++),
-                                        vardtypep);
+                                        vardtypep};
         varp->isConst(true);
         varp->isStatic(true);
         varp->valuep(initp);
@@ -6730,9 +6730,9 @@ private:
 
         // Default for all unspecified values
         if (attrType == VAttrType::ENUM_NAME) {
-            initp->defaultp(new AstConst(nodep->fileline(), AstConst::String(), ""));
+            initp->defaultp(new AstConst{nodep->fileline(), AstConst::String{}, ""});
         } else if (attrType == VAttrType::ENUM_NEXT || attrType == VAttrType::ENUM_PREV) {
-            initp->defaultp(new AstConst(nodep->fileline(), V3Number(nodep, nodep->width(), 0)));
+            initp->defaultp(new AstConst{nodep->fileline(), V3Number{nodep, nodep->width(), 0}});
         } else if (attrType == VAttrType::ENUM_VALID) {
             initp->defaultp(new AstConst{nodep->fileline(), AstConst::BitFalse{}});
         } else {
@@ -6752,13 +6752,13 @@ private:
                 UASSERT_OBJ(vconstp, nodep, "Enum item without constified value");
                 const uint64_t i = vconstp->toUQuad();
                 if (attrType == VAttrType::ENUM_NAME) {
-                    values[i] = new AstConst(nodep->fileline(), AstConst::String(), itemp->name());
+                    values[i] = new AstConst{nodep->fileline(), AstConst::String{}, itemp->name()};
                 } else if (attrType == VAttrType::ENUM_NEXT) {
                     values[i] = (nextp ? nextp : firstp)->valuep()->cloneTree(false);  // A const
                 } else if (attrType == VAttrType::ENUM_PREV) {
                     values[i] = prevp->valuep()->cloneTree(false);  // A const
                 } else if (attrType == VAttrType::ENUM_VALID) {
-                    values[i] = new AstConst(nodep->fileline(), AstConst::BitTrue{});
+                    values[i] = new AstConst{nodep->fileline(), AstConst::BitTrue{}};
                 } else {
                     nodep->v3fatalSrc("Bad case");
                 }
@@ -6935,7 +6935,7 @@ private:
         // Note can't call V3Const::constifyParam(nodep) here, as constify may change nodep on us!
         if (!VN_IS(nodep, Const)) {
             nodep->v3error(message);
-            nodep->replaceWith(new AstConst(nodep->fileline(), AstConst::Unsized32(), 1));
+            nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::Unsized32{}, 1});
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         }
     }
@@ -7025,7 +7025,7 @@ public:
         : m_paramsOnly{paramsOnly}
         , m_doGenerate{doGenerate} {}
     AstNode* mainAcceptEdit(AstNode* nodep) {
-        return userIterateSubtreeReturnEdits(nodep, WidthVP(SELF, BOTH).p());
+        return userIterateSubtreeReturnEdits(nodep, WidthVP{SELF, BOTH}.p());
     }
     ~WidthVisitor() override = default;
 };
diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp
index 42bed398f..07579768d 100644
--- a/src/V3WidthSel.cpp
+++ b/src/V3WidthSel.cpp
@@ -55,7 +55,7 @@ private:
         // Note can't call V3Const::constifyParam(nodep) here, as constify may change nodep on us!
         if (!VN_IS(nodep, Const)) {
             nodep->v3error(message);
-            nodep->replaceWith(new AstConst(nodep->fileline(), AstConst::Unsized32(), 1));
+            nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::Unsized32{}, 1});
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         }
     }
@@ -126,18 +126,18 @@ private:
             V3Number num(lhsp, lhsp->width());
             num.opSub(VN_AS(lhsp, Const)->num(), V3Number(lhsp, 32, rhs));
             num.isSigned(lhsp->isSigned());
-            return new AstConst(lhsp->fileline(), num);
+            return new AstConst{lhsp->fileline(), num};
         } else if (rhs > 0) {
             AstNodeExpr* const newp
-                = new AstSub(lhsp->fileline(), lhsp,
-                             new AstConst(lhsp->fileline(), AstConst::Unsized32(), rhs));
+                = new AstSub{lhsp->fileline(), lhsp,
+                             new AstConst(lhsp->fileline(), AstConst::Unsized32{}, rhs)};
             // We must make sure sub gets sign of original value, not from the constant
             newp->dtypeFrom(lhsp);
             return newp;
         } else {  // rhs < 0;
             AstNodeExpr* const newp
-                = new AstAdd(lhsp->fileline(), lhsp,
-                             new AstConst(lhsp->fileline(), AstConst::Unsized32(), -rhs));
+                = new AstAdd{lhsp->fileline(), lhsp,
+                             new AstConst(lhsp->fileline(), AstConst::Unsized32{}, -rhs)};
             // We must make sure sub gets sign of original value, not from the constant
             newp->dtypeFrom(lhsp);
             return newp;
@@ -146,8 +146,8 @@ private:
     AstNodeExpr* newSubNeg(int32_t lhs, AstNodeExpr* rhsp) {
         // Return lhs-rhs
         // We must make sure sub gets sign of original value
-        AstNodeExpr* const newp = new AstSub(
-            rhsp->fileline(), new AstConst(rhsp->fileline(), AstConst::Unsized32(), lhs), rhsp);
+        AstNodeExpr* const newp = new AstSub{
+            rhsp->fileline(), new AstConst(rhsp->fileline(), AstConst::Unsized32{}, lhs), rhsp};
         newp->dtypeFrom(rhsp);  // Important as AstSub default is lhs's sign
         return newp;
     }
@@ -180,11 +180,11 @@ private:
         } else {
             // Need a slice data type, which is an array of the extracted
             // type, but with (presumably) different size
-            const VNumRange newRange(msb, lsb, nodep->declRange().littleEndian());
+            const VNumRange newRange{msb, lsb, nodep->declRange().littleEndian()};
             AstNodeDType* const vardtypep
-                = new AstPackArrayDType(nodep->fileline(),
+                = new AstPackArrayDType{nodep->fileline(),
                                         nodep->subDTypep(),  // Need to strip off array reference
-                                        new AstRange(nodep->fileline(), newRange));
+                                        new AstRange{nodep->fileline(), newRange}};
             v3Global.rootp()->typeTablep()->addTypesp(vardtypep);
             return vardtypep;
         }
@@ -219,7 +219,7 @@ private:
             if (fromRange.lo() != 0 || fromRange.hi() < 0) {
                 subp = newSubNeg(subp, fromRange.lo());
             }
-            AstArraySel* const newp = new AstArraySel(nodep->fileline(), fromp, subp);
+            AstArraySel* const newp = new AstArraySel{nodep->fileline(), fromp, subp};
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off array reference
             if (debug() >= 9) newp->dumpTree(cout, "--SELBTn: ");
             nodep->replaceWith(newp);
@@ -237,11 +237,11 @@ private:
                         "Array extraction with width miscomputed " << adtypep->width() << "/"
                                                                    << fromRange.elements());
             const int elwidth = adtypep->width() / fromRange.elements();
-            AstSel* const newp = new AstSel(
+            AstSel* const newp = new AstSel{
                 nodep->fileline(), fromp,
-                new AstMul(nodep->fileline(),
-                           new AstConst(nodep->fileline(), AstConst::Unsized32(), elwidth), subp),
-                new AstConst(nodep->fileline(), AstConst::Unsized32(), elwidth));
+                new AstMul{nodep->fileline(),
+                           new AstConst(nodep->fileline(), AstConst::Unsized32{}, elwidth), subp},
+                new AstConst(nodep->fileline(), AstConst::Unsized32{}, elwidth)};
             newp->declRange(fromRange);
             newp->declElWidth(elwidth);
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off array reference
@@ -251,7 +251,7 @@ private:
         } else if (const AstAssocArrayDType* const adtypep = VN_CAST(ddtypep, AssocArrayDType)) {
             // SELBIT(array, index) -> ASSOCSEL(array, index)
             AstNodeExpr* const subp = rhsp;
-            AstAssocSel* const newp = new AstAssocSel(nodep->fileline(), fromp, subp);
+            AstAssocSel* const newp = new AstAssocSel{nodep->fileline(), fromp, subp};
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off array reference
             if (debug() >= 9) newp->dumpTree(cout, "--SELBTn: ");
             nodep->replaceWith(newp);
@@ -268,7 +268,7 @@ private:
         } else if (const AstDynArrayDType* const adtypep = VN_CAST(ddtypep, DynArrayDType)) {
             // SELBIT(array, index) -> CMETHODCALL(queue, "at", index)
             AstNodeExpr* const subp = rhsp;
-            AstCMethodHard* const newp = new AstCMethodHard(nodep->fileline(), fromp, "at", subp);
+            AstCMethodHard* const newp = new AstCMethodHard{nodep->fileline(), fromp, "at", subp};
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off queue reference
             if (debug() >= 9) newp->dumpTree(cout, "--SELBTq: ");
             nodep->replaceWith(newp);
@@ -276,7 +276,7 @@ private:
         } else if (const AstQueueDType* const adtypep = VN_CAST(ddtypep, QueueDType)) {
             // SELBIT(array, index) -> CMETHODCALL(queue, "at", index)
             AstNodeExpr* const subp = rhsp;
-            AstCMethodHard* const newp = new AstCMethodHard(nodep->fileline(), fromp, "at", subp);
+            AstCMethodHard* const newp = new AstCMethodHard{nodep->fileline(), fromp, "at", subp};
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off queue reference
             if (debug() >= 9) newp->dumpTree(cout, "--SELBTq: ");
             nodep->replaceWith(newp);
@@ -290,9 +290,9 @@ private:
             }
             AstNodeExpr* newp;
             if (varrefp && varrefp->access().isReadOnly()) {
-                newp = new AstGetcN(nodep->fileline(), fromp, rhsp);
+                newp = new AstGetcN{nodep->fileline(), fromp, rhsp};
             } else {
-                newp = new AstGetcRefN(nodep->fileline(), fromp, rhsp);
+                newp = new AstGetcRefN{nodep->fileline(), fromp, rhsp};
             }
             UINFO(6, "   new " << newp << endl);
             nodep->replaceWith(newp);
@@ -300,9 +300,9 @@ private:
         } else if (VN_IS(ddtypep, BasicDType)) {
             // SELBIT(range, index) -> SEL(array, index, 1)
             AstSel* const newp
-                = new AstSel(nodep->fileline(), fromp, newSubLsbOf(rhsp, fromRange),
+                = new AstSel{nodep->fileline(), fromp, newSubLsbOf(rhsp, fromRange),
                              // Unsized so width from user
-                             new AstConst(nodep->fileline(), AstConst::Unsized32(), 1));
+                             new AstConst{nodep->fileline(), AstConst::Unsized32{}, 1}};
             newp->declRange(fromRange);
             UINFO(6, "   new " << newp << endl);
             if (debug() >= 9) newp->dumpTree(cout, "--SELBTn: ");
@@ -311,9 +311,9 @@ private:
         } else if (VN_IS(ddtypep, NodeUOrStructDType)) {  // A bit from the packed struct
             // SELBIT(range, index) -> SEL(array, index, 1)
             AstSel* const newp
-                = new AstSel(nodep->fileline(), fromp, newSubLsbOf(rhsp, fromRange),
+                = new AstSel{nodep->fileline(), fromp, newSubLsbOf(rhsp, fromRange),
                              // Unsized so width from user
-                             new AstConst(nodep->fileline(), AstConst::Unsized32(), 1));
+                             new AstConst{nodep->fileline(), AstConst::Unsized32{}, 1}};
             newp->declRange(fromRange);
             UINFO(6, "   new " << newp << endl);
             if (debug() >= 9) newp->dumpTree(cout, "--SELBTn: ");
@@ -358,7 +358,7 @@ private:
                 nodep->replaceWith(fromp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
             } else if (fromRange.elements() == 1) {  // Extracting single element
-                AstArraySel* const newp = new AstArraySel(nodep->fileline(), fromp, lsbp);
+                AstArraySel* const newp = new AstArraySel{nodep->fileline(), fromp, lsbp};
                 nodep->replaceWith(newp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
             } else {  // Slice
@@ -392,11 +392,11 @@ private:
                 lsb = x;
             }
             const int elwidth = adtypep->width() / fromRange.elements();
-            AstSel* const newp = new AstSel(
+            AstSel* const newp = new AstSel{
                 nodep->fileline(), fromp,
-                new AstMul(nodep->fileline(), newSubLsbOf(lsbp, fromRange),
-                           new AstConst(nodep->fileline(), AstConst::Unsized32(), elwidth)),
-                new AstConst(nodep->fileline(), AstConst::Unsized32(), (msb - lsb + 1) * elwidth));
+                new AstMul{nodep->fileline(), newSubLsbOf(lsbp, fromRange),
+                           new AstConst(nodep->fileline(), AstConst::Unsized32{}, elwidth)},
+                new AstConst(nodep->fileline(), AstConst::Unsized32{}, (msb - lsb + 1) * elwidth)};
             newp->declRange(fromRange);
             newp->declElWidth(elwidth);
             newp->dtypeFrom(sliceDType(adtypep, msb, lsb));
@@ -421,12 +421,11 @@ private:
                 msb = lsb;
                 lsb = x;
             }
-            AstNodeExpr* const widthp
-                = new AstConst(msbp->fileline(),
-                               AstConst::Unsized32(),  // Unsized so width from user
-                               msb + 1 - lsb);
+            AstNodeExpr* const widthp = new AstConst(
+                msbp->fileline(), AstConst::Unsized32{},  // Unsized so width from user
+                msb + 1 - lsb);
             AstSel* const newp
-                = new AstSel(nodep->fileline(), fromp, newSubLsbOf(lsbp, fromRange), widthp);
+                = new AstSel{nodep->fileline(), fromp, newSubLsbOf(lsbp, fromRange), widthp};
             newp->declRange(fromRange);
             UINFO(6, "   new " << newp << endl);
             // if (debug() >= 9) newp->dumpTree(cout, "--SELEXnew: ");
@@ -444,19 +443,18 @@ private:
                 msb = lsb;
                 lsb = x;
             }
-            AstNodeExpr* const widthp
-                = new AstConst(msbp->fileline(),
-                               AstConst::Unsized32(),  // Unsized so width from user
-                               msb + 1 - lsb);
+            AstNodeExpr* const widthp = new AstConst(
+                msbp->fileline(), AstConst::Unsized32{},  // Unsized so width from user
+                msb + 1 - lsb);
             AstSel* const newp
-                = new AstSel(nodep->fileline(), fromp, newSubLsbOf(lsbp, fromRange), widthp);
+                = new AstSel{nodep->fileline(), fromp, newSubLsbOf(lsbp, fromRange), widthp};
             newp->declRange(fromRange);
             UINFO(6, "   new " << newp << endl);
             // if (debug() >= 9) newp->dumpTree(cout, "--SELEXnew: ");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (VN_IS(ddtypep, QueueDType)) {
-            auto* const newp = new AstCMethodHard(nodep->fileline(), fromp, "slice", msbp);
+            auto* const newp = new AstCMethodHard{nodep->fileline(), fromp, "slice", msbp};
             msbp->addNext(lsbp);
             newp->dtypep(ddtypep);
             newp->didWidth(true);
@@ -511,7 +509,7 @@ private:
                 nodep->replaceWith(fromp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
             } else if (fromRange.elements() == 1) {  // Extracting single element
-                AstArraySel* const newp = new AstArraySel(nodep->fileline(), fromp, rhsp);
+                AstArraySel* const newp = new AstArraySel{nodep->fileline(), fromp, rhsp};
                 nodep->replaceWith(newp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
             } else if (VN_IS(rhsp, Const)) {  // Slice
@@ -537,7 +535,7 @@ private:
             if (const AstPackArrayDType* const adtypep = VN_CAST(ddtypep, PackArrayDType)) {
                 elwidth = adtypep->width() / fromRange.elements();
                 newwidthp
-                    = new AstConst(nodep->fileline(), AstConst::Unsized32(), width * elwidth);
+                    = new AstConst(nodep->fileline(), AstConst::Unsized32{}, width * elwidth);
             }
             AstNodeExpr* newlsbp = nullptr;
             if (VN_IS(nodep, SelPlus)) {
@@ -560,10 +558,10 @@ private:
                 nodep->v3fatalSrc("Bad Case");
             }
             if (elwidth != 1) {
-                newlsbp = new AstMul(nodep->fileline(), newlsbp,
-                                     new AstConst(nodep->fileline(), elwidth));
+                newlsbp = new AstMul{nodep->fileline(), newlsbp,
+                                     new AstConst(nodep->fileline(), elwidth)};
             }
-            AstSel* const newp = new AstSel(nodep->fileline(), fromp, newlsbp, newwidthp);
+            AstSel* const newp = new AstSel{nodep->fileline(), fromp, newlsbp, newwidthp};
             newp->declRange(fromRange);
             newp->declElWidth(elwidth);
             UINFO(6, "   new " << newp << endl);
diff --git a/src/verilog.y b/src/verilog.y
index 3958341cc..f46cc147b 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -123,7 +123,7 @@ public:
     AstNode* createSupplyExpr(FileLine* fileline, const string& name, int value);
     AstText* createTextQuoted(FileLine* fileline, const string& text) {
         string newtext = deQuote(fileline, text);
-        return new AstText(fileline, newtext);
+        return new AstText{fileline, newtext};
     }
     AstNode* createCellOrIfaceRef(FileLine* fileline, const string& name, AstPin* pinlistp,
                                   AstNodeRange* rangelistp) {
@@ -151,8 +151,8 @@ public:
         return nodep;
     }
     AstDisplay* createDisplayError(FileLine* fileline) {
-        AstDisplay* nodep = new AstDisplay(fileline, VDisplayType::DT_ERROR, "", nullptr, nullptr);
-        AstNode::addNext<AstNode, AstNode>(nodep, new AstStop(fileline, true));
+        AstDisplay* nodep = new AstDisplay{fileline, VDisplayType::DT_ERROR, "", nullptr, nullptr};
+        AstNode::addNext<AstNode, AstNode>(nodep, new AstStop{fileline, true});
         return nodep;
     }
     AstNodeExpr* createGatePin(AstNodeExpr* exprp) {
@@ -160,7 +160,7 @@ public:
         if (!rangep) {
             return exprp;
         } else {
-            return new AstGatePin(rangep->fileline(), exprp, rangep->cloneTree(true));
+            return new AstGatePin{rangep->fileline(), exprp, rangep->cloneTree(true)};
         }
     }
     AstNode* createTypedef(FileLine* fl, const string& name, AstNode* attrsp, AstNodeDType* basep,
@@ -1159,7 +1159,7 @@ package_declaration:            // ==IEEE: package_declaration
 
 packageFront<nodeModulep>:
                 yPACKAGE lifetimeE idAny ';'
-                        { $$ = new AstPackage($<fl>3, *$3);
+                        { $$ = new AstPackage{$<fl>3, *$3};
                           $$->inLibrary(true);  // packages are always libraries; don't want to make them a "top"
                           $$->lifetime($2);
                           $$->modTrace(GRAMMARP->allTracingOn($$->fileline()));
@@ -1224,7 +1224,7 @@ package_import_item<nodep>:     // ==IEEE: package_import_item
                               $$ = nullptr;
                               $<fl>1->v3error("Importing from missing package '" << *$<strp>1 << "'");
                           } else {
-                              $$ = new AstPackageImport($<fl>2, VN_CAST($<scp>1, Package), *$3);
+                              $$ = new AstPackageImport{$<fl>2, VN_CAST($<scp>1, Package), *$3};
                               SYMP->importItem($<scp>1,*$3);
                           } }
         ;
@@ -1285,7 +1285,7 @@ modFront<nodeModulep>:
         //                      // General note: all *Front functions must call symPushNew before
         //                      // any formal arguments, as the arguments must land in the new scope.
                 yMODULE lifetimeE idAny
-                        { $$ = new AstModule($<fl>3,*$3);
+                        { $$ = new AstModule{$<fl>3, *$3};
                           $$->lifetime($2);
                           $$->inLibrary(PARSEP->inLibrary() || $$->fileline()->celldefineOn());
                           $$->modTrace(GRAMMARP->allTracingOn($$->fileline()));
@@ -1304,10 +1304,11 @@ importsAndParametersE<nodep>:   // IEEE: common part of module_declaration, inte
 
 udpFront<nodeModulep>:
                 yPRIMITIVE lifetimeE idAny
-                        { $$ = new AstPrimitive($<fl>3, *$3); $$->inLibrary(true);
+                        { $$ = new AstPrimitive{$<fl>3, *$3};
+                          $$->inLibrary(true);
                           $$->lifetime($2);
                           $$->modTrace(false);
-                          $$->addStmtsp(new AstPragma($<fl>3, VPragmaType::INLINE_MODULE));
+                          $$->addStmtsp(new AstPragma{$<fl>3, VPragmaType::INLINE_MODULE});
                           GRAMMARP->m_tracingParse = false;
                           PARSEP->rootp()->addModulesp($$);
                           SYMP->pushNew($$); }
@@ -1531,7 +1532,7 @@ interface_declaration:          // IEEE: interface_declaration + interface_nonan
 
 intFront<nodeModulep>:
                 yINTERFACE lifetimeE idAny/*new_interface*/
-                        { $$ = new AstIface($<fl>3, *$3);
+                        { $$ = new AstIface{$<fl>3, *$3};
                           $$->inLibrary(true);
                           $$->lifetime($2);
                           PARSEP->rootp()->addModulesp($$);
@@ -1623,7 +1624,7 @@ program_declaration:            // IEEE: program_declaration + program_nonansi_h
 
 pgmFront<nodeModulep>:
                 yPROGRAM lifetimeE idAny/*new_program*/
-                        { $$ = new AstModule($<fl>3, *$3, true);
+                        { $$ = new AstModule{$<fl>3, *$3, true};
                           $$->lifetime($2);
                           $$->inLibrary(PARSEP->inLibrary() || $$->fileline()->celldefineOn());
                           $$->modTrace(GRAMMARP->allTracingOn($$->fileline()));
@@ -4360,10 +4361,10 @@ dpi_import_export<nodep>:       // ==IEEE: dpi_import_export
                           if ($$->prettyName()[0]=='$') SYMP->reinsert($$,nullptr,$$->prettyName());  // For $SysTF overriding
                           SYMP->reinsert($$); }
         |       yEXPORT yaSTRING dpi_importLabelE yFUNCTION idAny ';'
-                        { $$ = new AstDpiExport($<fl>5, *$5, *$3);
+                        { $$ = new AstDpiExport{$<fl>5, *$5, *$3};
                           GRAMMARP->checkDpiVer($1, *$2); v3Global.dpi(true); }
         |       yEXPORT yaSTRING dpi_importLabelE yTASK     idAny ';'
-                        { $$ = new AstDpiExport($<fl>5, *$5, *$3);
+                        { $$ = new AstDpiExport{$<fl>5, *$5, *$3};
                           GRAMMARP->checkDpiVer($1, *$2); v3Global.dpi(true); }
         ;
 
@@ -4831,11 +4832,11 @@ streaming_concatenation<nodeStreamp>: // ==IEEE: streaming_concatenation
         |       '{' yP_SLEFT  stream_expressionOrDataType stream_concatenation '}'
                         { AstNodeExpr* const bitsp = VN_IS($3, NodeExpr) ? VN_AS($3, NodeExpr)
                                                                          : new AstAttrOf{$1, VAttrType::DIM_BITS, $3};
-                          $$ = new AstStreamL($2, $4, bitsp); }
+                          $$ = new AstStreamL{$2, $4, bitsp}; }
         |       '{' yP_SRIGHT stream_expressionOrDataType stream_concatenation '}'
                         { AstNodeExpr* const bitsp = VN_IS($3, NodeExpr) ? VN_AS($3, NodeExpr)
                                                                           : new AstAttrOf{$1, VAttrType::DIM_BITS, $3};
-                          $$ = new AstStreamR($2, $4, bitsp); }
+                          $$ = new AstStreamR{$2, $4, bitsp}; }
         ;
 
 stream_concatenation<nodeExprp>:    // ==IEEE: stream_concatenation
@@ -4960,7 +4961,7 @@ gateRangeE<nodep>:
 
 gateBuf<nodep>:
                 gateFront variable_lvalue ',' gatePinExpr ')'
-                        { $$ = new AstAssignW($<fl>1, $2, $4); DEL($1); }
+                        { $$ = new AstAssignW{$<fl>1, $2, $4}; DEL($1); }
         // UNSUP                        // IEEE: Multiple output variable_lvalues
         // UNSUP                        // Causes conflict - need to take in variable_lvalue or a gatePinExpr
         ;
@@ -5089,7 +5090,7 @@ tableEntryList<udpTableLinep>:  // IEEE: { combinational_entry | sequential_entr
         ;
 
 tableEntry<udpTableLinep>:      // IEEE: combinational_entry + sequential_entry
-                yaTABLELINE                             { $$ = new AstUdpTableLine($<fl>1,*$1); }
+                yaTABLELINE                             { $$ = new AstUdpTableLine{$<fl>1, *$1}; }
         |       error                                   { $$ = nullptr; }
         ;
 
@@ -5313,7 +5314,7 @@ endLabelE<strp>:
 clocking_declaration<nodep>:            // IEEE: clocking_declaration  (INCOMPLETE)
         //UNSUP: vvv remove this -- vastly simplified grammar:
                 yDEFAULT yCLOCKING '@' '(' senitemEdge ')' ';' yENDCLOCKING
-                        { $$ = new AstClocking($2, $5, nullptr); }
+                        { $$ = new AstClocking{$2, $5, nullptr}; }
         //UNSUP: ^^^ remove this -- vastly simplified grammar:
         //UNSUP clockingFront clocking_event ';'
         //UNSUP  clocking_itemListE yENDCLOCKING endLabelE { SYMP->popScope($$); }
@@ -5410,7 +5411,7 @@ assertion_item<nodep>:          // ==IEEE: assertion_item
 deferred_immediate_assertion_item<nodep>:       // ==IEEE: deferred_immediate_assertion_item
                 deferred_immediate_assertion_statement  { $$ = $1; }
         |       id/*block_identifier*/ ':' deferred_immediate_assertion_statement
-                        { $$ = new AstBegin($<fl>1, *$1, $3, false, true); }
+                        { $$ = new AstBegin{$<fl>1, *$1, $3, false, true}; }
         ;
 
 procedural_assertion_statement<nodep>:  // ==IEEE: procedural_assertion_statement
@@ -5466,7 +5467,7 @@ deferred_immediate_assertion_statement<nodep>:  // ==IEEE: deferred_immediate_as
 concurrent_assertion_item<nodep>:       // IEEE: concurrent_assertion_item
                 concurrent_assertion_statement          { $$ = $1; }
         |       id/*block_identifier*/ ':' concurrent_assertion_statement
-                        { $$ = new AstBegin($<fl>1, *$1, $3, false, true); }
+                        { $$ = new AstBegin{$<fl>1, *$1, $3, false, true}; }
         //                      // IEEE: checker_instantiation
         //                      // identical to module_instantiation; see etcInst
         ;
@@ -6312,14 +6313,14 @@ class_declaration<nodep>:       // ==IEEE: part of class_declaration
 
 classFront<classp>:             // IEEE: part of class_declaration
                 classVirtualE yCLASS lifetimeE idAny/*class_identifier*/
-                        { $$ = new AstClass($2, *$4);
+                        { $$ = new AstClass{$2, *$4};
                           $$->isVirtual($1);
                           $$->lifetime($3);
                           SYMP->pushNew($<classp>$);
                           v3Global.setHasClasses(); }
         //                      // IEEE: part of interface_class_declaration
         |       yINTERFACE yCLASS lifetimeE idAny/*class_identifier*/
-                        { $$ = new AstClass($2, *$4);
+                        { $$ = new AstClass{$2, *$4};
                           $$->lifetime($3);
                           SYMP->pushNew($<classp>$);
                           BBUNSUP($2, "Unsupported: interface classes");  }
@@ -6347,11 +6348,11 @@ classExtendsList<classExtendsp>:        // IEEE: part of class_declaration
 
 classExtendsOne<classExtendsp>:         // IEEE: part of class_declaration
                 class_typeExtImpList
-                        { $$ = new AstClassExtends($1->fileline(), $1);
+                        { $$ = new AstClassExtends{$1->fileline(), $1};
                           $<scp>$ = $<scp>1; }
         //
         |       class_typeExtImpList '(' list_of_argumentsE ')'
-                        { $$ = new AstClassExtends($1->fileline(), $1);
+                        { $$ = new AstClassExtends{$1->fileline(), $1};
                           $<scp>$ = $<scp>1;
                           if ($3) BBUNSUP($3, "Unsupported: extends with parameters"); }
         ;
@@ -6388,17 +6389,17 @@ class_typeExtImpOne<nodep>:     // part of IEEE: class_type, where we either get
                 idAny
         /*mid*/         { /* no nextId as not refing it above this*/ }
         /*cont*/    parameter_value_assignmentE
-                        { $$ = new AstClassOrPackageRef($<fl>1, *$1, $<scp>1, $3);
+                        { $$ = new AstClassOrPackageRef{$<fl>1, *$1, $<scp>1, $3};
                           $<scp>$ = $<scp>1; }
         //
         //                      // package_sopeIdFollows expanded
         |       yD_UNIT yP_COLONCOLON
-                        { $$ = new AstClassOrPackageRef($<fl>1, "$unit", nullptr, nullptr);
+                        { $$ = new AstClassOrPackageRef{$<fl>1, "$unit", nullptr, nullptr};
                           $<scp>$ = nullptr;  // No purpose otherwise, every symtab can see root
                           SYMP->nextId(PARSEP->rootp()); }
         //
         |       yLOCAL__COLONCOLON yP_COLONCOLON
-                        { $$ = new AstClassOrPackageRef($<fl>1, "local::", nullptr, nullptr);
+                        { $$ = new AstClassOrPackageRef{$<fl>1, "local::", nullptr, nullptr};
                           $<scp>$ = nullptr;  // UNSUP
                           SYMP->nextId(PARSEP->rootp());
                           BBUNSUP($1, "Unsupported: Randomize 'local::'"); }
@@ -6434,7 +6435,7 @@ packageClassScope<nodeExprp>:   // IEEE: class_scope
         |       localNextId yP_COLONCOLON               { $$ = $1; $<scp>$ = $<scp>1; }
         |       dollarUnitNextId yP_COLONCOLON          { $$ = $1; $<scp>$ = $<scp>1; }
         |       dollarUnitNextId yP_COLONCOLON packageClassScopeList
-                        { $$ = new AstDot($2, true, $1, $3); $<scp>$ = $<scp>3; }
+                        { $$ = new AstDot{$2, true, $1, $3}; $<scp>$ = $<scp>3; }
         ;
 
 packageClassScopeList<nodeExprp>:   // IEEE: class_type: "id [ parameter_value_assignment ]" but allow yaID__aTYPE
@@ -6445,7 +6446,7 @@ packageClassScopeList<nodeExprp>:   // IEEE: class_type: "id [ parameter_value_a
         //                      // If you follow the rules down, class_type is really a list via ps_class_identifier
                 packageClassScopeItem                   { $$ = $1; $<scp>$ = $<scp>1; }
         |       packageClassScopeList packageClassScopeItem
-                        { $$ = new AstDot($<fl>2, true, $1, $2); $<scp>$ = $<scp>2; }
+                        { $$ = new AstDot{$<fl>2, true, $1, $2}; $<scp>$ = $<scp>2; }
         ;
 
 packageClassScopeItem<nodeExprp>:   // IEEE: package_scope or [package_scope]::[class_scope]
@@ -6456,12 +6457,12 @@ packageClassScopeItem<nodeExprp>:   // IEEE: package_scope or [package_scope]::[
                 idCC
         /*mid*/         { SYMP->nextId($<scp>1); }
         /*cont*/    yP_COLONCOLON
-                        { $$ = new AstClassOrPackageRef($<fl>1, *$1, $<scp>1, nullptr); $<scp>$ = $<scp>1; }
+                        { $$ = new AstClassOrPackageRef{$<fl>1, *$1, $<scp>1, nullptr}; $<scp>$ = $<scp>1; }
         //
         |       idCC parameter_value_assignment
         /*mid*/         { SYMP->nextId($<scp>1); }   // Change next *after* we handle parameters, not before
         /*cont*/    yP_COLONCOLON
-                        { $$ = new AstClassOrPackageRef($<fl>1, *$1, $<scp>1, $2); $<scp>$ = $<scp>1; }
+                        { $$ = new AstClassOrPackageRef{$<fl>1, *$1, $<scp>1, $2}; $<scp>$ = $<scp>1; }
         ;
 
 dollarUnitNextId<nodeExprp>:    // $unit
@@ -6650,7 +6651,7 @@ constraintStaticE<cbool>:  // IEEE: part of extern_constraint_declaration
 
 timeNumAdjusted<nodeExprp>:         // Time constant, adjusted to module's time units/precision
                 yaTIMENUM
-                        { $$ = new AstTimeImport($<fl>1, new AstConst($<fl>1, AstConst::RealDouble(), $1)); }
+                        { $$ = new AstTimeImport{$<fl>1, new AstConst{$<fl>1, AstConst::RealDouble{}, $1}}; }
         ;
 
 //**********************************************************************

From 62bdd3ab497ac333dc528f080663ed9daed87f8f Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Mon, 21 Nov 2022 12:27:55 +0100
Subject: [PATCH 078/156] Fix timing control in while-break loops (#3733)
 (#3769)

---
 src/V3Const.cpp                          | 13 ++++------
 test_regress/t/t_while_timing_control.pl | 30 ++++++++++++++++++++++++
 test_regress/t/t_while_timing_control.v  | 24 +++++++++++++++++++
 3 files changed, 59 insertions(+), 8 deletions(-)
 create mode 100755 test_regress/t/t_while_timing_control.pl
 create mode 100644 test_regress/t/t_while_timing_control.v

diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 000b31dab..c583563d8 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -2801,14 +2801,11 @@ private:
             // least as frequently activating.  So we
             // SENGATE(SENITEM(x)) -> SENITEM(x), then let it collapse with the
             // other SENITEM(x).
-            {
-                const VNUser4InUse m_inuse4;
-                // Mark x in SENITEM(x)
-                for (AstSenItem* senp = nodep->sensesp(); senp;
-                     senp = VN_AS(senp->nextp(), SenItem)) {
-                    if (senp->varrefp() && senp->varrefp()->varScopep()) {
-                        senp->varrefp()->varScopep()->user4(1);
-                    }
+
+            // Mark x in SENITEM(x)
+            for (AstSenItem* senp = nodep->sensesp(); senp; senp = VN_AS(senp->nextp(), SenItem)) {
+                if (senp->varrefp() && senp->varrefp()->varScopep()) {
+                    senp->varrefp()->varScopep()->user4(1);
                 }
             }
 
diff --git a/test_regress/t/t_while_timing_control.pl b/test_regress/t/t_while_timing_control.pl
new file mode 100755
index 000000000..5f740b172
--- /dev/null
+++ b/test_regress/t/t_while_timing_control.pl
@@ -0,0 +1,30 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+$Self->{main_time_multiplier} = 10e-7 / 10e-9;
+
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    compile(
+        timing_loop => 1,
+        verilator_flags2 => ['--timing -Wno-ZERODLY'],
+        );
+
+    execute(
+        check_finished => 1,
+        );
+}
+
+ok(1);
+1;
diff --git a/test_regress/t/t_while_timing_control.v b/test_regress/t/t_while_timing_control.v
new file mode 100644
index 000000000..11d54b9c6
--- /dev/null
+++ b/test_regress/t/t_while_timing_control.v
@@ -0,0 +1,24 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t();
+   logic clk = 0;
+   logic out = 1;
+
+   always #5 clk = ~clk;
+
+   initial begin
+      while(1) begin
+         if(out) begin
+            break;
+         end
+         @(negedge clk);
+      end
+
+      $write("*-* All Finished *-*\n");
+      $finish();
+   end
+endmodule

From d3c1f4353e5136f3d830e2775d8e3c1697d9f044 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 21 Nov 2022 06:48:13 -0500
Subject: [PATCH 079/156] Fix float parameters without parens

---
 src/verilog.y            | 15 +++++++--------
 test_regress/t/t_param.v |  9 +++++++++
 2 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/src/verilog.y b/src/verilog.y
index f46cc147b..d7c64917b 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1322,12 +1322,11 @@ parameter_value_assignmentE<pinp>:      // IEEE: [ parameter_value_assignment ]
 parameter_value_assignment<pinp>:       // IEEE: parameter_value_assignment
                 '#' '(' cellparamList ')'               { $$ = $3; }
         //                      // Parentheses are optional around a single parameter
-        |       '#' yaINTNUM                            { $$ = new AstPin($<fl>2, 1, "", new AstConst($<fl>2, *$2)); }
-        |       '#' yaFLOATNUM                          { $$ = new AstPin($<fl>2, 1, "",
-                                                                          new AstConst($<fl>2, AstConst::Unsized32(),
-                                                                                       (int)(($2<0)?($2-0.5):($2+0.5)))); }
-        |       '#' timeNumAdjusted                     { $$ = new AstPin($<fl>2, 1, "", $2); }
-        |       '#' idClassSel                          { $$ = new AstPin($<fl>2, 1, "", $2); }
+        |       '#' yaINTNUM                            { $$ = new AstPin{$<fl>2, 1, "", new AstConst{$<fl>2, *$2}}; }
+        |       '#' yaFLOATNUM                          { $$ = new AstPin{$<fl>2, 1, "",
+                                                                          new AstConst{$<fl>2, AstConst::RealDouble{}, $2}}; }
+        |       '#' timeNumAdjusted                     { $$ = new AstPin{$<fl>2, 1, "", $2}; }
+        |       '#' idClassSel                          { $$ = new AstPin{$<fl>2, 1, "", $2}; }
         //                      // Not needed in Verilator:
         //                      // Side effect of combining *_instantiations
         //                      // '#' delay_value      { UNSUP }
@@ -2794,8 +2793,8 @@ delay_control<delayp>:   //== IEEE: delay_control
 delay_value<nodeExprp>:         // ==IEEE:delay_value
         //                      // IEEE: ps_identifier
                 packageClassScopeE varRefBase           { $$ = AstDot::newIfPkg($<fl>2, $1, $2); }
-        |       yaINTNUM                                { $$ = new AstConst($<fl>1, *$1); }
-        |       yaFLOATNUM                              { $$ = new AstConst($<fl>1, AstConst::RealDouble(), $1); }
+        |       yaINTNUM                                { $$ = new AstConst{$<fl>1, *$1}; }
+        |       yaFLOATNUM                              { $$ = new AstConst{$<fl>1, AstConst::RealDouble{}, $1}; }
         |       timeNumAdjusted                         { $$ = $1; }
         ;
 
diff --git a/test_regress/t/t_param.v b/test_regress/t/t_param.v
index 884b8f23c..abcc6e402 100644
--- a/test_regress/t/t_param.v
+++ b/test_regress/t/t_param.v
@@ -13,6 +13,7 @@ module t (/*AUTOARG*/
    m1 #(PAR) m1();
    m3 #(PAR) m3();
    mnooverride #(10) mno();
+   mreal #1.2 mr();
 
    input clk;
    integer cyc=1;
@@ -74,3 +75,11 @@ module mnooverride;
       if (PAR !== 10) $stop;
    end
 endmodule
+
+module mreal;
+   parameter real REAL = 99.99;
+   initial begin
+      $display("%f", REAL);
+      if (REAL !== 1.2) $stop;
+   end
+endmodule

From b82ce5743b65db6188400f99eb0a016c551f7282 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 21 Nov 2022 08:29:05 -0500
Subject: [PATCH 080/156] Internals: Fix verilog.y style

---
 src/verilog.y | 560 +++++++++++++++++++++++++++-----------------------
 1 file changed, 308 insertions(+), 252 deletions(-)

diff --git a/src/verilog.y b/src/verilog.y
index d7c64917b..0ef909f90 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1154,7 +1154,7 @@ package_declaration:            // ==IEEE: package_declaration
                           if ($2) $1->addStmtsp($2);
                           GRAMMARP->m_modp = nullptr;
                           SYMP->popScope($1);
-                          GRAMMARP->endLabel($<fl>4,$1,$4); }
+                          GRAMMARP->endLabel($<fl>4, $1, $4); }
         ;
 
 packageFront<nodeModulep>:
@@ -1205,7 +1205,8 @@ package_or_generate_item_declaration<nodep>:    // ==IEEE: package_or_generate_i
 
 package_import_declarationList<nodep>:
                 package_import_declaration              { $$ = $1; }
-        |       package_import_declarationList package_import_declaration { $$ = addNextNull($1, $2); }
+        |       package_import_declarationList package_import_declaration
+                        { $$ = addNextNull($1, $2); }
         ;
 
 package_import_declaration<nodep>:      // ==IEEE: package_import_declaration
@@ -1225,7 +1226,7 @@ package_import_item<nodep>:     // ==IEEE: package_import_item
                               $<fl>1->v3error("Importing from missing package '" << *$<strp>1 << "'");
                           } else {
                               $$ = new AstPackageImport{$<fl>2, VN_CAST($<scp>1, Package), *$3};
-                              SYMP->importItem($<scp>1,*$3);
+                              SYMP->importItem($<scp>1, *$3);
                           } }
         ;
 
@@ -1265,7 +1266,7 @@ module_declaration:             // ==IEEE: module_declaration
                           if ($5) $1->addStmtsp($5);
                           GRAMMARP->m_modp = nullptr;
                           SYMP->popScope($1);
-                          GRAMMARP->endLabel($<fl>7,$1,$7); }
+                          GRAMMARP->endLabel($<fl>7, $1, $7); }
         |       udpFront parameter_port_listE portsStarE ';'
         /*cont*/    module_itemListE yENDPRIMITIVE endLabelE
                         { $1->modTrace(false);  // Stash for implicit wires, etc
@@ -1275,7 +1276,7 @@ module_declaration:             // ==IEEE: module_declaration
                           GRAMMARP->m_tracingParse = true;
                           GRAMMARP->m_modp = nullptr;
                           SYMP->popScope($1);
-                          GRAMMARP->endLabel($<fl>7,$1,$7); }
+                          GRAMMARP->endLabel($<fl>7, $1, $7); }
         //
         |       yEXTERN modFront parameter_port_listE portsStarE ';'
                         { BBUNSUP($<fl>1, "Unsupported: extern module"); }
@@ -1344,7 +1345,8 @@ parameter_port_listE<nodep>:    // IEEE: parameter_port_list + empty == paramete
         //                      // IEEE: '#' '(' parameter_port_declaration { ',' parameter_port_declaration } ')'
         //                      // Can't just do that as "," conflicts with between vars and between stmts, so
         //                      // split into pre-comma and post-comma parts
-        |       '#' '(' {VARRESET_LIST(GPARAM);} paramPortDeclOrArgList ')'     { $$ = $4; VARRESET_NONLIST(UNKNOWN); }
+        |       '#' '(' {VARRESET_LIST(GPARAM);} paramPortDeclOrArgList ')'
+                        { $$ = $4; VARRESET_NONLIST(UNKNOWN); }
         //                      // Note legal to start with "a=b" with no parameter statement
         ;
 
@@ -1412,12 +1414,14 @@ port<nodep>:                    // ==IEEE: port
         //                      // We use instantCb here because the non-port form looks just like a module instantiation
                 portDirNetE id/*interface*/                      portSig variable_dimensionListE sigAttrListE
                         { $$ = $3; VARDECL(IFACEREF); VARIO(NONE);
-                          VARDTYPE(new AstIfaceRefDType($<fl>2,"",*$2));
-                          addNextNull($$, VARDONEP($$,$4,$5)); }
+                          AstNodeDType* const dtp = new AstIfaceRefDType{$<fl>2, "", *$2};
+                          VARDTYPE(dtp);
+                          addNextNull($$, VARDONEP($$, $4, $5)); }
         |       portDirNetE id/*interface*/ '.' idAny/*modport*/ portSig variable_dimensionListE sigAttrListE
                         { $$ = $5; VARDECL(IFACEREF); VARIO(NONE);
-                          VARDTYPE(new AstIfaceRefDType($<fl>2, $<fl>4, "", *$2, *$4));
-                          addNextNull($$, VARDONEP($$,$6,$7)); }
+                          AstNodeDType* const dtp = new AstIfaceRefDType{$<fl>2, $<fl>4, "", *$2, *$4};
+                          VARDTYPE(dtp);
+                          addNextNull($$, VARDONEP($$, $6, $7)); }
         |       portDirNetE yINTERFACE                           portSig rangeListE sigAttrListE
                         { $$ = nullptr; BBUNSUP($<fl>2, "Unsupported: generic interfaces"); }
         |       portDirNetE yINTERFACE      '.' idAny/*modport*/ portSig rangeListE sigAttrListE
@@ -1468,29 +1472,37 @@ port<nodep>:                    // ==IEEE: port
         //UNSUP         { UNSUP }
         //
         |       portDirNetE data_type           portSig variable_dimensionListE sigAttrListE
-                        { $$=$3; VARDTYPE($2); addNextNull($$, VARDONEP($$,$4,$5)); }
+                        { $$ = $3; VARDTYPE($2); addNextNull($$, VARDONEP($$, $4, $5)); }
         |       portDirNetE yVAR data_type      portSig variable_dimensionListE sigAttrListE
-                        { $$=$4; VARDTYPE($3); addNextNull($$, VARDONEP($$,$5,$6)); }
+                        { $$ = $4; VARDTYPE($3); addNextNull($$, VARDONEP($$, $5, $6)); }
         |       portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE
-                        { $$=$4; VARDTYPE($3); addNextNull($$, VARDONEP($$,$5,$6)); }
+                        { $$ = $4; VARDTYPE($3); addNextNull($$, VARDONEP($$, $5, $6)); }
         |       portDirNetE signing             portSig variable_dimensionListE sigAttrListE
-                        { $$=$3; VARDTYPE_NDECL(new AstBasicDType($3->fileline(), LOGIC_IMPLICIT, $2));
+                        { $$ = $3;
+                          AstNodeDType* const dtp = new AstBasicDType{$3->fileline(), LOGIC_IMPLICIT, $2};
+                          VARDTYPE_NDECL(dtp);
                           addNextNull($$, VARDONEP($$, $4, $5)); }
         |       portDirNetE signingE rangeList  portSig variable_dimensionListE sigAttrListE
-                        { $$=$4; VARDTYPE_NDECL(GRAMMARP->addRange(
-                                    new AstBasicDType{$3->fileline(), LOGIC_IMPLICIT, $2}, $3, true));
+                        { $$ = $4;
+                          AstNodeDType* const dtp = GRAMMARP->addRange(
+                                    new AstBasicDType{$3->fileline(), LOGIC_IMPLICIT, $2}, $3, true);
+                          VARDTYPE_NDECL(dtp);
                           addNextNull($$, VARDONEP($$, $5, $6)); }
         |       portDirNetE /*implicit*/        portSig variable_dimensionListE sigAttrListE
-                        { $$=$2; /*VARDTYPE-same*/ addNextNull($$, VARDONEP($$,$3,$4)); }
+                        { $$ = $2; /*VARDTYPE-same*/ addNextNull($$, VARDONEP($$, $3, $4)); }
         //
         |       portDirNetE data_type           portSig variable_dimensionListE sigAttrListE '=' constExpr
-                        { $$=$3; VARDTYPE($2); if (AstVar* vp = VARDONEP($$, $4, $5)) { addNextNull($$, vp); vp->valuep($7); } }
+                        { $$ = $3; VARDTYPE($2);
+                          if (AstVar* vp = VARDONEP($$, $4, $5)) { addNextNull($$, vp); vp->valuep($7); } }
         |       portDirNetE yVAR data_type      portSig variable_dimensionListE sigAttrListE '=' constExpr
-                        { $$=$4; VARDTYPE($3); if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
+                        { $$ = $4; VARDTYPE($3);
+                          if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
         |       portDirNetE yVAR implicit_typeE portSig variable_dimensionListE sigAttrListE '=' constExpr
-                        { $$=$4; VARDTYPE($3); if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
+                        { $$ = $4; VARDTYPE($3);
+                          if (AstVar* vp = VARDONEP($$, $5, $6)) { addNextNull($$, vp); vp->valuep($8); } }
         |       portDirNetE /*implicit*/        portSig variable_dimensionListE sigAttrListE '=' constExpr
-                        { $$=$2; /*VARDTYPE-same*/ if (AstVar* vp = VARDONEP($$, $3, $4)) { addNextNull($$, vp); vp->valuep($6); } }
+                        { $$ = $2; /*VARDTYPE-same*/
+                          if (AstVar* vp = VARDONEP($$, $3, $4)) { addNextNull($$, vp); vp->valuep($6); } }
         ;
 
 portDirNetE:                    // IEEE: part of port, optional net type and/or direction
@@ -1615,7 +1627,7 @@ program_declaration:            // IEEE: program_declaration + program_nonansi_h
                           if ($5) $1->addStmtsp($5);
                           GRAMMARP->m_modp = nullptr;
                           SYMP->popScope($1);
-                          GRAMMARP->endLabel($<fl>7,$1,$7); }
+                          GRAMMARP->endLabel($<fl>7, $1, $7); }
         |       yEXTERN pgmFront parameter_port_listE portsStarE ';'
                         { BBUNSUP($<fl>1, "Unsupported: extern program");
                           SYMP->popScope($2); }
@@ -1688,7 +1700,7 @@ modport_itemList<nodep>:                // IEEE: part of modport_declaration
 modport_item<nodep>:                    // ==IEEE: modport_item
                 id/*new-modport*/ '('
         /*mid*/         { VARRESET_NONLIST(UNKNOWN); VARIO(INOUT); }
-        /*cont*/    modportPortsDeclList ')'            { $$ = new AstModport($<fl>1, *$1, $4); }
+        /*cont*/    modportPortsDeclList ')'            { $$ = new AstModport{$<fl>1, *$1, $4}; }
         ;
 
 modportPortsDeclList<nodep>:
@@ -1702,22 +1714,22 @@ modportPortsDeclList<nodep>:
 // We track the type as with the V2k series of defines, then create as each ID is seen.
 modportPortsDecl<nodep>:
         //                      // IEEE: modport_simple_ports_declaration
-                port_direction modportSimplePort        { $$ = new AstModportVarRef($<fl>2, *$2, GRAMMARP->m_varIO); }
+                port_direction modportSimplePort        { $$ = new AstModportVarRef{$<fl>2, *$2, GRAMMARP->m_varIO}; }
         //                      // IEEE: modport_clocking_declaration
         |       yCLOCKING idAny/*clocking_identifier*/
                         { $$ = nullptr; BBUNSUP($<fl>1, "Unsupported: Modport clocking"); }
         //                      // IEEE: yIMPORT modport_tf_port
         //                      // IEEE: yEXPORT modport_tf_port
         //                      // modport_tf_port expanded here
-        |       yIMPORT id/*tf_identifier*/             { $$ = new AstModportFTaskRef($<fl>2, *$2, false); }
-        |       yEXPORT id/*tf_identifier*/             { $$ = new AstModportFTaskRef($<fl>2, *$2, true); }
+        |       yIMPORT id/*tf_identifier*/             { $$ = new AstModportFTaskRef{$<fl>2, *$2, false}; }
+        |       yEXPORT id/*tf_identifier*/             { $$ = new AstModportFTaskRef{$<fl>2, *$2, true}; }
         |       yIMPORT method_prototype
                         { $$ = nullptr; BBUNSUP($<fl>1, "Unsupported: Modport import with prototype"); }
         |       yEXPORT method_prototype
                         { $$ = nullptr; BBUNSUP($<fl>1, "Unsupported: Modport export with prototype"); }
         // Continuations of above after a comma.
         //                      // IEEE: modport_simple_ports_declaration
-        |       modportSimplePort                       { $$ = new AstModportVarRef($<fl>1,*$1,GRAMMARP->m_varIO); }
+        |       modportSimplePort                       { $$ = new AstModportVarRef{$<fl>1, *$1, GRAMMARP->m_varIO}; }
         ;
 
 modportSimplePort<strp>:        // IEEE: modport_simple_port or modport_tf_port, depending what keyword was earlier
@@ -1741,7 +1753,8 @@ list_of_genvar_identifiers<nodep>:      // IEEE: list_of_genvar_identifiers (for
 genvar_identifierDecl<varp>:            // IEEE: genvar_identifier (for declaration)
                 id/*new-genvar_identifier*/ sigAttrListE
                         { VARRESET_NONLIST(GENVAR);
-                          VARDTYPE(new AstBasicDType($<fl>1, VBasicDTypeKwd::INTEGER));
+                          AstNodeDType* const dtp = new AstBasicDType{$<fl>1, VBasicDTypeKwd::INTEGER};
+                          VARDTYPE(dtp);
                           $$ = VARDONEA($<fl>1, *$1, nullptr, $2); }
         ;
 
@@ -1763,7 +1776,7 @@ parameter_declarationFront:     // IEEE: local_ or parameter_declaration w/o ass
 
 parameter_declarationTypeFront: // IEEE: local_ or parameter_declaration w/o assignment
         //                      // Front must execute first so VARDTYPE is ready before list of vars
-                varParamReset yTYPE                     { /*VARRESET-in-varParam*/ VARDTYPE(new AstParseTypeDType($2)); }
+                varParamReset yTYPE                     { /*VARRESET-in-varParam*/ VARDTYPE(new AstParseTypeDType{$2}); }
         ;
 
 parameter_port_declarationFrontE: // IEEE: local_ or parameter_port_declaration w/o assignment
@@ -1780,8 +1793,8 @@ parameter_port_declarationTypeFrontE: // IEEE: parameter_port_declaration w/o as
         //                      // IEEE: parameter_declaration (minus assignment)
         //                      // IEEE: local_parameter_declaration (minus assignment)
         //                      // Front must execute first so VARDTYPE is ready before list of vars
-                varParamReset yTYPE                     { /*VARRESET-in-varParam*/ VARDTYPE(new AstParseTypeDType($2)); }
-        |       yTYPE                                   { /*VARRESET-in-varParam*/ VARDTYPE(new AstParseTypeDType($1)); }
+                varParamReset yTYPE                     { /*VARRESET-in-varParam*/ VARDTYPE(new AstParseTypeDType{$2}); }
+        |       yTYPE                                   { /*VARRESET-in-varParam*/ VARDTYPE(new AstParseTypeDType{$1}); }
         ;
 
 net_declaration<nodep>:         // IEEE: net_declaration - excluding implict
@@ -1885,10 +1898,13 @@ port_declaration<nodep>:        // ==IEEE: port_declaration
         /*mid*/         { VARDTYPE($4); }
         /*cont*/    list_of_variable_decl_assignments                   { $$ = $6; }
         |       port_directionReset port_declNetE signingE rangeList
-        /*mid*/         { VARDTYPE_NDECL(GRAMMARP->addRange(new AstBasicDType($4->fileline(), LOGIC_IMPLICIT, $3), $4, true)); }
+        /*mid*/         { AstNodeDType* const dtp = GRAMMARP->addRange(
+                              new AstBasicDType{$4->fileline(), LOGIC_IMPLICIT, $3}, $4, true);
+                          VARDTYPE_NDECL(dtp); }
         /*cont*/    list_of_variable_decl_assignments                   { $$ = $6; }
         |       port_directionReset port_declNetE signing
-        /*mid*/         { VARDTYPE_NDECL(new AstBasicDType($<fl>3, LOGIC_IMPLICIT, $3)); }
+        /*mid*/         { AstNodeDType* const dtp = new AstBasicDType{$<fl>3, LOGIC_IMPLICIT, $3};
+                          VARDTYPE_NDECL(dtp); }
         /*cont*/    list_of_variable_decl_assignments                   { $$ = $5; }
         |       port_directionReset port_declNetE /*implicit*/
         /*mid*/         { VARDTYPE_NDECL(nullptr); /*default_nettype*/ }
@@ -1909,24 +1925,24 @@ tf_port_declaration<nodep>:     // ==IEEE: tf_port_declaration
         ;
 
 integer_atom_type<basicDTypep>: // ==IEEE: integer_atom_type
-                yBYTE                                   { $$ = new AstBasicDType($1,VBasicDTypeKwd::BYTE); }
-        |       ySHORTINT                               { $$ = new AstBasicDType($1,VBasicDTypeKwd::SHORTINT); }
-        |       yINT                                    { $$ = new AstBasicDType($1,VBasicDTypeKwd::INT); }
-        |       yLONGINT                                { $$ = new AstBasicDType($1,VBasicDTypeKwd::LONGINT); }
-        |       yINTEGER                                { $$ = new AstBasicDType($1,VBasicDTypeKwd::INTEGER); }
-        |       yTIME                                   { $$ = new AstBasicDType($1,VBasicDTypeKwd::TIME); }
+                yBYTE                                   { $$ = new AstBasicDType{$1, VBasicDTypeKwd::BYTE}; }
+        |       ySHORTINT                               { $$ = new AstBasicDType{$1, VBasicDTypeKwd::SHORTINT}; }
+        |       yINT                                    { $$ = new AstBasicDType{$1, VBasicDTypeKwd::INT}; }
+        |       yLONGINT                                { $$ = new AstBasicDType{$1, VBasicDTypeKwd::LONGINT}; }
+        |       yINTEGER                                { $$ = new AstBasicDType{$1, VBasicDTypeKwd::INTEGER}; }
+        |       yTIME                                   { $$ = new AstBasicDType{$1, VBasicDTypeKwd::TIME}; }
         ;
 
 integer_vector_type<basicDTypep>:       // ==IEEE: integer_atom_type
-                yBIT                                    { $$ = new AstBasicDType($1,VBasicDTypeKwd::BIT); }
-        |       yLOGIC                                  { $$ = new AstBasicDType($1,VBasicDTypeKwd::LOGIC); }
-        |       yREG                                    { $$ = new AstBasicDType($1,VBasicDTypeKwd::LOGIC); } // logic==reg
+                yBIT                                    { $$ = new AstBasicDType{$1, VBasicDTypeKwd::BIT}; }
+        |       yLOGIC                                  { $$ = new AstBasicDType{$1, VBasicDTypeKwd::LOGIC}; }
+        |       yREG                                    { $$ = new AstBasicDType{$1, VBasicDTypeKwd::LOGIC}; } // logic==reg
         ;
 
 non_integer_type<basicDTypep>:  // ==IEEE: non_integer_type
-                yREAL                                   { $$ = new AstBasicDType($1,VBasicDTypeKwd::DOUBLE); }
-        |       yREALTIME                               { $$ = new AstBasicDType($1,VBasicDTypeKwd::DOUBLE); }
-        |       ySHORTREAL                              { $$ = new AstBasicDType($1,VBasicDTypeKwd::DOUBLE); UNSUPREAL($1); }
+                yREAL                                   { $$ = new AstBasicDType{$1, VBasicDTypeKwd::DOUBLE}; }
+        |       yREALTIME                               { $$ = new AstBasicDType{$1, VBasicDTypeKwd::DOUBLE}; }
+        |       ySHORTREAL                              { $$ = new AstBasicDType{$1, VBasicDTypeKwd::DOUBLE}; UNSUPREAL($1); }
         ;
 
 signingE<signstate>:            // IEEE: signing - plus empty
@@ -1978,7 +1994,7 @@ data_type<nodeDTypep>:          // ==IEEE: data_type
         ;
 
 data_typeBasic<nodeDTypep>:             // IEEE: part of data_type
-                integer_vector_type signingE rangeListE { $1->setSignedState($2); $$ = GRAMMARP->addRange($1,$3,true); }
+                integer_vector_type signingE rangeListE { $1->setSignedState($2); $$ = GRAMMARP->addRange($1, $3, true); }
         |       integer_atom_type signingE              { $1->setSignedState($2); $$ = $1; }
         |       non_integer_type                        { $$ = $1; }
         ;
@@ -2034,17 +2050,17 @@ var_data_type<nodeDTypep>:              // ==IEEE: var_data_type
 
 type_reference<nodeDTypep>:     // ==IEEE: type_reference
                 yTYPE '(' exprOrDataType ')'
-                        { $$ = new AstRefDType($1, AstRefDType::FlagTypeOfExpr(), $3); }
+                        { $$ = new AstRefDType{$1, AstRefDType::FlagTypeOfExpr{}, $3}; }
         ;
 
 struct_unionDecl<nodeUOrStructDTypep>:  // IEEE: part of data_type
         //                      // packedSigningE is NOP for unpacked
                 ySTRUCT        packedSigningE '{'
-        /*mid*/         { $<nodeUOrStructDTypep>$ = new AstStructDType($1, $2); SYMP->pushNew($<nodeUOrStructDTypep>$); }
+        /*mid*/         { $<nodeUOrStructDTypep>$ = new AstStructDType{$1, $2}; SYMP->pushNew($<nodeUOrStructDTypep>$); }
         /*cont*/    struct_union_memberList '}'
                         { $$ = $<nodeUOrStructDTypep>4; $$->addMembersp($5); SYMP->popScope($$); }
         |       yUNION taggedE packedSigningE '{'
-        /*mid*/         { $<nodeUOrStructDTypep>$ = new AstUnionDType($1, $3); SYMP->pushNew($<nodeUOrStructDTypep>$); }
+        /*mid*/         { $<nodeUOrStructDTypep>$ = new AstUnionDType{$1, $3}; SYMP->pushNew($<nodeUOrStructDTypep>$); }
         /*cont*/    struct_union_memberList '}'
                         { $$ = $<nodeUOrStructDTypep>5; $$->addMembersp($6); SYMP->popScope($$); }
         ;
@@ -2064,7 +2080,7 @@ struct_union_member<memberDTypep>:     // ==IEEE: struct_union_member
         ;
 
 list_of_member_decl_assignments<memberDTypep>: // Derived from IEEE: list_of_variable_decl_assignments
-                member_decl_assignment          { $$ = $1; }
+                member_decl_assignment                  { $$ = $1; }
         |       list_of_member_decl_assignments ',' member_decl_assignment      { $$ = addNextNull($1, $3); }
         ;
 
@@ -2074,8 +2090,8 @@ member_decl_assignment<memberDTypep>:   // Derived from IEEE: variable_decl_assi
                 id variable_dimensionListE
                         { if ($2) $2->v3warn(UNPACKED, "Unsupported: Unpacked array in packed struct/union"
                                                        " (struct/union converted to unpacked)");
-                          $$ = new AstMemberDType($<fl>1, *$1, VFlagChildDType(),
-                                                  AstNodeDType::cloneTreeNull(GRAMMARP->m_memDTypep, true));
+                          $$ = new AstMemberDType{$<fl>1, *$1, VFlagChildDType{},
+                                                  AstNodeDType::cloneTreeNull(GRAMMARP->m_memDTypep, true)};
                           PARSEP->tagNodep($$);
                           }
         |       id variable_dimensionListE '=' variable_declExpr
@@ -2103,9 +2119,9 @@ list_of_variable_decl_assignments<varp>:        // ==IEEE: list_of_variable_decl
 
 variable_decl_assignment<varp>: // ==IEEE: variable_decl_assignment
                 id variable_dimensionListE sigAttrListE
-                        { $$ = VARDONEA($<fl>1,*$1,$2,$3); }
+                        { $$ = VARDONEA($<fl>1, *$1, $2, $3); }
         |       id variable_dimensionListE sigAttrListE '=' variable_declExpr
-                        { $$ = VARDONEA($<fl>1,*$1,$2,$3); $$->valuep($5); }
+                        { $$ = VARDONEA($<fl>1, *$1, $2, $3); $$->valuep($5); }
         |       idSVKwd                                 { $$ = nullptr; }
         //
         //                      // IEEE: "dynamic_array_variable_identifier '[' ']' [ '=' dynamic_array_new ]"
@@ -2128,7 +2144,8 @@ list_of_tf_variable_identifiers<nodep>: // ==IEEE: list_of_tf_variable_identifie
 tf_variable_identifier<varp>:           // IEEE: part of list_of_tf_variable_identifiers
                 id variable_dimensionListE sigAttrListE exprEqE
                         { $$ = VARDONEA($<fl>1,*$1, $2, $3);
-                          if ($4) AstNode::addNext<AstNode, AstNode>($$, new AstAssign($4->fileline(), new AstVarRef($<fl>1, *$1, VAccess::WRITE), $4)); }
+                          if ($4) AstNode::addNext<AstNode, AstNode>(
+                                      $$, new AstAssign{$4->fileline(), new AstVarRef{$<fl>1, *$1, VAccess::WRITE}, $4}); }
         ;
 
 variable_declExpr<nodep>:               // IEEE: part of variable_decl_assignment - rhs of expr
@@ -2149,13 +2166,13 @@ variable_dimensionList<nodeRangep>:     // IEEE: variable_dimension + empty
 
 variable_dimension<nodeRangep>: // ==IEEE: variable_dimension
         //                      // IEEE: unsized_dimension
-                '[' ']'                                 { $$ = new AstUnsizedRange($1); }
+                '[' ']'                                 { $$ = new AstUnsizedRange{$1}; }
         //                      // IEEE: unpacked_dimension
         |       anyrange                                { $$ = $1; }
         //                      // IEEE: unpacked_dimension (if const_expr)
         //                      // IEEE: associative_dimension (if data_type)
         //                      // Can't tell which until see if expr is data type or not
-        |       '[' exprOrDataType ']'                  { $$ = new AstBracketRange($1, $2); }
+        |       '[' exprOrDataType ']'                  { $$ = new AstBracketRange{$1, $2}; }
         |       yP_BRASTAR ']'                          { $$ = new AstWildcardRange{$1}; }
         |       '[' '*' ']'                             { $$ = new AstWildcardRange{$1}; }
         //                      // IEEE: queue_dimension
@@ -2195,7 +2212,7 @@ enumDecl<nodeDTypep>:
 
 enum_base_typeE<nodeDTypep>:    // IEEE: enum_base_type
                 /* empty */
-                        { $$ = new AstBasicDType(CRELINE(), VBasicDTypeKwd::INT); }
+                        { $$ = new AstBasicDType{CRELINE(), VBasicDTypeKwd::INT}; }
         //                      // Not in spec, but obviously "enum [1:0]" should work
         //                      // implicit_type expanded, without empty
         //                      // Note enum base types are always packed data types
@@ -2213,9 +2230,9 @@ enum_base_typeE<nodeDTypep>:    // IEEE: enum_base_type
         //                      // IEEE: type_identifier [ packed_dimension ]
         //                      // however other simulators allow [ class_scope | package_scope ] type_identifier
         |       idAny rangeListE
-                        { $$ = GRAMMARP->createArray(new AstRefDType($<fl>1, *$1), $2, true); }
+                        { $$ = GRAMMARP->createArray(new AstRefDType{$<fl>1, *$1}, $2, true); }
         |       packageClassScope idAny rangeListE
-                        { AstRefDType* refp = new AstRefDType($<fl>2, *$2, $1, nullptr);
+                        { AstRefDType* refp = new AstRefDType{$<fl>2, *$2, $1, nullptr};
                           $$ = GRAMMARP->createArray(refp, $3, true); }
         ;
 
@@ -2226,14 +2243,14 @@ enum_nameList<enumItemp>:
 
 enum_name_declaration<enumItemp>:   // ==IEEE: enum_name_declaration
                 idAny/*enum_identifier*/ enumNameRangeE enumNameStartE
-                        { $$ = new AstEnumItem($<fl>1, *$1, $2, $3); }
+                        { $$ = new AstEnumItem{$<fl>1, *$1, $2, $3}; }
         ;
 
 enumNameRangeE<rangep>:          // IEEE: second part of enum_name_declaration
                 /* empty */
                         { $$ = nullptr; }
         |       '[' intnumAsConst ']'
-                        { $$ = new AstRange{$1, new AstConst($1, 0), new AstConst($1, $2->toSInt() - 1)}; }
+                        { $$ = new AstRange{$1, new AstConst{$1, 0}, new AstConst($1, $2->toSInt() - 1)}; }
         |       '[' intnumAsConst ':' intnumAsConst ']'
                         { $$ = new AstRange{$1, $2, $4}; }
         ;
@@ -2296,29 +2313,39 @@ data_declarationVarFront:       // IEEE: part of data_declaration
                         { VARRESET_NONLIST(VAR); VARLIFE($2); VARDTYPE($3); }
         |       yVAR lifetimeE
                         { VARRESET_NONLIST(VAR); VARLIFE($2);
-                          VARDTYPE(new AstBasicDType($<fl>1, LOGIC_IMPLICIT)); }
+                          AstNodeDType* const dtp = new AstBasicDType{$<fl>1, LOGIC_IMPLICIT};
+                          VARDTYPE(dtp); }
         |       yVAR lifetimeE signingE rangeList
                         { /*VARRESET-in-ddVar*/ VARLIFE($2);
-                          VARDTYPE(GRAMMARP->addRange(new AstBasicDType($<fl>1, LOGIC_IMPLICIT, $3), $4,true)); }
+                          AstNodeDType* const dtp = GRAMMARP->addRange(
+                              new AstBasicDType{$<fl>1, LOGIC_IMPLICIT, $3}, $4, true);
+                          VARDTYPE(dtp); }
         //
         //                      // implicit_type expanded into /*empty*/ or "signingE rangeList"
         |       yCONST__ETC yVAR lifetimeE data_type
                         { VARRESET_NONLIST(VAR); VARLIFE($3);
-                          VARDTYPE(new AstConstDType($<fl>2, VFlagChildDType(), $4)); }
+                          AstNodeDType* const dtp = new AstConstDType{$<fl>2, VFlagChildDType{}, $4};
+                          VARDTYPE(dtp); }
         |       yCONST__ETC yVAR lifetimeE
                         { VARRESET_NONLIST(VAR); VARLIFE($3);
-                          VARDTYPE(new AstConstDType($<fl>2, VFlagChildDType(), new AstBasicDType($<fl>2, LOGIC_IMPLICIT))); }
+                          AstNodeDType* const dtp = new AstConstDType{$<fl>2, VFlagChildDType{},
+                                                          new AstBasicDType{$<fl>2, LOGIC_IMPLICIT}};
+                          VARDTYPE(dtp); }
         |       yCONST__ETC yVAR lifetimeE signingE rangeList
                         { VARRESET_NONLIST(VAR); VARLIFE($3);
-                         VARDTYPE(new AstConstDType($<fl>2, VFlagChildDType(),
-                                  GRAMMARP->addRange(new AstBasicDType($<fl>2, LOGIC_IMPLICIT, $4), $5,true))); }
+                          AstNodeDType* const dtp = new AstConstDType{$<fl>2, VFlagChildDType{},
+                                  GRAMMARP->addRange(new AstBasicDType{$<fl>2, LOGIC_IMPLICIT, $4}, $5, true)};
+                          VARDTYPE(dtp); }
         //
         //                      // Expanded: "constE lifetimeE data_type"
-        |       /**/                  data_type         { VARRESET_NONLIST(VAR); VARDTYPE($1); }
-        |       /**/        lifetime  data_type         { VARRESET_NONLIST(VAR); VARLIFE($1); VARDTYPE($2); }
+        |       /**/                  data_type
+                        { VARRESET_NONLIST(VAR); VARDTYPE($1); }
+        |       /**/        lifetime  data_type
+                        { VARRESET_NONLIST(VAR); VARLIFE($1); VARDTYPE($2); }
         |       yCONST__ETC lifetimeE data_type
                         { VARRESET_NONLIST(VAR); VARLIFE($2);
-                          VARDTYPE(new AstConstDType($<fl>1, VFlagChildDType(), $3)); }
+                          AstNodeDType* const dtp = new AstConstDType{$<fl>1, VFlagChildDType{}, $3};
+                          VARDTYPE(dtp); }
         //                      // = class_new is in variable_decl_assignment
         ;
 
@@ -2330,7 +2357,8 @@ data_declarationVarFrontClass:  // IEEE: part of data_declaration (for class_pro
         |       yVAR lifetimeE                  { VARRESET_NONLIST(VAR); VARLIFE($2); }
         |       yVAR lifetimeE signingE rangeList
                         { /*VARRESET-in-ddVar*/
-                          VARDTYPE(GRAMMARP->addRange(new AstBasicDType{$<fl>1, LOGIC_IMPLICIT, $3}, $4, true));
+                          AstNodeDType* const dtp = GRAMMARP->addRange(new AstBasicDType{$<fl>1, LOGIC_IMPLICIT, $3}, $4, true);
+                          VARDTYPE(dtp);
                           VARLIFE($2); }
         //
         //                      // Expanded: "constE lifetimeE data_type"
@@ -2366,27 +2394,27 @@ type_declaration<nodep>:        // ==IEEE: type_declaration
                                 // Data_type expanded
                 yTYPEDEF data_typeNoRef
         /*cont*/    idAny variable_dimensionListE dtypeAttrListE ';'
-                        { AstNodeDType* dtp = $2;
+                        { AstNodeDType* const dtp = $2;
                           $$ = GRAMMARP->createTypedef($<fl>3, *$3, $5, dtp, $4); }
         |       yTYPEDEF packageClassScope idType packed_dimensionListE
         /*cont*/    idAny variable_dimensionListE dtypeAttrListE ';'
-                        { AstRefDType* refp = new AstRefDType($<fl>3, *$3, $2, nullptr);
-                          AstNodeDType* dtp = GRAMMARP->createArray(refp, $4, true);
+                        { AstRefDType* const refp = new AstRefDType{$<fl>3, *$3, $2, nullptr};
+                          AstNodeDType* const dtp = GRAMMARP->createArray(refp, $4, true);
                           $$ = GRAMMARP->createTypedef($<fl>5, *$5, $7, dtp, $6); }
         |       yTYPEDEF packageClassScope idType parameter_value_assignmentClass packed_dimensionListE
         /*cont*/    idAny variable_dimensionListE dtypeAttrListE ';'
-                        { AstRefDType* refp = new AstRefDType($<fl>3, *$3, $2, $4);
-                          AstNodeDType* dtp = GRAMMARP->createArray(refp, $5, true);
+                        { AstRefDType* const refp = new AstRefDType{$<fl>3, *$3, $2, $4};
+                          AstNodeDType* const dtp = GRAMMARP->createArray(refp, $5, true);
                           $$ = GRAMMARP->createTypedef($<fl>6, *$6, $8, dtp, $7); }
         |       yTYPEDEF idType packed_dimensionListE
         /*cont*/    idAny variable_dimensionListE dtypeAttrListE ';'
-                        { AstRefDType* refp = new AstRefDType($<fl>2, *$2, nullptr, nullptr);
-                          AstNodeDType* dtp = GRAMMARP->createArray(refp, $3, true);
+                        { AstRefDType* const refp = new AstRefDType{$<fl>2, *$2, nullptr, nullptr};
+                          AstNodeDType* const dtp = GRAMMARP->createArray(refp, $3, true);
                           $$ = GRAMMARP->createTypedef($<fl>4, *$4, $6, dtp, $5); }
         |       yTYPEDEF idType parameter_value_assignmentClass packed_dimensionListE
         /*cont*/    idAny variable_dimensionListE dtypeAttrListE ';'
-                        { AstRefDType* refp = new AstRefDType($<fl>2, *$2, nullptr, $3);
-                          AstNodeDType* dtp = GRAMMARP->createArray(refp, $4, true);
+                        { AstRefDType* const refp = new AstRefDType{$<fl>2, *$2, nullptr, $3};
+                          AstNodeDType* const dtp = GRAMMARP->createArray(refp, $4, true);
                           $$ = GRAMMARP->createTypedef($<fl>5, *$5, $7, dtp, $6); }
         //                      //
         |       yTYPEDEF id/*interface*/ '.' idAny/*type*/ idAny/*type*/ dtypeAttrListE ';'
@@ -2416,7 +2444,7 @@ dtypeAttrList<nodep>:
         ;
 
 dtypeAttr<nodep>:
-                yVL_PUBLIC                              { $$ = new AstAttrOf($1,VAttrType::DT_PUBLIC); }
+                yVL_PUBLIC                              { $$ = new AstAttrOf{$1, VAttrType::DT_PUBLIC}; }
         ;
 
 vlTag:                          // verilator tag handling
@@ -2456,16 +2484,16 @@ non_port_module_item<nodep>:    // ==IEEE: non_port_module_item
                         { $$ = nullptr; BBUNSUP(CRELINE(), "Unsupported: interface decls within module decls"); }
         |       timeunits_declaration                   { $$ = $1; }
         //                      // Verilator specific
-        |       yaSCHDR                                 { $$ = new AstScHdr($<fl>1,*$1); v3Global.setHasSCTextSections(); }
-        |       yaSCINT                                 { $$ = new AstScInt($<fl>1,*$1); v3Global.setHasSCTextSections(); }
-        |       yaSCIMP                                 { $$ = new AstScImp($<fl>1,*$1); v3Global.setHasSCTextSections(); }
-        |       yaSCIMPH                                { $$ = new AstScImpHdr($<fl>1,*$1); v3Global.setHasSCTextSections(); }
-        |       yaSCCTOR                                { $$ = new AstScCtor($<fl>1,*$1); v3Global.setHasSCTextSections(); }
-        |       yaSCDTOR                                { $$ = new AstScDtor($<fl>1,*$1); v3Global.setHasSCTextSections(); }
-        |       yVL_HIER_BLOCK                          { $$ = new AstPragma($1,VPragmaType::HIER_BLOCK); }
-        |       yVL_INLINE_MODULE                       { $$ = new AstPragma($1,VPragmaType::INLINE_MODULE); }
-        |       yVL_NO_INLINE_MODULE                    { $$ = new AstPragma($1,VPragmaType::NO_INLINE_MODULE); }
-        |       yVL_PUBLIC_MODULE                       { $$ = new AstPragma($1,VPragmaType::PUBLIC_MODULE); v3Global.dpi(true); }
+        |       yaSCHDR                                 { $$ = new AstScHdr{$<fl>1, *$1}; v3Global.setHasSCTextSections(); }
+        |       yaSCINT                                 { $$ = new AstScInt{$<fl>1, *$1}; v3Global.setHasSCTextSections(); }
+        |       yaSCIMP                                 { $$ = new AstScImp{$<fl>1, *$1}; v3Global.setHasSCTextSections(); }
+        |       yaSCIMPH                                { $$ = new AstScImpHdr{$<fl>1, *$1}; v3Global.setHasSCTextSections(); }
+        |       yaSCCTOR                                { $$ = new AstScCtor{$<fl>1, *$1}; v3Global.setHasSCTextSections(); }
+        |       yaSCDTOR                                { $$ = new AstScDtor{$<fl>1, *$1}; v3Global.setHasSCTextSections(); }
+        |       yVL_HIER_BLOCK                          { $$ = new AstPragma{$1, VPragmaType::HIER_BLOCK}; }
+        |       yVL_INLINE_MODULE                       { $$ = new AstPragma{$1, VPragmaType::INLINE_MODULE}; }
+        |       yVL_NO_INLINE_MODULE                    { $$ = new AstPragma{$1, VPragmaType::NO_INLINE_MODULE}; }
+        |       yVL_PUBLIC_MODULE                       { $$ = new AstPragma{$1, VPragmaType::PUBLIC_MODULE}; v3Global.dpi(true); }
         ;
 
 module_or_generate_item<nodep>: // ==IEEE: module_or_generate_item
@@ -2496,10 +2524,10 @@ module_common_item<nodep>:      // ==IEEE: module_common_item
         |       final_construct                         { $$ = $1; }
         //                      // IEEE: always_construct
         //                      // Verilator only - event_control attached to always
-        |       yALWAYS       stmtBlock                 { $$ = new AstAlways($1,VAlwaysKwd::ALWAYS, nullptr, $2); }
-        |       yALWAYS_FF    stmtBlock                 { $$ = new AstAlways($1,VAlwaysKwd::ALWAYS_FF, nullptr, $2); }
-        |       yALWAYS_LATCH stmtBlock                 { $$ = new AstAlways($1,VAlwaysKwd::ALWAYS_LATCH, nullptr, $2); }
-        |       yALWAYS_COMB  stmtBlock                 { $$ = new AstAlways($1,VAlwaysKwd::ALWAYS_COMB, nullptr, $2); }
+        |       yALWAYS       stmtBlock                 { $$ = new AstAlways{$1, VAlwaysKwd::ALWAYS, nullptr, $2}; }
+        |       yALWAYS_FF    stmtBlock                 { $$ = new AstAlways{$1, VAlwaysKwd::ALWAYS_FF, nullptr, $2}; }
+        |       yALWAYS_LATCH stmtBlock                 { $$ = new AstAlways{$1, VAlwaysKwd::ALWAYS_LATCH, nullptr, $2}; }
+        |       yALWAYS_COMB  stmtBlock                 { $$ = new AstAlways{$1, VAlwaysKwd::ALWAYS_COMB, nullptr, $2}; }
         //
         |       loop_generate_construct                 { $$ = $1; }
         |       conditional_generate_construct          { $$ = $1; }
@@ -2518,11 +2546,11 @@ continuous_assign<nodep>:       // IEEE: continuous_assign
         ;
 
 initial_construct<nodep>:       // IEEE: initial_construct
-                yINITIAL stmtBlock                      { $$ = new AstInitial($1,$2); }
+                yINITIAL stmtBlock                      { $$ = new AstInitial{$1, $2}; }
         ;
 
 final_construct<nodep>:         // IEEE: final_construct
-                yFINAL stmtBlock                        { $$ = new AstFinal($1,$2); }
+                yFINAL stmtBlock                        { $$ = new AstFinal{$1, $2}; }
         ;
 
 module_or_generate_item_declaration<nodep>:     // ==IEEE: module_or_generate_item_declaration
@@ -2544,7 +2572,7 @@ bind_directive<nodep>:          // ==IEEE: bind_directive + bind_target_scope
         //                      // - it's already in module_instantiation
         //                      // We merged the rules - id may be a bind_target_instance or
         //                      // module_identifier or interface_identifier
-                yBIND bind_target_instance bind_instantiation   { $$ = new AstBind($<fl>2, *$2, $3); }
+                yBIND bind_target_instance bind_instantiation   { $$ = new AstBind{$<fl>2, *$2, $3}; }
         |       yBIND bind_target_instance ':' bind_target_instance_list bind_instantiation
                         { $$ = nullptr; BBUNSUP($1, "Unsupported: Bind with instance list"); }
         ;
@@ -2588,20 +2616,24 @@ generate_block_or_null<nodep>:  // IEEE: generate_block_or_null (called from gen
         //      ';'             // is included in
         //                      // IEEE: generate_block
         //                      // Must always return a BEGIN node, or nullptr - see GenFor construction
-                generate_item                           { $$ = $1 ? (new AstBegin($1->fileline(),"",$1,true,true)) : nullptr; }
+                generate_item
+                        { $$ = $1 ? (new AstBegin{$1->fileline(), "", $1, true, true}) : nullptr; }
         |       genItemBegin                            { $$ = $1; }
         ;
 
 genItemBegin<nodep>:            // IEEE: part of generate_block
-                yBEGIN ~c~genItemList yEND              { $$ = new AstBegin($1,"",$2,true,false); }
+                yBEGIN ~c~genItemList yEND              { $$ = new AstBegin{$1, "", $2, true, false}; }
         |       yBEGIN yEND                             { $$ = nullptr; }
         |       id yP_COLON__BEGIN yBEGIN ~c~genItemList yEND endLabelE
-                        { $$ = new AstBegin($<fl>1,*$1,$4,true,false); GRAMMARP->endLabel($<fl>6,*$1,$6); }
+                        { $$ = new AstBegin{$<fl>1, *$1, $4, true, false};
+                          GRAMMARP->endLabel($<fl>6, *$1, $6); }
         |       id yP_COLON__BEGIN yBEGIN yEND endLabelE
-                        { $$ = nullptr; GRAMMARP->endLabel($<fl>5,*$1,$5); }
+                        { $$ = nullptr; GRAMMARP->endLabel($<fl>5, *$1, $5); }
         |       yBEGIN ':' idAny ~c~genItemList yEND endLabelE
-                        { $$ = new AstBegin($<fl>3,*$3,$4,true,false); GRAMMARP->endLabel($<fl>6,*$3,$6); }
-        |       yBEGIN ':' idAny yEND endLabelE         { $$ = nullptr; GRAMMARP->endLabel($<fl>5,*$3,$5); }
+                        { $$ = new AstBegin{$<fl>3, *$3, $4, true, false};
+                          GRAMMARP->endLabel($<fl>6, *$3, $6); }
+        |       yBEGIN ':' idAny yEND endLabelE
+                        { $$ = nullptr; GRAMMARP->endLabel($<fl>5, *$3, $5); }
         ;
 
 //UNSUPc_genItemBegin<nodep>:  // IEEE: part of generate_block (for checkers)
@@ -2642,11 +2674,11 @@ generate_item<nodep>:           // IEEE: module_or_interface_or_generate_item
 
 conditional_generate_construct<nodep>:  // ==IEEE: conditional_generate_construct
                 yCASE  '(' expr ')' ~c~case_generate_itemListE yENDCASE
-                        { $$ = new AstGenCase($1, $3, $5); }
+                        { $$ = new AstGenCase{$1, $3, $5}; }
         |       yIF '(' expr ')' ~c~generate_block_or_null      %prec prLOWER_THAN_ELSE
-                        { $$ = new AstGenIf($1, $3, $5, nullptr); }
+                        { $$ = new AstGenIf{$1, $3, $5, nullptr}; }
         |       yIF '(' expr ')' ~c~generate_block_or_null yELSE ~c~generate_block_or_null
-                        { $$ = new AstGenIf($1, $3, $5, $7); }
+                        { $$ = new AstGenIf{$1, $3, $5, $7}; }
         ;
 
 //UNSUPc_conditional_generate_construct<nodep>:  // IEEE: conditional_generate_construct (for checkers)
@@ -2674,7 +2706,7 @@ loop_generate_construct<nodep>: // ==IEEE: loop_generate_construct
                           }
                           // Statements are under 'genforp' as cells under this
                           // for loop won't get an extra layer of hierarchy tacked on
-                          blkp->genforp(new AstGenFor($1, initp, $5, $7, lowerNoBegp));
+                          blkp->genforp(new AstGenFor{$1, initp, $5, $7, lowerNoBegp});
                           $$ = blkp;
                           VL_DO_DANGLING(lowerBegp->deleteTree(), lowerBegp);
                         }
@@ -2685,9 +2717,10 @@ loop_generate_construct<nodep>: // ==IEEE: loop_generate_construct
 //UNSUP ;
 
 genvar_initialization<nodep>:   // ==IEEE: genvar_initialization
-                varRefBase '=' expr                     { $$ = new AstAssign($2,$1,$3); }
+                varRefBase '=' expr                     { $$ = new AstAssign{$2, $1, $3}; }
         |       yGENVAR genvar_identifierDecl '=' constExpr
-                        { $$ = $2; AstNode::addNext<AstNode, AstNode>($$, new AstAssign($3, new AstVarRef($2->fileline(), $2, VAccess::WRITE), $4)); }
+                        { $$ = $2; AstNode::addNext<AstNode, AstNode>($$,
+                                       new AstAssign{$3, new AstVarRef{$2->fileline(), $2, VAccess::WRITE}, $4}); }
         ;
 
 genvar_iteration<nodep>:        // ==IEEE: genvar_iteration
@@ -2764,13 +2797,13 @@ assignList<nodep>:
         ;
 
 assignOne<nodep>:
-                variable_lvalue '=' expr                { $$ = new AstAssignW($2,$1,$3); }
+                variable_lvalue '=' expr                { $$ = new AstAssignW{$2, $1, $3}; }
         ;
 
 delay_or_event_controlE<nodep>:  // IEEE: delay_or_event_control plus empty
-                /* empty */             { $$ = nullptr; }
-        |        delay_control          { $$ = $1; }
-        |        event_control          { $$ = $1; }
+                /* empty */                             { $$ = nullptr; }
+        |        delay_control                          { $$ = $1; }
+        |        event_control                          { $$ = $1; }
 //UNSUP        |        yREPEAT '(' expr ')' event_control        { }
         ;
 
@@ -2814,14 +2847,14 @@ netSigList<varp>:               // IEEE: list_of_port_identifiers
 
 netSig<varp>:                   // IEEE: net_decl_assignment -  one element from list_of_port_identifiers
                 netId sigAttrListE
-                        { $$ = VARDONEA($<fl>1,*$1, nullptr, $2); }
+                        { $$ = VARDONEA($<fl>1, *$1, nullptr, $2); }
         |       netId sigAttrListE '=' expr
                         { $$ = VARDONEA($<fl>1, *$1, nullptr, $2);
                           auto* const assignp = new AstAssignW{$3, new AstVarRef{$<fl>1, *$1, VAccess::WRITE}, $4};
                           if (GRAMMARP->m_netStrengthp) assignp->strengthSpecp(GRAMMARP->m_netStrengthp->cloneTree(false));
                           AstNode::addNext<AstNode, AstNode>($$, assignp); }
         |       netId variable_dimensionList sigAttrListE
-                        { $$ = VARDONEA($<fl>1,*$1, $2, $3); }
+                        { $$ = VARDONEA($<fl>1, *$1, $2, $3); }
         ;
 
 netId<strp>:
@@ -2840,20 +2873,20 @@ sigAttrList<nodep>:
         ;
 
 sigAttr<nodep>:
-                yVL_CLOCKER                             { $$ = new AstAttrOf($1,VAttrType::VAR_CLOCKER); }
-        |       yVL_NO_CLOCKER                          { $$ = new AstAttrOf($1,VAttrType::VAR_NO_CLOCKER); }
-        |       yVL_CLOCK_ENABLE                        { $$ = new AstAttrOf($1,VAttrType::VAR_CLOCK_ENABLE); }
-        |       yVL_FORCEABLE                           { $$ = new AstAttrOf($1,VAttrType::VAR_FORCEABLE); }
-        |       yVL_PUBLIC                              { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC); v3Global.dpi(true); }
-        |       yVL_PUBLIC_FLAT                         { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC_FLAT); v3Global.dpi(true); }
-        |       yVL_PUBLIC_FLAT_RD                      { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC_FLAT_RD); v3Global.dpi(true); }
-        |       yVL_PUBLIC_FLAT_RW                      { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC_FLAT_RW); v3Global.dpi(true); }
-        |       yVL_PUBLIC_FLAT_RW attr_event_control   { $$ = new AstAttrOf($1,VAttrType::VAR_PUBLIC_FLAT_RW); v3Global.dpi(true);
-                                                          $$ = $$->addNext(new AstAlwaysPublic($1,$2,nullptr)); }
-        |       yVL_ISOLATE_ASSIGNMENTS                 { $$ = new AstAttrOf($1,VAttrType::VAR_ISOLATE_ASSIGNMENTS); }
-        |       yVL_SC_BV                               { $$ = new AstAttrOf($1,VAttrType::VAR_SC_BV); }
-        |       yVL_SFORMAT                             { $$ = new AstAttrOf($1,VAttrType::VAR_SFORMAT); }
-        |       yVL_SPLIT_VAR                           { $$ = new AstAttrOf($1,VAttrType::VAR_SPLIT_VAR); }
+                yVL_CLOCKER                             { $$ = new AstAttrOf{$1, VAttrType::VAR_CLOCKER}; }
+        |       yVL_NO_CLOCKER                          { $$ = new AstAttrOf{$1, VAttrType::VAR_NO_CLOCKER}; }
+        |       yVL_CLOCK_ENABLE                        { $$ = new AstAttrOf{$1, VAttrType::VAR_CLOCK_ENABLE}; }
+        |       yVL_FORCEABLE                           { $$ = new AstAttrOf{$1, VAttrType::VAR_FORCEABLE}; }
+        |       yVL_PUBLIC                              { $$ = new AstAttrOf{$1, VAttrType::VAR_PUBLIC}; v3Global.dpi(true); }
+        |       yVL_PUBLIC_FLAT                         { $$ = new AstAttrOf{$1, VAttrType::VAR_PUBLIC_FLAT}; v3Global.dpi(true); }
+        |       yVL_PUBLIC_FLAT_RD                      { $$ = new AstAttrOf{$1, VAttrType::VAR_PUBLIC_FLAT_RD}; v3Global.dpi(true); }
+        |       yVL_PUBLIC_FLAT_RW                      { $$ = new AstAttrOf{$1, VAttrType::VAR_PUBLIC_FLAT_RW}; v3Global.dpi(true); }
+        |       yVL_PUBLIC_FLAT_RW attr_event_control   { $$ = new AstAttrOf{$1, VAttrType::VAR_PUBLIC_FLAT_RW}; v3Global.dpi(true);
+                                                          $$ = $$->addNext(new AstAlwaysPublic{$1, $2, nullptr}); }
+        |       yVL_ISOLATE_ASSIGNMENTS                 { $$ = new AstAttrOf{$1, VAttrType::VAR_ISOLATE_ASSIGNMENTS}; }
+        |       yVL_SC_BV                               { $$ = new AstAttrOf{$1, VAttrType::VAR_SC_BV}; }
+        |       yVL_SFORMAT                             { $$ = new AstAttrOf{$1, VAttrType::VAR_SFORMAT}; }
+        |       yVL_SPLIT_VAR                           { $$ = new AstAttrOf{$1, VAttrType::VAR_SPLIT_VAR}; }
         ;
 
 rangeListE<nodeRangep>:         // IEEE: [{packed_dimension}]
@@ -2875,7 +2908,7 @@ rangeList<nodeRangep>:          // IEEE: {packed_dimension}
 // Merged into more general idArray
 
 anyrange<nodeRangep>:
-                '[' constExpr ':' constExpr ']'         { $$ = new AstRange($1,$2,$4); }
+                '[' constExpr ':' constExpr ']'         { $$ = new AstRange{$1, $2, $4}; }
         ;
 
 packed_dimensionListE<nodeRangep>:      // IEEE: [{ packed_dimension }]
@@ -2906,7 +2939,7 @@ param_assignment<varp>:         // ==IEEE: param_assignment
                           if (AstNodeDType* const refp = VN_CAST($4, NodeDType)) {
                             if (VSymEnt* const foundp = SYMP->symCurrentp()->findIdFallback(refp->name())) {
                                 UINFO(9, "declaring type via param assignment" << foundp->nodep() << endl);
-                                VARDTYPE(new AstParseTypeDType{$<fl>1})
+                                VARDTYPE(new AstParseTypeDType{$<fl>1});
                                 SYMP->reinsert(foundp->nodep()->cloneTree(false), nullptr, *$1); }}
                           $$ = VARDONEA($<fl>1, *$1, $2, $3);
                           if ($4) $$->valuep($4); }
@@ -2936,7 +2969,7 @@ list_of_defparam_assignments<nodep>:    //== IEEE: list_of_defparam_assignments
         ;
 
 defparam_assignment<nodep>:     // ==IEEE: defparam_assignment
-                idAny '.' idAny '=' expr                { $$ = new AstDefParam($4, *$1, *$3, $5); }
+                idAny '.' idAny '=' expr                { $$ = new AstDefParam{$4, *$1, *$3, $5}; }
         |       idAny '.' idAny '.'
                         { $$ = nullptr; BBUNSUP($4, "Unsupported: defparam with more than one dot"); }
         ;
@@ -2969,9 +3002,10 @@ instDecl<nodep>:
         //                      // IEEE: interface_identifier' .' modport_identifier list_of_interface_identifiers
         |       id/*interface*/ '.' id/*modport*/
         /*mid*/         { VARRESET_NONLIST(VVarType::IFACEREF);
-                          VARDTYPE(new AstIfaceRefDType($<fl>1, $<fl>3, "", *$1, *$3)); }
+                          AstNodeDType* const dtp = new AstIfaceRefDType{$<fl>1, $<fl>3, "", *$1, *$3};
+                          VARDTYPE(dtp); }
         /*cont*/    mpInstnameList ';'
-                        { $$ = VARDONEP($5,nullptr,nullptr); }
+                        { $$ = VARDONEP($5, nullptr, nullptr); }
         //UNSUP: strengthSpecE for udp_instantiations
         ;
 
@@ -2981,7 +3015,7 @@ mpInstnameList<nodep>:          // Similar to instnameList, but for modport inst
         ;
 
 mpInstnameParen<nodep>:         // Similar to instnameParen, but for modport instantiations which have no parenthesis
-                id instRangeListE sigAttrListE          { $$ = VARDONEA($<fl>1,*$1,$2,$3); }
+                id instRangeListE sigAttrListE          { $$ = VARDONEA($<fl>1, *$1, $2, $3); }
         ;
 
 instnameList<nodep>:
@@ -3037,40 +3071,48 @@ cellpinItList<pinp>:            // IEEE: list_of_port_connections
 
 cellparamItemE<pinp>:           // IEEE: named_parameter_assignment + empty
         //                      // Note empty can match either () or (,); V3LinkCells cleans up ()
-                /* empty: ',,' is legal */              { $$ = new AstPin(CRELINE(), PINNUMINC(), "", nullptr); }
-        |       yP_DOTSTAR                              { $$ = new AstPin($1,PINNUMINC(),".*",nullptr); }
-        |       '.' idSVKwd                             { $$ = new AstPin($<fl>2,PINNUMINC(), *$2,
-                                                                          new AstParseRef($<fl>2,VParseRefExp::PX_TEXT,*$2,nullptr,nullptr));
-                                                                          $$->svImplicit(true); }
-        |       '.' idAny                               { $$ = new AstPin($<fl>2,PINNUMINC(), *$2,
-                                                                          new AstParseRef($<fl>2,VParseRefExp::PX_TEXT,*$2,nullptr,nullptr));
-                                                                          $$->svImplicit(true); }
-        |       '.' idAny '(' ')'                       { $$ = new AstPin($<fl>2,PINNUMINC(),*$2,nullptr); }
+                /* empty: ',,' is legal */              { $$ = new AstPin{CRELINE(), PINNUMINC(), "", nullptr}; }
+        |       yP_DOTSTAR                              { $$ = new AstPin{$1, PINNUMINC(), ".*", nullptr}; }
+        |       '.' idAny '(' ')'                       { $$ = new AstPin{$<fl>2, PINNUMINC(), *$2, nullptr}; }
+        |       '.' idSVKwd
+                        { $$ = new AstPin{$<fl>2, PINNUMINC(), *$2,
+                                          new AstParseRef{$<fl>2, VParseRefExp::PX_TEXT, *$2, nullptr, nullptr}};
+                          $$->svImplicit(true); }
+        |       '.' idAny
+                        { $$ = new AstPin{$<fl>2, PINNUMINC(), *$2,
+                                          new AstParseRef{$<fl>2, VParseRefExp::PX_TEXT, *$2, nullptr, nullptr}};
+                          $$->svImplicit(true); }
         //                      // mintypmax is expanded here, as it might be a UDP or gate primitive
         //                      // data_type for 'parameter type' hookups
-        |       '.' idAny '(' exprOrDataType ')'        { $$ = new AstPin($<fl>2, PINNUMINC(), *$2, $4); }
+        |       '.' idAny '(' exprOrDataType ')'        { $$ = new AstPin{$<fl>2, PINNUMINC(), *$2, $4}; }
         //UNSUP '.' idAny '(' exprOrDataType/*expr*/ ':' expr ')'               { }
         //UNSUP '.' idAny '(' exprOrDataType/*expr*/ ':' expr ':' expr ')'      { }
         //                      // data_type for 'parameter type' hookups
-        |       exprOrDataType                          { $$ = new AstPin(FILELINE_OR_CRE($1), PINNUMINC(), "", $1); }
+        |       exprOrDataType                          { $$ = new AstPin{FILELINE_OR_CRE($1), PINNUMINC(), "", $1}; }
         //UNSUP exprOrDataType/*expr*/ ':' expr         { }
         //UNSUP exprOrDataType/*expr*/ ':' expr ':' expr        { }
         ;
 
 cellpinItemE<pinp>:             // IEEE: named_port_connection + empty
         //                      // Note empty can match either () or (,); V3LinkCells cleans up ()
-                /* empty: ',,' is legal */              { $$ = new AstPin(CRELINE(), PINNUMINC(), "", nullptr); }
-        |       yP_DOTSTAR                              { $$ = new AstPin($1,PINNUMINC(),".*",nullptr); }
-        |       '.' idSVKwd                             { $$ = new AstPin($<fl>2,PINNUMINC(),*$2,new AstParseRef($<fl>2,VParseRefExp::PX_TEXT,*$2,nullptr,nullptr)); $$->svImplicit(true);}
-        |       '.' idAny                               { $$ = new AstPin($<fl>2,PINNUMINC(),*$2,new AstParseRef($<fl>2,VParseRefExp::PX_TEXT,*$2,nullptr,nullptr)); $$->svImplicit(true);}
-        |       '.' idAny '(' ')'                       { $$ = new AstPin($<fl>2,PINNUMINC(),*$2,nullptr); }
+                /* empty: ',,' is legal */              { $$ = new AstPin{CRELINE(), PINNUMINC(), "", nullptr}; }
+        |       yP_DOTSTAR                              { $$ = new AstPin{$1, PINNUMINC(), ".*", nullptr}; }
+        |       '.' idAny '(' ')'                       { $$ = new AstPin{$<fl>2, PINNUMINC(), *$2, nullptr}; }
+        |       '.' idSVKwd
+                        { $$ = new AstPin{$<fl>2, PINNUMINC(), *$2,
+                                          new AstParseRef{$<fl>2, VParseRefExp::PX_TEXT, *$2, nullptr, nullptr}};
+                          $$->svImplicit(true);}
+        |       '.' idAny
+                        { $$ = new AstPin{$<fl>2, PINNUMINC(), *$2,
+                                          new AstParseRef{$<fl>2, VParseRefExp::PX_TEXT, *$2, nullptr, nullptr}};
+                          $$->svImplicit(true);}
         //                      // mintypmax is expanded here, as it might be a UDP or gate primitive
         //UNSUP               pev_expr below
-        |       '.' idAny '(' expr ')'                  { $$ = new AstPin($<fl>2,PINNUMINC(),*$2,$4); }
+        |       '.' idAny '(' expr ')'                  { $$ = new AstPin{$<fl>2, PINNUMINC(), *$2, $4}; }
         //UNSUP '.' idAny '(' pev_expr ':' expr ')'     { }
         //UNSUP '.' idAny '(' pev_expr ':' expr ':' expr ')' { }
         //
-        |       expr                                    { $$ = new AstPin(FILELINE_OR_CRE($1),PINNUMINC(),"",$1); }
+        |       expr                                    { $$ = new AstPin{FILELINE_OR_CRE($1), PINNUMINC(), "", $1}; }
         //UNSUP expr ':' expr                           { }
         //UNSUP expr ':' expr ':' expr                  { }
         ;
@@ -3079,23 +3121,23 @@ cellpinItemE<pinp>:             // IEEE: named_port_connection + empty
 // EventControl lists
 
 attr_event_controlE<senTreep>:
-                /* empty */                                     { $$ = nullptr; }
+                /* empty */                             { $$ = nullptr; }
         |       attr_event_control                      { $$ = $1; }
         ;
 
 attr_event_control<senTreep>:   // ==IEEE: event_control
-                '@' '(' event_expression ')'            { $$ = new AstSenTree($1,$3); }
+                '@' '(' event_expression ')'            { $$ = new AstSenTree{$1, $3}; }
         |       '@' '(' '*' ')'                         { $$ = nullptr; }
         |       '@' '*'                                 { $$ = nullptr; }
         ;
 
 event_control<senTreep>:        // ==IEEE: event_control
-                '@' '(' event_expression ')'            { $$ = new AstSenTree($1,$3); }
+                '@' '(' event_expression ')'            { $$ = new AstSenTree{$1, $3}; }
         |       '@' '(' '*' ')'                         { $$ = nullptr; }
         |       '@' '*'                                 { $$ = nullptr; }
         //                      // IEEE: hierarchical_event_identifier
         //                      // UNSUP below should be idClassSel
-        |       '@' senitemVar                          { $$ = new AstSenTree($1,$2); } /* For events only */
+        |       '@' senitemVar                          { $$ = new AstSenTree{$1, $2}; } /* For events only */
         //                      // IEEE: sequence_instance
         //                      // sequence_instance without parens matches idClassSel above.
         //                      // Ambiguity: "'@' sequence (-for-sequence" versus
@@ -3128,9 +3170,9 @@ senitemVar<senItemp>:
         ;
 
 senitemEdge<senItemp>:          // IEEE: part of event_expression
-                yPOSEDGE expr                     { $$ = new AstSenItem{$1, VEdgeType::ET_POSEDGE, $2}; }
-        |       yNEGEDGE expr                     { $$ = new AstSenItem{$1, VEdgeType::ET_NEGEDGE, $2}; }
-        |       yEDGE expr                        { $$ = new AstSenItem{$1, VEdgeType::ET_BOTHEDGE, $2}; }
+                yPOSEDGE expr                           { $$ = new AstSenItem{$1, VEdgeType::ET_POSEDGE, $2}; }
+        |       yNEGEDGE expr                           { $$ = new AstSenItem{$1, VEdgeType::ET_NEGEDGE, $2}; }
+        |       yEDGE expr                              { $$ = new AstSenItem{$1, VEdgeType::ET_BOTHEDGE, $2}; }
         //UNSUP yPOSEDGE expr yIFF expr                 { UNSUP }
         //UNSUP yNEGEDGE expr yIFF expr                 { UNSUP }
         //UNSUP yEDGE expr yIFF expr                    { UNSUP }
@@ -3188,23 +3230,27 @@ par_blockPreId<nodep>:          // ==IEEE: par_block but called with leading ID
         ;
 
 seq_blockFront<beginp>:         // IEEE: part of seq_block
-                yBEGIN                                   { $$ = new AstBegin($1,"",nullptr);  SYMP->pushNew($$); }
-        |       yBEGIN ':' idAny/*new-block_identifier*/ { $$ = new AstBegin($<fl>3, *$3, nullptr); SYMP->pushNew($$); }
+                yBEGIN
+                        { $$ = new AstBegin{$1, "", nullptr};  SYMP->pushNew($$); }
+        |       yBEGIN ':' idAny/*new-block_identifier*/
+                        { $$ = new AstBegin{$<fl>3, *$3, nullptr}; SYMP->pushNew($$); }
         ;
 
 par_blockFront<forkp>:          // IEEE: part of par_block
-                yFORK                                   { $$ = new AstFork($1, "", nullptr);  SYMP->pushNew($$); }
-        |       yFORK ':' idAny/*new-block_identifier*/ { $$ = new AstFork($<fl>3, *$3, nullptr); SYMP->pushNew($$); }
+                yFORK
+                        { $$ = new AstFork{$1, "", nullptr};  SYMP->pushNew($$); }
+        |       yFORK ':' idAny/*new-block_identifier*/
+                        { $$ = new AstFork{$<fl>3, *$3, nullptr}; SYMP->pushNew($$); }
         ;
 
 seq_blockFrontPreId<beginp>:    // IEEE: part of seq_block/stmt with leading id
                 id/*block_identifier*/ yP_COLON__BEGIN yBEGIN
-                        { $$ = new AstBegin($3, *$1, nullptr); SYMP->pushNew($$); }
+                        { $$ = new AstBegin{$3, *$1, nullptr}; SYMP->pushNew($$); }
         ;
 
 par_blockFrontPreId<forkp>:     // IEEE: part of par_block/stmt with leading id
                 id/*block_identifier*/ yP_COLON__FORK yFORK
-                        { $$ = new AstFork($3, *$1, nullptr); SYMP->pushNew($$); }
+                        { $$ = new AstFork{$3, *$1, nullptr}; SYMP->pushNew($$); }
         ;
 
 
@@ -3239,7 +3285,7 @@ stmtList<nodep>:
 stmt<nodep>:                    // IEEE: statement_or_null == function_statement_or_null
                 statement_item                          { $$ = $1; }
         //                      // S05 block creation rule
-        |       id/*block_identifier*/ ':' statement_item       { $$ = new AstBegin($<fl>1, *$1, $3); }
+        |       id/*block_identifier*/ ':' statement_item       { $$ = new AstBegin{$<fl>1, *$1, $3}; }
         //                      // from _or_null
         |       ';'                                     { $$ = nullptr; }
         //                      // labeled par_block/seq_block with leading ':'
@@ -3254,8 +3300,8 @@ statement_item<nodep>:          // IEEE: statement_item
         //                      // IEEE: blocking_assignment
         //                      // 1800-2009 restricts LHS of assignment to new to not have a range
         //                      // This is ignored to avoid conflicts
-        |       fexprLvalue '=' class_new ';'           { $$ = new AstAssign($2, $1, $3); }
-        |       fexprLvalue '=' dynamic_array_new ';'   { $$ = new AstAssign($2, $1, $3); }
+        |       fexprLvalue '=' class_new ';'           { $$ = new AstAssign{$2, $1, $3}; }
+        |       fexprLvalue '=' dynamic_array_new ';'   { $$ = new AstAssign{$2, $1, $3}; }
         //
         //                      // IEEE: nonblocking_assignment
         |       fexprLvalue yP_LTE delay_or_event_controlE expr ';'
@@ -3270,10 +3316,11 @@ statement_item<nodep>:          // IEEE: statement_item
                         { $$ = new AstRelease{$1, $2}; v3Global.setHasForceableSignals(); }
         //
         //                      // IEEE: case_statement
-        |       unique_priorityE caseStart caseAttrE case_itemListE yENDCASE    { $$ = $2; if ($4) $2->addItemsp($4);
-                                                          if ($1 == uniq_UNIQUE) $2->uniquePragma(true);
-                                                          if ($1 == uniq_UNIQUE0) $2->unique0Pragma(true);
-                                                          if ($1 == uniq_PRIORITY) $2->priorityPragma(true); }
+        |       unique_priorityE caseStart caseAttrE case_itemListE yENDCASE
+                        { $$ = $2; if ($4) $2->addItemsp($4);
+                          if ($1 == uniq_UNIQUE) $2->uniquePragma(true);
+                          if ($1 == uniq_UNIQUE0) $2->unique0Pragma(true);
+                          if ($1 == uniq_PRIORITY) $2->priorityPragma(true); }
         //UNSUP caseStart caseAttrE yMATCHES case_patternListE yENDCASE { }
         |       unique_priorityE caseStart caseAttrE yINSIDE case_insideListE yENDCASE
                         { $$ = $2; if ($5) $2->addItemsp($5);
@@ -3340,8 +3387,9 @@ statement_item<nodep>:          // IEEE: statement_item
         |       statementVerilatorPragmas               { $$ = $1; }
         //
         //                      // IEEE: disable_statement
-        |       yDISABLE idAny/*hierarchical_identifier-task_or_block*/ ';'     { $$ = new AstDisable($1,*$2); }
-        |       yDISABLE yFORK ';'                      { $$ = new AstDisableFork($1); }
+        |       yDISABLE yFORK ';'                      { $$ = new AstDisableFork{$1}; }
+        |       yDISABLE idAny/*hierarchical_identifier-task_or_block*/ ';'
+                        { $$ = new AstDisable{$1, *$2}; }
         //                      // IEEE: event_trigger
         |       yP_MINUSGT idDotted/*hierarchical_identifier-event*/ ';'
                         { $$ = new AstFireEvent{$1, $2, false}; }
@@ -3349,20 +3397,21 @@ statement_item<nodep>:          // IEEE: statement_item
                         { $$ = new AstFireEvent{$1, $3, true}; }
         //
         //                      // IEEE: loop_statement
-        |       yFOREVER stmtBlock                      { $$ = new AstWhile($1,new AstConst($1, AstConst::BitTrue()), $2); }
+        |       yFOREVER stmtBlock
+                        { $$ = new AstWhile{$1, new AstConst{$1, AstConst::BitTrue{}}, $2}; }
         |       yREPEAT '(' expr ')' stmtBlock          { $$ = new AstRepeat{$1, $3, $5}; }
         |       yWHILE '(' expr ')' stmtBlock           { $$ = new AstWhile{$1, $3, $5}; }
         //                      // for's first ';' is in for_initialization
         |       statementFor                            { $$ = $1; }
         |       yDO stmtBlock yWHILE '(' expr ')' ';'   { $$ = new AstDoWhile{$1, $5, $2}; }
         //                      // IEEE says array_identifier here, but dotted accepted in VMM and 1800-2009
-        |       yFOREACH '(' idClassSelForeach ')' stmtBlock    { $$ = new AstForeach($1, $3, $5); }
+        |       yFOREACH '(' idClassSelForeach ')' stmtBlock    { $$ = new AstForeach{$1, $3, $5}; }
         //
         //                      // IEEE: jump_statement
-        |       yRETURN ';'                             { $$ = new AstReturn($1); }
-        |       yRETURN expr ';'                        { $$ = new AstReturn($1,$2); }
-        |       yBREAK ';'                              { $$ = new AstBreak($1); }
-        |       yCONTINUE ';'                           { $$ = new AstContinue($1); }
+        |       yRETURN ';'                             { $$ = new AstReturn{$1}; }
+        |       yRETURN expr ';'                        { $$ = new AstReturn{$1, $2}; }
+        |       yBREAK ';'                              { $$ = new AstBreak{$1}; }
+        |       yCONTINUE ';'                           { $$ = new AstContinue{$1}; }
         //
         |       par_block                               { $$ = $1; }
         //                      // IEEE: procedural_timing_control_statement + procedural_timing_control
@@ -3382,8 +3431,8 @@ statement_item<nodep>:          // IEEE: statement_item
         |       seq_block                               { $$ = $1; }
         //
         //                      // IEEE: wait_statement
-        |       yWAIT '(' expr ')' stmtBlock            { $$ = new AstWait($1, $3, $5); }
-        |       yWAIT yFORK ';'                         { $$ = new AstWaitFork($1); }
+        |       yWAIT '(' expr ')' stmtBlock            { $$ = new AstWait{$1, $3, $5}; }
+        |       yWAIT yFORK ';'                         { $$ = new AstWaitFork{$1}; }
         //UNSUP yWAIT_ORDER '(' hierarchical_identifierList ')' action_block    { UNSUP }
         //
         //                      // IEEE: procedural_assertion_statement
@@ -3412,7 +3461,7 @@ statementFor<beginp>:           // IEEE: part of statement
                           $$->addStmtsp(new AstWhile{$1, $4, $8, $6}); }
         |       yFOR '(' for_initialization ';' for_stepE ')' stmtBlock
                         { $$ = new AstBegin{$1, "", $3, false, true};
-                          $$->addStmtsp(new AstWhile{$1, new AstConst{$1, AstConst::BitTrue()}, $7, $5}); }
+                          $$->addStmtsp(new AstWhile{$1, new AstConst{$1, AstConst::BitTrue{}}, $7, $5}); }
         ;
 
 statementVerilatorPragmas<nodep>:
@@ -3437,8 +3486,8 @@ statementVerilatorPragmas<nodep>:
 
 foperator_assignment<nodep>:    // IEEE: operator_assignment (for first part of expression)
                 fexprLvalue '=' delay_or_event_controlE expr    { $$ = new AstAssign{$2, $1, $4, $3}; }
-        |       fexprLvalue '=' yD_FOPEN '(' expr ')'           { $$ = new AstFOpenMcd($3,$1,$5); }
-        |       fexprLvalue '=' yD_FOPEN '(' expr ',' expr ')'  { $$ = new AstFOpen($3,$1,$5,$7); }
+        |       fexprLvalue '=' yD_FOPEN '(' expr ')'           { $$ = new AstFOpenMcd{$3, $1, $5}; }
+        |       fexprLvalue '=' yD_FOPEN '(' expr ',' expr ')'  { $$ = new AstFOpen{$3, $1, $5, $7}; }
         //
         //UNSUP ~f~exprLvalue yP_PLUS(etc) expr         { UNSUP }
         |       fexprLvalue yP_PLUSEQ    expr
@@ -3470,14 +3519,18 @@ foperator_assignment<nodep>:    // IEEE: operator_assignment (for first part of
 inc_or_dec_expression<nodeExprp>:   // ==IEEE: inc_or_dec_expression
         //                      // Need fexprScope instead of variable_lvalue to prevent conflict
                 ~l~exprScope yP_PLUSPLUS
-                        { $<fl>$ = $<fl>1; $$ = new AstPostAdd{$2, new AstConst{$2, AstConst::StringToParse(), "'b1"}, $1, $1->cloneTree(true)}; }
+                        { $<fl>$ = $<fl>1; $$ = new AstPostAdd{$2, new AstConst{$2, AstConst::StringToParse{}, "'b1"},
+                                                               $1, $1->cloneTree(true)}; }
         |       ~l~exprScope yP_MINUSMINUS
-                        { $<fl>$ = $<fl>1; $$ = new AstPostSub{$2, new AstConst{$2, AstConst::StringToParse(), "'b1"}, $1, $1->cloneTree(true)}; }
+                        { $<fl>$ = $<fl>1; $$ = new AstPostSub{$2, new AstConst{$2, AstConst::StringToParse{}, "'b1"},
+                                                               $1, $1->cloneTree(true)}; }
         //                      // Need expr instead of variable_lvalue to prevent conflict
         |       yP_PLUSPLUS     expr
-                        { $<fl>$ = $<fl>1; $$ = new AstPreAdd{$1, new AstConst{$1, AstConst::StringToParse(), "'b1"}, $2, $2->cloneTree(true)}; }
+                        { $<fl>$ = $<fl>1; $$ = new AstPreAdd{$1, new AstConst{$1, AstConst::StringToParse{}, "'b1"},
+                                                              $2, $2->cloneTree(true)}; }
         |       yP_MINUSMINUS   expr
-                        { $<fl>$ = $<fl>1; $$ = new AstPreSub{$1, new AstConst{$1, AstConst::StringToParse(), "'b1"}, $2, $2->cloneTree(true)}; }
+                        { $<fl>$ = $<fl>1; $$ = new AstPreSub{$1, new AstConst{$1, AstConst::StringToParse{}, "'b1"},
+                                                              $2, $2->cloneTree(true)}; }
         ;
 
 finc_or_dec_expression<nodeExprp>:  // ==IEEE: inc_or_dec_expression
@@ -3502,14 +3555,14 @@ finc_or_dec_expression<nodeExprp>:  // ==IEEE: inc_or_dec_expression
 
 class_new<nodeExprp>:           // ==IEEE: class_new
         //                      // Special precence so (...) doesn't match expr
-                yNEW__ETC                               { $$ = new AstNew($1,  nullptr); }
-        |       yNEW__ETC expr                          { $$ = new AstNewCopy($1, $2); }
-        |       yNEW__PAREN '(' list_of_argumentsE ')'  { $$ = new AstNew($1, $3); }
+                yNEW__ETC                               { $$ = new AstNew{$1,  nullptr}; }
+        |       yNEW__ETC expr                          { $$ = new AstNewCopy{$1, $2}; }
+        |       yNEW__PAREN '(' list_of_argumentsE ')'  { $$ = new AstNew{$1, $3}; }
         ;
 
 dynamic_array_new<nodeExprp>:   // ==IEEE: dynamic_array_new
-                yNEW__ETC '[' expr ']'                  { $$ = new AstNewDynamic($1, $3, nullptr); }
-        |       yNEW__ETC '[' expr ']' '(' expr ')'     { $$ = new AstNewDynamic($1, $3, $6); }
+                yNEW__ETC '[' expr ']'                  { $$ = new AstNewDynamic{$1, $3, nullptr}; }
+        |       yNEW__ETC '[' expr ']' '(' expr ')'     { $$ = new AstNewDynamic{$1, $3, $6}; }
         ;
 
 //************************************************
@@ -3523,9 +3576,12 @@ unique_priorityE<uniqstate>:    // IEEE: unique_priority + empty
         ;
 
 caseStart<casep>:               // IEEE: part of case_statement
-                yCASE  '(' expr ')'                     { $$ = GRAMMARP->m_caseAttrp = new AstCase($1,VCaseType::CT_CASE,$3,nullptr); }
-        |       yCASEX '(' expr ')'                     { $$ = GRAMMARP->m_caseAttrp = new AstCase($1,VCaseType::CT_CASEX,$3,nullptr); }
-        |       yCASEZ '(' expr ')'                     { $$ = GRAMMARP->m_caseAttrp = new AstCase($1,VCaseType::CT_CASEZ,$3,nullptr); }
+                yCASE  '(' expr ')'
+                        { $$ = GRAMMARP->m_caseAttrp = new AstCase{$1, VCaseType::CT_CASE, $3, nullptr}; }
+        |       yCASEX '(' expr ')'
+                        { $$ = GRAMMARP->m_caseAttrp = new AstCase{$1, VCaseType::CT_CASEX, $3, nullptr}; }
+        |       yCASEZ '(' expr ')'
+                        { $$ = GRAMMARP->m_caseAttrp = new AstCase{$1, VCaseType::CT_CASEZ, $3, nullptr}; }
         ;
 
 caseAttrE:
@@ -3584,7 +3640,7 @@ open_value_range<nodeExprp>:    // ==IEEE: open_value_range
 
 value_range<nodeExprp>:         // ==IEEE: value_range
                 expr                                    { $$ = $1; }
-        |       '[' expr ':' expr ']'                   { $$ = new AstInsideRange($1, $2, $4); }
+        |       '[' expr ':' expr ']'                   { $$ = new AstInsideRange{$1, $2, $4}; }
         ;
 
 //UNSUPcovergroup_value_range<nodep>:  // ==IEEE-2012: covergroup_value_range
@@ -3627,10 +3683,10 @@ patternMemberList<nodep>:       // IEEE: part of pattern and assignment_pattern
         ;
 
 patternMemberOne<patMemberp>:   // IEEE: part of pattern and assignment_pattern
-                patternKey ':' expr                     { $$ = new AstPatMember($1->fileline(),$3,$1,nullptr); }
+                patternKey ':' expr                     { $$ = new AstPatMember{$1->fileline(), $3, $1, nullptr}; }
         |       patternKey ':' patternNoExpr            { $$ = nullptr; BBUNSUP($2, "Unsupported: '{} .* patterns"); }
         //                      // From assignment_pattern_key
-        |       yDEFAULT ':' expr                       { $$ = new AstPatMember($1,$3,nullptr,nullptr); $$->isDefault(true); }
+        |       yDEFAULT ':' expr                       { $$ = new AstPatMember{$1, $3, nullptr, nullptr}; $$->isDefault(true); }
         |       yDEFAULT ':' patternNoExpr              { $$ = nullptr; BBUNSUP($2, "Unsupported: '{} .* patterns"); }
         ;
 
@@ -3645,9 +3701,9 @@ patternKey<nodep>:              // IEEE: merge structure_pattern_key, array_patt
         //                      //   "foo"member (if structure)
         //                      //   So for now we only allow a true constant number, or an
         //                      //   identifier which we treat as a structure member name
-                yaINTNUM                                { $$ = new AstConst($<fl>1,*$1); }
-        |       yaFLOATNUM                              { $$ = new AstConst($<fl>1,AstConst::RealDouble(),$1); }
-        |       id                                      { $$ = new AstText($<fl>1,*$1); }
+                yaINTNUM                                { $$ = new AstConst{$<fl>1, *$1}; }
+        |       yaFLOATNUM                              { $$ = new AstConst{$<fl>1, AstConst::RealDouble{}, $1}; }
+        |       id                                      { $$ = new AstText{$<fl>1, *$1}; }
         |       strAsInt                                { $$ = $1; }
         |       simple_type                             { $$ = $1; }
         ;
@@ -3659,13 +3715,13 @@ assignment_pattern<patternp>:   // ==IEEE: assignment_pattern
         //                      // From patternNoExpr
         //                      // also IEEE: "''{' expression { ',' expression } '}'"
         //                      //      matches since patternList includes expr
-                yP_TICKBRA patternList '}'              { $$ = new AstPattern($1,$2); }
+                yP_TICKBRA patternList '}'              { $$ = new AstPattern{$1, $2}; }
         //                      // From patternNoExpr
         //                      // also IEEE "''{' structure_pattern_key ':' ...
         //                      // also IEEE "''{' array_pattern_key ':' ...
-        |       yP_TICKBRA patternMemberList '}'        { $$ = new AstPattern($1,$2); }
+        |       yP_TICKBRA patternMemberList '}'        { $$ = new AstPattern{$1, $2}; }
         //                      // IEEE: Not in grammar, but in VMM
-        |       yP_TICKBRA '}'                          { $$ = new AstPattern($1, nullptr); }
+        |       yP_TICKBRA '}'                          { $$ = new AstPattern{$1, nullptr}; }
         ;
 
 // "datatype id = x {, id = x }"  |  "yaId = x {, id=x}" is legal
@@ -3686,16 +3742,16 @@ for_initializationItem<nodep>:          // IEEE: variable_assignment + for_varia
         //                      // IEEE: for_variable_declaration
                 data_type idAny/*new*/ '=' expr
                         { VARRESET_NONLIST(VAR); VARDTYPE($1);
-                          $$ = VARDONEA($<fl>2,*$2,nullptr,nullptr);
-                          $$->addNext(new AstAssign($3, new AstVarRef($<fl>2, *$2, VAccess::WRITE), $4)); }
+                          $$ = VARDONEA($<fl>2, *$2, nullptr, nullptr);
+                          $$->addNext(new AstAssign{$3, new AstVarRef{$<fl>2, *$2, VAccess::WRITE}, $4}); }
         //                      // IEEE-2012:
         |       yVAR data_type idAny/*new*/ '=' expr
                         { VARRESET_NONLIST(VAR); VARDTYPE($2);
-                          $$ = VARDONEA($<fl>3,*$3,nullptr,nullptr);
-                          $$->addNext(new AstAssign($4, new AstVarRef($<fl>3, *$3, VAccess::WRITE), $5)); }
+                          $$ = VARDONEA($<fl>3, *$3, nullptr, nullptr);
+                          $$->addNext(new AstAssign{$4, new AstVarRef{$<fl>3, *$3, VAccess::WRITE}, $5}); }
         //                      // IEEE: variable_assignment
         //                      // UNSUP variable_lvalue below
-        |       varRefBase '=' expr                     { $$ = new AstAssign($2, $1, $3); }
+        |       varRefBase '=' expr                     { $$ = new AstAssign{$2, $1, $3}; }
         ;
 
 for_stepE<nodep>:               // IEEE: for_step + empty
@@ -3732,10 +3788,10 @@ loop_variables<nodep>:          // IEEE: loop_variables
 // Functions/tasks
 
 taskRef<nodeExprp>:            // IEEE: part of tf_call
-                id                              { $$ = new AstTaskRef($<fl>1,*$1,nullptr); }
-        |       id '(' list_of_argumentsE ')'   { $$ = new AstTaskRef($<fl>1,*$1,$3); }
+                id                                      { $$ = new AstTaskRef{$<fl>1, *$1, nullptr}; }
+        |       id '(' list_of_argumentsE ')'           { $$ = new AstTaskRef{$<fl>1, *$1, $3}; }
         |       packageClassScope id '(' list_of_argumentsE ')'
-                        { $$ = AstDot::newIfPkg($<fl>2, $1, new AstTaskRef($<fl>2, *$2, $4)); }
+                        { $$ = AstDot::newIfPkg($<fl>2, $1, new AstTaskRef{$<fl>2, *$2, $4}); }
         ;
 
 funcRef<nodeExprp>:             // IEEE: part of tf_call
@@ -3749,9 +3805,9 @@ funcRef<nodeExprp>:             // IEEE: part of tf_call
         //                      //      let_expression          let_identifier          let_actual_arg
         //
                 id '(' list_of_argumentsE ')'
-                        { $$ = new AstFuncRef($<fl>1, *$1, $3); }
+                        { $$ = new AstFuncRef{$<fl>1, *$1, $3}; }
         |       packageClassScope id '(' list_of_argumentsE ')'
-                        { $$ = AstDot::newIfPkg($<fl>2, $1, new AstFuncRef($<fl>2, *$2, $4)); }
+                        { $$ = AstDot::newIfPkg($<fl>2, $1, new AstFuncRef{$<fl>2, *$2, $4}); }
         //UNSUP list_of_argumentE should be pev_list_of_argumentE
         //UNSUP: idDotted is really just id to allow dotted method calls
         ;
@@ -3818,23 +3874,23 @@ system_t_call<nodeStmtp>:       // IEEE: system_tf_call (as task)
         //
         |       yD_C '(' cStrList ')'                   { $$ = (v3Global.opt.ignc() ? nullptr : new AstUCStmt($1,$3)); }
         |       yD_STACKTRACE parenE                    { $$ = new AstStackTraceT{$1}; }
-        |       yD_SYSTEM '(' expr ')'                  { $$ = new AstSystemT($1, $3); }
+        |       yD_SYSTEM '(' expr ')'                  { $$ = new AstSystemT{$1, $3}; }
         //
-        |       yD_EXIT parenE                          { $$ = new AstFinish($1); }
+        |       yD_EXIT parenE                          { $$ = new AstFinish{$1}; }
         //
         |       yD_FCLOSE '(' expr ')'                  { $$ = new AstFClose{$1, $3}; }
-        |       yD_FFLUSH parenE                        { $$ = new AstFFlush($1, nullptr); }
-        |       yD_FFLUSH '(' expr ')'                  { $$ = new AstFFlush($1, $3); }
-        |       yD_FINISH parenE                        { $$ = new AstFinish($1); }
-        |       yD_FINISH '(' expr ')'                  { $$ = new AstFinish($1); DEL($3); }
-        |       yD_STOP parenE                          { $$ = new AstStop($1, false); }
-        |       yD_STOP '(' expr ')'                    { $$ = new AstStop($1, false); DEL($3); }
+        |       yD_FFLUSH parenE                        { $$ = new AstFFlush{$1, nullptr}; }
+        |       yD_FFLUSH '(' expr ')'                  { $$ = new AstFFlush{$1, $3}; }
+        |       yD_FINISH parenE                        { $$ = new AstFinish{$1}; }
+        |       yD_FINISH '(' expr ')'                  { $$ = new AstFinish{$1}; DEL($3); }
+        |       yD_STOP parenE                          { $$ = new AstStop{$1, false}; }
+        |       yD_STOP '(' expr ')'                    { $$ = new AstStop{$1, false}; DEL($3); }
         //
-        |       yD_SFORMAT '(' expr ',' exprDispList ')'        { $$ = new AstSFormat($1, $3, $5); }
-        |       yD_SWRITE  '(' expr ',' exprDispList ')'        { $$ = new AstSFormat($1, $3, $5); }
-        |       yD_SWRITEB '(' expr ',' exprDispList ')'        { $$ = new AstSFormat($1, $3, $5, 'b'); }
-        |       yD_SWRITEH '(' expr ',' exprDispList ')'        { $$ = new AstSFormat($1, $3, $5, 'h'); }
-        |       yD_SWRITEO '(' expr ',' exprDispList ')'        { $$ = new AstSFormat($1, $3, $5, 'o'); }
+        |       yD_SFORMAT '(' expr ',' exprDispList ')'        { $$ = new AstSFormat{$1, $3, $5}; }
+        |       yD_SWRITE  '(' expr ',' exprDispList ')'        { $$ = new AstSFormat{$1, $3, $5}; }
+        |       yD_SWRITEB '(' expr ',' exprDispList ')'        { $$ = new AstSFormat{$1, $3, $5, 'b'}; }
+        |       yD_SWRITEH '(' expr ',' exprDispList ')'        { $$ = new AstSFormat{$1, $3, $5, 'h'}; }
+        |       yD_SWRITEO '(' expr ',' exprDispList ')'        { $$ = new AstSFormat{$1, $3, $5, 'o'}; }
         //
         |       yD_DISPLAY  parenE                      { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, nullptr); }
         |       yD_DISPLAY  '(' exprDispList ')'        { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, $3); }
@@ -3890,8 +3946,8 @@ system_t_call<nodeStmtp>:       // IEEE: system_tf_call (as task)
         |       yD_FATAL    '(' expr ')'                { $$ = new AstDisplay($1,VDisplayType::DT_FATAL,   nullptr, nullptr); $$->addNext(new AstStop($1, false)); DEL($3); }
         |       yD_FATAL    '(' expr ',' exprDispList ')'       { $$ = new AstDisplay($1,VDisplayType::DT_FATAL,   nullptr, $5);   $$->addNext(new AstStop($1, false)); DEL($3); }
         //
-        |       yD_MONITOROFF parenE                    { $$ = new AstMonitorOff($1, true); }
-        |       yD_MONITORON parenE                     { $$ = new AstMonitorOff($1, false); }
+        |       yD_MONITOROFF parenE                    { $$ = new AstMonitorOff{$1, true}; }
+        |       yD_MONITORON parenE                     { $$ = new AstMonitorOff{$1, false}; }
         //
         |       yD_PRINTTIMESCALE                       { $$ = new AstPrintTimeScale{$1}; }
         |       yD_PRINTTIMESCALE '(' ')'               { $$ = new AstPrintTimeScale{$1}; }
@@ -3919,16 +3975,16 @@ system_t_call<nodeStmtp>:       // IEEE: system_tf_call (as task)
                           $$ = new AstAssertIntrinsic(fl_nowarn, new AstCastDynamic(fl_nowarn, $5, $3), nullptr, nullptr, true); }
         //
         // Any system function as a task
-        |       system_f_call_or_t                      { $$ = new AstSysFuncAsTask($<fl>1, $1); }
+        |       system_f_call_or_t                      { $$ = new AstSysFuncAsTask{$<fl>1, $1}; }
         ;
 
 system_f_call<nodeExprp>:           // IEEE: system_tf_call (as func)
                 yaD_PLI systemDpiArgsE                  { $$ = new AstFuncRef($<fl>1, *$1, $2); VN_CAST($$, FuncRef)->pli(true); }
         //
-        |       yD_C '(' cStrList ')'                   { $$ = (v3Global.opt.ignc() ? nullptr : new AstUCFunc($1,$3)); }
-        |       yD_CAST '(' expr ',' expr ')'           { $$ = new AstCastDynamic($1, $5, $3); }
+        |       yD_C '(' cStrList ')'                   { $$ = (v3Global.opt.ignc() ? nullptr : new AstUCFunc{$1, $3}); }
+        |       yD_CAST '(' expr ',' expr ')'           { $$ = new AstCastDynamic{$1, $5, $3}; }
         |       yD_STACKTRACE parenE                    { $$ = new AstStackTraceF{$1}; }
-        |       yD_SYSTEM  '(' expr ')'                 { $$ = new AstSystemF($1,$3); }
+        |       yD_SYSTEM  '(' expr ')'                 { $$ = new AstSystemF{$1, $3}; }
         //
         |       system_f_call_or_t                      { $$ = $1; }
         ;
@@ -5028,15 +5084,15 @@ gateFront<nodep>:
 
 gateAndPinList<nodeExprp>:
                 gatePinExpr                             { $$ = $1; }
-        |       gateAndPinList ',' gatePinExpr          { $$ = new AstAnd($2,$1,$3); }
+        |       gateAndPinList ',' gatePinExpr          { $$ = new AstAnd{$2, $1, $3}; }
         ;
 gateOrPinList<nodeExprp>:
                 gatePinExpr                             { $$ = $1; }
-        |       gateOrPinList ',' gatePinExpr           { $$ = new AstOr($2,$1,$3); }
+        |       gateOrPinList ',' gatePinExpr           { $$ = new AstOr{$2, $1, $3}; }
         ;
 gateXorPinList<nodeExprp>:
                 gatePinExpr                             { $$ = $1; }
-        |       gateXorPinList ',' gatePinExpr          { $$ = new AstXor($2,$1,$3); }
+        |       gateXorPinList ',' gatePinExpr          { $$ = new AstXor{$2, $1, $3}; }
         ;
 gateUnsupPinList<nodeExprp>:
                 gatePinExpr                             { $$ = $1; }
@@ -5080,7 +5136,7 @@ driveStrength<nodep>:
 // Tables
 
 combinational_body<nodep>:      // IEEE: combinational_body + sequential_body
-                yTABLE tableEntryList yENDTABLE         { $$ = new AstUdpTable($1,$2); }
+                yTABLE tableEntryList yENDTABLE         { $$ = new AstUdpTable{$1, $2}; }
         ;
 
 tableEntryList<udpTableLinep>:  // IEEE: { combinational_entry | sequential_entry }
@@ -5157,9 +5213,9 @@ idRandomize<strp>:              // Keyword as an identifier
 idSVKwd<strp>:                  // Warn about non-forward compatible Verilog 2001 code
         //                      // yBIT, yBYTE won't work here as causes conflicts
                 yDO
-                        { static string s = "do"   ; $$ = &s; ERRSVKWD($1,*$$); $<fl>$ = $<fl>1; }
+                        { static string s = "do"   ; $$ = &s; ERRSVKWD($1, *$$); $<fl>$ = $<fl>1; }
         |       yFINAL
-                        { static string s = "final"; $$ = &s; ERRSVKWD($1,*$$); $<fl>$ = $<fl>1; }
+                        { static string s = "final"; $$ = &s; ERRSVKWD($1, *$$); $<fl>$ = $<fl>1; }
         ;
 
 variable_lvalue<nodeExprp>:         // IEEE: variable_lvalue or net_lvalue
@@ -5277,7 +5333,7 @@ parseRefBase<nodep>:
 
 // yaSTRING shouldn't be used directly, instead via an abstraction below
 str<strp>:                      // yaSTRING but with \{escapes} need decoded
-                yaSTRING                                { $$ = PARSEP->newString(GRAMMARP->deQuote($<fl>1,*$1)); }
+                yaSTRING                                { $$ = PARSEP->newString(GRAMMARP->deQuote($<fl>1, *$1)); }
         ;
 
 strAsInt<nodeExprp>:
@@ -5381,8 +5437,8 @@ clocking_declaration<nodep>:            // IEEE: clocking_declaration  (INCOMPLE
 //UNSUP |       yPOSEDGE delay_control                  { }
 //UNSUP |       yNEGEDGE                                { }
 //UNSUP |       yNEGEDGE delay_control                  { }
-//UNSUP |       yEDGE                                   { NEED_S09($<fl>1,"edge"); }
-//UNSUP |       yEDGE delay_control                     { NEED_S09($<fl>1,"edge"); }
+//UNSUP |       yEDGE                                   { NEED_S09($<fl>1, "edge"); }
+//UNSUP |       yEDGE delay_control                     { NEED_S09($<fl>1, "edge"); }
 //UNSUP |       delay_control                           { $$ = $1; }
 //UNSUP ;
 
@@ -5888,18 +5944,18 @@ complex_pexpr<nodeExprp>:  // IEEE: part of property_expr, see comments there
 //UNSUPcovergroup_declaration<nodep>:  // ==IEEE: covergroup_declaration
 //UNSUP         covergroup_declarationFront coverage_eventE ';' coverage_spec_or_optionListE
 //UNSUP                 yENDGROUP endLabelE
-//UNSUP                 { PARSEP->endgroupCb($<fl>5,$5);
+//UNSUP                 { PARSEP->endgroupCb($<fl>5, $5);
 //UNSUP                   SYMP->popScope($$); }
 //UNSUP |       covergroup_declarationFront '(' tf_port_listE ')' coverage_eventE ';' coverage_spec_or_optionListE
 //UNSUP                 yENDGROUP endLabelE
-//UNSUP                 { PARSEP->endgroupCb($<fl>8,$8);
+//UNSUP                 { PARSEP->endgroupCb($<fl>8, $8);
 //UNSUP                   SYMP->popScope($$); }
 //UNSUP ;
 
 //UNSUPcovergroup_declarationFront:  // IEEE: part of covergroup_declaration
 //UNSUP         yCOVERGROUP idAny
 //UNSUP                         { SYMP->pushNew($$);
-//UNSUP                   PARSEP->covergroupCb($<fl>1,$1,$2); }
+//UNSUP                   PARSEP->covergroupCb($<fl>1, $1, $2); }
 //UNSUP ;
 
 //UNSUPcgexpr<nodep>:  // IEEE-2012: covergroup_expression, before that just expression
@@ -6375,7 +6431,7 @@ class_typeExtImpList<nodep>:    // IEEE: class_type: "[package_scope] id [ param
         |       class_typeExtImpList yP_COLONCOLON class_typeExtImpOne
                         { $$ = $3; $<scp>$ = $<scp>1;
                           // Cannot just add as next() as that breaks implements lists
-                          //UNSUP $$ = new AstDot($<fl>1, true, $1, $3);
+                          //UNSUP $$ = new AstDot{$<fl>1, true, $1, $3};
                           BBUNSUP($2, "Unsupported: Hierarchical class references"); }
         ;
 
@@ -6691,7 +6747,7 @@ vltItem:
                         { if (($1 == V3ErrorCode::I_COVERAGE) || ($1 == V3ErrorCode::I_TRACING)) {
                               $<fl>1->v3error("Argument -match only supported for lint_off");
                           } else {
-                              V3Config::addWaiver($1,*$3,*$5);
+                              V3Config::addWaiver($1, *$3, *$5);
                           }}
         |       vltOnFront
                         { V3Config::addIgnore($1, true, "*", 0, 0); }

From 0af02563caa42ec442d109f7cb47bc26419978df Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 21 Nov 2022 20:22:13 -0500
Subject: [PATCH 081/156] Internals: Fix verilog.y style

---
 src/verilog.y | 777 ++++++++++++++++++++++++++------------------------
 1 file changed, 406 insertions(+), 371 deletions(-)

diff --git a/src/verilog.y b/src/verilog.y
index 0ef909f90..ec818941d 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -51,7 +51,8 @@
             MINTYPMAXDLY, \
             "Unsupported: minimum/typical/maximum delay expressions. Using the typical delay"); \
     }
-#define PUT_DLYS_IN_ASSIGNS(delayp, assignsp) \
+// Given a list of assignments, if there is a delay add it to each assignment
+#define DELAY_LIST(delayp, assignsp) \
     if (delayp) { \
         for (auto* nodep = assignsp; nodep; nodep = nodep->nextp()) { \
             auto* const assignp = VN_AS(nodep, NodeAssign); \
@@ -313,7 +314,8 @@ int V3ParseGrammar::s_modTypeImpNum = 0;
         if (nodep) nodep->deleteTree(); \
     }
 
-#define APPLY_STRENGTH_TO_LIST(beginp, strengthSpecNodep, typeToCast) \
+// Apply a strength to a list of nodes under beginp
+#define STRENGTH_LIST(beginp, strengthSpecNodep, typeToCast) \
     { \
         if (AstStrengthSpec* specp = VN_CAST(strengthSpecNodep, StrengthSpec)) { \
             for (auto* nodep = beginp; nodep; nodep = nodep->nextp()) { \
@@ -2143,7 +2145,7 @@ list_of_tf_variable_identifiers<nodep>: // ==IEEE: list_of_tf_variable_identifie
 
 tf_variable_identifier<varp>:           // IEEE: part of list_of_tf_variable_identifiers
                 id variable_dimensionListE sigAttrListE exprEqE
-                        { $$ = VARDONEA($<fl>1,*$1, $2, $3);
+                        { $$ = VARDONEA($<fl>1, *$1, $2, $3);
                           if ($4) AstNode::addNext<AstNode, AstNode>(
                                       $$, new AstAssign{$4->fileline(), new AstVarRef{$<fl>1, *$1, VAccess::WRITE}, $4}); }
         ;
@@ -2540,8 +2542,8 @@ continuous_assign<nodep>:       // IEEE: continuous_assign
                 yASSIGN driveStrengthE delay_controlE assignList ';'
                 {
                     $$ = $4;
-                    APPLY_STRENGTH_TO_LIST($4, $2, AssignW);
-                    PUT_DLYS_IN_ASSIGNS($3, $4);
+                    STRENGTH_LIST($4, $2, AssignW);
+                    DELAY_LIST($3, $4);
                 }
         ;
 
@@ -3850,29 +3852,29 @@ system_t_call<nodeStmtp>:       // IEEE: system_tf_call (as task)
                                                           refp->pli(true);
                                                           $$ = refp->makeStmt(); }
         //
-        |       yD_DUMPPORTS '(' idDotted ',' expr ')'  { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::FILE, $5); DEL($3);
-                                                          $$->addNext(new AstDumpCtl($<fl>1, VDumpCtlType::VARS,
-                                                                                     new AstConst($<fl>1, 1))); }
-        |       yD_DUMPPORTS '(' ',' expr ')'           { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::FILE, $4);
-                                                          $$->addNext(new AstDumpCtl($<fl>1, VDumpCtlType::VARS,
-                                                                                     new AstConst($<fl>1, 1))); }
-        |       yD_DUMPFILE '(' expr ')'                { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::FILE, $3); }
-        |       yD_DUMPVARS parenE                      { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::VARS,
-                                                                              new AstConst($<fl>1, 0)); }
-        |       yD_DUMPVARS '(' expr ')'                { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::VARS, $3); }
-        |       yD_DUMPVARS '(' expr ',' idDotted ')'   { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::VARS, $3); DEL($5); }
-        |       yD_DUMPALL parenE                       { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::ALL); }
-        |       yD_DUMPALL '(' expr ')'                 { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::ALL); DEL($3); }
-        |       yD_DUMPFLUSH parenE                     { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::FLUSH); }
-        |       yD_DUMPFLUSH '(' expr ')'               { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::FLUSH); DEL($3); }
-        |       yD_DUMPLIMIT '(' expr ')'               { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::LIMIT, $3); }
-        |       yD_DUMPLIMIT '(' expr ',' expr ')'      { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::LIMIT, $3); DEL($5); }
-        |       yD_DUMPOFF parenE                       { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::OFF); }
-        |       yD_DUMPOFF '(' expr ')'                 { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::OFF); DEL($3); }
-        |       yD_DUMPON parenE                        { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::ON); }
-        |       yD_DUMPON '(' expr ')'                  { $$ = new AstDumpCtl($<fl>1, VDumpCtlType::ON); DEL($3); }
+        |       yD_DUMPPORTS '(' idDotted ',' expr ')'  { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::FILE, $5}; DEL($3);
+                                                          $$->addNext(new AstDumpCtl{$<fl>1, VDumpCtlType::VARS,
+                                                                                     new AstConst{$<fl>1, 1}}); }
+        |       yD_DUMPPORTS '(' ',' expr ')'           { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::FILE, $4};
+                                                          $$->addNext(new AstDumpCtl{$<fl>1, VDumpCtlType::VARS,
+                                                                                     new AstConst{$<fl>1, 1}}); }
+        |       yD_DUMPFILE '(' expr ')'                { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::FILE, $3}; }
+        |       yD_DUMPVARS parenE                      { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::VARS,
+                                                                              new AstConst{$<fl>1, 0}}; }
+        |       yD_DUMPVARS '(' expr ')'                { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::VARS, $3}; }
+        |       yD_DUMPVARS '(' expr ',' idDotted ')'   { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::VARS, $3}; DEL($5); }
+        |       yD_DUMPALL parenE                       { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::ALL}; }
+        |       yD_DUMPALL '(' expr ')'                 { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::ALL}; DEL($3); }
+        |       yD_DUMPFLUSH parenE                     { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::FLUSH}; }
+        |       yD_DUMPFLUSH '(' expr ')'               { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::FLUSH}; DEL($3); }
+        |       yD_DUMPLIMIT '(' expr ')'               { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::LIMIT, $3}; }
+        |       yD_DUMPLIMIT '(' expr ',' expr ')'      { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::LIMIT, $3}; DEL($5); }
+        |       yD_DUMPOFF parenE                       { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::OFF}; }
+        |       yD_DUMPOFF '(' expr ')'                 { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::OFF}; DEL($3); }
+        |       yD_DUMPON parenE                        { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::ON}; }
+        |       yD_DUMPON '(' expr ')'                  { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::ON}; DEL($3); }
         //
-        |       yD_C '(' cStrList ')'                   { $$ = (v3Global.opt.ignc() ? nullptr : new AstUCStmt($1,$3)); }
+        |       yD_C '(' cStrList ')'                   { $$ = (v3Global.opt.ignc() ? nullptr : new AstUCStmt{$1, $3}); }
         |       yD_STACKTRACE parenE                    { $$ = new AstStackTraceT{$1}; }
         |       yD_SYSTEM '(' expr ')'                  { $$ = new AstSystemT{$1, $3}; }
         //
@@ -3892,59 +3894,67 @@ system_t_call<nodeStmtp>:       // IEEE: system_tf_call (as task)
         |       yD_SWRITEH '(' expr ',' exprDispList ')'        { $$ = new AstSFormat{$1, $3, $5, 'h'}; }
         |       yD_SWRITEO '(' expr ',' exprDispList ')'        { $$ = new AstSFormat{$1, $3, $5, 'o'}; }
         //
-        |       yD_DISPLAY  parenE                      { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, nullptr); }
-        |       yD_DISPLAY  '(' exprDispList ')'        { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, $3); }
-        |       yD_DISPLAYB  parenE                     { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, nullptr, 'b'); }
-        |       yD_DISPLAYB  '(' exprDispList ')'       { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, $3, 'b'); }
-        |       yD_DISPLAYH  parenE                     { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, nullptr, 'h'); }
-        |       yD_DISPLAYH  '(' exprDispList ')'       { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, $3, 'h'); }
-        |       yD_DISPLAYO  parenE                     { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, nullptr, 'o'); }
-        |       yD_DISPLAYO  '(' exprDispList ')'       { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, nullptr, $3, 'o'); }
-        |       yD_MONITOR   '(' exprDispList ')'       { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, nullptr, $3); }
-        |       yD_MONITORB  '(' exprDispList ')'       { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, nullptr, $3, 'b'); }
-        |       yD_MONITORH  '(' exprDispList ')'       { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, nullptr, $3, 'h'); }
-        |       yD_MONITORO  '(' exprDispList ')'       { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, nullptr, $3, 'o'); }
-        |       yD_STROBE   '(' exprDispList ')'        { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, nullptr, $3); }
-        |       yD_STROBEB  '(' exprDispList ')'        { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, nullptr, $3, 'b'); }
-        |       yD_STROBEH  '(' exprDispList ')'        { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, nullptr, $3, 'h'); }
-        |       yD_STROBEO  '(' exprDispList ')'        { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, nullptr, $3, 'o'); }
+        |       yD_DISPLAY  parenE                      { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, nullptr, nullptr}; }
+        |       yD_DISPLAY  '(' exprDispList ')'        { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, nullptr, $3}; }
+        |       yD_DISPLAYB  parenE                     { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, nullptr, nullptr, 'b'}; }
+        |       yD_DISPLAYB  '(' exprDispList ')'       { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, nullptr, $3, 'b'}; }
+        |       yD_DISPLAYH  parenE                     { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, nullptr, nullptr, 'h'}; }
+        |       yD_DISPLAYH  '(' exprDispList ')'       { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, nullptr, $3, 'h'}; }
+        |       yD_DISPLAYO  parenE                     { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, nullptr, nullptr, 'o'}; }
+        |       yD_DISPLAYO  '(' exprDispList ')'       { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, nullptr, $3, 'o'}; }
+        |       yD_MONITOR   '(' exprDispList ')'       { $$ = new AstDisplay{$1, VDisplayType::DT_MONITOR, nullptr, $3}; }
+        |       yD_MONITORB  '(' exprDispList ')'       { $$ = new AstDisplay{$1, VDisplayType::DT_MONITOR, nullptr, $3, 'b'}; }
+        |       yD_MONITORH  '(' exprDispList ')'       { $$ = new AstDisplay{$1, VDisplayType::DT_MONITOR, nullptr, $3, 'h'}; }
+        |       yD_MONITORO  '(' exprDispList ')'       { $$ = new AstDisplay{$1, VDisplayType::DT_MONITOR, nullptr, $3, 'o'}; }
+        |       yD_STROBE   '(' exprDispList ')'        { $$ = new AstDisplay{$1, VDisplayType::DT_STROBE, nullptr, $3}; }
+        |       yD_STROBEB  '(' exprDispList ')'        { $$ = new AstDisplay{$1, VDisplayType::DT_STROBE, nullptr, $3, 'b'}; }
+        |       yD_STROBEH  '(' exprDispList ')'        { $$ = new AstDisplay{$1, VDisplayType::DT_STROBE, nullptr, $3, 'h'}; }
+        |       yD_STROBEO  '(' exprDispList ')'        { $$ = new AstDisplay{$1, VDisplayType::DT_STROBE, nullptr, $3, 'o'}; }
         |       yD_WRITE    parenE                      { $$ = nullptr; }  // NOP
-        |       yD_WRITE    '(' exprDispList ')'        { $$ = new AstDisplay($1,VDisplayType::DT_WRITE,   nullptr, $3); }
+        |       yD_WRITE    '(' exprDispList ')'        { $$ = new AstDisplay{$1, VDisplayType::DT_WRITE, nullptr, $3}; }
         |       yD_WRITEB   parenE                      { $$ = nullptr; }  // NOP
-        |       yD_WRITEB   '(' exprDispList ')'        { $$ = new AstDisplay($1,VDisplayType::DT_WRITE,   nullptr, $3, 'b'); }
+        |       yD_WRITEB   '(' exprDispList ')'        { $$ = new AstDisplay{$1, VDisplayType::DT_WRITE, nullptr, $3, 'b'}; }
         |       yD_WRITEH   parenE                      { $$ = nullptr; }  // NOP
-        |       yD_WRITEH   '(' exprDispList ')'        { $$ = new AstDisplay($1,VDisplayType::DT_WRITE,   nullptr, $3, 'h'); }
+        |       yD_WRITEH   '(' exprDispList ')'        { $$ = new AstDisplay{$1, VDisplayType::DT_WRITE, nullptr, $3, 'h'}; }
         |       yD_WRITEO   parenE                      { $$ = nullptr; }  // NOP
-        |       yD_WRITEO   '(' exprDispList ')'        { $$ = new AstDisplay($1,VDisplayType::DT_WRITE,   nullptr, $3, 'o'); }
-        |       yD_FDISPLAY '(' expr ')'                { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, nullptr); }
-        |       yD_FDISPLAY '(' expr ',' exprDispList ')'       { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, $5); }
-        |       yD_FDISPLAYB '(' expr ')'                       { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, nullptr, 'b'); }
-        |       yD_FDISPLAYB '(' expr ',' exprDispList ')'      { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, $5, 'b'); }
-        |       yD_FDISPLAYH '(' expr ')'                       { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, nullptr, 'h'); }
-        |       yD_FDISPLAYH '(' expr ',' exprDispList ')'      { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, $5, 'h'); }
-        |       yD_FDISPLAYO '(' expr ')'                       { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, nullptr, 'o'); }
-        |       yD_FDISPLAYO '(' expr ',' exprDispList ')'      { $$ = new AstDisplay($1,VDisplayType::DT_DISPLAY, $3, $5, 'o'); }
-        |       yD_FMONITOR   '(' expr ',' exprDispList ')'     { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, $3, $5); }
-        |       yD_FMONITORB  '(' expr ',' exprDispList ')'     { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, $3, $5, 'b'); }
-        |       yD_FMONITORH  '(' expr ',' exprDispList ')'     { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, $3, $5, 'h'); }
-        |       yD_FMONITORO  '(' expr ',' exprDispList ')'     { $$ = new AstDisplay($1, VDisplayType::DT_MONITOR, $3, $5, 'o'); }
-        |       yD_FSTROBE   '(' expr ',' exprDispList ')'      { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, $3, $5); }
-        |       yD_FSTROBEB  '(' expr ',' exprDispList ')'      { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, $3, $5, 'b'); }
-        |       yD_FSTROBEH  '(' expr ',' exprDispList ')'      { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, $3, $5, 'h'); }
-        |       yD_FSTROBEO  '(' expr ',' exprDispList ')'      { $$ = new AstDisplay($1, VDisplayType::DT_STROBE, $3, $5, 'o'); }
-        |       yD_FWRITE   '(' expr ',' exprDispList ')'       { $$ = new AstDisplay($1, VDisplayType::DT_WRITE, $3, $5); }
-        |       yD_FWRITEB  '(' expr ',' exprDispList ')'       { $$ = new AstDisplay($1, VDisplayType::DT_WRITE, $3, $5, 'b'); }
-        |       yD_FWRITEH  '(' expr ',' exprDispList ')'       { $$ = new AstDisplay($1, VDisplayType::DT_WRITE, $3, $5, 'h'); }
-        |       yD_FWRITEO  '(' expr ',' exprDispList ')'       { $$ = new AstDisplay($1, VDisplayType::DT_WRITE, $3, $5, 'o'); }
-        |       yD_INFO     parenE                      { $$ = new AstDisplay($1,VDisplayType::DT_INFO,    nullptr, nullptr); }
-        |       yD_INFO     '(' exprDispList ')'        { $$ = new AstDisplay($1,VDisplayType::DT_INFO,    nullptr, $3); }
-        |       yD_WARNING  parenE                      { $$ = new AstDisplay($1,VDisplayType::DT_WARNING, nullptr, nullptr); }
-        |       yD_WARNING  '(' exprDispList ')'        { $$ = new AstDisplay($1,VDisplayType::DT_WARNING, nullptr, $3); }
+        |       yD_WRITEO   '(' exprDispList ')'        { $$ = new AstDisplay{$1, VDisplayType::DT_WRITE, nullptr, $3, 'o'}; }
+        |       yD_FDISPLAY '(' expr ')'                        { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, $3, nullptr}; }
+        |       yD_FDISPLAY '(' expr ',' exprDispList ')'       { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, $3, $5}; }
+        |       yD_FDISPLAYB '(' expr ')'                       { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, $3, nullptr, 'b'}; }
+        |       yD_FDISPLAYB '(' expr ',' exprDispList ')'      { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, $3, $5, 'b'}; }
+        |       yD_FDISPLAYH '(' expr ')'                       { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, $3, nullptr, 'h'}; }
+        |       yD_FDISPLAYH '(' expr ',' exprDispList ')'      { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, $3, $5, 'h'}; }
+        |       yD_FDISPLAYO '(' expr ')'                       { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, $3, nullptr, 'o'}; }
+        |       yD_FDISPLAYO '(' expr ',' exprDispList ')'      { $$ = new AstDisplay{$1, VDisplayType::DT_DISPLAY, $3, $5, 'o'}; }
+        |       yD_FMONITOR   '(' expr ',' exprDispList ')'     { $$ = new AstDisplay{$1, VDisplayType::DT_MONITOR, $3, $5}; }
+        |       yD_FMONITORB  '(' expr ',' exprDispList ')'     { $$ = new AstDisplay{$1, VDisplayType::DT_MONITOR, $3, $5, 'b'}; }
+        |       yD_FMONITORH  '(' expr ',' exprDispList ')'     { $$ = new AstDisplay{$1, VDisplayType::DT_MONITOR, $3, $5, 'h'}; }
+        |       yD_FMONITORO  '(' expr ',' exprDispList ')'     { $$ = new AstDisplay{$1, VDisplayType::DT_MONITOR, $3, $5, 'o'}; }
+        |       yD_FSTROBE   '(' expr ',' exprDispList ')'      { $$ = new AstDisplay{$1, VDisplayType::DT_STROBE, $3, $5}; }
+        |       yD_FSTROBEB  '(' expr ',' exprDispList ')'      { $$ = new AstDisplay{$1, VDisplayType::DT_STROBE, $3, $5, 'b'}; }
+        |       yD_FSTROBEH  '(' expr ',' exprDispList ')'      { $$ = new AstDisplay{$1, VDisplayType::DT_STROBE, $3, $5, 'h'}; }
+        |       yD_FSTROBEO  '(' expr ',' exprDispList ')'      { $$ = new AstDisplay{$1, VDisplayType::DT_STROBE, $3, $5, 'o'}; }
+        |       yD_FWRITE   '(' expr ',' exprDispList ')'       { $$ = new AstDisplay{$1, VDisplayType::DT_WRITE, $3, $5}; }
+        |       yD_FWRITEB  '(' expr ',' exprDispList ')'       { $$ = new AstDisplay{$1, VDisplayType::DT_WRITE, $3, $5, 'b'}; }
+        |       yD_FWRITEH  '(' expr ',' exprDispList ')'       { $$ = new AstDisplay{$1, VDisplayType::DT_WRITE, $3, $5, 'h'}; }
+        |       yD_FWRITEO  '(' expr ',' exprDispList ')'       { $$ = new AstDisplay{$1, VDisplayType::DT_WRITE, $3, $5, 'o'}; }
+        |       yD_INFO     parenE                      { $$ = new AstDisplay{$1, VDisplayType::DT_INFO, nullptr, nullptr}; }
+        |       yD_INFO     '(' exprDispList ')'        { $$ = new AstDisplay{$1, VDisplayType::DT_INFO, nullptr, $3}; }
+        |       yD_WARNING  parenE                      { $$ = new AstDisplay{$1, VDisplayType::DT_WARNING, nullptr, nullptr}; }
+        |       yD_WARNING  '(' exprDispList ')'        { $$ = new AstDisplay{$1, VDisplayType::DT_WARNING, nullptr, $3}; }
         |       yD_ERROR    parenE                      { $$ = GRAMMARP->createDisplayError($1); }
-        |       yD_ERROR    '(' exprDispList ')'        { $$ = new AstDisplay($1,VDisplayType::DT_ERROR,   nullptr, $3);   $$->addNext(new AstStop($1, true)); }
-        |       yD_FATAL    parenE                      { $$ = new AstDisplay($1,VDisplayType::DT_FATAL,   nullptr, nullptr); $$->addNext(new AstStop($1, false)); }
-        |       yD_FATAL    '(' expr ')'                { $$ = new AstDisplay($1,VDisplayType::DT_FATAL,   nullptr, nullptr); $$->addNext(new AstStop($1, false)); DEL($3); }
-        |       yD_FATAL    '(' expr ',' exprDispList ')'       { $$ = new AstDisplay($1,VDisplayType::DT_FATAL,   nullptr, $5);   $$->addNext(new AstStop($1, false)); DEL($3); }
+        |       yD_ERROR    '(' exprDispList ')'
+                        { $$ = new AstDisplay{$1, VDisplayType::DT_ERROR, nullptr, $3};
+                          $$->addNext(new AstStop{$1, true}); }
+        |       yD_FATAL    parenE
+                        { $$ = new AstDisplay{$1, VDisplayType::DT_FATAL, nullptr, nullptr};
+                          $$->addNext(new AstStop{$1, false}); }
+        |       yD_FATAL    '(' expr ')'
+                        { $$ = new AstDisplay{$1, VDisplayType::DT_FATAL, nullptr, nullptr};
+                          $$->addNext(new AstStop{$1, false}); DEL($3); }
+        |       yD_FATAL    '(' expr ',' exprDispList ')'
+                        { $$ = new AstDisplay{$1, VDisplayType::DT_FATAL, nullptr, $5};
+                          $$->addNext(new AstStop{$1, false}); DEL($3); }
         //
         |       yD_MONITOROFF parenE                    { $$ = new AstMonitorOff{$1, true}; }
         |       yD_MONITORON parenE                     { $$ = new AstMonitorOff{$1, false}; }
@@ -3955,31 +3965,32 @@ system_t_call<nodeStmtp>:       // IEEE: system_tf_call (as task)
         |       yD_TIMEFORMAT '(' expr ',' expr ',' expr ',' expr ')'
                         { $$ = new AstTimeFormat{$1, $3, $5, $7, $9}; }
         //
-        |       yD_READMEMB '(' expr ',' idClassSel ')'                         { $$ = new AstReadMem($1,false,$3,$5,nullptr,nullptr); }
-        |       yD_READMEMB '(' expr ',' idClassSel ',' expr ')'                { $$ = new AstReadMem($1,false,$3,$5,$7,nullptr); }
-        |       yD_READMEMB '(' expr ',' idClassSel ',' expr ',' expr ')'       { $$ = new AstReadMem($1,false,$3,$5,$7,$9); }
-        |       yD_READMEMH '(' expr ',' idClassSel ')'                         { $$ = new AstReadMem($1,true, $3,$5,nullptr,nullptr); }
-        |       yD_READMEMH '(' expr ',' idClassSel ',' expr ')'                { $$ = new AstReadMem($1,true, $3,$5,$7,nullptr); }
-        |       yD_READMEMH '(' expr ',' idClassSel ',' expr ',' expr ')'       { $$ = new AstReadMem($1,true, $3,$5,$7,$9); }
+        |       yD_READMEMB '(' expr ',' idClassSel ')'                         { $$ = new AstReadMem{$1, false, $3, $5, nullptr, nullptr}; }
+        |       yD_READMEMB '(' expr ',' idClassSel ',' expr ')'                { $$ = new AstReadMem{$1, false, $3, $5, $7, nullptr}; }
+        |       yD_READMEMB '(' expr ',' idClassSel ',' expr ',' expr ')'       { $$ = new AstReadMem{$1, false, $3, $5, $7, $9}; }
+        |       yD_READMEMH '(' expr ',' idClassSel ')'                         { $$ = new AstReadMem{$1, true,  $3, $5, nullptr, nullptr}; }
+        |       yD_READMEMH '(' expr ',' idClassSel ',' expr ')'                { $$ = new AstReadMem{$1, true,  $3, $5, $7, nullptr}; }
+        |       yD_READMEMH '(' expr ',' idClassSel ',' expr ',' expr ')'       { $$ = new AstReadMem{$1, true,  $3, $5, $7, $9}; }
         //
-        |       yD_WRITEMEMB '(' expr ',' idClassSel ')'                        { $$ = new AstWriteMem($1, false, $3, $5, nullptr, nullptr); }
-        |       yD_WRITEMEMB '(' expr ',' idClassSel ',' expr ')'               { $$ = new AstWriteMem($1, false, $3, $5, $7, nullptr); }
-        |       yD_WRITEMEMB '(' expr ',' idClassSel ',' expr ',' expr ')'      { $$ = new AstWriteMem($1, false, $3, $5, $7, $9); }
-        |       yD_WRITEMEMH '(' expr ',' idClassSel ')'                        { $$ = new AstWriteMem($1, true,  $3, $5, nullptr, nullptr); }
-        |       yD_WRITEMEMH '(' expr ',' idClassSel ',' expr ')'               { $$ = new AstWriteMem($1, true,  $3, $5, $7, nullptr); }
-        |       yD_WRITEMEMH '(' expr ',' idClassSel ',' expr ',' expr ')'      { $$ = new AstWriteMem($1, true,  $3, $5, $7, $9); }
+        |       yD_WRITEMEMB '(' expr ',' idClassSel ')'                        { $$ = new AstWriteMem{$1, false, $3, $5, nullptr, nullptr}; }
+        |       yD_WRITEMEMB '(' expr ',' idClassSel ',' expr ')'               { $$ = new AstWriteMem{$1, false, $3, $5, $7, nullptr}; }
+        |       yD_WRITEMEMB '(' expr ',' idClassSel ',' expr ',' expr ')'      { $$ = new AstWriteMem{$1, false, $3, $5, $7, $9}; }
+        |       yD_WRITEMEMH '(' expr ',' idClassSel ')'                        { $$ = new AstWriteMem{$1, true,  $3, $5, nullptr, nullptr}; }
+        |       yD_WRITEMEMH '(' expr ',' idClassSel ',' expr ')'               { $$ = new AstWriteMem{$1, true,  $3, $5, $7, nullptr}; }
+        |       yD_WRITEMEMH '(' expr ',' idClassSel ',' expr ',' expr ')'      { $$ = new AstWriteMem{$1, true,  $3, $5, $7, $9}; }
         //
         |       yD_CAST '(' expr ',' expr ')'
                         { FileLine* const fl_nowarn = new FileLine{$1};
                           fl_nowarn->warnOff(V3ErrorCode::WIDTH, true);
-                          $$ = new AstAssertIntrinsic(fl_nowarn, new AstCastDynamic(fl_nowarn, $5, $3), nullptr, nullptr, true); }
+                          $$ = new AstAssertIntrinsic{fl_nowarn, new AstCastDynamic{fl_nowarn, $5, $3},
+                                                      nullptr, nullptr, true}; }
         //
         // Any system function as a task
         |       system_f_call_or_t                      { $$ = new AstSysFuncAsTask{$<fl>1, $1}; }
         ;
 
 system_f_call<nodeExprp>:           // IEEE: system_tf_call (as func)
-                yaD_PLI systemDpiArgsE                  { $$ = new AstFuncRef($<fl>1, *$1, $2); VN_CAST($$, FuncRef)->pli(true); }
+                yaD_PLI systemDpiArgsE                  { $$ = new AstFuncRef{$<fl>1, *$1, $2}; VN_CAST($$, FuncRef)->pli(true); }
         //
         |       yD_C '(' cStrList ')'                   { $$ = (v3Global.opt.ignc() ? nullptr : new AstUCFunc{$1, $3}); }
         |       yD_CAST '(' expr ',' expr ')'           { $$ = new AstCastDynamic{$1, $5, $3}; }
@@ -3995,94 +4006,96 @@ systemDpiArgsE<argp>:           // IEEE: part of system_if_call for aruments of
         ;
 
 system_f_call_or_t<nodeExprp>:      // IEEE: part of system_tf_call (can be task or func)
-                yD_ACOS '(' expr ')'                    { $$ = new AstAcosD($1,$3); }
-        |       yD_ACOSH '(' expr ')'                   { $$ = new AstAcoshD($1,$3); }
-        |       yD_ASIN '(' expr ')'                    { $$ = new AstAsinD($1,$3); }
-        |       yD_ASINH '(' expr ')'                   { $$ = new AstAsinhD($1,$3); }
-        |       yD_ATAN '(' expr ')'                    { $$ = new AstAtanD($1,$3); }
-        |       yD_ATAN2 '(' expr ',' expr ')'          { $$ = new AstAtan2D($1,$3,$5); }
-        |       yD_ATANH '(' expr ')'                   { $$ = new AstAtanhD($1,$3); }
-        |       yD_BITS '(' exprOrDataType ')'          { $$ = new AstAttrOf($1,VAttrType::DIM_BITS,$3); }
-        |       yD_BITS '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,VAttrType::DIM_BITS,$3,$5); }
-        |       yD_BITSTOREAL '(' expr ')'              { $$ = new AstBitsToRealD($1,$3); }
-        |       yD_BITSTOSHORTREAL '(' expr ')'         { $$ = new AstBitsToRealD($1,$3); UNSUPREAL($1); }
-        |       yD_CEIL '(' expr ')'                    { $$ = new AstCeilD($1,$3); }
-        |       yD_CHANGED '(' expr ')'                 { $$ = new AstLogNot($1, new AstStable($1, $3)); }
+                yD_ACOS '(' expr ')'                    { $$ = new AstAcosD{$1, $3}; }
+        |       yD_ACOSH '(' expr ')'                   { $$ = new AstAcoshD{$1, $3}; }
+        |       yD_ASIN '(' expr ')'                    { $$ = new AstAsinD{$1, $3}; }
+        |       yD_ASINH '(' expr ')'                   { $$ = new AstAsinhD{$1, $3}; }
+        |       yD_ATAN '(' expr ')'                    { $$ = new AstAtanD{$1, $3}; }
+        |       yD_ATAN2 '(' expr ',' expr ')'          { $$ = new AstAtan2D{$1, $3, $5}; }
+        |       yD_ATANH '(' expr ')'                   { $$ = new AstAtanhD{$1, $3}; }
+        |       yD_BITS '(' exprOrDataType ')'          { $$ = new AstAttrOf{$1, VAttrType::DIM_BITS, $3}; }
+        |       yD_BITS '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf{$1, VAttrType::DIM_BITS, $3, $5}; }
+        |       yD_BITSTOREAL '(' expr ')'              { $$ = new AstBitsToRealD{$1, $3}; }
+        |       yD_BITSTOSHORTREAL '(' expr ')'         { $$ = new AstBitsToRealD{$1, $3}; UNSUPREAL($1); }
+        |       yD_CEIL '(' expr ')'                    { $$ = new AstCeilD{$1, $3}; }
+        |       yD_CHANGED '(' expr ')'                 { $$ = new AstLogNot{$1, new AstStable{$1, $3}}; }
         |       yD_CHANGED '(' expr ',' expr ')'        { $$ = $3; BBUNSUP($1, "Unsupported: $changed and clock arguments"); }
-        |       yD_CLOG2 '(' expr ')'                   { $$ = new AstCLog2($1,$3); }
-        |       yD_COS '(' expr ')'                     { $$ = new AstCosD($1,$3); }
-        |       yD_COSH '(' expr ')'                    { $$ = new AstCoshD($1,$3); }
-        |       yD_COUNTBITS '(' expr ',' expr ')'              { $$ = new AstCountBits($1,$3,$5); }
-        |       yD_COUNTBITS '(' expr ',' expr ',' expr ')'             { $$ = new AstCountBits($1,$3,$5,$7); }
-        |       yD_COUNTBITS '(' expr ',' expr ',' expr ',' expr ')'    { $$ = new AstCountBits($1,$3,$5,$7,$9); }
+        |       yD_CLOG2 '(' expr ')'                   { $$ = new AstCLog2{$1, $3}; }
+        |       yD_COS '(' expr ')'                     { $$ = new AstCosD{$1, $3}; }
+        |       yD_COSH '(' expr ')'                    { $$ = new AstCoshD{$1, $3}; }
+        |       yD_COUNTBITS '(' expr ',' expr ')'              { $$ = new AstCountBits{$1, $3, $5}; }
+        |       yD_COUNTBITS '(' expr ',' expr ',' expr ')'             { $$ = new AstCountBits{$1, $3, $5, $7}; }
+        |       yD_COUNTBITS '(' expr ',' expr ',' expr ',' expr ')'    { $$ = new AstCountBits{$1, $3, $5, $7, $9}; }
         |       yD_COUNTBITS '(' expr ',' expr ',' expr ',' expr ',' exprList ')'
-                        { $$ = new AstCountBits($1, $3, $5, $7, $9);
+                        { $$ = new AstCountBits{$1, $3, $5, $7, $9};
                           BBUNSUP($11, "Unsupported: $countbits with more than 3 control fields"); }
-        |       yD_COUNTONES '(' expr ')'               { $$ = new AstCountOnes($1,$3); }
-        |       yD_DIMENSIONS '(' exprOrDataType ')'    { $$ = new AstAttrOf($1,VAttrType::DIM_DIMENSIONS,$3); }
-        |       yD_EXP '(' expr ')'                     { $$ = new AstExpD($1,$3); }
-        |       yD_FELL '(' expr ')'                    { $$ = new AstFell($1,$3); }
+        |       yD_COUNTONES '(' expr ')'               { $$ = new AstCountOnes{$1, $3}; }
+        |       yD_DIMENSIONS '(' exprOrDataType ')'    { $$ = new AstAttrOf{$1, VAttrType::DIM_DIMENSIONS, $3}; }
+        |       yD_EXP '(' expr ')'                     { $$ = new AstExpD{$1, $3}; }
+        |       yD_FELL '(' expr ')'                    { $$ = new AstFell{$1, $3}; }
         |       yD_FELL '(' expr ',' expr ')'           { $$ = $3; BBUNSUP($1, "Unsupported: $fell and clock arguments"); }
-        |       yD_FEOF '(' expr ')'                    { $$ = new AstFEof($1,$3); }
-        |       yD_FERROR '(' idClassSel ',' idClassSel ')'     { $$ = new AstFError($1, $3, $5); }
-        |       yD_FGETC '(' expr ')'                   { $$ = new AstFGetC($1,$3); }
-        |       yD_FGETS '(' idClassSel ',' expr ')'    { $$ = new AstFGetS($1,$3,$5); }
-        |       yD_FREAD '(' idClassSel ',' expr ')'    { $$ = new AstFRead($1,$3,$5,nullptr,nullptr); }
-        |       yD_FREAD '(' idClassSel ',' expr ',' expr ')'   { $$ = new AstFRead($1,$3,$5,$7,nullptr); }
-        |       yD_FREAD '(' idClassSel ',' expr ',' expr ',' expr ')'  { $$ = new AstFRead($1,$3,$5,$7,$9); }
-        |       yD_FREWIND '(' idClassSel ')'           { $$ = new AstFRewind($1, $3); }
-        |       yD_FLOOR '(' expr ')'                   { $$ = new AstFloorD($1,$3); }
-        |       yD_FSCANF '(' expr ',' str commaVRDListE ')'    { $$ = new AstFScanF($1,*$5,$3,$6); }
-        |       yD_FSEEK '(' idClassSel ',' expr ',' expr ')'   { $$ = new AstFSeek($1,$3,$5,$7); }
-        |       yD_FTELL '(' idClassSel ')'             { $$ = new AstFTell($1, $3); }
-        |       yD_HIGH '(' exprOrDataType ')'          { $$ = new AstAttrOf($1,VAttrType::DIM_HIGH,$3,nullptr); }
-        |       yD_HIGH '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,VAttrType::DIM_HIGH,$3,$5); }
-        |       yD_HYPOT '(' expr ',' expr ')'          { $$ = new AstHypotD($1,$3,$5); }
-        |       yD_INCREMENT '(' exprOrDataType ')'     { $$ = new AstAttrOf($1,VAttrType::DIM_INCREMENT,$3,nullptr); }
-        |       yD_INCREMENT '(' exprOrDataType ',' expr ')'    { $$ = new AstAttrOf($1,VAttrType::DIM_INCREMENT,$3,$5); }
-        |       yD_ISUNBOUNDED '(' expr ')'             { $$ = new AstIsUnbounded($1, $3); }
-        |       yD_ISUNKNOWN '(' expr ')'               { $$ = new AstIsUnknown($1, $3); }
-        |       yD_ITOR '(' expr ')'                    { $$ = new AstIToRD($1,$3); }
-        |       yD_LEFT '(' exprOrDataType ')'          { $$ = new AstAttrOf($1,VAttrType::DIM_LEFT,$3,nullptr); }
-        |       yD_LEFT '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,VAttrType::DIM_LEFT,$3,$5); }
-        |       yD_LN '(' expr ')'                      { $$ = new AstLogD($1,$3); }
-        |       yD_LOG10 '(' expr ')'                   { $$ = new AstLog10D($1,$3); }
-        |       yD_LOW '(' exprOrDataType ')'           { $$ = new AstAttrOf($1,VAttrType::DIM_LOW,$3,nullptr); }
-        |       yD_LOW '(' exprOrDataType ',' expr ')'  { $$ = new AstAttrOf($1,VAttrType::DIM_LOW,$3,$5); }
-        |       yD_ONEHOT '(' expr ')'                  { $$ = new AstOneHot($1,$3); }
-        |       yD_ONEHOT0 '(' expr ')'                 { $$ = new AstOneHot0($1,$3); }
-        |       yD_PAST '(' expr ')'                    { $$ = new AstPast($1,$3, nullptr); }
-        |       yD_PAST '(' expr ',' expr ')'           { $$ = new AstPast($1,$3, $5); }
-        |       yD_PAST '(' expr ',' expr ',' expr ')'          { $$ = $3; BBUNSUP($1, "Unsupported: $past expr2 and clock arguments"); }
-        |       yD_PAST '(' expr ',' expr ',' expr ',' expr')'  { $$ = $3; BBUNSUP($1, "Unsupported: $past expr2 and clock arguments"); }
-        |       yD_POW '(' expr ',' expr ')'            { $$ = new AstPowD($1,$3,$5); }
-        |       yD_RANDOM '(' expr ')'                  { $$ = new AstRand($1, $3, false); }
-        |       yD_RANDOM parenE                        { $$ = new AstRand($1, nullptr, false); }
+        |       yD_FEOF '(' expr ')'                    { $$ = new AstFEof{$1, $3}; }
+        |       yD_FERROR '(' idClassSel ',' idClassSel ')'     { $$ = new AstFError{$1, $3, $5}; }
+        |       yD_FGETC '(' expr ')'                   { $$ = new AstFGetC{$1, $3}; }
+        |       yD_FGETS '(' idClassSel ',' expr ')'    { $$ = new AstFGetS{$1, $3, $5}; }
+        |       yD_FREAD '(' idClassSel ',' expr ')'    { $$ = new AstFRead{$1, $3, $5, nullptr, nullptr}; }
+        |       yD_FREAD '(' idClassSel ',' expr ',' expr ')'   { $$ = new AstFRead{$1, $3, $5, $7, nullptr}; }
+        |       yD_FREAD '(' idClassSel ',' expr ',' expr ',' expr ')'  { $$ = new AstFRead{$1, $3, $5, $7, $9}; }
+        |       yD_FREWIND '(' idClassSel ')'           { $$ = new AstFRewind{$1, $3}; }
+        |       yD_FLOOR '(' expr ')'                   { $$ = new AstFloorD{$1, $3}; }
+        |       yD_FSCANF '(' expr ',' str commaVRDListE ')'    { $$ = new AstFScanF{$1, *$5, $3, $6}; }
+        |       yD_FSEEK '(' idClassSel ',' expr ',' expr ')'   { $$ = new AstFSeek{$1, $3, $5, $7}; }
+        |       yD_FTELL '(' idClassSel ')'             { $$ = new AstFTell{$1, $3}; }
+        |       yD_HIGH '(' exprOrDataType ')'          { $$ = new AstAttrOf{$1, VAttrType::DIM_HIGH, $3, nullptr}; }
+        |       yD_HIGH '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf{$1, VAttrType::DIM_HIGH, $3, $5}; }
+        |       yD_HYPOT '(' expr ',' expr ')'          { $$ = new AstHypotD{$1, $3, $5}; }
+        |       yD_INCREMENT '(' exprOrDataType ')'     { $$ = new AstAttrOf{$1, VAttrType::DIM_INCREMENT, $3, nullptr}; }
+        |       yD_INCREMENT '(' exprOrDataType ',' expr ')'    { $$ = new AstAttrOf{$1, VAttrType::DIM_INCREMENT, $3, $5}; }
+        |       yD_ISUNBOUNDED '(' expr ')'             { $$ = new AstIsUnbounded{$1, $3}; }
+        |       yD_ISUNKNOWN '(' expr ')'               { $$ = new AstIsUnknown{$1, $3}; }
+        |       yD_ITOR '(' expr ')'                    { $$ = new AstIToRD{$1, $3}; }
+        |       yD_LEFT '(' exprOrDataType ')'          { $$ = new AstAttrOf{$1, VAttrType::DIM_LEFT, $3, nullptr}; }
+        |       yD_LEFT '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf{$1, VAttrType::DIM_LEFT, $3, $5}; }
+        |       yD_LN '(' expr ')'                      { $$ = new AstLogD{$1, $3}; }
+        |       yD_LOG10 '(' expr ')'                   { $$ = new AstLog10D{$1, $3}; }
+        |       yD_LOW '(' exprOrDataType ')'           { $$ = new AstAttrOf{$1, VAttrType::DIM_LOW, $3, nullptr}; }
+        |       yD_LOW '(' exprOrDataType ',' expr ')'  { $$ = new AstAttrOf{$1, VAttrType::DIM_LOW, $3, $5}; }
+        |       yD_ONEHOT '(' expr ')'                  { $$ = new AstOneHot{$1, $3}; }
+        |       yD_ONEHOT0 '(' expr ')'                 { $$ = new AstOneHot0{$1, $3}; }
+        |       yD_PAST '(' expr ')'                    { $$ = new AstPast{$1, $3, nullptr}; }
+        |       yD_PAST '(' expr ',' expr ')'           { $$ = new AstPast{$1, $3, $5}; }
+        |       yD_PAST '(' expr ',' expr ',' expr ')'
+                        { $$ = $3; BBUNSUP($1, "Unsupported: $past expr2 and clock arguments"); }
+        |       yD_PAST '(' expr ',' expr ',' expr ',' expr')'
+                        { $$ = $3; BBUNSUP($1, "Unsupported: $past expr2 and clock arguments"); }
+        |       yD_POW '(' expr ',' expr ')'            { $$ = new AstPowD{$1, $3, $5}; }
+        |       yD_RANDOM '(' expr ')'                  { $$ = new AstRand{$1, $3, false}; }
+        |       yD_RANDOM parenE                        { $$ = new AstRand{$1, nullptr, false}; }
         |       yD_REALTIME parenE                      { $$ = new AstTimeD{$1, VTimescale{VTimescale::NONE}}; }
-        |       yD_REALTOBITS '(' expr ')'              { $$ = new AstRealToBits($1,$3); }
-        |       yD_REWIND '(' idClassSel ')'            { $$ = new AstFSeek($1, $3, new AstConst($1, 0), new AstConst($1, 0)); }
-        |       yD_RIGHT '(' exprOrDataType ')'         { $$ = new AstAttrOf($1,VAttrType::DIM_RIGHT,$3,nullptr); }
-        |       yD_RIGHT '(' exprOrDataType ',' expr ')'        { $$ = new AstAttrOf($1,VAttrType::DIM_RIGHT,$3,$5); }
-        |       yD_ROSE '(' expr ')'                    { $$ = new AstRose($1,$3); }
+        |       yD_REALTOBITS '(' expr ')'              { $$ = new AstRealToBits{$1, $3}; }
+        |       yD_REWIND '(' idClassSel ')'            { $$ = new AstFSeek{$1, $3, new AstConst{$1, 0}, new AstConst{$1, 0}}; }
+        |       yD_RIGHT '(' exprOrDataType ')'         { $$ = new AstAttrOf{$1, VAttrType::DIM_RIGHT, $3, nullptr}; }
+        |       yD_RIGHT '(' exprOrDataType ',' expr ')'        { $$ = new AstAttrOf{$1, VAttrType::DIM_RIGHT, $3, $5}; }
+        |       yD_ROSE '(' expr ')'                    { $$ = new AstRose{$1, $3}; }
         |       yD_ROSE '(' expr ',' expr ')'           { $$ = $3; BBUNSUP($1, "Unsupported: $rose and clock arguments"); }
-        |       yD_RTOI '(' expr ')'                    { $$ = new AstRToIS($1,$3); }
-        |       yD_SAMPLED '(' expr ')'                 { $$ = new AstSampled($1, $3); }
-        |       yD_SFORMATF '(' exprDispList ')'        { $$ = new AstSFormatF($1, AstSFormatF::NoFormat(), $3, 'd', false); }
-        |       yD_SHORTREALTOBITS '(' expr ')'         { $$ = new AstRealToBits($1,$3); UNSUPREAL($1); }
-        |       yD_SIGNED '(' expr ')'                  { $$ = new AstSigned($1,$3); }
-        |       yD_SIN '(' expr ')'                     { $$ = new AstSinD($1,$3); }
-        |       yD_SINH '(' expr ')'                    { $$ = new AstSinhD($1,$3); }
-        |       yD_SIZE '(' exprOrDataType ')'          { $$ = new AstAttrOf($1,VAttrType::DIM_SIZE,$3,nullptr); }
-        |       yD_SIZE '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf($1,VAttrType::DIM_SIZE,$3,$5); }
-        |       yD_SQRT '(' expr ')'                    { $$ = new AstSqrtD($1,$3); }
-        |       yD_SSCANF '(' expr ',' str commaVRDListE ')'    { $$ = new AstSScanF($1,*$5,$3,$6); }
+        |       yD_RTOI '(' expr ')'                    { $$ = new AstRToIS{$1, $3}; }
+        |       yD_SAMPLED '(' expr ')'                 { $$ = new AstSampled{$1, $3}; }
+        |       yD_SFORMATF '(' exprDispList ')'        { $$ = new AstSFormatF{$1, AstSFormatF::NoFormat{}, $3, 'd', false}; }
+        |       yD_SHORTREALTOBITS '(' expr ')'         { $$ = new AstRealToBits{$1, $3}; UNSUPREAL($1); }
+        |       yD_SIGNED '(' expr ')'                  { $$ = new AstSigned{$1, $3}; }
+        |       yD_SIN '(' expr ')'                     { $$ = new AstSinD{$1, $3}; }
+        |       yD_SINH '(' expr ')'                    { $$ = new AstSinhD{$1, $3}; }
+        |       yD_SIZE '(' exprOrDataType ')'          { $$ = new AstAttrOf{$1, VAttrType::DIM_SIZE, $3, nullptr}; }
+        |       yD_SIZE '(' exprOrDataType ',' expr ')' { $$ = new AstAttrOf{$1, VAttrType::DIM_SIZE, $3, $5}; }
+        |       yD_SQRT '(' expr ')'                    { $$ = new AstSqrtD{$1, $3}; }
+        |       yD_SSCANF '(' expr ',' str commaVRDListE ')'    { $$ = new AstSScanF{$1, *$5, $3, $6}; }
         |       yD_STIME parenE
                         { $$ = new AstSel{$1, new AstTime{$1, VTimescale{VTimescale::NONE}}, 0, 32}; }
-        |       yD_STABLE '(' expr ')'                  { $$ = new AstStable($1,$3); }
+        |       yD_STABLE '(' expr ')'                  { $$ = new AstStable{$1, $3}; }
         |       yD_STABLE '(' expr ',' expr ')'         { $$ = $3; BBUNSUP($1, "Unsupported: $stable and clock arguments"); }
-        |       yD_TAN '(' expr ')'                     { $$ = new AstTanD($1,$3); }
-        |       yD_TANH '(' expr ')'                    { $$ = new AstTanhD($1,$3); }
-        |       yD_TESTPLUSARGS '(' expr ')'            { $$ = new AstTestPlusArgs($1, $3); }
+        |       yD_TAN '(' expr ')'                     { $$ = new AstTanD{$1, $3}; }
+        |       yD_TANH '(' expr ')'                    { $$ = new AstTanhD{$1, $3}; }
+        |       yD_TESTPLUSARGS '(' expr ')'            { $$ = new AstTestPlusArgs{$1, $3}; }
         |       yD_TIME parenE                          { $$ = new AstTime{$1, VTimescale{VTimescale::NONE}}; }
         |       yD_TIMEPRECISION                        { $$ = new AstTimePrecision{$1}; }
         |       yD_TIMEPRECISION '(' ')'                { $$ = new AstTimePrecision{$1}; }
@@ -4090,33 +4103,33 @@ system_f_call_or_t<nodeExprp>:      // IEEE: part of system_tf_call (can be task
         |       yD_TIMEUNIT                             { $$ = new AstTimeUnit{$1}; }
         |       yD_TIMEUNIT '(' ')'                     { $$ = new AstTimeUnit{$1}; }
         |       yD_TIMEUNIT '(' idClassSel ')'          { $$ = new AstTimeUnit{$1}; DEL($3); }
-        |       yD_TYPENAME '(' exprOrDataType ')'      { $$ = new AstAttrOf($1, VAttrType::TYPENAME, $3); }
-        |       yD_UNGETC '(' expr ',' expr ')'         { $$ = new AstFUngetC($1, $5, $3); }  // Arg swap to file first
-        |       yD_UNPACKED_DIMENSIONS '(' exprOrDataType ')'   { $$ = new AstAttrOf($1,VAttrType::DIM_UNPK_DIMENSIONS,$3); }
-        |       yD_UNSIGNED '(' expr ')'                { $$ = new AstUnsigned($1, $3); }
-        |       yD_URANDOM '(' expr ')'                 { $$ = new AstRand($1, $3, true); }
-        |       yD_URANDOM parenE                       { $$ = new AstRand($1, nullptr, true); }
-        |       yD_URANDOM_RANGE '(' expr ')'           { $$ = new AstURandomRange($1, $3, new AstConst($1, 0)); }
-        |       yD_URANDOM_RANGE '(' expr ',' expr ')'  { $$ = new AstURandomRange($1, $3, $5); }
-        |       yD_VALUEPLUSARGS '(' expr ',' expr ')'  { $$ = new AstValuePlusArgs($1, $3, $5); }
+        |       yD_TYPENAME '(' exprOrDataType ')'      { $$ = new AstAttrOf{$1, VAttrType::TYPENAME, $3}; }
+        |       yD_UNGETC '(' expr ',' expr ')'         { $$ = new AstFUngetC{$1, $5, $3}; }  // Arg swap to file first
+        |       yD_UNPACKED_DIMENSIONS '(' exprOrDataType ')'   { $$ = new AstAttrOf{$1, VAttrType::DIM_UNPK_DIMENSIONS, $3}; }
+        |       yD_UNSIGNED '(' expr ')'                { $$ = new AstUnsigned{$1, $3}; }
+        |       yD_URANDOM '(' expr ')'                 { $$ = new AstRand{$1, $3, true}; }
+        |       yD_URANDOM parenE                       { $$ = new AstRand{$1, nullptr, true}; }
+        |       yD_URANDOM_RANGE '(' expr ')'           { $$ = new AstURandomRange{$1, $3, new AstConst{$1, 0}}; }
+        |       yD_URANDOM_RANGE '(' expr ',' expr ')'  { $$ = new AstURandomRange{$1, $3, $5}; }
+        |       yD_VALUEPLUSARGS '(' expr ',' expr ')'  { $$ = new AstValuePlusArgs{$1, $3, $5}; }
         ;
 
 elaboration_system_task<nodep>: // IEEE: elaboration_system_task (1800-2009)
         //                      // TODO: These currently just make initial statements, should instead give runtime error
-                elaboration_system_task_guts ';'        { $$ = new AstInitial($<fl>1, $1); }
+                elaboration_system_task_guts ';'        { $$ = new AstInitial{$<fl>1, $1}; }
         ;
 
 elaboration_system_task_guts<nodep>:    // IEEE: part of elaboration_system_task (1800-2009)
         //                      // $fatal first argument is exit number, must be constant
-                yD_INFO    parenE                       { $$ = new AstElabDisplay($1, VDisplayType::DT_INFO, nullptr); }
-        |       yD_INFO    '(' exprList ')'             { $$ = new AstElabDisplay($1, VDisplayType::DT_INFO, $3); }
-        |       yD_WARNING parenE                       { $$ = new AstElabDisplay($1, VDisplayType::DT_WARNING, nullptr); }
-        |       yD_WARNING '(' exprList ')'             { $$ = new AstElabDisplay($1, VDisplayType::DT_WARNING, $3); }
-        |       yD_ERROR   parenE                       { $$ = new AstElabDisplay($1, VDisplayType::DT_ERROR, nullptr); }
-        |       yD_ERROR   '(' exprList ')'             { $$ = new AstElabDisplay($1, VDisplayType::DT_ERROR, $3); }
-        |       yD_FATAL   parenE                       { $$ = new AstElabDisplay($1, VDisplayType::DT_FATAL, nullptr); }
-        |       yD_FATAL   '(' expr ')'                 { $$ = new AstElabDisplay($1, VDisplayType::DT_FATAL, nullptr); DEL($3); }
-        |       yD_FATAL   '(' expr ',' exprListE ')'   { $$ = new AstElabDisplay($1, VDisplayType::DT_FATAL, $5); DEL($3); }
+                yD_INFO parenE                          { $$ = new AstElabDisplay{$1, VDisplayType::DT_INFO, nullptr}; }
+        |       yD_INFO '(' exprList ')'                { $$ = new AstElabDisplay{$1, VDisplayType::DT_INFO, $3}; }
+        |       yD_WARNING parenE                       { $$ = new AstElabDisplay{$1, VDisplayType::DT_WARNING, nullptr}; }
+        |       yD_WARNING '(' exprList ')'             { $$ = new AstElabDisplay{$1, VDisplayType::DT_WARNING, $3}; }
+        |       yD_ERROR parenE                         { $$ = new AstElabDisplay{$1, VDisplayType::DT_ERROR, nullptr}; }
+        |       yD_ERROR '(' exprList ')'               { $$ = new AstElabDisplay{$1, VDisplayType::DT_ERROR, $3}; }
+        |       yD_FATAL parenE                         { $$ = new AstElabDisplay{$1, VDisplayType::DT_FATAL, nullptr}; }
+        |       yD_FATAL '(' expr ')'                   { $$ = new AstElabDisplay{$1, VDisplayType::DT_FATAL, nullptr}; DEL($3); }
+        |       yD_FATAL '(' expr ',' exprListE ')'     { $$ = new AstElabDisplay{$1, VDisplayType::DT_FATAL, $5}; DEL($3); }
         ;
 
 //UNSUPproperty_actual_arg<nodep>:  // ==IEEE: property_actual_arg
@@ -4162,7 +4175,7 @@ task_declaration<nodeFTaskp>:   // ==IEEE: task_declaration
                 yTASK lifetimeE taskId tfGuts yENDTASK endLabelE
                         { $$ = $3; $$->addStmtsp($4); SYMP->popScope($$);
                           $$->lifetime($2);
-                          GRAMMARP->endLabel($<fl>6,$$,$6); }
+                          GRAMMARP->endLabel($<fl>6, $$, $6); }
         ;
 
 task_prototype<nodeFTaskp>:             // ==IEEE: task_prototype
@@ -4177,12 +4190,12 @@ function_declaration<nodeFTaskp>:       // IEEE: function_declaration + function
                         { $$ = $3; $3->attrIsolateAssign($4); $$->addStmtsp($5);
                           $$->lifetime($2);
                           SYMP->popScope($$);
-                          GRAMMARP->endLabel($<fl>7,$$,$7); }
+                          GRAMMARP->endLabel($<fl>7, $$, $7); }
         |       yFUNCTION lifetimeE funcIdNew funcIsolateE tfGuts yENDFUNCTION endLabelE
                         { $$ = $3; $3->attrIsolateAssign($4); $$->addStmtsp($5);
                           $$->lifetime($2);
                           SYMP->popScope($$);
-                          GRAMMARP->endLabel($<fl>7,$$,$7); }
+                          GRAMMARP->endLabel($<fl>7, $$, $7); }
         ;
 
 function_prototype<nodeFTaskp>: // IEEE: function_prototype
@@ -4222,16 +4235,16 @@ lifetime<lifetime>:             // ==IEEE: lifetime
 
 taskId<nodeFTaskp>:
                 id
-                        { $$ = new AstTask($<fl>$, *$1, nullptr);
+                        { $$ = new AstTask{$<fl>$, *$1, nullptr};
                           SYMP->pushNewUnderNodeOrCurrent($$, nullptr); }
         //
         |       id/*interface_identifier*/ '.' id
-                        { $$ = new AstTask($<fl>$, *$3, nullptr);
+                        { $$ = new AstTask{$<fl>$, *$3, nullptr};
                           BBUNSUP($2, "Unsupported: Out of block function declaration");
                           SYMP->pushNewUnderNodeOrCurrent($$, nullptr); }
         //
         |       packageClassScope id
-                        { $$ = new AstTask($<fl>$, *$2, nullptr);
+                        { $$ = new AstTask{$<fl>$, *$2, nullptr};
                           $$->classOrPackagep($1);
                           SYMP->pushNewUnderNodeOrCurrent($$, $<scp>1); }
         ;
@@ -4241,15 +4254,15 @@ funcId<nodeFTaskp>:                     // IEEE: function_data_type_or_implicit
         //                      // function_data_type expanded here to prevent conflicts with implicit_type:empty vs data_type:ID
                 /**/ fIdScoped
                         { $$ = $1;
-                          $$->fvarp(new AstBasicDType($<fl>1, LOGIC_IMPLICIT));
+                          $$->fvarp(new AstBasicDType{$<fl>1, LOGIC_IMPLICIT});
                           SYMP->pushNewUnderNodeOrCurrent($$, $<scp>1); }
         |       signingE rangeList fIdScoped
                         { $$ = $3;
-                          $$->fvarp(GRAMMARP->addRange(new AstBasicDType($<fl>3, LOGIC_IMPLICIT, $1), $2,true));
+                          $$->fvarp(GRAMMARP->addRange(new AstBasicDType{$<fl>3, LOGIC_IMPLICIT, $1}, $2, true));
                           SYMP->pushNewUnderNodeOrCurrent($$, $<scp>3); }
         |       signing fIdScoped
                         { $$ = $2;
-                          $$->fvarp(new AstBasicDType($<fl>2, LOGIC_IMPLICIT, $1));
+                          $$->fvarp(new AstBasicDType{$<fl>2, LOGIC_IMPLICIT, $1});
                           SYMP->pushNewUnderNodeOrCurrent($$, $<scp>2); }
         |       data_type fIdScoped
                         { $$ = $2;
@@ -4262,15 +4275,15 @@ funcId<nodeFTaskp>:                     // IEEE: function_data_type_or_implicit
 
 funcIdNew<nodeFTaskp>:          // IEEE: from class_constructor_declaration
                 yNEW__ETC
-                        { $$ = new AstFunc($<fl>1, "new", nullptr, nullptr);
+                        { $$ = new AstFunc{$<fl>1, "new", nullptr, nullptr};
                           $$->isConstructor(true);
                           SYMP->pushNewUnder($$, nullptr); }
         |       yNEW__PAREN
-                        { $$ = new AstFunc($<fl>1, "new", nullptr, nullptr);
+                        { $$ = new AstFunc{$<fl>1, "new", nullptr, nullptr};
                           $$->isConstructor(true);
                           SYMP->pushNewUnder($$, nullptr); }
         |       packageClassScopeNoId yNEW__PAREN
-                        { $$ = new AstFunc($<fl>2, "new", nullptr, nullptr);
+                        { $$ = new AstFunc{$<fl>2, "new", nullptr, nullptr};
                           $$->classOrPackagep($1);
                           $$->isConstructor(true);
                           SYMP->pushNewUnderNodeOrCurrent($$, $<scp>1); }
@@ -4281,18 +4294,18 @@ fIdScoped<funcp>:               // IEEE: part of function_body_declaration/task_
                 id
                         { $<fl>$ = $<fl>1;
                           $<scp>$ = nullptr;
-                          $$ = new AstFunc($<fl>$, *$1, nullptr, nullptr); }
+                          $$ = new AstFunc{$<fl>$, *$1, nullptr, nullptr}; }
         //
         |       id/*interface_identifier*/ '.' id
                         { $<fl>$ = $<fl>1;
                           $<scp>$ = nullptr;
-                          $$ = new AstFunc($<fl>$, *$1, nullptr, nullptr);
+                          $$ = new AstFunc{$<fl>$, *$1, nullptr, nullptr};
                           BBUNSUP($2, "Unsupported: Out of block function declaration"); }
         //
         |       packageClassScope id
                         { $<fl>$ = $<fl>1;
                           $<scp>$ = $<scp>1;
-                          $$ = new AstFunc($<fl>$, *$2, nullptr, nullptr);
+                          $$ = new AstFunc{$<fl>$, *$2, nullptr, nullptr};
                           $$->classOrPackagep($1); }
         ;
 
@@ -4320,8 +4333,8 @@ tf_item_declaration<nodep>:     // ==IEEE: tf_item_declaration
         ;
 
 tf_item_declarationVerilator<nodep>:    // Verilator extensions
-                yVL_PUBLIC                              { $$ = new AstPragma($1,VPragmaType::PUBLIC_TASK); v3Global.dpi(true); }
-        |       yVL_NO_INLINE_TASK                      { $$ = new AstPragma($1,VPragmaType::NO_INLINE_TASK); }
+                yVL_PUBLIC                              { $$ = new AstPragma{$1, VPragmaType::PUBLIC_TASK}; v3Global.dpi(true); }
+        |       yVL_NO_INLINE_TASK                      { $$ = new AstPragma{$1, VPragmaType::NO_INLINE_TASK}; }
         ;
 
 tf_port_listE<nodep>:           // IEEE: tf_port_list + empty
@@ -4345,15 +4358,25 @@ tf_port_item<nodep>:            // ==IEEE: tf_port_item
 
 tf_port_itemFront:              // IEEE: part of tf_port_item, which has the data type
                 data_type                               { VARDTYPE($1); }
-        |       signingE rangeList                      { VARDTYPE(GRAMMARP->addRange(new AstBasicDType($2->fileline(), LOGIC_IMPLICIT, $1), $2, true)); }
-        |       signing                                 { VARDTYPE(new AstBasicDType($<fl>1, LOGIC_IMPLICIT, $1)); }
+        |       signingE rangeList
+                        { AstNodeDType* const dtp = GRAMMARP->addRange(
+                              new AstBasicDType{$2->fileline(), LOGIC_IMPLICIT, $1}, $2, true);
+                          VARDTYPE(dtp); }
+        |       signing
+                        { AstNodeDType* const dtp = new AstBasicDType{$<fl>1, LOGIC_IMPLICIT, $1};
+                          VARDTYPE(dtp); }
         |       yVAR data_type                          { VARDTYPE($2); }
         |       yVAR implicit_typeE                     { VARDTYPE($2); }
         //
         |       tf_port_itemDir /*implicit*/            { VARDTYPE(nullptr); /*default_nettype-see spec*/ }
         |       tf_port_itemDir data_type               { VARDTYPE($2); }
-        |       tf_port_itemDir signingE rangeList      { VARDTYPE(GRAMMARP->addRange(new AstBasicDType($3->fileline(), LOGIC_IMPLICIT, $2),$3,true)); }
-        |       tf_port_itemDir signing                 { VARDTYPE(new AstBasicDType($<fl>2, LOGIC_IMPLICIT, $2)); }
+        |       tf_port_itemDir signingE rangeList
+                        { AstNodeDType* const dtp = GRAMMARP->addRange(
+                              new AstBasicDType{$3->fileline(), LOGIC_IMPLICIT, $2}, $3, true);
+                          VARDTYPE(dtp); }
+        |       tf_port_itemDir signing
+                        { AstNodeDType* const dtp = new AstBasicDType{$<fl>2, LOGIC_IMPLICIT, $2};
+                          VARDTYPE(dtp); }
         |       tf_port_itemDir yVAR data_type          { VARDTYPE($3); }
         |       tf_port_itemDir yVAR implicit_typeE     { VARDTYPE($3); }
         ;
@@ -4380,10 +4403,10 @@ parenE:
 //                              //   method_call_root not needed, part of expr resolution
 //                              // What's left is below array_methodNoRoot
 array_methodNoRoot<nodeFTaskRefp>:
-                yOR                                     { $$ = new AstFuncRef($1, "or", nullptr); }
-        |       yAND                                    { $$ = new AstFuncRef($1, "and", nullptr); }
-        |       yXOR                                    { $$ = new AstFuncRef($1, "xor", nullptr); }
-        |       yUNIQUE                                 { $$ = new AstFuncRef($1, "unique", nullptr); }
+                yOR                                     { $$ = new AstFuncRef{$1, "or", nullptr}; }
+        |       yAND                                    { $$ = new AstFuncRef{$1, "and", nullptr}; }
+        |       yXOR                                    { $$ = new AstFuncRef{$1, "xor", nullptr}; }
+        |       yUNIQUE                                 { $$ = new AstFuncRef{$1, "unique", nullptr}; }
         ;
 
 array_methodWith<nodeExprp>:
@@ -4391,7 +4414,7 @@ array_methodWith<nodeExprp>:
         |       array_methodNoRoot parenE yWITH__PAREN '(' expr ')'
                         { $$ = new AstWithParse{$3, $1, $5}; }
         |       array_methodNoRoot '(' expr ')' yWITH__PAREN '(' expr ')'
-                        { $$ = new AstWithParse{$5, $1, $7}; $1->addPinsp(new AstArg($<fl>3, "", $3)); }
+                        { $$ = new AstWithParse{$5, $1, $7}; $1->addPinsp(new AstArg{$<fl>3, "", $3}); }
         ;
 
 dpi_import_export<nodep>:       // ==IEEE: dpi_import_export
@@ -4403,7 +4426,7 @@ dpi_import_export<nodep>:       // ==IEEE: dpi_import_export
                           $5->dpiImport(true);
                           $5->dpiTraceInit($6);
                           GRAMMARP->checkDpiVer($1, *$2); v3Global.dpi(true);
-                          if ($$->prettyName()[0]=='$') SYMP->reinsert($$,nullptr,$$->prettyName());  // For $SysTF overriding
+                          if ($$->prettyName()[0]=='$') SYMP->reinsert($$, nullptr, $$->prettyName());  // For $SysTF overriding
                           SYMP->reinsert($$); }
         |       yIMPORT yaSTRING dpi_tf_import_propertyE dpi_importLabelE task_prototype ';'
                         { $$ = $5;
@@ -4413,7 +4436,7 @@ dpi_import_export<nodep>:       // ==IEEE: dpi_import_export
                           $5->dpiImport(true);
                           $5->dpiTask(true);
                           GRAMMARP->checkDpiVer($1, *$2); v3Global.dpi(true);
-                          if ($$->prettyName()[0]=='$') SYMP->reinsert($$,nullptr,$$->prettyName());  // For $SysTF overriding
+                          if ($$->prettyName()[0]=='$') SYMP->reinsert($$, nullptr, $$->prettyName());  // For $SysTF overriding
                           SYMP->reinsert($$); }
         |       yEXPORT yaSTRING dpi_importLabelE yFUNCTION idAny ';'
                         { $$ = new AstDpiExport{$<fl>5, *$5, *$3};
@@ -4472,15 +4495,15 @@ expr<nodeExprp>:                // IEEE: part of expression/constant_expression/
         //
         //                      // IEEE: unary_operator primary
                 '+' ~r~expr     %prec prUNARYARITH      { $$ = $2; }
-        |       '-' ~r~expr     %prec prUNARYARITH      { $$ = new AstNegate    ($1,$2); }
-        |       '!' ~r~expr     %prec prNEGATION        { $$ = new AstLogNot    ($1,$2); }
-        |       '&' ~r~expr     %prec prREDUCTION       { $$ = new AstRedAnd    ($1,$2); }
-        |       '~' ~r~expr     %prec prNEGATION        { $$ = new AstNot       ($1,$2); }
-        |       '|' ~r~expr     %prec prREDUCTION       { $$ = new AstRedOr     ($1,$2); }
-        |       '^' ~r~expr     %prec prREDUCTION       { $$ = new AstRedXor    ($1,$2); }
-        |       yP_NAND ~r~expr %prec prREDUCTION       { $$ = new AstLogNot($1, new AstRedAnd($1, $2)); }
-        |       yP_NOR  ~r~expr %prec prREDUCTION       { $$ = new AstLogNot($1, new AstRedOr($1, $2)); }
-        |       yP_XNOR ~r~expr %prec prREDUCTION       { $$ = new AstLogNot($1, new AstRedXor($1, $2)); }
+        |       '-' ~r~expr     %prec prUNARYARITH      { $$ = new AstNegate{$1, $2}; }
+        |       '!' ~r~expr     %prec prNEGATION        { $$ = new AstLogNot{$1, $2}; }
+        |       '&' ~r~expr     %prec prREDUCTION       { $$ = new AstRedAnd{$1, $2}; }
+        |       '~' ~r~expr     %prec prNEGATION        { $$ = new AstNot{$1, $2}; }
+        |       '|' ~r~expr     %prec prREDUCTION       { $$ = new AstRedOr{$1, $2}; }
+        |       '^' ~r~expr     %prec prREDUCTION       { $$ = new AstRedXor{$1, $2}; }
+        |       yP_NAND ~r~expr %prec prREDUCTION       { $$ = new AstLogNot{$1, new AstRedAnd{$1, $2}}; }
+        |       yP_NOR  ~r~expr %prec prREDUCTION       { $$ = new AstLogNot{$1, new AstRedOr{$1, $2}}; }
+        |       yP_XNOR ~r~expr %prec prREDUCTION       { $$ = new AstLogNot{$1, new AstRedXor{$1, $2}}; }
         //
         //                      // IEEE: inc_or_dec_expression
         |       ~l~inc_or_dec_expression                { $<fl>$ = $<fl>1; $$ = $1; }
@@ -4525,33 +4548,33 @@ expr<nodeExprp>:                // IEEE: part of expression/constant_expression/
                                                $2->cloneTree(true)}; }
         //
         //                      // IEEE: expression binary_operator expression
-        |       ~l~expr '+' ~r~expr                     { $$ = new AstAdd       ($2,$1,$3); }
-        |       ~l~expr '-' ~r~expr                     { $$ = new AstSub       ($2,$1,$3); }
-        |       ~l~expr '*' ~r~expr                     { $$ = new AstMul       ($2,$1,$3); }
-        |       ~l~expr '/' ~r~expr                     { $$ = new AstDiv       ($2,$1,$3); }
-        |       ~l~expr '%' ~r~expr                     { $$ = new AstModDiv    ($2,$1,$3); }
-        |       ~l~expr yP_EQUAL ~r~expr                { $$ = new AstEq        ($2,$1,$3); }
-        |       ~l~expr yP_NOTEQUAL ~r~expr             { $$ = new AstNeq       ($2,$1,$3); }
-        |       ~l~expr yP_CASEEQUAL ~r~expr            { $$ = new AstEqCase    ($2,$1,$3); }
-        |       ~l~expr yP_CASENOTEQUAL ~r~expr         { $$ = new AstNeqCase   ($2,$1,$3); }
-        |       ~l~expr yP_WILDEQUAL ~r~expr            { $$ = new AstEqWild    ($2,$1,$3); }
-        |       ~l~expr yP_WILDNOTEQUAL ~r~expr         { $$ = new AstNeqWild   ($2,$1,$3); }
-        |       ~l~expr yP_ANDAND ~r~expr               { $$ = new AstLogAnd    ($2,$1,$3); }
-        |       ~l~expr yP_OROR ~r~expr                 { $$ = new AstLogOr     ($2,$1,$3); }
-        |       ~l~expr yP_POW ~r~expr                  { $$ = new AstPow       ($2,$1,$3); }
-        |       ~l~expr '<' ~r~expr                     { $$ = new AstLt        ($2,$1,$3); }
-        |       ~l~expr '>' ~r~expr                     { $$ = new AstGt        ($2,$1,$3); }
-        |       ~l~expr yP_GTE ~r~expr                  { $$ = new AstGte       ($2,$1,$3); }
-        |       ~l~expr '&' ~r~expr                     { $$ = new AstAnd       ($2,$1,$3); }
-        |       ~l~expr '|' ~r~expr                     { $$ = new AstOr        ($2,$1,$3); }
-        |       ~l~expr '^' ~r~expr                     { $$ = new AstXor       ($2,$1,$3); }
+        |       ~l~expr '+' ~r~expr                     { $$ = new AstAdd{$2, $1, $3}; }
+        |       ~l~expr '-' ~r~expr                     { $$ = new AstSub{$2, $1, $3}; }
+        |       ~l~expr '*' ~r~expr                     { $$ = new AstMul{$2, $1, $3}; }
+        |       ~l~expr '/' ~r~expr                     { $$ = new AstDiv{$2, $1, $3}; }
+        |       ~l~expr '%' ~r~expr                     { $$ = new AstModDiv{$2, $1, $3}; }
+        |       ~l~expr yP_EQUAL ~r~expr                { $$ = new AstEq{$2, $1, $3}; }
+        |       ~l~expr yP_NOTEQUAL ~r~expr             { $$ = new AstNeq{$2, $1, $3}; }
+        |       ~l~expr yP_CASEEQUAL ~r~expr            { $$ = new AstEqCase{$2, $1, $3}; }
+        |       ~l~expr yP_CASENOTEQUAL ~r~expr         { $$ = new AstNeqCase{$2, $1, $3}; }
+        |       ~l~expr yP_WILDEQUAL ~r~expr            { $$ = new AstEqWild{$2, $1, $3}; }
+        |       ~l~expr yP_WILDNOTEQUAL ~r~expr         { $$ = new AstNeqWild{$2, $1, $3}; }
+        |       ~l~expr yP_ANDAND ~r~expr               { $$ = new AstLogAnd{$2, $1, $3}; }
+        |       ~l~expr yP_OROR ~r~expr                 { $$ = new AstLogOr{$2, $1, $3}; }
+        |       ~l~expr yP_POW ~r~expr                  { $$ = new AstPow{$2, $1, $3}; }
+        |       ~l~expr '<' ~r~expr                     { $$ = new AstLt{$2, $1, $3}; }
+        |       ~l~expr '>' ~r~expr                     { $$ = new AstGt{$2, $1, $3}; }
+        |       ~l~expr yP_GTE ~r~expr                  { $$ = new AstGte{$2, $1, $3}; }
+        |       ~l~expr '&' ~r~expr                     { $$ = new AstAnd{$2, $1, $3}; }
+        |       ~l~expr '|' ~r~expr                     { $$ = new AstOr{$2, $1, $3}; }
+        |       ~l~expr '^' ~r~expr                     { $$ = new AstXor{$2, $1, $3}; }
         |       ~l~expr yP_XNOR ~r~expr                 { $$ = new AstNot{$2, new AstXor{$2, $1, $3}}; }
         |       ~l~expr yP_NOR ~r~expr                  { $$ = new AstNot{$2, new AstOr{$2, $1, $3}}; }
         |       ~l~expr yP_NAND ~r~expr                 { $$ = new AstNot{$2, new AstAnd{$2, $1, $3}}; }
-        |       ~l~expr yP_SLEFT ~r~expr                { $$ = new AstShiftL    ($2,$1,$3); }
-        |       ~l~expr yP_SRIGHT ~r~expr               { $$ = new AstShiftR    ($2,$1,$3); }
-        |       ~l~expr yP_SSRIGHT ~r~expr              { $$ = new AstShiftRS   ($2,$1,$3); }
-        |       ~l~expr yP_LTMINUSGT ~r~expr            { $$ = new AstLogEq     ($2,$1,$3); }
+        |       ~l~expr yP_SLEFT ~r~expr                { $$ = new AstShiftL{$2, $1, $3}; }
+        |       ~l~expr yP_SRIGHT ~r~expr               { $$ = new AstShiftR{$2, $1, $3}; }
+        |       ~l~expr yP_SSRIGHT ~r~expr              { $$ = new AstShiftRS{$2, $1, $3}; }
+        |       ~l~expr yP_LTMINUSGT ~r~expr            { $$ = new AstLogEq{$2, $1, $3}; }
         //
         //                      // IEEE: expr yP_MINUSGT expr  (1800-2009)
         //                      // Conflicts with constraint_expression:"expr yP_MINUSGT constraint_set"
@@ -4559,17 +4582,17 @@ expr<nodeExprp>:                // IEEE: part of expression/constant_expression/
         //                      // Later Ast processing must ignore constraint terms where inappropriate
         //UNSUP ~l~expr yP_MINUSGT constraint_set               { $<fl>$ = $<fl>1; $$ = $1 + $2 + $3; }
         //UNSUP remove line below
-        |       ~l~expr yP_MINUSGT ~r~expr              { $$ = new AstLogIf($2, $1, $3); }
+        |       ~l~expr yP_MINUSGT ~r~expr              { $$ = new AstLogIf{$2, $1, $3}; }
         //
         //                      // <= is special, as we need to disambiguate it with <= assignment
         //                      // We copy all of expr to fexpr and rename this token to a fake one.
-        |       ~l~expr yP_LTE~f__IGNORE~ ~r~expr       { $$ = new AstLte($2, $1, $3); }
+        |       ~l~expr yP_LTE~f__IGNORE~ ~r~expr       { $$ = new AstLte{$2, $1, $3}; }
         //
         //                      // IEEE: conditional_expression
-        |       ~l~expr '?' ~r~expr ':' ~r~expr         { $$ = new AstCond($2,$1,$3,$5); }
+        |       ~l~expr '?' ~r~expr ':' ~r~expr         { $$ = new AstCond{$2, $1, $3, $5}; }
         //
         //                      // IEEE: inside_expression
-        |       ~l~expr yINSIDE '{' open_range_list '}' { $$ = new AstInside($2,$1,$4); }
+        |       ~l~expr yINSIDE '{' open_range_list '}' { $$ = new AstInside{$2, $1, $4}; }
         //
         //                      // IEEE: tagged_union_expression
         //UNSUP yTAGGED id/*member*/ %prec prTAGGED             { UNSUP }
@@ -4578,28 +4601,28 @@ expr<nodeExprp>:                // IEEE: part of expression/constant_expression/
         //======================// IEEE: primary/constant_primary
         //
         //                      // IEEE: primary_literal (minus string, which is handled specially)
-        |       yaINTNUM                                { $$ = new AstConst($<fl>1,*$1); }
-        |       yaFLOATNUM                              { $$ = new AstConst($<fl>1,AstConst::RealDouble(),$1); }
+        |       yaINTNUM                                { $$ = new AstConst{$<fl>1, *$1}; }
+        |       yaFLOATNUM                              { $$ = new AstConst{$<fl>1, AstConst::RealDouble{}, $1}; }
         |       timeNumAdjusted                         { $$ = $1; }
         |       strAsInt~noStr__IGNORE~                 { $$ = $1; }
         //
         //                      // IEEE: "... hierarchical_identifier select"  see below
         //
         //                      // IEEE: empty_queue (IEEE 1800-2017 empty_unpacked_array_concatenation)
-        |       '{' '}'                                 { $$ = new AstEmptyQueue($1); }
+        |       '{' '}'                                 { $$ = new AstEmptyQueue{$1}; }
         //
         //                      // IEEE: concatenation/constant_concatenation
         //                      // Part of exprOkLvalue below
         //
         //                      // IEEE: multiple_concatenation/constant_multiple_concatenation
-        |       '{' constExpr '{' cateList '}' '}'      { $$ = new AstReplicate($3, $4, $2); }
+        |       '{' constExpr '{' cateList '}' '}'      { $$ = new AstReplicate{$3, $4, $2}; }
         //                      // UNSUP some other rules above
         //
         |       function_subroutine_callNoMethod        { $$ = $1; }
         //                      // method_call
-        |       ~l~expr '.' function_subroutine_callNoMethod    { $$ = new AstDot($2, false, $1, $3); }
+        |       ~l~expr '.' function_subroutine_callNoMethod    { $$ = new AstDot{$2, false, $1, $3}; }
         //                      // method_call:array_method requires a '.'
-        |       ~l~expr '.' array_methodWith            { $$ = new AstDot($2, false, $1, $3); }
+        |       ~l~expr '.' array_methodWith            { $$ = new AstDot{$2, false, $1, $3}; }
         //
         //                      // IEEE: let_expression
         //                      // see funcRef
@@ -4613,16 +4636,18 @@ expr<nodeExprp>:                // IEEE: part of expression/constant_expression/
         //
         //                      // IEEE: cast/constant_cast
         //                      // expanded from casting_type
-        |       simple_type yP_TICK '(' expr ')'        { $$ = new AstCast($1->fileline(), $4, VFlagChildDType{}, $1); }
+        |       simple_type yP_TICK '(' expr ')'
+                        { $$ = new AstCast{$1->fileline(), $4, VFlagChildDType{}, $1}; }
         |       yTYPE '(' exprOrDataType ')' yP_TICK '(' expr ')'
-                        { $$ = new AstCast($1, $7, VFlagChildDType(), new AstRefDType($1, AstRefDType::FlagTypeOfExpr(), $3)); }
-        |       ySIGNED yP_TICK '(' expr ')'            { $$ = new AstSigned($1, $4); }
-        |       yUNSIGNED yP_TICK '(' expr ')'          { $$ = new AstUnsigned($1, $4); }
-        |       ySTRING yP_TICK '(' expr ')'            { $$ = new AstCvtPackString($1, $4); }
+                        { $$ = new AstCast{$1, $7, VFlagChildDType{},
+                                           new AstRefDType{$1, AstRefDType::FlagTypeOfExpr{}, $3}}; }
+        |       ySIGNED yP_TICK '(' expr ')'            { $$ = new AstSigned{$1, $4}; }
+        |       yUNSIGNED yP_TICK '(' expr ')'          { $$ = new AstUnsigned{$1, $4}; }
+        |       ySTRING yP_TICK '(' expr ')'            { $$ = new AstCvtPackString{$1, $4}; }
         |       yCONST__ETC yP_TICK '(' expr ')'        { $$ = $4; }  // Not linting const presently
         //                      // Spec only allows primary with addition of a type reference
         //                      // We'll be more general, and later assert LHS was a type.
-        |       ~l~expr yP_TICK '(' expr ')'            { $$ = new AstCastParse($2, $4, $1); }
+        |       ~l~expr yP_TICK '(' expr ')'            { $$ = new AstCastParse{$2, $4, $1}; }
         //
         //                      // IEEE: assignment_pattern_expression
         //                      // IEEE: streaming_concatenation
@@ -4631,8 +4656,8 @@ expr<nodeExprp>:                // IEEE: part of expression/constant_expression/
         //                      // IEEE: sequence_method_call
         //                      // Indistinguishable from function_subroutine_call:method_call
         //
-        |       '$'                                     { $$ = new AstUnbounded($<fl>1); }
-        |       yNULL                                   { $$ = new AstConst($1, AstConst::Null{}); }
+        |       '$'                                     { $$ = new AstUnbounded{$<fl>1}; }
+        |       yNULL                                   { $$ = new AstConst{$1, AstConst::Null{}}; }
         //                      // IEEE: yTHIS
         //                      // See exprScope
         //
@@ -4645,7 +4670,7 @@ expr<nodeExprp>:                // IEEE: part of expression/constant_expression/
         //
         //                      // IEEE: cond_predicate - here to avoid reduce problems
         //                      // Note expr includes cond_pattern
-        |       ~l~expr yP_ANDANDAND ~r~expr            { $$ = new AstConst($2, AstConst::BitFalse());
+        |       ~l~expr yP_ANDANDAND ~r~expr            { $$ = new AstConst{$2, AstConst::BitFalse{}};
                                                           BBUNSUP($<fl>2, "Unsupported: &&& expression"); }
         //
         //                      // IEEE: cond_pattern - here to avoid reduce problems
@@ -4700,14 +4725,14 @@ exprOkLvalue<nodeExprp>:            // expression that's also OK to use as a var
                 ~l~exprScope                            { $$ = $1; }
         //                      // IEEE: concatenation/constant_concatenation
         //                      // Replicate(1) required as otherwise "{a}" would not be self-determined
-        |       '{' cateList '}'                        { $$ = new AstReplicate($1,$2,1); }
-        |       '{' cateList '}' '[' expr ']'           { $$ = new AstSelBit($4, new AstReplicate($1,$2,1), $5); }
+        |       '{' cateList '}'                        { $$ = new AstReplicate{$1, $2, 1}; }
+        |       '{' cateList '}' '[' expr ']'           { $$ = new AstSelBit{$4, new AstReplicate{$1, $2, 1}, $5}; }
         |       '{' cateList '}' '[' constExpr ':' constExpr ']'
-                                                        { $$ = new AstSelExtract($4, new AstReplicate($1,$2,1), $5, $7); }
+                                                        { $$ = new AstSelExtract{$4, new AstReplicate{$1, $2, 1}, $5, $7}; }
         |       '{' cateList '}' '[' expr yP_PLUSCOLON constExpr ']'
-                                                        { $$ = new AstSelPlus($4, new AstReplicate($1,$2,1), $5, $7); }
+                                                        { $$ = new AstSelPlus{$4, new AstReplicate{$1, $2, 1}, $5, $7}; }
         |       '{' cateList '}' '[' expr yP_MINUSCOLON constExpr ']'
-                                                        { $$ = new AstSelMinus($4, new AstReplicate($1,$2,1), $5, $7); }
+                                                        { $$ = new AstSelMinus{$4, new AstReplicate{$1, $2, 1}, $5, $7}; }
         //                      // IEEE: assignment_pattern_expression
         //                      // IEEE: [ assignment_pattern_expression_type ] == [ ps_type_id /ps_paremeter_id/data_type]
         //                      // We allow more here than the spec requires
@@ -4750,15 +4775,15 @@ exprScope<nodeExprp>:               // scope and variable for use to inside an e
         //                      // IEEE: [ implicit_class_handle . | class_scope | package_scope ] hierarchical_identifier select
         //                      // Or method_call_body without parenthesis
         //                      // See also varRefClassBit, which is the non-expr version of most of this
-                yTHIS                                   { $$ = new AstParseRef($<fl>1, VParseRefExp::PX_ROOT, "this"); }
-        |       yD_ROOT                                 { $$ = new AstParseRef($<fl>1, VParseRefExp::PX_ROOT, "$root"); }
+                yTHIS                                   { $$ = new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "this"}; }
+        |       yD_ROOT                                 { $$ = new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "$root"}; }
         |       idArrayed                               { $$ = $1; }
         |       packageClassScope idArrayed             { $$ = AstDot::newIfPkg($2->fileline(), $1, $2); }
-        |       ~l~expr '.' idArrayed                   { $$ = new AstDot($<fl>2, false, $1, $3); }
+        |       ~l~expr '.' idArrayed                   { $$ = new AstDot{$<fl>2, false, $1, $3}; }
         //                      // expr below must be a "yTHIS"
         |       ~l~expr '.' ySUPER                      { $$ = $1; BBUNSUP($3, "Unsupported: super"); }
         //                      // Part of implicit_class_handle
-        |       ySUPER                                  { $$ = new AstParseRef($<fl>1, VParseRefExp::PX_ROOT, "super"); }
+        |       ySUPER                                  { $$ = new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "super"}; }
         ;
 
 fexprScope<nodeExprp>:              // exprScope, For use as first part of statement (disambiguates <=)
@@ -4796,7 +4821,7 @@ cStrList<nodep>:
 cateList<nodeExprp>:
         //                      // Not just 'expr' to prevent conflict via stream_concOrExprOrType
                 stream_expression                       { $$ = $1; }
-        |       cateList ',' stream_expression          { $$ = new AstConcat($2,$1,$3); }
+        |       cateList ',' stream_expression          { $$ = new AstConcat{$2, $1, $3}; }
         ;
 
 exprListE<nodeExprp>:
@@ -4814,7 +4839,7 @@ exprDispList<nodeExprp>:            // exprList for within $display
         |       exprDispList ',' expr                   { $$ = $1->addNext($3); }
         //                      // ,, creates a space in $display
         |       exprDispList ',' /*empty*/
-                        { $$ = $1->addNext(new AstConst($<fl>2, AstConst::VerilogStringLiteral(), " ")); }
+                        { $$ = $1->addNext(new AstConst{$<fl>2, AstConst::VerilogStringLiteral{}, " "}); }
         ;
 
 vrdList<nodep>:
@@ -4843,8 +4868,8 @@ argsExprListE<nodeExprp>:       // IEEE: part of list_of_arguments
 //UNSUP ;
 
 argsExprOneE<nodeExprp>:        // IEEE: part of list_of_arguments
-                /*empty*/                               { $$ = new AstArg(CRELINE(), "", nullptr); }
-        |       expr                                    { $$ = new AstArg($1->fileline(), "", $1); }
+                /*empty*/                               { $$ = new AstArg{CRELINE(), "", nullptr}; }
+        |       expr                                    { $$ = new AstArg{$1->fileline(), "", $1}; }
         ;
 
 //UNSUPpev_argsExprOneE<nodep>:  // IEEE: part of list_of_arguments - pev_expr at bottom
@@ -4863,13 +4888,13 @@ argsDottedList<nodeExprp>:      // IEEE: part of list_of_arguments
 //UNSUP ;
 
 argsDotted<nodeExprp>:          // IEEE: part of list_of_arguments
-                '.' idAny '(' ')'                       { $$ = new AstArg($<fl>2, *$2, nullptr); }
-        |       '.' idAny '(' expr ')'                  { $$ = new AstArg($<fl>2, *$2, $4); }
+                '.' idAny '(' ')'                       { $$ = new AstArg{$<fl>2, *$2, nullptr}; }
+        |       '.' idAny '(' expr ')'                  { $$ = new AstArg{$<fl>2, *$2, $4}; }
         ;
 
 //UNSUPpev_argsDotted<nodep>:  // IEEE: part of list_of_arguments - pev_expr at bottom
-//UNSUP         '.' idAny '(' ')'                       { $$ = new AstArg($<fl>2, *$2, nullptr); }
-//UNSUP |       '.' idAny '(' pev_expr ')'              { $$ = new AstArg($<fl>2, *$2, $4); }
+//UNSUP         '.' idAny '(' ')'                       { $$ = new AstArg{$<fl>2, *$2, nullptr}; }
+//UNSUP |       '.' idAny '(' pev_expr ')'              { $$ = new AstArg{$<fl>2, *$2, $4}; }
 //UNSUP ;
 
 streaming_concatenation<nodeStreamp>: // ==IEEE: streaming_concatenation
@@ -4881,9 +4906,9 @@ streaming_concatenation<nodeStreamp>: // ==IEEE: streaming_concatenation
         //                      // IEEE: "'{' yP_SL/R simple_type stream_concatenation '}'"
         //                      // IEEE: "'{' yP_SL/R constExpr   stream_concatenation '}'"
                 '{' yP_SLEFT  stream_concatenation '}'
-                        { $$ = new AstStreamL($2, $3, new AstConst($2, 1)); }
+                        { $$ = new AstStreamL{$2, $3, new AstConst{$2, 1}}; }
         |       '{' yP_SRIGHT stream_concatenation '}'
-                        { $$ = new AstStreamR($2, $3, new AstConst($2, 1)); }
+                        { $$ = new AstStreamR{$2, $3, new AstConst{$2, 1}}; }
         |       '{' yP_SLEFT  stream_expressionOrDataType stream_concatenation '}'
                         { AstNodeExpr* const bitsp = VN_IS($3, NodeExpr) ? VN_AS($3, NodeExpr)
                                                                          : new AstAttrOf{$1, VAttrType::DIM_BITS, $3};
@@ -4920,33 +4945,33 @@ stream_expressionOrDataType<nodep>:     // IEEE: from streaming_concatenation
 // Gate declarations
 
 gateDecl<nodep>:
-                yBUF      driveStrengthE delay_controlE gateBufList ';'        { $$ = $4; STRENGTHUNSUP($2); PUT_DLYS_IN_ASSIGNS($3, $4); }
-        |       yBUFIF0   driveStrengthE delay_controlE gateBufif0List ';'     { $$ = $4; STRENGTHUNSUP($2); PUT_DLYS_IN_ASSIGNS($3, $4); }
-        |       yBUFIF1   driveStrengthE delay_controlE gateBufif1List ';'     { $$ = $4; STRENGTHUNSUP($2); PUT_DLYS_IN_ASSIGNS($3, $4); }
-        |       yNOT      driveStrengthE delay_controlE gateNotList ';'        { $$ = $4; APPLY_STRENGTH_TO_LIST($4, $2, AssignW); PUT_DLYS_IN_ASSIGNS($3, $4); }
-        |       yNOTIF0   driveStrengthE delay_controlE gateNotif0List ';'     { $$ = $4; STRENGTHUNSUP($2); PUT_DLYS_IN_ASSIGNS($3, $4); }
-        |       yNOTIF1   driveStrengthE delay_controlE gateNotif1List ';'     { $$ = $4; STRENGTHUNSUP($2); PUT_DLYS_IN_ASSIGNS($3, $4); }
-        |       yAND      driveStrengthE delay_controlE gateAndList ';'        { $$ = $4; APPLY_STRENGTH_TO_LIST($4, $2, AssignW); PUT_DLYS_IN_ASSIGNS($3, $4); }
-        |       yNAND     driveStrengthE delay_controlE gateNandList ';'       { $$ = $4; APPLY_STRENGTH_TO_LIST($4, $2, AssignW); PUT_DLYS_IN_ASSIGNS($3, $4); }
-        |       yOR       driveStrengthE delay_controlE gateOrList ';'         { $$ = $4; APPLY_STRENGTH_TO_LIST($4, $2, AssignW); PUT_DLYS_IN_ASSIGNS($3, $4); }
-        |       yNOR      driveStrengthE delay_controlE gateNorList ';'        { $$ = $4; APPLY_STRENGTH_TO_LIST($4, $2, AssignW); PUT_DLYS_IN_ASSIGNS($3, $4); }
-        |       yXOR      driveStrengthE delay_controlE gateXorList ';'        { $$ = $4; APPLY_STRENGTH_TO_LIST($4, $2, AssignW); PUT_DLYS_IN_ASSIGNS($3, $4); }
-        |       yXNOR     driveStrengthE delay_controlE gateXnorList ';'       { $$ = $4; APPLY_STRENGTH_TO_LIST($4, $2, AssignW); PUT_DLYS_IN_ASSIGNS($3, $4); }
-        |       yPULLUP   delay_controlE gatePullupList ';'     { $$ = $3; PUT_DLYS_IN_ASSIGNS($2, $3); }
-        |       yPULLDOWN delay_controlE gatePulldownList ';'   { $$ = $3; PUT_DLYS_IN_ASSIGNS($2, $3); }
-        |       yNMOS     delay_controlE gateBufif1List ';'     { $$ = $3; PUT_DLYS_IN_ASSIGNS($2, $3); }
-        |       yPMOS     delay_controlE gateBufif0List ';'     { $$ = $3; PUT_DLYS_IN_ASSIGNS($2, $3); }
+                yBUF    driveStrengthE delay_controlE gateBufList ';'     { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($3, $4); }
+        |       yBUFIF0 driveStrengthE delay_controlE gateBufif0List ';'  { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($3, $4); }
+        |       yBUFIF1 driveStrengthE delay_controlE gateBufif1List ';'  { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($3, $4); }
+        |       yNOT    driveStrengthE delay_controlE gateNotList ';'     { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
+        |       yNOTIF0 driveStrengthE delay_controlE gateNotif0List ';'  { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($3, $4); }
+        |       yNOTIF1 driveStrengthE delay_controlE gateNotif1List ';'  { $$ = $4; STRENGTHUNSUP($2); DELAY_LIST($3, $4); }
+        |       yAND    driveStrengthE delay_controlE gateAndList ';'     { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
+        |       yNAND   driveStrengthE delay_controlE gateNandList ';'    { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
+        |       yOR     driveStrengthE delay_controlE gateOrList ';'      { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
+        |       yNOR    driveStrengthE delay_controlE gateNorList ';'     { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
+        |       yXOR    driveStrengthE delay_controlE gateXorList ';'     { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
+        |       yXNOR   driveStrengthE delay_controlE gateXnorList ';'    { $$ = $4; STRENGTH_LIST($4, $2, AssignW); DELAY_LIST($3, $4); }
+        |       yPULLUP   delay_controlE gatePullupList ';'     { $$ = $3; DELAY_LIST($2, $3); }
+        |       yPULLDOWN delay_controlE gatePulldownList ';'   { $$ = $3; DELAY_LIST($2, $3); }
+        |       yNMOS     delay_controlE gateBufif1List ';'     { $$ = $3; DELAY_LIST($2, $3); }
+        |       yPMOS     delay_controlE gateBufif0List ';'     { $$ = $3; DELAY_LIST($2, $3); }
         //
-        |       yTRAN delay_controlE gateUnsupList ';'          { $$ = $3; GATEUNSUP($3,"tran"); } // Unsupported
-        |       yRCMOS delay_controlE gateUnsupList ';'         { $$ = $3; GATEUNSUP($3,"rcmos"); } // Unsupported
-        |       yCMOS delay_controlE gateUnsupList ';'          { $$ = $3; GATEUNSUP($3,"cmos"); } // Unsupported
-        |       yRNMOS delay_controlE gateUnsupList ';'         { $$ = $3; GATEUNSUP($3,"rmos"); } // Unsupported
-        |       yRPMOS delay_controlE gateUnsupList ';'         { $$ = $3; GATEUNSUP($3,"pmos"); } // Unsupported
-        |       yRTRAN delay_controlE gateUnsupList ';'         { $$ = $3; GATEUNSUP($3,"rtran"); } // Unsupported
-        |       yRTRANIF0 delay_controlE gateUnsupList ';'      { $$ = $3; GATEUNSUP($3,"rtranif0"); } // Unsupported
-        |       yRTRANIF1 delay_controlE gateUnsupList ';'      { $$ = $3; GATEUNSUP($3,"rtranif1"); } // Unsupported
-        |       yTRANIF0 delay_controlE gateUnsupList ';'       { $$ = $3; GATEUNSUP($3,"tranif0"); } // Unsupported
-        |       yTRANIF1 delay_controlE gateUnsupList ';'       { $$ = $3; GATEUNSUP($3,"tranif1"); } // Unsupported
+        |       yTRAN delay_controlE gateUnsupList ';'          { $$ = $3; GATEUNSUP($3, "tran"); }
+        |       yRCMOS delay_controlE gateUnsupList ';'         { $$ = $3; GATEUNSUP($3, "rcmos"); }
+        |       yCMOS delay_controlE gateUnsupList ';'          { $$ = $3; GATEUNSUP($3, "cmos"); }
+        |       yRNMOS delay_controlE gateUnsupList ';'         { $$ = $3; GATEUNSUP($3, "rmos"); }
+        |       yRPMOS delay_controlE gateUnsupList ';'         { $$ = $3; GATEUNSUP($3, "pmos"); }
+        |       yRTRAN delay_controlE gateUnsupList ';'         { $$ = $3; GATEUNSUP($3, "rtran"); }
+        |       yRTRANIF0 delay_controlE gateUnsupList ';'      { $$ = $3; GATEUNSUP($3, "rtranif0"); }
+        |       yRTRANIF1 delay_controlE gateUnsupList ';'      { $$ = $3; GATEUNSUP($3, "rtranif1"); }
+        |       yTRANIF0 delay_controlE gateUnsupList ';'       { $$ = $3; GATEUNSUP($3, "tranif0"); }
+        |       yTRANIF1 delay_controlE gateUnsupList ';'       { $$ = $3; GATEUNSUP($3, "tranif1"); }
         ;
 
 gateBufList<nodep>:
@@ -5022,59 +5047,59 @@ gateBuf<nodep>:
         ;
 gateBufif0<nodep>:
                 gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'
-                        { $$ = new AstAssignW($<fl>1, $2, new AstBufIf1($<fl>1, new AstNot($<fl>1, $6), $4)); DEL($1); }
+                        { $$ = new AstAssignW{$<fl>1, $2, new AstBufIf1{$<fl>1, new AstNot{$<fl>1, $6}, $4}}; DEL($1); }
         ;
 gateBufif1<nodep>:
                 gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'
-                        { $$ = new AstAssignW($<fl>1, $2, new AstBufIf1($<fl>1, $6, $4)); DEL($1); }
+                        { $$ = new AstAssignW{$<fl>1, $2, new AstBufIf1{$<fl>1, $6, $4}}; DEL($1); }
         ;
 gateNot<nodep>:
                 gateFront variable_lvalue ',' gatePinExpr ')'
-                        { $$ = new AstAssignW($<fl>1, $2, new AstNot($<fl>1, $4)); DEL($1); }
+                        { $$ = new AstAssignW{$<fl>1, $2, new AstNot{$<fl>1, $4}}; DEL($1); }
         // UNSUP                        // IEEE: Multiple output variable_lvalues
         // UNSUP                        // Causes conflict - need to take in variable_lvalue or a gatePinExpr
         ;
 gateNotif0<nodep>:
                 gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'
-                        { $$ = new AstAssignW($<fl>1, $2, new AstBufIf1($<fl>1, new AstNot($<fl>1, $6),
-                                                                        new AstNot($<fl>1, $4))); DEL($1); }
+                        { $$ = new AstAssignW{$<fl>1, $2, new AstBufIf1{$<fl>1, new AstNot{$<fl>1, $6},
+                                                                        new AstNot{$<fl>1, $4}}}; DEL($1); }
         ;
 gateNotif1<nodep>:
                 gateFront variable_lvalue ',' gatePinExpr ',' gatePinExpr ')'
-                        { $$ = new AstAssignW($<fl>1, $2, new AstBufIf1($<fl>1, $6, new AstNot($<fl>1, $4))); DEL($1); }
+                        { $$ = new AstAssignW{$<fl>1, $2, new AstBufIf1{$<fl>1, $6, new AstNot{$<fl>1, $4}}}; DEL($1); }
         ;
 gateAnd<nodep>:
                 gateFront variable_lvalue ',' gateAndPinList ')'
-                        { $$ = new AstAssignW($<fl>1, $2, $4); DEL($1); }
+                        { $$ = new AstAssignW{$<fl>1, $2, $4}; DEL($1); }
         ;
 gateNand<nodep>:
                 gateFront variable_lvalue ',' gateAndPinList ')'
-                        { $$ = new AstAssignW($<fl>1, $2, new AstNot($<fl>1, $4)); DEL($1); }
+                        { $$ = new AstAssignW{$<fl>1, $2, new AstNot{$<fl>1, $4}}; DEL($1); }
         ;
 gateOr<nodep>:
                 gateFront variable_lvalue ',' gateOrPinList ')'
-                        { $$ = new AstAssignW($<fl>1, $2, $4); DEL($1); }
+                        { $$ = new AstAssignW{$<fl>1, $2, $4}; DEL($1); }
         ;
 gateNor<nodep>:
                 gateFront variable_lvalue ',' gateOrPinList ')'
-                        { $$ = new AstAssignW($<fl>1, $2, new AstNot($<fl>1, $4)); DEL($1); }
+                        { $$ = new AstAssignW{$<fl>1, $2, new AstNot{$<fl>1, $4}}; DEL($1); }
         ;
 gateXor<nodep>:
                 gateFront variable_lvalue ',' gateXorPinList ')'
-                        { $$ = new AstAssignW($<fl>1, $2, $4); DEL($1); }
+                        { $$ = new AstAssignW{$<fl>1, $2, $4}; DEL($1); }
         ;
 gateXnor<nodep>:
                 gateFront variable_lvalue ',' gateXorPinList ')'
-                        { $$ = new AstAssignW($<fl>1, $2, new AstNot($<fl>1, $4)); DEL($1); }
+                        { $$ = new AstAssignW{$<fl>1, $2, new AstNot{$<fl>1, $4}}; DEL($1); }
         ;
 gatePullup<nodep>:
-                gateFront variable_lvalue ')'           { $$ = new AstPull($<fl>1, $2, true); DEL($1); }
+                gateFront variable_lvalue ')'           { $$ = new AstPull{$<fl>1, $2, true}; DEL($1); }
         ;
 gatePulldown<nodep>:
-                gateFront variable_lvalue ')'           { $$ = new AstPull($<fl>1, $2, false); DEL($1); }
+                gateFront variable_lvalue ')'           { $$ = new AstPull{$<fl>1, $2, false}; DEL($1); }
         ;
 gateUnsup<nodep>:
-                gateFront gateUnsupPinList ')'          { $$ = new AstImplicit($<fl>1, $2); DEL($1); }
+                gateFront gateUnsupPinList ')'          { $$ = new AstImplicit{$<fl>1, $2}; DEL($1); }
         ;
 
 gateFront<nodep>:
@@ -5232,7 +5257,7 @@ variable_lvalue<nodeExprp>:         // IEEE: variable_lvalue or net_lvalue
 
 variable_lvalueConcList<nodeExprp>: // IEEE: part of variable_lvalue: '{' variable_lvalue { ',' variable_lvalue } '}'
                 variable_lvalue                                 { $$ = $1; }
-        |       variable_lvalueConcList ',' variable_lvalue     { $$ = new AstConcat($2,$1,$3); }
+        |       variable_lvalueConcList ',' variable_lvalue     { $$ = new AstConcat{$2, $1, $3}; }
         ;
 
 //UNSUPvariable_lvalueList<nodep>:  // IEEE: part of variable_lvalue: variable_lvalue { ',' variable_lvalue }
@@ -5245,46 +5270,46 @@ idClassSel<nodeExprp>:                      // Misc Ref to dotted, and/or arraye
                 idDotted                                { $$ = $1; }
         //                      // IEEE: [ implicit_class_handle . | package_scope ] hierarchical_variable_identifier select
         |       yTHIS '.' idDotted
-                        { $$ = new AstDot($2, false, new AstParseRef($<fl>1, VParseRefExp::PX_ROOT, "this"), $3); }
+                        { $$ = new AstDot{$2, false, new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "this"}, $3}; }
         |       ySUPER '.' idDotted
-                        { $$ = new AstDot($2, false, new AstParseRef($<fl>1, VParseRefExp::PX_ROOT, "super"), $3); }
+                        { $$ = new AstDot{$2, false, new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "super"}, $3}; }
         |       yTHIS '.' ySUPER '.' idDotted           { $$ = $5; BBUNSUP($1, "Unsupported: this.super"); }
         //                      // Expanded: package_scope idDotted
-        |       packageClassScope idDotted              { $$ = new AstDot($<fl>2, true, $1, $2); }
+        |       packageClassScope idDotted              { $$ = new AstDot{$<fl>2, true, $1, $2}; }
         ;
 
 idClassSelForeach<nodeExprp>:
                 idDottedForeach                         { $$ = $1; }
         //                      // IEEE: [ implicit_class_handle . | package_scope ] hierarchical_variable_identifier select
         |       yTHIS '.' idDottedForeach
-                        { $$ = new AstDot($2, false, new AstParseRef($<fl>1, VParseRefExp::PX_ROOT, "this"), $3); }
+                        { $$ = new AstDot{$2, false, new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "this"}, $3}; }
         |       ySUPER '.' idDottedForeach
-                        { $$ = new AstDot($2, false, new AstParseRef($<fl>1, VParseRefExp::PX_ROOT, "super"), $3); }
+                        { $$ = new AstDot{$2, false, new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "super"}, $3}; }
         |       yTHIS '.' ySUPER '.' idDottedForeach    { $$ = $5; BBUNSUP($1, "Unsupported: this.super"); }
         //                      // Expanded: package_scope idForeach
-        |       packageClassScope idDottedForeach       { $$ = new AstDot($<fl>2, true, $1, $2); }
+        |       packageClassScope idDottedForeach       { $$ = new AstDot{$<fl>2, true, $1, $2}; }
         ;
 
 idDotted<nodeExprp>:
                 yD_ROOT '.' idDottedMore
-                        { $$ = new AstDot($2, false, new AstParseRef($<fl>1, VParseRefExp::PX_ROOT, "$root"), $3); }
+                        { $$ = new AstDot{$2, false, new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "$root"}, $3}; }
         |       idDottedMore                            { $$ = $1; }
         ;
 
 idDottedForeach<nodeExprp>:
                 yD_ROOT '.' idDottedMoreForeach
-                        { $$ = new AstDot($2, false, new AstParseRef($<fl>1, VParseRefExp::PX_ROOT, "$root"), $3); }
+                        { $$ = new AstDot{$2, false, new AstParseRef{$<fl>1, VParseRefExp::PX_ROOT, "$root"}, $3}; }
         |       idDottedMoreForeach                     { $$ = $1; }
         ;
 
 idDottedMore<nodeExprp>:
                 idArrayed                               { $$ = $1; }
-        |       idDottedMore '.' idArrayed              { $$ = new AstDot($2, false, $1, $3); }
+        |       idDottedMore '.' idArrayed              { $$ = new AstDot{$2, false, $1, $3}; }
         ;
 
 idDottedMoreForeach<nodeExprp>:
                 idArrayedForeach                        { $$ = $1; }
-        |       idDottedMoreForeach '.' idArrayedForeach        { $$ = new AstDot($2, false, $1, $3); }
+        |       idDottedMoreForeach '.' idArrayedForeach        { $$ = new AstDot{$2, false, $1, $3}; }
         ;
 
 // Single component of dotted path, maybe [#].
@@ -5294,24 +5319,24 @@ idDottedMoreForeach<nodeExprp>:
 //       enum_identifier
 idArrayed<nodeExprp>:               // IEEE: id + select
                 id
-                        { $$ = new AstParseRef($<fl>1, VParseRefExp::PX_TEXT, *$1, nullptr, nullptr); }
+                        { $$ = new AstParseRef{$<fl>1, VParseRefExp::PX_TEXT, *$1, nullptr, nullptr}; }
         //                      // IEEE: id + part_select_range/constant_part_select_range
-        |       idArrayed '[' expr ']'                          { $$ = new AstSelBit($2, $1, $3); }  // Or AstArraySel, don't know yet.
-        |       idArrayed '[' constExpr ':' constExpr ']'       { $$ = new AstSelExtract($2, $1, $3, $5); }
+        |       idArrayed '[' expr ']'                          { $$ = new AstSelBit{$2, $1, $3}; }  // Or AstArraySel, don't know yet.
+        |       idArrayed '[' constExpr ':' constExpr ']'       { $$ = new AstSelExtract{$2, $1, $3, $5}; }
         //                      // IEEE: id + indexed_range/constant_indexed_range
-        |       idArrayed '[' expr yP_PLUSCOLON  constExpr ']'  { $$ = new AstSelPlus($2, $1, $3, $5); }
-        |       idArrayed '[' expr yP_MINUSCOLON constExpr ']'  { $$ = new AstSelMinus($2, $1, $3, $5); }
+        |       idArrayed '[' expr yP_PLUSCOLON  constExpr ']'  { $$ = new AstSelPlus{$2, $1, $3, $5}; }
+        |       idArrayed '[' expr yP_MINUSCOLON constExpr ']'  { $$ = new AstSelMinus{$2, $1, $3, $5}; }
         ;
 
 idArrayedForeach<nodeExprp>:    // IEEE: id + select (under foreach expression)
                 id
-                        { $$ = new AstParseRef($<fl>1, VParseRefExp::PX_TEXT, *$1, nullptr, nullptr); }
+                        { $$ = new AstParseRef{$<fl>1, VParseRefExp::PX_TEXT, *$1, nullptr, nullptr}; }
         //                      // IEEE: id + part_select_range/constant_part_select_range
-        |       idArrayed '[' expr ']'                          { $$ = new AstSelBit($2, $1, $3); }  // Or AstArraySel, don't know yet.
-        |       idArrayed '[' constExpr ':' constExpr ']'       { $$ = new AstSelExtract($2, $1, $3, $5); }
+        |       idArrayed '[' expr ']'                          { $$ = new AstSelBit{$2, $1, $3}; }  // Or AstArraySel, don't know yet.
+        |       idArrayed '[' constExpr ':' constExpr ']'       { $$ = new AstSelExtract{$2, $1, $3, $5}; }
         //                      // IEEE: id + indexed_range/constant_indexed_range
-        |       idArrayed '[' expr yP_PLUSCOLON  constExpr ']'  { $$ = new AstSelPlus($2, $1, $3, $5); }
-        |       idArrayed '[' expr yP_MINUSCOLON constExpr ']'  { $$ = new AstSelMinus($2, $1, $3, $5); }
+        |       idArrayed '[' expr yP_PLUSCOLON  constExpr ']'  { $$ = new AstSelPlus{$2, $1, $3, $5}; }
+        |       idArrayed '[' expr yP_MINUSCOLON constExpr ']'  { $$ = new AstSelMinus{$2, $1, $3, $5}; }
         //                      // IEEE: loop_variables (under foreach expression)
         //                      // To avoid conflicts we allow expr as first element, must post-check
         |       idArrayed '[' expr ',' loop_variables ']'
@@ -5322,7 +5347,7 @@ idArrayedForeach<nodeExprp>:    // IEEE: id + select (under foreach expression)
 
 // VarRef without any dots or vectorizaion
 varRefBase<varRefp>:
-                id                                      { $$ = new AstVarRef($<fl>1, *$1, VAccess::READ); }
+                id                                      { $$ = new AstVarRef{$<fl>1, *$1, VAccess::READ}; }
         ;
 
 // ParseRef
@@ -5344,7 +5369,7 @@ strAsInt<nodeExprp>:
                               // until V3Width converts as/if needed to a numerical constant
                               $$ = new AstConst{$<fl>1, AstConst::String{}, GRAMMARP->deQuote($<fl>1, *$1)};
                           } else {
-                              $$ = new AstConst{$<fl>1, AstConst::VerilogStringLiteral(), GRAMMARP->deQuote($<fl>1, *$1)};
+                              $$ = new AstConst{$<fl>1, AstConst::VerilogStringLiteral{}, GRAMMARP->deQuote($<fl>1, *$1)};
                           }
                         }
         ;
@@ -5460,7 +5485,7 @@ assertion_item_declaration<nodep>:  // ==IEEE: assertion_item_declaration
 assertion_item<nodep>:          // ==IEEE: assertion_item
                 concurrent_assertion_item               { $$ = $1; }
         |       deferred_immediate_assertion_item
-                        { $$ = $1 ? new AstAlways($1->fileline(), VAlwaysKwd::ALWAYS_COMB, nullptr, $1) : nullptr; }
+                        { $$ = $1 ? new AstAlways{$1->fileline(), VAlwaysKwd::ALWAYS_COMB, nullptr, $1} : nullptr; }
         ;
 
 deferred_immediate_assertion_item<nodep>:       // ==IEEE: deferred_immediate_assertion_item
@@ -5484,15 +5509,19 @@ immediate_assertion_statement<nodep>:   // ==IEEE: immediate_assertion_statement
 
 simple_immediate_assertion_statement<nodep>:    // ==IEEE: simple_immediate_assertion_statement
         //                              // action_block expanded here, for compatibility with AstAssert
-                yASSERT '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE  { $$ = new AstAssert($1, $3, $5, nullptr, true); }
-        |       yASSERT '(' expr ')'           yELSE stmtBlock          { $$ = new AstAssert($1, $3, nullptr, $6, true); }
-        |       yASSERT '(' expr ')' stmtBlock yELSE stmtBlock          { $$ = new AstAssert($1, $3, $5, $7, true); }
-        //                              // action_block expanded here, for compatibility with AstAssert
-        |       yASSUME '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE  { $$ = new AstAssert($1, $3, $5, nullptr, true); }
-        |       yASSUME '(' expr ')'           yELSE stmtBlock          { $$ = new AstAssert($1, $3, nullptr, $6, true); }
-        |       yASSUME '(' expr ')' stmtBlock yELSE stmtBlock          { $$ = new AstAssert($1, $3, $5, $7, true);   }
+                assertOrAssume '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE
+                        { $$ = new AstAssert{$1, $3, $5, nullptr, true}; }
+        |       assertOrAssume '(' expr ')'           yELSE stmtBlock
+                        { $$ = new AstAssert{$1, $3, nullptr, $6, true}; }
+        |       assertOrAssume '(' expr ')' stmtBlock yELSE stmtBlock
+                        { $$ = new AstAssert{$1, $3, $5, $7, true}; }
         //                      // IEEE: simple_immediate_cover_statement
-        |       yCOVER '(' expr ')' stmt                { $$ = new AstCover($1, $3, $5, true); }
+        |       yCOVER '(' expr ')' stmt                { $$ = new AstCover{$1, $3, $5, true}; }
+        ;
+
+assertOrAssume<fl>:
+                yASSERT                                 { $$ = $1; }
+        |       yASSUME                                 { $$ = $1; }
         ;
 
 final_zero:                     // IEEE: part of deferred_immediate_assertion_statement
@@ -5504,15 +5533,21 @@ final_zero:                     // IEEE: part of deferred_immediate_assertion_st
 
 deferred_immediate_assertion_statement<nodep>:  // ==IEEE: deferred_immediate_assertion_statement
         //                      // IEEE: deferred_immediate_assert_statement
-                yASSERT final_zero '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE       { $$ = new AstAssert($1, $4, $6, nullptr, true); }
-        |       yASSERT final_zero '(' expr ')'           yELSE stmtBlock               { $$ = new AstAssert($1, $4, nullptr, $7, true); }
-        |       yASSERT final_zero '(' expr ')' stmtBlock yELSE stmtBlock               { $$ = new AstAssert($1, $4, $6, $8, true);   }
+                yASSERT final_zero '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE
+                        { $$ = new AstAssert{$1, $4, $6, nullptr, true}; }
+        |       yASSERT final_zero '(' expr ')'           yELSE stmtBlock
+                        { $$ = new AstAssert{$1, $4, nullptr, $7, true}; }
+        |       yASSERT final_zero '(' expr ')' stmtBlock yELSE stmtBlock
+                        { $$ = new AstAssert{$1, $4, $6, $8, true}; }
         //                      // IEEE: deferred_immediate_assume_statement
-        |       yASSUME final_zero '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE       { $$ = new AstAssert($1, $4, $6, nullptr, true); }
-        |       yASSUME final_zero '(' expr ')'           yELSE stmtBlock               { $$ = new AstAssert($1, $4, nullptr, $7, true); }
-        |       yASSUME final_zero '(' expr ')' stmtBlock yELSE stmtBlock               { $$ = new AstAssert($1, $4, $6, $8, true); }
+        |       yASSUME final_zero '(' expr ')' stmtBlock %prec prLOWER_THAN_ELSE
+                        { $$ = new AstAssert{$1, $4, $6, nullptr, true}; }
+        |       yASSUME final_zero '(' expr ')'           yELSE stmtBlock
+                        { $$ = new AstAssert{$1, $4, nullptr, $7, true}; }
+        |       yASSUME final_zero '(' expr ')' stmtBlock yELSE stmtBlock
+                        { $$ = new AstAssert{$1, $4, $6, $8, true}; }
         //                      // IEEE: deferred_immediate_cover_statement
-        |       yCOVER final_zero '(' expr ')' stmt     { $$ = new AstCover($1, $4, $6, true); }
+        |       yCOVER final_zero '(' expr ')' stmt     { $$ = new AstCover{$1, $4, $6, true}; }
         ;
 
 //UNSUPexpect_property_statement<nodep>:  // ==IEEE: expect_property_statement
@@ -5538,7 +5573,7 @@ concurrent_assertion_statement<nodep>:  // ==IEEE: concurrent_assertion_statemen
                         { $$ = new AstAssert{$1, new AstSampled{$1, $4}, nullptr, $6, false}; }
         //UNSUP yASSUME yPROPERTY '(' property_spec ')' action_block    { }
         //                      // IEEE: cover_property_statement
-        |       yCOVER yPROPERTY '(' property_spec ')' stmtBlock        { $$ = new AstCover($1, $4, $6, false); }
+        |       yCOVER yPROPERTY '(' property_spec ')' stmtBlock        { $$ = new AstCover{$1, $4, $6, false}; }
         //                      // IEEE: cover_sequence_statement
         //UNSUP yCOVER ySEQUENCE '(' sexpr ')' stmt                     { }
         //                      // IEEE: yCOVER ySEQUENCE '(' clocking_event sexpr ')' stmt
@@ -5546,7 +5581,7 @@ concurrent_assertion_statement<nodep>:  // ==IEEE: concurrent_assertion_statemen
         //UNSUP yCOVER ySEQUENCE '(' clocking_event yDISABLE yIFF '(' expr/*expression_or_dist*/ ')' sexpr ')' stmt     { }
         //UNSUP yCOVER ySEQUENCE '(' yDISABLE yIFF '(' expr/*expression_or_dist*/ ')' sexpr ')' stmt    { }
         //                      // IEEE: restrict_property_statement
-        |       yRESTRICT yPROPERTY '(' property_spec ')' ';'           { $$ = new AstRestrict($1, $4); }
+        |       yRESTRICT yPROPERTY '(' property_spec ')' ';'           { $$ = new AstRestrict{$1, $4}; }
         ;
 
 elseStmtBlock<nodep>:   // Part of concurrent_assertion_statement
@@ -5600,7 +5635,7 @@ property_port_itemFront: // IEEE: part of property_port_item/sequence_port_item
                         { VARDTYPE($2); GRAMMARP->m_typedPropertyPort = true; }
 //UNSUP |       property_port_itemDirE yVAR data_type           { VARDTYPE($3); }
 //UNSUP |       property_port_itemDirE yVAR implicit_typeE      { VARDTYPE($3); }
-//UNSUP |       property_port_itemDirE signingE rangeList       { VARDTYPE(SPACED($2,$3)); }
+//UNSUP |       property_port_itemDirE signingE rangeList       { VARDTYPE(SPACED($2, $3)); }
         |       property_port_itemDirE implicit_typeE           { VARDTYPE($2); }
         ;
 
@@ -5767,8 +5802,8 @@ pexpr<nodeExprp>:  // IEEE: property_expr  (The name pexpr is important as regex
         ;
 
 complex_pexpr<nodeExprp>:  // IEEE: part of property_expr, see comments there
-                expr yP_ORMINUSGT pexpr                 { $$ = new AstLogOr($2, new AstLogNot($2, $1), $3); }
-        |       expr yP_OREQGT pexpr                    { $$ = new AstImplication($2, $1, $3); }
+                expr yP_ORMINUSGT pexpr                 { $$ = new AstLogOr{$2, new AstLogNot{$2, $1}, $3}; }
+        |       expr yP_OREQGT pexpr                    { $$ = new AstImplication{$2, $1, $3}; }
         |       yNOT pexpr %prec prNEGATION             { $$ = new AstLogNot{$1, $2}; }
         |       '(' complex_pexpr ')'                   { $$ = $2; }
         //UNSUP remove above, use below:

From 73d6de447116c080c4535c881e17a9613785cf7b Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 21 Nov 2022 20:41:32 -0500
Subject: [PATCH 082/156] Internals: Fix constructor style.

---
 src/V3AstNodeExpr.h     |  8 ++++----
 src/V3Hash.h            |  2 +-
 src/V3Options.cpp       |  2 +-
 src/V3SenTree.h         |  2 +-
 src/V3Unknown.cpp       |  2 +-
 src/V3VariableOrder.cpp |  2 +-
 src/V3Width.cpp         | 31 ++++++++++++++++---------------
 7 files changed, 25 insertions(+), 24 deletions(-)

diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index ab1fad6e5..ffac83677 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -138,7 +138,7 @@ public:
 class AstNodeSystemBiop VL_NOT_FINAL : public AstNodeBiop {
 public:
     AstNodeSystemBiop(VNType t, FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
-        : AstNodeBiop(t, fl, lhsp, rhsp) {
+        : AstNodeBiop{t, fl, lhsp, rhsp} {
         dtypeSetDouble();
     }
     ASTGEN_MEMBERS_AstNodeSystemBiop;
@@ -391,7 +391,7 @@ public:
 class AstNodeSystemUniop VL_NOT_FINAL : public AstNodeUniop {
 public:
     AstNodeSystemUniop(VNType t, FileLine* fl, AstNodeExpr* lhsp)
-        : AstNodeUniop(t, fl, lhsp) {
+        : AstNodeUniop{t, fl, lhsp} {
         dtypeSetDouble();
     }
     ASTGEN_MEMBERS_AstNodeSystemUniop;
@@ -825,7 +825,7 @@ public:
     class VerilogStringLiteral {};  // for creator type-overload selection
     AstConst(FileLine* fl, VerilogStringLiteral, const string& str)
         : ASTGEN_SUPER_Const(fl)
-        , m_num(V3Number::VerilogStringLiteral(), this, str) {
+        , m_num(V3Number::VerilogStringLiteral{}, this, str) {
         initWithNumber();
     }
     AstConst(FileLine* fl, uint32_t num)
@@ -871,7 +871,7 @@ public:
     class String {};  // for creator type-overload selection
     AstConst(FileLine* fl, String, const string& num)
         : ASTGEN_SUPER_Const(fl)
-        , m_num(V3Number::String(), this, num) {
+        , m_num(V3Number::String{}, this, num) {
         dtypeSetString();
     }
     class BitFalse {};
diff --git a/src/V3Hash.h b/src/V3Hash.h
index b9ab8bd98..8bf377cd6 100644
--- a/src/V3Hash.h
+++ b/src/V3Hash.h
@@ -59,7 +59,7 @@ public:
     // '+' combines hashes
     template <class T>
     V3Hash operator+(T that) const {
-        return V3Hash(combine(m_value, V3Hash{that}.m_value));
+        return V3Hash{combine(m_value, V3Hash{that}.m_value)};
     }
 
     // '+=' combines in place
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index f8dd03135..fbc408488 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -266,7 +266,7 @@ void VTimescale::parseSlashed(FileLine* fl, const char* textp, VTimescale& unitr
     unitr = unit;
 
     if (!precStr.empty()) {
-        VTimescale prec(VTimescale::NONE);
+        VTimescale prec{VTimescale::NONE};
         bool precbad;
         prec = VTimescale{precStr, precbad /*ref*/};
         if (precbad) {
diff --git a/src/V3SenTree.h b/src/V3SenTree.h
index 698406c74..eea4128f3 100644
--- a/src/V3SenTree.h
+++ b/src/V3SenTree.h
@@ -53,7 +53,7 @@ private:
 public:
     // CONSTRUCTORS
     SenTreeFinder()
-        : SenTreeFinder(v3Global.rootp()) {}
+        : SenTreeFinder{v3Global.rootp()} {}
 
     explicit SenTreeFinder(AstNetlist* netlistp)
         : m_topScopep{netlistp->topScopep()} {
diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp
index 55d7e63ab..459112a11 100644
--- a/src/V3Unknown.cpp
+++ b/src/V3Unknown.cpp
@@ -396,7 +396,7 @@ private:
             // If (maxmsb >= selected), we're in bound
             AstNodeExpr* condp
                 = new AstGte{nodep->fileline(),
-                             new AstConst(nodep->fileline(), AstConst::WidthedValue(),
+                             new AstConst(nodep->fileline(), AstConst::WidthedValue{},
                                           nodep->lsbp()->width(), maxmsb),
                              nodep->lsbp()->cloneTree(false)};
             // See if the condition is constant true (e.g. always in bound due to constant select)
diff --git a/src/V3VariableOrder.cpp b/src/V3VariableOrder.cpp
index 6ebd72c87..b360aaca0 100644
--- a/src/V3VariableOrder.cpp
+++ b/src/V3VariableOrder.cpp
@@ -195,7 +195,7 @@ class VariableOrder final {
     }
 
 public:
-    static void processModule(AstNodeModule* modp) { VariableOrder().orderModuleVars(modp); }
+    static void processModule(AstNodeModule* modp) { VariableOrder{}.orderModuleVars(modp); }
 };
 
 //######################################################################
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index f875fe300..27bb1ed7d 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -2300,7 +2300,7 @@ private:
             if (nodep->lhsp()) {
                 if (VN_IS(nodep->lhsp()->dtypep(), DynArrayDType)
                     || VN_IS(nodep->lhsp(), ConsDynArray)) {
-                    userIterateAndNext(nodep->lhsp(), WidthVP(vdtypep, FINAL).p());
+                    userIterateAndNext(nodep->lhsp(), WidthVP{vdtypep, FINAL}.p());
                 } else {
                     // Sub elements are not queues, but concats, must always pass concats down
                     iterateCheckTyped(nodep, "LHS", nodep->lhsp(), vdtypep->subDTypep(), FINAL);
@@ -2309,7 +2309,7 @@ private:
             if (nodep->rhsp()) {
                 if (VN_IS(nodep->rhsp()->dtypep(), DynArrayDType)
                     || VN_IS(nodep->rhsp(), ConsDynArray)) {
-                    userIterateAndNext(nodep->rhsp(), WidthVP(vdtypep, FINAL).p());
+                    userIterateAndNext(nodep->rhsp(), WidthVP{vdtypep, FINAL}.p());
                 } else {
                     iterateCheckTyped(nodep, "RHS", nodep->rhsp(), vdtypep->subDTypep(), FINAL);
                 }
@@ -2341,7 +2341,7 @@ private:
             if (nodep->rhsp()) {
                 if (VN_IS(nodep->rhsp()->dtypep(), QueueDType)
                     || VN_IS(nodep->rhsp(), ConsQueue)) {
-                    userIterateAndNext(nodep->rhsp(), WidthVP(vdtypep, FINAL).p());
+                    userIterateAndNext(nodep->rhsp(), WidthVP{vdtypep, FINAL}.p());
                 } else {
                     iterateCheckTyped(nodep, "RHS", nodep->rhsp(), vdtypep->subDTypep(), FINAL);
                 }
@@ -2360,7 +2360,7 @@ private:
             nodep->dtypep(vdtypep);
             const AstNodeDType* const arrayp = vdtypep->skipRefp();
             if (VN_IS(arrayp, NodeArrayDType) || VN_IS(arrayp, AssocArrayDType)) {
-                userIterateChildren(nodep, WidthVP(arrayp->subDTypep(), BOTH).p());
+                userIterateChildren(nodep, WidthVP{arrayp->subDTypep(), BOTH}.p());
             } else {
                 UINFO(1, "dtype object " << vdtypep->skipRefp() << endl);
                 nodep->v3fatalSrc("InitArray on non-array");
@@ -2709,7 +2709,7 @@ private:
         if (AstWith* const withp = VN_CAST(nodep->pinsp(), With)) {
             withp->indexArgRefp()->dtypep(indexDtp);
             withp->valueArgRefp()->dtypep(valueDtp);
-            userIterate(withp, WidthVP(returnDtp, BOTH).p());
+            userIterate(withp, WidthVP{returnDtp, BOTH}.p());
             withp->unlinkFrBack();
             return withp;
         } else if (required) {
@@ -4000,7 +4000,7 @@ private:
     }
     AstNodeExpr* patternMemberValueIterate(AstPatMember* patp) {
         // Determine values - might be another InitArray
-        userIterate(patp, WidthVP(patp->dtypep(), BOTH).p());
+        userIterate(patp, WidthVP{patp->dtypep(), BOTH}.p());
         // Convert to InitArray or constify immediately
         AstNodeExpr* valuep = patp->lhssp()->unlinkFrBack();
         if (VN_IS(valuep, Const)) {
@@ -4822,7 +4822,7 @@ private:
             }
             // Very much like like an assignment, but which side is LH/RHS
             // depends on pin being a in/output/inout.
-            userIterateAndNext(nodep->exprp(), WidthVP(nodep->modVarp()->dtypep(), PRELIM).p());
+            userIterateAndNext(nodep->exprp(), WidthVP{nodep->modVarp()->dtypep(), PRELIM}.p());
             AstNodeDType* modDTypep = nodep->modVarp()->dtypep();
             AstNodeDType* conDTypep = nodep->exprp()->dtypep();
             if (!modDTypep) nodep->v3fatalSrc("Unlinked pin data type");
@@ -4834,7 +4834,7 @@ private:
             const int conwidth = conDTypep->width();
             if (conDTypep == modDTypep  // If match, we're golden
                 || similarDTypeRecurse(conDTypep, modDTypep)) {
-                userIterateAndNext(nodep->exprp(), WidthVP(subDTypep, FINAL).p());
+                userIterateAndNext(nodep->exprp(), WidthVP{subDTypep, FINAL}.p());
             } else if (m_cellp->rangep()) {
                 const int numInsts = m_cellp->rangep()->elementsConst();
                 if (conwidth == modwidth) {
@@ -4855,7 +4855,7 @@ private:
                                    << " bits. (IEEE 1800-2017 23.3.3)");
                     subDTypep = conDTypep;  // = same expr dtype
                 }
-                userIterateAndNext(nodep->exprp(), WidthVP(subDTypep, FINAL).p());
+                userIterateAndNext(nodep->exprp(), WidthVP{subDTypep, FINAL}.p());
             } else {
                 if (nodep->modVarp()->direction() == VDirection::REF) {
                     nodep->v3error("Ref connection "
@@ -4955,9 +4955,10 @@ private:
             const int conwidth = conDTypep->width();
             if (conwidth == 1 && modwidth > 1) {  // Multiple connections
                 AstNodeDType* const subDTypep = nodep->findLogicDType(1, 1, conDTypep->numeric());
-                userIterateAndNext(nodep->exprp(), WidthVP(subDTypep, FINAL).p());
-                AstNode* const newp = new AstReplicate(nodep->fileline(),
-                                                       nodep->exprp()->unlinkFrBack(), numInsts);
+                userIterateAndNext(nodep->exprp(), WidthVP{subDTypep, FINAL}.p());
+                AstNode* const newp
+                    = new AstReplicate{nodep->fileline(), nodep->exprp()->unlinkFrBack(),
+                                       static_cast<uint32_t>(numInsts)};
                 nodep->replaceWith(newp);
             } else {
                 // Eliminating so pass down all of vup
@@ -5167,7 +5168,7 @@ private:
                     pinp = newp;
                 }
                 // AstPattern requires assignments to pass datatype on PRELIM
-                VL_DO_DANGLING(userIterate(pinp, WidthVP(portp->dtypep(), PRELIM).p()), pinp);
+                VL_DO_DANGLING(userIterate(pinp, WidthVP{portp->dtypep(), PRELIM}.p()), pinp);
             }
         } while (false);
         // Stage 2
@@ -5193,7 +5194,7 @@ private:
                 if (!pinp) continue;  // Argument error we'll find later
                 // Do PRELIM again, because above accept may have exited early
                 // due to node replacement
-                userIterate(pinp, WidthVP(portp->dtypep(), PRELIM).p());
+                userIterate(pinp, WidthVP{portp->dtypep(), PRELIM}.p());
             }
         }
         // Cleanup any open arrays
@@ -5223,7 +5224,7 @@ private:
                 }
                 if (!portp->basicp() || portp->basicp()->isOpaque()) {
                     checkClassAssign(nodep, "Function Argument", pinp, portp->dtypep());
-                    userIterate(pinp, WidthVP(portp->dtypep(), FINAL).p());
+                    userIterate(pinp, WidthVP{portp->dtypep(), FINAL}.p());
                 } else {
                     iterateCheckAssign(nodep, "Function Argument", pinp, FINAL, portp->dtypep());
                 }

From 66d85b33817c2cdadc41004f3b1ade9f6a2f9ee6 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 21 Nov 2022 21:40:49 -0500
Subject: [PATCH 083/156] Internals: Fix cppcheck warnings. No functional
 change intended.

---
 include/verilated.cpp      |  1 +
 include/verilated_imp.h    |  1 +
 include/verilated_timing.h |  2 ++
 include/verilated_types.h  |  2 +-
 src/V3Ast.cpp              |  4 ++--
 src/V3Ast.h                |  5 +++--
 src/V3AstNodeExpr.h        |  6 +++---
 src/V3AstNodeOther.h       |  2 +-
 src/V3DfgOptimizer.cpp     | 12 ++++++------
 src/V3DfgPasses.cpp        |  2 +-
 src/V3DfgPasses.h          |  2 +-
 src/V3Options.cpp          |  2 +-
 src/V3Order.cpp            |  4 ++--
 src/V3Partition.cpp        |  8 ++++----
 src/V3Simulate.h           |  2 +-
 src/V3Timing.cpp           |  1 -
 src/V3Width.cpp            | 10 +++++-----
 17 files changed, 35 insertions(+), 31 deletions(-)

diff --git a/include/verilated.cpp b/include/verilated.cpp
index 5105bca90..ec82b6a16 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -1641,6 +1641,7 @@ std::string VL_STACKTRACE_N() VL_MT_SAFE {
     strings = backtrace_symbols(buffer, nptrs);
 #endif
 
+    // cppcheck-suppress knownConditionTrueFalse
     if (!strings) return "Unable to backtrace\n";
 
     std::string out = "Backtrace:\n";
diff --git a/include/verilated_imp.h b/include/verilated_imp.h
index afc3d01c8..ad6d96cac 100644
--- a/include/verilated_imp.h
+++ b/include/verilated_imp.h
@@ -362,6 +362,7 @@ public:  // But only for verilated*.cpp
 private:
     VerilatedFpList fdToFpList(IData fdi) VL_REQUIRES(m_fdMutex) {
         VerilatedFpList fp;
+        // cppcheck-suppress integeroverflow shifttoomanybitssigned
         if ((fdi & (1 << 31)) != 0) {
             // Non-MCD case
             const IData idx = fdi & VL_MASK_I(31);
diff --git a/include/verilated_timing.h b/include/verilated_timing.h
index f39d88ed6..bead97e9d 100644
--- a/include/verilated_timing.h
+++ b/include/verilated_timing.h
@@ -404,11 +404,13 @@ public:
 
     // CONSTRUCTORS
     // Construct
+    // cppcheck-suppress noExplicitConstructor
     VlCoroutine(VlPromise* promisep)
         : m_promisep{promisep} {
         m_promisep->m_corop = this;
     }
     // Move. Update the pointers each time the return object is moved
+    // cppcheck-suppress noExplicitConstructor
     VlCoroutine(VlCoroutine&& other)
         : m_promisep{std::exchange(other.m_promisep, nullptr)} {
         if (m_promisep) m_promisep->m_corop = this;
diff --git a/include/verilated_types.h b/include/verilated_types.h
index 4d080e942..d6d6879e2 100644
--- a/include/verilated_types.h
+++ b/include/verilated_types.h
@@ -1113,7 +1113,7 @@ public:
     // CONSTRUCTORS
     VlClassRef() = default;
     // Init with nullptr
-    VlClassRef(VlNull){};
+    explicit VlClassRef(VlNull){};
     template <typename... T_Args>
     VlClassRef(VlDeleter& deleter, T_Args&&... args)
         : m_objp{new T_Class{std::forward<T_Args>(args)...}} {
diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp
index 20652b369..2f8f609a1 100644
--- a/src/V3Ast.cpp
+++ b/src/V3Ast.cpp
@@ -1001,9 +1001,9 @@ bool AstNode::sameTreeIter(const AstNode* node1p, const AstNode* node2p, bool ig
 //======================================================================
 // Debugging
 
-void AstNode::checkTreeIter(const AstNode* backp) const {
+void AstNode::checkTreeIter(const AstNode* prevBackp) const {
     // private: Check a tree and children
-    UASSERT_OBJ(backp == this->backp(), this, "Back node inconsistent");
+    UASSERT_OBJ(prevBackp == this->backp(), this, "Back node inconsistent");
     switch (this->type()) {
 #include "V3Ast__gen_op_checks.h"
     default: VL_UNREACHABLE;  // LCOV_EXCL_LINE
diff --git a/src/V3Ast.h b/src/V3Ast.h
index 486daa879..30efa7ffa 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -1543,7 +1543,7 @@ class AstNode VL_NOT_FINAL {
 private:
     AstNode* cloneTreeIter();
     AstNode* cloneTreeIterList();
-    void checkTreeIter(const AstNode* backp) const VL_MT_SAFE;
+    void checkTreeIter(const AstNode* prevBackp) const VL_MT_SAFE;
     bool gateTreeIter() const;
     static bool sameTreeIter(const AstNode* node1p, const AstNode* node2p, bool ignNext,
                              bool gateOnly);
@@ -2439,9 +2439,10 @@ class VNRef final : public std::reference_wrapper<T_Node> {
 
 public:
     template <typename U>
+    // cppcheck-suppress noExplicitConstructor
     VNRef(U&& x)
         : std::reference_wrapper<T_Node>{x} {}
-
+    // cppcheck-suppress noExplicitConstructor
     VNRef(const std::reference_wrapper<T_Node>& other)
         : std::reference_wrapper<T_Node>{other} {}
 };
diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index ffac83677..464c4e5a7 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -1718,7 +1718,7 @@ public:
 class AstStackTraceF final : public AstNodeExpr {
     // $stacktrace used as function
 public:
-    AstStackTraceF(FileLine* fl)
+    explicit AstStackTraceF(FileLine* fl)
         : ASTGEN_SUPER_StackTraceF(fl) {
         dtypeSetString();
     }
@@ -1809,7 +1809,7 @@ public:
 class AstTimePrecision final : public AstNodeExpr {
     // Verilog $timeprecision
 public:
-    AstTimePrecision(FileLine* fl)
+    explicit AstTimePrecision(FileLine* fl)
         : ASTGEN_SUPER_TimePrecision(fl) {
         dtypeSetSigned32();
     }
@@ -1825,7 +1825,7 @@ class AstTimeUnit final : public AstNodeExpr {
     VTimescale m_timeunit;  // Parent module time unit
     // Verilog $timeunit
 public:
-    AstTimeUnit(FileLine* fl)
+    explicit AstTimeUnit(FileLine* fl)
         : ASTGEN_SUPER_TimeUnit(fl) {
         dtypeSetSigned32();
     }
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index 6725d14c4..6b816d971 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -2936,7 +2936,7 @@ public:
 class AstStackTraceT final : public AstNodeStmt {
     // $stacktrace used as task
 public:
-    AstStackTraceT(FileLine* fl)
+    explicit AstStackTraceT(FileLine* fl)
         : ASTGEN_SUPER_StackTraceT(fl) {}
     ASTGEN_MEMBERS_AstStackTraceT;
     string verilogKwd() const override { return "$stacktrace"; }
diff --git a/src/V3DfgOptimizer.cpp b/src/V3DfgOptimizer.cpp
index 94f880edb..958d73202 100644
--- a/src/V3DfgOptimizer.cpp
+++ b/src/V3DfgOptimizer.cpp
@@ -110,7 +110,7 @@ class DataflowExtractVisitor final : public VNVisitor {
             if (!VN_IS(modp, Module)) continue;
 
             for (const auto& pair : m_extractionCandidates(modp)) {
-                AstNodeExpr* const nodep = pair.first;
+                AstNodeExpr* const cnodep = pair.first;
 
                 // Do not extract expressions without any variable references
                 if (pair.second.empty()) continue;
@@ -132,18 +132,18 @@ class DataflowExtractVisitor final : public VNVisitor {
                 }
 
                 // Create temporary variable
-                FileLine* const flp = nodep->fileline();
-                const string name = names.get(nodep);
-                AstVar* const varp = new AstVar{flp, VVarType::MODULETEMP, name, nodep->dtypep()};
+                FileLine* const flp = cnodep->fileline();
+                const string name = names.get(cnodep);
+                AstVar* const varp = new AstVar{flp, VVarType::MODULETEMP, name, cnodep->dtypep()};
                 varp->trace(false);
                 modp->addStmtsp(varp);
 
                 // Replace expression with temporary variable
-                nodep->replaceWith(new AstVarRef{flp, varp, VAccess::READ});
+                cnodep->replaceWith(new AstVarRef{flp, varp, VAccess::READ});
 
                 // Add assignment driving temporary variable
                 modp->addStmtsp(
-                    new AstAssignW{flp, new AstVarRef{flp, varp, VAccess::WRITE}, nodep});
+                    new AstAssignW{flp, new AstVarRef{flp, varp, VAccess::WRITE}, cnodep});
             }
         }
     }
diff --git a/src/V3DfgPasses.cpp b/src/V3DfgPasses.cpp
index 26e1b3b6b..4e03c3870 100644
--- a/src/V3DfgPasses.cpp
+++ b/src/V3DfgPasses.cpp
@@ -137,7 +137,7 @@ void V3DfgPasses::cse(DfgGraph& dfg, V3DfgCseContext& ctx) {
     removeUnused(dfg);
 }
 
-void V3DfgPasses::inlineVars(DfgGraph& dfg) {
+void V3DfgPasses::inlineVars(const DfgGraph& dfg) {
     for (DfgVertexVar *vtxp = dfg.varVerticesBeginp(), *nextp; vtxp; vtxp = nextp) {
         nextp = vtxp->verticesNext();
         if (DfgVarPacked* const varp = vtxp->cast<DfgVarPacked>()) {
diff --git a/src/V3DfgPasses.h b/src/V3DfgPasses.h
index 93c0d94fa..7d8ed5913 100644
--- a/src/V3DfgPasses.h
+++ b/src/V3DfgPasses.h
@@ -103,7 +103,7 @@ AstModule* dfgToAst(DfgGraph&, V3DfgOptimizationContext&);
 // Common subexpression elimination
 void cse(DfgGraph&, V3DfgCseContext&);
 // Inline fully driven variables
-void inlineVars(DfgGraph&);
+void inlineVars(const DfgGraph&);
 // Peephole optimizations
 void peephole(DfgGraph&, V3DfgPeepholeContext&);
 // Remove redundant variables
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index fbc408488..2e0368743 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -257,7 +257,7 @@ void VTimescale::parseSlashed(FileLine* fl, const char* textp, VTimescale& unitr
         return;
     }
 
-    bool unitbad;
+    bool unitbad = false;
     const VTimescale unit{unitStr, unitbad /*ref*/};
     if (unitbad && !(unitStr.empty() && allowEmpty)) {
         fl->v3error("`timescale timeunit syntax error: '" << unitStr << "'");
diff --git a/src/V3Order.cpp b/src/V3Order.cpp
index 1e3f50987..8bd94252b 100644
--- a/src/V3Order.cpp
+++ b/src/V3Order.cpp
@@ -836,7 +836,7 @@ class OrderProcess final : VNDeleter {
     void processMovePrepReady();
     void processMoveReadyOne(OrderMoveVertex* vertexp);
     void processMoveDoneOne(OrderMoveVertex* vertexp);
-    void processMoveOne(OrderMoveVertex* vertexp, OrderMoveDomScope* domScopep, int level);
+    void processMoveOne(OrderMoveVertex* vertexp, const OrderMoveDomScope* domScopep, int level);
     AstActive* processMoveOneLogic(const OrderLogicVertex* lvertexp, AstCFunc*& newFuncpr,
                                    int& newStmtsr);
 
@@ -1180,7 +1180,7 @@ void OrderProcess::processMoveDoneOne(OrderMoveVertex* vertexp) {
     }
 }
 
-void OrderProcess::processMoveOne(OrderMoveVertex* vertexp, OrderMoveDomScope* domScopep,
+void OrderProcess::processMoveOne(OrderMoveVertex* vertexp, const OrderMoveDomScope* domScopep,
                                   int level) {
     UASSERT_OBJ(vertexp->domScopep() == domScopep, vertexp, "Domain mismatch; list misbuilt?");
     const OrderLogicVertex* const lvertexp = vertexp->logicp();
diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp
index a49b98f7f..87a631ea0 100644
--- a/src/V3Partition.cpp
+++ b/src/V3Partition.cpp
@@ -197,7 +197,7 @@ private:
     // Set of MTaskMoveVertex's assigned to this mtask. LogicMTask does not
     // own the MTaskMoveVertex objects, we merely keep pointers to them
     // here.
-    VxList m_vertices;
+    VxList m_mvertices;
 
     // Cost estimate for this LogicMTask, derived from V3InstrCount.
     // In abstract time units.
@@ -234,7 +234,7 @@ public:
         : AbstractLogicMTask{graphp} {
         for (uint32_t& item : m_critPathCost) item = 0;
         if (mtmvVxp) {  // Else null for test
-            m_vertices.push_back(mtmvVxp);
+            m_mvertices.push_back(mtmvVxp);
             if (const OrderLogicVertex* const olvp = mtmvVxp->logicp()) {
                 m_cost += V3InstrCount::count(olvp->nodep(), true);
             }
@@ -252,10 +252,10 @@ public:
 
     void moveAllVerticesFrom(LogicMTask* otherp) {
         // splice() is constant time
-        m_vertices.splice(m_vertices.end(), otherp->m_vertices);
+        m_mvertices.splice(m_mvertices.end(), otherp->m_mvertices);
         m_cost += otherp->m_cost;
     }
-    const VxList* vertexListp() const override { return &m_vertices; }
+    const VxList* vertexListp() const override { return &m_mvertices; }
     static uint64_t incGeneration() {
         static uint64_t s_generation = 0;
         ++s_generation;
diff --git a/src/V3Simulate.h b/src/V3Simulate.h
index 08eefad33..1fd4a64d4 100644
--- a/src/V3Simulate.h
+++ b/src/V3Simulate.h
@@ -382,7 +382,7 @@ private:
     int unrollCount() const {
         return m_params ? v3Global.opt.unrollCount() * 16 : v3Global.opt.unrollCount();
     }
-    bool jumpingOver(AstNode* nodep) {
+    bool jumpingOver(AstNode* nodep) const {
         // True to jump over this node - all visitors must call this up front
         return (m_jumpp && m_jumpp->labelp() != nodep);
     }
diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp
index eb76178f8..2ff9c4a85 100644
--- a/src/V3Timing.cpp
+++ b/src/V3Timing.cpp
@@ -605,7 +605,6 @@ private:
             auto* const sensesp = m_finder.getSenTree(nodep->sensesp());
             nodep->sensesp()->unlinkFrBack()->deleteTree();
             // Get this sentree's trigger scheduler
-            FileLine* const flp = nodep->fileline();
             // Replace self with a 'co_await trigSched.trigger()'
             auto* const triggerMethodp = new AstCMethodHard{
                 flp, new AstVarRef{flp, getCreateTriggerSchedulerp(sensesp), VAccess::WRITE},
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 27bb1ed7d..b4a4fb442 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3765,7 +3765,7 @@ private:
 
     AstNodeExpr* nestedvalueConcat_patternUOrStruct(AstNodeUOrStructDType* memp_vdtypep,
                                                     AstPatMember* defaultp, AstNodeExpr* newp,
-                                                    AstPattern* nodep, DTypeMap dtypemap) {
+                                                    AstPattern* nodep, const DTypeMap& dtypemap) {
         AstPatMember* patp = nullptr;
         for (AstMemberDType* memp_nested = memp_vdtypep->membersp(); memp_nested;
              memp_nested = VN_AS(memp_nested->nextp(), MemberDType)) {
@@ -3787,7 +3787,7 @@ private:
     AstPatMember* Defaultpatp_patternUOrStruct(AstPattern* nodep, AstMemberDType* memp,
                                                AstPatMember* patp,
                                                AstNodeUOrStructDType* memp_vdtypep,
-                                               AstPatMember* defaultp, DTypeMap dtypemap) {
+                                               AstPatMember* defaultp, const DTypeMap& dtypemap) {
         const string memp_DType = memp->virtRefDTypep()->prettyDTypeName();
         const auto it = dtypemap.find(memp_DType);
         if (it != dtypemap.end()) {
@@ -6127,17 +6127,17 @@ private:
         } else if (expDTypep->isDouble() && !underp->isDouble()) {
             AstNode* const oldp
                 = underp;  // Need FINAL on children; otherwise splice would block it
-            underp = spliceCvtD(VN_AS(underp, NodeExpr));
+            spliceCvtD(VN_AS(underp, NodeExpr));
             underp = userIterateSubtreeReturnEdits(oldp, WidthVP{SELF, FINAL}.p());
         } else if (!expDTypep->isDouble() && underp->isDouble()) {
             AstNode* const oldp
                 = underp;  // Need FINAL on children; otherwise splice would block it
-            underp = spliceCvtS(VN_AS(underp, NodeExpr), true, expDTypep->width());  // Round RHS
+            spliceCvtS(VN_AS(underp, NodeExpr), true, expDTypep->width());  // Round RHS
             underp = userIterateSubtreeReturnEdits(oldp, WidthVP{SELF, FINAL}.p());
         } else if (expDTypep->isString() && !underp->dtypep()->isString()) {
             AstNode* const oldp
                 = underp;  // Need FINAL on children; otherwise splice would block it
-            underp = spliceCvtString(VN_AS(underp, NodeExpr));
+            spliceCvtString(VN_AS(underp, NodeExpr));
             underp = userIterateSubtreeReturnEdits(oldp, WidthVP{SELF, FINAL}.p());
         } else {
             const AstBasicDType* const expBasicp = expDTypep->basicp();

From 57975c82b7deee3b709285eebbf57ca735bc6115 Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Tue, 22 Nov 2022 15:10:25 +0100
Subject: [PATCH 084/156] Support 'with' in unique, unique_index, min, max in
 queues (#3772)

---
 include/verilated_types.h             | 56 +++++++++++++++++++++++++--
 src/V3Width.cpp                       |  4 +-
 test_regress/t/t_queue_method.v       | 13 ++++++-
 test_regress/t/t_queue_method_bad.out | 40 +++++++++----------
 test_regress/t/t_queue_method_bad.v   |  1 -
 5 files changed, 85 insertions(+), 29 deletions(-)

diff --git a/include/verilated_types.h b/include/verilated_types.h
index d6d6879e2..af00f31b7 100644
--- a/include/verilated_types.h
+++ b/include/verilated_types.h
@@ -429,9 +429,9 @@ public:
     void shuffle() { std::shuffle(m_deque.begin(), m_deque.end(), VlURNG{}); }
     VlQueue unique() const {
         VlQueue out;
-        std::unordered_set<T_Value> saw;
+        std::set<T_Value> saw;
         for (const auto& i : m_deque) {
-            auto it = saw.find(i);
+            const auto it = saw.find(i);
             if (it == saw.end()) {
                 saw.insert(it, i);
                 out.push_back(i);
@@ -439,12 +439,26 @@ public:
         }
         return out;
     }
+    template <typename Func>
+    VlQueue unique(Func with_func) const {
+        VlQueue out;
+        std::set<T_Value> saw;
+        for (const auto& i : m_deque) {
+            const auto i_mapped = with_func(0, i);
+            const auto it = saw.find(i_mapped);
+            if (it == saw.end()) {
+                saw.insert(it, i_mapped);
+                out.push_back(i);
+            }
+        }
+        return out;
+    }
     VlQueue<IData> unique_index() const {
         VlQueue<IData> out;
         IData index = 0;
-        std::unordered_set<T_Value> saw;
+        std::set<T_Value> saw;
         for (const auto& i : m_deque) {
-            auto it = saw.find(i);
+            const auto it = saw.find(i);
             if (it == saw.end()) {
                 saw.insert(it, i);
                 out.push_back(index);
@@ -454,6 +468,22 @@ public:
         return out;
     }
     template <typename Func>
+    VlQueue<IData> unique_index(Func with_func) const {
+        VlQueue<IData> out;
+        IData index = 0;
+        std::unordered_set<T_Value> saw;
+        for (const auto& i : m_deque) {
+            const auto i_mapped = with_func(index, i);
+            auto it = saw.find(i_mapped);
+            if (it == saw.end()) {
+                saw.insert(it, i_mapped);
+                out.push_back(index);
+            }
+            ++index;
+        }
+        return out;
+    }
+    template <typename Func>
     VlQueue find(Func with_func) const {
         VlQueue out;
         IData index = 0;
@@ -517,11 +547,29 @@ public:
         const auto it = std::min_element(m_deque.begin(), m_deque.end());
         return VlQueue::cons(*it);
     }
+    template <typename Func>
+    VlQueue min(Func with_func) const {
+        if (m_deque.empty()) return VlQueue{};
+        const auto it = std::min_element(m_deque.begin(), m_deque.end(),
+                                         [&with_func](const IData& a, const IData& b) {
+                                             return with_func(0, a) < with_func(0, b);
+                                         });
+        return VlQueue::cons(*it);
+    }
     VlQueue max() const {
         if (m_deque.empty()) return VlQueue{};
         const auto it = std::max_element(m_deque.begin(), m_deque.end());
         return VlQueue::cons(*it);
     }
+    template <typename Func>
+    VlQueue max(Func with_func) const {
+        if (m_deque.empty()) return VlQueue{};
+        const auto it = std::max_element(m_deque.begin(), m_deque.end(),
+                                         [&with_func](const IData& a, const IData& b) {
+                                             return with_func(0, a) < with_func(0, b);
+                                         });
+        return VlQueue::cons(*it);
+    }
 
     T_Value r_sum() const {
         T_Value out(0);  // Type must have assignment operator
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index b4a4fb442..fef048368 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3231,10 +3231,12 @@ private:
             newp->dtypeSetVoid();
         } else if (nodep->name() == "min" || nodep->name() == "max" || nodep->name() == "unique"
                    || nodep->name() == "unique_index") {
+            AstWith* const withp = methodWithArgument(
+                nodep, false, true, nullptr, nodep->findUInt32DType(), adtypep->subDTypep());
             methodOkArguments(nodep, 0, 0);
             methodCallLValueRecurse(nodep, nodep->fromp(), VAccess::READ);
             newp = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(),
-                                      nodep->name()};
+                                      nodep->name(), withp};
             if (nodep->name() == "unique_index") {
                 newp->dtypep(newp->findQueueIndexDType());
             } else {
diff --git a/test_regress/t/t_queue_method.v b/test_regress/t/t_queue_method.v
index 0446f406e..0b7bd29b0 100644
--- a/test_regress/t/t_queue_method.v
+++ b/test_regress/t/t_queue_method.v
@@ -44,10 +44,17 @@ module t (/*AUTOARG*/);
       v = $sformatf("%p", qv); `checks(v, "'{'h2, 'h4, 'h1, 'h3} ");
       qv = qe.unique;
       `checkh(qv.size(), 0);
+      qv = q.unique(x) with (x % 2);
+      `checkh(qv.size(), 2);
       qi = q.unique_index; qv.sort;
-      v = $sformatf("%p", qi); `checks(v, "'{'h0, 'h2, 'h3, 'h4} ");
+      // According to 7.12.1 of IEEE Std 1800-2017, it is not specified which index of duplicated value should be returned
+      `checkh(qi.size(), 4);
+      qi.delete(1);
+      v = $sformatf("%p", qi); `checks(v, "'{'h0, 'h3, 'h4} ");
       qi = qe.unique_index;
       `checkh(qi.size(), 0);
+      qi = q.unique_index(x) with (x % 3); qv.sort;
+      `checkh(qi.size(), 3);
 
       q.reverse;
       v = $sformatf("%p", q); `checks(v, "'{'h3, 'h1, 'h4, 'h2, 'h2} ");
@@ -104,8 +111,12 @@ module t (/*AUTOARG*/);
 
       qv = q.min;
       v = $sformatf("%p", qv); `checks(v, "'{'h1} ");
+      qv = q.min(x) with (x + 1);
+      v = $sformatf("%p", qv); `checks(v, "'{'h1} ");
       qv = q.max;
       v = $sformatf("%p", qv); `checks(v, "'{'h4} ");
+      qv = q.max(x) with ((x % 4) + 100);
+      v = $sformatf("%p", qv); `checks(v, "'{'h3} ");
       qv = qe.min;
       v = $sformatf("%p", qv); `checks(v, "'{}");
       qv = qe.max;
diff --git a/test_regress/t/t_queue_method_bad.out b/test_regress/t/t_queue_method_bad.out
index 584d57b0f..64de372f9 100755
--- a/test_regress/t/t_queue_method_bad.out
+++ b/test_regress/t/t_queue_method_bad.out
@@ -1,41 +1,37 @@
-%Error: t/t_queue_method_bad.v:15:21: 'with' not legal on this method
-                                    : ... In instance t
-   15 |       qv = q.unique with (1);   
-      |                     ^~~~
-%Error: t/t_queue_method_bad.v:16:9: The 1 arguments passed to .reverse method does not match its requiring 0 arguments
+%Error: t/t_queue_method_bad.v:15:9: The 1 arguments passed to .reverse method does not match its requiring 0 arguments
                                    : ... In instance t
-   16 |       q.reverse(1);   
+   15 |       q.reverse(1);   
       |         ^~~~~~~
-%Error: t/t_queue_method_bad.v:17:9: The 1 arguments passed to .shuffle method does not match its requiring 0 arguments
+%Error: t/t_queue_method_bad.v:16:9: The 1 arguments passed to .shuffle method does not match its requiring 0 arguments
                                    : ... In instance t
-   17 |       q.shuffle(1);   
+   16 |       q.shuffle(1);   
       |         ^~~~~~~
-%Error: t/t_queue_method_bad.v:18:14: 'with' statement is required for .find method
+%Error: t/t_queue_method_bad.v:17:14: 'with' statement is required for .find method
                                     : ... In instance t
-   18 |       qv = q.find;   
+   17 |       qv = q.find;   
       |              ^~~~
-%Error: t/t_queue_method_bad.v:19:14: 'with' statement is required for .find_first method
+%Error: t/t_queue_method_bad.v:18:14: 'with' statement is required for .find_first method
                                     : ... In instance t
-   19 |       qv = q.find_first;   
+   18 |       qv = q.find_first;   
       |              ^~~~~~~~~~
-%Error: t/t_queue_method_bad.v:20:14: 'with' statement is required for .find_last method
+%Error: t/t_queue_method_bad.v:19:14: 'with' statement is required for .find_last method
                                     : ... In instance t
-   20 |       qv = q.find_last;   
+   19 |       qv = q.find_last;   
       |              ^~~~~~~~~
-%Error: t/t_queue_method_bad.v:21:14: 'with' statement is required for .find_index method
+%Error: t/t_queue_method_bad.v:20:14: 'with' statement is required for .find_index method
                                     : ... In instance t
-   21 |       qi = q.find_index;   
+   20 |       qi = q.find_index;   
       |              ^~~~~~~~~~
-%Error: t/t_queue_method_bad.v:22:14: 'with' statement is required for .find_first_index method
+%Error: t/t_queue_method_bad.v:21:14: 'with' statement is required for .find_first_index method
                                     : ... In instance t
-   22 |       qi = q.find_first_index;   
+   21 |       qi = q.find_first_index;   
       |              ^~~~~~~~~~~~~~~~
-%Error: t/t_queue_method_bad.v:23:14: 'with' statement is required for .find_last_index method
+%Error: t/t_queue_method_bad.v:22:14: 'with' statement is required for .find_last_index method
                                     : ... In instance t
-   23 |       qi = q.find_last_index;   
+   22 |       qi = q.find_last_index;   
       |              ^~~~~~~~~~~~~~~
-%Error: t/t_queue_method_bad.v:25:19: 'with' not legal on this method
+%Error: t/t_queue_method_bad.v:24:19: 'with' not legal on this method
                                     : ... In instance t
-   25 |       qi = q.size with (1);   
+   24 |       qi = q.size with (1);   
       |                   ^~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_queue_method_bad.v b/test_regress/t/t_queue_method_bad.v
index 3036d05b1..e9e0089a6 100644
--- a/test_regress/t/t_queue_method_bad.v
+++ b/test_regress/t/t_queue_method_bad.v
@@ -12,7 +12,6 @@ module t (/*AUTOARG*/);
       int qi[$];  // Index returns
 
       q = '{2, 2, 4, 1, 3};
-      qv = q.unique with (1);  // Bad no with allowed
       q.reverse(1);  // Bad no args allowed
       q.shuffle(1);  // Bad no args allowed
       qv = q.find;  // Bad missing with

From 508e937164ce7388ba76263d97842c7b14c7fd7a Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Tue, 22 Nov 2022 13:48:49 +0000
Subject: [PATCH 085/156] Fix tautological predicate in V3DfgPeephole

Fixes #3771
---
 src/V3DfgPeephole.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/V3DfgPeephole.cpp b/src/V3DfgPeephole.cpp
index c17f3776c..ee4374230 100644
--- a/src/V3DfgPeephole.cpp
+++ b/src/V3DfgPeephole.cpp
@@ -1509,8 +1509,7 @@ class V3DfgPeephole final : public DfgVisitor {
         if (DfgNot* const thenNotp = thenp->cast<DfgNot>()) {
             if (DfgNot* const elseNotp = elsep->cast<DfgNot>()) {
                 if (!thenNotp->srcp()->is<DfgConst>() && !elseNotp->srcp()->is<DfgConst>()
-                    && (!thenp->hasMultipleSinks() || thenNotp->hasMultipleSinks())
-                    && (!elsep->hasMultipleSinks() || elsep->hasMultipleSinks())) {
+                    && !thenNotp->hasMultipleSinks() && !elseNotp->hasMultipleSinks()) {
                     APPLYING(PULL_NOTS_THROUGH_COND) {
                         DfgNot* const replacementp
                             = make<DfgNot>(thenp->fileline(), vtxp->dtypep());

From e97e6c22137d538dff696d44e509ff41af6d5f1d Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 22 Nov 2022 17:46:58 -0500
Subject: [PATCH 086/156] Fix V3Tristate warning (#3773)

---
 src/V3Tristate.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp
index be5db5f0a..6a274d160 100644
--- a/src/V3Tristate.cpp
+++ b/src/V3Tristate.cpp
@@ -600,9 +600,9 @@ class TristateVisitor final : public TristateBaseVisitor {
         }
         // Ignore Var's because they end up adjacent to statements
         if ((nodep->op1p() && nodep->op1p()->user1p() && !VN_IS(nodep->op1p(), Var))
-            || (nodep->op2p() && nodep->op2p()->user1p() && !VN_IS(nodep->op1p(), Var))
-            || (nodep->op3p() && nodep->op3p()->user1p() && !VN_IS(nodep->op1p(), Var))
-            || (nodep->op4p() && nodep->op4p()->user1p() && !VN_IS(nodep->op1p(), Var))) {
+            || (nodep->op2p() && nodep->op2p()->user1p() && !VN_IS(nodep->op2p(), Var))
+            || (nodep->op3p() && nodep->op3p()->user1p() && !VN_IS(nodep->op3p(), Var))
+            || (nodep->op4p() && nodep->op4p()->user1p() && !VN_IS(nodep->op4p(), Var))) {
             nodep->v3warn(E_UNSUPPORTED,
                           "Unsupported tristate construct: " << nodep->prettyTypeName());
         }

From 06fdf7be587649ce6d2edfc16fdacaf6daba3361 Mon Sep 17 00:00:00 2001
From: Yves Mathieu <75626303+mathieu-tp@users.noreply.github.com>
Date: Wed, 23 Nov 2022 10:07:14 +0100
Subject: [PATCH 087/156] Add support of Events for VCD/FST traces (#3759)

---
 include/verilated_fst_c.cpp           | 10 +++
 include/verilated_fst_c.h             |  3 +
 include/verilated_trace.h             | 11 ++++
 include/verilated_trace_imp.h         | 11 ++++
 include/verilated_vcd_c.cpp           | 16 +++++
 include/verilated_vcd_c.h             |  2 +
 src/V3EmitCImp.cpp                    |  7 ++-
 test_regress/t/t_timing_trace.out     | 62 ++++++++++---------
 test_regress/t/t_timing_trace.v       |  8 ++-
 test_regress/t/t_timing_trace_fst.out | 87 +++++++++++++++++++++++++++
 test_regress/t/t_timing_trace_fst.pl  | 32 ++++++++++
 11 files changed, 218 insertions(+), 31 deletions(-)
 create mode 100644 test_regress/t/t_timing_trace_fst.out
 create mode 100755 test_regress/t/t_timing_trace_fst.pl

diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp
index 6e1f5a33b..de5f4bbc4 100644
--- a/include/verilated_fst_c.cpp
+++ b/include/verilated_fst_c.cpp
@@ -221,6 +221,10 @@ void VerilatedFst::declare(uint32_t code, const char* name, int dtypenum, fstVar
     }
 }
 
+void VerilatedFst::declEvent(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+                           fstVarType vartype, bool array, int arraynum) {
+    declare(code, name, dtypenum, vardir, vartype, array, arraynum, false, 0, 0);
+}
 void VerilatedFst::declBit(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                            fstVarType vartype, bool array, int arraynum) {
     declare(code, name, dtypenum, vardir, vartype, array, arraynum, false, 0, 0);
@@ -279,6 +283,12 @@ void VerilatedFst::configure(const VerilatedTraceConfig& config) {
 // verilated_trace_imp.h, which is included in this file at the top),
 // so always inline them.
 
+VL_ATTR_ALWINLINE
+void VerilatedFstBuffer::emitEvent(uint32_t code, VlEvent newval) {
+        VL_DEBUG_IFDEF(assert(m_symbolp[code]););
+        fstWriterEmitValueChange(m_fst, m_symbolp[code], "1");
+}
+
 VL_ATTR_ALWINLINE
 void VerilatedFstBuffer::emitBit(uint32_t code, CData newval) {
     VL_DEBUG_IFDEF(assert(m_symbolp[code]););
diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h
index fafcd415c..9e92f12bf 100644
--- a/include/verilated_fst_c.h
+++ b/include/verilated_fst_c.h
@@ -101,6 +101,8 @@ public:
     //=========================================================================
     // Internal interface to Verilator generated code
 
+    void declEvent(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
+                 fstVarType vartype, bool array, int arraynum);
     void declBit(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                  fstVarType vartype, bool array, int arraynum);
     void declBus(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
@@ -161,6 +163,7 @@ class VerilatedFstBuffer VL_NOT_FINAL {
 
     // Implementations of duck-typed methods for VerilatedTraceBuffer. These are
     // called from only one place (the full* methods), so always inline them.
+    VL_ATTR_ALWINLINE void emitEvent(uint32_t code, VlEvent newval);
     VL_ATTR_ALWINLINE void emitBit(uint32_t code, CData newval);
     VL_ATTR_ALWINLINE void emitCData(uint32_t code, CData newval, int bits);
     VL_ATTR_ALWINLINE void emitSData(uint32_t code, SData newval, int bits);
diff --git a/include/verilated_trace.h b/include/verilated_trace.h
index 2d75ea0ab..2a19c6795 100644
--- a/include/verilated_trace.h
+++ b/include/verilated_trace.h
@@ -107,6 +107,7 @@ public:
         CHG_QDATA = 0x5,
         CHG_WDATA = 0x6,
         CHG_DOUBLE = 0x8,
+        CHG_EVENT  = 0x9,
         // TODO: full..
         TIME_CHANGE = 0xc,
         TRACE_BUFFER = 0xd,
@@ -422,6 +423,7 @@ public:
     void fullQData(uint32_t* oldp, QData newval, int bits);
     void fullWData(uint32_t* oldp, const WData* newvalp, int bits);
     void fullDouble(uint32_t* oldp, double newval);
+    void fullEvent(uint32_t* oldp, VlEvent newval);
 
     // In non-offload mode, these are called directly by the trace callbacks,
     // and are called chg*. In offload mode, they are called by the worker
@@ -456,6 +458,9 @@ public:
             }
         }
     }
+    VL_ATTR_ALWINLINE void chgEvent(uint32_t* oldp, VlEvent newval) {
+        fullEvent(oldp, newval);
+    }
     VL_ATTR_ALWINLINE void chgDouble(uint32_t* oldp, double newval) {
         // cppcheck-suppress invalidPointerCast
         if (VL_UNLIKELY(*reinterpret_cast<double*>(oldp) != newval)) fullDouble(oldp, newval);
@@ -533,6 +538,12 @@ public:
         m_offloadBufferWritep += 4;
         VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp););
     }
+    void chgEvent(uint32_t code, VlEvent newval) {
+        m_offloadBufferWritep[0] = VerilatedTraceOffloadCommand::CHG_EVENT ;
+        m_offloadBufferWritep[1] = code;
+        m_offloadBufferWritep += 2;
+        VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp););
+    }
 };
 
 #endif  // guard
diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h
index c863649c6..aa37ff9fb 100644
--- a/include/verilated_trace_imp.h
+++ b/include/verilated_trace_imp.h
@@ -183,6 +183,10 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::offloadWorkerThreadMain() {
                 traceBufp->chgDouble(oldp, *reinterpret_cast<const double*>(readp));
                 readp += 2;
                 continue;
+            case VerilatedTraceOffloadCommand::CHG_EVENT:
+                VL_TRACE_OFFLOAD_DEBUG("Command CHG_EVENT " << top);
+                traceBufp->chgEvent(oldp, *reinterpret_cast<const VlEvent*>(readp));
+                continue;
 
                 //===
                 // Rare commands
@@ -834,6 +838,13 @@ void VerilatedTraceBuffer<VL_BUF_T>::fullBit(uint32_t* oldp, CData newval) {
     emitBit(code, newval);
 }
 
+template <>
+void VerilatedTraceBuffer<VL_BUF_T>::fullEvent(uint32_t* oldp, VlEvent newval) {
+    const uint32_t code = oldp - m_sigs_oldvalp;
+    *oldp = 1;  // Do we really store an "event" ?
+    emitEvent(code, newval);
+}
+
 template <>
 void VerilatedTraceBuffer<VL_BUF_T>::fullCData(uint32_t* oldp, CData newval, int bits) {
     const uint32_t code = oldp - m_sigs_oldvalp;
diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp
index a0145b2af..c313e044c 100644
--- a/include/verilated_vcd_c.cpp
+++ b/include/verilated_vcd_c.cpp
@@ -548,6 +548,9 @@ void VerilatedVcd::declare(uint32_t code, const char* name, const char* wirep, b
     m_namemapp->emplace(hiername, decl);
 }
 
+void VerilatedVcd::declEvent(uint32_t code, const char* name, bool array, int arraynum) {
+    declare(code, name, "event", array, arraynum, false, false, 0, 0);
+}
 void VerilatedVcd::declBit(uint32_t code, const char* name, bool array, int arraynum) {
     declare(code, name, "wire", array, arraynum, false, false, 0, 0);
 }
@@ -694,6 +697,19 @@ void VerilatedVcdBuffer::finishLine(uint32_t code, char* writep) {
 // verilated_trace_imp.h, which is included in this file at the top),
 // so always inline them.
 
+VL_ATTR_ALWINLINE
+void VerilatedVcdBuffer::emitEvent(uint32_t code, VlEvent newval) {
+    const bool triggered = newval.isTriggered();
+    // TODO : It seems that untriggerd events are not filtered
+    // should be tested before this last step
+    if(triggered) {
+    // Don't prefetch suffix as it's a bit too late;
+    char* wp = m_writep;
+    *wp++ = '1' ;
+    finishLine(code, wp);
+    }
+}
+
 VL_ATTR_ALWINLINE
 void VerilatedVcdBuffer::emitBit(uint32_t code, CData newval) {
     // Don't prefetch suffix as it's a bit too late;
diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h
index 166a48322..64469d430 100644
--- a/include/verilated_vcd_c.h
+++ b/include/verilated_vcd_c.h
@@ -140,6 +140,7 @@ public:
     //=========================================================================
     // Internal interface to Verilator generated code
 
+    void declEvent(uint32_t code, const char* name, bool array, int arraynum);
     void declBit(uint32_t code, const char* name, bool array, int arraynum);
     void declBus(uint32_t code, const char* name, bool array, int arraynum, int msb, int lsb);
     void declQuad(uint32_t code, const char* name, bool array, int arraynum, int msb, int lsb);
@@ -206,6 +207,7 @@ class VerilatedVcdBuffer VL_NOT_FINAL {
     // Implementation of VerilatedTraceBuffer interface
     // Implementations of duck-typed methods for VerilatedTraceBuffer. These are
     // called from only one place (the full* methods), so always inline them.
+    VL_ATTR_ALWINLINE void emitEvent(uint32_t code, VlEvent newval);
     VL_ATTR_ALWINLINE void emitBit(uint32_t code, CData newval);
     VL_ATTR_ALWINLINE void emitCData(uint32_t code, CData newval, int bits);
     VL_ATTR_ALWINLINE void emitSData(uint32_t code, SData newval, int bits);
diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp
index cf6fa6ccd..b7db6e5b2 100644
--- a/src/V3EmitCImp.cpp
+++ b/src/V3EmitCImp.cpp
@@ -637,6 +637,8 @@ class EmitCTrace final : EmitCFunc {
             puts("tracep->declQuad");
         } else if (nodep->bitRange().ranged()) {
             puts("tracep->declBus");
+        } else if (nodep->dtypep()->basicp()->isEvent()) {
+            puts("tracep->declEvent");
         } else {
             puts("tracep->declBit");
         }
@@ -689,11 +691,11 @@ class EmitCTrace final : EmitCFunc {
             else if (kwd == VBasicDTypeKwd::SHORTINT) { fstvt = "FST_VT_SV_SHORTINT"; }
             else if (kwd == VBasicDTypeKwd::LONGINT) {  fstvt = "FST_VT_SV_LONGINT"; }
             else if (kwd == VBasicDTypeKwd::BYTE) {     fstvt = "FST_VT_SV_BYTE"; }
+            else if (kwd == VBasicDTypeKwd::EVENT) {     fstvt = "FST_VT_VCD_EVENT"; }
             else { fstvt = "FST_VT_SV_BIT"; }
             // clang-format on
             //
             // Not currently supported
-            // FST_VT_VCD_EVENT
             // FST_VT_VCD_PORT
             // FST_VT_VCD_SHORTREAL
             // FST_VT_VCD_REALTIME
@@ -779,6 +781,9 @@ class EmitCTrace final : EmitCFunc {
             puts("bufp->" + func + "SData");
         } else if (nodep->declp()->widthMin() > 1) {
             puts("bufp->" + func + "CData");
+        } else if (nodep->dtypep()->basicp()->isEvent()) {
+            puts("bufp->" + func + "Event");
+            emitWidth = false;
         } else {
             puts("bufp->" + func + "Bit");
             emitWidth = false;
diff --git a/test_regress/t/t_timing_trace.out b/test_regress/t/t_timing_trace.out
index f4c2f96b8..f1a84fcb5 100644
--- a/test_regress/t/t_timing_trace.out
+++ b/test_regress/t/t_timing_trace.out
@@ -1,16 +1,17 @@
 $version Generated by VerilatedVcd $end
-$date Thu Oct 20 09:56:59 2022 $end
+$date Tue Nov 22 16:48:14 2022 $end
 $timescale 1ps $end
 
  $scope module TOP $end
   $scope module t $end
-   $var wire 32 * CLK_HALF_PERIOD [31:0] $end
-   $var wire 32 ) CLK_PERIOD [31:0] $end
+   $var wire 32 + CLK_HALF_PERIOD [31:0] $end
+   $var wire 32 * CLK_PERIOD [31:0] $end
    $var wire  1 $ a $end
    $var wire  1 % b $end
    $var wire  1 & c $end
-   $var wire  1 ( clk $end
+   $var wire  1 ) clk $end
    $var wire  1 ' d $end
+   $var event  1 ( ev $end
    $var wire  1 # rst $end
   $upscope $end
  $upscope $end
@@ -23,54 +24,57 @@ $enddefinitions $end
 0%
 0&
 0'
-0(
-b00000000000000000000000000001010 )
-b00000000000000000000000000000101 *
+0)
+b00000000000000000000000000001010 *
+b00000000000000000000000000000101 +
 #5
-1(
+1)
 #10
 0#
 1%
-0(
+1(
+0)
 #15
-1(
+1)
 #20
-0(
+1(
+0)
 #25
-1(
+1)
 #30
-0(
+0)
 #35
-1(
+1)
 #40
-0(
+0)
 #45
-1(
+1)
 #50
-0(
+0)
 #55
-1(
+1)
 #60
-0(
+0)
 #65
-1(
+1)
 #70
-0(
+0)
 #75
-1(
+1)
 #80
-0(
+0)
 #85
-1(
+1)
 #90
-0(
+0)
 #95
-1(
+1)
 #100
-0(
+0)
 #105
-1(
+1)
 #110
 1#
 0%
-0(
+1(
+0)
diff --git a/test_regress/t/t_timing_trace.v b/test_regress/t/t_timing_trace.v
index af789dbeb..9893856cc 100644
--- a/test_regress/t/t_timing_trace.v
+++ b/test_regress/t/t_timing_trace.v
@@ -16,6 +16,7 @@ module t;
     logic b;
     logic c;
     logic d;
+    event ev;
 
     initial begin
         $dumpfile(`STRINGIFY(`TEST_DUMPFILE));
@@ -34,10 +35,15 @@ module t;
         #CLK_PERIOD;
         rst = 0;
         b = 1;
+        -> ev ;
+        #CLK_PERIOD;
+        -> ev ;
 
-        #(10 * CLK_PERIOD);
+        #(9 * CLK_PERIOD);
+        -> ev ;
 
         $write("*-* All Finished *-*\n");
         $finish;
     end
+
 endmodule
diff --git a/test_regress/t/t_timing_trace_fst.out b/test_regress/t/t_timing_trace_fst.out
new file mode 100644
index 000000000..a0170939c
--- /dev/null
+++ b/test_regress/t/t_timing_trace_fst.out
@@ -0,0 +1,87 @@
+$date
+	Tue Nov 22 18:14:18 2022
+
+$end
+$version
+	fstWriter
+$end
+$timescale
+	1ps
+$end
+$scope module TOP $end
+$scope module t $end
+$var parameter 32 ! CLK_PERIOD [31:0] $end
+$var parameter 32 " CLK_HALF_PERIOD [31:0] $end
+$var logic 1 # rst $end
+$var logic 1 $ clk $end
+$var logic 1 % a $end
+$var logic 1 & b $end
+$var logic 1 ' c $end
+$var logic 1 ( d $end
+$var event 1 ) ev $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+1)
+0(
+0'
+0&
+0%
+0$
+1#
+b00000000000000000000000000000101 "
+b00000000000000000000000000001010 !
+$end
+#5
+1$
+#10
+0$
+0#
+1&
+1)
+#15
+1$
+#20
+0$
+1)
+#25
+1$
+#30
+0$
+#35
+1$
+#40
+0$
+#45
+1$
+#50
+0$
+#55
+1$
+#60
+0$
+#65
+1$
+#70
+0$
+#75
+1$
+#80
+0$
+#85
+1$
+#90
+0$
+#95
+1$
+#100
+0$
+#105
+1$
+#110
+0$
+1)
+0&
+1#
diff --git a/test_regress/t/t_timing_trace_fst.pl b/test_regress/t/t_timing_trace_fst.pl
new file mode 100755
index 000000000..0ac004740
--- /dev/null
+++ b/test_regress/t/t_timing_trace_fst.pl
@@ -0,0 +1,32 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 Yves Mathieu. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+top_filename("t/t_timing_trace.v");
+
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    compile(
+        verilator_flags2 => ["--exe --main --timing --trace-fst -Wno-MINTYPMAXDLY"],
+        make_main => 0,
+        );
+
+    execute(
+        check_finished => 1,
+        );
+
+    fst_identical($Self->trace_filename, $Self->{golden_filename});
+}
+
+ok(1);
+1;

From 821dd070bf1f357ad10960f7e6d1ac0c4dcbe4b0 Mon Sep 17 00:00:00 2001
From: github action <action@example.com>
Date: Wed, 23 Nov 2022 09:08:02 +0000
Subject: [PATCH 088/156] Apply 'make format'

---
 include/verilated_fst_c.cpp |  6 +++---
 include/verilated_fst_c.h   |  2 +-
 include/verilated_trace.h   |  8 +++-----
 include/verilated_vcd_c.cpp | 10 +++++-----
 4 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp
index de5f4bbc4..6dd5bbd84 100644
--- a/include/verilated_fst_c.cpp
+++ b/include/verilated_fst_c.cpp
@@ -222,7 +222,7 @@ void VerilatedFst::declare(uint32_t code, const char* name, int dtypenum, fstVar
 }
 
 void VerilatedFst::declEvent(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
-                           fstVarType vartype, bool array, int arraynum) {
+                             fstVarType vartype, bool array, int arraynum) {
     declare(code, name, dtypenum, vardir, vartype, array, arraynum, false, 0, 0);
 }
 void VerilatedFst::declBit(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
@@ -285,8 +285,8 @@ void VerilatedFst::configure(const VerilatedTraceConfig& config) {
 
 VL_ATTR_ALWINLINE
 void VerilatedFstBuffer::emitEvent(uint32_t code, VlEvent newval) {
-        VL_DEBUG_IFDEF(assert(m_symbolp[code]););
-        fstWriterEmitValueChange(m_fst, m_symbolp[code], "1");
+    VL_DEBUG_IFDEF(assert(m_symbolp[code]););
+    fstWriterEmitValueChange(m_fst, m_symbolp[code], "1");
 }
 
 VL_ATTR_ALWINLINE
diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h
index 9e92f12bf..dea14aeb6 100644
--- a/include/verilated_fst_c.h
+++ b/include/verilated_fst_c.h
@@ -102,7 +102,7 @@ public:
     // Internal interface to Verilator generated code
 
     void declEvent(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
-                 fstVarType vartype, bool array, int arraynum);
+                   fstVarType vartype, bool array, int arraynum);
     void declBit(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
                  fstVarType vartype, bool array, int arraynum);
     void declBus(uint32_t code, const char* name, int dtypenum, fstVarDir vardir,
diff --git a/include/verilated_trace.h b/include/verilated_trace.h
index 2a19c6795..b9cf68c6c 100644
--- a/include/verilated_trace.h
+++ b/include/verilated_trace.h
@@ -107,7 +107,7 @@ public:
         CHG_QDATA = 0x5,
         CHG_WDATA = 0x6,
         CHG_DOUBLE = 0x8,
-        CHG_EVENT  = 0x9,
+        CHG_EVENT = 0x9,
         // TODO: full..
         TIME_CHANGE = 0xc,
         TRACE_BUFFER = 0xd,
@@ -458,9 +458,7 @@ public:
             }
         }
     }
-    VL_ATTR_ALWINLINE void chgEvent(uint32_t* oldp, VlEvent newval) {
-        fullEvent(oldp, newval);
-    }
+    VL_ATTR_ALWINLINE void chgEvent(uint32_t* oldp, VlEvent newval) { fullEvent(oldp, newval); }
     VL_ATTR_ALWINLINE void chgDouble(uint32_t* oldp, double newval) {
         // cppcheck-suppress invalidPointerCast
         if (VL_UNLIKELY(*reinterpret_cast<double*>(oldp) != newval)) fullDouble(oldp, newval);
@@ -539,7 +537,7 @@ public:
         VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp););
     }
     void chgEvent(uint32_t code, VlEvent newval) {
-        m_offloadBufferWritep[0] = VerilatedTraceOffloadCommand::CHG_EVENT ;
+        m_offloadBufferWritep[0] = VerilatedTraceOffloadCommand::CHG_EVENT;
         m_offloadBufferWritep[1] = code;
         m_offloadBufferWritep += 2;
         VL_DEBUG_IF(assert(m_offloadBufferWritep <= m_offloadBufferEndp););
diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp
index c313e044c..69e7b0654 100644
--- a/include/verilated_vcd_c.cpp
+++ b/include/verilated_vcd_c.cpp
@@ -702,11 +702,11 @@ void VerilatedVcdBuffer::emitEvent(uint32_t code, VlEvent newval) {
     const bool triggered = newval.isTriggered();
     // TODO : It seems that untriggerd events are not filtered
     // should be tested before this last step
-    if(triggered) {
-    // Don't prefetch suffix as it's a bit too late;
-    char* wp = m_writep;
-    *wp++ = '1' ;
-    finishLine(code, wp);
+    if (triggered) {
+        // Don't prefetch suffix as it's a bit too late;
+        char* wp = m_writep;
+        *wp++ = '1';
+        finishLine(code, wp);
     }
 }
 

From a83ed6b06faf94a2ee4d2f4c392d3fa277567030 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 23 Nov 2022 07:04:22 -0500
Subject: [PATCH 089/156] Internals: Fix destructor calling virtual. No
 functional change intended.

---
 include/verilated_save.cpp | 10 +++++-----
 include/verilated_save.h   | 24 +++++++++++++++---------
 2 files changed, 20 insertions(+), 14 deletions(-)

diff --git a/include/verilated_save.cpp b/include/verilated_save.cpp
index f2c80363d..a4dd64562 100644
--- a/include/verilated_save.cpp
+++ b/include/verilated_save.cpp
@@ -172,18 +172,18 @@ void VerilatedRestore::open(const char* filenamep) VL_MT_UNSAFE_ONE {
     header();
 }
 
-void VerilatedSave::close() VL_MT_UNSAFE_ONE {
+void VerilatedSave::closeImp() VL_MT_UNSAFE_ONE {
     if (!isOpen()) return;
     trailer();
-    flush();
+    flushImp();
     m_isOpen = false;
     ::close(m_fd);  // May get error, just ignore it
 }
 
-void VerilatedRestore::close() VL_MT_UNSAFE_ONE {
+void VerilatedRestore::closeImp() VL_MT_UNSAFE_ONE {
     if (!isOpen()) return;
     trailer();
-    flush();
+    flushImp();
     m_isOpen = false;
     ::close(m_fd);  // May get error, just ignore it
 }
@@ -191,7 +191,7 @@ void VerilatedRestore::close() VL_MT_UNSAFE_ONE {
 //=============================================================================
 // Buffer management
 
-void VerilatedSave::flush() VL_MT_UNSAFE_ONE {
+void VerilatedSave::flushImp() VL_MT_UNSAFE_ONE {
     m_assertOne.check();
     if (VL_UNLIKELY(!isOpen())) return;
     const uint8_t* wp = m_bufp;
diff --git a/include/verilated_save.h b/include/verilated_save.h
index 71d01fa49..5b3385b1e 100644
--- a/include/verilated_save.h
+++ b/include/verilated_save.h
@@ -62,9 +62,9 @@ public:
         m_bufp = new uint8_t[bufferSize()];
         m_cp = m_bufp;
     }
-    /// Flish, close, and destruct
+    /// Flush, close, and destruct
     virtual ~VerilatedSerialize() {
-        close();
+        // Child classes will need to typically call closeImp() in destructors
         if (m_bufp) VL_DO_CLEAR(delete[] m_bufp, m_bufp = nullptr);
     }
     // METHODS
@@ -137,7 +137,7 @@ public:
     }
     /// Destruct
     virtual ~VerilatedDeserialize() {
-        close();
+        // Child classes will need to typically call closeImp() in destructors
         if (m_bufp) VL_DO_CLEAR(delete[] m_bufp, m_bufp = nullptr);
     }
     // METHODS
@@ -190,21 +190,24 @@ class VerilatedSave final : public VerilatedSerialize {
 private:
     int m_fd = -1;  // File descriptor we're writing to
 
+    void closeImp() VL_MT_UNSAFE_ONE;
+    void flushImp() VL_MT_UNSAFE_ONE;
+
 public:
     // CONSTRUCTORS
     /// Construct new object
     VerilatedSave() = default;
     /// Flush, close and destruct
-    ~VerilatedSave() override { close(); }
+    ~VerilatedSave() override { closeImp(); }
     // METHODS
     /// Open the file; call isOpen() to see if errors
     void open(const char* filenamep) VL_MT_UNSAFE_ONE;
     /// Open the file; call isOpen() to see if errors
     void open(const std::string& filename) VL_MT_UNSAFE_ONE { open(filename.c_str()); }
     /// Flush and close the file
-    void close() override VL_MT_UNSAFE_ONE;
+    void close() override VL_MT_UNSAFE_ONE { closeImp(); }
     /// Flush data to file
-    void flush() override VL_MT_UNSAFE_ONE;
+    void flush() override VL_MT_UNSAFE_ONE { flushImp(); }
 };
 
 //=============================================================================
@@ -217,12 +220,15 @@ class VerilatedRestore final : public VerilatedDeserialize {
 private:
     int m_fd = -1;  // File descriptor we're writing to
 
+    void closeImp() VL_MT_UNSAFE_ONE;
+    void flushImp() VL_MT_UNSAFE_ONE {}
+
 public:
     // CONSTRUCTORS
     /// Construct new object
     VerilatedRestore() = default;
     /// Flush, close and destruct
-    ~VerilatedRestore() override { close(); }
+    ~VerilatedRestore() override { closeImp(); }
 
     // METHODS
     /// Open the file; call isOpen() to see if errors
@@ -230,8 +236,8 @@ public:
     /// Open the file; call isOpen() to see if errors
     void open(const std::string& filename) VL_MT_UNSAFE_ONE { open(filename.c_str()); }
     /// Close the file
-    void close() override VL_MT_UNSAFE_ONE;
-    void flush() override VL_MT_UNSAFE_ONE {}
+    void close() override VL_MT_UNSAFE_ONE { closeImp(); }
+    void flush() override VL_MT_UNSAFE_ONE { flushImp(); }
     void fill() override VL_MT_UNSAFE_ONE;
 };
 

From 68f8617f791ab6d85cf75f31e73d701161ed16aa Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Wed, 23 Nov 2022 19:15:10 +0100
Subject: [PATCH 090/156] Support member selects in with clauses (#3775)

---
 src/V3LinkDot.cpp                      |  5 ++++-
 test_regress/t/t_queue_method.v        | 22 ++++++++++++++++++++++
 test_regress/t/t_queue_method3_bad.out | 10 ++++++++++
 test_regress/t/t_queue_method3_bad.pl  | 19 +++++++++++++++++++
 test_regress/t/t_queue_method3_bad.v   | 21 +++++++++++++++++++++
 5 files changed, 76 insertions(+), 1 deletion(-)
 create mode 100644 test_regress/t/t_queue_method3_bad.out
 create mode 100755 test_regress/t/t_queue_method3_bad.pl
 create mode 100644 test_regress/t/t_queue_method3_bad.v

diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 8bfa0fae8..7c6c601eb 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -2347,9 +2347,11 @@ private:
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
             return;
         }
-        if (m_ds.m_dotPos == DP_FINAL && VN_IS(m_ds.m_unlinkedScopep, LambdaArgRef)
+        if (m_ds.m_dotPos == DP_MEMBER && VN_IS(m_ds.m_dotp->lhsp(), LambdaArgRef)
             && nodep->name() == "index") {
             // 'with' statement's 'item.index'
+            // m_ds.dotp->lhsp() was checked to know if `index` is directly after lambda arg ref.
+            // If not, treat it as normal member select
             iterateChildren(nodep);
             const auto newp = new AstLambdaArgRef{
                 nodep->fileline(), m_ds.m_unlinkedScopep->name() + "__DOT__index", true};
@@ -2577,6 +2579,7 @@ private:
                     nodep->replaceWith(newp);
                     VL_DO_DANGLING(pushDeletep(nodep), nodep);
                     ok = true;
+                    m_ds.m_dotPos = DP_MEMBER;
                     m_ds.m_dotText = "";
                 }
             }
diff --git a/test_regress/t/t_queue_method.v b/test_regress/t/t_queue_method.v
index 0b7bd29b0..24c90e470 100644
--- a/test_regress/t/t_queue_method.v
+++ b/test_regress/t/t_queue_method.v
@@ -11,6 +11,8 @@
 `define checkg(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='%g' exp='%g'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 
 module t (/*AUTOARG*/);
+   typedef struct packed { int x, y; } point;
+   typedef struct packed { point p; int z; } point_3d;
    initial begin
       int q[$];
       int qe[$];  // Empty
@@ -19,6 +21,18 @@ module t (/*AUTOARG*/);
       int qi[$];  // Index returns
       int i;
       string v;
+      string string_q[$];
+      string string_qv[$];
+      point_3d points_q[$];  // Same as q and qv, but complex value type
+      point_3d points_qv[$];
+
+      points_q.push_back(point_3d'{point'{1, 2}, 3});
+      points_q.push_back(point_3d'{point'{2, 3}, 5});
+      points_q.push_back(point_3d'{point'{1, 4}, 5});
+
+      string_q.push_back("a");
+      string_q.push_back("A");
+      string_q.push_back("b");
 
       q = '{1, 2, 2, 4, 3};
       v = $sformatf("%p", q); `checks(v, "'{'h1, 'h2, 'h2, 'h4, 'h3} ");
@@ -46,6 +60,8 @@ module t (/*AUTOARG*/);
       `checkh(qv.size(), 0);
       qv = q.unique(x) with (x % 2);
       `checkh(qv.size(), 2);
+      string_qv = string_q.unique(s) with (s.toupper);
+      `checkh(string_qv.size(), 2);
       qi = q.unique_index; qv.sort;
       // According to 7.12.1 of IEEE Std 1800-2017, it is not specified which index of duplicated value should be returned
       `checkh(qi.size(), 4);
@@ -73,8 +89,14 @@ module t (/*AUTOARG*/);
       v = $sformatf("%p", qv); `checks(v, "'{'h1, 'h3} ");
       qv = q.find_first with (item == 2);
       v = $sformatf("%p", qv); `checks(v, "'{'h2} ");
+      points_qv = points_q.find_first with (item.z == 5);
+      `checkh(points_qv[0].p.y, 3);
+      points_qv = points_q.find_first with (item.p.x == 1);
+      `checkh(points_qv[0].p.y, 2);
       qv = q.find_last with (item == 2);
       v = $sformatf("%p", qv); `checks(v, "'{'h2} ");
+      string_qv = string_q.find_last(s) with (s.tolower() == "a");
+      `checks(string_qv[0], "A");
 
       qv = q.find with (item == 20);
       `checkh(qv.size, 0);
diff --git a/test_regress/t/t_queue_method3_bad.out b/test_regress/t/t_queue_method3_bad.out
new file mode 100644
index 000000000..4beb3e580
--- /dev/null
+++ b/test_regress/t/t_queue_method3_bad.out
@@ -0,0 +1,10 @@
+%Error-UNSUPPORTED: t/t_queue_method3_bad.v:16:52: Unsupported: Member call on object 'SEL' which is a 'BASICDTYPE 'int''
+                                                 : ... In instance t
+   16 |       points_qv = points_q.find_first(a) with (a.x.index == 0);
+      |                                                    ^~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: Internal Error: t/t_queue_method3_bad.v:16:58: ../V3Width.cpp:#: Node has no type
+                                                     : ... In instance t
+   16 |       points_qv = points_q.find_first(a) with (a.x.index == 0);
+      |                                                          ^~
+                        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.
diff --git a/test_regress/t/t_queue_method3_bad.pl b/test_regress/t/t_queue_method3_bad.pl
new file mode 100755
index 000000000..fbdf9000e
--- /dev/null
+++ b/test_regress/t/t_queue_method3_bad.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_queue_method3_bad.v b/test_regress/t/t_queue_method3_bad.v
new file mode 100644
index 000000000..274690022
--- /dev/null
+++ b/test_regress/t/t_queue_method3_bad.v
@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+   typedef struct packed { int x, y; } point;
+   initial begin
+      point points_q[$];
+      point points_qv[$];
+      points_q.push_back(point'{1, 2});
+
+      // `index` should be treated as normal member select,
+      // but the member is not present in the struct
+      points_qv = points_q.find_first(a) with (a.x.index == 0);
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

From 4b3731d31805324b72ca5bdb62c9ed6abb031db5 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 23 Nov 2022 18:50:31 -0500
Subject: [PATCH 091/156] Remove env from main() to be C++11 compatible

---
 docs/guide/connecting.rst                    | 2 +-
 docs/guide/example_cc.rst                    | 2 +-
 docs/guide/faq.rst                           | 4 ++--
 examples/make_hello_c/sim_main.cpp           | 9 +++++----
 examples/make_hello_sc/sc_main.cpp           | 7 ++++---
 examples/make_protect_lib/sim_main.cpp       | 4 ++--
 examples/make_tracing_c/sim_main.cpp         | 4 ++--
 src/Verilator.cpp                            | 2 +-
 src/VlcMain.cpp                              | 2 +-
 test_regress/driver.pl                       | 2 +-
 test_regress/t/t_clk_inp_init.cpp            | 2 +-
 test_regress/t/t_comb_input_0.cpp            | 2 +-
 test_regress/t/t_comb_input_1.cpp            | 2 +-
 test_regress/t/t_comb_input_2.cpp            | 2 +-
 test_regress/t/t_dpi_var.cpp                 | 2 +-
 test_regress/t/t_gantt_two.cpp               | 2 +-
 test_regress/t/t_public_clk.cpp              | 2 +-
 test_regress/t/t_public_seq.cpp              | 2 +-
 test_regress/t/t_scope_map.cpp               | 2 +-
 test_regress/t/t_trace_cat.cpp               | 2 +-
 test_regress/t/t_trace_cat_fst.cpp           | 2 +-
 test_regress/t/t_trace_dumpvars_dyn.cpp      | 2 +-
 test_regress/t/t_trace_public_func.cpp       | 2 +-
 test_regress/t/t_trace_public_sig.cpp        | 2 +-
 test_regress/t/t_trace_rollover.cpp          | 2 +-
 test_regress/t/t_trace_two_cc.cpp            | 2 +-
 test_regress/t/t_var_overwidth_bad.cpp       | 2 +-
 test_regress/t/t_vpi_cb_iter.cpp             | 2 +-
 test_regress/t/t_vpi_cbs_called.cpp          | 2 +-
 test_regress/t/t_vpi_get.cpp                 | 2 +-
 test_regress/t/t_vpi_memory.cpp              | 2 +-
 test_regress/t/t_vpi_module.cpp              | 2 +-
 test_regress/t/t_vpi_param.cpp               | 2 +-
 test_regress/t/t_vpi_time_cb.cpp             | 2 +-
 test_regress/t/t_vpi_unimpl.cpp              | 2 +-
 test_regress/t/t_vpi_var.cpp                 | 2 +-
 test_regress/t/t_vpi_zero_time_cb.cpp        | 2 +-
 test_regress/t/t_wrapper_context.cpp         | 2 +-
 test_regress/t/t_wrapper_del_context_bad.cpp | 2 +-
 test_regress/t/t_wrapper_legacy.cpp          | 2 +-
 40 files changed, 50 insertions(+), 48 deletions(-)

diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst
index 638f5c33d..16f569007 100644
--- a/docs/guide/connecting.rst
+++ b/docs/guide/connecting.rst
@@ -406,7 +406,7 @@ accesses the above signal "readme" would be:
            printf("Value of v: %d\n", v.value.integer);  // Prints "readme"
        }
 
-       int main(int argc, char** argv, char** env) {
+       int main(int argc, char** argv) {
            Verilated::commandArgs(argc, argv);
            const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
            const std::unique_ptr<Vour> top{new Vour{contextp.get()}};
diff --git a/docs/guide/example_cc.rst b/docs/guide/example_cc.rst
index 192704559..3d8662aba 100644
--- a/docs/guide/example_cc.rst
+++ b/docs/guide/example_cc.rst
@@ -28,7 +28,7 @@ Now, let's create an example Verilog, and C++ wrapper file:
      cat >sim_main.cpp <<'EOF'
        #include "Vour.h"
        #include "verilated.h"
-       int main(int argc, char** argv, char** env) {
+       int main(int argc, char** argv) {
            VerilatedContext* contextp = new VerilatedContext;
            contextp->commandArgs(argc, argv);
            Vour* top = new Vour{contextp};
diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst
index 0b70ea289..46d52a3b5 100644
--- a/docs/guide/faq.rst
+++ b/docs/guide/faq.rst
@@ -144,7 +144,7 @@ B. Or, for finer-grained control, or C++ files with multiple Verilated
 
       #include "verilated_vcd_c.h"
       ...
-      int main(int argc, char** argv, char** env) {
+      int main(int argc, char** argv) {
           const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
           ...
           Verilated::traceEverOn(true);
@@ -197,7 +197,7 @@ C. Alternatively you may use the C++ trace mechanism described in the
 
       #include "verilated_vcd_sc.h"
       ...
-      int main(int argc, char** argv, char** env) {
+      int main(int argc, char** argv) {
           ...
           Verilated::traceEverOn(true);
           VerilatedVcdSc* tfp = new VerilatedVcdSc;
diff --git a/examples/make_hello_c/sim_main.cpp b/examples/make_hello_c/sim_main.cpp
index 2e605d512..f2df7b52e 100644
--- a/examples/make_hello_c/sim_main.cpp
+++ b/examples/make_hello_c/sim_main.cpp
@@ -11,19 +11,20 @@
 // Include model header, generated from Verilating "top.v"
 #include "Vtop.h"
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     // See a similar example walkthrough in the verilator manpage.
 
     // This is intended to be a minimal example.  Before copying this to start a
     // real project, it is better to start with a more complete example,
     // e.g. examples/c_tracing.
 
-    // Prevent unused variable warnings
-    if (false && argc && argv && env) {}
-
     // Construct a VerilatedContext to hold simulation time, etc.
     VerilatedContext* contextp = new VerilatedContext;
 
+    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+    // This needs to be called before you create any model
+    contextp->commandArgs(argc, argv);
+
     // Construct the Verilated model, from Vtop.h generated from Verilating "top.v"
     Vtop* top = new Vtop{contextp};
 
diff --git a/examples/make_hello_sc/sc_main.cpp b/examples/make_hello_sc/sc_main.cpp
index 587010712..91fe02220 100644
--- a/examples/make_hello_sc/sc_main.cpp
+++ b/examples/make_hello_sc/sc_main.cpp
@@ -22,12 +22,13 @@ int sc_main(int argc, char* argv[]) {
     // real project, it is better to start with a more complete example,
     // e.g. examples/c_tracing.
 
-    // Prevent unused variable warnings
-    if (false && argc && argv) {}
-
     // Construct the Verilated model, from Vtop.h generated from Verilating "top.v"
     Vtop* top = new Vtop{"top"};
 
+    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+    // This needs to be called before you create any model
+    Verilated::commandArgs(argc, argv);
+
     // Initialize SC model
     sc_start(1, SC_NS);
 
diff --git a/examples/make_protect_lib/sim_main.cpp b/examples/make_protect_lib/sim_main.cpp
index fefcb0c5a..0c11180f5 100644
--- a/examples/make_protect_lib/sim_main.cpp
+++ b/examples/make_protect_lib/sim_main.cpp
@@ -16,8 +16,8 @@
 #include <verilated_vcd_c.h>
 #endif
 
-int main(int argc, char** argv, char** env) {
-    if (false && argc && argv && env) {}
+int main(int argc, char** argv) {
+    if (false && argc && argv) {}
 
     // Construct context to hold simulation time, etc
     VerilatedContext* contextp = new VerilatedContext;
diff --git a/examples/make_tracing_c/sim_main.cpp b/examples/make_tracing_c/sim_main.cpp
index 06d399901..a49225cdc 100644
--- a/examples/make_tracing_c/sim_main.cpp
+++ b/examples/make_tracing_c/sim_main.cpp
@@ -17,11 +17,11 @@
 // Legacy function required only so linking works on Cygwin and MSVC++
 double sc_time_stamp() { return 0; }
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     // This is a more complicated example, please also see the simpler examples/make_hello_c.
 
     // Prevent unused variable warnings
-    if (false && argc && argv && env) {}
+    if (false && argc && argv) {}
 
     // Create logs/ directory in case we have traces to put under it
     Verilated::mkdir("logs");
diff --git a/src/Verilator.cpp b/src/Verilator.cpp
index febe42703..464e68e4e 100644
--- a/src/Verilator.cpp
+++ b/src/Verilator.cpp
@@ -721,7 +721,7 @@ static void execHierVerilation() {
 
 //######################################################################
 
-int main(int argc, char** argv, char** /*env*/) {
+int main(int argc, char** argv) {
     // General initialization
     std::ios::sync_with_stdio();
 
diff --git a/src/VlcMain.cpp b/src/VlcMain.cpp
index 5f1b01ec5..a2f93f043 100644
--- a/src/VlcMain.cpp
+++ b/src/VlcMain.cpp
@@ -113,7 +113,7 @@ void VlcOptions::showVersion(bool verbose) {
 
 //######################################################################
 
-int main(int argc, char** argv, char** /*env*/) {
+int main(int argc, char** argv) {
     // General initialization
     std::ios::sync_with_stdio();
 
diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 86bee331e..29e7b7c32 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -1788,7 +1788,7 @@ sub _make_main {
         print $fh "    sc_set_time_resolution(1, $Self->{sc_time_resolution});\n";
         print $fh "    sc_time sim_time($self->{sim_time}, $Self->{sc_time_resolution});\n";
     } else {
-        print $fh "int main(int argc, char** argv, char** env) {\n";
+        print $fh "int main(int argc, char** argv) {\n";
         print $fh "    uint64_t sim_time = $self->{sim_time};\n";
     }
 
diff --git a/test_regress/t/t_clk_inp_init.cpp b/test_regress/t/t_clk_inp_init.cpp
index b8a31e3f2..c80c819a3 100644
--- a/test_regress/t/t_clk_inp_init.cpp
+++ b/test_regress/t/t_clk_inp_init.cpp
@@ -51,7 +51,7 @@ void oneTest(int argc, char** argv, int seed) {
     topp->final();
 }
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
 #if VL_DEBUG
     // Verilated::debug(1);
 #endif
diff --git a/test_regress/t/t_comb_input_0.cpp b/test_regress/t/t_comb_input_0.cpp
index 03db9b00d..926562092 100644
--- a/test_regress/t/t_comb_input_0.cpp
+++ b/test_regress/t/t_comb_input_0.cpp
@@ -16,7 +16,7 @@
 
 #include <memory>
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
     contextp->commandArgs(argc, argv);
     contextp->debug(0);
diff --git a/test_regress/t/t_comb_input_1.cpp b/test_regress/t/t_comb_input_1.cpp
index ffd4c0e52..0277f3ca1 100644
--- a/test_regress/t/t_comb_input_1.cpp
+++ b/test_regress/t/t_comb_input_1.cpp
@@ -16,7 +16,7 @@
 
 #include <memory>
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
     contextp->commandArgs(argc, argv);
     contextp->debug(0);
diff --git a/test_regress/t/t_comb_input_2.cpp b/test_regress/t/t_comb_input_2.cpp
index 69138e068..527cfae3d 100644
--- a/test_regress/t/t_comb_input_2.cpp
+++ b/test_regress/t/t_comb_input_2.cpp
@@ -16,7 +16,7 @@
 
 #include <memory>
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
     contextp->commandArgs(argc, argv);
     contextp->debug(0);
diff --git a/test_regress/t/t_dpi_var.cpp b/test_regress/t/t_dpi_var.cpp
index 5f9ee79f1..d494db7f3 100644
--- a/test_regress/t/t_dpi_var.cpp
+++ b/test_regress/t/t_dpi_var.cpp
@@ -110,7 +110,7 @@ void mon_eval() {
 
 //======================================================================
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     uint64_t sim_time = 1100;
diff --git a/test_regress/t/t_gantt_two.cpp b/test_regress/t/t_gantt_two.cpp
index 5754c91fe..04b412836 100644
--- a/test_regress/t/t_gantt_two.cpp
+++ b/test_regress/t/t_gantt_two.cpp
@@ -12,7 +12,7 @@
 
 #include <memory>
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     srand48(5);
 
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
diff --git a/test_regress/t/t_public_clk.cpp b/test_regress/t/t_public_clk.cpp
index 15ff2985b..ebed647f7 100644
--- a/test_regress/t/t_public_clk.cpp
+++ b/test_regress/t/t_public_clk.cpp
@@ -13,7 +13,7 @@
 #include "verilated.h"
 
 std::unique_ptr<Vt_public_clk> topp;
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     vluint64_t sim_time = 1100;
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
     contextp->commandArgs(argc, argv);
diff --git a/test_regress/t/t_public_seq.cpp b/test_regress/t/t_public_seq.cpp
index 26906bd88..f69b3ab8d 100644
--- a/test_regress/t/t_public_seq.cpp
+++ b/test_regress/t/t_public_seq.cpp
@@ -13,7 +13,7 @@
 #include "verilated.h"
 
 std::unique_ptr<Vt_public_seq> topp;
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     vluint64_t sim_time = 1100;
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
     contextp->commandArgs(argc, argv);
diff --git a/test_regress/t/t_scope_map.cpp b/test_regress/t/t_scope_map.cpp
index d9f554d8b..bfd276936 100644
--- a/test_regress/t/t_scope_map.cpp
+++ b/test_regress/t/t_scope_map.cpp
@@ -17,7 +17,7 @@
 
 const unsigned long long dt_2 = 3;
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     Vt_scope_map* top = new Vt_scope_map{contextp.get(), "top"};
diff --git a/test_regress/t/t_trace_cat.cpp b/test_regress/t/t_trace_cat.cpp
index 914f87a84..bc5cc83bc 100644
--- a/test_regress/t/t_trace_cat.cpp
+++ b/test_regress/t/t_trace_cat.cpp
@@ -22,7 +22,7 @@ const char* trace_name() {
     return name;
 }
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     std::unique_ptr<VM_PREFIX> top{new VM_PREFIX("top")};
 
     Verilated::debug(0);
diff --git a/test_regress/t/t_trace_cat_fst.cpp b/test_regress/t/t_trace_cat_fst.cpp
index bb35df44b..d541834a1 100644
--- a/test_regress/t/t_trace_cat_fst.cpp
+++ b/test_regress/t/t_trace_cat_fst.cpp
@@ -22,7 +22,7 @@ const char* trace_name() {
     return name;
 }
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     std::unique_ptr<VM_PREFIX> top{new VM_PREFIX("top")};
 
     Verilated::debug(0);
diff --git a/test_regress/t/t_trace_dumpvars_dyn.cpp b/test_regress/t/t_trace_dumpvars_dyn.cpp
index 02634e50a..57f8c50ca 100644
--- a/test_regress/t/t_trace_dumpvars_dyn.cpp
+++ b/test_regress/t/t_trace_dumpvars_dyn.cpp
@@ -19,7 +19,7 @@ double sc_time_stamp() { return (double)main_time; }
 
 const unsigned long long dt_2 = 3;
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     std::unique_ptr<VM_PREFIX> top{new VM_PREFIX("top")};
 
     Verilated::debug(0);
diff --git a/test_regress/t/t_trace_public_func.cpp b/test_regress/t/t_trace_public_func.cpp
index bd31c9a6f..cd65cf622 100644
--- a/test_regress/t/t_trace_public_func.cpp
+++ b/test_regress/t/t_trace_public_func.cpp
@@ -27,7 +27,7 @@ double sc_time_stamp() { return (double)main_time; }
 
 const unsigned long long dt_2 = 3;
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     std::unique_ptr<VM_PREFIX> top{new VM_PREFIX("top")};
 
     Verilated::debug(0);
diff --git a/test_regress/t/t_trace_public_sig.cpp b/test_regress/t/t_trace_public_sig.cpp
index 04d5be921..7295bd20c 100644
--- a/test_regress/t/t_trace_public_sig.cpp
+++ b/test_regress/t/t_trace_public_sig.cpp
@@ -25,7 +25,7 @@ double sc_time_stamp() { return (double)main_time; }
 
 const unsigned long long dt_2 = 3;
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     VM_PREFIX* top = new VM_PREFIX{"top"};
 
     Verilated::debug(0);
diff --git a/test_regress/t/t_trace_rollover.cpp b/test_regress/t/t_trace_rollover.cpp
index f2331b124..b9f72042b 100644
--- a/test_regress/t/t_trace_rollover.cpp
+++ b/test_regress/t/t_trace_rollover.cpp
@@ -16,7 +16,7 @@
 unsigned long long main_time = 0;
 double sc_time_stamp() { return (double)main_time; }
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     std::unique_ptr<VM_PREFIX> top{new VM_PREFIX("top")};
 
     Verilated::debug(0);
diff --git a/test_regress/t/t_trace_two_cc.cpp b/test_regress/t/t_trace_two_cc.cpp
index 31c314f86..9b4378a40 100644
--- a/test_regress/t/t_trace_two_cc.cpp
+++ b/test_regress/t/t_trace_two_cc.cpp
@@ -26,7 +26,7 @@
 VM_PREFIX* ap;
 Vt_trace_two_b* bp;
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     uint64_t sim_time = 1100;
diff --git a/test_regress/t/t_var_overwidth_bad.cpp b/test_regress/t/t_var_overwidth_bad.cpp
index 586314a73..e0f45a1b0 100644
--- a/test_regress/t/t_var_overwidth_bad.cpp
+++ b/test_regress/t/t_var_overwidth_bad.cpp
@@ -19,7 +19,7 @@ double main_time;
 
 double sc_time_stamp() { return main_time; }
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     Verilated::debug(0);
 
     VM_PREFIX* topp = new VM_PREFIX{""};  // Note null name - we're flattening it out
diff --git a/test_regress/t/t_vpi_cb_iter.cpp b/test_regress/t/t_vpi_cb_iter.cpp
index 544e1bc62..295b95e4d 100644
--- a/test_regress/t/t_vpi_cb_iter.cpp
+++ b/test_regress/t/t_vpi_cb_iter.cpp
@@ -143,7 +143,7 @@ static void register_filler_cb() {
 
 double sc_time_stamp() { return main_time; }
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     uint64_t sim_time = 100;
diff --git a/test_regress/t/t_vpi_cbs_called.cpp b/test_regress/t/t_vpi_cbs_called.cpp
index a2371716a..16dac6df9 100644
--- a/test_regress/t/t_vpi_cbs_called.cpp
+++ b/test_regress/t/t_vpi_cbs_called.cpp
@@ -245,7 +245,7 @@ static int register_test_callback() {
     return 0;
 }
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     uint64_t sim_time = 100;
diff --git a/test_regress/t/t_vpi_get.cpp b/test_regress/t/t_vpi_get.cpp
index 898664841..6d28d1d76 100644
--- a/test_regress/t/t_vpi_get.cpp
+++ b/test_regress/t/t_vpi_get.cpp
@@ -239,7 +239,7 @@ void vpi_compat_bootstrap(void) {
 void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 
 #else
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     uint64_t sim_time = 1100;
diff --git a/test_regress/t/t_vpi_memory.cpp b/test_regress/t/t_vpi_memory.cpp
index 64122cc24..63562b2f2 100644
--- a/test_regress/t/t_vpi_memory.cpp
+++ b/test_regress/t/t_vpi_memory.cpp
@@ -250,7 +250,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 
 #else
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     uint64_t sim_time = 1100;
diff --git a/test_regress/t/t_vpi_module.cpp b/test_regress/t/t_vpi_module.cpp
index 1c2de048c..14ba4236f 100644
--- a/test_regress/t/t_vpi_module.cpp
+++ b/test_regress/t/t_vpi_module.cpp
@@ -171,7 +171,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 
 #else
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     uint64_t sim_time = 1100;
diff --git a/test_regress/t/t_vpi_param.cpp b/test_regress/t/t_vpi_param.cpp
index dcc4a7fb9..46b7cad4c 100644
--- a/test_regress/t/t_vpi_param.cpp
+++ b/test_regress/t/t_vpi_param.cpp
@@ -239,7 +239,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 
 #else
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     uint64_t sim_time = 1100;
diff --git a/test_regress/t/t_vpi_time_cb.cpp b/test_regress/t/t_vpi_time_cb.cpp
index 0665e6a10..d41fddc30 100644
--- a/test_regress/t/t_vpi_time_cb.cpp
+++ b/test_regress/t/t_vpi_time_cb.cpp
@@ -24,7 +24,7 @@
 
 //======================================================================
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     uint64_t sim_time = 1100;
diff --git a/test_regress/t/t_vpi_unimpl.cpp b/test_regress/t/t_vpi_unimpl.cpp
index e91515a6e..f3797f9eb 100644
--- a/test_regress/t/t_vpi_unimpl.cpp
+++ b/test_regress/t/t_vpi_unimpl.cpp
@@ -183,7 +183,7 @@ extern "C" int mon_check() {
 
 //======================================================================
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     uint64_t sim_time = 1100;
diff --git a/test_regress/t/t_vpi_var.cpp b/test_regress/t/t_vpi_var.cpp
index 1c5c76f50..a75095d5c 100644
--- a/test_regress/t/t_vpi_var.cpp
+++ b/test_regress/t/t_vpi_var.cpp
@@ -693,7 +693,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 #else
 
 double sc_time_stamp() { return main_time; }
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     uint64_t sim_time = 1100;
diff --git a/test_regress/t/t_vpi_zero_time_cb.cpp b/test_regress/t/t_vpi_zero_time_cb.cpp
index cd35de936..b5c74feb5 100644
--- a/test_regress/t/t_vpi_zero_time_cb.cpp
+++ b/test_regress/t/t_vpi_zero_time_cb.cpp
@@ -105,7 +105,7 @@ void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0};
 
 #else
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
 
     uint64_t sim_time = 1100;
diff --git a/test_regress/t/t_wrapper_context.cpp b/test_regress/t/t_wrapper_context.cpp
index c712cd603..267932a21 100644
--- a/test_regress/t/t_wrapper_context.cpp
+++ b/test_regress/t/t_wrapper_context.cpp
@@ -88,7 +88,7 @@ void sim(VM_PREFIX* topp) {
     contextp->coveragep()->write(filename.c_str());
 }
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     // Create contexts
     std::unique_ptr<VerilatedContext> context0p{new VerilatedContext};
     std::unique_ptr<VerilatedContext> context1p{new VerilatedContext};
diff --git a/test_regress/t/t_wrapper_del_context_bad.cpp b/test_regress/t/t_wrapper_del_context_bad.cpp
index 28f80eee4..b825a5a4b 100644
--- a/test_regress/t/t_wrapper_del_context_bad.cpp
+++ b/test_regress/t/t_wrapper_del_context_bad.cpp
@@ -9,7 +9,7 @@
 
 #include VM_PREFIX_INCLUDE
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     // Create contexts
     VerilatedContext* contextp{new VerilatedContext};
 
diff --git a/test_regress/t/t_wrapper_legacy.cpp b/test_regress/t/t_wrapper_legacy.cpp
index a2a5ac518..d14d72ce3 100644
--- a/test_regress/t/t_wrapper_legacy.cpp
+++ b/test_regress/t/t_wrapper_legacy.cpp
@@ -29,7 +29,7 @@ vluint64_t vl_time_stamp64() { return main_time; }
 double sc_time_stamp() { return main_time; }
 #endif
 
-int main(int argc, char** argv, char** env) {
+int main(int argc, char** argv) {
     // Test that the old non-context Verilated:: calls all work
     // (This test should never get updated to use context)
 

From 833780fac166174ebc324b0a0ee5fff41d6c6c93 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 27 Nov 2022 05:52:40 -0500
Subject: [PATCH 092/156] Internal: cppcheck fixes. No functional change
 intended.

---
 Makefile.in                | 50 ++++++++++++++++++++++---------
 include/verilated.cpp      | 16 ++++++----
 include/verilated_funcs.h  |  4 +++
 include/verilated_imp.h    |  2 +-
 src/V3Ast.cpp              |  1 +
 src/V3AstNodeExpr.h        |  8 +++--
 src/V3AstNodes.cpp         |  2 ++
 src/V3Case.cpp             |  6 ++--
 src/V3Cdc.cpp              |  3 +-
 src/V3Dfg.h                |  5 ++--
 src/V3DfgDecomposition.cpp |  5 ++--
 src/V3DfgPasses.cpp        |  2 +-
 src/V3EmitCSyms.cpp        | 10 +++----
 src/V3EmitV.cpp            |  9 ++----
 src/V3Error.cpp            |  1 +
 src/V3File.cpp             | 16 ++++------
 src/V3File.h               |  9 +++---
 src/V3FileLine.cpp         |  1 +
 src/V3Graph.cpp            |  3 +-
 src/V3Graph.h              |  2 +-
 src/V3LinkCells.cpp        |  4 +--
 src/V3LinkDot.cpp          |  2 +-
 src/V3LinkLevel.cpp        |  6 ++--
 src/V3MergeCond.cpp        |  4 +++
 src/V3Options.cpp          | 18 ++++--------
 src/V3Os.cpp               |  1 +
 src/V3Param.cpp            |  2 ++
 src/V3ParseImp.h           |  2 +-
 src/V3ParseSym.h           |  1 +
 src/V3PreLex.h             |  2 +-
 src/V3ProtectLib.cpp       |  1 +
 src/V3Sched.cpp            | 16 +++++-----
 src/V3SchedTiming.cpp      |  3 +-
 src/V3SenExprBuilder.h     |  2 +-
 src/V3Simulate.h           |  2 +-
 src/V3SplitVar.cpp         |  1 +
 src/V3StatsReport.cpp      |  5 ++--
 src/V3TSP.cpp              |  6 ++--
 src/astgen                 |  3 +-
 src/cppcheck_filtered      | 60 +++++++++++++++++++++++++-------------
 40 files changed, 175 insertions(+), 121 deletions(-)

diff --git a/Makefile.in b/Makefile.in
index 63d040be4..cebc67a91 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -302,34 +302,56 @@ install-all: installbin installman installdata install-msg
 install-here: installman info
 
 # Use --xml flag to see the cppcheck code to use for suppression
-CPPCHECK_CPP = $(wildcard \
-	$(srcdir)/examples/*/*.cpp \
-	$(srcdir)/include/*.cpp \
-	$(srcdir)/src/*.cpp )
-CPPCHECK_H = $(wildcard \
+CPPCHECK1_CPP = $(wildcard $(srcdir)/include/*.cpp)
+CPPCHECK2_CPP = $(wildcard $(srcdir)/examples/*/*.cpp)
+CPPCHECK3_CPP = $(wildcard $(srcdir)/src/Vlc*.cpp)
+CPPCHECK4_CPP = $(wildcard $(srcdir)/src/V3[A-D]*.cpp $(srcdir)/src/Verilator*.cpp)
+CPPCHECK5_CPP = $(wildcard $(srcdir)/src/V3[E-I]*.cpp)
+CPPCHECK6_CPP = $(wildcard $(srcdir)/src/V3[P-Z]*.cpp)
+CPPCHECK7_CPP = $(wildcard $(srcdir)/src/V3[L-R]*.cpp)
+CPPCHECK8_CPP = $(wildcard $(srcdir)/src/V3[S-Z]*.cpp)
+CHECK_CPP = $(CPPCHECK1_CPP) $(CPPCHECK2_CPP) $(CPPCHECK3_CPP) $(CPPCHECK4_CPP) \
+	$(CPPCHECK5_CPP) $(CPPCHECK6_CPP) $(CPPCHECK7_CPP) $(CPPCHECK8_CPP)
+CHECK_H = $(wildcard \
 	$(srcdir)/include/*.h \
 	$(srcdir)/src/*.h )
-CPPCHECK_YL = $(wildcard \
+CHECK_YL = $(wildcard \
 	$(srcdir)/src/*.y \
 	$(srcdir)/src/*.l )
 CPPCHECK = src/cppcheck_filtered cppcheck
 CPPCHECK_FLAGS = --enable=all --inline-suppr \
-	--suppress=unusedScopedObject --suppress=cstyleCast --suppress=useInitializationList \
-	--suppress=nullPointerRedundantCheck
+	--suppress=cstyleCast --suppress=useInitializationList \
+	--suppress=nullPointer --suppress=nullPointerRedundantCheck --suppress=ctunullpointer \
+	--suppress=unusedFunction --suppress=unusedScopedObject \
+	--suppress=useStlAlgorithm
 CPPCHECK_FLAGS += --xml
-CPPCHECK_DEP = $(subst .cpp,.cppcheck,$(CPPCHECK_CPP))
+CPPCHECK_DEP = $(subst .cpp,.cppcheck,$(CHECK_CPP))
 CPPCHECK_INC = -I$(srcdir)/include -I$(srcdir)/src/obj_dbg -I$(srcdir)/src
 
-cppcheck: $(CPPCHECK_DEP)
-%.cppcheck: %.cpp
-	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $<
+cppcheck: cppcheck-1 cppcheck-2 cppcheck-3 cppcheck-4 cppcheck-5 cppcheck-6 cppcheck-7 cppcheck-8
+cppcheck-1:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK1_CPP)
+cppcheck-2:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK2_CPP)
+cppcheck-3:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK3_CPP)
+cppcheck-4:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK4_CPP)
+cppcheck-5:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK5_CPP)
+cppcheck-6:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK6_CPP)
+cppcheck-7:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK7_CPP)
+cppcheck-8:
+	$(CPPCHECK) $(CPPCHECK_FLAGS) -DVL_DEBUG=1 -DVL_CPPCHECK=1 $(CPPCHECK_INC) $(CPPCHECK8_CPP)
 
 CLANGTIDY = clang-tidy
 CLANGTIDY_FLAGS = -config='' \
 	-header-filter='.*' \
 	-checks='-fuchsia-*,-cppcoreguidelines-avoid-c-arrays,-cppcoreguidelines-init-variables,-cppcoreguidelines-avoid-goto,-modernize-avoid-c-arrays,-readability-magic-numbers,-readability-simplify-boolean-expr,-cppcoreguidelines-macro-usage' \
 
-CLANGTIDY_DEP = $(subst .cpp,.cpp.tidy,$(CPPCHECK_CPP))
+CLANGTIDY_DEP = $(subst .cpp,.cpp.tidy,$(CHECK_CPP))
 CLANGTIDY_DEFS = -DVL_DEBUG=1 -DVL_CPPCHECK=1
 
 clang-tidy: $(CLANGTIDY_DEP)
@@ -350,7 +372,7 @@ format: clang-format yapf format-pl-exec
 
 CLANGFORMAT = clang-format-14
 CLANGFORMAT_FLAGS = -i
-CLANGFORMAT_FILES = $(CPPCHECK_CPP) $(CPPCHECK_H) $(CPPCHECK_YL) test_regress/t/*.c* test_regress/t/*.h
+CLANGFORMAT_FILES = $(CHECK_CPP) $(CHECK_H) $(CHECK_YL) test_regress/t/*.c* test_regress/t/*.h
 
 clang-format:
 	@$(CLANGFORMAT) --version | egrep 14.0 > /dev/null \
diff --git a/include/verilated.cpp b/include/verilated.cpp
index ec82b6a16..25392fc72 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -491,11 +491,11 @@ WDataOutP VL_POW_WWW(int obits, int, int rbits, WDataOutP owp, const WDataInP lw
     // obits==lbits, rbits can be different
     owp[0] = 1;
     for (int i = 1; i < VL_WORDS_I(obits); i++) owp[i] = 0;
-    // cppcheck-suppress variableScope
+    // cppcheck-has-bug-suppress variableScope
     VlWide<VL_MULS_MAX_WORDS> powstore;  // Fixed size, as MSVC++ doesn't allow [words] here
     VlWide<VL_MULS_MAX_WORDS> lastpowstore;  // Fixed size, as MSVC++ doesn't allow [words] here
     VlWide<VL_MULS_MAX_WORDS> lastoutstore;  // Fixed size, as MSVC++ doesn't allow [words] here
-    // cppcheck-suppress variableScope
+    // cppcheck-has-bug-suppress variableScope
     VL_ASSIGN_W(obits, powstore, lwp);
     for (int bit = 0; bit < rbits; bit++) {
         if (bit > 0) {  // power = power*power
@@ -1227,7 +1227,7 @@ IData _vl_vsscanf(FILE* fp,  // If a fscanf
                     _vl_vsss_skipspace(fp, floc, fromp, fstr);
                     _vl_vsss_read_str(fp, floc, fromp, fstr, t_tmp, "+-.0123456789eE");
                     if (!t_tmp[0]) goto done;
-                    // cppcheck-suppress unusedStructMember  // It's used
+                    // cppcheck-has-bug-suppress unusedStructMember, unreadVariable
                     union {
                         double r;
                         int64_t ld;
@@ -1682,7 +1682,7 @@ IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_M
             inPct = true;
         } else if (!inPct) {  // Normal text
             prefix += *posp;
-        } else if (inPct && posp[0] == '0') {  // %0
+        } else if (*posp == '0') {  // %0
         } else {  // Format character
             switch (std::tolower(*posp)) {
             case '%':
@@ -1906,7 +1906,7 @@ VlReadMem::VlReadMem(bool hex, int bits, const std::string& filename, QData star
     if (VL_UNLIKELY(!m_fp)) {
         // We don't report the Verilog source filename as it slow to have to pass it down
         VL_WARN_MT(filename.c_str(), 0, "", "$readmem file not found");
-        // cppcheck-suppress resourceLeak  // m_fp is nullptr - bug in cppcheck
+        // cppcheck-has-bug-suppress resourceLeak  // m_fp is nullptr
         return;
     }
 }
@@ -2044,7 +2044,7 @@ VlWriteMem::VlWriteMem(bool hex, int bits, const std::string& filename, QData st
     m_fp = std::fopen(filename.c_str(), "w");
     if (VL_UNLIKELY(!m_fp)) {
         VL_FATAL_MT(filename.c_str(), 0, "", "$writemem file not found");
-        // cppcheck-suppress resourceLeak  // m_fp is nullptr - bug in cppcheck
+        // cppcheck-has-bug-suppress resourceLeak  // m_fp is nullptr
         return;
     }
 }
@@ -2227,6 +2227,7 @@ static const char* vl_time_str(int scale) VL_PURE {
 double vl_time_multiplier(int scale) VL_PURE {
     // Return timescale multipler -18 to +18
     // For speed, this does not check for illegal values
+    // cppcheck-has-bug-suppress arrayIndexOutOfBoundsCond
     if (scale < 0) {
         static const double neg10[] = {1.0,
                                        0.1,
@@ -2247,6 +2248,7 @@ double vl_time_multiplier(int scale) VL_PURE {
                                        0.0000000000000001,
                                        0.00000000000000001,
                                        0.000000000000000001};
+        // cppcheck-has-bug-suppress arrayIndexOutOfBoundsCond
         return neg10[-scale];
     } else {
         static const double pow10[] = {1.0,
@@ -2268,6 +2270,7 @@ double vl_time_multiplier(int scale) VL_PURE {
                                        10000000000000000.0,
                                        100000000000000000.0,
                                        1000000000000000000.0};
+        // cppcheck-has-bug-suppress arrayIndexOutOfBoundsCond
         return pow10[scale];
     }
 }
@@ -2754,6 +2757,7 @@ VerilatedSyms::VerilatedSyms(VerilatedContext* contextp)
     : _vm_contextp__(contextp ? contextp : Verilated::threadContextp()) {
     VerilatedContext::checkMagic(_vm_contextp__);
     Verilated::threadContextp(_vm_contextp__);
+    // cppcheck-has-bug-suppress noCopyConstructor
     __Vm_evalMsgQp = new VerilatedEvalMsgQueue;
 }
 
diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h
index 0252411aa..605580cbb 100644
--- a/include/verilated_funcs.h
+++ b/include/verilated_funcs.h
@@ -274,6 +274,7 @@ extern uint64_t vl_time_stamp64() VL_ATTR_WEAK;
 extern double sc_time_stamp() VL_ATTR_WEAK;  // Verilator 4.032 and newer
 inline uint64_t vl_time_stamp64() {
     // clang9.0.1 requires & although we really do want the weak symbol value
+    // cppcheck-suppress duplicateValueTernary
     return VL_LIKELY(&sc_time_stamp) ? static_cast<uint64_t>(sc_time_stamp()) : 0;
 }
 #  endif
@@ -593,6 +594,7 @@ static inline IData VL_REDAND_IW(int lbits, WDataInP const lwp) VL_PURE {
     EData combine = lwp[0];
     for (int i = 1; i < words - 1; ++i) combine &= lwp[i];
     combine &= ~VL_MASK_E(lbits) | lwp[words - 1];
+    // cppcheck-has-bug-suppress knownConditionTrueFalse
     return ((~combine) == 0);
 }
 
@@ -1024,12 +1026,14 @@ static inline WDataOutP VL_MULS_WWW(int lbits, WDataOutP owp, WDataInP const lwp
     if (lneg) {  // Negate lhs
         lwusp = lwstore;
         VL_NEGATE_W(words, lwstore, lwp);
+        // cppcheck-has-bug-suppress unreadVariable
         lwstore[words - 1] &= VL_MASK_E(lbits);  // Clean it
     }
     const EData rneg = VL_SIGN_E(lbits, rwp[words - 1]);
     if (rneg) {  // Negate rhs
         rwusp = rwstore;
         VL_NEGATE_W(words, rwstore, rwp);
+        // cppcheck-has-bug-suppress unreadVariable
         rwstore[words - 1] &= VL_MASK_E(lbits);  // Clean it
     }
     VL_MUL_W(words, owp, lwusp, rwusp);
diff --git a/include/verilated_imp.h b/include/verilated_imp.h
index ad6d96cac..0d6c907b7 100644
--- a/include/verilated_imp.h
+++ b/include/verilated_imp.h
@@ -362,7 +362,7 @@ public:  // But only for verilated*.cpp
 private:
     VerilatedFpList fdToFpList(IData fdi) VL_REQUIRES(m_fdMutex) {
         VerilatedFpList fp;
-        // cppcheck-suppress integeroverflow shifttoomanybitssigned
+        // cppverilator-suppress integerOverflow shiftTooManyBitsSigned
         if ((fdi & (1 << 31)) != 0) {
             // Non-MCD case
             const IData idx = fdi & VL_MASK_I(31);
diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp
index 2f8f609a1..5aa1c9292 100644
--- a/src/V3Ast.cpp
+++ b/src/V3Ast.cpp
@@ -852,6 +852,7 @@ void AstNode::iterateAndNext(VNVisitor& v) {
 #ifdef VL_DEBUG  // Otherwise too hot of a function for debug
     UASSERT_OBJ(!(nodep && !nodep->m_backp), nodep, "iterateAndNext node has no back");
 #endif
+    // cppcheck-suppress knownConditionTrueFalse
     if (nodep) ASTNODE_PREFETCH(nodep->m_nextp);
     while (nodep) {  // effectively: if (!this) return;  // Callers rely on this
         if (nodep->m_nextp) ASTNODE_PREFETCH(nodep->m_nextp->m_nextp);
diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index 464c4e5a7..77d881621 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -1464,9 +1464,11 @@ public:
     string emitC() override {
         return m_reset ? "VL_RAND_RESET_%nq(%nw, %P)"
                : seedp()
-                   ? (urandom() ? "VL_URANDOM_SEEDED_%nq%lq(%li)" : "VL_RANDOM_SEEDED_%nq%lq(%li)")
-               : isWide() ? "VL_RANDOM_%nq(%nw, %P)"  //
-                          : "VL_RANDOM_%nq()";
+                   // cppcheck-has-bug-suppress knownConditionTrueFalse
+                   ? (urandom() ? "VL_URANDOM_SEEDED_%nq%lq(%li)"  //
+                                : "VL_RANDOM_SEEDED_%nq%lq(%li)")
+                   : (isWide() ? "VL_RANDOM_%nq(%nw, %P)"  //
+                               : "VL_RANDOM_%nq()");
     }
     bool cleanOut() const override { return false; }
     bool isGateOptimizable() const override { return false; }
diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index 9ebf80b50..bb4be9ecf 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -1193,6 +1193,7 @@ AstVarScope* AstConstPool::findTable(AstInitArray* initp) {
         UASSERT_OBJ(VN_IS(valuep, Const), valuep, "Const pool table entry must be Const");
     }
     // Try to find an existing table with the same content
+    // cppcheck-has-bug-suppress unreadVariable
     const V3Hash hash = V3Hasher::uncachedHash(initp);
     const auto& er = m_tables.equal_range(hash.value());
     for (auto it = er.first; it != er.second; ++it) {
@@ -1222,6 +1223,7 @@ static bool sameInit(const AstConst* ap, const AstConst* bp) {
 
 AstVarScope* AstConstPool::findConst(AstConst* initp, bool mergeDType) {
     // Try to find an existing constant with the same value
+    // cppcheck-has-bug-suppress unreadVariable
     const V3Hash hash = initp->num().toHash();
     const auto& er = m_consts.equal_range(hash.value());
     for (auto it = er.first; it != er.second; ++it) {
diff --git a/src/V3Case.cpp b/src/V3Case.cpp
index d2cf2e666..ca9c1ab38 100644
--- a/src/V3Case.cpp
+++ b/src/V3Case.cpp
@@ -255,12 +255,14 @@ private:
             // There's no space for a IF.  We know upperValue is thus down to a specific
             // exact value, so just return the tree value
             // Note can't clone here, as we're going to check for equivalence above
-            return m_valueItem[upperValue];
+            AstNode* const foundp = m_valueItem[upperValue];
+            return foundp;
         } else {
             // Make left and right subtrees
             // cexpr[msb:lsb] == 1
             AstNode* tree0p = replaceCaseFastRecurse(cexprp, msb - 1, upperValue | 0);
-            AstNode* tree1p = replaceCaseFastRecurse(cexprp, msb - 1, upperValue | (1UL << msb));
+            AstNode* tree1p = replaceCaseFastRecurse(
+                cexprp, msb - 1, upperValue | (1UL << static_cast<uint32_t>(msb)));
 
             if (tree0p == tree1p) {
                 // Same logic on both sides, so we can just return one of 'em
diff --git a/src/V3Cdc.cpp b/src/V3Cdc.cpp
index 177689093..b1d60f438 100644
--- a/src/V3Cdc.cpp
+++ b/src/V3Cdc.cpp
@@ -558,8 +558,7 @@ private:
         }  // Fully computed
 
         std::set<AstSenTree*> senouts;  // List of all sensitivities for new signal
-        if (const CdcLogicVertex* const vvertexp = dynamic_cast<CdcLogicVertex*>(vertexp)) {
-            if (vvertexp) {}  // Unused
+        if (dynamic_cast<CdcLogicVertex*>(vertexp)) {
         } else if (const CdcVarVertex* const vvertexp = dynamic_cast<CdcVarVertex*>(vertexp)) {
             // If primary I/O, give it domain of the input
             const AstVar* const varp = vvertexp->varScp()->varp();
diff --git a/src/V3Dfg.h b/src/V3Dfg.h
index 8578a7c53..247a177b3 100644
--- a/src/V3Dfg.h
+++ b/src/V3Dfg.h
@@ -101,10 +101,10 @@ class DfgGraph final {
         DfgGraph* m_graphp;  // The referenced graph
 
     public:
-        UserDataInUse(DfgGraph* graphp)
+        explicit UserDataInUse(DfgGraph* graphp)
             : m_graphp{graphp} {}
         VL_UNCOPYABLE(UserDataInUse);
-        UserDataInUse(UserDataInUse&& that) {
+        explicit UserDataInUse(UserDataInUse&& that) {
             UASSERT(that.m_graphp, "Moving from empty");
             m_graphp = vlstd::exchange(that.m_graphp, nullptr);
         }
@@ -353,6 +353,7 @@ public:
         UDEBUGONLY(UASSERT_OBJ(userCurrent, this, "DfgVertex user data used without reserving"););
         if (m_userCnt != userCurrent) {
             m_userCnt = userCurrent;
+            // cppcheck-has-bug-suppress uninitvar
             VL_ATTR_UNUSED T* const resultp = new (storagep) T{};
             UDEBUGONLY(UASSERT_OBJ(resultp == storagep, this, "Something is odd"););
         }
diff --git a/src/V3DfgDecomposition.cpp b/src/V3DfgDecomposition.cpp
index d12e9946e..c8cc73e0d 100644
--- a/src/V3DfgDecomposition.cpp
+++ b/src/V3DfgDecomposition.cpp
@@ -89,7 +89,7 @@ class SplitIntoComponents final {
         }
     }
 
-    SplitIntoComponents(DfgGraph& dfg, std::string label)
+    SplitIntoComponents(DfgGraph& dfg, const std::string& label)
         : m_dfg{dfg}
         , m_prefix{dfg.name() + (label.empty() ? "" : "-") + label + "-component-"} {
         // Component number is stored as DfgVertex::user<size_t>()
@@ -356,6 +356,7 @@ class ExtractCyclicComponents final {
             // Unlink the source edge (source is reconnected by 'relink'
             edge.unlinkSource();
             // Apply the fixup
+            // cppcheck-has-bug-suppress constVariable
             DfgVertexVar& clone = getClone(vtx, sourceComponent);
             relink(*(clone.as<T_Vertex>()), source, idx);
         });
@@ -517,7 +518,7 @@ class ExtractCyclicComponents final {
     }
 
     // CONSTRUCTOR - entry point
-    explicit ExtractCyclicComponents(DfgGraph& dfg, std::string label)
+    explicit ExtractCyclicComponents(DfgGraph& dfg, const std::string& label)
         : m_dfg{dfg}
         , m_prefix{dfg.name() + (label.empty() ? "" : "-") + label + "-component-"} {
         // VertexState is stored as user data
diff --git a/src/V3DfgPasses.cpp b/src/V3DfgPasses.cpp
index 4e03c3870..0fc891e13 100644
--- a/src/V3DfgPasses.cpp
+++ b/src/V3DfgPasses.cpp
@@ -283,7 +283,7 @@ void V3DfgPasses::optimize(DfgGraph& dfg, V3DfgOptimizationContext& ctx) {
 
     int passNumber = 0;
 
-    const auto apply = [&](int dumpLevel, const string name, std::function<void()> pass) {
+    const auto apply = [&](int dumpLevel, const string& name, std::function<void()> pass) {
         pass();
         if (dumpDfg() >= dumpLevel) {
             const string strippedName = VString::removeWhitespace(name);
diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp
index f19410b84..86692e6d4 100644
--- a/src/V3EmitCSyms.cpp
+++ b/src/V3EmitCSyms.cpp
@@ -322,10 +322,8 @@ class EmitCSyms final : EmitCBaseVisitor {
         // UINFO(9,"scnameins sp "<<nodep->name()<<" sp "<<nodep->scopePrettySymName()
         // <<" ss"<<name<<endl);
         const int timeunit = m_modp ? m_modp->timeunit().powerOfTen() : 0;
-        if (m_scopeNames.find(name) == m_scopeNames.end()) {
-            m_scopeNames.emplace(
-                name, ScopeData(name, nodep->scopePrettySymName(), timeunit, "SCOPE_OTHER"));
-        }
+        m_scopeNames.emplace(
+            name, ScopeData(name, nodep->scopePrettySymName(), timeunit, "SCOPE_OTHER"));
         if (nodep->dpiExport()) {
             UASSERT_OBJ(m_cfuncp, nodep, "ScopeName not under DPI function");
             m_scopeFuncs.insert(std::make_pair(name + " " + m_cfuncp->name(),
@@ -984,7 +982,7 @@ void EmitCSyms::emitDpiHdr() {
     const string filename = v3Global.opt.makeDir() + "/" + topClassName() + "__Dpi.h";
     AstCFile* const cfilep = newCFile(filename, false /*slow*/, false /*source*/);
     cfilep->support(true);
-    V3OutCFile hf(filename);
+    V3OutCFile hf{filename};
     m_ofp = &hf;
 
     m_ofp->putsHeader();
@@ -1029,6 +1027,7 @@ void EmitCSyms::emitDpiHdr() {
     puts("#endif\n");
 
     ofp()->putsEndGuard();
+    m_ofp = nullptr;
 }
 
 //######################################################################
@@ -1083,6 +1082,7 @@ void EmitCSyms::emitDpiImp() {
             puts("\n");
         }
     }
+    m_ofp = nullptr;
 }
 
 //######################################################################
diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp
index bf56a4b11..5561ee89e 100644
--- a/src/V3EmitV.cpp
+++ b/src/V3EmitV.cpp
@@ -740,10 +740,7 @@ public:
 // Emit to an output file
 
 class EmitVFileVisitor final : public EmitVBaseVisitor {
-    // MEMBERS
-    V3OutFile* m_ofp;
     // METHODS
-    V3OutFile* ofp() const { return m_ofp; }
     void puts(const string& str) override { ofp()->puts(str); }
     void putbs(const string& str) override { ofp()->putbs(str); }
     void putfs(AstNode*, const string& str) override { putbs(str); }
@@ -751,9 +748,9 @@ class EmitVFileVisitor final : public EmitVBaseVisitor {
     void putsNoTracking(const string& str) override { ofp()->putsNoTracking(str); }
 
 public:
-    EmitVFileVisitor(AstNode* nodep, V3OutFile* ofp, bool trackText, bool suppressUnknown)
-        : EmitVBaseVisitor{suppressUnknown, nullptr}
-        , m_ofp{ofp} {
+    EmitVFileVisitor(AstNode* nodep, V3OutVFile* ofp, bool trackText, bool suppressUnknown)
+        : EmitVBaseVisitor{suppressUnknown, nullptr} {
+        m_ofp = ofp;
         m_trackText = trackText;
         iterate(nodep);
     }
diff --git a/src/V3Error.cpp b/src/V3Error.cpp
index 54b61132d..798c280c0 100644
--- a/src/V3Error.cpp
+++ b/src/V3Error.cpp
@@ -184,6 +184,7 @@ void V3Error::suppressThisWarning() {
 
 string V3Error::warnMore() { return string(msgPrefix().size(), ' '); }
 
+// cppcheck-has-bug-suppress constParameter
 void V3Error::v3errorEnd(std::ostringstream& sstr, const string& extra) {
 #if defined(__COVERITY__) || defined(__cppcheck__)
     if (s_errorCode == V3ErrorCode::EC_FATAL) __coverity_panic__(x);
diff --git a/src/V3File.cpp b/src/V3File.cpp
index eef75c73a..d2b24cf9a 100644
--- a/src/V3File.cpp
+++ b/src/V3File.cpp
@@ -122,20 +122,16 @@ class V3FileDependImp final {
 public:
     // ACCESSOR METHODS
     void addSrcDepend(const string& filename) {
-        if (m_filenameSet.find(filename) == m_filenameSet.end()) {
-            // cppcheck-suppress stlFindInsert  // cppcheck 1.90 bug
-            m_filenameSet.insert(filename);
+        const auto itFoundPair = m_filenameSet.insert(filename);
+        if (itFoundPair.second) {
             DependFile df{filename, false};
             df.loadStats();  // Get size now, in case changes during the run
             m_filenameList.insert(df);
         }
     }
     void addTgtDepend(const string& filename) {
-        if (m_filenameSet.find(filename) == m_filenameSet.end()) {
-            // cppcheck-suppress stlFindInsert  // cppcheck 1.90 bug
-            m_filenameSet.insert(filename);
-            m_filenameList.insert(DependFile{filename, true});
-        }
+        const auto itFoundPair = m_filenameSet.insert(filename);
+        if (itFoundPair.second) m_filenameList.insert(DependFile{filename, true});
     }
     void writeDepend(const string& filename);
     std::vector<string> getAllDeps() const;
@@ -424,7 +420,7 @@ private:
             }
         }
     }
-    // cppcheck-suppress unusedFunction unusedPrivateFunction
+    // cppverilator-suppress unusedFunction unusedPrivateFunction
     string readFilterLine() {
         // Slow, but we don't need it much
         UINFO(9, "readFilterLine\n");
@@ -446,7 +442,7 @@ private:
         UINFO(6, "filter-line-in: " << line);
         return line;
     }
-    // cppcheck-suppress unusedFunction unusedPrivateFunction
+    // cppverilator-suppress unusedFunction unusedPrivateFunction
     void writeFilter(const string& out) {
         if (debug() >= 6) {
             UINFO(6, "filter-out: " << out);
diff --git a/src/V3File.h b/src/V3File.h
index eb6673e38..db1104ae2 100644
--- a/src/V3File.h
+++ b/src/V3File.h
@@ -242,8 +242,9 @@ class V3OutCFile VL_NOT_FINAL : public V3OutFile {
     int m_guard = false;  // Created header guard
     int m_private;  // 1 = Most recently emitted private:, 2 = public:
 public:
-    explicit V3OutCFile(const string& filename)
-        : V3OutFile{filename, V3OutFormatter::LA_C} {
+    explicit V3OutCFile(const string& filename,
+                        V3OutFormatter::Language lang = V3OutFormatter::LA_C)
+        : V3OutFile{filename, lang} {
         resetPrivate();
     }
     ~V3OutCFile() override = default;
@@ -279,10 +280,10 @@ public:
     }
 };
 
-class V3OutVFile final : public V3OutFile {
+class V3OutVFile final : public V3OutCFile {
 public:
     explicit V3OutVFile(const string& filename)
-        : V3OutFile{filename, V3OutFormatter::LA_VERILOG} {}
+        : V3OutCFile{filename, V3OutFormatter::LA_VERILOG} {}
     ~V3OutVFile() override = default;
     virtual void putsHeader() { puts("// Verilated -*- Verilog -*-\n"); }
 };
diff --git a/src/V3FileLine.cpp b/src/V3FileLine.cpp
index 8a83b110e..4ded807ee 100644
--- a/src/V3FileLine.cpp
+++ b/src/V3FileLine.cpp
@@ -379,6 +379,7 @@ bool FileLine::warnIsOff(V3ErrorCode code) const VL_MT_SAFE {
     return false;
 }
 
+// cppverilator-suppress constParameter
 void FileLine::v3errorEnd(std::ostringstream& sstr, const string& extra) {
     std::ostringstream nsstr;
     if (lastLineno()) nsstr << this;
diff --git a/src/V3Graph.cpp b/src/V3Graph.cpp
index ca3a4ed91..751b2ab36 100644
--- a/src/V3Graph.cpp
+++ b/src/V3Graph.cpp
@@ -128,6 +128,7 @@ V3GraphEdge* V3GraphVertex::findConnectingEdgep(GraphWay way, const V3GraphVerte
     return nullptr;
 }
 
+// cppcheck-has-bug-suppress constParameter
 void V3GraphVertex::v3errorEnd(std::ostringstream& str) const {
     std::ostringstream nsstr;
     nsstr << str.str();
@@ -300,7 +301,7 @@ void V3Graph::dump(std::ostream& os) {
     }
 }
 
-void V3Graph::dumpEdge(std::ostream& os, V3GraphVertex* vertexp, V3GraphEdge* edgep) {
+void V3Graph::dumpEdge(std::ostream& os, const V3GraphVertex* vertexp, const V3GraphEdge* edgep) {
     if (edgep->weight() && (edgep->fromp() == vertexp || edgep->top() == vertexp)) {
         os << "\t\t";
         if (edgep->fromp() == vertexp) os << "-> " << edgep->top()->name();
diff --git a/src/V3Graph.h b/src/V3Graph.h
index ee7f7a2ef..e54e5d46c 100644
--- a/src/V3Graph.h
+++ b/src/V3Graph.h
@@ -88,7 +88,7 @@ protected:
     friend class GraphAcyc;
     // METHODS
     double orderDFSIterate(V3GraphVertex* vertexp);
-    void dumpEdge(std::ostream& os, V3GraphVertex* vertexp, V3GraphEdge* edgep);
+    void dumpEdge(std::ostream& os, const V3GraphVertex* vertexp, const V3GraphEdge* edgep);
     void verticesUnlink() { m_vertices.reset(); }
     // ACCESSORS
 
diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp
index e5e2cb1f9..e9cc52c1d 100644
--- a/src/V3LinkCells.cpp
+++ b/src/V3LinkCells.cpp
@@ -197,8 +197,8 @@ private:
                 && !nodep->internal()) {
                 // We only complain once per file, otherwise library-like files
                 // have a huge mess of warnings
-                if (m_declfnWarned.find(nodep->fileline()->filename()) == m_declfnWarned.end()) {
-                    m_declfnWarned.insert(nodep->fileline()->filename());
+                const auto itFoundPair = m_declfnWarned.insert(nodep->fileline()->filename());
+                if (itFoundPair.second) {
                     nodep->v3warn(DECLFILENAME, "Filename '"
                                                     << nodep->fileline()->filebasenameNoExt()
                                                     << "' does not match " << nodep->typeName()
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 7c6c601eb..b28ebc5b0 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1140,7 +1140,7 @@ class LinkDotFindVisitor final : public VNVisitor {
             bool ins = false;
             if (!foundp) {
                 ins = true;
-            } else if (!findvarp && foundp && m_curSymp->findIdFlat(nodep->name())) {
+            } else if (!findvarp && m_curSymp->findIdFlat(nodep->name())) {
                 nodep->v3error("Unsupported in C: Variable has same name as "
                                << LinkDotState::nodeTextType(foundp->nodep()) << ": "
                                << nodep->prettyNameQ());
diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp
index 171349790..c3780e434 100644
--- a/src/V3LinkLevel.cpp
+++ b/src/V3LinkLevel.cpp
@@ -267,10 +267,8 @@ void V3LinkLevel::wrapTopCell(AstNetlist* rootp) {
                     varp->protect(false);
                     newmodp->addStmtsp(varp);
                     varp->sigPublic(true);  // User needs to be able to get to it...
-                    if (oldvarp->isIO()) {
-                        oldvarp->primaryIO(false);
-                        varp->primaryIO(true);
-                    }
+                    oldvarp->primaryIO(false);
+                    varp->primaryIO(true);
                     if (varp->direction().isRefOrConstRef()) {
                         varp->v3warn(E_UNSUPPORTED,
                                      "Unsupported: ref/const ref as primary input/output: "
diff --git a/src/V3MergeCond.cpp b/src/V3MergeCond.cpp
index 31760c61a..04e3287fa 100644
--- a/src/V3MergeCond.cpp
+++ b/src/V3MergeCond.cpp
@@ -491,7 +491,10 @@ private:
 
             // Close pending merge, if there is one at the end of the whole sub-tree list
             if (m_mgFirstp) mergeEnd();
+            m_stmtPropertiesp = nullptr;
         } while (!m_workQueuep->empty());
+
+        m_workQueuep = nullptr;
     }
 
     // Skip past AstArraySel and AstWordSel with const index
@@ -716,6 +719,7 @@ private:
             iterateAndNextNull(recursivep->elsesp());
             // Close a pending merge to ensure merge state is
             // reset as expected at the end of this function
+            // cppcheck-has-bug-suppress knownConditionTrueFalse
             if (m_mgFirstp) mergeEnd();
         }
     }
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index 2e0368743..a345cd810 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -75,9 +75,9 @@ public:
 
     // ACCESSOR METHODS
     void addIncDirUser(const string& incdir) {
-        if (m_incDirUserSet.find(incdir) == m_incDirUserSet.end()) {
+        const auto itFoundPair = m_incDirUserSet.insert(incdir);
+        if (itFoundPair.second) {
             // cppcheck-suppress stlFindInsert  // cppcheck 1.90 bug
-            m_incDirUserSet.insert(incdir);
             m_incDirUsers.push_back(incdir);
             m_incDirFallbacks.remove(incdir);  // User has priority over Fallback
             m_incDirFallbackSet.erase(incdir);  // User has priority over Fallback
@@ -86,11 +86,8 @@ public:
     void addIncDirFallback(const string& incdir) {
         if (m_incDirUserSet.find(incdir)
             == m_incDirUserSet.end()) {  // User has priority over Fallback
-            if (m_incDirFallbackSet.find(incdir) == m_incDirFallbackSet.end()) {
-                // cppcheck-suppress stlFindInsert  // cppcheck 1.90 bug
-                m_incDirFallbackSet.insert(incdir);
-                m_incDirFallbacks.push_back(incdir);
-            }
+            const auto itFoundPair = m_incDirFallbackSet.insert(incdir);
+            if (itFoundPair.second) m_incDirFallbacks.push_back(incdir);
         }
     }
     void addLangExt(const string& langext, const V3LangCode& lc) {
@@ -100,11 +97,8 @@ public:
     }
 
     void addLibExtV(const string& libext) {
-        if (m_libExtVSet.find(libext) == m_libExtVSet.end()) {
-            // cppcheck-suppress stlFindInsert  // cppcheck 1.90 bug
-            m_libExtVSet.insert(libext);
-            m_libExtVs.push_back(libext);
-        }
+        const auto itFoundPair = m_libExtVSet.insert(libext);
+        if (itFoundPair.second) m_libExtVs.push_back(libext);
     }
     V3OptionsImp() = default;
     ~V3OptionsImp() = default;
diff --git a/src/V3Os.cpp b/src/V3Os.cpp
index a0f936e4c..1bd78f583 100644
--- a/src/V3Os.cpp
+++ b/src/V3Os.cpp
@@ -155,6 +155,7 @@ string V3Os::filenameNonExt(const string& filename) {
 
 string V3Os::filenameSubstitute(const string& filename) {
     string out;
+    // cppcheck-has-bug-suppress unusedLabel
     enum : uint8_t { NONE, PAREN, CURLY } brackets = NONE;
     for (string::size_type pos = 0; pos < filename.length(); ++pos) {
         if ((filename[pos] == '$') && (pos + 1 < filename.length())) {
diff --git a/src/V3Param.cpp b/src/V3Param.cpp
index 86434f450..8ad9a5a23 100644
--- a/src/V3Param.cpp
+++ b/src/V3Param.cpp
@@ -342,8 +342,10 @@ class ParamProcessor final {
         //       particularly robust for type parameters. We should really have a type
         //       equivalence predicate function.
         const string key = paramValueKey(nodep);
+        // cppcheck-has-bug-suppress unreadVariable
         V3Hash hash = V3Hasher::uncachedHash(nodep);
         // Force hash collisions -- for testing only
+        // cppcheck-has-bug-suppress unreadVariable
         if (VL_UNLIKELY(v3Global.opt.debugCollision())) hash = V3Hash{};
         int num;
         const auto it = m_valueMap.find(hash);
diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h
index fb89516ad..de7ee0ef7 100644
--- a/src/V3ParseImp.h
+++ b/src/V3ParseImp.h
@@ -142,7 +142,7 @@ class V3ParseImp final {
     static V3ParseImp* s_parsep;  // Current THIS, bison() isn't class based
     FileLine* m_lexFileline = nullptr;  // Filename/linenumber currently active for lexing
 
-    FileLine* m_bisonLastFileline;  // Filename/linenumber of last token
+    FileLine* m_bisonLastFileline = nullptr;  // Filename/linenumber of last token
 
     bool m_inLibrary = false;  // Currently reading a library vs. regular file
     int m_lexKwdDepth = 0;  // Inside a `begin_keywords
diff --git a/src/V3ParseSym.h b/src/V3ParseSym.h
index b9e0d26e3..4eae7b6a2 100644
--- a/src/V3ParseSym.h
+++ b/src/V3ParseSym.h
@@ -87,6 +87,7 @@ public:
     void reinsert(AstNode* nodep, VSymEnt* parentp = nullptr) {
         reinsert(nodep, parentp, nodep->name());
     }
+    // cppcheck-suppress passedByValue
     void reinsert(AstNode* nodep, VSymEnt* parentp, string name) {
         if (!parentp) parentp = symCurrentp();
         if (name == "") {  // New name with space in name so can't collide with users
diff --git a/src/V3PreLex.h b/src/V3PreLex.h
index 3a001153f..721075495 100644
--- a/src/V3PreLex.h
+++ b/src/V3PreLex.h
@@ -176,7 +176,7 @@ public:  // Used only by V3PreLex.cpp and V3PreProc.cpp
     int m_enterExit = 0;  // For VL_LINE, the enter/exit level
     int m_protLength = 0;  // unencoded length for BASE64
     int m_protBytes = 0;  // decoded length for BASE64
-    Enctype m_encType;  // encoding type for `pragma protect
+    Enctype m_encType{};  // encoding type for `pragma protect
 
     // CONSTRUCTORS
     V3PreLex(V3PreProcImp* preimpp, FileLine* filelinep)
diff --git a/src/V3ProtectLib.cpp b/src/V3ProtectLib.cpp
index 7d04a1fc8..aefb9fa35 100644
--- a/src/V3ProtectLib.cpp
+++ b/src/V3ProtectLib.cpp
@@ -90,6 +90,7 @@ private:
 
         iterateChildren(nodep);
 
+        // cppcheck-has-bug-suppress unreadVariable
         const V3Hash hash = V3Hasher::uncachedHash(m_cfilep);
         m_hashValuep->addText(fl, cvtToStr(hash.value()) + ";\n");
         m_cHashValuep->addText(fl, cvtToStr(hash.value()) + "U;\n");
diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp
index 52b7adce5..84fc939b0 100644
--- a/src/V3Sched.cpp
+++ b/src/V3Sched.cpp
@@ -493,12 +493,12 @@ const TriggerKit createTriggers(AstNetlist* netlistp, AstCFunc* const initFuncp,
 
     // Add the initialization statements
     if (initialTrigsp) {
-        AstVarScope* const vscp = scopeTopp->createTemp("__V" + name + "DidInit", 1);
-        AstVarRef* const condp = new AstVarRef{flp, vscp, VAccess::READ};
+        AstVarScope* const tempVscp = scopeTopp->createTemp("__V" + name + "DidInit", 1);
+        AstVarRef* const condp = new AstVarRef{flp, tempVscp, VAccess::READ};
         AstIf* const ifp = new AstIf{flp, new AstNot{flp, condp}};
         funcp->addStmtsp(ifp);
         ifp->branchPred(VBranchPred::BP_UNLIKELY);
-        ifp->addThensp(setVar(vscp, 1));
+        ifp->addThensp(setVar(tempVscp, 1));
         ifp->addThensp(initialTrigsp);
     }
 
@@ -574,10 +574,10 @@ std::pair<AstVarScope*, AstNodeStmt*> makeEvalLoop(AstNetlist* netlistp, const s
             // If we exceeded the iteration limit, die
             {
                 const uint32_t limit = v3Global.opt.convergeLimit();
-                AstVarRef* const refp = new AstVarRef{flp, counterp, VAccess::READ};
+                AstVarRef* const counterRefp = new AstVarRef{flp, counterp, VAccess::READ};
                 AstConst* const constp = new AstConst{flp, AstConst::DTyped{}, counterp->dtypep()};
                 constp->num().setLong(limit);
-                AstNodeExpr* const condp = new AstGt{flp, refp, constp};
+                AstNodeExpr* const condp = new AstGt{flp, counterRefp, constp};
                 AstIf* const failp = new AstIf{flp, condp};
                 failp->branchPred(VBranchPred::BP_UNLIKELY);
                 ifp->addThensp(failp);
@@ -588,9 +588,9 @@ std::pair<AstVarScope*, AstNodeStmt*> makeEvalLoop(AstNetlist* netlistp, const s
                 const string& line = cvtToStr(locp->lineno());
                 const auto add = [&](const string& text) { blockp->addText(flp, text, true); };
                 add("#ifdef VL_DEBUG\n");
-                AstCCall* const callp = new AstCCall{flp, trigDumpp};
-                callp->dtypeSetVoid();
-                blockp->addNodesp(callp->makeStmt());
+                AstCCall* const newcallp = new AstCCall{flp, trigDumpp};
+                newcallp->dtypeSetVoid();
+                blockp->addNodesp(newcallp->makeStmt());
                 add("#endif\n");
                 add("VL_FATAL_MT(\"" + file + "\", " + line + ", \"\", ");
                 add("\"" + name + " region did not converge.\");\n");
diff --git a/src/V3SchedTiming.cpp b/src/V3SchedTiming.cpp
index 4bf3de0c7..897877253 100644
--- a/src/V3SchedTiming.cpp
+++ b/src/V3SchedTiming.cpp
@@ -296,7 +296,6 @@ void transformForks(AstNetlist* const netlistp) {
                 AstVarScope* const vscp = refp->varScopep();
                 if (!vscp->user2p()) {
                     // Clone the var to the new function
-                    AstVar* const varp = refp->varp();
                     AstVar* const newvarp
                         = new AstVar{varp->fileline(), VVarType::BLOCKTEMP, varp->name(), varp};
                     newvarp->funcLocal(true);
@@ -308,7 +307,7 @@ void transformForks(AstNetlist* const netlistp) {
                     vscp->user2p(newvscp);
                     callp->addArgsp(new AstVarRef{refp->fileline(), vscp, VAccess::READ});
                 }
-                auto* const newvscp = VN_AS(vscp->user2p(), VarScope);
+                AstVarScope* const newvscp = VN_AS(vscp->user2p(), VarScope);
                 refp->varScopep(newvscp);
                 refp->varp(newvscp->varp());
             });
diff --git a/src/V3SenExprBuilder.h b/src/V3SenExprBuilder.h
index 2634bbeec..f4294368f 100644
--- a/src/V3SenExprBuilder.h
+++ b/src/V3SenExprBuilder.h
@@ -244,7 +244,7 @@ public:
     }
 
     // CONSTRUCTOR
-    SenExprBuilder(AstScope* scopep)
+    explicit SenExprBuilder(AstScope* scopep)
         : m_scopep{scopep} {}
 };
 
diff --git a/src/V3Simulate.h b/src/V3Simulate.h
index 1fd4a64d4..8b0854c90 100644
--- a/src/V3Simulate.h
+++ b/src/V3Simulate.h
@@ -382,7 +382,7 @@ private:
     int unrollCount() const {
         return m_params ? v3Global.opt.unrollCount() * 16 : v3Global.opt.unrollCount();
     }
-    bool jumpingOver(AstNode* nodep) const {
+    bool jumpingOver(const AstNode* nodep) const {
         // True to jump over this node - all visitors must call this up front
         return (m_jumpp && m_jumpp->labelp() != nodep);
     }
diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp
index dfece3f3c..bc6786ba6 100644
--- a/src/V3SplitVar.cpp
+++ b/src/V3SplitVar.cpp
@@ -675,6 +675,7 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
             setContextAndIterate(assignp, nodes[1]);
         }
     }
+    // cppcheck-has-bug-suppress constParameter
     size_t collapse(UnpackRefMap& refs) {
         size_t numSplit = 0;
         for (const auto& pair : refs) {
diff --git a/src/V3StatsReport.cpp b/src/V3StatsReport.cpp
index 0135bd547..daab941dd 100644
--- a/src/V3StatsReport.cpp
+++ b/src/V3StatsReport.cpp
@@ -121,8 +121,9 @@ class StatsReport final {
             const V3Statistic* repp = &(*it);
             if (repp->stage() != "*" && repp->printit()) {
                 if (maxWidth < repp->name().length()) maxWidth = repp->name().length();
-                if (stageInt.find(repp->stage()) == stageInt.end()) {
-                    stageInt.emplace(repp->stage(), stage++);
+                const auto itFoundPair = stageInt.emplace(repp->stage(), stage);
+                if (itFoundPair.second) {
+                    ++stage;
                     stages.push_back(repp->stage());
                 }
                 byName.emplace(repp->name(), repp);
diff --git a/src/V3TSP.cpp b/src/V3TSP.cpp
index 522856da2..6690fb2ba 100644
--- a/src/V3TSP.cpp
+++ b/src/V3TSP.cpp
@@ -486,10 +486,8 @@ void V3TSP::tspSort(const V3TSP::StateVec& states, V3TSP::StateVec* resultp) {
         for (V3TSP::StateVec::iterator it = prelim_result.begin(); it != prelim_result.end();
              ++it) {
             const TspStateBase* const elemp = *it;
-            if (seen.find(elemp) == seen.end()) {
-                seen.insert(elemp);
-                resultp->push_back(elemp);
-            }
+            const auto itFoundPair = seen.insert(elemp);
+            if (itFoundPair.second) resultp->push_back(elemp);
         }
     }
 
diff --git a/src/astgen b/src/astgen
index 6d656117f..f79ddc6ab 100755
--- a/src/astgen
+++ b/src/astgen
@@ -1055,7 +1055,8 @@ def write_ast_op_checks(filename):
                                     backp = tailp = opp;
                                     opp = {next};
                                 }} while (opp);
-                                if (headp && tailp) {{}}  // Prevent unused
+                                // cppcheck-suppress knownConditionTrueFalse
+                                if (false && headp && tailp) {{}}  // Prevent unused
                                 UASSERT_OBJ(headp->m_headtailp == tailp, headp, "Tail in headtailp is inconsistent");
                                 UASSERT_OBJ(tailp->m_headtailp == headp, tailp, "Head in headtailp is inconsistent");
                             }}
diff --git a/src/cppcheck_filtered b/src/cppcheck_filtered
index 2b96dc070..ce991abe3 100755
--- a/src/cppcheck_filtered
+++ b/src/cppcheck_filtered
@@ -20,7 +20,6 @@ def process(cppcheck_args):
     if Args.debug:
         print("\t" + cmd)
     fh = os.popen(cmd)
-    uniq = {}
     errs = False
     last_error = ""
     for line in fh:
@@ -30,27 +29,23 @@ def process(cppcheck_args):
         line = re.sub(r'^\s+', '', line)
         # Sometimes tacked at end-of-line
         line = re.sub(r'Checking usage of global functions\.+', '', line)
-        # General gunk
-        if line in uniq:
-            continue
-        uniq[line] = 1
+        line = re.sub(r' file0="[^"]+"', r'', line)
 
         if re.search(r'^<\?xml version', line):
             continue
         if re.search(r'^<cppcheck', line):
             continue
-        if re.search(r'^<results', line):
-            continue
-        if re.search(r'^</results>', line):
-            continue
         if re.search(r'^<errors', line):
             continue
         if re.search(r'^</error>', line):
             continue
         if re.search(r'^</errors>', line):
             continue
-        # --suppress=unmatchedSuppression doesn't work
-        if re.search(r'^<error.*id="unmatchedSuppression"', line):
+        if re.search(r'^<results', line):
+            continue
+        if re.search(r'^</results>', line):
+            continue
+        if re.search(r'^<symbol>', line):
             continue
         # An earlier id line is more specific
         if re.search(r'Cppcheck cannot find all the include files', line):
@@ -64,11 +59,6 @@ def process(cppcheck_args):
         if re.search(r'^\s+$', line):
             continue
 
-        # Specific suppressions (see _suppress also)
-        # Doesn't know UINFO will use it
-        if re.search(r'id="unusedPrivateFunction" .*::debug', line):
-            continue
-
         # Output
         if re.search(r'^cppcheck --', line):
             if Args.debug:
@@ -87,7 +77,7 @@ def process(cppcheck_args):
         match = re.search(r'<location.* file="([^"]+)"\s+line="(\d+)"', line)
         if match:
             file = match.group(1)
-            linenum = match.group(2)
+            linenum = int(match.group(2))
             match = re.search(r' id="([^"]+)"', last_error)
             eid = match.group(1) if match else '?'
             if _suppress(file, linenum, eid):
@@ -95,7 +85,7 @@ def process(cppcheck_args):
             if file == "*":
                 suppress = True
             if not suppress:
-                print(file + ":" + linenum + ": " + last_error)
+                print("%s:%s: %s" % (file, linenum, last_error))
                 suppress = True
 
         if not suppress:
@@ -121,16 +111,42 @@ def _suppress(filename, linenum, eid):
     filename = re.sub(r'^\.\./(.*)', r'src/\1', filename)
 
     # Specific suppressions
+    if eid == 'asctimeCalled' and re.search(r'gtkwave/', filename):
+        return True
+    if eid == 'constParameter' and re.search(r'gtkwave/', filename):
+        return True
+    if eid == 'ctuOneDefinitionRuleViolation' and re.search(
+            r'vltstd/', filename):
+        return True
+    if eid == 'duplicateConditionalAssign' and re.search(
+            r'gtkwave/', filename):
+        return True
+    if eid == 'knownConditionTrueFalse' and re.search(r'gtkwave/', filename):
+        return True
     if eid == 'missingInclude' and re.search(r'systemc.h', filename):
         return True
     if eid == 'missingInclude' and re.search(r'svdpi.h', filename):
         return True
+    if eid == 'shiftNegativeLHS' and re.search(r'gtkwave/', filename):
+        return True
+    if eid == 'shiftTooManyBits' and re.search(r'gtkwave/', filename):
+        return True
+    if eid == 'shiftTooManyBitsSigned' and re.search(r'gtkwave/', filename):
+        return True
+    if eid == 'nullPointerArithmetic' and re.search(r'gtkwave/', filename):
+        return True
+    if eid == 'unmatchedSuppression':
+        return True
     if eid == 'unusedFunction' and re.search(r'verilated_dpi.cpp', filename):
         return True
     if eid == 'unusedFunction' and re.search(r'verilated_vpi.cpp', filename):
         return True
     if eid == 'unreachableCode' and re.search(r'V3ParseBison.c', filename):
         return True
+    if eid == 'unreadVariable' and re.search(r'gtkwave/', filename):
+        return True
+    if eid == 'uselessAssignmentPtrArg' and re.search(r'gtkwave/', filename):
+        return True
     if eid == 'variableScope' and re.search(r'fstapi.c', filename):
         return True
 
@@ -143,10 +159,12 @@ def _suppress(filename, linenum, eid):
         lineno = 0
         for line in fh:
             lineno += 1
-            if lineno + 1 == linenum:
-                match = re.search(r'cppcheck-suppress((\s+\S+)+)', line)
+            if ((lineno + 1) == linenum):
+                match = re.search(
+                    r'(cppcheck|cppcheck-has-bug|cppverilator)-suppress((\s+\S+)+)',
+                    line)
                 if match:
-                    for supid in match.group(1).split():
+                    for supid in match.group(2).split():
                         if (supid == eid or (eid in SuppressMap
                                              and supid == SuppressMap[eid])):
                             return True

From d8071819fc41e8fdb80f0719da554f60afeebda4 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 27 Nov 2022 05:59:40 -0500
Subject: [PATCH 093/156] Fix unquoted name in dtype errors.

---
 src/V3AstNodeDType.h                              | 2 +-
 test_regress/t/t_randomize_method_types_unsup.out | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h
index 2e76588bd..69b2f5bec 100644
--- a/src/V3AstNodeDType.h
+++ b/src/V3AstNodeDType.h
@@ -1073,7 +1073,7 @@ public:
     void dumpSmall(std::ostream& str) const override;
     string name() const override { return m_name; }
     string prettyDTypeName() const override {
-        return subDTypep() ? subDTypep()->name() : prettyName();
+        return subDTypep() ? prettyName(subDTypep()->name()) : prettyName();
     }
     AstBasicDType* basicp() const override VL_MT_SAFE {
         return subDTypep() ? subDTypep()->basicp() : nullptr;
diff --git a/test_regress/t/t_randomize_method_types_unsup.out b/test_regress/t/t_randomize_method_types_unsup.out
index 66d2da0d7..175d8a134 100644
--- a/test_regress/t/t_randomize_method_types_unsup.out
+++ b/test_regress/t/t_randomize_method_types_unsup.out
@@ -11,7 +11,7 @@
                                                             : ... In instance t
    14 |    rand int unpackarr[5];
       |             ^~~~~~~~~
-%Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:15:15: Unsupported: random member variables with type '__024unit::Union'
+%Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:15:15: Unsupported: random member variables with type '$unit::Union'
                                                             : ... In instance t
    15 |    rand Union uni;
       |               ^~~

From fa4270b551fd04e4deb57f186c0ff42c17156317 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 27 Nov 2022 06:17:44 -0500
Subject: [PATCH 094/156] bisonpre: Commentary

---
 src/bisonpre | 22 +++++++++++++++-------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/src/bisonpre b/src/bisonpre
index c60e3575d..48f1761ff 100755
--- a/src/bisonpre
+++ b/src/bisonpre
@@ -17,20 +17,28 @@ def process():
 
     bison_version_check()
     supports_report = Bison_Version >= 2.3
+    supports_counter_examples = Bison_Version >= 3.8
 
     clean_input(Args.input, tmp_prefix() + ".y")
 
     # Run bison
     command = (
-        Args.yacc + (" -t" if Args.debug else "") +
-        (" -d" if Args.definitions else "") +
-        (" -k" if Args.token_table else "") + (" -v" if Args.verbose else "") +
-        (" --report=itemset --report=lookahead" if
-         (Args.verbose and supports_report) else "")
+        Args.yacc  #
+        + (" -t" if Args.debug else "")  #
+        + (" -d" if Args.definitions else "")  #
+        + (" -k" if Args.token_table else "")  #
+        + (" -v" if Args.verbose else "")  #
+        + (" --report=itemset --report=lookahead" if
+           (Args.verbose and supports_report) else "")
+        # Useful but slow:
+        # (" -Wcounterexamples" if
+        # (Args.verbose and supports_counter_examples) else "")
+        #
         # -p required for GLR parsers; they write to -p basename, not -o
         + ((" -p " + Args.name_prefix) if Args.name_prefix else "") + " -b " +
-        tmp_prefix() + " -o " + tmp_prefix() + ".c" + " " + tmp_prefix() +
-        ".y")
+        tmp_prefix()  #
+        + " -o " + tmp_prefix() + ".c"  #
+        + " " + tmp_prefix() + ".y")
 
     print("  " + command)
     status = subprocess.call(command, shell=True)

From 5f583b068070d0b5b6c434c41c1f59e9d6464cd2 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 27 Nov 2022 06:27:51 -0500
Subject: [PATCH 095/156] Fix clang warning from previous commits.

---
 src/V3Dfg.h  | 8 +++++---
 src/V3File.h | 2 +-
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/V3Dfg.h b/src/V3Dfg.h
index 247a177b3..5d86805f8 100644
--- a/src/V3Dfg.h
+++ b/src/V3Dfg.h
@@ -101,13 +101,15 @@ class DfgGraph final {
         DfgGraph* m_graphp;  // The referenced graph
 
     public:
-        explicit UserDataInUse(DfgGraph* graphp)
+        // cppcheck-suppress noExplicitConstructor
+        UserDataInUse(DfgGraph* graphp)
             : m_graphp{graphp} {}
-        VL_UNCOPYABLE(UserDataInUse);
-        explicit UserDataInUse(UserDataInUse&& that) {
+        // cppcheck-suppress noExplicitConstructor
+        UserDataInUse(UserDataInUse&& that) {
             UASSERT(that.m_graphp, "Moving from empty");
             m_graphp = vlstd::exchange(that.m_graphp, nullptr);
         }
+        VL_UNCOPYABLE(UserDataInUse);
         UserDataInUse& operator=(UserDataInUse&& that) {
             UASSERT(that.m_graphp, "Moving from empty");
             m_graphp = vlstd::exchange(that.m_graphp, nullptr);
diff --git a/src/V3File.h b/src/V3File.h
index db1104ae2..ba2b5c6d1 100644
--- a/src/V3File.h
+++ b/src/V3File.h
@@ -285,7 +285,7 @@ public:
     explicit V3OutVFile(const string& filename)
         : V3OutCFile{filename, V3OutFormatter::LA_VERILOG} {}
     ~V3OutVFile() override = default;
-    virtual void putsHeader() { puts("// Verilated -*- Verilog -*-\n"); }
+    void putsHeader() override { puts("// Verilated -*- Verilog -*-\n"); }
 };
 
 class V3OutXmlFile final : public V3OutFile {

From 2c7f1ef40f833fe7dd8c6c22264b44810f5fdc29 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 27 Nov 2022 08:31:22 -0500
Subject: [PATCH 096/156] Internals: Cleanup debug dumps so can grep-out
 leading-dashed lines

---
 src/V3Assert.cpp     |   2 +-
 src/V3Ast.cpp        |   4 +-
 src/V3Ast.h          |   2 +-
 src/V3Case.cpp       |  14 +++---
 src/V3Cast.cpp       |   2 +-
 src/V3Cdc.cpp        |   2 +-
 src/V3Clock.cpp      |   2 +-
 src/V3Const.cpp      |  86 ++++++++++++++++++------------------
 src/V3Depth.cpp      |   2 +-
 src/V3DepthBlock.cpp |   6 +--
 src/V3Descope.cpp    |   2 +-
 src/V3Expand.cpp     |   2 +-
 src/V3Gate.cpp       |   8 ++--
 src/V3Inline.cpp     |   4 +-
 src/V3Inst.cpp       |  16 +++----
 src/V3Life.cpp       |   2 +-
 src/V3LinkDot.cpp    |  20 ++++-----
 src/V3LinkInc.cpp    |   4 +-
 src/V3LinkJump.cpp   |   4 +-
 src/V3Param.cpp      |   8 ++--
 src/V3Randomize.cpp  |   4 +-
 src/V3Reloop.cpp     |   4 +-
 src/V3Simulate.h     |   2 +-
 src/V3Slice.cpp      |   6 +--
 src/V3Split.cpp      |   8 ++--
 src/V3SplitAs.cpp    |   6 +--
 src/V3Subst.cpp      |   4 +-
 src/V3Table.cpp      |   2 +-
 src/V3Task.cpp       |  16 +++----
 src/V3Trace.cpp      |   2 +-
 src/V3Tristate.cpp   |  36 +++++++--------
 src/V3Unknown.cpp    |  22 +++++-----
 src/V3Unroll.cpp     |   8 ++--
 src/V3Width.cpp      | 102 +++++++++++++++++++++----------------------
 src/V3WidthCommit.h  |   4 +-
 src/V3WidthSel.cpp   |  36 +++++++--------
 36 files changed, 227 insertions(+), 227 deletions(-)

diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp
index 4c37f2f76..cf2de9ad0 100644
--- a/src/V3Assert.cpp
+++ b/src/V3Assert.cpp
@@ -363,7 +363,7 @@ private:
             AstNode* const assp = new AstAssignDly{
                 nodep->fileline(), new AstVarRef{nodep->fileline(), outvarp, VAccess::WRITE}, inp};
             alwaysp->addStmtsp(assp);
-            // if (debug() >= 9) assp->dumpTree(cout, "-ass: ");
+            // if (debug() >= 9) assp->dumpTree("-  ass: ");
             invarp = outvarp;
             inp = new AstVarRef{nodep->fileline(), invarp, VAccess::READ};
         }
diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp
index 5aa1c9292..ad11ff8c0 100644
--- a/src/V3Ast.cpp
+++ b/src/V3Ast.cpp
@@ -226,9 +226,9 @@ void AstNode::debugTreeChange(const AstNode* nodep, const char* prefix, int line
 //  // Commenting out the section below may crash, as the tree state
 //  // between edits is not always consistent for printing
 //  cout<<"-treeChange: V3Ast.cpp:"<<lineno<<" Tree Change for "<<prefix<<endl;
-//  v3Global.rootp()->dumpTree(cout, "-treeChange: ");
+//  v3Global.rootp()->dumpTree("-  treeChange: ");
 //  if (next||1) this->dumpTreeAndNext(cout, prefix);
-//  else this->dumpTree(cout, prefix);
+//  else this->dumpTree(prefix);
 //  this->checkTree();
 //  v3Global.rootp()->checkTree();
 //}
diff --git a/src/V3Ast.h b/src/V3Ast.h
index 30efa7ffa..e303c989c 100644
--- a/src/V3Ast.h
+++ b/src/V3Ast.h
@@ -1909,7 +1909,7 @@ public:
     void dumpTree(std::ostream& os = std::cout, const string& indent = "    ",
                   int maxDepth = 0) const;
     void dumpTree(const string& indent, int maxDepth = 0) const {
-        dumpTree(cout, indent, maxDepth);
+        dumpTree(std::cout, indent, maxDepth);
     }
     static void dumpTreeGdb(const AstNode* nodep);  // For GDB only
     void dumpTreeAndNext(std::ostream& os = std::cout, const string& indent = "    ",
diff --git a/src/V3Case.cpp b/src/V3Case.cpp
index ca9c1ab38..a8ffe9ae0 100644
--- a/src/V3Case.cpp
+++ b/src/V3Case.cpp
@@ -170,7 +170,7 @@ private:
         for (AstCaseItem* itemp = nodep->itemsp(); itemp;
              itemp = VN_AS(itemp->nextp(), CaseItem)) {
             for (AstNode* icondp = itemp->condsp(); icondp; icondp = icondp->nextp()) {
-                // if (debug() >= 9) icondp->dumpTree(cout, " caseitem: ");
+                // if (debug() >= 9) icondp->dumpTree("-  caseitem: ");
                 AstConst* const iconstp = VN_AS(icondp, Const);
                 UASSERT_OBJ(iconstp, nodep, "above 'can't parse' should have caught this");
                 if (neverItem(nodep, iconstp)) {
@@ -331,7 +331,7 @@ private:
         }
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
         VL_DO_DANGLING(cexprp->deleteTree(), cexprp);
-        if (debug() >= 9) ifrootp->dumpTree(cout, "    _simp: ");
+        if (debug() >= 9) ifrootp->dumpTree("-    _simp: ");
     }
 
     void replaceCaseComplicated(AstCase* nodep) {
@@ -342,7 +342,7 @@ private:
         AstNodeExpr* const cexprp = nodep->exprp()->unlinkFrBack();
         // We'll do this in two stages.  First stage, convert the conditions to
         // the appropriate IF AND terms.
-        if (debug() >= 9) nodep->dumpTree(cout, "    _comp_IN:   ");
+        if (debug() >= 9) nodep->dumpTree("-    _comp_IN::: ");
         bool hadDefault = false;
         for (AstCaseItem* itemp = nodep->itemsp(); itemp;
              itemp = VN_AS(itemp->nextp(), CaseItem)) {
@@ -409,7 +409,7 @@ private:
             nodep->addItemsp(new AstCaseItem{
                 nodep->fileline(), new AstConst{nodep->fileline(), AstConst::BitTrue{}}, nullptr});
         }
-        if (debug() >= 9) nodep->dumpTree(cout, "    _comp_COND: ");
+        if (debug() >= 9) nodep->dumpTree("-    _comp_COND: ");
         // Now build the IF statement tree
         // The tree can be quite huge.  Pull ever group of 8 out, and make a OR tree.
         // This reduces the depth for the bottom elements, at the cost of
@@ -459,11 +459,11 @@ private:
                 itemnextp = newp;
             }
         }
-        if (debug() >= 9) nodep->dumpTree(cout, "    _comp_TREE: ");
+        if (debug() >= 9) nodep->dumpTree("-    _comp_TREE: ");
         // Handle any assertions
         replaceCaseParallel(nodep, false);
         // Replace the CASE... with IF...
-        if (debug() >= 9 && grouprootp) grouprootp->dumpTree(cout, "     _new: ");
+        if (debug() >= 9 && grouprootp) grouprootp->dumpTree("-     _new: ");
         if (grouprootp) {
             nodep->replaceWith(grouprootp);
         } else {
@@ -498,7 +498,7 @@ private:
     void visit(AstCase* nodep) override {
         V3Case::caseLint(nodep);
         iterateChildren(nodep);
-        if (debug() >= 9) nodep->dumpTree(cout, " case_old: ");
+        if (debug() >= 9) nodep->dumpTree("-  case_old: ");
         if (isCaseTreeFast(nodep) && v3Global.opt.fCase()) {
             // It's a simple priority encoder or complete statement
             // we can make a tree of statements to avoid extra comparisons
diff --git a/src/V3Cast.cpp b/src/V3Cast.cpp
index 89563eb5c..b27e22669 100644
--- a/src/V3Cast.cpp
+++ b/src/V3Cast.cpp
@@ -71,7 +71,7 @@ private:
         AstCCast* const castp
             = new AstCCast{nodep->fileline(), nodep, needsize, nodep->widthMin()};
         relinkHandle.relink(castp);
-        // if (debug() > 8) castp->dumpTree(cout, "-castins: ");
+        // if (debug() > 8) castp->dumpTree("-  castins: ");
         //
         ensureLower32Cast(castp);
         nodep->user1(1);  // Now must be of known size
diff --git a/src/V3Cdc.cpp b/src/V3Cdc.cpp
index b1d60f438..a13e79554 100644
--- a/src/V3Cdc.cpp
+++ b/src/V3Cdc.cpp
@@ -251,7 +251,7 @@ private:
 
             if (false && debug() >= 9) {
                 UINFO(9, "Trace Logic:\n");
-                nodep->dumpTree(cout, "-log1: ");
+                nodep->dumpTree("-  log1: ");
             }
         }
     }
diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp
index 68d9326b6..7d2d39103 100644
--- a/src/V3Clock.cpp
+++ b/src/V3Clock.cpp
@@ -122,7 +122,7 @@ private:
     }
     // VISITORS
     void visit(AstCoverToggle* nodep) override {
-        // nodep->dumpTree(cout, "ct:");
+        // nodep->dumpTree("-  ct: ");
         // COVERTOGGLE(INC, ORIG, CHANGE) ->
         //   IF(ORIG ^ CHANGE) { INC; CHANGE = ORIG; }
         AstNode* const incp = nodep->incp()->unlinkFrBack();
diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index c583563d8..befd7dabd 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -366,7 +366,7 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
         if (fail && !m_failed) {
             UINFO(9, "cannot optimize " << m_rootp << " reason:" << reason << " called from line:"
                                         << line << " when checking:" << nodep << std::endl);
-            // if (debug() >= 9) m_rootp->dumpTree(std::cout << "Root node:\n");
+            // if (debug() >= 9) m_rootp->dumpTree("-  root: ");
             m_failed = true;
         }
         return m_failed;
@@ -752,16 +752,16 @@ public:
         if (needsCleaning) ++resultOps;
 
         if (debug() >= 9) {  // LCOV_EXCL_START
-            cout << "Bitop tree considered: " << endl;
-            for (AstNodeExpr* const termp : termps) termp->dumpTree("Reduced term: ");
+            cout << "-  Bitop tree considered: " << endl;
+            for (AstNodeExpr* const termp : termps) termp->dumpTree("-  Reduced term: ");
             for (const std::pair<AstNodeExpr*, FrozenNodeInfo>& termp : visitor.m_frozenNodes) {
-                termp.first->dumpTree("Frozen term with lsb " + std::to_string(termp.second.m_lsb)
-                                      + " polarity " + std::to_string(termp.second.m_polarity)
-                                      + ": ");
+                termp.first->dumpTree("-  Frozen term with lsb "
+                                      + std::to_string(termp.second.m_lsb) + " polarity "
+                                      + std::to_string(termp.second.m_polarity) + ": ");
             }
-            cout << "Needs flipping: " << needsFlip << endl;
-            cout << "Needs cleaning: " << needsCleaning << endl;
-            cout << "Size: " << resultOps << " input size: " << visitor.m_ops << endl;
+            cout << "-  Needs flipping: " << needsFlip << endl;
+            cout << "-  Needs cleaning: " << needsCleaning << endl;
+            cout << "-  Size: " << resultOps << " input size: " << visitor.m_ops << endl;
         }  // LCOV_EXCL_END
 
         // Sometimes we have no terms left after ignoring redundant terms
@@ -1148,7 +1148,7 @@ private:
         string debugPrefix;
         if (debug() >= 9) {  // LCOV_EXCL_START
             static int c = 0;
-            debugPrefix = "matchBitOpTree[";
+            debugPrefix = "-  matchBitOpTree[";
             debugPrefix += cvtToStr(++c);
             debugPrefix += "] ";
             nodep->dumpTree(debugPrefix + "INPUT: ");
@@ -1277,12 +1277,12 @@ private:
         if (!(m_doV && bip && VN_IS(nodep->lsbp(), Const) && VN_IS(nodep->widthp(), Const)
               && nodep->lsbConst() == 0))
             return false;
-        if (debug() >= 9) nodep->dumpTree(cout, "SEL(BI)-in:");
+        if (debug() >= 9) nodep->dumpTree("-  SEL(BI)-in: ");
         AstNodeExpr* const bilhsp = bip->lhsp()->unlinkFrBack();
         AstNodeExpr* const birhsp = bip->rhsp()->unlinkFrBack();
         bip->lhsp(new AstSel{nodep->fileline(), bilhsp, 0, nodep->widthConst()});
         bip->rhsp(new AstSel{nodep->fileline(), birhsp, 0, nodep->widthConst()});
-        if (debug() >= 9) bip->dumpTree(cout, "SEL(BI)-ou:");
+        if (debug() >= 9) bip->dumpTree("-  SEL(BI)-ou: ");
         VL_DO_DANGLING(replaceWChild(nodep, bip), nodep);
         return true;
     }
@@ -1306,11 +1306,11 @@ private:
         if (newLsb + nodep->widthConst() > ap->width()) return false;
         //
         UINFO(9, "SEL(SHIFTR(a,b),l,w) -> SEL(a,l+b,w)\n");
-        if (debug() >= 9) nodep->dumpTree(cout, "SEL(SH)-in:");
+        if (debug() >= 9) nodep->dumpTree("-  SEL(SH)-in: ");
         AstSel* const newp
             = new AstSel{nodep->fileline(), ap->unlinkFrBack(), newLsb, nodep->widthConst()};
         newp->dtypeFrom(nodep);
-        if (debug() >= 9) newp->dumpTree(cout, "SEL(SH)-ou:");
+        if (debug() >= 9) newp->dumpTree("-  SEL(SH)-ou: ");
         VL_DO_DANGLING(nodep->replaceWith(newp), nodep);
         return true;
     }
@@ -1328,7 +1328,7 @@ private:
         if (!constp) return false;
         if (!constp->num().isBitsZero(constp->width() - 1, subsize)) return false;
         //
-        if (debug() >= 9) nodep->dumpTree(cout, "BI(EXTEND)-in:");
+        if (debug() >= 9) nodep->dumpTree("-  BI(EXTEND)-in: ");
         smallerp->unlinkFrBack();
         VL_DO_DANGLING(extendp->unlinkFrBack()->deleteTree(), extendp);  // aka nodep->lhsp.
         nodep->rhsp(smallerp);
@@ -1338,7 +1338,7 @@ private:
         num.opAssign(constp->num());
         nodep->lhsp(new AstConst{constp->fileline(), num});
         VL_DO_DANGLING(constp->deleteTree(), constp);
-        if (debug() >= 9) nodep->dumpTree(cout, "BI(EXTEND)-ou:");
+        if (debug() >= 9) nodep->dumpTree("-  BI(EXTEND)-ou: ");
         return true;
     }
     bool operandBiExtendConstOver(const AstNodeBiop* nodep) {
@@ -1553,8 +1553,8 @@ private:
                     "Already constant??");
         AstNode* const newp = new AstConst{oldp->fileline(), num};
         newp->dtypeFrom(oldp);
-        if (debug() > 5) oldp->dumpTree(cout, "  const_old: ");
-        if (debug() > 5) newp->dumpTree(cout, "       _new: ");
+        if (debug() > 5) oldp->dumpTree("-  const_old: ");
+        if (debug() > 5) newp->dumpTree("-       _new: ");
         oldp->replaceWith(newp);
         VL_DO_DANGLING(oldp->deleteTree(), oldp);
     }
@@ -1629,8 +1629,8 @@ private:
         // Replace oldp node with a constant set to specified value
         UASSERT(oldp, "Null old");
         AstNode* const newp = new AstConst{oldp->fileline(), AstConst::String{}, num};
-        if (debug() > 5) oldp->dumpTree(cout, "  const_old: ");
-        if (debug() > 5) newp->dumpTree(cout, "       _new: ");
+        if (debug() > 5) oldp->dumpTree("-  const_old: ");
+        if (debug() > 5) newp->dumpTree("-       _new: ");
         oldp->replaceWith(newp);
         VL_DO_DANGLING(oldp->deleteTree(), oldp);
     }
@@ -1688,7 +1688,7 @@ private:
     void replaceAsv(AstNodeBiop* nodep) {
         // BIASV(CONSTa, BIASV(CONSTb, c)) -> BIASV( BIASV_CONSTED(a,b), c)
         // BIASV(SAMEa,  BIASV(SAMEb, c))  -> BIASV( BIASV(SAMEa,SAMEb), c)
-        // nodep->dumpTree(cout, "  repAsvConst_old: ");
+        // nodep->dumpTree("-  repAsvConst_old: ");
         AstNodeExpr* const ap = nodep->lhsp();
         AstNodeBiop* const rp = VN_AS(nodep->rhsp(), NodeBiop);
         AstNodeExpr* const bp = rp->lhsp();
@@ -1702,7 +1702,7 @@ private:
         rp->lhsp(ap);
         rp->rhsp(bp);
         if (VN_IS(rp->lhsp(), Const) && VN_IS(rp->rhsp(), Const)) replaceConst(rp);
-        // nodep->dumpTree(cout, "  repAsvConst_new: ");
+        // nodep->dumpTree("-  repAsvConst_new: ");
     }
     void replaceAsvLUp(AstNodeBiop* nodep) {
         // BIASV(BIASV(CONSTll,lr),r) -> BIASV(CONSTll,BIASV(lr,r))
@@ -1714,7 +1714,7 @@ private:
         nodep->rhsp(lp);
         lp->lhsp(lrp);
         lp->rhsp(rp);
-        // nodep->dumpTree(cout, "  repAsvLUp_new: ");
+        // nodep->dumpTree("-  repAsvLUp_new: ");
     }
     void replaceAsvRUp(AstNodeBiop* nodep) {
         // BIASV(l,BIASV(CONSTrl,rr)) -> BIASV(CONSTrl,BIASV(l,rr))
@@ -1726,7 +1726,7 @@ private:
         nodep->rhsp(rp);
         rp->lhsp(lp);
         rp->rhsp(rrp);
-        // nodep->dumpTree(cout, "  repAsvRUp_new: ");
+        // nodep->dumpTree("-  repAsvRUp_new: ");
     }
     void replaceAndOr(AstNodeBiop* nodep) {
         //  OR  (AND (CONSTll,lr), AND(CONSTrl==ll,rr))    -> AND (CONSTll, OR(lr,rr))
@@ -1759,7 +1759,7 @@ private:
         } else {
             nodep->v3fatalSrc("replaceAndOr on something operandAndOrSame shouldn't have matched");
         }
-        // nodep->dumpTree(cout, "  repAndOr_new: ");
+        // nodep->dumpTree("-  repAndOr_new: ");
     }
     void replaceShiftSame(AstNodeBiop* nodep) {
         // Or(Shift(ll,CONSTlr),Shift(rl,CONSTrr==lr)) -> Shift(Or(ll,rl),CONSTlr)
@@ -1778,7 +1778,7 @@ private:
         nodep->dtypep(llp->dtypep());  // dtype of Biop is before shift.
         VL_DO_DANGLING(rp->deleteTree(), rp);
         VL_DO_DANGLING(rrp->deleteTree(), rrp);
-        // nodep->dumpTree(cout, "  repShiftSame_new: ");
+        // nodep->dumpTree("-  repShiftSame_new: ");
     }
     void replaceConcatSel(AstConcat* nodep) {
         // {a[1], a[0]} -> a[1:0]
@@ -1902,7 +1902,7 @@ private:
     }
     void replaceShiftShift(AstNodeBiop* nodep) {
         UINFO(4, "SHIFT(SHIFT(a,s1),s2)->SHIFT(a,ADD(s1,s2)) " << nodep << endl);
-        if (debug() >= 9) nodep->dumpTree(cout, "  repShiftShift_old: ");
+        if (debug() >= 9) nodep->dumpTree("-  repShiftShift_old: ");
         AstNodeBiop* const lhsp = VN_AS(nodep->lhsp(), NodeBiop);
         lhsp->unlinkFrBack();
         AstNodeExpr* const ap = lhsp->lhsp()->unlinkFrBack();
@@ -1955,7 +1955,7 @@ private:
             newp->dtypeFrom(nodep);
             nodep->replaceWith(newp);
             VL_DO_DANGLING(nodep->deleteTree(), nodep);
-            // newp->dumpTree(cout, "  repShiftShift_new: ");
+            // newp->dumpTree("-  repShiftShift_new: ");
             iterate(newp);  // Further reduce, either node may have more reductions.
         }
         VL_DO_DANGLING(lhsp->deleteTree(), lhsp);
@@ -1998,8 +1998,8 @@ private:
         const bool lsbFirstAssign = (con1p->toUInt() < con2p->toUInt());
         UINFO(4, "replaceAssignMultiSel " << nodep << endl);
         UINFO(4, "                   && " << nextp << endl);
-        // nodep->dumpTree(cout, "comb1: ");
-        // nextp->dumpTree(cout, "comb2: ");
+        // nodep->dumpTree("-  comb1: ");
+        // nextp->dumpTree("-  comb2: ");
         AstNodeExpr* const rhs1p = nodep->rhsp()->unlinkFrBack();
         AstNodeExpr* const rhs2p = nextp->rhsp()->unlinkFrBack();
         AstNodeAssign* newp;
@@ -2012,7 +2012,7 @@ private:
                                                sel2p->lsbConst(), sel1p->width() + sel2p->width()},
                                     new AstConcat{rhs1p->fileline(), rhs1p, rhs2p});
         }
-        // pnewp->dumpTree(cout, "conew: ");
+        // pnewp->dumpTree("-  conew: ");
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
         VL_DO_DANGLING(nextp->unlinkFrBack()->deleteTree(), nextp);
@@ -2071,7 +2071,7 @@ private:
                 // ASSIGN(CONCAT(lc1,lc2),rhs) -> ASSIGN(lc1,SEL(rhs,{size})),
                 //                                ASSIGN(lc2,SEL(newrhs,{size}))
             }
-            if (debug() >= 9) nodep->dumpTree(cout, "  Ass_old: ");
+            if (debug() >= 9) nodep->dumpTree("-  Ass_old: ");
             // Unlink the stuff
             AstNodeExpr* const lc1p = VN_AS(nodep->lhsp(), Concat)->lhsp()->unlinkFrBack();
             AstNodeExpr* const lc2p = VN_AS(nodep->lhsp(), Concat)->rhsp()->unlinkFrBack();
@@ -2129,7 +2129,7 @@ private:
                 newp = AstNode::addNext(newp, asn1bp);
                 newp = AstNode::addNext(newp, asn2bp);
             }
-            if (debug() >= 9 && newp) newp->dumpTreeAndNext(cout, "     _new: ");
+            if (debug() >= 9 && newp) newp->dumpTreeAndNext(cout, "-     _new: ");
             nodep->addNextHere(newp);
             // Cleanup
             VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
@@ -2209,7 +2209,7 @@ private:
         return true;
     }
     void replaceBoolShift(AstNode* nodep) {
-        if (debug() >= 9) nodep->dumpTree(cout, "  bshft_old: ");
+        if (debug() >= 9) nodep->dumpTree("-  bshft_old: ");
         AstConst* const andConstp = VN_AS(VN_AS(nodep, And)->lhsp(), Const);
         AstNodeExpr* const fromp
             = VN_AS(VN_AS(nodep, And)->rhsp(), ShiftR)->lhsp()->unlinkFrBack();
@@ -2223,7 +2223,7 @@ private:
         newp->dtypeSetLogicSized(nodep->width(), VSigning::UNSIGNED);
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
-        if (debug() >= 9) newp->dumpTree(cout, "       _new: ");
+        if (debug() >= 9) newp->dumpTree("-       _new: ");
     }
 
     void replaceWithSimulation(AstNode* nodep) {
@@ -2617,7 +2617,7 @@ private:
         UASSERT_OBJ(nodep->varp(), nodep, "Not linked");
         bool did = false;
         if (m_doV && nodep->varp()->valuep() && !m_attrp) {
-            // if (debug()) valuep->dumpTree(cout, "  visitvaref: ");
+            // if (debug()) valuep->dumpTree("-  visitvaref: ");
             iterateAndNextNull(nodep->varp()->valuep());  // May change nodep->varp()->valuep()
             AstNode* const valuep = nodep->varp()->valuep();
             if (nodep->access().isReadOnly()
@@ -2671,7 +2671,7 @@ private:
         UASSERT_OBJ(nodep->itemp(), nodep, "Not linked");
         bool did = false;
         if (nodep->itemp()->valuep()) {
-            // if (debug()) nodep->itemp()->valuep()->dumpTree(cout, "  visitvaref: ");
+            // if (debug()) nodep->itemp()->valuep()->dumpTree("-  visitvaref: ");
             if (nodep->itemp()->user4()) {
                 nodep->v3error("Recursive enum value: " << nodep->itemp()->prettyNameQ());
             } else {
@@ -2791,7 +2791,7 @@ private:
     void visit(AstSenTree* nodep) override {
         iterateChildren(nodep);
         if (m_doExpensive) {
-            // cout<<endl; nodep->dumpTree(cout, "ssin: ");
+            // cout<<endl; nodep->dumpTree("-  ssin: ");
             // Optimize ideas for the future:
             //   SENTREE(... SENGATE(x,a), SENGATE(SENITEM(x),b) ...)  => SENGATE(x,OR(a,b))
 
@@ -2859,7 +2859,7 @@ private:
                     }
                 }
             }
-            // nodep->dumpTree(cout, "ssou: ");
+            // nodep->dumpTree("-  ssou: ");
         }
     }
 
@@ -3645,7 +3645,7 @@ uint32_t ConstVisitor::s_globalPassNum = 0;
 //! Force this cell node's parameter list to become a constant
 //! @return  Pointer to the edited node.
 AstNode* V3Const::constifyParamsEdit(AstNode* nodep) {
-    // if (debug() > 0) nodep->dumpTree(cout, "  forceConPRE : ");
+    // if (debug() > 0) nodep->dumpTree("-  forceConPRE : ");
     // Resize even if the node already has a width, because buried in the tree
     // we may have a node we just created with signing, etc, that isn't sized yet.
 
@@ -3661,7 +3661,7 @@ AstNode* V3Const::constifyParamsEdit(AstNode* nodep) {
         nodep = visitor.mainAcceptEdit(nodep);
     }
     // Because we do edits, nodep links may get trashed and core dump this.
-    // if (debug() > 0) nodep->dumpTree(cout, "  forceConDONE: ");
+    // if (debug() > 0) nodep->dumpTree("-  forceConDONE: ");
     return nodep;
 }
 
@@ -3674,7 +3674,7 @@ AstNode* V3Const::constifyParamsEdit(AstNode* nodep) {
 //! width check.
 //! @return  Pointer to the edited node.
 AstNode* V3Const::constifyGenerateParamsEdit(AstNode* nodep) {
-    // if (debug() > 0) nodep->dumpTree(cout, "  forceConPRE : ");
+    // if (debug() > 0) nodep->dumpTree("-  forceConPRE:: ");
     // Resize even if the node already has a width, because buried in the tree
     // we may have a node we just created with signing, etc, that isn't sized
     // yet.
@@ -3691,7 +3691,7 @@ AstNode* V3Const::constifyGenerateParamsEdit(AstNode* nodep) {
         nodep = visitor.mainAcceptEdit(nodep);
     }
     // Because we do edits, nodep links may get trashed and core dump this.
-    // if (debug() > 0) nodep->dumpTree(cout, "  forceConDONE: ");
+    // if (debug() > 0) nodep->dumpTree("-  forceConDONE: ");
     return nodep;
 }
 
diff --git a/src/V3Depth.cpp b/src/V3Depth.cpp
index a9644165b..a7f2a4288 100644
--- a/src/V3Depth.cpp
+++ b/src/V3Depth.cpp
@@ -54,7 +54,7 @@ private:
 
     void createDeepTemp(AstNodeExpr* nodep) {
         UINFO(6, "  Deep  " << nodep << endl);
-        // if (debug() >= 9) nodep->dumpTree(cout, "deep:");
+        // if (debug() >= 9) nodep->dumpTree("-  deep: ");
         AstVar* const varp = new AstVar{nodep->fileline(), VVarType::STMTTEMP,
                                         m_tempNames.get(nodep), nodep->dtypep()};
         if (m_cfuncp) {
diff --git a/src/V3DepthBlock.cpp b/src/V3DepthBlock.cpp
index 09ea0c1eb..b45e5f208 100644
--- a/src/V3DepthBlock.cpp
+++ b/src/V3DepthBlock.cpp
@@ -98,11 +98,11 @@ private:
         if (m_depth > v3Global.opt.compLimitBlocks()) {  // Already done
             UINFO(4, "DeepBlocks " << m_depth << " " << nodep << endl);
             const AstNode* const backp = nodep->backp();  // Only for debug
-            if (debug() >= 9) backp->dumpTree(cout, "-   pre : ");
+            if (debug() >= 9) backp->dumpTree("-   pre : ");
             AstCFunc* const funcp = createDeepFunc(nodep);
             iterate(funcp);
-            if (debug() >= 9) backp->dumpTree(cout, "-   post: ");
-            if (debug() >= 9) funcp->dumpTree(cout, "-   func: ");
+            if (debug() >= 9) backp->dumpTree("-   post: ");
+            if (debug() >= 9) funcp->dumpTree("-   func: ");
         } else {
             iterateChildren(nodep);
         }
diff --git a/src/V3Descope.cpp b/src/V3Descope.cpp
index 1cfccf607..be9020dd8 100644
--- a/src/V3Descope.cpp
+++ b/src/V3Descope.cpp
@@ -181,7 +181,7 @@ private:
                 //                                   string("%%Error: ")+name+"() called with bad
                 //                                   scope", nullptr));
                 // newfuncp->addStmtsp(new AstStop(newfuncp->fileline()));
-                if (debug() >= 9) newfuncp->dumpTree(cout, "   newfunc: ");
+                if (debug() >= 9) newfuncp->dumpTree("-  newfunc: ");
             } else {
                 // Only a single function under this name, we can rename it
                 UINFO(6, "  Wrapping " << name << " just one " << topFuncp << endl);
diff --git a/src/V3Expand.cpp b/src/V3Expand.cpp
index 93147f5cf..5efbb7592 100644
--- a/src/V3Expand.cpp
+++ b/src/V3Expand.cpp
@@ -595,7 +595,7 @@ private:
                 return false;
             } else {
                 UINFO(8, "    ASSIGNSEL(varlsb,narrow) " << nodep << endl);
-                // nodep->dumpTree(cout, "-  old: ");
+                // nodep->dumpTree("-  old: ");
                 AstNodeExpr* rhsp = nodep->rhsp()->unlinkFrBack();
                 AstNodeExpr* const destp = lhsp->fromp()->unlinkFrBack();
                 AstNodeExpr* oldvalp = destp->cloneTree(true);
diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp
index 618c6ed3b..3898d0a6d 100644
--- a/src/V3Gate.cpp
+++ b/src/V3Gate.cpp
@@ -286,7 +286,7 @@ public:
                 clearSimple("Circular logic\n");  // Oh my, we'll get a UNOPTFLAT much later.
             }
         }
-        if (debug() >= 9 && !m_isSimple) nodep->dumpTree(cout, "    gate!Ok: ");
+        if (debug() >= 9 && !m_isSimple) nodep->dumpTree("-    gate!Ok: ");
     }
     ~GateOkVisitor() override = default;
     // PUBLIC METHODS
@@ -387,7 +387,7 @@ private:
     }
 
     void optimizeElimVar(AstVarScope* varscp, AstNode* substp, AstNode* consumerp) {
-        if (debug() >= 5) consumerp->dumpTree(cout, "    elimUsePre: ");
+        if (debug() >= 5) consumerp->dumpTree("-    elimUsePre: ");
         if (!m_substitutions.tryGet(consumerp)) m_optimized.push_back(consumerp);
         m_substitutions(consumerp).emplace(varscp, substp->cloneTree(false));
     }
@@ -619,8 +619,8 @@ void GateVisitor::optimizeSignals(bool allowMultiIn) {
 
         // Process it
         AstNode* const substp = okVisitor.substTree();
-        if (debug() >= 5) logicp->dumpTree(cout, "    elimVar:  ");
-        if (debug() >= 5) substp->dumpTree(cout, "      subst:  ");
+        if (debug() >= 5) logicp->dumpTree("-    elimVar: ");
+        if (debug() >= 5) substp->dumpTree("-      subst: ");
         ++m_statSigs;
         bool removedAllUsages = true;
         for (V3GraphEdge* edgep = vvertexp->outBeginp(); edgep;) {
diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp
index 26abb43c6..cfb3f0f41 100644
--- a/src/V3Inline.cpp
+++ b/src/V3Inline.cpp
@@ -355,8 +355,8 @@ private:
         const string name = m_cellp->name() + "__DOT__" + nodep->name();
         if (!nodep->isFuncLocal() && !nodep->isClassMember()) nodep->inlineAttrReset(name);
         if (!m_cellp->isTrace()) nodep->trace(false);
-        if (debug() >= 9) nodep->dumpTree(cout, "varchanged:");
-        if (debug() >= 9 && nodep->valuep()) nodep->valuep()->dumpTree(cout, "varchangei:");
+        if (debug() >= 9) nodep->dumpTree("-  varchanged: ");
+        if (debug() >= 9 && nodep->valuep()) nodep->valuep()->dumpTree("-  varchangei: ");
     }
     void visit(AstNodeFTask* nodep) override {
         // Function under the inline cell, need to rename to avoid conflicts
diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp
index 11ceaec21..e0338e071 100644
--- a/src/V3Inst.cpp
+++ b/src/V3Inst.cpp
@@ -65,7 +65,7 @@ private:
             V3Inst::pinReconnectSimple(nodep, m_cellp, false);
         }
         if (!nodep->exprp()) return;  // No-connect
-        if (debug() >= 9) nodep->dumpTree(cout, "  Pin_oldb: ");
+        if (debug() >= 9) nodep->dumpTree("-  Pin_oldb: ");
         V3Inst::checkOutputShort(nodep);
         // Use user1p on the PIN to indicate we created an assign for this pin
         if (!nodep->user1SetOnce()) {
@@ -89,7 +89,7 @@ private:
                                                     m_cellp->name(), VAccess::WRITE},
                                      exprp};
                 m_cellp->addNextHere(assp);
-                if (debug() >= 9) assp->dumpTree(cout, "     _new: ");
+                if (debug() >= 9) assp->dumpTree("-     _new: ");
             } else if (nodep->modVarp()->isIfaceRef()
                        || (VN_IS(nodep->modVarp()->subDTypep(), UnpackArrayDType)
                            && VN_IS(
@@ -227,7 +227,7 @@ private:
             }
             if (prevp) nodep->addNextHere(prevp);
             if (prevp && debug() == 9) {
-                prevp->dumpTree(cout, "newintf: ");
+                prevp->dumpTree("-  newintf: ");
                 cout << endl;
             }
         }
@@ -285,14 +285,14 @@ private:
                     varNewp->dtypep(ifaceRefp);
                     newp->addNextHere(varNewp);
                     if (debug() == 9) {
-                        varNewp->dumpTree(cout, "newintf: ");
+                        varNewp->dumpTree("-  newintf: ");
                         cout << endl;
                     }
                 }
                 // Fixup pins
                 iterateAndNextNull(newp->pinsp());
                 if (debug() == 9) {
-                    newp->dumpTree(cout, "newcell: ");
+                    newp->dumpTree("-  newcell: ");
                     cout << endl;
                 }
             }
@@ -551,7 +551,7 @@ public:
             // Done. Constant.
         } else {
             // Make a new temp wire
-            // if (1 || debug() >= 9) pinp->dumpTree(cout, "-in_pin:");
+            // if (1 || debug() >= 9) pinp->dumpTree("-  in_pin: ");
             V3Inst::checkOutputShort(pinp);
             AstNodeExpr* const pinexprp = VN_AS(pinp->exprp(), NodeExpr)->unlinkFrBack();
             const string newvarname
@@ -583,8 +583,8 @@ public:
                 pinp->exprp(new AstVarRef{pinexprp->fileline(), newvarp, VAccess::READ});
             }
             if (assignp) cellp->addNextHere(assignp);
-            // if (debug()) pinp->dumpTree(cout, "-  out:");
-            // if (debug()) assignp->dumpTree(cout, "- aout:");
+            // if (debug()) pinp->dumpTree("-  out: ");
+            // if (debug()) assignp->dumpTree("-  aout: ");
         }
         return assignp;
     }
diff --git a/src/V3Life.cpp b/src/V3Life.cpp
index 407880934..4bbfb904b 100644
--- a/src/V3Life.cpp
+++ b/src/V3Life.cpp
@@ -150,7 +150,7 @@ public:
                 // Redundant assignment, in same level block
                 // Don't delete it now as it will confuse iteration since it maybe WAY
                 // above our current iteration point.
-                if (debug() > 4) oldassp->dumpTree(cout, "       REMOVE/SAMEBLK ");
+                if (debug() > 4) oldassp->dumpTree("-      REMOVE/SAMEBLK: ");
                 entp->complexAssign();
                 VL_DO_DANGLING(m_statep->pushUnlinkDeletep(oldassp), oldassp);
                 ++m_statep->m_statAssnDel;
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index b28ebc5b0..bf6a6c5ad 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1741,7 +1741,7 @@ class LinkDotScopeVisitor final : public VNVisitor {
     void visit(AstAssignAlias* nodep) override {
         // Track aliases created by V3Inline; if we get a VARXREF(aliased_from)
         // we'll need to replace it with a VARXREF(aliased_to)
-        if (debug() >= 9) nodep->dumpTree(cout, "-    alias: ");
+        if (debug() >= 9) nodep->dumpTree("-    alias: ");
         AstVarScope* const fromVscp = VN_AS(nodep->lhsp(), VarRef)->varScopep();
         AstVarScope* const toVscp = VN_AS(nodep->rhsp(), VarRef)->varScopep();
         UASSERT_OBJ(fromVscp && toVscp, nodep, "Bad alias scopes");
@@ -1750,7 +1750,7 @@ class LinkDotScopeVisitor final : public VNVisitor {
     }
     void visit(AstAssignVarScope* nodep) override {
         UINFO(5, "ASSIGNVARSCOPE  " << nodep << endl);
-        if (debug() >= 9) nodep->dumpTree(cout, "-    avs: ");
+        if (debug() >= 9) nodep->dumpTree("-    avs: ");
         VSymEnt* rhsSymp;
         {
             AstVarRef* const refp = VN_CAST(nodep->rhsp(), VarRef);
@@ -2142,8 +2142,8 @@ private:
             else {
                 m_pinSymp = m_statep->getNodeSym(nodep->modp());
                 UINFO(4, "(Backto) Link Cell: " << nodep << endl);
-                // if (debug()) nodep->dumpTree(cout, "linkcell:");
-                // if (debug()) nodep->modp()->dumpTree(cout, "linkcemd:");
+                // if (debug()) nodep->dumpTree("-  linkcell: ");
+                // if (debug()) nodep->modp()->dumpTree("-  linkcemd: ");
                 iterateChildren(nodep);
             }
         }
@@ -2162,8 +2162,8 @@ private:
             // ClassRef's have pins, so track
             m_pinSymp = m_statep->getNodeSym(nodep->classp());
             UINFO(4, "(Backto) Link ClassRefDType: " << nodep << endl);
-            // if (debug()) nodep->dumpTree(cout, "linkcell:");
-            // if (debug()) nodep->modp()->dumpTree(cout, "linkcemd:");
+            // if (debug()) nodep->dumpTree("-  linkcell: ");
+            // if (debug()) nodep->modp()->dumpTree("-  linkcemd: ");
             iterateChildren(nodep);
         }
     }
@@ -2221,7 +2221,7 @@ private:
         const bool start = (m_ds.m_dotPos == DP_NONE);  // Save, as m_dotp will be changed
         {
             if (start) {  // Starting dot sequence
-                if (debug() >= 9) nodep->dumpTree("-dot-in: ");
+                if (debug() >= 9) nodep->dumpTree("-  dot-in: ");
                 m_ds.init(m_curSymp);  // Start from current point
             }
             m_ds.m_dotp = nodep;  // Always, not just at start
@@ -2264,7 +2264,7 @@ private:
             } else {
                 m_ds.m_dotPos = DP_SCOPE;
                 iterateAndNextNull(nodep->lhsp());
-                // if (debug() >= 9) nodep->dumpTree("-dot-lho: ");
+                // if (debug() >= 9) nodep->dumpTree("-  dot-lho: ");
             }
             if (m_statep->forPrimary() && isParamedClassRef(nodep->lhsp())) {
                 // Dots of paramed classes will be linked after deparametrization
@@ -2281,7 +2281,7 @@ private:
                 // DOT(DOT(x,*here*),real-rhs) which we consider a RHS
                 if (start && m_ds.m_dotPos == DP_SCOPE) m_ds.m_dotPos = DP_FINAL;
                 iterateAndNextNull(nodep->rhsp());
-                // if (debug() >= 9) nodep->dumpTree("-dot-rho: ");
+                // if (debug() >= 9) nodep->dumpTree("-  dot-rho: ");
             }
             if (start) {
                 AstNode* newp;
@@ -2291,7 +2291,7 @@ private:
                     // RHS is what we're left with
                     newp = nodep->rhsp()->unlinkFrBack();
                 }
-                if (debug() >= 9) newp->dumpTree("-dot-out: ");
+                if (debug() >= 9) newp->dumpTree("-  dot-out: ");
                 nodep->replaceWith(newp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
             } else {  // Dot midpoint
diff --git a/src/V3LinkInc.cpp b/src/V3LinkInc.cpp
index 6f4970486..c08b58f6a 100644
--- a/src/V3LinkInc.cpp
+++ b/src/V3LinkInc.cpp
@@ -70,11 +70,11 @@ private:
     void insertBeforeStmt(AstNode* nodep, AstNode* newp) {
         // Return node that must be visited, if any
         // See also AstNode::addBeforeStmt; this predates that function
-        if (debug() >= 9) newp->dumpTree(cout, "-newstmt:");
+        if (debug() >= 9) newp->dumpTree("-  newstmt: ");
         UASSERT_OBJ(m_insStmtp, nodep, "Function not underneath a statement");
         if (m_insMode == IM_BEFORE) {
             // Add the whole thing before insertAt
-            if (debug() >= 9) newp->dumpTree(cout, "-newfunc:");
+            if (debug() >= 9) newp->dumpTree("-  newfunc: ");
             m_insStmtp->addHereThisAsNext(newp);
         } else if (m_insMode == IM_AFTER) {
             m_insStmtp->addNextHere(newp);
diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp
index a614834f6..d028cb11f 100644
--- a/src/V3LinkJump.cpp
+++ b/src/V3LinkJump.cpp
@@ -289,7 +289,7 @@ private:
                 break;
             }
         }
-        // if (debug() >= 9) { UINFO(0, "\n"); blockp->dumpTree(cout, "  labeli: "); }
+        // if (debug() >= 9) { UINFO(0, "\n"); blockp->dumpTree("-  labeli: "); }
         if (!blockp) {
             nodep->v3error("disable isn't underneath a begin with name: " << nodep->prettyNameQ());
         } else if (AstBegin* const beginp = VN_CAST(blockp, Begin)) {
@@ -301,7 +301,7 @@ private:
         }
         nodep->unlinkFrBack();
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
-        // if (debug() >= 9) { UINFO(0, "\n"); beginp->dumpTree(cout, "  labelo: "); }
+        // if (debug() >= 9) { UINFO(0, "\n"); beginp->dumpTree("-  labelo: "); }
     }
     void visit(AstVarRef* nodep) override {
         if (m_loopInc && nodep->varp()) nodep->varp()->usedLoopIdx(true);
diff --git a/src/V3Param.cpp b/src/V3Param.cpp
index 8ad9a5a23..f3e4b5037 100644
--- a/src/V3Param.cpp
+++ b/src/V3Param.cpp
@@ -655,7 +655,7 @@ class ParamProcessor final {
                 AstConst* const exprp = VN_CAST(pinp->exprp(), Const);
                 const AstConst* const origp = VN_CAST(modvarp->valuep(), Const);
                 if (!exprp) {
-                    if (debug()) pinp->dumpTree(cout, "-nodes: ");
+                    if (debug()) pinp->dumpTree("-  ");
                     pinp->v3error("Can't convert defparam value to constant: Param "
                                   << pinp->prettyNameQ() << " of " << nodep->prettyNameQ());
                     pinp->exprp()->replaceWith(new AstConst{
@@ -768,9 +768,9 @@ class ParamProcessor final {
                            AstPin* pinsp, bool any_overrides) {
         // Make sure constification worked
         // Must be a separate loop, as constant conversion may have changed some pointers.
-        // if (debug()) nodep->dumpTree(cout, "-cel2: ");
+        // if (debug()) nodep->dumpTree("-  cel2: ");
         string longname = srcModpr->name() + "_";
-        if (debug() > 8 && paramsp) paramsp->dumpTreeAndNext(cout, "-cellparams: ");
+        if (debug() > 8 && paramsp) paramsp->dumpTreeAndNext(cout, "-  cellparams: ");
 
         if (srcModpr->hierBlock()) {
             longname = parameterizedHierBlockName(srcModpr, paramsp);
@@ -849,7 +849,7 @@ public:
         // and remove any recursive references
         UINFO(4, "De-parameterize: " << nodep << endl);
         // Create new module name with _'s between the constants
-        if (debug() >= 10) nodep->dumpTree(cout, "-cell: ");
+        if (debug() >= 10) nodep->dumpTree("-  cell: ");
         // Evaluate all module constants
         V3Const::constifyParamsEdit(nodep);
         srcModpr->someInstanceName(someInstanceName + "." + nodep->name());
diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp
index a7e1bcc77..493b2db67 100644
--- a/src/V3Randomize.cpp
+++ b/src/V3Randomize.cpp
@@ -281,7 +281,7 @@ private:
         //   else warning
         // Note this code assumes that the expressions after V3Const are fast to compute
         // Optimize: we would be better with a binary search tree to reduce ifs that execute
-        if (debug() >= 9) nodep->dumpTree(cout, "-rcin:  ");
+        if (debug() >= 9) nodep->dumpTree("-  rcin:: ");
         AstNodeDType* const sumDTypep = nodep->findUInt64DType();
 
         FileLine* const fl = nodep->fileline();
@@ -324,7 +324,7 @@ private:
                                     new AstAdd{fl, new AstConst{fl, AstConst::Unsized64{}, 1},
                                                new AstModDiv{fl, randp, sump}}});
         newp->addNext(firstIfsp);
-        if (debug() >= 9) newp->dumpTreeAndNext(cout, "-rcnew: ");
+        if (debug() >= 9) newp->dumpTreeAndNext(cout, "-  rcnew: ");
         nodep->replaceWith(newp);
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
     }
diff --git a/src/V3Reloop.cpp b/src/V3Reloop.cpp
index 75108c134..bed943f75 100644
--- a/src/V3Reloop.cpp
+++ b/src/V3Reloop.cpp
@@ -130,8 +130,8 @@ private:
                     rbitp->replaceWith(m_mgOffset < 0 ? new AstAdd{fl, rvrefp, offsetp} : rvrefp);
                     VL_DO_DANGLING(rbitp->deleteTree(), lbitp);
                 }
-                if (debug() >= 9) initp->dumpTree(cout, "-new: ");
-                if (debug() >= 9) whilep->dumpTree(cout, "-new: ");
+                if (debug() >= 9) initp->dumpTree("-  new: ");
+                if (debug() >= 9) whilep->dumpTree("-  new: ");
 
                 // Remove remaining assigns
                 for (AstNodeAssign* assp : m_mgAssignps) {
diff --git a/src/V3Simulate.h b/src/V3Simulate.h
index 8b0854c90..24113394f 100644
--- a/src/V3Simulate.h
+++ b/src/V3Simulate.h
@@ -702,7 +702,7 @@ private:
             // Values are in the "real" tree under the InitArray so can eventually extract it,
             // Not in the usual setValue (pointed to by user2/3p)
             initp->addIndexValuep(index, valuep);
-            if (debug() >= 9) initp->dumpTree(cout, "-array-");
+            if (debug() >= 9) initp->dumpTree("-  array: ");
             assignOutValue(nodep, vscp, initp);
         }
     }
diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp
index 0c027e5fe..59a08ee8c 100644
--- a/src/V3Slice.cpp
+++ b/src/V3Slice.cpp
@@ -135,7 +135,7 @@ class SliceVisitor final : public VNVisitor {
         if (!nodep->user1() && !VN_IS(nodep, AssignAlias)) {
             nodep->user1(true);
             m_assignError = false;
-            if (debug() >= 9) nodep->dumpTree(cout, " Deslice-In: ");
+            if (debug() >= 9) nodep->dumpTree("-  Deslice-In: ");
             AstNodeDType* const dtp = nodep->lhsp()->dtypep()->skipRefp();
             if (const AstUnpackArrayDType* const arrayp = VN_CAST(dtp, UnpackArrayDType)) {
                 // Left and right could have different msb/lsbs/endianness, but #elements is common
@@ -147,10 +147,10 @@ class SliceVisitor final : public VNVisitor {
                     AstNodeAssign* const newp
                         = nodep->cloneType(cloneAndSel(nodep->lhsp(), elements, offset),
                                            cloneAndSel(nodep->rhsp(), elements, offset));
-                    if (debug() >= 9) newp->dumpTree(cout, "-new ");
+                    if (debug() >= 9) newp->dumpTree("-  new: ");
                     newlistp = AstNode::addNext(newlistp, newp);
                 }
-                if (debug() >= 9) nodep->dumpTree(cout, " Deslice-Dn: ");
+                if (debug() >= 9) nodep->dumpTree("-  Deslice-Dn: ");
                 nodep->replaceWith(newlistp);
                 VL_DO_DANGLING(nodep->deleteTree(), nodep);
                 // Normal edit iterator will now iterate on all of the expansion assignments
diff --git a/src/V3Split.cpp b/src/V3Split.cpp
index 9eca2f8ca..380801070 100644
--- a/src/V3Split.cpp
+++ b/src/V3Split.cpp
@@ -320,7 +320,7 @@ protected:
                 if (debug() >= 9) {
                     const SplitVarStdVertex* const stdp = static_cast<SplitVarStdVertex*>(vertexp);
                     UINFO(0, "Will prune deps on var " << stdp->nodep() << endl);
-                    stdp->nodep()->dumpTree(cout, "- ");
+                    stdp->nodep()->dumpTree("-  ");
                 }
                 for (V3GraphEdge* edgep = vertexp->inBeginp(); edgep; edgep = edgep->inNextp()) {
                     SplitEdge* const oedgep = dynamic_cast<SplitEdge*>(edgep);
@@ -600,10 +600,10 @@ protected:
 
     void visit(AstAlways* nodep) override {
         UINFO(4, "   ALW   " << nodep << endl);
-        if (debug() >= 9) nodep->dumpTree(cout, "   alwIn:: ");
+        if (debug() >= 9) nodep->dumpTree("-  alwIn:: ");
         scoreboardClear();
         processBlock(nodep->stmtsp());
-        if (debug() >= 9) nodep->dumpTree(cout, "   alwOut: ");
+        if (debug() >= 9) nodep->dumpTree("-  alwOut: ");
     }
 
     void visit(AstNodeIf* nodep) override {
@@ -924,7 +924,7 @@ protected:
                         const SplitNodeVertex* const nvxp = dynamic_cast<SplitNodeVertex*>(vxp);
                         UINFO(0, "Cannot prune if-node due to edge "
                                      << oedgep << " pointing to node " << nvxp->nodep() << endl);
-                        nvxp->nodep()->dumpTree(cout, "- ");
+                        nvxp->nodep()->dumpTree("-  ");
                     }
 
                     break;
diff --git a/src/V3SplitAs.cpp b/src/V3SplitAs.cpp
index 52810f33c..564e023df 100644
--- a/src/V3SplitAs.cpp
+++ b/src/V3SplitAs.cpp
@@ -136,18 +136,18 @@ private:
     void splitAlways(AstAlways* nodep) {
         UINFO(3, "Split  " << nodep << endl);
         UINFO(3, "   For " << m_splitVscp << endl);
-        if (debug() >= 9) nodep->dumpTree(cout, "-in  : ");
+        if (debug() >= 9) nodep->dumpTree("-  in: ");
         // Duplicate it and link in
         AstAlways* const newp = nodep->cloneTree(false);
         newp->user1(true);  // So we don't clone it again
         nodep->addNextHere(newp);
         {  // Delete stuff we don't want in old
             const SplitAsCleanVisitor visitor{nodep, m_splitVscp, false};
-            if (debug() >= 9) nodep->dumpTree(cout, "-out0: ");
+            if (debug() >= 9) nodep->dumpTree("-  out0: ");
         }
         {  // Delete stuff we don't want in new
             const SplitAsCleanVisitor visitor{newp, m_splitVscp, true};
-            if (debug() >= 9) newp->dumpTree(cout, "-out1: ");
+            if (debug() >= 9) newp->dumpTree("-  out1: ");
         }
     }
 
diff --git a/src/V3Subst.cpp b/src/V3Subst.cpp
index 04535e9a2..56c74181b 100644
--- a/src/V3Subst.cpp
+++ b/src/V3Subst.cpp
@@ -288,12 +288,12 @@ private:
         if (!hit) iterate(nodep->lhsp());
     }
     void replaceSubstEtc(AstNode* nodep, AstNodeExpr* substp) {
-        if (debug() > 5) nodep->dumpTree(cout, "  substw_old: ");
+        if (debug() > 5) nodep->dumpTree("-  substw_old: ");
         AstNodeExpr* newp = substp->cloneTree(true);
         if (!nodep->isQuad() && newp->isQuad()) {
             newp = new AstCCast{newp->fileline(), newp, nodep};
         }
-        if (debug() > 5) newp->dumpTree(cout, "       w_new: ");
+        if (debug() > 5) newp->dumpTree("-       w_new: ");
         nodep->replaceWith(newp);
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
         ++m_statSubsts;
diff --git a/src/V3Table.cpp b/src/V3Table.cpp
index 7269ab9df..5680d80af 100644
--- a/src/V3Table.cpp
+++ b/src/V3Table.cpp
@@ -277,7 +277,7 @@ private:
         // Keep sensitivity list, but delete all else
         nodep->stmtsp()->unlinkFrBackWithNext()->deleteTree();
         nodep->addStmtsp(stmtsp);
-        if (debug() >= 6) nodep->dumpTree(cout, "  table_new: ");
+        if (debug() >= 6) nodep->dumpTree("-  table_new: ");
     }
 
     void createTables(AstAlways* nodep, TableBuilder& outputAssignedTableBuilder) {
diff --git a/src/V3Task.cpp b/src/V3Task.cpp
index c8d0ef3fb..73a93679d 100644
--- a/src/V3Task.cpp
+++ b/src/V3Task.cpp
@@ -427,7 +427,7 @@ private:
         AstNode* const beginp
             = new AstComment{refp->fileline(), string("Function: ") + refp->name(), true};
         if (newbodysp) beginp->addNext(newbodysp);
-        if (debug() >= 9) beginp->dumpTreeAndNext(cout, "-newbegi:");
+        if (debug() >= 9) beginp->dumpTreeAndNext(cout, "-  newbegi: ");
         //
         // Create input variables
         AstNode::user2ClearTree();
@@ -530,7 +530,7 @@ private:
         // Replace variable refs
         relink(beginp);
         //
-        if (debug() >= 9) beginp->dumpTreeAndNext(cout, "-iotask: ");
+        if (debug() >= 9) beginp->dumpTreeAndNext(cout, "-  iotask: ");
         return beginp;
     }
 
@@ -637,7 +637,7 @@ private:
 
         if (outvscp) ccallp->addArgsp(new AstVarRef{refp->fileline(), outvscp, VAccess::WRITE});
 
-        if (debug() >= 9) beginp->dumpTreeAndNext(cout, "-nitask: ");
+        if (debug() >= 9) beginp->dumpTreeAndNext(cout, "-  nitask: ");
         return beginp;
     }
 
@@ -1313,7 +1313,7 @@ private:
 
         // Delete rest of cloned task and return new func
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
-        if (debug() >= 9) cfuncp->dumpTree(cout, "-userFunc: ");
+        if (debug() >= 9) cfuncp->dumpTree("-  userFunc: ");
         return cfuncp;
     }
 
@@ -1331,13 +1331,13 @@ private:
     AstNode* insertBeforeStmt(AstNode* nodep, AstNode* newp) {
         // Return node that must be visited, if any
         // See also AstNode::addBeforeStmt; this predates that function
-        if (debug() >= 9) nodep->dumpTree(cout, "-newstmt:");
+        if (debug() >= 9) nodep->dumpTree("-  newstmt: ");
         UASSERT_OBJ(m_insStmtp, nodep, "Function not underneath a statement");
         AstNode* visitp = nullptr;
         if (m_insMode == IM_BEFORE) {
             // Add the whole thing before insertAt
             UINFO(5, "     IM_Before  " << m_insStmtp << endl);
-            if (debug() >= 9) newp->dumpTree(cout, "-newfunc:");
+            if (debug() >= 9) newp->dumpTree("-  newfunc: ");
             m_insStmtp->addHereThisAsNext(newp);
         } else if (m_insMode == IM_AFTER) {
             UINFO(5, "     IM_After   " << m_insStmtp << endl);
@@ -1383,7 +1383,7 @@ private:
         UASSERT_OBJ(nodep->taskp(), nodep, "Unlinked?");
         iterateIntoFTask(nodep->taskp());  // First, do hierarchical funcs
         UINFO(4, " FTask REF   " << nodep << endl);
-        if (debug() >= 9) nodep->dumpTree(cout, "-inlfunc:");
+        if (debug() >= 9) nodep->dumpTree("-  inlfunc: ");
         UASSERT_OBJ(m_scopep, nodep, "func ref not under scope");
         const string namePrefix = ((VN_IS(nodep, FuncRef) ? "__Vfunc_" : "__Vtask_")
                                    + nodep->taskp()->shortName() + "__" + cvtToStr(m_modNCalls++));
@@ -1687,7 +1687,7 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp)
     }
 
     if (debug() >= 9) {  // LCOV_EXCL_START
-        nodep->dumpTree(cout, "-ftref-out: ");
+        nodep->dumpTree("-  ftref-out: ");
         for (int i = 0; i < tpinnum; ++i) {
             UINFO(0, "   pin " << i << "  conn=" << cvtToHex(tconnects[i].second) << endl);
         }
diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp
index ec9d3fa6a..618a1dd0a 100644
--- a/src/V3Trace.cpp
+++ b/src/V3Trace.cpp
@@ -331,7 +331,7 @@ private:
             if (TraceTraceVertex* const vtxp = dynamic_cast<TraceTraceVertex*>(itp)) {
                 ActCodeSet actSet;
                 UINFO(9, "  Add to sort: " << vtxp << endl);
-                if (debug() >= 9) vtxp->nodep()->dumpTree(cout, "-   trnode: ");
+                if (debug() >= 9) vtxp->nodep()->dumpTree("-   trnode: ");
                 for (const V3GraphEdge* edgep = vtxp->inBeginp(); edgep;
                      edgep = edgep->inNextp()) {
                     const TraceActivityVertex* const cfvertexp
diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp
index 6a274d160..cd5a1eba7 100644
--- a/src/V3Tristate.cpp
+++ b/src/V3Tristate.cpp
@@ -818,7 +818,7 @@ class TristateVisitor final : public TristateBaseVisitor {
         if (envarp) {
             AstAssignW* const enAssp = new AstAssignW{
                 enp->fileline(), new AstVarRef{envarp->fileline(), envarp, VAccess::WRITE}, enp};
-            if (debug() >= 9) enAssp->dumpTree(cout, "enAssp: ");
+            if (debug() >= 9) enAssp->dumpTree("-  enAssp: ");
             nodep->addStmtsp(enAssp);
         }
 
@@ -826,7 +826,7 @@ class TristateVisitor final : public TristateBaseVisitor {
         AstNode* const assp = new AstAssignW{
             lhsp->fileline(), new AstVarRef{lhsp->fileline(), lhsp, VAccess::WRITE}, orp};
         assp->user2(U2_BOTH);  // Don't process further; already resolved
-        if (debug() >= 9) assp->dumpTree(cout, "-lhsp-eqn: ");
+        if (debug() >= 9) assp->dumpTree("-  lhsp-eqn: ");
         nodep->addStmtsp(assp);
     }
 
@@ -1072,7 +1072,7 @@ class TristateVisitor final : public TristateBaseVisitor {
                     AstNodeExpr* const newp
                         = newEnableDeposit(nodep, VN_AS(nodep->user1p(), NodeExpr));
                     nodep->fromp()->user1p(newp);  // Push to varref (etc)
-                    if (debug() >= 9) newp->dumpTree(cout, "-assign-sel; ");
+                    if (debug() >= 9) newp->dumpTree("-  assign-sel: ");
                     m_tgraph.didProcess(nodep);
                 }
                 iterateChildren(nodep);
@@ -1150,7 +1150,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             associateLogic(nodep->rhsp(), nodep);
             m_tgraph.setTristate(nodep);
         } else {
-            if (debug() >= 9) nodep->backp()->dumpTree(cout, "-bufif: ");
+            if (debug() >= 9) nodep->backp()->dumpTree("-  bufif: ");
             if (m_alhs) {
                 nodep->v3warn(E_UNSUPPORTED,
                               "Unsupported LHS tristate construct: " << nodep->prettyTypeName());
@@ -1252,7 +1252,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             nodep->user2(U2_NONGRAPH);
             iterateAndNextNull(nodep->rhsp());
             UINFO(9, dbgState() << nodep << endl);
-            if (debug() >= 9) nodep->dumpTree(cout, "-assign: ");
+            if (debug() >= 9) nodep->dumpTree("-  assign: ");
             // if the rhsp of this assign statement has an output enable driver,
             // then propagate the corresponding output enable assign statement.
             // down the lvalue tree by recursion for eventual attachment to
@@ -1322,8 +1322,8 @@ class TristateVisitor final : public TristateBaseVisitor {
                                     new AstEqCase{fl, new AstConst{fl, oneIfEnOne}, rhsp}};
                 if (neq) newp = new AstLogNot{fl, newp};
                 UINFO(9, "       newceq " << newp << endl);
-                if (debug() >= 9) nodep->dumpTree(cout, "-caseeq-old: ");
-                if (debug() >= 9) newp->dumpTree(cout, "-caseeq-new: ");
+                if (debug() >= 9) nodep->dumpTree("-  caseeq-old: ");
+                if (debug() >= 9) newp->dumpTree("-  caseeq-new: ");
                 nodep->replaceWith(newp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
             } else if (constp && nodep->rhsp()->user1p()) {
@@ -1338,8 +1338,8 @@ class TristateVisitor final : public TristateBaseVisitor {
                 if (neq) newp = new AstLogNot{fl, newp};
                 rhsp->user1p(nullptr);
                 UINFO(9, "       newceq " << newp << endl);
-                if (debug() >= 9) nodep->dumpTree(cout, "-caseeq-old: ");
-                if (debug() >= 9) newp->dumpTree(cout, "-caseeq-new: ");
+                if (debug() >= 9) nodep->dumpTree("-  caseeq-old: ");
+                if (debug() >= 9) newp->dumpTree("-  caseeq-new: ");
                 nodep->replaceWith(newp);
                 VL_DO_DANGLING(pushDeletep(nodep), nodep);
             } else {
@@ -1419,7 +1419,7 @@ class TristateVisitor final : public TristateBaseVisitor {
                     }
                     newp = new AstAdd{nodep->fileline(), nodep, newp};
                 }
-                if (debug() >= 9) newp->dumpTree(cout, "-countout: ");
+                if (debug() >= 9) newp->dumpTree("-  countout: ");
                 relinkHandle.relink(newp);
             }
             iterateChildren(nodep);
@@ -1435,7 +1435,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             varrefp = VN_AS(VN_AS(nodep->lhsp(), Sel)->fromp(), VarRef);
         }
         if (!varrefp) {
-            if (debug() >= 4) nodep->dumpTree(cout, "- ");
+            if (debug() >= 4) nodep->dumpTree("-  ");
             nodep->v3warn(E_UNSUPPORTED, "Unsupported pullup/down (weak driver) construct.");
         } else {
             if (m_graphing) {
@@ -1514,7 +1514,7 @@ class TristateVisitor final : public TristateBaseVisitor {
             }
             // Tristate exists:
             UINFO(9, dbgState() << nodep << endl);
-            if (debug() >= 9) nodep->dumpTree(cout, "-pin-pre: ");
+            if (debug() >= 9) nodep->dumpTree("-  pin-pre: ");
 
             // Empty/in-only; need Z to propagate
             const bool inDeclProcessing = (nodep->exprp()
@@ -1569,7 +1569,7 @@ class TristateVisitor final : public TristateBaseVisitor {
                 m_modp->addStmtsp(enVarp);
                 enrefp = new AstVarRef{nodep->fileline(), enVarp, VAccess::READ};
                 UINFO(9, "       newvrf " << enrefp << endl);
-                if (debug() >= 9) enpinp->dumpTree(cout, "-pin-ena: ");
+                if (debug() >= 9) enpinp->dumpTree("-  pin-ena: ");
             }
             // Create new output pin
             const AstAssignW* outAssignp = nullptr;  // If reconnected, the related assignment
@@ -1600,11 +1600,11 @@ class TristateVisitor final : public TristateBaseVisitor {
                     // a VarRef without any ArraySel, etc
                     TristatePinVisitor{outexprp, m_tgraph, true};
                 }
-                if (debug() >= 9) outpinp->dumpTree(cout, "-pin-opr: ");
+                if (debug() >= 9) outpinp->dumpTree("-  pin-opr: ");
                 outAssignp = V3Inst::pinReconnectSimple(outpinp, m_cellp,
                                                         true);  // Note may change outpinp->exprp()
-                if (debug() >= 9) outpinp->dumpTree(cout, "-pin-out: ");
-                if (debug() >= 9 && outAssignp) outAssignp->dumpTree(cout, "-pin-out: ");
+                if (debug() >= 9) outpinp->dumpTree("-  pin-out: ");
+                if (debug() >= 9 && outAssignp) outAssignp->dumpTree("-  pin-out: ");
                 // Must still iterate the outAssignp, as need to build output equation
             }
 
@@ -1612,8 +1612,8 @@ class TristateVisitor final : public TristateBaseVisitor {
             const TristatePinVisitor visitor{nodep->exprp(), m_tgraph, false};
             const AstNode* const inAssignp = V3Inst::pinReconnectSimple(
                 nodep, m_cellp, true);  // Note may change nodep->exprp()
-            if (debug() >= 9) nodep->dumpTree(cout, "-pin-in:  ");
-            if (debug() >= 9 && inAssignp) inAssignp->dumpTree(cout, "-pin-as:  ");
+            if (debug() >= 9) nodep->dumpTree("-  pin-in:: ");
+            if (debug() >= 9 && inAssignp) inAssignp->dumpTree("-  pin-as:: ");
 
             // Connect enable to output signal
             AstVarRef* exprrefp;  // Tristate variable that the Pin's expression refers to
diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp
index 459112a11..ccd394846 100644
--- a/src/V3Unknown.cpp
+++ b/src/V3Unknown.cpp
@@ -135,7 +135,7 @@ private:
                          fl, prep, new AstVarRef{fl, varp, VAccess::READ}, m_timingControlp}))};
             newp->branchPred(VBranchPred::BP_LIKELY);
             newp->isBoundsCheck(true);
-            if (debug() >= 9) newp->dumpTree(cout, "     _new: ");
+            if (debug() >= 9) newp->dumpTree("-     _new: ");
             abovep->addNextStmt(newp, abovep);
             prep->user2p(newp);  // Save so we may LogAnd it next time
         }
@@ -321,7 +321,7 @@ private:
     void visit(AstConst* nodep) override {
         if (m_constXCvt && nodep->num().isFourState()) {
             UINFO(4, " CONST4 " << nodep << endl);
-            if (debug() >= 9) nodep->dumpTree(cout, "  Const_old: ");
+            if (debug() >= 9) nodep->dumpTree("-  Const_old: ");
             // CONST(num) -> VARREF(newvarp)
             //          -> VAR(newvarp)
             //          -> INITIAL(VARREF(newvarp, OR(num_No_Xs,AND(random,num_1s_Where_X))
@@ -371,9 +371,9 @@ private:
                 m_modp->addStmtsp(newvarp);
                 m_modp->addStmtsp(newinitp);
                 m_modp->addStmtsp(afterp);
-                if (debug() >= 9) newref1p->dumpTree(cout, "     _new: ");
-                if (debug() >= 9) newvarp->dumpTree(cout, "     _new: ");
-                if (debug() >= 9) newinitp->dumpTree(cout, "     _new: ");
+                if (debug() >= 9) newref1p->dumpTree("-     _new: ");
+                if (debug() >= 9) newvarp->dumpTree("-     _new: ");
+                if (debug() >= 9) newinitp->dumpTree("-     _new: ");
                 VL_DO_DANGLING(nodep->deleteTree(), nodep);
             }
         }
@@ -391,7 +391,7 @@ private:
             // Find range of dtype we are selecting from
             // Similar code in V3Const::warnSelect
             const int maxmsb = nodep->fromp()->dtypep()->width() - 1;
-            if (debug() >= 9) nodep->dumpTree(cout, "sel_old: ");
+            if (debug() >= 9) nodep->dumpTree("-  sel_old: ");
 
             // If (maxmsb >= selected), we're in bound
             AstNodeExpr* condp
@@ -413,7 +413,7 @@ private:
                 xnum.setAllBitsX();
                 AstNode* const newp = new AstCondBound{nodep->fileline(), condp, nodep,
                                                        new AstConst{nodep->fileline(), xnum}};
-                if (debug() >= 9) newp->dumpTree(cout, "        _new: ");
+                if (debug() >= 9) newp->dumpTree("-        _new: ");
                 // Link in conditional
                 replaceHandle.relink(newp);
                 // Added X's, tristate them too
@@ -430,7 +430,7 @@ private:
     void visit(AstArraySel* nodep) override {
         iterateChildren(nodep);
         if (!nodep->user1SetOnce()) {
-            if (debug() == 9) nodep->dumpTree(cout, "-in: ");
+            if (debug() == 9) nodep->dumpTree("-  in: ");
             // Guard against reading/writing past end of arrays
             AstNode* const basefromp = AstArraySel::baseFromp(nodep->fromp(), true);
             bool lvalue = false;
@@ -450,7 +450,7 @@ private:
             } else {
                 nodep->v3error("Select from non-array " << dtypep->prettyTypeName());
             }
-            if (debug() >= 9) nodep->dumpTree(cout, "arraysel_old: ");
+            if (debug() >= 9) nodep->dumpTree("-  arraysel_old: ");
 
             // See if the condition is constant true
             AstNodeExpr* condp
@@ -477,7 +477,7 @@ private:
                 }
                 AstNode* const newp = new AstCondBound{nodep->fileline(), condp, nodep,
                                                        new AstConst{nodep->fileline(), xnum}};
-                if (debug() >= 9) newp->dumpTree(cout, "        _new: ");
+                if (debug() >= 9) newp->dumpTree("-        _new: ");
                 // Link in conditional, can blow away temp xor
                 replaceHandle.relink(newp);
                 // Added X's, tristate them too
@@ -490,7 +490,7 @@ private:
                     bitp->fileline(), condp, bitp,
                     new AstConst{bitp->fileline(), AstConst::WidthedValue{}, bitp->width(), 0}};
                 // Added X's, tristate them too
-                if (debug() >= 9) newp->dumpTree(cout, "        _new: ");
+                if (debug() >= 9) newp->dumpTree("-        _new: ");
                 replaceHandle.relink(newp);
                 iterate(newp);
             } else {  // lvalue
diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp
index 73fbaaabc..23e4b3974 100644
--- a/src/V3Unroll.cpp
+++ b/src/V3Unroll.cpp
@@ -65,7 +65,7 @@ private:
         if (m_generate)
             nodep->v3warn(E_UNSUPPORTED, "Unsupported: Can't unroll generate for; " << reason);
         UINFO(3, "   Can't Unroll: " << reason << " :" << nodep << endl);
-        // if (debug() >= 9) nodep->dumpTree(cout, "-cant-");
+        // if (debug() >= 9) nodep->dumpTree("-  cant: ");
         V3Stats::addStatSum(std::string{"Unrolling gave up, "} + reason, 1);
         return false;
     }
@@ -151,7 +151,7 @@ private:
         } else {
             UINFO(8, "   Loop Variable: " << m_forVarp << endl);
         }
-        if (debug() >= 9) nodep->dumpTree(cout, "-   for: ");
+        if (debug() >= 9) nodep->dumpTree("-   for: ");
 
         if (!m_generate) {
             const AstAssign* const incpAssign = VN_AS(incp, Assign);
@@ -213,7 +213,7 @@ private:
         simvis.mainParamEmulate(clonep);
         if (!simvis.optimizable()) {
             UINFO(3, "Unable to simulate" << endl);
-            if (debug() >= 9) nodep->dumpTree(cout, "- _simtree: ");
+            if (debug() >= 9) nodep->dumpTree("-  _simtree: ");
             VL_DO_DANGLING(clonep->deleteTree(), clonep);
             return false;
         }
@@ -368,7 +368,7 @@ private:
         if (precondsp) VL_DO_DANGLING(pushDeletep(precondsp), precondsp);
         if (initp) VL_DO_DANGLING(pushDeletep(initp), initp);
         if (incp && !incp->backp()) VL_DO_DANGLING(pushDeletep(incp), incp);
-        if (debug() >= 9 && newbodysp) newbodysp->dumpTree(cout, "-  _new: ");
+        if (debug() >= 9 && newbodysp) newbodysp->dumpTree("-  _new: ");
         return true;
     }
 
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index fef048368..d5cf3d5f2 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -819,7 +819,7 @@ private:
         if (nodep->didWidth()) return;
         UASSERT_OBJ(m_vup, nodep, "Select under an unexpected context");
         if (m_vup->prelim()) {
-            if (debug() >= 9) nodep->dumpTree(cout, "-selWidth: ");
+            if (debug() >= 9) nodep->dumpTree("-  selWidth: ");
             userIterateAndNext(nodep->fromp(), WidthVP{CONTEXT_DET, PRELIM}.p());
             userIterateAndNext(nodep->lsbp(), WidthVP{SELF, PRELIM}.p());
             checkCvtUS(nodep->fromp());
@@ -1838,8 +1838,8 @@ private:
         UINFO(9, "CAST " << nodep << endl);
         nodep->dtypep(iterateEditMoveDTypep(nodep, nodep->subDTypep()));
         if (m_vup->prelim()) {
-            // if (debug()) nodep->dumpTree(cout, "  CastPre: ");
-            // if (debug()) nodep->backp()->dumpTree(cout, "  CastPreUpUp: ");
+            // if (debug()) nodep->dumpTree("-  CastPre: ");
+            // if (debug()) nodep->backp()->dumpTree("-  CastPreUpUp: ");
             userIterateAndNext(nodep->fromp(), WidthVP{SELF, PRELIM}.p());
             AstNodeDType* const toDtp = nodep->dtypep()->skipRefToEnump();
             AstNodeDType* const fromDtp = nodep->fromp()->dtypep()->skipRefToEnump();
@@ -1914,14 +1914,14 @@ private:
             }
             if (!newp) newp = nodep->fromp()->unlinkFrBack();
             nodep->fromp(newp);
-            // if (debug()) nodep->dumpTree(cout, "  CastOut: ");
-            // if (debug()) nodep->backp()->dumpTree(cout, "  CastOutUpUp: ");
+            // if (debug()) nodep->dumpTree("-  CastOut: ");
+            // if (debug()) nodep->backp()->dumpTree("-  CastOutUpUp: ");
         }
         if (m_vup->final()) {
             iterateCheck(nodep, "value", nodep->fromp(), SELF, FINAL, nodep->fromp()->dtypep(),
                          EXTEND_EXP, false);
             AstNode* const underp = nodep->fromp()->unlinkFrBack();
-            // if (debug()) underp->dumpTree(cout, "  CastRep: ");
+            // if (debug()) underp->dumpTree("-  CastRep: ");
             underp->dtypeFrom(nodep);
             nodep->replaceWith(underp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
@@ -1931,7 +1931,7 @@ private:
     void visit(AstCastSize* nodep) override {
         // IEEE: Signedness of result is same as self-determined signedness
         // However, the result is same as BITSEL, so we do not sign extend the LHS
-        // if (debug()) nodep->dumpTree(cout, "  CastSizePre: ");
+        // if (debug()) nodep->dumpTree("-  CastSizePre: ");
         if (m_vup->prelim()) {
             int width = nodep->rhsp()->toSInt();
             if (width < 1) {
@@ -1948,7 +1948,7 @@ private:
             nodep->replaceWith(underp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         }
-        // if (debug()) nodep->dumpTree(cout, "  CastSizeOut: ");
+        // if (debug()) nodep->dumpTree("-  CastSizeOut: ");
     }
     void castSized(AstNode* nodep, AstNode* underp, int width) {
         const AstBasicDType* underDtp = VN_CAST(underp->dtypep(), BasicDType);
@@ -1975,7 +1975,7 @@ private:
             VL_DANGLING(underp);
             underp = nodep->op1p();  // Above asserts that op1 was underp pre-relink
         }
-        // if (debug()) nodep->dumpTree(cout, "  CastSizeClc: ");
+        // if (debug()) nodep->dumpTree("-  CastSizeClc: ");
         // Next step, make the proper output width
         {
             AstNodeDType* const outDtp
@@ -1990,7 +1990,7 @@ private:
         }
     }
     void visit(AstVar* nodep) override {
-        // if (debug()) nodep->dumpTree(cout, "  InitPre: ");
+        // if (debug()) nodep->dumpTree("-  InitPre: ");
         // Must have deterministic constant width
         // We can't skip this step when width()!=0, as creating a AstVar
         // with non-constant range gets size 1, not size 0.  So use didWidth().
@@ -2091,13 +2091,13 @@ private:
             VL_DANGLING(bdtypep);
         }
         if (nodep->valuep() && !didchk) {
-            // if (debug()) nodep->dumpTree(cout, "  final: ");
+            // if (debug()) nodep->dumpTree("-  final: ");
             // AstPattern requires assignments to pass datatype on PRELIM
             userIterateAndNext(nodep->valuep(), WidthVP{nodep->dtypep(), PRELIM}.p());
             iterateCheckAssign(nodep, "Initial value", nodep->valuep(), FINAL, nodep->dtypep());
         }
         UINFO(4, "varWidthed " << nodep << endl);
-        // if (debug()) nodep->dumpTree(cout, "  InitOut: ");
+        // if (debug()) nodep->dumpTree("-  InitOut: ");
         nodep->didWidth(true);
         nodep->doingWidth(false);
     }
@@ -2118,14 +2118,14 @@ private:
             // Var hasn't been widthed, so make it so.
             userIterate(nodep->varp(), nullptr);
         }
-        // if (debug()>=9) { nodep->dumpTree(cout, "  VRin  ");
-        //  nodep->varp()->dumpTree(cout, " forvar "); }
+        // if (debug()>=9) { nodep->dumpTree("-  VRin:: ");
+        //  nodep->varp()->dumpTree("-  forvar: "); }
         // Note genvar's are also entered as integers
         nodep->dtypeFrom(nodep->varp());
         if (VN_IS(nodep->backp(), NodeAssign) && nodep->access().isWriteOrRW()) {  // On LHS
             UASSERT_OBJ(nodep->dtypep(), nodep, "LHS var should be dtype completed");
         }
-        // if (debug() >= 9) nodep->dumpTree(cout, "  VRout ");
+        // if (debug() >= 9) nodep->dumpTree("-  VRout: ");
         if (nodep->access().isWriteOrRW() && nodep->varp()->direction() == VDirection::CONSTREF) {
             nodep->v3error("Assigning to const ref variable: " << nodep->prettyNameQ());
         } else if (nodep->access().isWriteOrRW() && nodep->varp()->isConst() && !m_paramsOnly
@@ -2156,7 +2156,7 @@ private:
             if (itemp->valuep()) {
                 if (debug() >= 9) {
                     UINFO(0, "EnumInit " << itemp << endl);
-                    itemp->valuep()->dumpTree(cout, "-EnumInit: ");
+                    itemp->valuep()->dumpTree("-  EnumInit: ");
                 }
                 V3Const::constifyParamsEdit(itemp->valuep());  // itemp may change
                 if (!VN_IS(itemp->valuep(), Const)) {
@@ -2390,7 +2390,7 @@ private:
             iterateCheck(nodep, "Inside Item", itemp, CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP);
         }
         nodep->dtypeSetBit();
-        if (debug() >= 9) nodep->dumpTree(cout, "-inside-in: ");
+        if (debug() >= 9) nodep->dumpTree("-  inside-in: ");
         // Now rip out the inside and replace with simple math
         AstNodeExpr* newp = nullptr;
         for (AstNodeExpr *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) {
@@ -2423,7 +2423,7 @@ private:
             }
         }
         if (!newp) newp = new AstConst{nodep->fileline(), AstConst::BitFalse{}};
-        if (debug() >= 9) newp->dumpTree(cout, "-inside-out: ");
+        if (debug() >= 9) newp->dumpTree("-  inside-out: ");
         nodep->replaceWith(newp);
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
     }
@@ -2445,7 +2445,7 @@ private:
     void visit(AstNodeUOrStructDType* nodep) override {
         if (nodep->didWidthAndSet()) return;  // This node is a dtype & not both PRELIMed+FINALed
         UINFO(5, "   NODECLASS " << nodep << endl);
-        // if (debug() >= 9) nodep->dumpTree("-class-in--");
+        // if (debug() >= 9) nodep->dumpTree("-  class-in: ");
         if (!nodep->packed()) {
             nodep->v3warn(UNPACKED, "Unsupported: Unpacked struct/union");
             if (!v3Global.opt.structsPacked()) {
@@ -2475,7 +2475,7 @@ private:
             }
         }
         nodep->widthForce(width, width);  // Signing stays as-is, as parsed from declaration
-        // if (debug() >= 9) nodep->dumpTree("-class-out-");
+        // if (debug() >= 9) nodep->dumpTree("-  class-out: ");
     }
     void visit(AstClass* nodep) override {
         if (nodep->didWidthAndSet()) return;
@@ -2521,9 +2521,9 @@ private:
     }
     void visit(AstMemberSel* nodep) override {
         UINFO(5, "   MEMBERSEL " << nodep << endl);
-        if (debug() >= 9) nodep->dumpTree("-mbs-in: ");
+        if (debug() >= 9) nodep->dumpTree("-  mbs-in: ");
         userIterateChildren(nodep, WidthVP{SELF, BOTH}.p());
-        if (debug() >= 9) nodep->dumpTree("-mbs-ic: ");
+        if (debug() >= 9) nodep->dumpTree("-  mbs-ic: ");
         // Find the fromp dtype - should be a class
         if (!nodep->fromp()->dtypep()) nodep->fromp()->v3fatalSrc("Unlinked data type");
         AstNodeDType* const fromDtp = nodep->fromp()->dtypep()->skipRefToEnump();
@@ -2664,7 +2664,7 @@ private:
     void visit(AstMethodCall* nodep) override {
         UINFO(5, "   METHODCALL " << nodep << endl);
         if (nodep->didWidth()) return;
-        if (debug() >= 9) nodep->dumpTree("-mts-in: ");
+        if (debug() >= 9) nodep->dumpTree("-  mts-in: ");
         // Should check types the method requires, but at present we don't do much
         userIterate(nodep->fromp(), WidthVP{SELF, BOTH}.p());
         // Any AstWith is checked later when know types, in methodWithArgument
@@ -3879,7 +3879,7 @@ private:
         } else {
             nodep->v3error("Assignment pattern with no members");
         }
-        // if (debug() >= 9) newp->dumpTree("-apat-out: ");
+        // if (debug() >= 9) newp->dumpTree("-  apat-out: ");
         VL_DO_DANGLING(pushDeletep(nodep), nodep);  // Deletes defaultp also, if present
     }
     void patternAssoc(AstPattern* nodep, AstAssocArrayDType* arrayDtp, AstPatMember* defaultp) {
@@ -3898,7 +3898,7 @@ private:
             newp = newap;
         }
         nodep->replaceWith(newp);
-        // if (debug() >= 9) newp->dumpTree("-apat-out: ");
+        // if (debug() >= 9) newp->dumpTree("-  apat-out: ");
         VL_DO_DANGLING(pushDeletep(nodep), nodep);  // Deletes defaultp also, if present
     }
     void patternWildcard(AstPattern* nodep, AstWildcardArrayDType* arrayDtp,
@@ -3918,7 +3918,7 @@ private:
             newp = newap;
         }
         nodep->replaceWith(newp);
-        // if (debug() >= 9) newp->dumpTree("-apat-out: ");
+        // if (debug() >= 9) newp->dumpTree("-  apat-out: ");
         VL_DO_DANGLING(pushDeletep(nodep), nodep);  // Deletes defaultp also, if present
     }
     void patternDynArray(AstPattern* nodep, AstDynArrayDType* arrayp, AstPatMember*) {
@@ -3933,7 +3933,7 @@ private:
             newp = newap;
         }
         nodep->replaceWith(newp);
-        // if (debug() >= 9) newp->dumpTree("-apat-out: ");
+        // if (debug() >= 9) newp->dumpTree("-  apat-out: ");
         VL_DO_DANGLING(pushDeletep(nodep), nodep);  // Deletes defaultp also, if present
     }
     void patternQueue(AstPattern* nodep, AstQueueDType* arrayp, AstPatMember*) {
@@ -3948,7 +3948,7 @@ private:
             newp = newap;
         }
         nodep->replaceWith(newp);
-        // if (debug() >= 9) newp->dumpTree("-apat-out: ");
+        // if (debug() >= 9) newp->dumpTree("-  apat-out: ");
         VL_DO_DANGLING(pushDeletep(nodep), nodep);  // Deletes defaultp also, if present
     }
     void patternBasic(AstPattern* nodep, AstNodeDType* vdtypep, AstPatMember* defaultp) {
@@ -3997,7 +3997,7 @@ private:
         } else {
             nodep->v3error("Assignment pattern with no members");
         }
-        // if (debug() >= 9) newp->dumpTree("-apat-out: ");
+        // if (debug() >= 9) newp->dumpTree("-  apat-out: ");
         VL_DO_DANGLING(pushDeletep(nodep), nodep);  // Deletes defaultp also, if present
     }
     AstNodeExpr* patternMemberValueIterate(AstPatMember* patp) {
@@ -4153,13 +4153,13 @@ private:
     }
     void visit(AstNodeIf* nodep) override {
         assertAtStatement(nodep);
-        // if (debug()) nodep->dumpTree(cout, "  IfPre: ");
+        // if (debug()) nodep->dumpTree("-  IfPre: ");
         if (!VN_IS(nodep, GenIf)) {  // for m_paramsOnly
             userIterateAndNext(nodep->thensp(), nullptr);
             userIterateAndNext(nodep->elsesp(), nullptr);
         }
         iterateCheckBool(nodep, "If", nodep->condp(), BOTH);  // it's like an if() condition.
-        // if (debug()) nodep->dumpTree(cout, "  IfOut: ");
+        // if (debug()) nodep->dumpTree("-  IfOut: ");
     }
     void visit(AstExprStmt* nodep) override {
         userIterateAndNext(nodep->stmtsp(), nullptr);
@@ -4170,7 +4170,7 @@ private:
     void visit(AstForeach* nodep) override {
         const AstSelLoopVars* const loopsp = VN_CAST(nodep->arrayp(), SelLoopVars);
         UASSERT_OBJ(loopsp, nodep, "No loop variables under foreach");
-        // if (debug()) nodep->dumpTree(cout, "-foreach-old: ");
+        // if (debug()) nodep->dumpTree("-  foreach-old: ");
         userIterateAndNext(loopsp->fromp(), WidthVP{SELF, BOTH}.p());
         AstNodeExpr* const fromp = loopsp->fromp();
         UASSERT_OBJ(fromp->dtypep(), fromp, "Missing data type");
@@ -4308,7 +4308,7 @@ private:
         } else {
             lastBodyPointp->unlinkFrBack();
         }
-        // if (debug()) newp->dumpTreeAndNext(cout, "-foreach-new: ");
+        // if (debug()) newp->dumpTreeAndNext(cout, "-  foreach-new: ");
         nodep->replaceWith(newp);
         VL_DO_DANGLING(lastBodyPointp->deleteTree(), lastBodyPointp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
@@ -4352,9 +4352,9 @@ private:
         //       handled in each visitor.
         //    Then LHS sign-extends only if *RHS* is signed
         assertAtStatement(nodep);
-        // if (debug()) nodep->dumpTree(cout, "  AssignPre: ");
+        // if (debug()) nodep->dumpTree("-  AssignPre: ");
         {
-            // if (debug()) nodep->dumpTree(cout, "-    assin:  ");
+            // if (debug()) nodep->dumpTree("-    assin:: ");
             userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p());
             UASSERT_OBJ(nodep->lhsp()->dtypep(), nodep, "How can LHS be untyped?");
             UASSERT_OBJ(nodep->lhsp()->dtypep()->widthSized(), nodep, "How can LHS be unsized?");
@@ -4363,11 +4363,11 @@ private:
             // AstPattern needs to know the proposed data type of the lhs, so pass on the prelim
             userIterateAndNext(nodep->rhsp(), WidthVP{nodep->dtypep(), PRELIM}.p());
             //
-            // if (debug()) nodep->dumpTree(cout, "-    assign: ");
+            // if (debug()) nodep->dumpTree("-    assign: ");
             AstNodeDType* const lhsDTypep
                 = nodep->lhsp()->dtypep();  // Note we use rhsp for context determined
             iterateCheckAssign(nodep, "Assign RHS", nodep->rhsp(), FINAL, lhsDTypep);
-            // if (debug()) nodep->dumpTree(cout, "  AssignOut: ");
+            // if (debug()) nodep->dumpTree("-  AssignOut: ");
         }
         if (const AstBasicDType* const basicp = nodep->rhsp()->dtypep()->basicp()) {
             if (basicp->isEvent()) {
@@ -4797,7 +4797,7 @@ private:
         iterateCheckBool(nodep, "Property", nodep->propp(), BOTH);  // it's like an if() condition.
     }
     void visit(AstPin* nodep) override {
-        // if (debug()) nodep->dumpTree(cout, "-  PinPre: ");
+        // if (debug()) nodep->dumpTree("-  PinPre: ");
         // TOP LEVEL NODE
         if (nodep->modVarp() && nodep->modVarp()->isGParam()) {
             // Widthing handled as special init() case
@@ -4926,7 +4926,7 @@ private:
                 iterateCheckAssign(nodep, "pin connection", nodep->exprp(), FINAL, subDTypep);
             }
         }
-        // if (debug()) nodep->dumpTree(cout, "-  PinOut: ");
+        // if (debug()) nodep->dumpTree("-  PinOut: ");
     }
     void visit(AstCell* nodep) override {
         VL_RESTORER(m_cellp);
@@ -5066,7 +5066,7 @@ private:
     void visit(AstFuncRef* nodep) override {
         visit(static_cast<AstNodeFTaskRef*>(nodep));
         nodep->dtypeFrom(nodep->taskp());
-        // if (debug()) nodep->dumpTree(cout, "  FuncOut: ");
+        // if (debug()) nodep->dumpTree("-  FuncOut: ");
     }
     // Returns true if dtypep0 and dtypep1 have same dimensions
     static bool areSameSize(AstUnpackArrayDType* dtypep0, AstUnpackArrayDType* dtypep1) {
@@ -5726,7 +5726,7 @@ private:
         // because the rhs could be larger, and we need to have proper editing to get the widths
         // to be the same for our operations.
         //
-        // if (debug() >= 9) { UINFO(0,"-rus "<<m_vup<<endl); nodep->dumpTree(cout, "-rusin-"); }
+        // if (debug() >= 9) { UINFO(0,"rus "<<m_vup<<endl); nodep->dumpTree("-  rusin: "); }
         if (m_vup->prelim()) {  // First stage evaluation
             // Determine expression widths only relying on what's in the subops
             userIterateAndNext(nodep->lhsp(), WidthVP{CONTEXT_DET, PRELIM}.p());
@@ -5782,7 +5782,7 @@ private:
             iterateCheck(nodep, "RHS", nodep->rhsp(), CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP,
                          rhsWarn);
         }
-        // if (debug() >= 9) nodep->dumpTree(cout, "-rusou-");
+        // if (debug() >= 9) nodep->dumpTree("-  rusou: ");
     }
     void visit_real_add_sub(AstNodeBiop* nodep) {
         // CALLER: AddD, MulD, ...
@@ -5925,8 +5925,8 @@ private:
                 num.opRepl(constp->num(), expWidth);  // {width{'1}}
                 AstNodeExpr* const newp = new AstConst{constp->fileline(), num};
                 // Spec says always unsigned with proper width
-                if (debug() > 4) constp->dumpTree(cout, "  fixAutoExtend_old: ");
-                if (debug() > 4) newp->dumpTree(cout, "               _new: ");
+                if (debug() > 4) constp->dumpTree("-  fixAutoExtend_old: ");
+                if (debug() > 4) newp->dumpTree("-               _new: ");
                 constp->replaceWith(newp);
                 VL_DO_DANGLING(constp->deleteTree(), constp);
                 // Tell caller the new constp, and that we changed it.
@@ -5943,8 +5943,8 @@ private:
                 num.opExtendXZ(constp->num(), constp->width());
                 AstNodeExpr* const newp = new AstConst{constp->fileline(), num};
                 // Spec says always unsigned with proper width
-                if (debug() > 4) constp->dumpTree(cout, "  fixUnszExtend_old: ");
-                if (debug() > 4) newp->dumpTree(cout, "               _new: ");
+                if (debug() > 4) constp->dumpTree("-  fixUnszExtend_old: ");
+                if (debug() > 4) newp->dumpTree("-               _new: ");
                 constp->replaceWith(newp);
                 VL_DO_DANGLING(constp->deleteTree(), constp);
                 // Tell caller the new constp, and that we changed it.
@@ -6043,7 +6043,7 @@ private:
     void iterateCheckAssign(AstNode* nodep, const char* side, AstNode* rhsp, Stage stage,
                             AstNodeDType* lhsDTypep) {
         // Check using assignment-like context rules
-        // if (debug()) nodep->dumpTree(cout, "-checkass: ");
+        // if (debug()) nodep->dumpTree("-  checkass: ");
         UASSERT_OBJ(stage == FINAL, nodep, "Bad width call");
         // We iterate and size the RHS based on the result of RHS evaluation
         checkClassAssign(nodep, side, rhsp, lhsDTypep);
@@ -6051,7 +6051,7 @@ private:
             = (VN_IS(nodep, NodeAssign) && VN_IS(VN_AS(nodep, NodeAssign)->lhsp(), NodeStream));
         rhsp = iterateCheck(nodep, side, rhsp, ASSIGN, FINAL, lhsDTypep,
                             lhsStream ? EXTEND_OFF : EXTEND_LHS);
-        // if (debug()) nodep->dumpTree(cout, "-checkout: ");
+        // if (debug()) nodep->dumpTree("-  checkout: ");
         if (rhsp) {}  // cppcheck
     }
 
@@ -6092,7 +6092,7 @@ private:
             const bool bad = widthBad(underp, nodep->findBitDType());
             if (bad) {
                 {  // if (warnOn), but not needed here
-                    if (debug() > 4) nodep->backp()->dumpTree(cout, "  back: ");
+                    if (debug() > 4) nodep->backp()->dumpTree("-  back: ");
                     nodep->v3warn(WIDTH, "Logical operator "
                                              << nodep->prettyTypeName() << " expects 1 bit on the "
                                              << side << ", but " << side << "'s "
@@ -6157,7 +6157,7 @@ private:
                                           << " (IEEE 1800-2017 6.19.3)\n"
                                           << nodep->warnMore()
                                           << "... Suggest use enum's mnemonic, or static cast");
-                        if (debug()) nodep->backp()->dumpTree(cout, "- back: ");
+                        if (debug()) nodep->backp()->dumpTree("-  back: ");
                     }
                 }
                 AstNodeDType* subDTypep = expDTypep;
@@ -6273,7 +6273,7 @@ private:
                 warnOn = false;
             }
             if (bad && warnOn) {
-                if (debug() > 4) nodep->backp()->dumpTree(cout, "  back: ");
+                if (debug() > 4) nodep->backp()->dumpTree("-  back: ");
                 nodep->v3warn(
                     WIDTH, ucfirst(nodep->prettyOperatorName())
                                << " expects " << expWidth
diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h
index 39e1ad8c5..5b262b058 100644
--- a/src/V3WidthCommit.h
+++ b/src/V3WidthCommit.h
@@ -171,8 +171,8 @@ private:
             nodep->replaceWith(newp);
             AstNode* const oldp = nodep;
             nodep = newp;
-            // if (debug() > 4) oldp->dumpTree(cout, "  fixConstSize_old: ");
-            // if (debug() > 4) newp->dumpTree(cout, "              _new: ");
+            // if (debug() > 4) oldp->dumpTree("-  fixConstSize_old: ");
+            // if (debug() > 4) newp->dumpTree("-              _new: ");
             VL_DO_DANGLING(pushDeletep(oldp), oldp);
         }
         editDType(nodep);
diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp
index 07579768d..98437443b 100644
--- a/src/V3WidthSel.cpp
+++ b/src/V3WidthSel.cpp
@@ -204,11 +204,11 @@ private:
         // Select of a non-width specified part of an array, i.e. "array[2]"
         // This select style has a lsb and msb (no user specified width)
         UINFO(6, "SELBIT " << nodep << endl);
-        if (debug() >= 9) nodep->backp()->dumpTree(cout, "--SELBT0: ");
+        if (debug() >= 9) nodep->backp()->dumpTree("-  SELBT0: ");
         // lhsp/rhsp do not need to be constant
         AstNodeExpr* const fromp = nodep->fromp()->unlinkFrBack();
         AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();  // bit we're extracting
-        if (debug() >= 9) nodep->dumpTree(cout, "--SELBT2: ");
+        if (debug() >= 9) nodep->dumpTree("-  SELBT2: ");
         const FromData fromdata = fromDataForArray(nodep, fromp);
         AstNodeDType* const ddtypep = fromdata.m_dtypep;
         const VNumRange fromRange = fromdata.m_fromRange;
@@ -221,7 +221,7 @@ private:
             }
             AstArraySel* const newp = new AstArraySel{nodep->fileline(), fromp, subp};
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off array reference
-            if (debug() >= 9) newp->dumpTree(cout, "--SELBTn: ");
+            if (debug() >= 9) newp->dumpTree("-  SELBTn: ");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (const AstPackArrayDType* const adtypep = VN_CAST(ddtypep, PackArrayDType)) {
@@ -245,7 +245,7 @@ private:
             newp->declRange(fromRange);
             newp->declElWidth(elwidth);
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off array reference
-            if (debug() >= 9) newp->dumpTree(cout, "--SELBTn: ");
+            if (debug() >= 9) newp->dumpTree("-  SELBTn: ");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (const AstAssocArrayDType* const adtypep = VN_CAST(ddtypep, AssocArrayDType)) {
@@ -253,7 +253,7 @@ private:
             AstNodeExpr* const subp = rhsp;
             AstAssocSel* const newp = new AstAssocSel{nodep->fileline(), fromp, subp};
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off array reference
-            if (debug() >= 9) newp->dumpTree(cout, "--SELBTn: ");
+            if (debug() >= 9) newp->dumpTree("-  SELBTn: ");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (const AstWildcardArrayDType* const adtypep
@@ -262,7 +262,7 @@ private:
             AstNodeExpr* const subp = rhsp;
             AstWildcardSel* const newp = new AstWildcardSel{nodep->fileline(), fromp, subp};
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off array reference
-            if (debug() >= 9) newp->dumpTree(cout, "--SELBTn: ");
+            if (debug() >= 9) newp->dumpTree("-  SELBTn: ");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (const AstDynArrayDType* const adtypep = VN_CAST(ddtypep, DynArrayDType)) {
@@ -270,7 +270,7 @@ private:
             AstNodeExpr* const subp = rhsp;
             AstCMethodHard* const newp = new AstCMethodHard{nodep->fileline(), fromp, "at", subp};
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off queue reference
-            if (debug() >= 9) newp->dumpTree(cout, "--SELBTq: ");
+            if (debug() >= 9) newp->dumpTree("-  SELBTq: ");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (const AstQueueDType* const adtypep = VN_CAST(ddtypep, QueueDType)) {
@@ -278,7 +278,7 @@ private:
             AstNodeExpr* const subp = rhsp;
             AstCMethodHard* const newp = new AstCMethodHard{nodep->fileline(), fromp, "at", subp};
             newp->dtypeFrom(adtypep->subDTypep());  // Need to strip off queue reference
-            if (debug() >= 9) newp->dumpTree(cout, "--SELBTq: ");
+            if (debug() >= 9) newp->dumpTree("-  SELBTq: ");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (VN_IS(ddtypep, BasicDType) && ddtypep->isString()) {
@@ -305,7 +305,7 @@ private:
                              new AstConst{nodep->fileline(), AstConst::Unsized32{}, 1}};
             newp->declRange(fromRange);
             UINFO(6, "   new " << newp << endl);
-            if (debug() >= 9) newp->dumpTree(cout, "--SELBTn: ");
+            if (debug() >= 9) newp->dumpTree("-  SELBTn: ");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (VN_IS(ddtypep, NodeUOrStructDType)) {  // A bit from the packed struct
@@ -316,7 +316,7 @@ private:
                              new AstConst{nodep->fileline(), AstConst::Unsized32{}, 1}};
             newp->declRange(fromRange);
             UINFO(6, "   new " << newp << endl);
-            if (debug() >= 9) newp->dumpTree(cout, "--SELBTn: ");
+            if (debug() >= 9) newp->dumpTree("-  SELBTn: ");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else {  // nullptr=bad extract, or unknown node type
@@ -333,11 +333,11 @@ private:
         // SELEXTRACT(from,msb,lsb) -> SEL(from, lsb, 1+msb-lsb)
         // This select style has a (msb or lsb) and width
         UINFO(6, "SELEXTRACT " << nodep << endl);
-        // if (debug() >= 9) nodep->dumpTree(cout, "--SELEX0: ");
+        // if (debug() >= 9) nodep->dumpTree("-  SELEX0: ");
         // Below 2 lines may change nodep->widthp()
         V3Const::constifyParamsEdit(nodep->leftp());  // May relink pointed to node
         V3Const::constifyParamsEdit(nodep->rightp());  // May relink pointed to node
-        // if (debug() >= 9) nodep->dumpTree(cout, "--SELEX3: ");
+        // if (debug() >= 9) nodep->dumpTree("-  SELEX3: ");
         checkConstantOrReplace(nodep->leftp(),
                                "First value of [a:b] isn't a constant, maybe you want +: or -:");
         checkConstantOrReplace(nodep->rightp(),
@@ -400,7 +400,7 @@ private:
             newp->declRange(fromRange);
             newp->declElWidth(elwidth);
             newp->dtypeFrom(sliceDType(adtypep, msb, lsb));
-            // if (debug() >= 9) newp->dumpTree(cout, "--EXTBTn: ");
+            // if (debug() >= 9) newp->dumpTree("-  EXTBTn: ");
             UASSERT_OBJ(newp->widthMin() == newp->widthConst(), nodep, "Width mismatch");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
@@ -428,7 +428,7 @@ private:
                 = new AstSel{nodep->fileline(), fromp, newSubLsbOf(lsbp, fromRange), widthp};
             newp->declRange(fromRange);
             UINFO(6, "   new " << newp << endl);
-            // if (debug() >= 9) newp->dumpTree(cout, "--SELEXnew: ");
+            // if (debug() >= 9) newp->dumpTree("-  SELEXnew: ");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (VN_IS(ddtypep, NodeUOrStructDType)) {
@@ -450,7 +450,7 @@ private:
                 = new AstSel{nodep->fileline(), fromp, newSubLsbOf(lsbp, fromRange), widthp};
             newp->declRange(fromRange);
             UINFO(6, "   new " << newp << endl);
-            // if (debug() >= 9) newp->dumpTree(cout, "--SELEXnew: ");
+            // if (debug() >= 9) newp->dumpTree("-  SELEXnew: ");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else if (VN_IS(ddtypep, QueueDType)) {
@@ -481,12 +481,12 @@ private:
         // This select style has a lsb and width
         UINFO(6, "SELPLUS/MINUS " << nodep << endl);
         // Below 2 lines may change nodep->widthp()
-        if (debug() >= 9) nodep->dumpTree(cout, "--SELPM0: ");
+        if (debug() >= 9) nodep->dumpTree("-  SELPM0: ");
         V3Width::widthParamsEdit(nodep->rhsp());  // constifyEdit doesn't ensure widths finished
         V3Const::constifyEdit(nodep->rhsp());  // May relink pointed to node, ok if not const
         V3Const::constifyParamsEdit(nodep->thsp());  // May relink pointed to node
         checkConstantOrReplace(nodep->thsp(), "Width of :+ or :- bit extract isn't a constant");
-        if (debug() >= 9) nodep->dumpTree(cout, "--SELPM3: ");
+        if (debug() >= 9) nodep->dumpTree("-  SELPM3: ");
         // Now replace it with an AstSel
         AstNodeExpr* const fromp = nodep->fromp()->unlinkFrBack();
         AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack();
@@ -565,7 +565,7 @@ private:
             newp->declRange(fromRange);
             newp->declElWidth(elwidth);
             UINFO(6, "   new " << newp << endl);
-            if (debug() >= 9) newp->dumpTree(cout, "--SELNEW: ");
+            if (debug() >= 9) newp->dumpTree("-  SELNEW: ");
             nodep->replaceWith(newp);
             VL_DO_DANGLING(pushDeletep(nodep), nodep);
         } else {  // nullptr=bad extract, or unknown node type

From c303ba7f0a2048361095a6507a5a16f152d52b09 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 27 Nov 2022 08:32:34 -0500
Subject: [PATCH 097/156] Prefer std:: in examples

---
 examples/make_tracing_sc/sc_main.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/make_tracing_sc/sc_main.cpp b/examples/make_tracing_sc/sc_main.cpp
index a23040a54..223cce885 100644
--- a/examples/make_tracing_sc/sc_main.cpp
+++ b/examples/make_tracing_sc/sc_main.cpp
@@ -90,7 +90,7 @@ int sc_main(int argc, char* argv[]) {
     VerilatedVcdSc* tfp = nullptr;
     const char* flag = Verilated::commandArgsPlusMatch("trace");
     if (flag && 0 == std::strcmp(flag, "+trace")) {
-        cout << "Enabling waves into logs/vlt_dump.vcd...\n";
+        std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
         tfp = new VerilatedVcdSc;
         top->trace(tfp, 99);  // Trace 99 levels of hierarchy
         Verilated::mkdir("logs");

From 054b792021f7e256615724d00b7b74fbe9da9059 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 27 Nov 2022 08:44:30 -0500
Subject: [PATCH 098/156] Fix ENUMVALUE error to show value location (#3783)

---
 src/V3Width.cpp                    | 17 +++++++++--------
 test_regress/t/t_enum_type_bad.out | 18 +++++++++---------
 2 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index d5cf3d5f2..c99f2368e 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -6149,14 +6149,15 @@ private:
                     = VN_CAST(expDTypep->skipRefToEnump(), EnumDType)) {
                     const auto castable = computeCastable(expEnump, underp->dtypep(), underp);
                     if (castable != COMPATIBLE && castable != ENUM_IMPLICIT && !VN_IS(underp, Cast)
-                        && !VN_IS(underp, CastDynamic) && !m_enumItemp && warnOn) {
-                        nodep->v3warn(ENUMVALUE,
-                                      "Implicit conversion to enum "
-                                          << expDTypep->prettyDTypeNameQ() << " from "
-                                          << underp->dtypep()->prettyDTypeNameQ()
-                                          << " (IEEE 1800-2017 6.19.3)\n"
-                                          << nodep->warnMore()
-                                          << "... Suggest use enum's mnemonic, or static cast");
+                        && !VN_IS(underp, CastDynamic) && !m_enumItemp
+                        && !nodep->fileline()->warnIsOff(V3ErrorCode::ENUMVALUE) && warnOn) {
+                        underp->v3warn(ENUMVALUE,
+                                       "Implicit conversion to enum "
+                                           << expDTypep->prettyDTypeNameQ() << " from "
+                                           << underp->dtypep()->prettyDTypeNameQ()
+                                           << " (IEEE 1800-2017 6.19.3)\n"
+                                           << nodep->warnMore()
+                                           << "... Suggest use enum's mnemonic, or static cast");
                         if (debug()) nodep->backp()->dumpTree("-  back: ");
                     }
                 }
diff --git a/test_regress/t/t_enum_type_bad.out b/test_regress/t/t_enum_type_bad.out
index 2d782732e..59d5cb988 100644
--- a/test_regress/t/t_enum_type_bad.out
+++ b/test_regress/t/t_enum_type_bad.out
@@ -1,17 +1,17 @@
-%Error-ENUMVALUE: t/t_enum_type_bad.v:28:9: Implicit conversion to enum 't.e_t' from 'logic[31:0]' (IEEE 1800-2017 6.19.3)
-                                          : ... In instance t
+%Error-ENUMVALUE: t/t_enum_type_bad.v:28:11: Implicit conversion to enum 't.e_t' from 'logic[31:0]' (IEEE 1800-2017 6.19.3)
+                                           : ... In instance t
                                           : ... Suggest use enum's mnemonic, or static cast
    28 |       e = 1;   
-      |         ^
+      |           ^
                   ... For error description see https://verilator.org/warn/ENUMVALUE?v=latest
-%Error-ENUMVALUE: t/t_enum_type_bad.v:29:9: Implicit conversion to enum 't.o_t' from 't.e_t' (IEEE 1800-2017 6.19.3)
-                                          : ... In instance t
+%Error-ENUMVALUE: t/t_enum_type_bad.v:29:11: Implicit conversion to enum 't.o_t' from 't.e_t' (IEEE 1800-2017 6.19.3)
+                                           : ... In instance t
                                           : ... Suggest use enum's mnemonic, or static cast
    29 |       o = e;   
-      |         ^
-%Error-ENUMVALUE: t/t_enum_type_bad.v:35:9: Implicit conversion to enum 't.o_t' from 'ENUMDTYPE 't.e_t'' (IEEE 1800-2017 6.19.3)
-                                          : ... In instance t
+      |           ^
+%Error-ENUMVALUE: t/t_enum_type_bad.v:35:15: Implicit conversion to enum 't.o_t' from 'ENUMDTYPE 't.e_t'' (IEEE 1800-2017 6.19.3)
+                                           : ... In instance t
                                           : ... Suggest use enum's mnemonic, or static cast
    35 |       o = str.m_e;   
-      |         ^
+      |               ^~~
 %Error: Exiting due to

From f4be3d5d2b0827b7623fe1b899a2605d864d509a Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 27 Nov 2022 13:28:57 -0500
Subject: [PATCH 099/156] Fix empty string literals converting to string types
 (#3774).

---
 Changes                             |  1 +
 include/verilated.cpp               |  6 +--
 src/V3Number.cpp                    | 31 +++++------
 src/V3Width.cpp                     | 21 ++++----
 src/verilog.y                       | 11 +---
 test_regress/t/t_display.out        |  2 +-
 test_regress/t/t_string_dyn_num.out |  4 ++
 test_regress/t/t_string_dyn_num.pl  | 22 ++++++++
 test_regress/t/t_string_dyn_num.v   | 69 ++++++++++++++++++++++++
 test_regress/t/t_string_size.out    |  7 ++-
 test_regress/t/t_string_size.v      | 83 ++++++++++++++++++++++-------
 11 files changed, 194 insertions(+), 63 deletions(-)
 create mode 100644 test_regress/t/t_string_dyn_num.out
 create mode 100755 test_regress/t/t_string_dyn_num.pl
 create mode 100644 test_regress/t/t_string_dyn_num.v

diff --git a/Changes b/Changes
index 205064554..b1e03f214 100644
--- a/Changes
+++ b/Changes
@@ -27,6 +27,7 @@ Verilator 5.003 devel
 * Fix tracing parameters overridden with -G (#3723). [Iztok Jeras]
 * Fix wait 0.
 * Fix comparing ranged slices of unpacked arrays.
+* Fix empty string literals converting to string types (#3774). [miree]
 
 
 Verilator 5.002 2022-10-29
diff --git a/include/verilated.cpp b/include/verilated.cpp
index 25392fc72..c5ec3af73 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -1812,16 +1812,14 @@ std::string VL_CVT_PACK_STR_NW(int lwords, const WDataInP lwp) VL_MT_SAFE {
     char destout[VL_VALUE_STRING_MAX_CHARS + 1];
     const int obits = lwords * VL_EDATASIZE;
     int lsb = obits - 1;
-    bool start = true;
     char* destp = destout;
     size_t len = 0;
     for (; lsb >= 0; --lsb) {
         lsb = (lsb / 8) * 8;  // Next digit
         const IData charval = VL_BITRSHIFT_W(lwp, lsb) & 0xff;
-        if (!start || charval) {
-            *destp++ = (charval == 0) ? ' ' : charval;
+        if (charval) {
+            *destp++ = static_cast<char>(charval);
             ++len;
-            start = false;  // Drop leading 0s
         }
     }
     return std::string{destout, len};
diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index 63c0c381d..49081321a 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -100,15 +100,19 @@ void V3Number::v3errorEndFatal(const std::ostringstream& str) const VL_MT_SAFE {
 
 V3Number::V3Number(VerilogStringLiteral, AstNode* nodep, const string& str) {
     // Create a number using a verilog string as the value, thus 8 bits per character.
-    init(nodep, std::max<int>(str.length() * 8, 1));
-    m_data.m_fromString = true;
-    for (unsigned pos = 0; pos < str.length(); ++pos) {
-        const int topos = str.length() - 1 - pos;
-        ValueAndX& v = m_data.num()[topos / 4];
-        for (int bit = 0; bit < 8; ++bit) {
-            if (str[pos] & (1UL << bit)) { v.m_value |= (1UL << (bit + (topos % 4) * 8)); }
+    if (str.empty()) {  // IEEE 1800-2017 11.10.3 "" = "\000"
+        init(nodep, 8);
+    } else {
+        init(nodep, std::max<int>(str.length() * 8, 1));
+        for (unsigned pos = 0; pos < str.length(); ++pos) {
+            const int topos = str.length() - 1 - pos;
+            ValueAndX& v = m_data.num()[topos / 4];
+            for (int bit = 0; bit < 8; ++bit) {
+                if (str[pos] & (1UL << bit)) { v.m_value |= (1UL << (bit + (topos % 4) * 8)); }
+            }
         }
     }
+    m_data.m_fromString = true;
     opCleanThis(true);
 }
 
@@ -948,18 +952,15 @@ int64_t V3Number::toSQuad() const {
 
 string V3Number::toString() const {
     UASSERT(!isFourState(), "toString with 4-state " << *this);
-    // Spec says always drop leading zeros, this isn't quite right, we space pad.
+    // IEEE says \000 are removed
+    // If used to print a %s space padding is still required after call to here
     if (isString()) return m_data.str();
     int bit = width() - 1;
-    bool start = true;
-    while ((bit % 8) != 7) bit++;
-    string str;
+    while ((bit % 8) != 7) ++bit;
+    std::string str;
     for (; bit >= 0; bit -= 8) {
         const int v = bitsValue(bit - 7, 8);
-        if (!start || v) {
-            str += static_cast<char>((v == 0) ? ' ' : v);
-            start = false;  // Drop leading 0s
-        }
+        if (v) str += static_cast<char>(v);
     }
     return str;
 }
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index c99f2368e..3613b6ca3 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -374,7 +374,15 @@ private:
     void visit(AstRealToBits* nodep) override { visit_Ou64_Lr(nodep); }
 
     // Output integer, input string
-    void visit(AstLenN* nodep) override { visit_Os32_string(nodep); }
+    void visit(AstLenN* nodep) override {
+        // Widths: 32 bit out
+        UASSERT_OBJ(nodep->lhsp(), nodep, "For unary ops only!");
+        if (m_vup->prelim()) {
+            // See similar handling in visit_cmp_eq_gt where created
+            iterateCheckString(nodep, "LHS", nodep->lhsp(), BOTH);
+            nodep->dtypeSetSigned32();
+        }
+    }
     void visit(AstPutcN* nodep) override {
         // CALLER: str.putc()
         UASSERT_OBJ(nodep->rhsp() && nodep->thsp(), nodep, "For ternary ops only!");
@@ -5556,17 +5564,6 @@ private:
         }
     }
 
-    void visit_Os32_string(AstNodeUniop* nodep) {
-        // CALLER: LenN
-        // Widths: 32 bit out
-        UASSERT_OBJ(nodep->lhsp(), nodep, "For unary ops only!");
-        if (m_vup->prelim()) {
-            // See similar handling in visit_cmp_eq_gt where created
-            iterateCheckString(nodep, "LHS", nodep->lhsp(), BOTH);
-            nodep->dtypeSetSigned32();
-        }
-    }
-
     void visit_negate_not(AstNodeUniop* nodep, bool real_ok) {
         // CALLER: (real_ok=false) Not
         // CALLER: (real_ok=true) Negate - allow real numbers
diff --git a/src/verilog.y b/src/verilog.y
index ec818941d..61cb9e552 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -5363,15 +5363,8 @@ str<strp>:                      // yaSTRING but with \{escapes} need decoded
 
 strAsInt<nodeExprp>:
                 yaSTRING
-                        { if ($1->empty()) {
-                              // else "" is not representable as number as is width 0
-                              // TODO all strings should be represented this way
-                              // until V3Width converts as/if needed to a numerical constant
-                              $$ = new AstConst{$<fl>1, AstConst::String{}, GRAMMARP->deQuote($<fl>1, *$1)};
-                          } else {
-                              $$ = new AstConst{$<fl>1, AstConst::VerilogStringLiteral{}, GRAMMARP->deQuote($<fl>1, *$1)};
-                          }
-                        }
+                        { // Numeric context, so IEEE 1800-2017 11.10.3 "" is a "\000"
+                          $$ = new AstConst{$<fl>1, AstConst::VerilogStringLiteral{}, GRAMMARP->deQuote($<fl>1, *$1)}; }
         ;
 
 strAsIntIgnore<nodeExprp>:          // strAsInt, but never matches for when expr shouldn't parse strings
diff --git a/test_regress/t/t_display.out b/test_regress/t/t_display.out
index 0ecc886a1..3a8033e7d 100644
--- a/test_regress/t/t_display.out
+++ b/test_regress/t/t_display.out
@@ -65,7 +65,7 @@ hello, from a concatenated string.
 hello, from a concatenated format string [0].
 extra argument:                    0
                    0 : pre argument after
-empty: ><
+empty: > <
 [0] Embedded tab '	' and <#013> return
 [0] Embedded
 multiline
diff --git a/test_regress/t/t_string_dyn_num.out b/test_regress/t/t_string_dyn_num.out
new file mode 100644
index 000000000..81995b29b
--- /dev/null
+++ b/test_regress/t/t_string_dyn_num.out
@@ -0,0 +1,4 @@
+istr='    ' istr%0=' ' sstr=''
+istr='  A ' istr%0='A ' sstr='A'
+istr='B A ' istr%0='B A ' sstr='BA'
+*-* All Finished *-*
diff --git a/test_regress/t/t_string_dyn_num.pl b/test_regress/t/t_string_dyn_num.pl
new file mode 100755
index 000000000..a2660234f
--- /dev/null
+++ b/test_regress/t/t_string_dyn_num.pl
@@ -0,0 +1,22 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_string_dyn_num.v b/test_regress/t/t_string_dyn_num.v
new file mode 100644
index 000000000..639c578a1
--- /dev/null
+++ b/test_regress/t/t_string_dyn_num.v
@@ -0,0 +1,69 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// Use this file as a template for submitting bugs, etc.
+// This module takes a single clock input, and should either
+//      $write("*-* All Finished *-*\n");
+//      $finish;
+// on success, or $stop.
+//
+// The code as shown applies a random vector to the Test
+// module, then calculates a CRC on the Test module's outputs.
+//
+// **If you do not wish for your code to be released to the public
+// please note it here, otherwise:**
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer cyc = 0;
+
+   reg [31:0] istr;
+   string     sstr;
+   string     v;
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d istr='%s' sstr='%s'\n", $time, cyc, istr, sstr);
+`endif
+      cyc <= cyc + 1;
+      sstr <= string'(istr);  // Note takes another cycle
+      if (cyc < 10) begin
+         istr <= 32'h00_00_00_00;
+      end
+      else if (cyc == 13) begin
+         // These displays are needed to check padding of %s
+         $display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr);
+         if (sstr.len() != 0) $stop;
+         if (sstr != "") $stop;
+      end
+      else if (cyc == 20) begin
+         istr <= 32'h00_00_41_00;
+      end
+      else if (cyc == 23) begin
+         $display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr);
+         if (sstr.len() != 1) $stop;
+         if (sstr != "A") $stop;
+      end
+      else if (cyc == 30) begin
+         istr <= 32'h42_00_41_00;
+      end
+      else if (cyc == 33) begin
+         $display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr);
+         if (sstr.len() != 2) $stop;
+         if (sstr != "BA") $stop;
+      end
+      else if (cyc == 99) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+   end
+
+endmodule
diff --git a/test_regress/t/t_string_size.out b/test_regress/t/t_string_size.out
index cd674d097..e3d341a1a 100644
--- a/test_regress/t/t_string_size.out
+++ b/test_regress/t/t_string_size.out
@@ -1,4 +1,7 @@
+> < == >< (or > < also legal)
+> < == >< (or > < also legal)
+>    < == >    <
+>   < == >   <
+>        < == >        <
 >< == ><
->< == ><
-> < == > <
 *-* All Finished *-*
diff --git a/test_regress/t/t_string_size.v b/test_regress/t/t_string_size.v
index b18b92137..26949ef3d 100644
--- a/test_regress/t/t_string_size.v
+++ b/test_regress/t/t_string_size.v
@@ -4,41 +4,84 @@
 // any use, without warranty, 2021 by wilson Snyder.
 // SPDX-License-Identifier: CC0-1.0
 
-module t;
-   parameter string ES = "";
-   parameter EI = "";  // B is an integer of width 8
+module t(/*AUTOARG*/
+   // Outputs
+   outempty64
+   );
+   output [63:0] outempty64;
+
    parameter string OS = "O";
    parameter OI = "O";  // B is an integer of width 8
 
+   // verilator lint_off WIDTH
+   parameter string EMPTYS = "";
+   parameter EMPTYI = "";  // B is an integer of width 8
+   parameter bit [23:0] EMPTY24 = "";
+   parameter bit [63:0] EMPTY64 = "";
+   // verilator lint_on WIDTH
    parameter bit [31:0] NEST = "NEST";
    parameter bit [31:0] TEST = "TEST";
-   bit [31:0] rest;
    string s;
 
+   // verilator lint_off WIDTH
+   assign outempty64 = "";
+   // verilator lint_on WIDTH
+
    initial begin
-      $display(">< == >%s<", "");
-      $display(">< == >%s<", ES);
-      $display("> < == >%s<", EI);
+      // IEEE: "Leading 0s are never printed" but that does not mean spaces are not
+      $display(">%s< == >< (or > < also legal)", "\000");
+      $display(">%s< == >< (or > < also legal)", "");
+      $display(">%s< == >    <", 32'h0);
+
+      // Numeric context, so IEEE 1800-2017 11.10.3 "" is a "\000"
+      if ($bits("") != 8) $stop;
+      if ("" != "\000") $stop;
 
-      if ($bits("") != 0) $stop;
       if ($bits("A") != 8) $stop;
-      if ($bits(ES) != 0) $stop;
-      if ($bits(EI) != 8) $stop;
-      if ($bits(OS) != 8) $stop;
-      if ($bits(OI) != 8) $stop;
 
-      if (ES == "TEST") $stop;  // Illegal in some simulators as not both strings
-      if (EI == "TEST") $stop;
+      s = "";
+      if (s.len != 0) $stop;
+
+      // IEEE 1800-2017 6.16 "\000" assigned to string is ignored
+      s = "\000yo\000";
+      if (s.len != 2) $stop;
+      if (s != "yo") $stop;
+
+      if ($bits(EMPTYI) != 8) $stop;
+      if (EMPTYI != "\000") $stop;
+      // verilator lint_off WIDTH
+      if (EMPTYI == "TEST") $stop;
+      if (EMPTYI == TEST) $stop;
+      // verilator lint_on WIDTH
+
+      if ($bits(EMPTY24) != 24) $stop;
+      if (EMPTY24 != 0) $stop;
+      $display(">%s< == >   <", EMPTY24);
+
+      if ($bits(EMPTY64) != 64) $stop;
+      if (EMPTY64 != 0) $stop;
+      $display(">%s< == >        <", EMPTY64);
+
+      if ($bits(EMPTYS) != 0) $stop;
+      if (EMPTYS == "TEST") $stop;  // Illegal in some simulators as not both strings
+      if (EMPTYS == TEST) $stop;
+      $display(">%s< == ><", EMPTYS);
+
+      if ($bits(OS) != 8) $stop;
+      if (OS != "O") $stop;
       if (OS == "TEST") $stop;  // Illegal in some simulators as not both strings
+      if (OS == TEST) $stop;
+
+      if ($bits(OI) != 8) $stop;
+      if (OI != "O") $stop;
+
       // verilator lint_off WIDTH
       if (OI == "TEST") $stop;
-      if (rest == "TEST") $stop;
-
-      if (ES == TEST) $stop;
-      if (EI == TEST) $stop;
-      if (OS == TEST) $stop;
       if (OI == TEST) $stop;
-      if (rest == TEST) $stop;
+      // verilator lint_on WIDTH
+
+      if ($bits(outempty64) != 64) $stop;
+      if (outempty64 != 64'h00_00_00_00_00_00_00_00) $stop;
 
       $write("*-* All Finished *-*\n");
       $finish;

From 6349e76abd9a73220fafd70e343d52a0a9408107 Mon Sep 17 00:00:00 2001
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Sun, 27 Nov 2022 17:24:22 -0800
Subject: [PATCH 100/156] Remove $date from .vcd files (#3779)

---
 include/verilated_vcd_c.cpp | 19 +++++++------------
 include/verilatedos.h       |  6 ------
 2 files changed, 7 insertions(+), 18 deletions(-)

diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp
index 69e7b0654..66ccea3ba 100644
--- a/include/verilated_vcd_c.cpp
+++ b/include/verilated_vcd_c.cpp
@@ -29,7 +29,6 @@
 
 #include <algorithm>
 #include <cerrno>
-#include <ctime>
 #include <fcntl.h>
 
 #if defined(_WIN32) && !defined(__MINGW32__) && !defined(__CYGWIN__)
@@ -362,17 +361,13 @@ void VerilatedVcd::printIndent(int level_change) {
 
 void VerilatedVcd::dumpHeader() {
     printStr("$version Generated by VerilatedVcd $end\n");
-    printStr("$date ");
-    {
-        const time_t tick = time(nullptr);
-        tm ticktm;
-        VL_LOCALTIME_R(&tick, &ticktm);
-        constexpr size_t LEN_BUF = 50;
-        char buf[LEN_BUF];
-        std::strftime(buf, LEN_BUF, "%c", &ticktm);
-        printStr(buf);
-    }
-    printStr(" $end\n");
+
+    // Verilator used to put in a $date here.  Although $date is shown in
+    // IEEE examples, and it is common in VCD writers, VCD readers don't
+    // seem to care about it.  Thus, we omit the $date so artifacts are
+    // more likely to be reproducible.  If use cases show up that require
+    // the $date command to be present, it could be re-added with support
+    // for the SOURCE_DATE_EPOCH hook.
 
     printStr("$timescale ");
     printStr(timeResStr().c_str());  // lintok-begin-on-ref
diff --git a/include/verilatedos.h b/include/verilatedos.h
index eff312137..5d6f220a5 100644
--- a/include/verilatedos.h
+++ b/include/verilatedos.h
@@ -502,12 +502,6 @@ using ssize_t = uint32_t;  ///< signed size_t; returned from read()
 # define VL_STRCASECMP strcasecmp
 #endif
 
-#if defined(__MINGW32__) || defined(_MSC_VER)
-# define VL_LOCALTIME_R(timep, tmp) localtime_s((tmp), (timep))
-#else
-# define VL_LOCALTIME_R(timep, tmp) localtime_r((timep), (tmp))
-#endif
-
 //=========================================================================
 // Macros controlling target specific optimizations
 

From 4452a9b10f02052cf230d115e4a6fd874eec0b2f Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 28 Nov 2022 07:08:34 -0500
Subject: [PATCH 101/156] Internals: Fix some VL_MT metacomments.

---
 include/verilated.cpp     |  2 +-
 include/verilated.h       | 14 +++++++-------
 include/verilated_cov.h   |  2 +-
 include/verilated_funcs.h |  8 ++++----
 include/verilated_imp.h   |  2 +-
 5 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/include/verilated.cpp b/include/verilated.cpp
index c5ec3af73..17ee99aa9 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -279,7 +279,7 @@ void VL_PRINTF_MT(const char* formatp, ...) VL_MT_SAFE {
 //===========================================================================
 // Random -- Mostly called at init time, so not inline.
 
-static uint32_t vl_sys_rand32() VL_MT_UNSAFE {
+static uint32_t vl_sys_rand32() VL_MT_SAFE {
     // Return random 32-bits using system library.
     // Used only to construct seed for Verilator's PNRG.
     static VerilatedMutex s_mutex;
diff --git a/include/verilated.h b/include/verilated.h
index 09a8c8670..9aee9cfad 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -275,7 +275,7 @@ private:
 public:
     explicit VerilatedModule(const char* namep);  // Create module with given hierarchy name
     ~VerilatedModule();
-    const char* name() const { return m_namep; }  ///< Return name of module
+    const char* name() const VL_MT_SAFE_POSTINIT { return m_namep; }  ///< Return name of module
 };
 
 //=========================================================================
@@ -533,8 +533,8 @@ public:
     // METHODS - public but for internal use only
 
     // Internal: access to implementation class
-    VerilatedContextImp* impp() { return reinterpret_cast<VerilatedContextImp*>(this); }
-    const VerilatedContextImp* impp() const {
+    VerilatedContextImp* impp() VL_MT_SAFE { return reinterpret_cast<VerilatedContextImp*>(this); }
+    const VerilatedContextImp* impp() const VL_MT_SAFE {
         return reinterpret_cast<const VerilatedContextImp*>(this);
     }
 
@@ -617,10 +617,10 @@ public:  // But internals only - called from VerilatedModule's
     void varInsert(int finalize, const char* namep, void* datap, bool isParam,
                    VerilatedVarType vltype, int vlflags, int dims, ...) VL_MT_UNSAFE;
     // ACCESSORS
-    const char* name() const { return m_namep; }
-    const char* identifier() const { return m_identifierp; }
-    int8_t timeunit() const { return m_timeunit; }
-    VerilatedSyms* symsp() const { return m_symsp; }
+    const char* name() const VL_MT_SAFE_POSTINIT { return m_namep; }
+    const char* identifier() const VL_MT_SAFE_POSTINIT { return m_identifierp; }
+    int8_t timeunit() const VL_MT_SAFE_POSTINIT { return m_timeunit; }
+    VerilatedSyms* symsp() const VL_MT_SAFE_POSTINIT { return m_symsp; }
     VerilatedVar* varFind(const char* namep) const VL_MT_SAFE_POSTINIT;
     VerilatedVarNameMap* varsp() const VL_MT_SAFE_POSTINIT { return m_varsp; }
     void scopeDump() const;
diff --git a/include/verilated_cov.h b/include/verilated_cov.h
index 4697c4f88..01240f60f 100644
--- a/include/verilated_cov.h
+++ b/include/verilated_cov.h
@@ -152,7 +152,7 @@ protected:
 
     // METHODS
     // Internal: access to implementation class
-    VerilatedCovImp* impp() { return reinterpret_cast<VerilatedCovImp*>(this); }
+    VerilatedCovImp* impp() VL_MT_SAFE { return reinterpret_cast<VerilatedCovImp*>(this); }
 };
 
 //=============================================================================
diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h
index 605580cbb..c3db7c7a6 100644
--- a/include/verilated_funcs.h
+++ b/include/verilated_funcs.h
@@ -259,20 +259,20 @@ extern void _vl_debug_print_w(int lbits, WDataInP const iwp);
 #if defined(SYSTEMC_VERSION)
 /// Return current simulation time
 // Already defined: extern sc_time sc_time_stamp();
-inline uint64_t vl_time_stamp64() { return sc_time_stamp().value(); }
+inline uint64_t vl_time_stamp64() VL_MT_SAFE { return sc_time_stamp().value(); }
 #else  // Non-SystemC
 # if !defined(VL_TIME_CONTEXT) && !defined(VL_NO_LEGACY)
 #  ifdef VL_TIME_STAMP64
 // vl_time_stamp64() may be optionally defined by the user to return time.
 // On MSVC++ weak symbols are not supported so must be declared, or define
 // VL_TIME_CONTEXT.
-extern uint64_t vl_time_stamp64() VL_ATTR_WEAK;
+extern uint64_t vl_time_stamp64() VL_ATTR_WEAK VL_MT_SAFE;
 #  else
 // sc_time_stamp() may be optionally defined by the user to return time.
 // On MSVC++ weak symbols are not supported so must be declared, or define
 // VL_TIME_CONTEXT.
-extern double sc_time_stamp() VL_ATTR_WEAK;  // Verilator 4.032 and newer
-inline uint64_t vl_time_stamp64() {
+extern double sc_time_stamp() VL_ATTR_WEAK VL_MT_SAFE;  // Verilator 4.032 and newer
+inline uint64_t vl_time_stamp64() VL_MT_SAFE {
     // clang9.0.1 requires & although we really do want the weak symbol value
     // cppcheck-suppress duplicateValueTernary
     return VL_LIKELY(&sc_time_stamp) ? static_cast<uint64_t>(sc_time_stamp()) : 0;
diff --git a/include/verilated_imp.h b/include/verilated_imp.h
index 0d6c907b7..5684da3c5 100644
--- a/include/verilated_imp.h
+++ b/include/verilated_imp.h
@@ -226,7 +226,7 @@ class VerilatedContextImp final : VerilatedContext {
         // Number incrementing on each reseed, 0=illegal
         int s_randSeedEpoch = 1;  // Reads ok, wish had a VL_WRITE_GUARDED_BY(s_randMutex)
     };
-    static Statics& s() {
+    static Statics& s() VL_MT_SAFE {
         static Statics s_s;
         return s_s;
     }

From 68e1b473e2f85bb50e852aaaf24445ac5c6ed8ad Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Mon, 28 Nov 2022 16:53:55 +0100
Subject: [PATCH 102/156] Support `std::semaphore` and typed `std::mailbox`
 (#3708)

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 include/std.sv                                | 106 ++++++++++++++++++
 src/V3AstNodeOther.h                          |   3 +
 src/V3Global.cpp                              |   7 ++
 src/V3Global.h                                |   3 +
 src/V3LinkParse.cpp                           |  11 +-
 src/V3Options.cpp                             |   2 +
 src/V3Options.h                               |   1 +
 src/V3ParseImp.cpp                            |  10 +-
 src/V3ParseImp.h                              |   1 +
 src/V3Width.cpp                               |  30 +++++
 src/verilog.y                                 |   7 ++
 test_regress/t/t_mailbox.out                  |   6 -
 test_regress/t/t_mailbox.pl                   |  19 ++--
 test_regress/t/t_mailbox.v                    |   1 +
 test_regress/t/t_mailbox_bad.out              |  11 +-
 test_regress/t/t_mailbox_std.out              |   6 -
 test_regress/t/t_mailbox_std.pl               |  22 ++--
 test_regress/t/t_notiming.out                 |  16 +++
 test_regress/t/t_notiming.v                   |  10 ++
 test_regress/t/t_semaphore.out                |   7 --
 test_regress/t/t_semaphore.pl                 |  19 ++--
 test_regress/t/t_semaphore.v                  |   2 +-
 test_regress/t/t_semaphore_bad.out            |   7 +-
 test_regress/t/t_semaphore_std.out            |   7 --
 test_regress/t/t_semaphore_std.pl             |  22 ++--
 test_regress/t/t_std_identifier.out           |   5 +
 ...semaphore_parse.pl => t_std_identifier.pl} |  13 ++-
 test_regress/t/t_std_identifier.v             |  17 +++
 test_regress/t/t_std_pkg_bad.out              |   4 +
 .../{t_mailbox_parse.pl => t_std_pkg_bad.pl}  |   9 +-
 test_regress/t/t_std_pkg_bad.v                |  11 ++
 test_regress/t/t_timing_unset1.out            |  16 +++
 32 files changed, 329 insertions(+), 82 deletions(-)
 create mode 100644 include/std.sv
 delete mode 100644 test_regress/t/t_mailbox.out
 delete mode 100644 test_regress/t/t_mailbox_std.out
 delete mode 100644 test_regress/t/t_semaphore.out
 delete mode 100644 test_regress/t/t_semaphore_std.out
 create mode 100644 test_regress/t/t_std_identifier.out
 rename test_regress/t/{t_semaphore_parse.pl => t_std_identifier.pl} (65%)
 create mode 100644 test_regress/t/t_std_identifier.v
 create mode 100644 test_regress/t/t_std_pkg_bad.out
 rename test_regress/t/{t_mailbox_parse.pl => t_std_pkg_bad.pl} (71%)
 create mode 100644 test_regress/t/t_std_pkg_bad.v

diff --git a/include/std.sv b/include/std.sv
new file mode 100644
index 000000000..7b27bc98b
--- /dev/null
+++ b/include/std.sv
@@ -0,0 +1,106 @@
+// DESCRIPTION: Verilator: built-in packages and classes
+//
+// Code available from: https://verilator.org
+//
+//*************************************************************************
+//
+// Copyright 2022 by Wilson Snyder. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU Lesser
+// General Public License Version 3 or the Perl Artistic License Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+//
+//*************************************************************************
+
+// verilator lint_off DECLFILENAME
+// verilator lint_off TIMESCALEMOD
+// verilator lint_off UNUSEDSIGNAL
+package std;
+    class mailbox #(type T);
+        protected int m_bound;
+        protected T m_queue[$];
+
+        function new(int bound = 0);
+            m_bound = bound;
+        endfunction
+
+        function int num();
+            return m_queue.size();
+        endfunction
+
+        task put(T message);
+    `ifdef VERILATOR_TIMING
+            if (m_bound != 0)
+                wait (m_queue.size() < m_bound);
+            m_queue.push_back(message);
+    `endif
+        endtask
+
+        function int try_put(T message);
+            if (num() < m_bound) begin
+                m_queue.push_back(message);
+                return 1;
+            end
+            return 0;
+        endfunction
+
+        task get(ref T message);
+    `ifdef VERILATOR_TIMING
+            wait (m_queue.size() > 0);
+            message = m_queue.pop_front();
+    `endif
+        endtask
+
+        function int try_get(ref T message);
+            if (num() > 0) begin
+                message = m_queue.pop_front();
+                return 1;
+            end
+            return 0;
+        endfunction
+
+        task peek(ref T message);
+    `ifdef VERILATOR_TIMING
+            wait (m_queue.size() > 0);
+            message = m_queue[0];
+    `endif
+        endtask
+
+        function int try_peek(ref T message);
+            if (num() > 0) begin
+                message = m_queue[0];
+                return 1;
+            end
+            return 0;
+        endfunction
+    endclass
+
+    class semaphore;
+        protected int m_keyCount;
+
+        function new(int keyCount = 0);
+            m_keyCount = keyCount;
+        endfunction
+
+        function void put(int keyCount = 1);
+            m_keyCount += keyCount;
+        endfunction
+
+        task get(int keyCount = 1);
+    `ifdef VERILATOR_TIMING
+            wait (m_keyCount >= keyCount);
+            m_keyCount -= keyCount;
+    `endif
+        endtask
+
+        function int try_get(int keyCount = 1);
+            if (m_keyCount >= keyCount) begin
+                m_keyCount -= keyCount;
+                return 1;
+            end
+            return 0;
+        endfunction
+    endclass
+endpackage
+
+// verilator lint_off IMPORTSTAR
+import std::*;
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index 6b816d971..a3ae3b246 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -1086,6 +1086,7 @@ class AstNetlist final : public AstNode {
     AstTypeTable* const m_typeTablep;  // Reference to top type table, for faster lookup
     AstConstPool* const m_constPoolp;  // Reference to constant pool, for faster lookup
     AstPackage* m_dollarUnitPkgp = nullptr;  // $unit
+    AstPackage* m_stdPackagep = nullptr;  // SystemVerilog std package
     AstCFunc* m_evalp = nullptr;  // The '_eval' function
     AstCFunc* m_evalNbap = nullptr;  // The '_eval__nba' function
     AstVarScope* m_dpiExportTriggerp = nullptr;  // The DPI export trigger variable
@@ -1119,6 +1120,8 @@ public:
     void dpiExportTriggerp(AstVarScope* varScopep) { m_dpiExportTriggerp = varScopep; }
     AstVar* delaySchedulerp() const { return m_delaySchedulerp; }
     void delaySchedulerp(AstVar* const varScopep) { m_delaySchedulerp = varScopep; }
+    void stdPackagep(AstPackage* const packagep) { m_stdPackagep = packagep; }
+    AstPackage* stdPackagep() const { return m_stdPackagep; }
     AstTopScope* topScopep() const { return m_topScopep; }
     void createTopScope(AstScope* scopep);
     VTimescale timeunit() const { return m_timeunit; }
diff --git a/src/V3Global.cpp b/src/V3Global.cpp
index dd9ec4ac5..20daa8177 100644
--- a/src/V3Global.cpp
+++ b/src/V3Global.cpp
@@ -63,6 +63,13 @@ void V3Global::readFiles() {
                          "Cannot find file containing module: ");
     }
 
+    if (usesStdPackage()) {
+        // Parse the std package
+        parser.parseFile(new FileLine{FileLine::commandLineFilename()},
+                         V3Options::getStdPackagePath(), false,
+                         "Cannot find std.sv containing built-in std:: definitions: ");
+    }
+
     // Read libraries
     // To be compatible with other simulators,
     // this needs to be done after the top file is read
diff --git a/src/V3Global.h b/src/V3Global.h
index 7108f4148..6c8f8dc86 100644
--- a/src/V3Global.h
+++ b/src/V3Global.h
@@ -107,6 +107,7 @@ class V3Global final {
     bool m_dpi = false;  // Need __Dpi include files
     bool m_hasEvents = false;  // Design uses SystemVerilog named events
     bool m_hasClasses = false;  // Design uses SystemVerilog classes
+    bool m_usesStdPackage = false;  // Design uses the std package
     bool m_usesTiming = false;  // Design uses timing constructs
     bool m_hasForceableSignals = false;  // Need to apply V3Force pass
     bool m_hasSCTextSections = false;  // Has `systemc_* sections that need to be emitted
@@ -152,6 +153,8 @@ public:
     void setHasEvents() { m_hasEvents = true; }
     bool hasClasses() const { return m_hasClasses; }
     void setHasClasses() { m_hasClasses = true; }
+    bool usesStdPackage() const { return m_usesStdPackage; }
+    void setUsesStdPackage() { m_usesStdPackage = true; }
     bool usesTiming() const { return m_usesTiming; }
     void setUsesTiming() { m_usesTiming = true; }
     bool hasForceableSignals() const { return m_hasForceableSignals; }
diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index 127d472a3..5d844725c 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -50,6 +50,7 @@ private:
     using ImplTypedefMap = std::map<const std::pair<void*, std::string>, AstTypedef*>;
 
     // STATE
+    AstPackage* const m_stdPackagep;  // SystemVerilog std package
     AstVar* m_varp = nullptr;  // Variable we're under
     ImplTypedefMap m_implTypedef;  // Created typedefs for each <container,name>
     std::unordered_set<FileLine*> m_filelines;  // Filelines that have been seen
@@ -600,6 +601,11 @@ private:
             VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep);
         }
     }
+    void visit(AstClassOrPackageRef* nodep) override {
+        if (nodep->name() == "std" && !nodep->classOrPackagep()) {
+            nodep->classOrPackagep(m_stdPackagep);
+        }
+    }
 
     void visit(AstNode* nodep) override {
         // Default: Just iterate
@@ -609,7 +615,10 @@ private:
 
 public:
     // CONSTRUCTORS
-    explicit LinkParseVisitor(AstNetlist* rootp) { iterate(rootp); }
+    explicit LinkParseVisitor(AstNetlist* rootp)
+        : m_stdPackagep{rootp->stdPackagep()} {
+        iterate(rootp);
+    }
     ~LinkParseVisitor() override = default;
 };
 
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index a345cd810..4f14b672e 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -706,6 +706,8 @@ string V3Options::getenvVERILATOR_ROOT() {
     return var;
 }
 
+string V3Options::getStdPackagePath() { return getenvVERILATOR_ROOT() + "/include/std.sv"; }
+
 string V3Options::getSupported(const string& var) {
     // If update below, also update V3Options::showVersion()
     if (var == "COROUTINES" && coroutineSupport()) {
diff --git a/src/V3Options.h b/src/V3Options.h
index 1dcb95edf..6fd2e8ac7 100644
--- a/src/V3Options.h
+++ b/src/V3Options.h
@@ -666,6 +666,7 @@ public:
     static string getenvSYSTEMC_INCLUDE();
     static string getenvSYSTEMC_LIBDIR();
     static string getenvVERILATOR_ROOT();
+    static string getStdPackagePath();
     static string getSupported(const string& var);
     static bool systemCSystemWide();
     static bool systemCFound();  // SystemC installed, or environment points to it
diff --git a/src/V3ParseImp.cpp b/src/V3ParseImp.cpp
index c73b6b64c..e6f1705ca 100644
--- a/src/V3ParseImp.cpp
+++ b/src/V3ParseImp.cpp
@@ -532,14 +532,17 @@ void V3ParseImp::tokenPipelineSym() {
                    && (*(yylval.strp) == "mailbox"  // IEEE-standard class
                        || *(yylval.strp) == "process"  // IEEE-standard class
                        || *(yylval.strp) == "semaphore")) {  // IEEE-standard class
+            v3Global.setUsesStdPackage();
             yylval.scp = nullptr;
             if (token == yaID__LEX) token = yaID__aTYPE;
         } else {  // Not found
             yylval.scp = nullptr;
             if (token == yaID__CC) {
-                // IEEE does require this, but we may relax this as UVM breaks it, so allow bbox
-                // for today
-                if (!v3Global.opt.bboxUnsup()) {
+                if (!m_afterColonColon && *(yylval.strp) == "std") {
+                    v3Global.setUsesStdPackage();
+                } else if (!v3Global.opt.bboxUnsup()) {
+                    // IEEE does require this, but we may relax this as UVM breaks it, so allow
+                    // bbox for today
                     // We'll get a parser error eventually but might not be obvious
                     // is missing package, and this confuses people
                     static int warned = false;
@@ -554,6 +557,7 @@ void V3ParseImp::tokenPipelineSym() {
             }
         }
     }
+    m_afterColonColon = token == yP_COLONCOLON;
     yylval.token = token;
     // effectively returns yylval
 }
diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h
index de7ee0ef7..961e87216 100644
--- a/src/V3ParseImp.h
+++ b/src/V3ParseImp.h
@@ -150,6 +150,7 @@ class V3ParseImp final {
     VOptionBool m_unconnectedDrive;  // Last unconnected drive
 
     int m_lexPrevToken = 0;  // previous parsed token (for lexer)
+    bool m_afterColonColon = false;  // The previous token was '::'
     std::deque<V3ParseBisonYYSType> m_tokensAhead;  // Tokens we parsed ahead of parser
 
     std::deque<string*> m_stringps;  // Created strings for later cleanup
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 3613b6ca3..ab687a457 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3291,6 +3291,16 @@ private:
         VL_DANGLING(index_exprp);  // May have been edited
         return VN_AS(nodep->pinsp(), Arg)->exprp();
     }
+    void methodCallWarnTiming(AstMethodCall* const nodep, const std::string& className) {
+        if (v3Global.opt.timing().isSetFalse()) {
+            nodep->v3warn(E_NOTIMING,
+                          className << "::" << nodep->name() << "() requires --timing");
+        } else if (!v3Global.opt.timing().isSetTrue()) {
+            nodep->v3warn(E_NEEDTIMINGOPT, "Use --timing or --no-timing to specify how "
+                                               << className << "::" << nodep->name()
+                                               << "() should be handled");
+        }
+    }
     void methodCallClass(AstMethodCall* nodep, AstClassRefDType* adtypep) {
         // No need to width-resolve the class, as it was done when we did the child
         AstClass* const first_classp = adtypep->classp();
@@ -3300,6 +3310,26 @@ private:
         }
         UASSERT_OBJ(first_classp, nodep, "Unlinked");
         for (AstClass* classp = first_classp; classp;) {
+            if (nodep->fileline()->timingOn()) {
+                if (classp->name() == "semaphore"
+                    || VString::startsWith(classp->name(), "mailbox")) {
+                    // Find the package the class is in
+                    AstNode* pkgItemp = classp;
+                    while (pkgItemp->backp() && pkgItemp->backp()->nextp() == pkgItemp) {
+                        pkgItemp = pkgItemp->backp();
+                    }
+                    AstPackage* const packagep = VN_CAST(pkgItemp->backp(), Package);
+                    // Check if it's std
+                    if (packagep && packagep->name() == "std") {
+                        if (classp->name() == "semaphore" && nodep->name() == "get") {
+                            methodCallWarnTiming(nodep, "semaphore");
+                        } else if (nodep->name() == "put" || nodep->name() == "get"
+                                   || nodep->name() == "peek") {
+                            methodCallWarnTiming(nodep, "mailbox");
+                        }
+                    }
+                }
+            }
             if (AstNodeFTask* const ftaskp
                 = VN_CAST(classp->findMember(nodep->name()), NodeFTask)) {
                 userIterate(ftaskp, nullptr);
diff --git a/src/verilog.y b/src/verilog.y
index 61cb9e552..289b4e6fb 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1162,6 +1162,13 @@ package_declaration:            // ==IEEE: package_declaration
 packageFront<nodeModulep>:
                 yPACKAGE lifetimeE idAny ';'
                         { $$ = new AstPackage{$<fl>3, *$3};
+                          if ($$->name() == "std") {
+                              if ($$->fileline()->filename() != V3Options::getStdPackagePath()) {
+                                  $$->v3error("Redeclaring the 'std' package is not allowed");
+                              } else {
+                                  PARSEP->rootp()->stdPackagep(VN_AS($$, Package));
+                              }
+                          }
                           $$->inLibrary(true);  // packages are always libraries; don't want to make them a "top"
                           $$->lifetime($2);
                           $$->modTrace(GRAMMARP->allTracingOn($$->fileline()));
diff --git a/test_regress/t/t_mailbox.out b/test_regress/t/t_mailbox.out
deleted file mode 100644
index d09756948..000000000
--- a/test_regress/t/t_mailbox.out
+++ /dev/null
@@ -1,6 +0,0 @@
-%Error: t/t_mailbox.v:24:4: Can't find typedef: 'mailbox'
-   24 |    mailbox #(int) m;
-      |    ^~~~~~~
-%Error: Internal Error: t/t_mailbox.v:24:14: ../V3LinkDot.cpp:#: Pin not under instance?
-   24 |    mailbox #(int) m;
-      |              ^~~
diff --git a/test_regress/t/t_mailbox.pl b/test_regress/t/t_mailbox.pl
index 2ad4a887d..d7ae01e91 100755
--- a/test_regress/t/t_mailbox.pl
+++ b/test_regress/t/t_mailbox.pl
@@ -10,14 +10,19 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-compile(
-    fails => $Self->{vlt_all},
-    expect_filename => $Self->{golden_filename},
-    );
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    compile(
+        verilator_flags2 => ["--exe --main --timing -Wall"],
+        make_main => 0,
+        );
 
-execute(
-    check_finished => 1,
-    ) if !$Self->{vlt_all};
+    execute(
+        check_finished => 1,
+        );
+}
 
 ok(1);
 1;
diff --git a/test_regress/t/t_mailbox.v b/test_regress/t/t_mailbox.v
index 64e2ba175..e4402f606 100644
--- a/test_regress/t/t_mailbox.v
+++ b/test_regress/t/t_mailbox.v
@@ -20,6 +20,7 @@
  `define MAILBOX_T mailbox
 `endif
 
+// verilator lint_off DECLFILENAME
 module t(/*AUTOARG*/);
    `MAILBOX_T #(int) m;
    int     msg;
diff --git a/test_regress/t/t_mailbox_bad.out b/test_regress/t/t_mailbox_bad.out
index 218a34ad3..3ef286864 100644
--- a/test_regress/t/t_mailbox_bad.out
+++ b/test_regress/t/t_mailbox_bad.out
@@ -1,6 +1,5 @@
-%Error: t/t_mailbox_bad.v:8:4: Can't find typedef: 'mailbox'
-    8 |    mailbox #(int) m;
-      |    ^~~~~~~
-%Error: Internal Error: t/t_mailbox_bad.v:8:14: ../V3LinkDot.cpp:#: Pin not under instance?
-    8 |    mailbox #(int) m;
-      |              ^~~
+%Error: t/t_mailbox_bad.v:12:13: Class method 'bad_method' not found in class 'mailbox__Tz1'
+                               : ... In instance t
+   12 |       if (m.bad_method() != 0) $stop;
+      |             ^~~~~~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_mailbox_std.out b/test_regress/t/t_mailbox_std.out
deleted file mode 100644
index d09756948..000000000
--- a/test_regress/t/t_mailbox_std.out
+++ /dev/null
@@ -1,6 +0,0 @@
-%Error: t/t_mailbox.v:24:4: Can't find typedef: 'mailbox'
-   24 |    mailbox #(int) m;
-      |    ^~~~~~~
-%Error: Internal Error: t/t_mailbox.v:24:14: ../V3LinkDot.cpp:#: Pin not under instance?
-   24 |    mailbox #(int) m;
-      |              ^~~
diff --git a/test_regress/t/t_mailbox_std.pl b/test_regress/t/t_mailbox_std.pl
index 3b640c6e1..54f95ce97 100755
--- a/test_regress/t/t_mailbox_std.pl
+++ b/test_regress/t/t_mailbox_std.pl
@@ -10,17 +10,21 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-top_filename("t/t_mailbox.v");
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    top_filename("t/t_mailbox.v");
 
-compile(
-    v_flags2 => ["+define+T_MAILBOX+std::mailbox"],
-    fails => $Self->{vlt_all},
-    expect_filename => $Self->{golden_filename},
-    );
+    compile(
+        verilator_flags2 => ["--exe --main --timing -Wall -DMAILBOX_T=std::mailbox"],
+        make_main => 0,
+        );
 
-execute(
-    check_finished => 1,
-    ) if !$Self->{vlt_all};
+    execute(
+        check_finished => 1,
+        );
+}
 
 ok(1);
 1;
diff --git a/test_regress/t/t_notiming.out b/test_regress/t/t_notiming.out
index b625df546..e12212acd 100644
--- a/test_regress/t/t_notiming.out
+++ b/test_regress/t/t_notiming.out
@@ -30,4 +30,20 @@
                                       : ... In instance t
    27 |    initial #2 $stop;  
       |            ^
+%Error-NOTIMING: t/t_notiming.v:33:10: mailbox::put() requires --timing
+                                     : ... In instance t
+   33 |        m.put(i);
+      |          ^~~
+%Error-NOTIMING: t/t_notiming.v:34:10: mailbox::get() requires --timing
+                                     : ... In instance t
+   34 |        m.get(i);
+      |          ^~~
+%Error-NOTIMING: t/t_notiming.v:35:10: mailbox::peek() requires --timing
+                                     : ... In instance t
+   35 |        m.peek(i);
+      |          ^~~~
+%Error-NOTIMING: t/t_notiming.v:36:10: semaphore::get() requires --timing
+                                     : ... In instance t
+   36 |        s.get();
+      |          ^~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_notiming.v b/test_regress/t/t_notiming.v
index 649888e1f..ae163d23c 100644
--- a/test_regress/t/t_notiming.v
+++ b/test_regress/t/t_notiming.v
@@ -25,6 +25,16 @@ module t;
 
    initial #1 ->e;
    initial #2 $stop; // timeout
+
+   mailbox#(int) m = new;
+   semaphore s = new;
+   initial begin
+       int i;
+       m.put(i);
+       m.get(i);
+       m.peek(i);
+       s.get();
+   end
 endmodule
 
 `ifdef VERILATOR_TIMING
diff --git a/test_regress/t/t_semaphore.out b/test_regress/t/t_semaphore.out
deleted file mode 100644
index 95ce89973..000000000
--- a/test_regress/t/t_semaphore.out
+++ /dev/null
@@ -1,7 +0,0 @@
-%Error: t/t_semaphore.v:21:4: Can't find typedef: 'semaphore'
-   21 |    semaphore s;
-      |    ^~~~~~~~~
-%Error: t/t_semaphore.v:22:4: Can't find typedef: 'semaphore'
-   22 |    semaphore s2;
-      |    ^~~~~~~~~
-%Error: Exiting due to
diff --git a/test_regress/t/t_semaphore.pl b/test_regress/t/t_semaphore.pl
index 2ad4a887d..d7ae01e91 100755
--- a/test_regress/t/t_semaphore.pl
+++ b/test_regress/t/t_semaphore.pl
@@ -10,14 +10,19 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-compile(
-    fails => $Self->{vlt_all},
-    expect_filename => $Self->{golden_filename},
-    );
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    compile(
+        verilator_flags2 => ["--exe --main --timing -Wall"],
+        make_main => 0,
+        );
 
-execute(
-    check_finished => 1,
-    ) if !$Self->{vlt_all};
+    execute(
+        check_finished => 1,
+        );
+}
 
 ok(1);
 1;
diff --git a/test_regress/t/t_semaphore.v b/test_regress/t/t_semaphore.v
index 500fac7e8..6635cff9d 100644
--- a/test_regress/t/t_semaphore.v
+++ b/test_regress/t/t_semaphore.v
@@ -16,11 +16,11 @@
  `define SEMAPHORE_T semaphore
 `endif
 
+// verilator lint_off DECLFILENAME
 module t(/*AUTOARG*/);
    // From UVM:
    `SEMAPHORE_T s;
    `SEMAPHORE_T s2;
-   int       msg;
 
    initial begin
       s = new(1);
diff --git a/test_regress/t/t_semaphore_bad.out b/test_regress/t/t_semaphore_bad.out
index c07616459..2fc1c33cb 100644
--- a/test_regress/t/t_semaphore_bad.out
+++ b/test_regress/t/t_semaphore_bad.out
@@ -1,4 +1,5 @@
-%Error: t/t_semaphore_bad.v:8:4: Can't find typedef: 'semaphore'
-    8 |    semaphore s;
-      |    ^~~~~~~~~
+%Error: t/t_semaphore_bad.v:12:13: Class method 'bad_method' not found in class 'semaphore'
+                                 : ... In instance t
+   12 |       if (s.bad_method() != 0) $stop;
+      |             ^~~~~~~~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_semaphore_std.out b/test_regress/t/t_semaphore_std.out
deleted file mode 100644
index 95ce89973..000000000
--- a/test_regress/t/t_semaphore_std.out
+++ /dev/null
@@ -1,7 +0,0 @@
-%Error: t/t_semaphore.v:21:4: Can't find typedef: 'semaphore'
-   21 |    semaphore s;
-      |    ^~~~~~~~~
-%Error: t/t_semaphore.v:22:4: Can't find typedef: 'semaphore'
-   22 |    semaphore s2;
-      |    ^~~~~~~~~
-%Error: Exiting due to
diff --git a/test_regress/t/t_semaphore_std.pl b/test_regress/t/t_semaphore_std.pl
index ece82f871..7fcb5b404 100755
--- a/test_regress/t/t_semaphore_std.pl
+++ b/test_regress/t/t_semaphore_std.pl
@@ -10,17 +10,21 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-top_filename("t/t_semaphore.v");
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    top_filename("t/t_semaphore.v");
 
-compile(
-    v_flags2 => ["+define+T_SEMAPHORE+std::semaphore"],
-    fails => $Self->{vlt_all},
-    expect_filename => $Self->{golden_filename},
-    );
+    compile(
+        verilator_flags2 => ["--exe --main --timing -Wall -DSEMAPHORE_T=std::semaphore"],
+        make_main => 0,
+        );
 
-execute(
-    check_finished => 1,
-    ) if !$Self->{vlt_all};
+    execute(
+        check_finished => 1,
+        );
+}
 
 ok(1);
 1;
diff --git a/test_regress/t/t_std_identifier.out b/test_regress/t/t_std_identifier.out
new file mode 100644
index 000000000..1b970e684
--- /dev/null
+++ b/test_regress/t/t_std_identifier.out
@@ -0,0 +1,5 @@
+%Error-PKGNODECL: t/t_std_identifier.v:16:20: Package/class 'std' not found, and needs to be predeclared (IEEE 1800-2017 26.3)
+   16 |     int baz = foo::std::bar;
+      |                    ^~~
+                  ... For error description see https://verilator.org/warn/PKGNODECL?v=latest
+%Error: Exiting due to
diff --git a/test_regress/t/t_semaphore_parse.pl b/test_regress/t/t_std_identifier.pl
similarity index 65%
rename from test_regress/t/t_semaphore_parse.pl
rename to test_regress/t/t_std_identifier.pl
index 8149e4600..3e2acea9f 100755
--- a/test_regress/t/t_semaphore_parse.pl
+++ b/test_regress/t/t_std_identifier.pl
@@ -2,18 +2,21 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003 by Wilson Snyder. This program is free software; you
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-scenarios(vlt => 1);
-
-top_filename("t_semaphore.v");
+scenarios(linter => 1);
 
 lint(
-    verilator_flags2 => ["--debug-exit-uvm"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+lint(
+    verilator_flags2 => ["-DTEST_DECLARE_STD"],
     );
 
 ok(1);
diff --git a/test_regress/t/t_std_identifier.v b/test_regress/t/t_std_identifier.v
new file mode 100644
index 000000000..882fb5658
--- /dev/null
+++ b/test_regress/t/t_std_identifier.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+package foo;
+`ifdef TEST_DECLARE_STD
+    class std;
+        static int bar;
+    endclass
+`endif
+endpackage
+
+module t;
+    int baz = foo::std::bar;
+endmodule
diff --git a/test_regress/t/t_std_pkg_bad.out b/test_regress/t/t_std_pkg_bad.out
new file mode 100644
index 000000000..54a735e56
--- /dev/null
+++ b/test_regress/t/t_std_pkg_bad.out
@@ -0,0 +1,4 @@
+%Error: t/t_std_pkg_bad.v:7:9: Redeclaring the 'std' package is not allowed
+    7 | package std;
+      |         ^~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_mailbox_parse.pl b/test_regress/t/t_std_pkg_bad.pl
similarity index 71%
rename from test_regress/t/t_mailbox_parse.pl
rename to test_regress/t/t_std_pkg_bad.pl
index 6074d4d9a..19ba90d40 100755
--- a/test_regress/t/t_mailbox_parse.pl
+++ b/test_regress/t/t_std_pkg_bad.pl
@@ -2,18 +2,17 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2003 by Wilson Snyder. This program is free software; you
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-scenarios(vlt => 1);
-
-top_filename("t_mailbox.v");
+scenarios(linter => 1);
 
 lint(
-    verilator_flags2 => ["--debug-exit-uvm"],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
     );
 
 ok(1);
diff --git a/test_regress/t/t_std_pkg_bad.v b/test_regress/t/t_std_pkg_bad.v
new file mode 100644
index 000000000..c1969368e
--- /dev/null
+++ b/test_regress/t/t_std_pkg_bad.v
@@ -0,0 +1,11 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+package std;
+endpackage
+
+module t;
+endmodule
diff --git a/test_regress/t/t_timing_unset1.out b/test_regress/t/t_timing_unset1.out
index c6bcbb64a..eb8c53eb8 100644
--- a/test_regress/t/t_timing_unset1.out
+++ b/test_regress/t/t_timing_unset1.out
@@ -31,4 +31,20 @@
                                           : ... In instance t
    27 |    initial #2 $stop;  
       |            ^
+%Error-NEEDTIMINGOPT: t/t_notiming.v:33:10: Use --timing or --no-timing to specify how mailbox::put() should be handled
+                                          : ... In instance t
+   33 |        m.put(i);
+      |          ^~~
+%Error-NEEDTIMINGOPT: t/t_notiming.v:34:10: Use --timing or --no-timing to specify how mailbox::get() should be handled
+                                          : ... In instance t
+   34 |        m.get(i);
+      |          ^~~
+%Error-NEEDTIMINGOPT: t/t_notiming.v:35:10: Use --timing or --no-timing to specify how mailbox::peek() should be handled
+                                          : ... In instance t
+   35 |        m.peek(i);
+      |          ^~~~
+%Error-NEEDTIMINGOPT: t/t_notiming.v:36:10: Use --timing or --no-timing to specify how semaphore::get() should be handled
+                                          : ... In instance t
+   36 |        s.get();
+      |          ^~~
 %Error: Exiting due to

From e569ff2752f92dfc7aa510005d3eb2030b3b129b Mon Sep 17 00:00:00 2001
From: Yinan Xu <xuyinan@ict.ac.cn>
Date: Tue, 29 Nov 2022 19:37:38 +0800
Subject: [PATCH 103/156] Add error when use --exe with --lib-create. (#3785)

---
 docs/CONTRIBUTORS                      |  1 +
 src/V3Options.cpp                      |  4 ++++
 test_regress/t/t_lib_prot_delay_bad.pl |  1 +
 test_regress/t/t_lib_prot_exe_bad.out  |  2 ++
 test_regress/t/t_lib_prot_exe_bad.pl   | 25 +++++++++++++++++++++++++
 test_regress/t/t_lib_prot_inout_bad.pl |  1 +
 6 files changed, 34 insertions(+)
 create mode 100644 test_regress/t/t_lib_prot_exe_bad.out
 create mode 100755 test_regress/t/t_lib_prot_exe_bad.pl

diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS
index c9756852e..517d03f61 100644
--- a/docs/CONTRIBUTORS
+++ b/docs/CONTRIBUTORS
@@ -133,6 +133,7 @@ Victor Besyakov
 William D. Jones
 Wilson Snyder
 Xi Zhang
+Yinan Xu
 Yoda Lee
 Yossi Nivin
 Yuri Victorovich
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index 4f14b672e..ca7ee2f3f 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -761,6 +761,10 @@ void V3Options::notify() {
         cmdfl->v3error("--make cannot be used together with --build. Suggest see manual");
     }
 
+    if (m_exe && !v3Global.opt.libCreate().empty()) {
+        cmdfl->v3error("--exe cannot be used together with --lib-create. Suggest see manual");
+    }
+
     // Make sure at least one make system is enabled
     if (!m_gmake && !m_cmake) m_gmake = true;
 
diff --git a/test_regress/t/t_lib_prot_delay_bad.pl b/test_regress/t/t_lib_prot_delay_bad.pl
index 7bb3853cf..802270587 100755
--- a/test_regress/t/t_lib_prot_delay_bad.pl
+++ b/test_regress/t/t_lib_prot_delay_bad.pl
@@ -18,6 +18,7 @@ compile (
                          "--timing",
                        ],
     verilator_make_gcc => 0,
+    make_main => 0,
     fails => 1,
     expect_filename => $Self->{golden_filename},
     );
diff --git a/test_regress/t/t_lib_prot_exe_bad.out b/test_regress/t/t_lib_prot_exe_bad.out
new file mode 100644
index 000000000..7b64aaaa2
--- /dev/null
+++ b/test_regress/t/t_lib_prot_exe_bad.out
@@ -0,0 +1,2 @@
+%Error: --exe cannot be used together with --lib-create. Suggest see manual
+%Error: Exiting due to
diff --git a/test_regress/t/t_lib_prot_exe_bad.pl b/test_regress/t/t_lib_prot_exe_bad.pl
new file mode 100755
index 000000000..a89483bf5
--- /dev/null
+++ b/test_regress/t/t_lib_prot_exe_bad.pl
@@ -0,0 +1,25 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Yinan Xu. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+compile (
+    verilator_flags2 => ["--protect-lib",
+                         "secret",
+                         "--protect-key",
+                         "secret-key",
+                       ],
+    verilator_make_gcc => 0,
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_lib_prot_inout_bad.pl b/test_regress/t/t_lib_prot_inout_bad.pl
index d3c7f81d2..375b280ce 100755
--- a/test_regress/t/t_lib_prot_inout_bad.pl
+++ b/test_regress/t/t_lib_prot_inout_bad.pl
@@ -17,6 +17,7 @@ compile (
                          "secret-key"
                        ],
     verilator_make_gcc => 0,
+    make_main => 0,
     fails => 1,
     expect_filename => $Self->{golden_filename},
     );

From 7d807a7e0ece211e31f0f5813189f9d35347d17e Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 28 Nov 2022 19:58:08 -0500
Subject: [PATCH 104/156] Commentary

---
 include/verilatedos.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/verilatedos.h b/include/verilatedos.h
index 5d6f220a5..5fed91b1b 100644
--- a/include/verilatedos.h
+++ b/include/verilatedos.h
@@ -111,7 +111,7 @@
 # define VL_ATTR_WEAK  ///< Attribute that function external that is optionally defined
 #endif
 #ifndef VL_CAPABILITY
-# define VL_ACQUIRE(...)  ///< Function requires a capability/lock (-fthread-safety)
+# define VL_ACQUIRE(...)  ///< Function aquires a capability/lock (-fthread-safety)
 # define VL_ACQUIRE_SHARED(...)  ///< Function aquires a shared capability/lock (-fthread-safety)
 # define VL_RELEASE(...)  ///< Function releases a capability/lock (-fthread-safety)
 # define VL_RELEASE_SHARED(...)  ///< Function releases a shared capability/lock (-fthread-safety)

From ff9596bb23dd3675ce061a20ab14ebbd7fe6bc96 Mon Sep 17 00:00:00 2001
From: Yinan Xu <xuyinan@ict.ac.cn>
Date: Tue, 29 Nov 2022 22:02:39 +0800
Subject: [PATCH 105/156] Fix missing user objects in --lib-create mode (#3780)
 (#3784)

---
 src/V3EmitMk.cpp | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp
index 7c1bf0094..eefba5e92 100644
--- a/src/V3EmitMk.cpp
+++ b/src/V3EmitMk.cpp
@@ -231,13 +231,16 @@ public:
             of.puts("\n### Executable rules... (from --exe)\n");
             of.puts("VPATH += $(VM_USER_DIR)\n");
             of.puts("\n");
-            for (const string& cppfile : cppFiles) {
-                const string basename = V3Os::filenameNonExt(cppfile);
-                // NOLINTNEXTLINE(performance-inefficient-string-concatenation)
-                of.puts(basename + ".o: " + cppfile + "\n");
-                of.puts("\t$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<\n");
-            }
+        }
 
+        for (const string& cppfile : cppFiles) {
+            const string basename = V3Os::filenameNonExt(cppfile);
+            // NOLINTNEXTLINE(performance-inefficient-string-concatenation)
+            of.puts(basename + ".o: " + cppfile + "\n");
+            of.puts("\t$(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $<\n");
+        }
+
+        if (v3Global.opt.exe()) {
             of.puts("\n### Link rules... (from --exe)\n");
             of.puts(v3Global.opt.exeName()
                     + ": $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a $(VM_HIER_LIBS)\n");

From faedcc755b152883672c4625e0af32501f785ad6 Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Tue, 29 Nov 2022 16:46:26 +0100
Subject: [PATCH 106/156] Tests: Add test of passing this as argument (#3790)

---
 test_regress/t/t_class_uses_this.v | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/test_regress/t/t_class_uses_this.v b/test_regress/t/t_class_uses_this.v
index 966f8bb23..862296e6a 100644
--- a/test_regress/t/t_class_uses_this.v
+++ b/test_regress/t/t_class_uses_this.v
@@ -30,6 +30,17 @@ function void Cls::setext2(bit [3:0] addr);
    c2.addr = addr;
 endfunction
 
+class wrapped_int;
+   int x;
+   static wrapped_int q[$];
+   function new(int a);
+      this.x = a;
+   endfunction
+   function void push_this;
+      q.push_back(this);
+   endfunction
+endclass
+
 module t(/*AUTOARG*/
    // Inputs
    clk
@@ -37,6 +48,8 @@ module t(/*AUTOARG*/
    input clk;
    Cls bar;
    Cls baz;
+   wrapped_int i1, i2;
+
    initial begin
       bar = new();
       baz = new();
@@ -52,6 +65,13 @@ module t(/*AUTOARG*/
       if (bar.addr != 2) $stop;
       bar.setext2(3);
       if (bar.addr != 3) $stop;
+
+      i1 = new(1);
+      i1.push_this();
+      i2 = new(2);
+      i2.push_this();
+      if (wrapped_int::q.size() != 2) $stop;
+
       $write("*-* All Finished *-*\n");
       $finish;
    end

From f0a7abcef8cc7ea47a355578dc59f0bb7e3db085 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 29 Nov 2022 18:17:50 -0500
Subject: [PATCH 107/156] Internals: Use named accessors instead of op1p etc.
 No functional change intended.

---
 src/V3EmitCFunc.cpp | 12 +++---------
 src/V3EmitXml.cpp   | 22 +++++++++++-----------
 src/V3Param.cpp     |  6 +++---
 3 files changed, 17 insertions(+), 23 deletions(-)

diff --git a/src/V3EmitCFunc.cpp b/src/V3EmitCFunc.cpp
index 059e64c65..128c70351 100644
--- a/src/V3EmitCFunc.cpp
+++ b/src/V3EmitCFunc.cpp
@@ -36,15 +36,9 @@ bool EmitCFunc::emitSimpleOk(AstNodeExpr* nodep) {
     // Can we put out a simple (A + B) instead of VL_ADD_III(A,B)?
     if (nodep->emitSimpleOperator() == "") return false;
     if (nodep->isWide()) return false;
-    if (nodep->op1p()) {
-        if (nodep->op1p()->isWide()) return false;
-    }
-    if (nodep->op2p()) {
-        if (nodep->op2p()->isWide()) return false;
-    }
-    if (nodep->op3p()) {
-        if (nodep->op3p()->isWide()) return false;
-    }
+    if (nodep->op1p() && nodep->op1p()->isWide()) return false;
+    if (nodep->op2p() && nodep->op2p()->isWide()) return false;
+    if (nodep->op3p() && nodep->op3p()->isWide()) return false;
     return true;
 }
 
diff --git a/src/V3EmitXml.cpp b/src/V3EmitXml.cpp
index db6ec800f..c3ac43da1 100644
--- a/src/V3EmitXml.cpp
+++ b/src/V3EmitXml.cpp
@@ -117,13 +117,13 @@ class EmitXmlFileVisitor final : public VNVisitor {
     void visit(AstNodeIf* nodep) override {
         outputTag(nodep, "if");
         puts(">\n");
-        iterateAndNextNull(nodep->op1p());
+        iterateAndNextNull(nodep->condp());
         puts("<begin>\n");
-        iterateAndNextNull(nodep->op2p());
+        iterateAndNextNull(nodep->thensp());
         puts("</begin>\n");
-        if (nodep->op3p()) {
+        if (nodep->elsesp()) {
             puts("<begin>\n");
-            iterateAndNextNull(nodep->op3p());
+            iterateAndNextNull(nodep->elsesp());
             puts("</begin>\n");
         }
         puts("</if>\n");
@@ -132,21 +132,21 @@ class EmitXmlFileVisitor final : public VNVisitor {
         outputTag(nodep, "while");
         puts(">\n");
         puts("<begin>\n");
-        iterateAndNextNull(nodep->op1p());
+        iterateAndNextNull(nodep->precondsp());
         puts("</begin>\n");
-        if (nodep->op2p()) {
+        if (nodep->condp()) {
             puts("<begin>\n");
-            iterateAndNextNull(nodep->op2p());
+            iterateAndNextNull(nodep->condp());
             puts("</begin>\n");
         }
-        if (nodep->op3p()) {
+        if (nodep->stmtsp()) {
             puts("<begin>\n");
-            iterateAndNextNull(nodep->op3p());
+            iterateAndNextNull(nodep->stmtsp());
             puts("</begin>\n");
         }
-        if (nodep->op4p()) {
+        if (nodep->incsp()) {
             puts("<begin>\n");
-            iterateAndNextNull(nodep->op4p());
+            iterateAndNextNull(nodep->incsp());
             puts("</begin>\n");
         }
         puts("</while>\n");
diff --git a/src/V3Param.cpp b/src/V3Param.cpp
index f3e4b5037..969ec8e30 100644
--- a/src/V3Param.cpp
+++ b/src/V3Param.cpp
@@ -1098,8 +1098,8 @@ class ParamVisitor final : public VNVisitor {
     }
 
     void visit(AstUnlinkedRef* nodep) override {
-        AstVarXRef* const varxrefp = VN_CAST(nodep->op1p(), VarXRef);
-        AstNodeFTaskRef* const taskrefp = VN_CAST(nodep->op1p(), NodeFTaskRef);
+        AstVarXRef* const varxrefp = VN_CAST(nodep->refp(), VarXRef);
+        AstNodeFTaskRef* const taskrefp = VN_CAST(nodep->refp(), NodeFTaskRef);
         if (varxrefp) {
             m_unlinkedTxt = varxrefp->dotted();
         } else if (taskrefp) {
@@ -1115,7 +1115,7 @@ class ParamVisitor final : public VNVisitor {
         } else {
             taskrefp->dotted(m_unlinkedTxt);
         }
-        nodep->replaceWith(nodep->op1p()->unlinkFrBack());
+        nodep->replaceWith(nodep->refp()->unlinkFrBack());
         VL_DO_DANGLING(pushDeletep(nodep), nodep);
     }
     void visit(AstCellArrayRef* nodep) override {

From b51bb4d0e7956864b5e6118e82f5497766c108d9 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 29 Nov 2022 18:32:28 -0500
Subject: [PATCH 108/156] Internal: Add node objects to UASSERT (#3786)

---
 src/V3Const.cpp | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index befd7dabd..2790b9620 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -100,12 +100,12 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
 
         // METHODS
         void setLeaf(AstVarRef* refp) {
-            UASSERT(!m_refp && !m_constp, "Must be called just once");
+            UASSERT_OBJ(!m_refp && !m_constp, refp, "Must be called just once");
             m_refp = refp;
             m_msb = refp->varp()->widthMin() - 1;
         }
         void setLeaf(const AstConst* constp) {
-            UASSERT(!m_refp && !m_constp, "Must be called just once");
+            UASSERT_OBJ(!m_refp && !m_constp, constp, "Must be called just once");
             m_constp = constp;
             m_msb = constp->widthMin() - 1;
         }
@@ -129,10 +129,10 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
             UASSERT(m_refp, "m_refp should be set");
             const int width = m_refp->varp()->widthMin();
             if (!m_refp->isWide()) {
-                UASSERT(m_wordIdx == -1, "Bad word index into non-wide");
+                UASSERT_OBJ(m_wordIdx == -1, m_refp, "Bad word index into non-wide");
                 return width;
             } else {
-                UASSERT(m_wordIdx >= 0, "Bad word index into wide");
+                UASSERT_OBJ(m_wordIdx >= 0, m_refp, "Bad word index into wide");
                 const int bitsInMSW = VL_BITBIT_E(width) ? VL_BITBIT_E(width) : VL_EDATASIZE;
                 return m_wordIdx == m_refp->widthWords() - 1 ? bitsInMSW : VL_EDATASIZE;
             }
@@ -239,7 +239,7 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
         // Return reduction term for this VarInfo, together with the number of ops in the term,
         // and a boolean indicating if the term is clean (1-bit vs multi-bit value)
         ResultTerm getResultTerm() const {
-            UASSERT(!hasConstResult(), "getTerm on reduction that yields constant");
+            UASSERT_OBJ(!hasConstResult(), m_refp, "getTerm on reduction that yields constant");
             FileLine* const fl = m_refp->fileline();
 
             // Get the term we are referencing (the WordSel, if wide, otherwise just the VarRef)
@@ -257,7 +257,8 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
             V3Number maskNum{srcp, m_width, 0};
             maskNum.opBitsNonX(m_bitPolarity);  // 'x' -> 0, 0->1, 1->1
             const uint64_t maskVal = maskNum.toUQuad();
-            UASSERT(maskVal != 0, "Should have been recognized as having const 0 result");
+            UASSERT_OBJ(maskVal != 0, m_refp,
+                        "Should have been recognized as having const 0 result");
 
             // Parts of the return value
             AstNodeExpr* resultp = srcp;  // The tree for this term

From 614389261981306f3d88e68feec9dde0ee1592d5 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 29 Nov 2022 20:36:56 -0500
Subject: [PATCH 109/156] Internals: Add some VL_UNLIKELY. No functional
 change.

---
 include/verilated.cpp        | 4 ++--
 include/verilated_fst_sc.cpp | 2 +-
 include/verilated_vcd_sc.cpp | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/verilated.cpp b/include/verilated.cpp
index 17ee99aa9..c975b76e0 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -2453,7 +2453,7 @@ void VerilatedContext::timeprecision(int value) VL_MT_SAFE {
             sc_prec = 15;
         }
     }
-    if (value != sc_prec) {
+    if (VL_UNLIKELY(value != sc_prec)) {
         std::ostringstream msg;
         msg << "SystemC's sc_set_time_resolution is 10^-" << sc_prec
             << ", which does not match Verilog timeprecision 10^-" << value
@@ -2524,7 +2524,7 @@ void VerilatedContext::internalsDump() const VL_MT_SAFE {
 void VerilatedContext::addModel(VerilatedModel* modelp) {
     threadPoolp();  // Ensure thread pool is created, so m_threads cannot change any more
 
-    if (modelp->threads() > m_threads) {
+    if (VL_UNLIKELY(modelp->threads() > m_threads)) {
         std::ostringstream msg;
         msg << "VerilatedContext has " << m_threads << " threads but model '"
             << modelp->modelName() << "' (instantiated as '" << modelp->hierName()
diff --git a/include/verilated_fst_sc.cpp b/include/verilated_fst_sc.cpp
index f6bfeb41a..b093e1eac 100644
--- a/include/verilated_fst_sc.cpp
+++ b/include/verilated_fst_sc.cpp
@@ -29,7 +29,7 @@
 //======================================================================
 
 void VerilatedFstSc::open(const char* filename) {
-    if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) {
+    if (VL_UNLIKELY(!sc_core::sc_get_curr_simcontext()->elaboration_done())) {
         vl_fatal(__FILE__, __LINE__, "VerilatedFstSc",
                  ("%Error: VerilatedFstSc::open(\"" + std::string{filename}
                   + "\") is called before sc_core::sc_start(). "
diff --git a/include/verilated_vcd_sc.cpp b/include/verilated_vcd_sc.cpp
index a7286d050..2da4de7b1 100644
--- a/include/verilated_vcd_sc.cpp
+++ b/include/verilated_vcd_sc.cpp
@@ -29,7 +29,7 @@
 //======================================================================
 
 void VerilatedVcdSc::open(const char* filename) {
-    if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) {
+    if (VL_UNLIKELY(!sc_core::sc_get_curr_simcontext()->elaboration_done())) {
         vl_fatal(__FILE__, __LINE__, "VerilatedVcdSc",
                  ("%Error: VerilatedVcdSc::open(\"" + std::string{filename}
                   + "\") is called before sc_core::sc_start(). "

From 8ff607f679b444663cf799f02c74fb6b3b97fef6 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 29 Nov 2022 22:17:50 -0500
Subject: [PATCH 110/156] Deprecate verilated_fst_sc.cpp and
 verilated_vcd_sc.cpp (#3507)

---
 Changes                      |  1 +
 include/verilated.cpp        |  8 ++++
 include/verilated.h          |  1 +
 include/verilated_fst_sc.cpp | 77 ++----------------------------------
 include/verilated_fst_sc.h   | 48 +++++++++++++---------
 include/verilated_vcd_sc.cpp | 77 ++----------------------------------
 include/verilated_vcd_sc.h   | 23 +++++++----
 src/V3EmitCMake.cpp          |  4 --
 src/V3EmitMk.cpp             |  3 --
 9 files changed, 62 insertions(+), 180 deletions(-)

diff --git a/Changes b/Changes
index b1e03f214..5e6743357 100644
--- a/Changes
+++ b/Changes
@@ -22,6 +22,7 @@ Verilator 5.003 devel
 * Add ENUMVALUE warning when value misused for enum (#726).
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Change ENDLABEL from warning into an error.
+* Deprecate verilated_fst_sc.cpp and verilated_vcd_sc.cpp.
 * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
 * Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
 * Fix tracing parameters overridden with -G (#3723). [Iztok Jeras]
diff --git a/include/verilated.cpp b/include/verilated.cpp
index c975b76e0..ad7570598 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -2883,6 +2883,14 @@ void Verilated::overWidthError(const char* signame) VL_MT_SAFE {
     VL_UNREACHABLE;
 }
 
+void Verilated::scTraceBeforeElaboration() VL_MT_SAFE {
+    // Slowpath - Called only when trace file opened before SystemC elaboration
+    VL_FATAL_MT("unknown", 0, "",
+                "%Error: Verilated*Sc::open(...) was called before sc_core::sc_start(). "
+                "Run sc_core::sc_start(sc_core::SC_ZERO_TIME) before opening a wave file.");
+    VL_UNREACHABLE;
+}
+
 void Verilated::mkdir(const char* dirname) VL_MT_UNSAFE {
 #if defined(_WIN32) || defined(__MINGW32__)
     ::mkdir(dirname);
diff --git a/include/verilated.h b/include/verilated.h
index 9aee9cfad..aaab1dc37 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -861,6 +861,7 @@ public:
     // Internal: Throw signal assertion
     static void nullPointerError(const char* filename, int linenum) VL_ATTR_NORETURN VL_MT_SAFE;
     static void overWidthError(const char* signame) VL_ATTR_NORETURN VL_MT_SAFE;
+    static void scTraceBeforeElaboration() VL_ATTR_NORETURN VL_MT_SAFE;
 
     // Internal: Get and set DPI context
     static const VerilatedScope* dpiScope() VL_MT_SAFE { return t_s.t_dpiScopep; }
diff --git a/include/verilated_fst_sc.cpp b/include/verilated_fst_sc.cpp
index b093e1eac..807d2beff 100644
--- a/include/verilated_fst_sc.cpp
+++ b/include/verilated_fst_sc.cpp
@@ -14,80 +14,11 @@
 /// \file
 /// \brief Verilated tracing in FST for SystemC implementation code
 ///
-/// This file must be compiled and linked against all Verilated objects
-/// that use --sc --trace-fst.
-///
-/// Use "verilator --sc --trace-fst" to add this to the Makefile for the linker.
+/// This file is deprecated, only verilated_fst_sc.h is needed.
+/// It is provided only for backward compatibility with user's linker scripts.
 ///
 //=============================================================================
 
-#include "verilatedos.h"
-
-#include "verilated_fst_sc.h"
-
-//======================================================================
-//======================================================================
-
-void VerilatedFstSc::open(const char* filename) {
-    if (VL_UNLIKELY(!sc_core::sc_get_curr_simcontext()->elaboration_done())) {
-        vl_fatal(__FILE__, __LINE__, "VerilatedFstSc",
-                 ("%Error: VerilatedFstSc::open(\"" + std::string{filename}
-                  + "\") is called before sc_core::sc_start(). "
-                    "Run sc_core::sc_start(sc_core::SC_ZERO_TIME) before opening a wave file.")
-                     .c_str());
-    }
-    VerilatedFstC::open(filename);
-}
-
-//--------------------------------------------------
-// SystemC 2.1.v1
-// cppcheck-suppress unusedFunction
-void VerilatedFstSc::write_comment(const std::string&) {}
-void VerilatedFstSc::trace(const unsigned int&, const std::string&, const char**) {}
-
-#define DECL_TRACE_METHOD_A(tp) \
-    void VerilatedFstSc::trace(const tp& object, const std::string& name) {}
-#define DECL_TRACE_METHOD_B(tp) \
-    void VerilatedFstSc::trace(const tp& object, const std::string& name, int width) {}
-
-// clang-format off
-#if (SYSTEMC_VERSION >= 20171012)
-    DECL_TRACE_METHOD_A( sc_event )
-    DECL_TRACE_METHOD_A( sc_time )
+#ifdef VL_NO_LEGACY
+#error "verilated_fst_sc.cpp is deprecated; verilated_fst_sc.h is self-sufficient"
 #endif
-
-    DECL_TRACE_METHOD_A( bool )
-    DECL_TRACE_METHOD_A( sc_dt::sc_bit )
-    DECL_TRACE_METHOD_A( sc_dt::sc_logic )
-
-    DECL_TRACE_METHOD_B( unsigned char )
-    DECL_TRACE_METHOD_B( unsigned short )
-    DECL_TRACE_METHOD_B( unsigned int )
-    DECL_TRACE_METHOD_B( unsigned long )
-    DECL_TRACE_METHOD_B( char )
-    DECL_TRACE_METHOD_B( short )
-    DECL_TRACE_METHOD_B( int )
-    DECL_TRACE_METHOD_B( long )
-    DECL_TRACE_METHOD_B( sc_dt::int64 )
-    DECL_TRACE_METHOD_B( sc_dt::uint64 )
-
-    DECL_TRACE_METHOD_A( float )
-    DECL_TRACE_METHOD_A( double )
-    DECL_TRACE_METHOD_A( sc_dt::sc_int_base )
-    DECL_TRACE_METHOD_A( sc_dt::sc_uint_base )
-    DECL_TRACE_METHOD_A( sc_dt::sc_signed )
-    DECL_TRACE_METHOD_A( sc_dt::sc_unsigned )
-
-    DECL_TRACE_METHOD_A( sc_dt::sc_fxval )
-    DECL_TRACE_METHOD_A( sc_dt::sc_fxval_fast )
-    DECL_TRACE_METHOD_A( sc_dt::sc_fxnum )
-    DECL_TRACE_METHOD_A( sc_dt::sc_fxnum_fast )
-
-    DECL_TRACE_METHOD_A( sc_dt::sc_bv_base )
-    DECL_TRACE_METHOD_A( sc_dt::sc_lv_base )
-// clang-format on
-
-#undef DECL_TRACE_METHOD_A
-#undef DECL_TRACE_METHOD_B
-
-//********************************************************************
diff --git a/include/verilated_fst_sc.h b/include/verilated_fst_sc.h
index a34d72d0b..82c0a0003 100644
--- a/include/verilated_fst_sc.h
+++ b/include/verilated_fst_sc.h
@@ -10,7 +10,7 @@
 //=============================================================================
 ///
 /// \file
-/// \brief Verilator tracing in FST format for SystemC header
+/// \brief Verilated tracing in FST format for SystemC header
 ///
 /// User wrapper code should use this header when creating FST SystemC
 /// traces.
@@ -19,8 +19,8 @@
 ///
 //=============================================================================
 
-#ifndef _VERILATED_FST_SC_H_
-#define _VERILATED_FST_SC_H_ 1
+#ifndef VERILATOR_VERILATED_VCD_SC_H_
+#define VERILATOR_VERILATED_VCD_SC_H_
 
 #include "verilatedos.h"
 
@@ -32,40 +32,48 @@
 //=============================================================================
 // VerilatedFstSc
 ///
-/// This class is passed to the SystemC simulation kernel, just like a
-/// documented SystemC trace format.
+/// Class representing a Verilator-friendly FST trace format registered
+/// with the SystemC simulation kernel, just like a SystemC-documented
+/// trace format.
 
 class VerilatedFstSc final : sc_trace_file, public VerilatedFstC {
     // CONSTRUCTORS
     VL_UNCOPYABLE(VerilatedFstSc);
 
 public:
+    /// Construct a SC trace object, and register with the SystemC kernel
     VerilatedFstSc() {
         sc_get_curr_simcontext()->add_trace_file(this);
         // We want to avoid a depreciated warning, but still be back compatible.
         // Turning off the message just for this still results in an
         // annoying "to turn off" message.
-        const sc_time t1sec(1, SC_SEC);
+        const sc_time t1sec{1, SC_SEC};
         if (t1sec.to_default_time_units() != 0) {
-            const sc_time tunits(1.0 / t1sec.to_default_time_units(), SC_SEC);
+            const sc_time tunits{1.0 / t1sec.to_default_time_units(), SC_SEC};
             spTrace()->set_time_unit(tunits.to_string());
         }
         spTrace()->set_time_resolution(sc_get_time_resolution().to_string());
     }
+    /// Destruct, flush, and close the dump
     ~VerilatedFstSc() override { close(); }
 
-    // METHODS
-    /// Called by SystemC simulate()
+    // METHODS - for SC kernel
+    // Called by SystemC simulate()
     void cycle(bool delta_cycle) override {
-        if (!delta_cycle) { this->dump(sc_time_stamp().to_double()); }
+        if (!delta_cycle) this->dump(sc_time_stamp().to_double());
     }
 
     // Override VerilatedFstC. Must be called after starting simulation.
     // Note: this is not a virtual function in the base class, so no 'override'
-    virtual void open(const char* filename) VL_MT_SAFE;
+    virtual void open(const char* filename) VL_MT_SAFE {
+        if (VL_UNLIKELY(!sc_core::sc_get_curr_simcontext()->elaboration_done())) {
+            Verilated::scTraceBeforeElaboration();
+        }
+        VerilatedFstC::open(filename);
+    }
 
 private:
-    /// Fake outs for linker
+    // METHODS - Fake outs for linker
 
 #ifdef NC_SYSTEMC
     // Cadence Incisive has these as abstract functions so we must create them
@@ -73,14 +81,16 @@ private:
 #endif
     void set_time_unit(double v, sc_time_unit tu) override {}  // LCOV_EXCL_LINE
 
-//--------------------------------------------------
-// SystemC 2.1.v1
-#define DECL_TRACE_METHOD_A(tp) void trace(const tp& object, const std::string& name) override;
-#define DECL_TRACE_METHOD_B(tp) \
-    void trace(const tp& object, const std::string& name, int width) override;
+    //--------------------------------------------------
+    // SystemC 2.1.v1
 
-    void write_comment(const std::string&) override;
-    void trace(const unsigned int&, const std::string&, const char**) override;
+    void write_comment(const std::string&) override {}
+    void trace(const unsigned int&, const std::string&, const char**) override {}
+
+#define DECL_TRACE_METHOD_A(tp) \
+    void trace(const tp& object, const std::string& name) override {}
+#define DECL_TRACE_METHOD_B(tp) \
+    void trace(const tp& object, const std::string& name, int width) override {}
 
     // clang-format off
     // Formatting matches that of sc_trace.h
diff --git a/include/verilated_vcd_sc.cpp b/include/verilated_vcd_sc.cpp
index 2da4de7b1..dcccc975b 100644
--- a/include/verilated_vcd_sc.cpp
+++ b/include/verilated_vcd_sc.cpp
@@ -14,80 +14,11 @@
 /// \file
 /// \brief Verilated tracing in VCD Format implementation code
 ///
-/// This file must be compiled and linked against all Verilated objects
-/// that use --trace.
-///
-/// Use "verilator --trace" to add this to the Makefile for the linker.
+/// This file is deprecated, only verilated_vcd_sc.h is needed.
+/// It is provided only for backward compatibility with user's linker scripts.
 ///
 //=============================================================================
 
-#include "verilatedos.h"
-
-#include "verilated_vcd_sc.h"
-
-//======================================================================
-//======================================================================
-
-void VerilatedVcdSc::open(const char* filename) {
-    if (VL_UNLIKELY(!sc_core::sc_get_curr_simcontext()->elaboration_done())) {
-        vl_fatal(__FILE__, __LINE__, "VerilatedVcdSc",
-                 ("%Error: VerilatedVcdSc::open(\"" + std::string{filename}
-                  + "\") is called before sc_core::sc_start(). "
-                    "Run sc_core::sc_start(sc_core::SC_ZERO_TIME) before opening a wave file.")
-                     .c_str());
-    }
-    VerilatedVcdC::open(filename);
-}
-
-//--------------------------------------------------
-// SystemC 2.1.v1
-// cppcheck-suppress unusedFunction
-void VerilatedVcdSc::write_comment(const std::string&) {}
-void VerilatedVcdSc::trace(const unsigned int&, const std::string&, const char**) {}
-
-#define DECL_TRACE_METHOD_A(tp) \
-    void VerilatedVcdSc::trace(const tp& object, const std::string& name) {}
-#define DECL_TRACE_METHOD_B(tp) \
-    void VerilatedVcdSc::trace(const tp& object, const std::string& name, int width) {}
-
-// clang-format off
-#if (SYSTEMC_VERSION >= 20171012)
-    DECL_TRACE_METHOD_A( sc_event )
-    DECL_TRACE_METHOD_A( sc_time )
+#ifdef VL_NO_LEGACY
+#error "verilated_vcd_sc.cpp is deprecated; verilated_vcd_sc.h is self-sufficient"
 #endif
-
-    DECL_TRACE_METHOD_A( bool )
-    DECL_TRACE_METHOD_A( sc_dt::sc_bit )
-    DECL_TRACE_METHOD_A( sc_dt::sc_logic )
-
-    DECL_TRACE_METHOD_B( unsigned char )
-    DECL_TRACE_METHOD_B( unsigned short )
-    DECL_TRACE_METHOD_B( unsigned int )
-    DECL_TRACE_METHOD_B( unsigned long )
-    DECL_TRACE_METHOD_B( char )
-    DECL_TRACE_METHOD_B( short )
-    DECL_TRACE_METHOD_B( int )
-    DECL_TRACE_METHOD_B( long )
-    DECL_TRACE_METHOD_B( sc_dt::int64 )
-    DECL_TRACE_METHOD_B( sc_dt::uint64 )
-
-    DECL_TRACE_METHOD_A( float )
-    DECL_TRACE_METHOD_A( double )
-    DECL_TRACE_METHOD_A( sc_dt::sc_int_base )
-    DECL_TRACE_METHOD_A( sc_dt::sc_uint_base )
-    DECL_TRACE_METHOD_A( sc_dt::sc_signed )
-    DECL_TRACE_METHOD_A( sc_dt::sc_unsigned )
-
-    DECL_TRACE_METHOD_A( sc_dt::sc_fxval )
-    DECL_TRACE_METHOD_A( sc_dt::sc_fxval_fast )
-    DECL_TRACE_METHOD_A( sc_dt::sc_fxnum )
-    DECL_TRACE_METHOD_A( sc_dt::sc_fxnum_fast )
-
-    DECL_TRACE_METHOD_A( sc_dt::sc_bv_base )
-    DECL_TRACE_METHOD_A( sc_dt::sc_lv_base )
-// clang-format on
-
-#undef DECL_TRACE_METHOD_A
-#undef DECL_TRACE_METHOD_B
-
-//********************************************************************
diff --git a/include/verilated_vcd_sc.h b/include/verilated_vcd_sc.h
index ad8de7133..ec8023f10 100644
--- a/include/verilated_vcd_sc.h
+++ b/include/verilated_vcd_sc.h
@@ -64,7 +64,12 @@ public:
     }
 
     // Override VerilatedVcdC. Must be called after starting simulation.
-    void open(const char* filename) override VL_MT_SAFE;
+    void open(const char* filename) override VL_MT_SAFE {
+        if (VL_UNLIKELY(!sc_core::sc_get_curr_simcontext()->elaboration_done())) {
+            Verilated::scTraceBeforeElaboration();
+        }
+        VerilatedVcdC::open(filename);
+    }
 
 private:
     // METHODS - Fake outs for linker
@@ -75,14 +80,16 @@ private:
 #endif
     void set_time_unit(double v, sc_time_unit tu) override {}  // LCOV_EXCL_LINE
 
-//--------------------------------------------------
-// SystemC 2.1.v1
-#define DECL_TRACE_METHOD_A(tp) void trace(const tp& object, const std::string& name) override;
-#define DECL_TRACE_METHOD_B(tp) \
-    void trace(const tp& object, const std::string& name, int width) override;
+    //--------------------------------------------------
+    // SystemC 2.1.v1
 
-    void write_comment(const std::string&) override;
-    void trace(const unsigned int&, const std::string&, const char**) override;
+    void write_comment(const std::string&) override {}
+    void trace(const unsigned int&, const std::string&, const char**) override {}
+
+#define DECL_TRACE_METHOD_A(tp) \
+    void trace(const tp& object, const std::string& name) override {}
+#define DECL_TRACE_METHOD_B(tp) \
+    void trace(const tp& object, const std::string& name, int width) override {}
 
     // clang-format off
     // Formatting matches that of sc_trace.h
diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp
index 06ef3be8f..f6845df70 100644
--- a/src/V3EmitCMake.cpp
+++ b/src/V3EmitCMake.cpp
@@ -158,10 +158,6 @@ class CMakeEmitter final {
         if (v3Global.opt.trace()) {
             global.emplace_back("${VERILATOR_ROOT}/include/" + v3Global.opt.traceSourceBase()
                                 + "_c.cpp");
-            if (v3Global.opt.systemC()) {
-                global.emplace_back("${VERILATOR_ROOT}/include/" + v3Global.opt.traceSourceLang()
-                                    + ".cpp");
-            }
         }
         if (v3Global.usesTiming()) {
             global.emplace_back("${VERILATOR_ROOT}/include/verilated_timing.cpp");
diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp
index eefba5e92..26083c2f0 100644
--- a/src/V3EmitMk.cpp
+++ b/src/V3EmitMk.cpp
@@ -105,9 +105,6 @@ public:
                     if (v3Global.opt.coverage()) putMakeClassEntry(of, "verilated_cov.cpp");
                     if (v3Global.opt.trace()) {
                         putMakeClassEntry(of, v3Global.opt.traceSourceBase() + "_c.cpp");
-                        if (v3Global.opt.systemC()) {
-                            putMakeClassEntry(of, v3Global.opt.traceSourceLang() + ".cpp");
-                        }
                     }
                     if (v3Global.usesTiming()) putMakeClassEntry(of, "verilated_timing.cpp");
                     if (v3Global.opt.threads()) putMakeClassEntry(of, "verilated_threads.cpp");

From 468a33b61cec281f2178fe18298805b50e50b45a Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 29 Nov 2022 22:44:37 -0500
Subject: [PATCH 111/156] Move SystemC requirement out of .cpp files (#3507)

---
 include/verilated.cpp      | 52 ++++++++++----------------------------
 include/verilated.h        | 35 +++++++++++++++++++++++--
 include/verilated_fst_sc.h |  2 +-
 include/verilated_vcd_sc.h |  2 +-
 4 files changed, 48 insertions(+), 43 deletions(-)

diff --git a/include/verilated.cpp b/include/verilated.cpp
index ad7570598..544baa478 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -2429,44 +2429,6 @@ void VerilatedContext::timeunit(int value) VL_MT_SAFE {
     const VerilatedLockGuard lock{m_mutex};
     m_s.m_timeunit = value;
 }
-void VerilatedContext::timeprecision(int value) VL_MT_SAFE {
-    if (value < 0) value = -value;  // Stored as 0..15
-#ifdef SYSTEMC_VERSION
-    int sc_prec = 99;
-#endif
-    {
-        const VerilatedLockGuard lock{m_mutex};
-        m_s.m_timeprecision = value;
-#ifdef SYSTEMC_VERSION
-        const sc_time sc_res = sc_get_time_resolution();
-        if (sc_res == sc_time(1, SC_SEC)) {
-            sc_prec = 0;
-        } else if (sc_res == sc_time(1, SC_MS)) {
-            sc_prec = 3;
-        } else if (sc_res == sc_time(1, SC_US)) {
-            sc_prec = 6;
-        } else if (sc_res == sc_time(1, SC_NS)) {
-            sc_prec = 9;
-        } else if (sc_res == sc_time(1, SC_PS)) {
-            sc_prec = 12;
-        } else if (sc_res == sc_time(1, SC_FS)) {
-            sc_prec = 15;
-        }
-    }
-    if (VL_UNLIKELY(value != sc_prec)) {
-        std::ostringstream msg;
-        msg << "SystemC's sc_set_time_resolution is 10^-" << sc_prec
-            << ", which does not match Verilog timeprecision 10^-" << value
-            << ". Suggest use 'sc_set_time_resolution(" << vl_time_str(value)
-            << ")', or Verilator '--timescale-override " << vl_time_str(sc_prec) << "/"
-            << vl_time_str(sc_prec) << "'";
-        const std::string msgs = msg.str();
-        VL_FATAL_MT("", 0, "", msgs.c_str());
-    }
-#else
-    }
-#endif
-}
 const char* VerilatedContext::timeunitString() const VL_MT_SAFE { return vl_time_str(timeunit()); }
 const char* VerilatedContext::timeprecisionString() const VL_MT_SAFE {
     return vl_time_str(timeprecision());
@@ -2883,7 +2845,19 @@ void Verilated::overWidthError(const char* signame) VL_MT_SAFE {
     VL_UNREACHABLE;
 }
 
-void Verilated::scTraceBeforeElaboration() VL_MT_SAFE {
+void Verilated::scTimePrecisionError(int sc_prec, int vl_prec) VL_MT_SAFE {
+    std::ostringstream msg;
+    msg << "SystemC's sc_set_time_resolution is 10^-" << sc_prec
+        << ", which does not match Verilog timeprecision 10^-" << vl_prec
+        << ". Suggest use 'sc_set_time_resolution(" << vl_time_str(vl_prec)
+        << ")', or Verilator '--timescale-override " << vl_time_str(sc_prec) << "/"
+        << vl_time_str(sc_prec) << "'";
+    const std::string msgs = msg.str();
+    VL_FATAL_MT("", 0, "", msgs.c_str());
+    VL_UNREACHABLE;
+}
+
+void Verilated::scTraceBeforeElaborationError() VL_MT_SAFE {
     // Slowpath - Called only when trace file opened before SystemC elaboration
     VL_FATAL_MT("unknown", 0, "",
                 "%Error: Verilated*Sc::open(...) was called before sc_core::sc_start(). "
diff --git a/include/verilated.h b/include/verilated.h
index aaab1dc37..81c174774 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -505,7 +505,7 @@ public:
     /// Get time precision as power-of-ten
     int timeprecision() const VL_MT_SAFE { return -m_s.m_timeprecision; }
     /// Return time precision as power-of-ten
-    void timeprecision(int value) VL_MT_SAFE;
+    inline void timeprecision(int value) VL_MT_SAFE;
     /// Get time precision as IEEE-standard text
     const char* timeprecisionString() const VL_MT_SAFE;
 
@@ -861,7 +861,8 @@ public:
     // Internal: Throw signal assertion
     static void nullPointerError(const char* filename, int linenum) VL_ATTR_NORETURN VL_MT_SAFE;
     static void overWidthError(const char* signame) VL_ATTR_NORETURN VL_MT_SAFE;
-    static void scTraceBeforeElaboration() VL_ATTR_NORETURN VL_MT_SAFE;
+    static void scTimePrecisionError(int sc_prec, int vl_prec) VL_ATTR_NORETURN VL_MT_SAFE;
+    static void scTraceBeforeElaborationError() VL_ATTR_NORETURN VL_MT_SAFE;
 
     // Internal: Get and set DPI context
     static const VerilatedScope* dpiScope() VL_MT_SAFE { return t_s.t_dpiScopep; }
@@ -911,5 +912,35 @@ int VerilatedContext::debug() VL_MT_SAFE { return Verilated::debug(); }
 
 //======================================================================
 
+void VerilatedContext::timeprecision(int value) VL_MT_SAFE {
+    if (value < 0) value = -value;  // Stored as 0..15
+#if VM_SC
+    int sc_prec = 99;
+#endif
+    {
+        const VerilatedLockGuard lock{m_mutex};
+        m_s.m_timeprecision = value;
+#if VM_SC
+        const sc_time sc_res = sc_get_time_resolution();
+        if (sc_res == sc_time(1, SC_SEC)) {
+            sc_prec = 0;
+        } else if (sc_res == sc_time(1, SC_MS)) {
+            sc_prec = 3;
+        } else if (sc_res == sc_time(1, SC_US)) {
+            sc_prec = 6;
+        } else if (sc_res == sc_time(1, SC_NS)) {
+            sc_prec = 9;
+        } else if (sc_res == sc_time(1, SC_PS)) {
+            sc_prec = 12;
+        } else if (sc_res == sc_time(1, SC_FS)) {
+            sc_prec = 15;
+        }
+#endif
+    }
+#if VM_SC
+    if (VL_UNLIKELY(value != sc_prec)) Verilated::scTimePrecisionError(sc_prec, value);
+#endif
+}
+
 #undef VERILATOR_VERILATED_H_INTERNAL_
 #endif  // Guard
diff --git a/include/verilated_fst_sc.h b/include/verilated_fst_sc.h
index 82c0a0003..f65342146 100644
--- a/include/verilated_fst_sc.h
+++ b/include/verilated_fst_sc.h
@@ -67,7 +67,7 @@ public:
     // Note: this is not a virtual function in the base class, so no 'override'
     virtual void open(const char* filename) VL_MT_SAFE {
         if (VL_UNLIKELY(!sc_core::sc_get_curr_simcontext()->elaboration_done())) {
-            Verilated::scTraceBeforeElaboration();
+            Verilated::scTraceBeforeElaborationError();
         }
         VerilatedFstC::open(filename);
     }
diff --git a/include/verilated_vcd_sc.h b/include/verilated_vcd_sc.h
index ec8023f10..2905a37cf 100644
--- a/include/verilated_vcd_sc.h
+++ b/include/verilated_vcd_sc.h
@@ -66,7 +66,7 @@ public:
     // Override VerilatedVcdC. Must be called after starting simulation.
     void open(const char* filename) override VL_MT_SAFE {
         if (VL_UNLIKELY(!sc_core::sc_get_curr_simcontext()->elaboration_done())) {
-            Verilated::scTraceBeforeElaboration();
+            Verilated::scTraceBeforeElaborationError();
         }
         VerilatedVcdC::open(filename);
     }

From 073dc03adc78b815e00ede017b8c2c640b16decd Mon Sep 17 00:00:00 2001
From: Ryszard Rozak <rrozak@antmicro.com>
Date: Wed, 30 Nov 2022 12:42:48 +0100
Subject: [PATCH 112/156] Support super.new calls (#3789)

---
 src/V3AstNodeOther.h                |   8 +--
 src/V3EmitCFunc.cpp                 |   6 +-
 src/V3EmitCFunc.h                   |  42 ++++++++----
 src/V3Task.cpp                      |   4 +-
 src/V3Width.cpp                     |  40 ++++++-----
 test_regress/t/t_class_super_new.pl |  20 ++++++
 test_regress/t/t_class_super_new.v  | 101 ++++++++++++++++++++++++++++
 7 files changed, 183 insertions(+), 38 deletions(-)
 create mode 100755 test_regress/t/t_class_super_new.pl
 create mode 100644 test_regress/t/t_class_super_new.v

diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index a3ae3b246..44c22b42f 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -550,7 +550,7 @@ private:
     string m_cname;  // C name, for dpiExports
     string m_rtnType;  // void, bool, or other return type
     string m_argTypes;  // Argument types
-    string m_ctorInits;  // Constructor sub-class inits
+    string m_baseCtors;  // Base class constructor
     string m_ifdef;  // #ifdef symbol around this function
     VBoolOrUnknown m_isConst;  // Function is declared const (*this not changed)
     bool m_isStatic : 1;  // Function is static (no need for a 'this' pointer)
@@ -611,7 +611,7 @@ public:
     bool same(const AstNode* samep) const override {
         const AstCFunc* const asamep = static_cast<const AstCFunc*>(samep);
         return ((isTrace() == asamep->isTrace()) && (rtnTypeVoid() == asamep->rtnTypeVoid())
-                && (argTypes() == asamep->argTypes()) && (ctorInits() == asamep->ctorInits())
+                && (argTypes() == asamep->argTypes()) && (baseCtors() == asamep->baseCtors())
                 && isLoose() == asamep->isLoose()
                 && (!(dpiImportPrototype() || dpiExportImpl()) || name() == asamep->name()));
     }
@@ -644,8 +644,8 @@ public:
     void funcPublic(bool flag) { m_funcPublic = flag; }
     void argTypes(const string& str) { m_argTypes = str; }
     string argTypes() const { return m_argTypes; }
-    void ctorInits(const string& str) { m_ctorInits = str; }
-    string ctorInits() const { return m_ctorInits; }
+    void baseCtors(const string& str) { m_baseCtors = str; }
+    string baseCtors() const { return m_baseCtors; }
     void ifdef(const string& str) { m_ifdef = str; }
     string ifdef() const { return m_ifdef; }
     bool isConstructor() const { return m_isConstructor; }
diff --git a/src/V3EmitCFunc.cpp b/src/V3EmitCFunc.cpp
index 128c70351..214d8d9b1 100644
--- a/src/V3EmitCFunc.cpp
+++ b/src/V3EmitCFunc.cpp
@@ -422,11 +422,7 @@ void EmitCFunc::emitCCallArgs(const AstNodeCCall* nodep, const string& selfPoint
         puts(nodep->argTypes());
         comma = true;
     }
-    for (AstNode* subnodep = nodep->argsp(); subnodep; subnodep = subnodep->nextp()) {
-        if (comma) puts(", ");
-        iterate(subnodep);
-        comma = true;
-    }
+    putCommaIterateNext(nodep->argsp(), comma);
     puts(")");
 }
 
diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h
index 5ab0211af..e19a42995 100644
--- a/src/V3EmitCFunc.h
+++ b/src/V3EmitCFunc.h
@@ -205,6 +205,13 @@ public:
         m_emitConstInit = true;
         iterate(initp);
     }
+    void putCommaIterateNext(AstNode* nodep, bool comma = false) {
+        for (AstNode* subnodep = nodep; subnodep; subnodep = subnodep->nextp()) {
+            if (comma) puts(", ");
+            iterate(subnodep);
+            comma = true;
+        }
+    }
 
     // VISITORS
     using EmitCConstInit::visit;
@@ -221,11 +228,24 @@ public:
         if (nodep->isInline()) puts("VL_INLINE_OPT ");
         emitCFuncHeader(nodep, m_modp, /* withScope: */ true);
 
-        // TODO perhaps better to have a new AstCCtorInit so we can pass arguments
-        // rather than requiring a string here
-        if (!nodep->ctorInits().empty()) {
+        if (!nodep->baseCtors().empty()) {
             puts(": ");
-            puts(nodep->ctorInits());
+            puts(nodep->baseCtors());
+            puts("(vlSymsp");
+            // Find call to super.new to get the arguments
+            for (AstNode* stmtp = nodep->stmtsp(); stmtp; stmtp = stmtp->nextp()) {
+                AstNode* exprp;
+                if (VN_IS(stmtp, StmtExpr)) {
+                    exprp = VN_CAST(stmtp, StmtExpr)->exprp();
+                } else {
+                    exprp = stmtp;
+                }
+                if (AstCNew* const newRefp = VN_CAST(exprp, CNew)) {
+                    putCommaIterateNext(newRefp->argsp(), true);
+                    break;
+                }
+            }
+            puts(")");
         }
         puts(" {\n");
 
@@ -417,15 +437,13 @@ public:
         iterate(nodep->exprp());
     }
     void visit(AstCNew* nodep) override {
-        bool comma = false;
-        puts("VL_NEW(" + prefixNameProtect(nodep->dtypep()) + ", ");
-        puts("vlSymsp");  // TODO make this part of argsp, and eliminate when unnecessary
-        if (nodep->argsp()) comma = true;
-        for (AstNode* subnodep = nodep->argsp(); subnodep; subnodep = subnodep->nextp()) {
-            if (comma) puts(", ");
-            iterate(subnodep);
-            comma = true;
+        if (VN_IS(nodep->dtypep(), VoidDType)) {
+            // super.new case
+            return;
         }
+        // assignment case
+        puts("VL_NEW(" + prefixNameProtect(nodep->dtypep()) + ", vlSymsp");
+        putCommaIterateNext(nodep->argsp(), true);
         puts(")");
     }
     void visit(AstCMethodHard* nodep) override {
diff --git a/src/V3Task.cpp b/src/V3Task.cpp
index 73a93679d..84cf450d3 100644
--- a/src/V3Task.cpp
+++ b/src/V3Task.cpp
@@ -1181,8 +1181,8 @@ private:
             cfuncp->isConstructor(true);
             AstClass* const classp = m_statep->getClassp(nodep);
             if (classp->extendsp()) {
-                cfuncp->ctorInits(EmitCBaseVisitor::prefixNameProtect(classp->extendsp()->classp())
-                                  + "(vlSymsp)");
+                cfuncp->baseCtors(
+                    EmitCBaseVisitor::prefixNameProtect(classp->extendsp()->classp()));
             }
         }
         if (cfuncp->dpiExportImpl()) cfuncp->cname(nodep->cname());
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index ab687a457..6c8578780 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3555,22 +3555,32 @@ private:
 
     void visit(AstNew* nodep) override {
         if (nodep->didWidth()) return;
-        AstClassRefDType* const refp
-            = m_vup ? VN_CAST(m_vup->dtypeNullSkipRefp(), ClassRefDType) : nullptr;
-        if (!refp) {  // e.g. int a = new;
-            nodep->v3error("new() not expected in this context");
-            return;
-        }
-        nodep->dtypep(refp);
+        AstClass* classp = nullptr;
+        if (VN_IS(nodep->backp(), Assign)) {  // assignment case
+            AstClassRefDType* const refp
+                = m_vup ? VN_CAST(m_vup->dtypeNullSkipRefp(), ClassRefDType) : nullptr;
+            if (!refp) {  // e.g. int a = new;
+                nodep->v3error("new() not expected in this context");
+                return;
+            }
+            nodep->dtypep(refp);
 
-        AstClass* const classp = refp->classp();
-        UASSERT_OBJ(classp, nodep, "Unlinked");
-        if (AstNodeFTask* const ftaskp = VN_CAST(classp->findMember("new"), Func)) {
-            nodep->taskp(ftaskp);
-            nodep->classOrPackagep(classp);
-        } else {
-            // Either made explicitly or V3LinkDot made implicitly
-            classp->v3fatalSrc("Can't find class's new");
+            classp = refp->classp();
+            UASSERT_OBJ(classp, nodep, "Unlinked");
+            if (AstNodeFTask* const ftaskp = VN_CAST(classp->findMember("new"), Func)) {
+                nodep->taskp(ftaskp);
+                nodep->classOrPackagep(classp);
+            } else {
+                // Either made explicitly or V3LinkDot made implicitly
+                classp->v3fatalSrc("Can't find class's new");
+            }
+        } else {  // super.new case
+            // in this case class and taskp() should be properly linked in V3LinkDot.cpp during
+            // "super" reference resolution
+            classp = VN_CAST(nodep->classOrPackagep(), Class);
+            UASSERT_OBJ(classp, nodep, "Unlinked classOrPackagep()");
+            UASSERT_OBJ(nodep->taskp(), nodep, "Unlinked taskp()");
+            nodep->dtypeFrom(nodep->taskp());
         }
         if (classp->isVirtual()) {
             nodep->v3error(
diff --git a/test_regress/t/t_class_super_new.pl b/test_regress/t/t_class_super_new.pl
new file mode 100755
index 000000000..bf4e4ce9f
--- /dev/null
+++ b/test_regress/t/t_class_super_new.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile();
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_class_super_new.v b/test_regress/t/t_class_super_new.v
new file mode 100644
index 000000000..5cecc1ca6
--- /dev/null
+++ b/test_regress/t/t_class_super_new.v
@@ -0,0 +1,101 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+
+class Foo;
+   int x;
+   function new;
+      this.x = 10;
+   endfunction
+endclass
+
+class Bar extends Foo;
+   function new;
+      super.new;
+   endfunction
+endclass
+
+class BarUnusedArg extends Foo;
+   function new (int a);
+      super.new;
+   endfunction
+endclass
+
+class FooArg;
+   int x;
+   function new (int a);
+      this.x = a;
+   endfunction
+endclass
+
+class BarArg extends FooArg;
+   function new (int a);
+      super.new(a);
+   endfunction
+endclass
+
+class BarExpr extends FooArg;
+   function new (int a, string b);
+      super.new(a + b.len());
+   endfunction
+endclass
+
+class Foo2Args;
+   int x;
+   function new (int a, int b);
+      this.x = a + b;
+   endfunction
+endclass
+
+class Bar2Args extends Foo2Args;
+   function new (int a, int b);
+      super.new(a, b);
+   endfunction
+endclass
+
+module t (/*AUTOARG*/
+   );
+
+   class FooInModule;
+      int x;
+      function new;
+         this.x = 15;
+      endfunction
+   endclass
+
+   class BarInModule extends FooInModule;
+      function new;
+         super.new;
+      endfunction
+   endclass
+
+   Bar bar;
+   BarInModule barInModule;
+   BarUnusedArg barUnusedArg;
+   BarArg barArg;
+   BarExpr barExpr;
+   Bar2Args bar2Args;
+
+   initial begin
+      bar = new;
+      `checkh(bar.x, 10);
+      barInModule = new;
+      `checkh(barInModule.x, 15);
+      barUnusedArg = new(2);
+      `checkh(barUnusedArg.x, 10);
+      barArg = new(2);
+      `checkh(barArg.x, 2);
+      barExpr = new (7, "ABCDEFGHI");
+      `checkh(barExpr.x, 16);
+      bar2Args = new(2, 12);
+      `checkh(bar2Args.x, 14);
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

From 355c4f76d08cc3a5c7945e5843a096e5babc2828 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 30 Nov 2022 07:40:06 -0500
Subject: [PATCH 113/156] Add error when super.new is not first statement
 (#3789)

---
 src/V3LinkParse.cpp                           | 26 +++++++++++++++
 test_regress/t/t_class_super_new.pl           |  5 +--
 .../t/t_class_super_new_bad_nfirst.out        |  7 ++++
 .../t/t_class_super_new_bad_nfirst.pl         | 19 +++++++++++
 test_regress/t/t_class_super_new_bad_nfirst.v | 32 +++++++++++++++++++
 5 files changed, 87 insertions(+), 2 deletions(-)
 create mode 100644 test_regress/t/t_class_super_new_bad_nfirst.out
 create mode 100755 test_regress/t/t_class_super_new_bad_nfirst.pl
 create mode 100644 test_regress/t/t_class_super_new_bad_nfirst.v

diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index 5d844725c..e26272673 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -551,6 +551,32 @@ private:
         cleanFileline(nodep);
         iterateChildren(nodep);
     }
+    void visit(AstDot* nodep) override {
+        cleanFileline(nodep);
+        iterateChildren(nodep);
+        if (VN_IS(nodep->lhsp(), ParseRef) && nodep->lhsp()->name() == "super"
+            && VN_IS(nodep->rhsp(), New)) {
+            // Look for other statements until hit function start
+            AstNode* scanp = nodep;
+            // Skip over the New's statement
+            for (; scanp && !VN_IS(scanp, StmtExpr); scanp = scanp->backp()) {}
+            if (VN_IS(scanp, StmtExpr)) {  // Ignore warnign if something not understood
+                scanp = scanp->backp();
+                for (; scanp; scanp = scanp->backp()) {
+                    if (VN_IS(scanp, NodeStmt) || VN_IS(scanp, NodeModule)
+                        || VN_IS(scanp, NodeFTask))
+                        break;
+                }
+                if (!VN_IS(scanp, NodeFTask)) {
+                    nodep->rhsp()->v3error(
+                        "'super.new' not first statement in new function (IEEE 1800-2017 8.15)\n"
+                        << nodep->rhsp()->warnContextPrimary() << scanp->warnOther()
+                        << "... Location of earlier statement\n"
+                        << scanp->warnContextSecondary());
+                }
+            }
+        }
+    }
     void visit(AstPrintTimeScale* nodep) override {
         // Inlining may change hierarchy, so just save timescale where needed
         cleanFileline(nodep);
diff --git a/test_regress/t/t_class_super_new.pl b/test_regress/t/t_class_super_new.pl
index bf4e4ce9f..aabcde63e 100755
--- a/test_regress/t/t_class_super_new.pl
+++ b/test_regress/t/t_class_super_new.pl
@@ -2,7 +2,7 @@
 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
-# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# Copyright 2020 by Wilson Snyder. This program is free software; you
 # can redistribute it and/or modify it under the terms of either the GNU
 # Lesser General Public License Version 3 or the Perl Artistic License
 # Version 2.0.
@@ -10,7 +10,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-compile();
+compile(
+    );
 
 execute(
     check_finished => 1,
diff --git a/test_regress/t/t_class_super_new_bad_nfirst.out b/test_regress/t/t_class_super_new_bad_nfirst.out
new file mode 100644
index 000000000..28662df24
--- /dev/null
+++ b/test_regress/t/t_class_super_new_bad_nfirst.out
@@ -0,0 +1,7 @@
+%Error: t/t_class_super_new_bad_nfirst.v:18:13: 'super.new' not first statement in new function (IEEE 1800-2017 8.15)
+   18 |       super.new(imemberc);   
+      |             ^~~
+        t/t_class_super_new_bad_nfirst.v:17:16: ... Location of earlier statement
+   17 |       imemberc = 10;
+      |                ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_class_super_new_bad_nfirst.pl b/test_regress/t/t_class_super_new_bad_nfirst.pl
new file mode 100755
index 000000000..8b81d9f75
--- /dev/null
+++ b/test_regress/t/t_class_super_new_bad_nfirst.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+compile(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_class_super_new_bad_nfirst.v b/test_regress/t/t_class_super_new_bad_nfirst.v
new file mode 100644
index 000000000..8e1197305
--- /dev/null
+++ b/test_regress/t/t_class_super_new_bad_nfirst.v
@@ -0,0 +1,32 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class Base;
+   int imemberb;
+   function new(int adder);
+      imemberb = 5 + adder;
+   endfunction
+endclass
+
+class Cls extends Base;
+   int imemberc;
+   function new();
+      imemberc = 10;
+      super.new(imemberc);  // BAD not first
+   endfunction
+endclass
+
+module t (/*AUTOARG*/);
+   initial begin
+      Cls   c;
+      c = new;
+      if (c.imemberc != 10) $stop;
+      if (c.imemberb != 5) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule

From 42e4e18ec80ce25fea0422f254550e98ebd23eae Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 30 Nov 2022 18:13:57 -0500
Subject: [PATCH 114/156] Support multiple $dumpvar identifiers

---
 src/verilog.y                  | 2 +-
 test_regress/t/t_trace_two_a.v | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/verilog.y b/src/verilog.y
index 289b4e6fb..5b4c9cb96 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3869,7 +3869,7 @@ system_t_call<nodeStmtp>:       // IEEE: system_tf_call (as task)
         |       yD_DUMPVARS parenE                      { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::VARS,
                                                                               new AstConst{$<fl>1, 0}}; }
         |       yD_DUMPVARS '(' expr ')'                { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::VARS, $3}; }
-        |       yD_DUMPVARS '(' expr ',' idDotted ')'   { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::VARS, $3}; DEL($5); }
+        |       yD_DUMPVARS '(' expr ',' exprList ')'   { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::VARS, $3}; DEL($5); }
         |       yD_DUMPALL parenE                       { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::ALL}; }
         |       yD_DUMPALL '(' expr ')'                 { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::ALL}; DEL($3); }
         |       yD_DUMPFLUSH parenE                     { $$ = new AstDumpCtl{$<fl>1, VDumpCtlType::FLUSH}; }
diff --git a/test_regress/t/t_trace_two_a.v b/test_regress/t/t_trace_two_a.v
index 83f3ed363..b6a310870 100644
--- a/test_regress/t/t_trace_two_a.v
+++ b/test_regress/t/t_trace_two_a.v
@@ -33,6 +33,8 @@ module t (/*AUTOARG*/
 `ifdef TEST_DUMP
       $dumpfile(filename);
       $dumpvars(0);  // Intentionally no ", top" for parsing coverage with just (expr)
+      $dumpvars(1, top);  // Intentionally checking parsing coverage
+      $dumpvars(1, top, top);  // Intentionally checking parsing coverage
       $dumplimit(10 * 1024 * 1024);
 `elsif TEST_DUMPPORTS
       $dumpports(top, filename);

From 4f4c26383c5827694347af086b356e438155274f Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 30 Nov 2022 19:17:28 -0500
Subject: [PATCH 115/156] Support unpacked byte assignment from strings.

---
 src/V3Width.cpp                 | 33 +++++++++++++++++++++++++++++++++
 test_regress/t/t_string_byte.pl | 21 +++++++++++++++++++++
 test_regress/t/t_string_byte.v  | 29 +++++++++++++++++++++++++++++
 3 files changed, 83 insertions(+)
 create mode 100755 test_regress/t/t_string_byte.pl
 create mode 100644 test_regress/t/t_string_byte.v

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 6c8578780..604ae8497 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -6082,6 +6082,39 @@ private:
         // Check using assignment-like context rules
         // if (debug()) nodep->dumpTree("-  checkass: ");
         UASSERT_OBJ(stage == FINAL, nodep, "Bad width call");
+        // Create unpacked byte from string perl IEEE 1800-2017 5.9
+        if (AstConst* constp = VN_CAST(rhsp, Const)) {
+            if (const AstUnpackArrayDType* const arrayp
+                = VN_CAST(lhsDTypep->skipRefp(), UnpackArrayDType)) {
+                if (AstBasicDType* basicp = VN_CAST(arrayp->subDTypep()->skipRefp(), BasicDType)) {
+                    if (basicp->width() == 8 && constp->num().isFromString()) {
+                        AstInitArray* newp = new AstInitArray{
+                            constp->fileline(), lhsDTypep,
+                            new AstConst{constp->fileline(), AstConst::WidthedValue{}, 8, 0}};
+                        for (int aindex = arrayp->lo(); aindex <= arrayp->hi(); ++aindex) {
+                            int cindex = arrayp->declRange().littleEndian()
+                                             ? (arrayp->hi() - aindex)
+                                             : (aindex - arrayp->lo());
+                            V3Number selected{constp, 8};
+                            selected.opSel(constp->num(), cindex * 8 + 7, cindex * 8);
+                            UINFO(0, "   aindex=" << aindex << "  cindex=" << cindex
+                                                  << "  c=" << selected << endl);
+                            if (!selected.isFourState()) {
+                                if (const uint32_t c = selected.toUInt()) {
+                                    newp->addIndexValuep(
+                                        aindex, new AstConst{constp->fileline(),
+                                                             AstConst::WidthedValue{}, 8, c});
+                                }
+                            }
+                        }
+                        UINFO(6, "   unpackFromString: " << nodep << endl);
+                        rhsp->replaceWith(newp);
+                        VL_DO_DANGLING(pushDeletep(rhsp), rhsp);
+                        rhsp = newp;
+                    }
+                }
+            }
+        }
         // We iterate and size the RHS based on the result of RHS evaluation
         checkClassAssign(nodep, side, rhsp, lhsDTypep);
         const bool lhsStream
diff --git a/test_regress/t/t_string_byte.pl b/test_regress/t/t_string_byte.pl
new file mode 100755
index 000000000..1aa73f80a
--- /dev/null
+++ b/test_regress/t/t_string_byte.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_string_byte.v b/test_regress/t/t_string_byte.v
new file mode 100644
index 000000000..58ad58b47
--- /dev/null
+++ b/test_regress/t/t_string_byte.v
@@ -0,0 +1,29 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+
+module t(/*AUTOARG*/);
+
+   // Unpacked byte from string IEEE 1800-2017 5.9
+   byte bh[3:0] = "hi2";
+   byte bl[0:3] = "lo2";
+
+   initial begin
+      `checkh(bh[0], "2");
+      `checkh(bh[1], "i");
+      `checkh(bh[2], "h");
+      `checkh(bh[3], 0);
+      `checkh(bl[0], 0);
+      `checkh(bl[1], "l");
+      `checkh(bl[2], "o");
+      `checkh(bl[3], "2");
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule

From d87ef8394ac7490f7dff3c093c2f56fd921f7388 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 30 Nov 2022 19:42:21 -0500
Subject: [PATCH 116/156] Fix CASEINCOMPLETE when covers all enum values
 (#3745) (#3782).

Co-authored-by: "G-A. Kamendje" <gkamendje@gmail.com>
---
 Changes                                       |  1 +
 docs/CONTRIBUTORS                             |  1 +
 docs/guide/warnings.rst                       |  6 +++
 src/V3Case.cpp                                | 45 +++++++++++++++----
 test_regress/t/t_case_enum_complete.pl        | 19 ++++++++
 test_regress/t/t_case_enum_complete.v         | 20 +++++++++
 test_regress/t/t_case_enum_incomplete_bad.out |  6 +++
 test_regress/t/t_case_enum_incomplete_bad.pl  | 20 +++++++++
 test_regress/t/t_case_enum_incomplete_bad.v   | 19 ++++++++
 9 files changed, 129 insertions(+), 8 deletions(-)
 create mode 100755 test_regress/t/t_case_enum_complete.pl
 create mode 100644 test_regress/t/t_case_enum_complete.v
 create mode 100644 test_regress/t/t_case_enum_incomplete_bad.out
 create mode 100755 test_regress/t/t_case_enum_incomplete_bad.pl
 create mode 100644 test_regress/t/t_case_enum_incomplete_bad.v

diff --git a/Changes b/Changes
index 5e6743357..3dfd580ca 100644
--- a/Changes
+++ b/Changes
@@ -23,6 +23,7 @@ Verilator 5.003 devel
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Change ENDLABEL from warning into an error.
 * Deprecate verilated_fst_sc.cpp and verilated_vcd_sc.cpp.
+* Fix CASEINCOMPLETE when covers all enum values (#3745) (#3782). [Guy-Armand Kamendje]
 * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
 * Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
 * Fix tracing parameters overridden with -G (#3723). [Iztok Jeras]
diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS
index 517d03f61..29af74174 100644
--- a/docs/CONTRIBUTORS
+++ b/docs/CONTRIBUTORS
@@ -36,6 +36,7 @@ Glen Gibb
 Graham Rushton
 Guokai Chen
 Gustav Svensk
+G-A. Kamendje
 Harald Heckmann
 Howard Su
 Huang Rui
diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst
index b91ed900a..071fc01b8 100644
--- a/docs/guide/warnings.rst
+++ b/docs/guide/warnings.rst
@@ -253,6 +253,12 @@ List Of Warnings
    :code:`default: ;` so that any design assumption violations will be
    discovered in simulation.
 
+   Unique case statements that select on an enumerated variable, where all
+   of the enumerated values are covered by case items, are considered
+   complete even if illegal non-enumerated values are not covered by the
+   case statement.  To check that illegal values are not hit, use
+   :vlopt:`--assert` (see IEEE 1800-2017 12.5.3).
+
    Ignoring this warning will only suppress the lint check, it will
    simulate correctly.
 
diff --git a/src/V3Case.cpp b/src/V3Case.cpp
index a8ffe9ae0..dc378d51f 100644
--- a/src/V3Case.cpp
+++ b/src/V3Case.cpp
@@ -139,7 +139,33 @@ private:
     std::array<AstNode*, 1 << CASE_OVERLAP_WIDTH> m_valueItem;
 
     // METHODS
-
+    bool caseIsEnumComplete(AstCase* nodep, uint32_t numCases) {
+        // Return true if case is across an enum, and every value in the case
+        // statement corresponds to one of the enum values
+        if (!nodep->uniquePragma() && !nodep->unique0Pragma()) return false;
+        AstEnumDType* const enumDtp
+            = VN_CAST(nodep->exprp()->dtypep()->skipRefToEnump(), EnumDType);
+        if (!enumDtp) return false;  // Case isn't enum
+        AstBasicDType* const basicp = enumDtp->subDTypep()->basicp();
+        if (!basicp) return false;  // Not simple type (perhaps IEEE illegal)
+        if (basicp->width() > 32) return false;
+        // Find all case values into a set
+        std::set<uint32_t> caseSet;
+        for (uint32_t i = 0; i < numCases; ++i) {  // All case items
+            if (m_valueItem[i]) caseSet.emplace(i);
+        }
+        // Find all enum values into a set
+        std::set<uint32_t> enumSet;
+        for (AstEnumItem* itemp = enumDtp->itemsp(); itemp;
+             itemp = VN_AS(itemp->nextp(), EnumItem)) {
+            AstConst* const econstp = VN_AS(itemp->valuep(), Const);
+            const uint32_t val = econstp->toUInt();
+            // UINFO(9, "Complete enum item " << val << ": " << itemp << endl);
+            enumSet.emplace(val);
+        }
+        // If sets match, all covered
+        return (caseSet == enumSet);
+    }
     bool isCaseTreeFast(AstCase* nodep) {
         int width = 0;
         bool opaque = false;
@@ -227,15 +253,18 @@ private:
                 }
             }
         }
-        for (uint32_t i = 0; i < numCases; ++i) {
-            if (!m_valueItem[i]) {
-                nodep->v3warn(CASEINCOMPLETE, "Case values incompletely covered "
-                                              "(example pattern 0x"
-                                                  << std::hex << i << ")");
-                m_caseNoOverlapsAllCovered = false;
-                return false;
+        if (!caseIsEnumComplete(nodep, numCases)) {
+            for (uint32_t i = 0; i < numCases; ++i) {
+                if (!m_valueItem[i]) {
+                    nodep->v3warn(CASEINCOMPLETE, "Case values incompletely covered "
+                                                  "(example pattern 0x"
+                                                      << std::hex << i << ")");
+                    m_caseNoOverlapsAllCovered = false;
+                    return false;
+                }
             }
         }
+
         if (m_caseItems <= 3
             // Avoid e.g. priority expanders from going crazy in expansion
             || (m_caseWidth >= 8 && (m_caseItems <= (m_caseWidth + 1)))) {
diff --git a/test_regress/t/t_case_enum_complete.pl b/test_regress/t/t_case_enum_complete.pl
new file mode 100755
index 000000000..c2379584a
--- /dev/null
+++ b/test_regress/t/t_case_enum_complete.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ["--lint-only -Wwarn-CASEINCOMPLETE"],
+    fails => 0,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_case_enum_complete.v b/test_regress/t/t_case_enum_complete.v
new file mode 100644
index 000000000..7ee354cfd
--- /dev/null
+++ b/test_regress/t/t_case_enum_complete.v
@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: SystemVerilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   enum logic [2:0] {S0, S1, S2} state;
+
+   initial begin
+      state = S1;
+
+      unique case (state)
+        S0: $stop;
+        S1: $finish;
+        S2: $stop;
+      endcase
+   end
+endmodule
diff --git a/test_regress/t/t_case_enum_incomplete_bad.out b/test_regress/t/t_case_enum_incomplete_bad.out
new file mode 100644
index 000000000..4a88a83dc
--- /dev/null
+++ b/test_regress/t/t_case_enum_incomplete_bad.out
@@ -0,0 +1,6 @@
+%Warning-CASEINCOMPLETE: t/t_case_enum_incomplete_bad.v:14:14: Case values incompletely covered (example pattern 0x1)
+   14 |       unique case (state)
+      |              ^~~~
+                         ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest
+                         ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message.
+%Error: Exiting due to
diff --git a/test_regress/t/t_case_enum_incomplete_bad.pl b/test_regress/t/t_case_enum_incomplete_bad.pl
new file mode 100755
index 000000000..1d5773686
--- /dev/null
+++ b/test_regress/t/t_case_enum_incomplete_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ['--assert'],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_case_enum_incomplete_bad.v b/test_regress/t/t_case_enum_incomplete_bad.v
new file mode 100644
index 000000000..b6f6bc740
--- /dev/null
+++ b/test_regress/t/t_case_enum_incomplete_bad.v
@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: SystemVerilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+
+   enum logic [2:0] {S0, S1, S2} state;
+
+   initial begin
+      state = S1;
+
+      unique case (state)
+        S0: $stop;
+        S2: $stop;
+      endcase
+   end
+endmodule

From 31d8b4cb8e7ba7c05ac12270cccd714f3a7bff17 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 30 Nov 2022 22:08:57 -0500
Subject: [PATCH 117/156] Internals: Rename AstNodeSystem*D etc. No functional
 change intended.

---
 src/V3AstNodeExpr.h | 56 ++++++++++++++++++++++-----------------------
 src/V3ParseImp.cpp  | 10 +++-----
 src/V3Width.cpp     |  4 ++--
 3 files changed, 33 insertions(+), 37 deletions(-)

diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index 77d881621..1d1a76769 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -135,13 +135,13 @@ protected:
 public:
     ASTGEN_MEMBERS_AstNodeStream;
 };
-class AstNodeSystemBiop VL_NOT_FINAL : public AstNodeBiop {
+class AstNodeSystemBiopD VL_NOT_FINAL : public AstNodeBiop {
 public:
-    AstNodeSystemBiop(VNType t, FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
+    AstNodeSystemBiopD(VNType t, FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : AstNodeBiop{t, fl, lhsp, rhsp} {
         dtypeSetDouble();
     }
-    ASTGEN_MEMBERS_AstNodeSystemBiop;
+    ASTGEN_MEMBERS_AstNodeSystemBiopD;
     bool cleanOut() const override { return false; }
     bool cleanLhs() const override { return false; }
     bool cleanRhs() const override { return false; }
@@ -388,13 +388,13 @@ public:
     int instrCount() const override { return widthInstrs(); }
     bool same(const AstNode*) const override { return true; }
 };
-class AstNodeSystemUniop VL_NOT_FINAL : public AstNodeUniop {
+class AstNodeSystemUniopD VL_NOT_FINAL : public AstNodeUniop {
 public:
-    AstNodeSystemUniop(VNType t, FileLine* fl, AstNodeExpr* lhsp)
+    AstNodeSystemUniopD(VNType t, FileLine* fl, AstNodeExpr* lhsp)
         : AstNodeUniop{t, fl, lhsp} {
         dtypeSetDouble();
     }
-    ASTGEN_MEMBERS_AstNodeSystemUniop;
+    ASTGEN_MEMBERS_AstNodeSystemUniopD;
     bool cleanOut() const override { return true; }
     bool cleanLhs() const override { return false; }
     bool sizeMattersLhs() const override { return false; }
@@ -3706,8 +3706,8 @@ public:
     int instrCount() const override { return widthInstrs() * 2; }
 };
 
-// === AstNodeSystemBiop ===
-class AstAtan2D final : public AstNodeSystemBiop {
+// === AstNodeSystemBiopD ===
+class AstAtan2D final : public AstNodeSystemBiopD {
 public:
     AstAtan2D(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_Atan2D(fl, lhsp, rhsp) {}
@@ -3721,7 +3721,7 @@ public:
     string emitVerilog() override { return "%f$atan2(%l,%r)"; }
     string emitC() override { return "atan2(%li,%ri)"; }
 };
-class AstHypotD final : public AstNodeSystemBiop {
+class AstHypotD final : public AstNodeSystemBiopD {
 public:
     AstHypotD(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
         : ASTGEN_SUPER_HypotD(fl, lhsp, rhsp) {}
@@ -4805,8 +4805,8 @@ public:
     int instrCount() const override { return 0; }
 };
 
-// === AstNodeSystemUniop ===
-class AstAcosD final : public AstNodeSystemUniop {
+// === AstNodeSystemUniopD ===
+class AstAcosD final : public AstNodeSystemUniopD {
 public:
     AstAcosD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_AcosD(fl, lhsp) {}
@@ -4817,7 +4817,7 @@ public:
     string emitVerilog() override { return "%f$acos(%l)"; }
     string emitC() override { return "acos(%li)"; }
 };
-class AstAcoshD final : public AstNodeSystemUniop {
+class AstAcoshD final : public AstNodeSystemUniopD {
 public:
     AstAcoshD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_AcoshD(fl, lhsp) {}
@@ -4828,7 +4828,7 @@ public:
     string emitVerilog() override { return "%f$acosh(%l)"; }
     string emitC() override { return "acosh(%li)"; }
 };
-class AstAsinD final : public AstNodeSystemUniop {
+class AstAsinD final : public AstNodeSystemUniopD {
 public:
     AstAsinD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_AsinD(fl, lhsp) {}
@@ -4839,7 +4839,7 @@ public:
     string emitVerilog() override { return "%f$asin(%l)"; }
     string emitC() override { return "asin(%li)"; }
 };
-class AstAsinhD final : public AstNodeSystemUniop {
+class AstAsinhD final : public AstNodeSystemUniopD {
 public:
     AstAsinhD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_AsinhD(fl, lhsp) {}
@@ -4850,7 +4850,7 @@ public:
     string emitVerilog() override { return "%f$asinh(%l)"; }
     string emitC() override { return "asinh(%li)"; }
 };
-class AstAtanD final : public AstNodeSystemUniop {
+class AstAtanD final : public AstNodeSystemUniopD {
 public:
     AstAtanD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_AtanD(fl, lhsp) {}
@@ -4861,7 +4861,7 @@ public:
     string emitVerilog() override { return "%f$atan(%l)"; }
     string emitC() override { return "atan(%li)"; }
 };
-class AstAtanhD final : public AstNodeSystemUniop {
+class AstAtanhD final : public AstNodeSystemUniopD {
 public:
     AstAtanhD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_AtanhD(fl, lhsp) {}
@@ -4872,7 +4872,7 @@ public:
     string emitVerilog() override { return "%f$atanh(%l)"; }
     string emitC() override { return "atanh(%li)"; }
 };
-class AstCeilD final : public AstNodeSystemUniop {
+class AstCeilD final : public AstNodeSystemUniopD {
 public:
     AstCeilD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_CeilD(fl, lhsp) {}
@@ -4883,7 +4883,7 @@ public:
     string emitVerilog() override { return "%f$ceil(%l)"; }
     string emitC() override { return "ceil(%li)"; }
 };
-class AstCosD final : public AstNodeSystemUniop {
+class AstCosD final : public AstNodeSystemUniopD {
 public:
     AstCosD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_CosD(fl, lhsp) {}
@@ -4894,7 +4894,7 @@ public:
     string emitVerilog() override { return "%f$cos(%l)"; }
     string emitC() override { return "cos(%li)"; }
 };
-class AstCoshD final : public AstNodeSystemUniop {
+class AstCoshD final : public AstNodeSystemUniopD {
 public:
     AstCoshD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_CoshD(fl, lhsp) {}
@@ -4905,7 +4905,7 @@ public:
     string emitVerilog() override { return "%f$cosh(%l)"; }
     string emitC() override { return "cosh(%li)"; }
 };
-class AstExpD final : public AstNodeSystemUniop {
+class AstExpD final : public AstNodeSystemUniopD {
 public:
     AstExpD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_ExpD(fl, lhsp) {}
@@ -4916,7 +4916,7 @@ public:
     string emitVerilog() override { return "%f$exp(%l)"; }
     string emitC() override { return "exp(%li)"; }
 };
-class AstFloorD final : public AstNodeSystemUniop {
+class AstFloorD final : public AstNodeSystemUniopD {
 public:
     AstFloorD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_FloorD(fl, lhsp) {}
@@ -4927,7 +4927,7 @@ public:
     string emitVerilog() override { return "%f$floor(%l)"; }
     string emitC() override { return "floor(%li)"; }
 };
-class AstLog10D final : public AstNodeSystemUniop {
+class AstLog10D final : public AstNodeSystemUniopD {
 public:
     AstLog10D(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_Log10D(fl, lhsp) {}
@@ -4938,7 +4938,7 @@ public:
     string emitVerilog() override { return "%f$log10(%l)"; }
     string emitC() override { return "log10(%li)"; }
 };
-class AstLogD final : public AstNodeSystemUniop {
+class AstLogD final : public AstNodeSystemUniopD {
 public:
     AstLogD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_LogD(fl, lhsp) {}
@@ -4949,7 +4949,7 @@ public:
     string emitVerilog() override { return "%f$ln(%l)"; }
     string emitC() override { return "log(%li)"; }
 };
-class AstSinD final : public AstNodeSystemUniop {
+class AstSinD final : public AstNodeSystemUniopD {
 public:
     AstSinD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_SinD(fl, lhsp) {}
@@ -4960,7 +4960,7 @@ public:
     string emitVerilog() override { return "%f$sin(%l)"; }
     string emitC() override { return "sin(%li)"; }
 };
-class AstSinhD final : public AstNodeSystemUniop {
+class AstSinhD final : public AstNodeSystemUniopD {
 public:
     AstSinhD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_SinhD(fl, lhsp) {}
@@ -4971,7 +4971,7 @@ public:
     string emitVerilog() override { return "%f$sinh(%l)"; }
     string emitC() override { return "sinh(%li)"; }
 };
-class AstSqrtD final : public AstNodeSystemUniop {
+class AstSqrtD final : public AstNodeSystemUniopD {
 public:
     AstSqrtD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_SqrtD(fl, lhsp) {}
@@ -4982,7 +4982,7 @@ public:
     string emitVerilog() override { return "%f$sqrt(%l)"; }
     string emitC() override { return "sqrt(%li)"; }
 };
-class AstTanD final : public AstNodeSystemUniop {
+class AstTanD final : public AstNodeSystemUniopD {
 public:
     AstTanD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_TanD(fl, lhsp) {}
@@ -4993,7 +4993,7 @@ public:
     string emitVerilog() override { return "%f$tan(%l)"; }
     string emitC() override { return "tan(%li)"; }
 };
-class AstTanhD final : public AstNodeSystemUniop {
+class AstTanhD final : public AstNodeSystemUniopD {
 public:
     AstTanhD(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_TanhD(fl, lhsp) {}
diff --git a/src/V3ParseImp.cpp b/src/V3ParseImp.cpp
index e6f1705ca..640dfa9f5 100644
--- a/src/V3ParseImp.cpp
+++ b/src/V3ParseImp.cpp
@@ -469,13 +469,9 @@ void V3ParseImp::tokenPipeline() {
             if (nexttok == yP_COLONCOLON) {
                 token = yaID__CC;
             } else if (nexttok == '#') {
-                const V3ParseBisonYYSType curValueHold
-                    = yylval;  // Remember value, as about to read ahead
-                {
-                    const size_t depth = tokenPipeScanParam(0);
-                    if (tokenPeekp(depth)->token == yP_COLONCOLON) token = yaID__CC;
-                }
-                yylval = curValueHold;
+                VL_RESTORER(yylval);  // Remember value, as about to read ahead
+                const size_t depth = tokenPipeScanParam(0);
+                if (tokenPeekp(depth)->token == yP_COLONCOLON) token = yaID__CC;
             }
         }
         // If add to above "else if", also add to "if (token" further above
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 604ae8497..e7135d834 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -340,10 +340,10 @@ private:
     void visit(AstDivD* nodep) override { visit_real_add_sub(nodep); }
     void visit(AstMulD* nodep) override { visit_real_add_sub(nodep); }
     void visit(AstPowD* nodep) override { visit_real_add_sub(nodep); }
-    void visit(AstNodeSystemBiop* nodep) override { visit_real_add_sub(nodep); }
+    void visit(AstNodeSystemBiopD* nodep) override { visit_real_add_sub(nodep); }
     // Real: Output real
     void visit(AstNegateD* nodep) override { visit_real_neg_ceil(nodep); }
-    void visit(AstNodeSystemUniop* nodep) override { visit_real_neg_ceil(nodep); }
+    void visit(AstNodeSystemUniopD* nodep) override { visit_real_neg_ceil(nodep); }
 
     // Widths: out signed/unsigned width = lhs width, input un|signed
     void visit(AstSigned* nodep) override { visit_signed_unsigned(nodep, VSigning::SIGNED); }

From 889a1211f1394b475b02f70daa2d9712af297c83 Mon Sep 17 00:00:00 2001
From: Yutetsu TAKATSUKASA <y.takatsukasa@gmail.com>
Date: Thu, 1 Dec 2022 22:00:24 +0900
Subject: [PATCH 118/156] Fix 3786 (Internal error in bit op tree optimization)
 (#3793)

* Tests: Add a test to reproduce 3786

* Fix #3786 (Internal error in bit op tree optimization).
---
 src/V3Const.cpp                         | 10 +++++++++
 test_regress/t/t_const_opt.v            | 20 ++++++++++++++++--
 test_regress/t/t_const_opt_no_expand.pl | 27 +++++++++++++++++++++++++
 3 files changed, 55 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_const_opt_no_expand.pl

diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 2790b9620..89972e6c1 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -122,6 +122,10 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
         const AstConst* constp() const { return m_constp; }
         int wordIdx() const { return m_wordIdx; }
         bool polarity() const { return m_polarity; }
+        bool missingWordSel() const {
+            // When V3Expand is skipped, WordSel is not inserted.
+            return m_refp->isWide() && m_wordIdx == -1;
+        }
         int lsb() const { return m_lsb; }
 
         int msb() const { return std::min(m_msb, varWidth() - 1); }
@@ -132,6 +136,7 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
                 UASSERT_OBJ(m_wordIdx == -1, m_refp, "Bad word index into non-wide");
                 return width;
             } else {
+                if (missingWordSel()) return width;
                 UASSERT_OBJ(m_wordIdx >= 0, m_refp, "Bad word index into wide");
                 const int bitsInMSW = VL_BITBIT_E(width) ? VL_BITBIT_E(width) : VL_EDATASIZE;
                 return m_wordIdx == m_refp->widthWords() - 1 ? bitsInMSW : VL_EDATASIZE;
@@ -393,6 +398,11 @@ class ConstBitOpTreeVisitor final : public VNVisitor {
         if (!varInfop) {
             varInfop = new VarInfo{this, ref.refp(), ref.varWidth()};
             m_varInfos[idx].reset(varInfop);
+            if (ref.missingWordSel()) {
+                // ConstBitOpTreeVisitor makes some constants for masks and its type is uint64_t.
+                // That's why V3Expand, that inserts WordSel, is needed.
+                CONST_BITOP_SET_FAILED("V3Expand is skipped", ref.refp());
+            }
         } else {
             if (!varInfop->sameVarAs(ref.refp()))
                 CONST_BITOP_SET_FAILED("different var (scope?)", ref.refp());
diff --git a/test_regress/t/t_const_opt.v b/test_regress/t/t_const_opt.v
index d1c545a61..8ebb397b3 100644
--- a/test_regress/t/t_const_opt.v
+++ b/test_regress/t/t_const_opt.v
@@ -62,7 +62,7 @@ module t(/*AUTOARG*/
          $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
          if (crc !== 64'hc77bb9b3784ea091) $stop;
          // What checksum will we end up with (above print should match)
-`define EXPECTED_SUM 64'h9366e49d91bfe942
+`define EXPECTED_SUM 64'h94c0495e8e279723
 
          if (sum !== `EXPECTED_SUM) $stop;
          $write("*-* All Finished *-*\n");
@@ -90,10 +90,11 @@ module Test(/*AUTOARG*/
    logic bug3509_out;
    wire  bug3399_out0;
    wire  bug3399_out1;
+   logic bug3786_out;
 
    output logic o;
 
-   logic [11:0] tmp;
+   logic [12:0] tmp;
    assign o = ^tmp;
 
    always_ff @(posedge clk) begin
@@ -121,6 +122,7 @@ module Test(/*AUTOARG*/
       tmp[9] <= bug3509_out;
       tmp[10]<= bug3399_out0;
       tmp[11]<= bug3399_out1;
+      tmp[12]<= bug3786_out;
    end
 
    bug3182 i_bug3182(.in(d[4:0]), .out(bug3182_out));
@@ -129,6 +131,7 @@ module Test(/*AUTOARG*/
    bug3470 i_bug3470(.clk(clk), .in(d), .out(bug3470_out));
    bug3509 i_bug3509(.clk(clk), .in(d), .out(bug3509_out));
    bug3399 i_bug3399(.clk(clk), .in(d), .out0(bug3399_out0), .out1(bug3399_out1));
+   bug3786 i_bug3786(.clk(clk), .in(d), .out(bug3786_out));
 
 endmodule
 
@@ -315,3 +318,16 @@ module bug3399(input wire clk, input wire [31:0] in, inout wire out0, inout wire
    assign out0 = driver[0] ? d[0] : 1'bz;
    assign out1 = driver[1] ? d[1] : 1'bz;
 endmodule
+
+// Bug3786
+// When V3Expand is skipped, wide number is not split by WORDSEL.
+// Bit op tree opt. expects that bit width is 64 bit at most.
+module bug3786(input wire clk, input wire [31:0] in, inout wire out);
+   logic [127:0] d0, d1;
+   always_ff @(posedge clk) begin
+      d0 <= {d0[127:32], in};
+      d1 <= d1;
+   end
+
+   assign out = ^{d1, d0};
+endmodule
diff --git a/test_regress/t/t_const_opt_no_expand.pl b/test_regress/t/t_const_opt_no_expand.pl
new file mode 100755
index 000000000..db812ea9a
--- /dev/null
+++ b/test_regress/t/t_const_opt_no_expand.pl
@@ -0,0 +1,27 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+top_filename("t/t_const_opt.v");
+
+compile(
+    verilator_flags2 => ["-Wno-UNOPTTHREADS", "-fno-dfg", "-fno-expand",
+                         "--stats", "$Self->{t_dir}/t_const_opt.cpp"],
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+if ($Self->{vlt}) {
+    file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 2);
+}
+ok(1);
+1;

From e465a30eee8957cb1986f81a2af669b7d662041e Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 1 Dec 2022 18:27:36 -0500
Subject: [PATCH 119/156] Fix lint_off EOFNEWLINE in .vlt files (#3796).

---
 Changes                               |  1 +
 src/V3Config.cpp                      |  2 +-
 src/V3PreProc.cpp                     |  2 ++
 test_regress/t/t_lint_eofline_vlt.pl  | 36 +++++++++++++++++++++++++++
 test_regress/t/t_lint_eofline_vlt.vlt |  9 +++++++
 test_regress/t/t_vlt_warn.pl          |  2 +-
 6 files changed, 50 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_lint_eofline_vlt.pl
 create mode 100755 test_regress/t/t_lint_eofline_vlt.vlt

diff --git a/Changes b/Changes
index 3dfd580ca..63f6a978b 100644
--- a/Changes
+++ b/Changes
@@ -30,6 +30,7 @@ Verilator 5.003 devel
 * Fix wait 0.
 * Fix comparing ranged slices of unpacked arrays.
 * Fix empty string literals converting to string types (#3774). [miree]
+* Fix lint_off EOFNEWLINE in .vlt files (#3796). [Andrew Nolte]
 
 
 Verilator 5.002 2022-10-29
diff --git a/src/V3Config.cpp b/src/V3Config.cpp
index 1cefb40cf..1c98e2725 100644
--- a/src/V3Config.cpp
+++ b/src/V3Config.cpp
@@ -319,7 +319,7 @@ public:
             const int curlineno = filelinep->lastLineno();
             for (; m_lastIgnore.it != m_ignLines.end(); ++m_lastIgnore.it) {
                 if (m_lastIgnore.it->m_lineno > curlineno) break;
-                // UINFO(9, "     Hit " << *m_lastIt << endl);
+                // UINFO(9, "     Hit " << *m_lastIgnore.it << endl);
                 filelinep->warnOn(m_lastIgnore.it->m_code, m_lastIgnore.it->m_on);
             }
             if (false && debug() >= 9) {
diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp
index 2236eb934..6957331fd 100644
--- a/src/V3PreProc.cpp
+++ b/src/V3PreProc.cpp
@@ -19,6 +19,7 @@
 
 #include "V3PreProc.h"
 
+#include "V3Config.h"
 #include "V3Error.h"
 #include "V3File.h"
 #include "V3Global.h"
@@ -843,6 +844,7 @@ void V3PreProcImp::openFile(FileLine*, VInFilter* filterp, const string& filenam
         FileLine* const fl = new FileLine{flsp};
         fl->contentLineno(eof_lineno);
         fl->column(eof_newline + 1, eof_newline + 1);
+        V3Config::applyIgnores(fl);  // As preprocessor hasn't otherwise applied yet
         fl->v3warn(EOFNEWLINE, "Missing newline at end of file (POSIX 3.206).\n"
                                    << fl->warnMore() << "... Suggest add newline.");
     }
diff --git a/test_regress/t/t_lint_eofline_vlt.pl b/test_regress/t/t_lint_eofline_vlt.pl
new file mode 100755
index 000000000..9bea83d86
--- /dev/null
+++ b/test_regress/t/t_lint_eofline_vlt.pl
@@ -0,0 +1,36 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+use IO::File;
+use strict;
+use vars qw($Self);
+
+scenarios(vlt => 1);
+
+sub gen {
+    my $filename = shift;
+
+    my $fh = IO::File->new(">$filename");
+    $fh->print("// Generated by t_lint_eofline_bad.pl\n");
+    $fh->print("module t;\n");
+    $fh->print("// No newline below:\n");
+    $fh->print("endmodule");  # Intentionally no newline
+}
+
+top_filename("$Self->{obj_dir}/t_lint_eofline_bad.v");
+
+gen($Self->{top_filename});
+
+lint(
+    verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME t/t_lint_eofline_vlt.vlt"],
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_lint_eofline_vlt.vlt b/test_regress/t/t_lint_eofline_vlt.vlt
new file mode 100755
index 000000000..7c575bb83
--- /dev/null
+++ b/test_regress/t/t_lint_eofline_vlt.vlt
@@ -0,0 +1,9 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2010 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`verilator_config
+
+lint_off -rule EOFNEWLINE --file "*.v"
diff --git a/test_regress/t/t_vlt_warn.pl b/test_regress/t/t_vlt_warn.pl
index 9d2a06917..32163cf4e 100755
--- a/test_regress/t/t_vlt_warn.pl
+++ b/test_regress/t/t_vlt_warn.pl
@@ -11,7 +11,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(vlt => 1);
 
 lint(
-    verilator_flags2 => ["--lint-only t/t_vlt_warn.vlt -Wall"],
+    verilator_flags2 => ["--lint-only -Wall t/t_vlt_warn.vlt"],
     );
 
 ok(1);

From 87135d0b2d520debc2dccd5fc819aafafe0353dc Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 1 Dec 2022 18:47:09 -0500
Subject: [PATCH 120/156] Internals: Fix missing const. No functional change.

---
 src/V3AstNodeDType.h | 42 +++++++++++++++++++++---------------------
 src/V3AstNodes.cpp   |  4 ++--
 2 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h
index 69b2f5bec..d06961356 100644
--- a/src/V3AstNodeDType.h
+++ b/src/V3AstNodeDType.h
@@ -82,7 +82,7 @@ public:
     // Iff has second dtype, set as generic node function
     virtual void virtRefDType2p(AstNodeDType* nodep) {}
     // Assignable equivalence.  Call skipRefp() on this and samep before calling
-    virtual bool similarDType(AstNodeDType* samep) const = 0;
+    virtual bool similarDType(const AstNodeDType* samep) const = 0;
     // Iff has a non-null subDTypep(), as generic node function
     virtual AstNodeDType* subDTypep() const { return nullptr; }
     virtual bool isFourstate() const;
@@ -161,7 +161,7 @@ public:
         return (hi() == asamep->hi() && subDTypep() == asamep->subDTypep()
                 && rangenp()->sameTree(asamep->rangenp()));
     }  // HashedDT doesn't recurse, so need to check children
-    bool similarDType(AstNodeDType* samep) const override {
+    bool similarDType(const AstNodeDType* samep) const override {
         const AstNodeArrayDType* const asamep = static_cast<const AstNodeArrayDType*>(samep);
         return (asamep && type() == samep->type() && hi() == asamep->hi()
                 && rangenp()->sameTree(asamep->rangenp())
@@ -235,7 +235,7 @@ public:
     int widthAlignBytes() const override;
     // (Slow) recurses - Width in bytes rounding up 1,2,4,8,12,...
     int widthTotalBytes() const override;
-    bool similarDType(AstNodeDType* samep) const override {
+    bool similarDType(const AstNodeDType* samep) const override {
         return this == samep;  // We don't compare members, require exact equivalence
     }
     string name() const override { return m_name; }
@@ -321,7 +321,7 @@ public:
         if (!asamep->keyDTypep()) return false;
         return (subDTypep() == asamep->subDTypep() && keyDTypep() == asamep->keyDTypep());
     }
-    bool similarDType(AstNodeDType* samep) const override {
+    bool similarDType(const AstNodeDType* samep) const override {
         const AstAssocArrayDType* const asamep = static_cast<const AstAssocArrayDType*>(samep);
         return type() == samep->type() && asamep->subDTypep()
                && subDTypep()->skipRefp()->similarDType(asamep->subDTypep()->skipRefp());
@@ -399,7 +399,7 @@ public:
         const AstBasicDType* const sp = static_cast<const AstBasicDType*>(samep);
         return m == sp->m;
     }
-    bool similarDType(AstNodeDType* samep) const override {
+    bool similarDType(const AstNodeDType* samep) const override {
         return type() == samep->type() && same(samep);
     }
     string name() const override { return m.m_keyword.ascii(); }
@@ -483,7 +483,7 @@ public:
         this->elementsp(elementsp);
     }
     ASTGEN_MEMBERS_AstBracketArrayDType;
-    bool similarDType(AstNodeDType* samep) const override { V3ERROR_NA_RETURN(false); }
+    bool similarDType(const AstNodeDType* samep) const override { V3ERROR_NA_RETURN(false); }
     AstNodeDType* subDTypep() const override { return childDTypep(); }
     // METHODS
     // Will be removed in V3Width, which relies on this
@@ -518,7 +518,7 @@ public:
         const AstClassRefDType* const asamep = static_cast<const AstClassRefDType*>(samep);
         return (m_classp == asamep->m_classp && m_classOrPackagep == asamep->m_classOrPackagep);
     }
-    bool similarDType(AstNodeDType* samep) const override {
+    bool similarDType(const AstNodeDType* samep) const override {
         return this == samep || (type() == samep->type() && same(samep));
     }
     void dump(std::ostream& str = std::cout) const override;
@@ -567,7 +567,7 @@ public:
         const AstConstDType* const sp = static_cast<const AstConstDType*>(samep);
         return (m_refDTypep == sp->m_refDTypep);
     }
-    bool similarDType(AstNodeDType* samep) const override {
+    bool similarDType(const AstNodeDType* samep) const override {
         return skipRefp()->similarDType(samep->skipRefp());
     }
     AstNodeDType* getChildDTypep() const override { return childDTypep(); }
@@ -614,7 +614,7 @@ public:
         const AstDefImplicitDType* const sp = static_cast<const AstDefImplicitDType*>(samep);
         return uniqueNum() == sp->uniqueNum();
     }
-    bool similarDType(AstNodeDType* samep) const override {
+    bool similarDType(const AstNodeDType* samep) const override {
         return type() == samep->type() && same(samep);
     }
     AstNodeDType* getChildDTypep() const override { return childDTypep(); }
@@ -664,7 +664,7 @@ public:
         if (!asamep->subDTypep()) return false;
         return subDTypep() == asamep->subDTypep();
     }
-    bool similarDType(AstNodeDType* samep) const override {
+    bool similarDType(const AstNodeDType* samep) const override {
         const AstAssocArrayDType* const asamep = static_cast<const AstAssocArrayDType*>(samep);
         return type() == samep->type() && asamep->subDTypep()
                && subDTypep()->skipRefp()->similarDType(asamep->subDTypep()->skipRefp());
@@ -702,7 +702,7 @@ public:
     AstNodeDType* subDTypep() const override { return nullptr; }
     AstNodeDType* virtRefDTypep() const override { return nullptr; }
     void virtRefDTypep(AstNodeDType* nodep) override {}
-    bool similarDType(AstNodeDType* samep) const override { return this == samep; }
+    bool similarDType(const AstNodeDType* samep) const override { return this == samep; }
     AstBasicDType* basicp() const override VL_MT_SAFE { return nullptr; }
     // cppcheck-suppress csyleCast
     AstNodeDType* skipRefp() const override VL_MT_SAFE { return (AstNodeDType*)this; }
@@ -747,7 +747,7 @@ public:
         const AstEnumDType* const sp = static_cast<const AstEnumDType*>(samep);
         return uniqueNum() == sp->uniqueNum();
     }
-    bool similarDType(AstNodeDType* samep) const override { return this == samep; }
+    bool similarDType(const AstNodeDType* samep) const override { return this == samep; }
     AstNodeDType* getChildDTypep() const override { return childDTypep(); }
     AstNodeDType* subDTypep() const override { return m_refDTypep ? m_refDTypep : childDTypep(); }
     void refDTypep(AstNodeDType* nodep) { m_refDTypep = nodep; }
@@ -815,7 +815,7 @@ public:
     AstNodeDType* skipRefp() const override VL_MT_SAFE { return (AstNodeDType*)this; }
     AstNodeDType* skipRefToConstp() const override { return (AstNodeDType*)this; }
     AstNodeDType* skipRefToEnump() const override { return (AstNodeDType*)this; }
-    bool similarDType(AstNodeDType* samep) const override { return this == samep; }
+    bool similarDType(const AstNodeDType* samep) const override { return this == samep; }
     int widthAlignBytes() const override { return 1; }
     int widthTotalBytes() const override { return 1; }
     FileLine* modportFileline() const { return m_modportFileline; }
@@ -876,7 +876,7 @@ public:
     void refDTypep(AstNodeDType* nodep) { m_refDTypep = nodep; }
     AstNodeDType* virtRefDTypep() const override { return m_refDTypep; }
     void virtRefDTypep(AstNodeDType* nodep) override { refDTypep(nodep); }
-    bool similarDType(AstNodeDType* samep) const override { return this == samep; }
+    bool similarDType(const AstNodeDType* samep) const override { return this == samep; }
     //
     // (Slow) recurse down to find basic data type (Note don't need virtual -
     // AstVar isn't a NodeDType)
@@ -925,7 +925,7 @@ public:
     AstNodeDType* skipRefp() const override VL_MT_SAFE { return subDTypep()->skipRefp(); }
     AstNodeDType* skipRefToConstp() const override { return subDTypep()->skipRefToConstp(); }
     AstNodeDType* skipRefToEnump() const override { return subDTypep()->skipRefToEnump(); }
-    bool similarDType(AstNodeDType* samep) const override {
+    bool similarDType(const AstNodeDType* samep) const override {
         const AstParamTypeDType* const sp = static_cast<const AstParamTypeDType*>(samep);
         return type() == samep->type() && sp
                && this->subDTypep()->skipRefp()->similarDType(sp->subDTypep()->skipRefp());
@@ -955,7 +955,7 @@ public:
     ASTGEN_MEMBERS_AstParseTypeDType;
     AstNodeDType* dtypep() const { return nullptr; }
     // METHODS
-    bool similarDType(AstNodeDType* samep) const override { return this == samep; }
+    bool similarDType(const AstNodeDType* samep) const override { return this == samep; }
     AstBasicDType* basicp() const override VL_MT_SAFE { return nullptr; }
     AstNodeDType* skipRefp() const override VL_MT_SAFE { return nullptr; }
     // cppcheck-suppress csyleCast
@@ -1003,7 +1003,7 @@ public:
         if (!asamep->subDTypep()) return false;
         return (subDTypep() == asamep->subDTypep());
     }
-    bool similarDType(AstNodeDType* samep) const override {
+    bool similarDType(const AstNodeDType* samep) const override {
         const AstQueueDType* const asamep = static_cast<const AstQueueDType*>(samep);
         return type() == samep->type() && asamep->subDTypep()
                && subDTypep()->skipRefp()->similarDType(asamep->subDTypep()->skipRefp());
@@ -1066,7 +1066,7 @@ public:
         return (m_typedefp == asamep->m_typedefp && m_refDTypep == asamep->m_refDTypep
                 && m_name == asamep->m_name && m_classOrPackagep == asamep->m_classOrPackagep);
     }
-    bool similarDType(AstNodeDType* samep) const override {
+    bool similarDType(const AstNodeDType* samep) const override {
         return skipRefp()->similarDType(samep->skipRefp());
     }
     void dump(std::ostream& str = std::cout) const override;
@@ -1143,7 +1143,7 @@ public:
         if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep();
     }
     bool same(const AstNode* samep) const override;
-    bool similarDType(AstNodeDType* samep) const override;
+    bool similarDType(const AstNodeDType* samep) const override;
     void dumpSmall(std::ostream& str) const override;
     AstNodeDType* getChildDTypep() const override { return childDTypep(); }
     AstNodeDType* subDTypep() const override { return m_refDTypep ? m_refDTypep : childDTypep(); }
@@ -1174,7 +1174,7 @@ public:
     AstNodeDType* subDTypep() const override { return nullptr; }
     AstNodeDType* virtRefDTypep() const override { return nullptr; }
     void virtRefDTypep(AstNodeDType* nodep) override {}
-    bool similarDType(AstNodeDType* samep) const override { return this == samep; }
+    bool similarDType(const AstNodeDType* samep) const override { return this == samep; }
     AstBasicDType* basicp() const override VL_MT_SAFE { return nullptr; }
     // cppcheck-suppress csyleCast
     AstNodeDType* skipRefp() const override VL_MT_SAFE { return (AstNodeDType*)this; }
@@ -1208,7 +1208,7 @@ public:
         if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep();
     }
     bool same(const AstNode* samep) const override;
-    bool similarDType(AstNodeDType* samep) const override;
+    bool similarDType(const AstNodeDType* samep) const override;
     void dumpSmall(std::ostream& str) const override;
     AstNodeDType* getChildDTypep() const override { return childDTypep(); }
     AstNodeDType* subDTypep() const override VL_MT_SAFE {
diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index bb4be9ecf..6d833054e 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -1994,7 +1994,7 @@ bool AstWildcardArrayDType::same(const AstNode* samep) const {
     if (!asamep->subDTypep()) return false;
     return (subDTypep() == asamep->subDTypep());
 }
-bool AstWildcardArrayDType::similarDType(AstNodeDType* samep) const {
+bool AstWildcardArrayDType::similarDType(const AstNodeDType* samep) const {
     const AstNodeArrayDType* const asamep = static_cast<const AstNodeArrayDType*>(samep);
     return type() == samep->type() && asamep->subDTypep()
            && subDTypep()->skipRefp()->similarDType(asamep->subDTypep()->skipRefp());
@@ -2008,7 +2008,7 @@ bool AstUnsizedArrayDType::same(const AstNode* samep) const {
     if (!asamep->subDTypep()) return false;
     return (subDTypep() == asamep->subDTypep());
 }
-bool AstUnsizedArrayDType::similarDType(AstNodeDType* samep) const {
+bool AstUnsizedArrayDType::similarDType(const AstNodeDType* samep) const {
     const AstNodeArrayDType* const asamep = static_cast<const AstNodeArrayDType*>(samep);
     return type() == samep->type() && asamep->subDTypep()
            && subDTypep()->skipRefp()->similarDType(asamep->subDTypep()->skipRefp());

From 338e875b707c3eecb40e35b56764aefe144ab89a Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 1 Dec 2022 19:32:09 -0500
Subject: [PATCH 121/156] Internals: Mark more VL_MT_SAFE functions. No
 functional change

---
 include/verilated.h       | 4 ++--
 include/verilated_imp.h   | 2 +-
 include/verilated_vcd_c.h | 2 +-
 include/verilated_vpi.cpp | 2 +-
 4 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/verilated.h b/include/verilated.h
index 81c174774..f64de2226 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -248,7 +248,7 @@ protected:
 public:
     /// Returns the VerilatedContext this model is instantiated under
     /// Used to get to e.g. simulation time via contextp()->time()
-    VerilatedContext* contextp() const { return &m_context; }
+    VerilatedContext* contextp() const VL_MT_SAFE { return &m_context; }
     /// Returns the hierarchical name of this module instance.
     virtual const char* hierName() const = 0;
     /// Returns the name of this model (the name of the generated model class).
@@ -718,7 +718,7 @@ public:
         lastContextp(contextp);
     }
     /// Return the VerilatedContext for the current thread
-    static VerilatedContext* threadContextp() {
+    static VerilatedContext* threadContextp() VL_MT_SAFE {
         if (VL_UNLIKELY(!t_s.t_contextp)) t_s.t_contextp = lastContextp();
         return t_s.t_contextp;
     }
diff --git a/include/verilated_imp.h b/include/verilated_imp.h
index 5684da3c5..e70fffd3b 100644
--- a/include/verilated_imp.h
+++ b/include/verilated_imp.h
@@ -441,7 +441,7 @@ protected:
     friend class Verilated;
 
     // MEMBERS
-    static VerilatedImpData& s() {  // Singleton
+    static VerilatedImpData& s() VL_MT_SAFE {  // Singleton
         static VerilatedImpData s_s;
         return s_s;
     }
diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h
index 64469d430..94361115b 100644
--- a/include/verilated_vcd_c.h
+++ b/include/verilated_vcd_c.h
@@ -123,7 +123,7 @@ public:
 
     // ACCESSORS
     // Set size in bytes after which new file should be created.
-    void rolloverSize(uint64_t size) { m_rolloverSize = size; }
+    void rolloverSize(uint64_t size) VL_MT_SAFE { m_rolloverSize = size; }
 
     // METHODS - All must be thread safe
     // Open the file; call isOpen() to see if errors
diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp
index 2fb4ecdba..f8640c64d 100644
--- a/include/verilated_vpi.cpp
+++ b/include/verilated_vpi.cpp
@@ -67,7 +67,7 @@ class VerilatedVpio VL_NOT_FINAL {
     // CONSTANTS
     // Magic value stored in front of object to detect double free etc
     // Must be odd, as aligned pointer can never be odd
-    static constexpr uint32_t activeMagic() { return 0xfeed100f; }
+    static constexpr uint32_t activeMagic() VL_PURE { return 0xfeed100f; }
 
     // MEM MANGLEMENT
     // Internal note: Globals may multi-construct, see verilated.cpp top.

From 701d2277cda34eaf9b6af1565f6b590df24f2820 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 2 Dec 2022 07:34:34 -0500
Subject: [PATCH 122/156] Tests: rename

---
 test_regress/t/{t_a4_examples.pl => t_a6_examples.pl} | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename test_regress/t/{t_a4_examples.pl => t_a6_examples.pl} (100%)

diff --git a/test_regress/t/t_a4_examples.pl b/test_regress/t/t_a6_examples.pl
similarity index 100%
rename from test_regress/t/t_a4_examples.pl
rename to test_regress/t/t_a6_examples.pl

From f27cf4c8045461f481cefd5eb68d97cd71f4b2b8 Mon Sep 17 00:00:00 2001
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Fri, 2 Dec 2022 15:46:38 -0800
Subject: [PATCH 123/156] Commentary: Fix spelling in C++ comments (#3797)
 (#3798)

---
 include/verilated.cpp          | 12 ++++++------
 include/verilated.h            |  2 +-
 include/verilated_funcs.h      |  2 +-
 include/verilated_profiler.cpp |  2 +-
 include/verilated_timing.h     |  2 +-
 include/verilated_trace_imp.h  |  6 +++---
 include/verilated_types.h      |  4 ++--
 include/verilated_vcd_c.cpp    |  8 ++++----
 include/verilated_vcd_c.h      |  2 +-
 include/verilated_vpi.cpp      | 10 +++++-----
 include/verilated_vpi.h        |  2 +-
 include/verilatedos.h          |  8 ++++----
 src/V3Active.cpp               |  2 +-
 src/V3AssertPre.cpp            |  2 +-
 src/V3Ast.cpp                  |  2 +-
 src/V3AstNodeExpr.h            |  6 +++---
 src/V3AstNodeOther.h           | 16 ++++++++--------
 src/V3Class.cpp                |  4 ++--
 src/V3Config.cpp               |  4 ++--
 src/V3Const.cpp                |  4 ++--
 src/V3DfgDecomposition.cpp     |  2 +-
 src/V3DfgPasses.cpp            |  2 +-
 src/V3DfgPeephole.cpp          |  2 +-
 src/V3EmitCImp.cpp             |  2 +-
 src/V3EmitCMain.cpp            |  2 +-
 src/V3FileLine.h               |  2 +-
 src/V3Gate.cpp                 |  2 +-
 src/V3Global.cpp               |  2 +-
 src/V3Global.h                 |  2 +-
 src/V3HierBlock.cpp            |  4 ++--
 src/V3HierBlock.h              |  4 ++--
 src/V3Inst.cpp                 |  2 +-
 src/V3LinkParse.cpp            |  2 +-
 src/V3MergeCond.cpp            |  6 +++---
 src/V3OptionParser.h           | 10 +++++-----
 src/V3Order.cpp                |  4 ++--
 src/V3PairingHeap.h            |  4 ++--
 src/V3Param.cpp                |  4 ++--
 src/V3ParseGrammar.cpp         |  2 +-
 src/V3ParseImp.h               |  2 +-
 src/V3PreProc.cpp              |  4 ++--
 src/V3ProtectLib.cpp           |  2 +-
 src/V3Sched.cpp                |  2 +-
 src/V3Sched.h                  |  2 +-
 src/V3SenExprBuilder.h         |  4 ++--
 src/V3SplitVar.cpp             |  6 +++---
 src/V3Tristate.cpp             |  2 +-
 src/V3Undriven.cpp             |  2 +-
 src/V3Width.cpp                |  8 ++++----
 49 files changed, 97 insertions(+), 97 deletions(-)

diff --git a/include/verilated.cpp b/include/verilated.cpp
index 544baa478..eff55246c 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -281,7 +281,7 @@ void VL_PRINTF_MT(const char* formatp, ...) VL_MT_SAFE {
 
 static uint32_t vl_sys_rand32() VL_MT_SAFE {
     // Return random 32-bits using system library.
-    // Used only to construct seed for Verilator's PNRG.
+    // Used only to construct seed for Verilator's PRNG.
     static VerilatedMutex s_mutex;
     const VerilatedLockGuard lock{s_mutex};  // Otherwise rand is unsafe
 #if defined(_WIN32) && !defined(__CYGWIN__)
@@ -2223,7 +2223,7 @@ static const char* vl_time_str(int scale) VL_PURE {
     return names[2 - scale];
 }
 double vl_time_multiplier(int scale) VL_PURE {
-    // Return timescale multipler -18 to +18
+    // Return timescale multiplier -18 to +18
     // For speed, this does not check for illegal values
     // cppcheck-has-bug-suppress arrayIndexOutOfBoundsCond
     if (scale < 0) {
@@ -2340,8 +2340,8 @@ void VerilatedContext::checkMagic(const VerilatedContext* contextp) {
 
 VerilatedContext::Serialized::Serialized() {
     constexpr int8_t picosecond = -12;
-    m_timeunit = picosecond;  // Initial value until overriden by _Vconfigure
-    m_timeprecision = picosecond;  // Initial value until overriden by _Vconfigure
+    m_timeunit = picosecond;  // Initial value until overridden by _Vconfigure
+    m_timeprecision = picosecond;  // Initial value until overridden by _Vconfigure
 }
 
 void VerilatedContext::assertOn(bool flag) VL_MT_SAFE {
@@ -2659,7 +2659,7 @@ void VerilatedContext::randSeed(int val) VL_MT_SAFE {
     const VerilatedLockGuard lock{VerilatedContextImp::s().s_randMutex};
     m_s.m_randSeed = val;
     const uint64_t newEpoch = VerilatedContextImp::s().s_randSeedEpoch + 1;
-    // Obververs must see new epoch AFTER seed updated
+    // Observers must see new epoch AFTER seed updated
     std::atomic_signal_fence(std::memory_order_release);
     VerilatedContextImp::s().s_randSeedEpoch = newEpoch;
 }
@@ -3117,7 +3117,7 @@ void VlDeleter::deleteAll() {
         if (m_newGarbage.empty()) break;
         VerilatedLockGuard deleteLock{m_deleteMutex};
         std::swap(m_newGarbage, m_toDelete);
-        lock.unlock();  // So destuctors can enqueue new objects
+        lock.unlock();  // So destructors can enqueue new objects
         for (VlDeletable* const objp : m_toDelete) delete objp;
         m_toDelete.clear();
     }
diff --git a/include/verilated.h b/include/verilated.h
index f64de2226..d1bc8c8f2 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -440,7 +440,7 @@ public:
     void errorLimit(int val) VL_MT_SAFE;
     /// Return number of errors/assertions before stop
     int errorLimit() const VL_MT_SAFE { return m_s.m_errorLimit; }
-    /// Set to throw fatal error on $stop/non-fatal ettot
+    /// Set to throw fatal error on $stop/non-fatal error
     void fatalOnError(bool flag) VL_MT_SAFE;
     /// Return if to throw fatal error on $stop/non-fatal
     bool fatalOnError() const VL_MT_SAFE { return m_s.m_fatalOnError; }
diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h
index c3db7c7a6..7cf7604f6 100644
--- a/include/verilated_funcs.h
+++ b/include/verilated_funcs.h
@@ -1394,7 +1394,7 @@ static inline IData VL_STREAML_FAST_III(int lbits, IData ld, IData rd_log2) VL_P
     //
     // If lbits is not a multiple of the slice size (i.e., lbits % rd != 0),
     // then we end up with a "gap" in our reversed result. For example, if we
-    // have a 5-bit Verlilog signal (lbits=5) in an 8-bit C data type:
+    // have a 5-bit Verilog signal (lbits=5) in an 8-bit C data type:
     //
     //   ld = ---43210
     //
diff --git a/include/verilated_profiler.cpp b/include/verilated_profiler.cpp
index 7ea499c1b..5aab5df71 100644
--- a/include/verilated_profiler.cpp
+++ b/include/verilated_profiler.cpp
@@ -119,7 +119,7 @@ VerilatedVirtualBase* VlExecutionProfiler::construct(VerilatedContext& context)
                 },
                 &data);
 
-            // Wait until initializationis complete
+            // Wait until initialization is complete
             threadPoolp->workerp(i)->wait();
         }
     }
diff --git a/include/verilated_timing.h b/include/verilated_timing.h
index bead97e9d..535839389 100644
--- a/include/verilated_timing.h
+++ b/include/verilated_timing.h
@@ -194,7 +194,7 @@ public:
 //=============================================================================
 // VlTriggerScheduler stores coroutines to be resumed by a trigger. It does not keep track of its
 // trigger, relying on calling code to resume when appropriate. Coroutines are kept in two stages
-// - 'uncommitted' and 'ready'. Whenever a coroutine is suspended, it lands in the 'uncommited'
+// - 'uncommitted' and 'ready'. Whenever a coroutine is suspended, it lands in the 'uncommitted'
 // stage. Only when commit() is called, these coroutines get moved to the 'ready' stage. That's
 // when they can be resumed. This is done to avoid resuming processes before they start waiting.
 
diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h
index aa37ff9fb..d925bcaf4 100644
--- a/include/verilated_trace_imp.h
+++ b/include/verilated_trace_imp.h
@@ -82,7 +82,7 @@ static std::string doubleToTimescale(double value) {
 template <>
 uint32_t* VerilatedTrace<VL_SUB_T, VL_BUF_T>::getOffloadBuffer() {
     uint32_t* bufferp;
-    // Some jitter is expected, so some number of alternative offlaod buffers are
+    // Some jitter is expected, so some number of alternative offload buffers are
     // required, but don't allocate more than 8 buffers.
     if (m_numOffloadBuffers < 8) {
         // Allocate a new buffer if none is available
@@ -348,7 +348,7 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::traceInit() VL_MT_UNSAFE {
         // Else if was empty, m_sigs_enabledp = nullptr to short circuit tests
         // But it isn't, so alloc one bit for each code to indicate enablement
         // We don't want to still use m_signs_enabledVec as std::vector<bool> is not
-        // guarenteed to be fast
+        // guaranteed to be fast
         m_sigs_enabledp = new uint32_t[1 + VL_WORDS_I(nextCode())]{0};
         m_sigs_enabledVec.reserve(nextCode());
         for (size_t code = 0; code < nextCode(); ++code) {
@@ -513,7 +513,7 @@ void VerilatedTrace<VL_SUB_T, VL_BUF_T>::runCallbacks(const std::vector<Callback
                 mainThreadWorkerData.push_back(itemp);
             }
         }
-        // Execute main thead jobs
+        // Execute main thread jobs
         for (ParallelWorkerData* const itemp : mainThreadWorkerData) {
             parallelWorkerTask(itemp, false);
         }
diff --git a/include/verilated_types.h b/include/verilated_types.h
index af00f31b7..5c852e54a 100644
--- a/include/verilated_types.h
+++ b/include/verilated_types.h
@@ -412,7 +412,7 @@ public:
     void sort(Func with_func) {
         // with_func returns arbitrary type to use for the sort comparison
         std::sort(m_deque.begin(), m_deque.end(), [=](const T_Value& a, const T_Value& b) {
-            // index number is meaninless with sort, as it changes
+            // index number is meaningless with sort, as it changes
             return with_func(0, a) < with_func(0, b);
         });
     }
@@ -421,7 +421,7 @@ public:
     void rsort(Func with_func) {
         // with_func returns arbitrary type to use for the sort comparison
         std::sort(m_deque.rbegin(), m_deque.rend(), [=](const T_Value& a, const T_Value& b) {
-            // index number is meaninless with sort, as it changes
+            // index number is meaningless with sort, as it changes
             return with_func(0, a) < with_func(0, b);
         });
     }
diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp
index 66ccea3ba..e65b0380f 100644
--- a/include/verilated_vcd_c.cpp
+++ b/include/verilated_vcd_c.cpp
@@ -475,7 +475,7 @@ void VerilatedVcd::declare(uint32_t code, const char* name, const char* wirep, b
         m_suffixes.resize(nextCode() * VL_TRACE_SUFFIX_ENTRY_SIZE * 2, 0);
     }
 
-    // Keep upper bound on bytes a single signal cna emit into the buffer
+    // Keep upper bound on bytes a single signal can emit into the buffer
     m_maxSignalBytes = std::max<size_t>(m_maxSignalBytes, bits + 32);
     // Make sure write buffer is large enough, plus header
     bufferResize(m_maxSignalBytes + 1024);
@@ -571,7 +571,7 @@ void VerilatedVcd::declDouble(uint32_t code, const char* name, bool array, int a
 VerilatedVcd::Buffer* VerilatedVcd::getTraceBuffer() {
     VerilatedVcd::Buffer* const bufp = new Buffer{*this};
     if (parallel()) {
-        // Note: This is called from VeriltedVcd::dump, which already holds the lock
+        // Note: This is called from VerilatedVcd::dump, which already holds the lock
         // If no buffer available, allocate a new one
         if (m_freeBuffers.empty()) {
             constexpr size_t pageSize = 4096;
@@ -594,7 +594,7 @@ VerilatedVcd::Buffer* VerilatedVcd::getTraceBuffer() {
 
 void VerilatedVcd::commitTraceBuffer(VerilatedVcd::Buffer* bufp) {
     if (parallel()) {
-        // Note: This is called from VeriltedVcd::dump, which already holds the lock
+        // Note: This is called from VerilatedVcd::dump, which already holds the lock
         // Resize output buffer. Note, we use the full size of the trace buffer, as
         // this is a lot more stable than the actual occupancy of the trace buffer.
         // This helps us to avoid re-allocations due to small size changes.
@@ -695,7 +695,7 @@ void VerilatedVcdBuffer::finishLine(uint32_t code, char* writep) {
 VL_ATTR_ALWINLINE
 void VerilatedVcdBuffer::emitEvent(uint32_t code, VlEvent newval) {
     const bool triggered = newval.isTriggered();
-    // TODO : It seems that untriggerd events are not filtered
+    // TODO : It seems that untriggered events are not filtered
     // should be tested before this last step
     if (triggered) {
         // Don't prefetch suffix as it's a bit too late;
diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h
index 94361115b..233f86192 100644
--- a/include/verilated_vcd_c.h
+++ b/include/verilated_vcd_c.h
@@ -168,7 +168,7 @@ void VerilatedVcd::Super::dumpvars(int level, const std::string& hier);
 // VerilatedVcdBuffer
 
 class VerilatedVcdBuffer VL_NOT_FINAL {
-    // Give the trace file ans sub-classes access to the private bits
+    // Give the trace file and sub-classes access to the private bits
     friend VerilatedVcd;
     friend VerilatedVcd::Super;
     friend VerilatedVcd::Buffer;
diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp
index f8640c64d..85358d731 100644
--- a/include/verilated_vpi.cpp
+++ b/include/verilated_vpi.cpp
@@ -1792,11 +1792,11 @@ void vl_get_value(const VerilatedVar* varp, void* varDatap, p_vpi_value valuep,
             // align so least significant 3 bits represent octal char
             val >>= idx.rem;
             if (i == (chars - 1)) {
-                // most signifcant char, mask off non existant bits when vector
+                // most significant char, mask off nonexistent bits when vector
                 // size is not a multiple of 3
                 const unsigned int rem = varp->packed().elements() % 3;
                 if (rem) {
-                    // generate bit mask & zero non existant bits
+                    // generate bit mask & zero nonexistent bits
                     val &= (1 << rem) - 1;
                 }
             }
@@ -1842,11 +1842,11 @@ void vl_get_value(const VerilatedVar* varp, void* varDatap, p_vpi_value valuep,
         for (i = 0; i < chars; ++i) {
             char val = (datap[i >> 1] >> ((i & 1) << 2)) & 15;
             if (i == (chars - 1)) {
-                // most signifcant char, mask off non existant bits when vector
+                // most significant char, mask off nonexistent bits when vector
                 // size is not a multiple of 4
                 const unsigned int rem = varp->packed().elements() & 3;
                 if (rem) {
-                    // generate bit mask & zero non existant bits
+                    // generate bit mask & zero nonexistent bits
                     val &= (1 << rem) - 1;
                 }
             }
@@ -2269,7 +2269,7 @@ PLI_INT32 vpi_chk_error(p_vpi_error_info error_info_p) {
     VerilatedVpiImp::assertOneCheck();
     p_vpi_error_info const _error_info_p = VerilatedVpiImp::error_info()->getError();
     if (error_info_p && _error_info_p) *error_info_p = *_error_info_p;
-    if (!_error_info_p) return 0;  // no error occured
+    if (!_error_info_p) return 0;  // no error occurred
     return _error_info_p->level;  // return error severity level
 }
 
diff --git a/include/verilated_vpi.h b/include/verilated_vpi.h
index aeb58e210..12cb0088c 100644
--- a/include/verilated_vpi.h
+++ b/include/verilated_vpi.h
@@ -36,7 +36,7 @@
 
 //======================================================================
 
-/// Class for namespace-like groupng of Verilator VPI functions.
+/// Class for namespace-like grouping of Verilator VPI functions.
 
 class VerilatedVpi final {
 public:
diff --git a/include/verilatedos.h b/include/verilatedos.h
index 5fed91b1b..db9b18932 100644
--- a/include/verilatedos.h
+++ b/include/verilatedos.h
@@ -111,12 +111,12 @@
 # define VL_ATTR_WEAK  ///< Attribute that function external that is optionally defined
 #endif
 #ifndef VL_CAPABILITY
-# define VL_ACQUIRE(...)  ///< Function aquires a capability/lock (-fthread-safety)
-# define VL_ACQUIRE_SHARED(...)  ///< Function aquires a shared capability/lock (-fthread-safety)
+# define VL_ACQUIRE(...)  ///< Function acquires a capability/lock (-fthread-safety)
+# define VL_ACQUIRE_SHARED(...)  ///< Function acquires a shared capability/lock (-fthread-safety)
 # define VL_RELEASE(...)  ///< Function releases a capability/lock (-fthread-safety)
 # define VL_RELEASE_SHARED(...)  ///< Function releases a shared capability/lock (-fthread-safety)
-# define VL_TRY_ACQUIRE(...)  ///< Function returns bool if aquired a capability (-fthread-safety)
-# define VL_TRY_ACQUIRE_SHARED(...)  ///< Function returns bool if aquired shared (-fthread-safety)
+# define VL_TRY_ACQUIRE(...)  ///< Function returns bool if acquired a capability (-fthread-safety)
+# define VL_TRY_ACQUIRE_SHARED(...)  ///< Function returns bool if acquired shared (-fthread-safety)
 # define VL_REQUIRES(x)  ///< Function requires a capability inbound (-fthread-safety)
 # define VL_EXCLUDES(x)  ///< Function requires not having a capability inbound (-fthread-safety)
 # define VL_CAPABILITY(x)  ///< Name of capability/lock (-fthread-safety)
diff --git a/src/V3Active.cpp b/src/V3Active.cpp
index 0350609cc..7cfa896ae 100644
--- a/src/V3Active.cpp
+++ b/src/V3Active.cpp
@@ -88,7 +88,7 @@ protected:
     // Recursively traverse the graph to determine whether every control 'BLOCK' has an assignment
     // to the output we are currently analysing (the output whose 'user() is set), if so return
     // true. Where a BLOCK contains a BRANCH, both the if and else sides of the branch must return
-    // true for the BRANCH to evalute to true. A BLOCK however needs only a single one of its
+    // true for the BRANCH to evaluate to true. A BLOCK however needs only a single one of its
     // siblings to evaluate true in order to evaluate true itself. On output vertex only evaluates
     // true if it is the vertex we are analyzing on this check
 
diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp
index ac851beac..8e84e2986 100644
--- a/src/V3AssertPre.cpp
+++ b/src/V3AssertPre.cpp
@@ -91,7 +91,7 @@ private:
         if (AstFuncRef* const funcrefp = VN_CAST(nodep->propp(), FuncRef)) {
             if (AstProperty* const propp = VN_CAST(funcrefp->taskp(), Property)) {
                 AstPropSpec* propExprp = getPropertyExprp(propp);
-                // Substitute inner property call befory copying in order to not doing the same for
+                // Substitute inner property call before copying in order to not doing the same for
                 // each call of outer property call.
                 propExprp = substitutePropertyCall(propExprp);
                 // Clone subtree after substitution. It is needed, because property might be called
diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp
index ad11ff8c0..14fd978df 100644
--- a/src/V3Ast.cpp
+++ b/src/V3Ast.cpp
@@ -112,7 +112,7 @@ string AstNode::encodeName(const string& namein) {
     }
     // Shorten names
     // TODO long term use VName in place of "string name"
-    // Then we also won't need to save the table of hased values
+    // Then we also won't need to save the table of hashed values
     VName vname{out};
     return vname.hashedName();
 }
diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index 1d1a76769..c67a4335a 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -115,7 +115,7 @@ public:
 class AstNodeSel VL_NOT_FINAL : public AstNodeBiop {
     // Single bit range extraction, perhaps with non-constant selection or array selection
     // @astgen alias op1 := fromp // Expression we are indexing into
-    // @astgen alias op2 := bitp // The index // TOOD: rename to idxp
+    // @astgen alias op2 := bitp // The index // TODO: rename to idxp
 protected:
     AstNodeSel(VNType t, FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* bitp)
         : AstNodeBiop{t, fl, fromp, bitp} {}
@@ -4178,7 +4178,7 @@ public:
 
 // === AstNodeCond ===
 class AstCond final : public AstNodeCond {
-    // Conditional ?: expressoin
+    // Conditional ?: expression
 public:
     AstCond(FileLine* fl, AstNodeExpr* condp, AstNodeExpr* thenp, AstNodeExpr* elsep)
         : ASTGEN_SUPER_Cond(fl, condp, thenp, elsep) {}
@@ -4463,7 +4463,7 @@ public:
     int instrCount() const override { return INSTR_COUNT_DBL; }
 };
 class AstIsUnbounded final : public AstNodeUniop {
-    // True if is unmbounded ($)
+    // True if is unbounded ($)
 public:
     AstIsUnbounded(FileLine* fl, AstNodeExpr* lhsp)
         : ASTGEN_SUPER_IsUnbounded(fl, lhsp) {
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index 44c22b42f..74a14a238 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -15,7 +15,7 @@
 //*************************************************************************
 //
 // This files contains all 'AstNode' sub-types that relate to other constructs
-// not covered by the more speficic V3AstNode*.h files.
+// not covered by the more specific V3AstNode*.h files.
 //
 //*************************************************************************
 
@@ -83,7 +83,7 @@ private:
     bool m_isHideProtected : 1;  // Verilog protected
     bool m_pure : 1;  // DPI import pure (vs. virtual pure)
     bool m_pureVirtual : 1;  // Pure virtual
-    bool m_recursive : 1;  // Recusive or part of recursion
+    bool m_recursive : 1;  // Recursive or part of recursion
     bool m_underGenerate : 1;  // Under generate (for warning)
     bool m_virtual : 1;  // Virtual method in class
     VLifetime m_lifetime;  // Lifetime
@@ -175,7 +175,7 @@ public:
     bool isFirstInMyListOfStatements(AstNode* n) const override { return n == stmtsp(); }
 };
 class AstNodeFile VL_NOT_FINAL : public AstNode {
-    // Emitted Otput file
+    // Emitted Output file
     // Parents:  NETLIST
     // @astgen op1 := tblockp : Optional[AstTextBlock]
 private:
@@ -210,7 +210,7 @@ private:
     bool m_modTrace : 1;  // Tracing this module
     bool m_inLibrary : 1;  // From a library, no error if not used, never top level
     bool m_dead : 1;  // LinkDot believes is dead; will remove in Dead visitors
-    bool m_hierBlock : 1;  // Hiearchical Block marked by HIER_BLOCK pragma
+    bool m_hierBlock : 1;  // Hierarchical Block marked by HIER_BLOCK pragma
     bool m_internal : 1;  // Internally created
     bool m_recursive : 1;  // Recursive module
     bool m_recursiveClone : 1;  // If recursive, what module it clones, otherwise nullptr
@@ -356,7 +356,7 @@ class AstNodeCoverOrAssert VL_NOT_FINAL : public AstNodeStmt {
     // @astgen op1 := propp : AstNode
     // @astgen op2 := sentreep : Optional[AstSenTree]
     // op3 used by some sub-types only
-    // @astgen op4 := passsp: List[AstNode] // Statments when propp is passing/truthly
+    // @astgen op4 := passsp: List[AstNode] // Statements when propp is passing/truthly
     string m_name;  // Name to report
     const bool m_immediate;  // Immediate assertion/cover
 public:
@@ -1183,7 +1183,7 @@ public:
     void packagep(AstPackage* nodep) { m_packagep = nodep; }
 };
 class AstPin final : public AstNode {
-    // A port or parameter assignment on an instantiaton
+    // A port or parameter assignment on an instantiation
     // @astgen op1 := exprp : Optional[AstNode] // NodeExpr or NodeDType (nullptr if unconnected)
 private:
     int m_pinNum;  // Pin number
@@ -3353,7 +3353,7 @@ public:
 
 // === AstNodeCoverOrAssert ===
 class AstAssert final : public AstNodeCoverOrAssert {
-    // @astgen op3 := failsp: List[AstNode] // Statments when propp is failing/falsey
+    // @astgen op3 := failsp: List[AstNode] // Statements when propp is failing/falsey
 public:
     ASTGEN_MEMBERS_AstAssert;
     AstAssert(FileLine* fl, AstNode* propp, AstNode* passsp, AstNode* failsp, bool immediate,
@@ -3364,7 +3364,7 @@ public:
 };
 class AstAssertIntrinsic final : public AstNodeCoverOrAssert {
     // A $cast or other compiler inserted assert, that must run even without --assert option
-    // @astgen op3 := failsp: List[AstNode] // Statments when propp is failing/falsey
+    // @astgen op3 := failsp: List[AstNode] // Statements when propp is failing/falsey
 public:
     ASTGEN_MEMBERS_AstAssertIntrinsic;
     AstAssertIntrinsic(FileLine* fl, AstNode* propp, AstNode* passsp, AstNode* failsp,
diff --git a/src/V3Class.cpp b/src/V3Class.cpp
index 88cae1fc9..c717e0b6f 100644
--- a/src/V3Class.cpp
+++ b/src/V3Class.cpp
@@ -114,7 +114,7 @@ private:
         iterateChildren(nodep);
         if (m_packageScopep) {
             if (m_ftaskp && m_ftaskp->lifetime().isStatic()) {
-                // Move later, or we wouldn't keep interating the class
+                // Move later, or we wouldn't keep iterating the class
                 // We're really moving the VarScope but we might not
                 // have a pointer to it yet
                 m_toScopeMoves.emplace_back(std::make_pair(nodep, m_packageScopep));
@@ -145,7 +145,7 @@ private:
     }
     void visit(AstCFunc* nodep) override {
         iterateChildren(nodep);
-        // Don't move now, or wouldn't keep interating the class
+        // Don't move now, or wouldn't keep iterating the class
         // TODO move function statics only
         // if (m_classScopep) {
         //    m_toScopeMoves.push_back(std::make_pair(nodep, m_classScopep));
diff --git a/src/V3Config.cpp b/src/V3Config.cpp
index 1c98e2725..0b3d277be 100644
--- a/src/V3Config.cpp
+++ b/src/V3Config.cpp
@@ -258,7 +258,7 @@ class V3ConfigFile final {
     using WaiverSetting = std::pair<V3ErrorCode, std::string>;  // Waive code if string matches
     using Waivers = std::vector<WaiverSetting>;  // List of {code,wildcard string}
 
-    LineAttrMap m_lineAttrs;  // Atributes to line mapping
+    LineAttrMap m_lineAttrs;  // Attributes to line mapping
     IgnLines m_ignLines;  // Ignore line settings
     Waivers m_waivers;  // Waive messages
 
@@ -416,7 +416,7 @@ public:
         for (const auto& ent : m_entries) {
             // We apply shortest match first for each rule component
             // (Otherwise the levels would be useless as "--scope top* --levels 1" would
-            // always match at every scopepart, and we wound't know how to count levels)
+            // always match at every scopepart, and we wouldn't know how to count levels)
             int partLevel = 1;
             for (string::size_type partEnd = 0; true;) {
                 partEnd = scope.find('.', partEnd + 1);
diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index 89972e6c1..4c2640d7f 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -835,7 +835,7 @@ public:
 
         // Set width of masks to expected result width. This is required to prevent later removal
         // of the masking node e.g. by the "AND with all ones" rule. If the result width happens
-        // to be 1, we still need to ensure the AstAnd is not dropped, so use a wider maks in this
+        // to be 1, we still need to ensure the AstAnd is not dropped, so use a wider mask in this
         // special case.
         const int maskWidth = resultWidth == 1 ? VL_IDATASIZE : resultWidth;
 
@@ -1051,7 +1051,7 @@ private:
         // Push down a AND into conditional, when one side of conditional is constant
         // (otherwise we'd be trading one operation for two operations)
         // V3Clean often makes this pattern, as it postpones the AND until
-        // as high as possible, which is usally the right choice, except for this.
+        // as high as possible, which is usually the right choice, except for this.
         AstNodeCond* const condp = VN_CAST(nodep->rhsp(), NodeCond);
         if (!condp) return false;
         if (!VN_IS(condp->thenp(), Const) && !VN_IS(condp->elsep(), Const)) return false;
diff --git a/src/V3DfgDecomposition.cpp b/src/V3DfgDecomposition.cpp
index c8cc73e0d..b81edf12f 100644
--- a/src/V3DfgDecomposition.cpp
+++ b/src/V3DfgDecomposition.cpp
@@ -306,7 +306,7 @@ class ExtractCyclicComponents final {
     void mergeSCCs() {
         // Ensure that component boundaries are always at variables, by merging SCCs. Merging stops
         // at variable boundaries, so we don't need to iterate variables. Constants are reachable
-        // from their sinks, or ar unused, so we don't need to iterate them either.
+        // from their sinks, or are unused, so we don't need to iterate them either.
         for (DfgVertex *vtxp = m_dfg.opVerticesBeginp(), *nextp; vtxp; vtxp = nextp) {
             nextp = vtxp->verticesNext();
             DfgVertex& vtx = *vtxp;
diff --git a/src/V3DfgPasses.cpp b/src/V3DfgPasses.cpp
index 0fc891e13..0b6f43758 100644
--- a/src/V3DfgPasses.cpp
+++ b/src/V3DfgPasses.cpp
@@ -226,7 +226,7 @@ void V3DfgPasses::removeUnused(DfgGraph& dfg) {
 
     // Head of work list. Note that we want all next pointers in the list to be non-zero (including
     // that of the last element). This allows as to do two important things: detect if an element
-    // is in the list by checking for a non-zero next poitner, and easy prefetching without
+    // is in the list by checking for a non-zero next pointer, and easy prefetching without
     // conditionals. The address of the graph is a good sentinel as it is a valid memory address,
     // and we can easily check for the end of the list.
     DfgVertex* const sentinelp = reinterpret_cast<DfgVertex*>(&dfg);
diff --git a/src/V3DfgPeephole.cpp b/src/V3DfgPeephole.cpp
index ee4374230..c62875526 100644
--- a/src/V3DfgPeephole.cpp
+++ b/src/V3DfgPeephole.cpp
@@ -141,7 +141,7 @@ class V3DfgPeephole final : public DfgVisitor {
     AstNodeDType* const m_bitDType = DfgVertex::dtypeForWidth(1);  // Common, so grab it up front
     // Head of work list. Note that we want all next pointers in the list to be non-zero (including
     // that of the last element). This allows as to do two important things: detect if an element
-    // is in the list by checking for a non-zero next poitner, and easy prefetching without
+    // is in the list by checking for a non-zero next pointer, and easy prefetching without
     // conditionals. The 'this' pointer is a good sentinel as it is a valid memory address, and we
     // can easily check for the end of the list.
     DfgVertex* m_workListp = reinterpret_cast<DfgVertex*>(this);
diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp
index b7db6e5b2..bcdeb9618 100644
--- a/src/V3EmitCImp.cpp
+++ b/src/V3EmitCImp.cpp
@@ -543,7 +543,7 @@ class EmitCImp final : EmitCFunc {
         m_modp = modp;
 
         // Emit implementation of this module, if this is an AstClassPackage, then put the
-        // corresponding AstClass implementation in the same file as often optimziations are
+        // corresponding AstClass implementation in the same file as often optimizations are
         // possible when both are seen by the compiler
         // TODO: is the above comment still true?
 
diff --git a/src/V3EmitCMain.cpp b/src/V3EmitCMain.cpp
index ca6cc31ea..992720031 100644
--- a/src/V3EmitCMain.cpp
+++ b/src/V3EmitCMain.cpp
@@ -51,7 +51,7 @@ private:
         // Not defining main_time/vl_time_stamp, so
         v3Global.opt.addCFlags("-DVL_TIME_CONTEXT");  // On MSVC++ anyways
 
-        // Heavly commented output, as users are likely to look at or copy this code
+        // Heavily commented output, as users are likely to look at or copy this code
         ofp()->putsHeader();
         puts("// DESCRIPTION: main() calling loop, created with Verilator --main\n");
         puts("\n");
diff --git a/src/V3FileLine.h b/src/V3FileLine.h
index b846bba22..4453f0db6 100644
--- a/src/V3FileLine.h
+++ b/src/V3FileLine.h
@@ -81,7 +81,7 @@ class FileLineSingleton final {
     msgEnSetIdx_t addMsgEnBitSet(const MsgEnBitSet& bitSet);
     // Add index of default bitset
     msgEnSetIdx_t defaultMsgEnIndex();
-    // Set bitIdx to value in bitset at interned idnex setIdx, return interned index of result
+    // Set bitIdx to value in bitset at interned index setIdx, return interned index of result
     msgEnSetIdx_t msgEnSetBit(msgEnSetIdx_t setIdx, size_t bitIdx, bool value);
     // Return index to intersection set
     msgEnSetIdx_t msgEnAnd(msgEnSetIdx_t lhsIdx, msgEnSetIdx_t rhsIdx);
diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp
index 3898d0a6d..ead1d325f 100644
--- a/src/V3Gate.cpp
+++ b/src/V3Gate.cpp
@@ -785,7 +785,7 @@ private:
     std::unordered_set<AstNode*> m_nodeDeleteds;  // Any node in this hash was deleted
 
     bool same(AstNode* node1p, AstNode* node2p) {
-        // Regarding the complexity of this funcition 'same':
+        // Regarding the complexity of this function 'same':
         // Applying this comparison function to a a set of n trees pairwise is O(n^2) in the
         // number of comparisons (number of pairs). AstNode::sameTree itself, is O(sizeOfTree) in
         // the worst case, which happens if the operands of sameTree are indeed identical copies,
diff --git a/src/V3Global.cpp b/src/V3Global.cpp
index 20daa8177..73b083d83 100644
--- a/src/V3Global.cpp
+++ b/src/V3Global.cpp
@@ -1,6 +1,6 @@
 // -*- mode: C++; c-file-style: "cc-mode" -*-
 //*************************************************************************
-// DESCRIPTION: Verilator: Common implemenetations
+// DESCRIPTION: Verilator: Common implementations
 //
 // Code available from: https://verilator.org
 //
diff --git a/src/V3Global.h b/src/V3Global.h
index 6c8f8dc86..bcbdc172f 100644
--- a/src/V3Global.h
+++ b/src/V3Global.h
@@ -126,7 +126,7 @@ public:
     V3Global() {}
     void boot();
     void clear();
-    void shutdown();  // Release allocated resorces
+    void shutdown();  // Release allocated resources
     // ACCESSORS (general)
     AstNetlist* rootp() const VL_MT_SAFE { return m_rootp; }
     VWidthMinUsage widthMinUsage() const { return m_widthMinUsage; }
diff --git a/src/V3HierBlock.cpp b/src/V3HierBlock.cpp
index a1a2342aa..e1f258ccd 100644
--- a/src/V3HierBlock.cpp
+++ b/src/V3HierBlock.cpp
@@ -118,7 +118,7 @@ V3HierBlock::StrGParams V3HierBlock::stringifyParams(const GParams& gparams, boo
             // V3Param.cpp. See also ParamVisitor::checkSupportedParam() in the file.
             if (constp->isDouble()) {
                 // 64 bit width of hex can be expressed with 16 chars.
-                // 32 chars must be long enough for hexadecial floating point
+                // 32 chars must be long enough for hexadecimal floating point
                 // considering prefix of '0x', '.', and 'P'.
                 std::vector<char> hexFpStr(32, '\0');
                 const int len = VL_SNPRINTF(hexFpStr.data(), hexFpStr.size(), "%a",
@@ -377,7 +377,7 @@ V3HierBlockPlan::HierVector V3HierBlockPlan::hierBlocksSorted() const {
         const V3HierBlock* hblockp = sorted[i];
         const V3HierBlock::HierBlockSet& p = hblockp->parents();
         for (V3HierBlock::HierBlockSet::const_iterator it = p.begin(); it != p.end(); ++it) {
-            // Delete hblockp from parrents. If a parent does not have a child anymore, then it is
+            // Delete hblockp from parents. If a parent does not have a child anymore, then it is
             // a leaf too.
             const auto parentIt = childrenOfHierBlock.find(*it);
             UASSERT_OBJ(parentIt != childrenOfHierBlock.end(), (*it)->modp(), "must be included");
diff --git a/src/V3HierBlock.h b/src/V3HierBlock.h
index 7526423d5..28df43ff7 100644
--- a/src/V3HierBlock.h
+++ b/src/V3HierBlock.h
@@ -87,14 +87,14 @@ public:
     string hierGenerated(bool withDir) const;
     // Returns the original HDL file if it is not included in v3Global.opt.vFiles().
     string vFileIfNecessary() const;
-    // Write command line argumuents to .f file for this hierarchical block
+    // Write command line arguments to .f file for this hierarchical block
     void writeCommandArgsFile(bool forCMake) const;
     string commandArgsFileName(bool forCMake) const;
 };
 
 //######################################################################
 
-// Holds relashonship between AstNodeModule and V3HierBlock
+// Holds relationship between AstNodeModule and V3HierBlock
 class V3HierBlockPlan final {
     using HierMap = std::unordered_map<const AstNodeModule*, V3HierBlock*>;
     HierMap m_blocks;
diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp
index e0338e071..3fedd9803 100644
--- a/src/V3Inst.cpp
+++ b/src/V3Inst.cpp
@@ -510,7 +510,7 @@ public:
         // If a pin connection is "simple" leave it as-is
         // Else create a intermediate wire to perform the interconnect
         // Return the new assignment, if one was made
-        // Note this module calles cloneTree() via new AstVar
+        // Note this module calls cloneTree() via new AstVar
         AstVar* const pinVarp = pinp->modVarp();
         if (!pinp->exprp()) {
             // No-connect, perhaps promote based on `unconnected_drive,
diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index e26272673..ea67c2aea 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -560,7 +560,7 @@ private:
             AstNode* scanp = nodep;
             // Skip over the New's statement
             for (; scanp && !VN_IS(scanp, StmtExpr); scanp = scanp->backp()) {}
-            if (VN_IS(scanp, StmtExpr)) {  // Ignore warnign if something not understood
+            if (VN_IS(scanp, StmtExpr)) {  // Ignore warning if something not understood
                 scanp = scanp->backp();
                 for (; scanp; scanp = scanp->backp()) {
                     if (VN_IS(scanp, NodeStmt) || VN_IS(scanp, NodeModule)
diff --git a/src/V3MergeCond.cpp b/src/V3MergeCond.cpp
index 04e3287fa..51f4e1679 100644
--- a/src/V3MergeCond.cpp
+++ b/src/V3MergeCond.cpp
@@ -177,7 +177,7 @@ class CodeMotionAnalysisVisitor final : public VNVisitor {
     std::vector<V3DupFinder> m_stack;
     StmtProperties* m_propsp = nullptr;  // StmtProperties structure of current AstNodeStmt
 
-    // Extract condition expression from a megeable conditional statement, if any
+    // Extract condition expression from a mergeable conditional statement, if any
     static AstNodeExpr* extractCondition(const AstNodeStmt* nodep) {
         AstNodeExpr* conditionp = nullptr;
         if (const AstNodeAssign* const assignp = VN_CAST(nodep, NodeAssign)) {
@@ -590,7 +590,7 @@ private:
     }
 
     // Fold the RHS expression of an assignment assuming the given condition state.
-    // Unlink bits from the RHS which is only used once, and can be reused (is an unomdified
+    // Unlink bits from the RHS which is only used once, and can be reused (is an unmodified
     // sub-tree). What remains of the RHS is expected to be deleted by the caller.
     AstNodeExpr* foldAndUnlink(AstNodeExpr* rhsp, bool condTrue) {
         if (rhsp->sameTree(m_mgCondp)) {
@@ -793,7 +793,7 @@ private:
     }
 
     // If this node is the next expected node and is helpful to add to the list, do so,
-    // otherwise end the current merge. Return ture if added, false if ended merge.
+    // otherwise end the current merge. Return true if added, false if ended merge.
     bool addIfHelpfulElseEndMerge(AstNodeStmt* nodep) {
         UASSERT_OBJ(m_mgFirstp, nodep, "List must be open");
         if (!checkOrMakeMergeable(nodep)) return false;
diff --git a/src/V3OptionParser.h b/src/V3OptionParser.h
index 23da89245..d087e71e5 100644
--- a/src/V3OptionParser.h
+++ b/src/V3OptionParser.h
@@ -29,8 +29,8 @@
 class VOptionBool;
 #endif
 
-// Typycal usage would look as below.
-// See also V3Options::parseOptsList() in V3Optoins.cpp for more detailed usage.
+// Typical usage would look as below.
+// See also V3Options::parseOptsList() in V3Options.cpp for more detailed usage.
 //
 //    V3OptionParser parser;
 //    V3OptionParser::AppendHelper DECL_OPTION{parser};
@@ -89,8 +89,8 @@ class V3OptionParser::ActionIfs VL_NOT_FINAL {
 public:
     virtual ~ActionIfs() = default;
     virtual bool isValueNeeded() const = 0;  // Need val of "-opt val"
-    virtual bool isFOnOffAllowed() const = 0;  // true if "-fno-opt" is allowd
-    virtual bool isOnOffAllowed() const = 0;  // true if "-no-opt" is allowd
+    virtual bool isFOnOffAllowed() const = 0;  // true if "-fno-opt" is allowed
+    virtual bool isOnOffAllowed() const = 0;  // true if "-no-opt" is allowed
     virtual bool isPartialMatchAllowed() const = 0;  // true if "-Wno-" matches "-Wno-fatal"
     virtual bool isUndocumented() const = 0;  // Will not be suggested in typo
     // Set a value or run callback
@@ -117,7 +117,7 @@ public:
 
 private:
     // MEMBERS
-    V3OptionParser& m_parser;  // The actual option registory
+    V3OptionParser& m_parser;  // The actual option registry
 
 public:
     // METHODS
diff --git a/src/V3Order.cpp b/src/V3Order.cpp
index 8bd94252b..037b16230 100644
--- a/src/V3Order.cpp
+++ b/src/V3Order.cpp
@@ -173,7 +173,7 @@ class OrderBuildVisitor final : public VNVisitor {
 
     // Current AstScope being processed
     AstScope* m_scopep = nullptr;
-    // Sensitivity list for clocked logic, nullptr for combinational and hybird logic
+    // Sensitivity list for clocked logic, nullptr for combinational and hybrid logic
     AstSenTree* m_domainp = nullptr;
     // Sensitivity list for hybrid logic, nullptr for everything else
     AstSenTree* m_hybridp = nullptr;
@@ -810,7 +810,7 @@ class OrderProcess final : VNDeleter {
 
     SenTreeFinder m_finder;  // Global AstSenTree manager
     AstSenTree* const m_deleteDomainp;  // Dummy AstSenTree indicating needs deletion
-    const string m_tag;  // Subtring to add to generated names
+    const string m_tag;  // Substring to add to generated names
     const bool m_slow;  // Ordering slow code
     std::vector<AstNode*> m_result;  // The result nodes (~statements) in their sequential order
 
diff --git a/src/V3PairingHeap.h b/src/V3PairingHeap.h
index 9904225f3..d7dc489d4 100644
--- a/src/V3PairingHeap.h
+++ b/src/V3PairingHeap.h
@@ -80,7 +80,7 @@ public:
             return result;
         }
 
-        // Minimal convenience acessors and operators
+        // Minimal convenience accessors and operators
         VL_ATTR_ALWINLINE Node* ptr() const { return m_ptr; }
         VL_ATTR_ALWINLINE operator bool() const { return m_ptr; }
         VL_ATTR_ALWINLINE bool operator!() const { return !m_ptr; }
@@ -214,7 +214,7 @@ public:
         if (nodep == m_root.ptr()) return;
         // Otherwise we do have a little work to do
         if (!nodep->m_kids) {
-            // If the node has no children, replace it with its siblings (migtht be null)
+            // If the node has no children, replace it with its siblings (might be null)
             nodep->replaceWith(nodep->m_next.unlink());
         } else if (!nodep->m_next) {
             // If the node has no siblings, replace it with its children
diff --git a/src/V3Param.cpp b/src/V3Param.cpp
index 969ec8e30..421586b3e 100644
--- a/src/V3Param.cpp
+++ b/src/V3Param.cpp
@@ -198,7 +198,7 @@ public:
             }
             return v3EpsilonEqual(var, hierOptParamp->num().toDouble());
         } else {  // Now integer type is assumed
-            // Bitwidth of hierOptParamp is accurate because V3Width already caluclated in the
+            // Bitwidth of hierOptParamp is accurate because V3Width already calculated in the
             // previous run. Bitwidth of pinValuep is before width analysis, so pinValuep is casted
             // to hierOptParamp width.
             V3Number varNum{pinValuep, hierOptParamp->num().width()};
@@ -495,7 +495,7 @@ class ParamProcessor final {
                     if (varp->isGParam()) {
                         AstConst* const constp = VN_CAST(varp->valuep(), Const);
                         // constp can be nullptr if the parameter is not used to instantiate sub
-                        // module. varp->valuep() is not contified yet in the case.
+                        // module. varp->valuep() is not constified yet in the case.
                         // nullptr means that the parameter is using some default value.
                         params.emplace(varp->name(), constp);
                     }
diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp
index a0e4977db..278dd2a2b 100644
--- a/src/V3ParseGrammar.cpp
+++ b/src/V3ParseGrammar.cpp
@@ -191,7 +191,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name,
         }
     }
     if (type == VVarType::GENVAR) {
-        // Should be impossible as the grammer blocks this, but...
+        // Should be impossible as the grammar blocks this, but...
         if (arrayp) fileline->v3error("Genvars may not be arrayed: " << name);  // LCOV_EXCL_LINE
     }
 
diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h
index 961e87216..7a5eeefbe 100644
--- a/src/V3ParseImp.h
+++ b/src/V3ParseImp.h
@@ -240,7 +240,7 @@ public:
     }
 
     // Bison sometimes needs error context without a token, so remember last token's line
-    // Only use this if do not have and cannot get a token-relevent fileline
+    // Only use this if do not have and cannot get a token-relevant fileline
     FileLine* bisonLastFileline() const { return m_bisonLastFileline; }
 
     // Return next token, for bison, since bison isn't class based, use a global THIS
diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp
index 6957331fd..15817b78f 100644
--- a/src/V3PreProc.cpp
+++ b/src/V3PreProc.cpp
@@ -1002,7 +1002,7 @@ int V3PreProcImp::getStateToken() {
 
         if (tok == VP_DEFREF_JOIN) {
             // Here's something fun and unspecified as yet:
-            // The existence of non-existance of a base define changes `` expansion
+            // The existence of non-existence of a base define changes `` expansion
             //  `define QA_b zzz
             //  `define Q1 `QA``_b
             //   1Q1 -> zzz
@@ -1249,7 +1249,7 @@ int V3PreProcImp::getStateToken() {
                 refp->nextarg(refp->nextarg() + rtn);
                 goto next_tok;
             } else if (tok == VP_STRIFY) {
-                // We must expand stringinfication, when done will return to this state
+                // We must expand stringification, when done will return to this state
                 statePush(ps_STRIFY);
                 goto next_tok;
             } else {
diff --git a/src/V3ProtectLib.cpp b/src/V3ProtectLib.cpp
index aefb9fa35..27a088878 100644
--- a/src/V3ProtectLib.cpp
+++ b/src/V3ProtectLib.cpp
@@ -151,7 +151,7 @@ private:
 
         // Timescale
         if (v3Global.opt.hierChild() && v3Global.rootp()->timescaleSpecified()) {
-            // Emit timescale for hierarhical verilation if input HDL specifies timespec
+            // Emit timescale for hierarchical verilation if input HDL specifies timespec
             txtp->addText(fl, std::string{"timeunit "} + modp->timeunit().ascii() + ";\n");
             txtp->addText(fl, std::string{"timeprecision "}
                                   + +v3Global.rootp()->timeprecision().ascii() + ";\n");
diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp
index 84fc939b0..36dc28712 100644
--- a/src/V3Sched.cpp
+++ b/src/V3Sched.cpp
@@ -349,7 +349,7 @@ AstSenTree* createTriggerSenTree(AstNetlist* netlistp, AstVarScope* const vscp,
 // Utility for extra trigger allocation
 
 class ExtraTriggers final {
-    std::vector<string> m_descriptions;  // Human readable descirption of extra triggers
+    std::vector<string> m_descriptions;  // Human readable description of extra triggers
 
 public:
     ExtraTriggers() = default;
diff --git a/src/V3Sched.h b/src/V3Sched.h
index efde069af..3132706e8 100644
--- a/src/V3Sched.h
+++ b/src/V3Sched.h
@@ -79,7 +79,7 @@ struct LogicClasses final {
     LogicByScope m_initial;  // initial blocks
     LogicByScope m_final;  // final blocks
     LogicByScope m_comb;  // Combinational logic (logic with implicit sensitivities)
-    LogicByScope m_clocked;  // Clocked (or sequential) logic (logic with explictit sensitivities)
+    LogicByScope m_clocked;  // Clocked (or sequential) logic (logic with explicit sensitivities)
     LogicByScope m_hybrid;  // Hybrid logic (combinational logic with some explicit sensitivities)
     LogicByScope m_postponed;  // Postponed logic ($strobe)
 
diff --git a/src/V3SenExprBuilder.h b/src/V3SenExprBuilder.h
index f4294368f..fe7c30f08 100644
--- a/src/V3SenExprBuilder.h
+++ b/src/V3SenExprBuilder.h
@@ -32,7 +32,7 @@ class SenExprBuilder final {
     AstScope* const m_scopep;  // The scope
 
     std::vector<AstVar*> m_locals;  // Trigger eval local variables
-    std::vector<AstNodeStmt*> m_inits;  // Initialization statements for prevoius values
+    std::vector<AstNodeStmt*> m_inits;  // Initialization statements for previous values
     std::vector<AstNodeStmt*> m_preUpdates;  // Pre update assignments
     std::vector<AstNodeStmt*> m_postUpdates;  // Post update assignments
 
@@ -40,7 +40,7 @@ class SenExprBuilder final {
     std::unordered_map<VNRef<AstNode>, AstVarScope*> m_curr;  // The 'current value' signals
     std::unordered_set<VNRef<AstNode>> m_hasPreUpdate;  // Whether the given sen expression already
                                                         // has an update statement in m_preUpdates
-    std::unordered_set<VNRef<AstNode>> m_hasPostUpdate;  // Likewis for m_postUpdates
+    std::unordered_set<VNRef<AstNode>> m_hasPostUpdate;  // Likewise for m_postUpdates
 
     V3UniqueNames m_currNames{"__Vtrigcurrexpr"};  // For generating unique current value
                                                    // signal names
diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp
index bc6786ba6..da1b95c87 100644
--- a/src/V3SplitVar.cpp
+++ b/src/V3SplitVar.cpp
@@ -14,9 +14,9 @@
 //
 //*************************************************************************
 // V3SplitVar divides a variable into multiple variables to avoid UNOPTFLAT warning
-// and get better perfomance.
+// and get better performance.
 // Variables to be split must be marked by /*verilator split_var*/ metacomment.
-// There are sveral kinds of data types that may cause the warning.
+// There are several kinds of data types that may cause the warning.
 // 1) Unpacked arrays
 // 2) Packed arrays
 // 3) Unpacked structs
@@ -1142,7 +1142,7 @@ class SplitPackedVarVisitor final : public VNVisitor, public SplitVarImpl {
                     }
                 }
                 // If varp is an argument of task/func, need to update temporary var
-                // everytime the var is updated. See also another call of connectPortAndVar() in
+                // every time the var is updated. See also another call of connectPortAndVar() in
                 // split()
                 if (varp->isIO() && (varp->isFuncLocal() || varp->isFuncReturn()))
                     connectPortAndVar(vars, varp, ref.nodep());
diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp
index cd5a1eba7..24cbb7da5 100644
--- a/src/V3Tristate.cpp
+++ b/src/V3Tristate.cpp
@@ -656,7 +656,7 @@ class TristateVisitor final : public TristateBaseVisitor {
     void aggregateTriSameStrength(AstNodeModule* nodep, AstVar* const varp, AstVar* const envarp,
                                   RefStrengthVec::iterator beginStrength,
                                   RefStrengthVec::iterator endStrength) {
-        // For each driver seperate variables (normal and __en) are created and initialized with
+        // For each driver separate variables (normal and __en) are created and initialized with
         // values. In case of normal variable, the original expression is reused. Their values are
         // aggregated using | to form one expression, which are assigned to varp end envarp.
         AstNodeExpr* orp = nullptr;
diff --git a/src/V3Undriven.cpp b/src/V3Undriven.cpp
index 2a2b2943d..68abc5ee0 100644
--- a/src/V3Undriven.cpp
+++ b/src/V3Undriven.cpp
@@ -386,7 +386,7 @@ private:
             if (m_inBBox || nodep->access().isReadOrRW()
                 || fdrv
                 // Inouts have only isWrite set, as we don't have more
-                // information and operating on module boundry, treat as
+                // information and operating on module boundary, treat as
                 // both read and writing
                 || m_inInoutPin)
                 entryp->usedWhole();
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index e7135d834..1c9ab3a85 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1138,7 +1138,7 @@ private:
         if (nodep->didWidthAndSet()) return;
         if (m_vup && m_vup->prelim()) {
             if (VN_IS(nodep->dtypep()->skipRefToEnump(), EnumDType)) {
-                // Assume this constant was properly casted ealier
+                // Assume this constant was properly casted earlier
                 // (Otherwise it couldn't have an enum data type)
             } else if (nodep->num().isString()) {
                 nodep->dtypeSetString();
@@ -1713,7 +1713,7 @@ private:
             userIterate(nodep->subDTypep(), nullptr);
             nodep->refDTypep(iterateEditMoveDTypep(nodep, nodep->subDTypep()));
             nodep->typedefp(nullptr);  // Note until line above subDTypep() may have followed this
-            // Widths are resolved, but special iterate to check for recurstion
+            // Widths are resolved, but special iterate to check for recursion
             userIterate(nodep->subDTypep(), nullptr);
         }
         // Effectively nodep->dtypeFrom(nodep->dtypeSkipRefp());
@@ -1732,7 +1732,7 @@ private:
                                                           << refp->warnOther()
                                                           << "... Location of reference\n"
                                                           << refp->warnContextSecondary());
-            // May cause internel error but avoids infinite loop on dump
+            // May cause internal error but avoids infinite loop on dump
             refp->typedefp(nullptr);
             VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
             return;
@@ -3789,7 +3789,7 @@ private:
             const auto it = patmap.find(memp);
             AstPatMember* patp = nullptr;
             if (it == patmap.end()) {
-                // default or deafult_type assignment
+                // default or default_type assignment
                 if (AstNodeUOrStructDType* const memp_nested_vdtypep
                     = VN_CAST(memp->virtRefDTypep(), NodeUOrStructDType)) {
                     newp = nestedvalueConcat_patternUOrStruct(memp_nested_vdtypep, defaultp, newp,

From 0809c17ce133f198b823e67456b9d877c40c2787 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 2 Dec 2022 19:17:29 -0500
Subject: [PATCH 124/156] Tests: Rename some tests that should be _bad.

---
 ...l_2.pl => t_assert_property_fail_2_bad.pl} |   0
 test_regress/t/t_case_enum_complete.pl        |   1 -
 test_regress/t/t_castdyn_bbox.pl              |   1 -
 test_regress/t/t_flag_wfatal.pl               |   1 -
 test_regress/t/t_interface_modportlist.pl     |   1 -
 test_regress/t/t_lint_edge_real.out           |   5 -
 test_regress/t/t_lint_edge_real_bad.out       |   5 +
 ...t_edge_real.pl => t_lint_edge_real_bad.pl} |   0
 ...int_edge_real.v => t_lint_edge_real_bad.v} |   0
 ...t_infinite.out => t_lint_infinite_bad.out} |   8 +-
 ...int_infinite.pl => t_lint_infinite_bad.pl} |   0
 ..._lint_infinite.v => t_lint_infinite_bad.v} |   0
 test_regress/t/t_lint_nullport.out            | 108 ------------------
 test_regress/t/t_lint_nullport_bad.out        | 108 ++++++++++++++++++
 ...int_nullport.pl => t_lint_nullport_bad.pl} |   0
 ..._lint_nullport.v => t_lint_nullport_bad.v} |   0
 test_regress/t/t_runflag_errorlimit.out       |   7 --
 test_regress/t/t_runflag_errorlimit_bad.out   |   7 ++
 ...orlimit.pl => t_runflag_errorlimit_bad.pl} |   0
 ...rrorlimit.v => t_runflag_errorlimit_bad.v} |   0
 test_regress/t/t_runflag_seed.pl              |   2 -
 ...dentifier.out => t_std_identifier_bad.out} |   2 +-
 ..._identifier.pl => t_std_identifier_bad.pl} |   0
 ...td_identifier.v => t_std_identifier_bad.v} |   0
 ...r.cpp => t_trace_open_wrong_order_bad.cpp} |   5 +-
 ...der.pl => t_trace_open_wrong_order_bad.pl} |   0
 ...order.v => t_trace_open_wrong_order_bad.v} |   0
 27 files changed, 128 insertions(+), 133 deletions(-)
 rename test_regress/t/{t_assert_property_fail_2.pl => t_assert_property_fail_2_bad.pl} (100%)
 delete mode 100644 test_regress/t/t_lint_edge_real.out
 create mode 100644 test_regress/t/t_lint_edge_real_bad.out
 rename test_regress/t/{t_lint_edge_real.pl => t_lint_edge_real_bad.pl} (100%)
 rename test_regress/t/{t_lint_edge_real.v => t_lint_edge_real_bad.v} (100%)
 rename test_regress/t/{t_lint_infinite.out => t_lint_infinite_bad.out} (53%)
 rename test_regress/t/{t_lint_infinite.pl => t_lint_infinite_bad.pl} (100%)
 rename test_regress/t/{t_lint_infinite.v => t_lint_infinite_bad.v} (100%)
 delete mode 100644 test_regress/t/t_lint_nullport.out
 create mode 100644 test_regress/t/t_lint_nullport_bad.out
 rename test_regress/t/{t_lint_nullport.pl => t_lint_nullport_bad.pl} (100%)
 rename test_regress/t/{t_lint_nullport.v => t_lint_nullport_bad.v} (100%)
 delete mode 100644 test_regress/t/t_runflag_errorlimit.out
 create mode 100644 test_regress/t/t_runflag_errorlimit_bad.out
 rename test_regress/t/{t_runflag_errorlimit.pl => t_runflag_errorlimit_bad.pl} (100%)
 rename test_regress/t/{t_runflag_errorlimit.v => t_runflag_errorlimit_bad.v} (100%)
 rename test_regress/t/{t_std_identifier.out => t_std_identifier_bad.out} (58%)
 rename test_regress/t/{t_std_identifier.pl => t_std_identifier_bad.pl} (100%)
 rename test_regress/t/{t_std_identifier.v => t_std_identifier_bad.v} (100%)
 rename test_regress/t/{t_trace_open_wrong_order.cpp => t_trace_open_wrong_order_bad.cpp} (88%)
 rename test_regress/t/{t_trace_open_wrong_order.pl => t_trace_open_wrong_order_bad.pl} (100%)
 rename test_regress/t/{t_trace_open_wrong_order.v => t_trace_open_wrong_order_bad.v} (100%)

diff --git a/test_regress/t/t_assert_property_fail_2.pl b/test_regress/t/t_assert_property_fail_2_bad.pl
similarity index 100%
rename from test_regress/t/t_assert_property_fail_2.pl
rename to test_regress/t/t_assert_property_fail_2_bad.pl
diff --git a/test_regress/t/t_case_enum_complete.pl b/test_regress/t/t_case_enum_complete.pl
index c2379584a..59837c4db 100755
--- a/test_regress/t/t_case_enum_complete.pl
+++ b/test_regress/t/t_case_enum_complete.pl
@@ -12,7 +12,6 @@ scenarios(linter => 1);
 
 lint(
     verilator_flags2 => ["--lint-only -Wwarn-CASEINCOMPLETE"],
-    fails => 0,
     );
 
 ok(1);
diff --git a/test_regress/t/t_castdyn_bbox.pl b/test_regress/t/t_castdyn_bbox.pl
index 59ccbb0ea..3c7a5909b 100755
--- a/test_regress/t/t_castdyn_bbox.pl
+++ b/test_regress/t/t_castdyn_bbox.pl
@@ -14,7 +14,6 @@ top_filename("t/t_castdyn.v");
 
 lint(
     verilator_flags2 => ['-bbox-unsup'],
-    fails => 0,
     );
 
 ok(1);
diff --git a/test_regress/t/t_flag_wfatal.pl b/test_regress/t/t_flag_wfatal.pl
index e480941ab..1fee4b430 100755
--- a/test_regress/t/t_flag_wfatal.pl
+++ b/test_regress/t/t_flag_wfatal.pl
@@ -14,7 +14,6 @@ top_filename("t/t_flag_wfatal.v");
 
 lint(
     verilator_flags2 => ["--lint-only -Wno-fatal"],
-    fails => 0,
     expect_filename => $Self->{golden_filename},
     );
 
diff --git a/test_regress/t/t_interface_modportlist.pl b/test_regress/t/t_interface_modportlist.pl
index f3e6a6cf4..78cb97ce0 100755
--- a/test_regress/t/t_interface_modportlist.pl
+++ b/test_regress/t/t_interface_modportlist.pl
@@ -11,7 +11,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    fails => 0,
     verilator_make_gmake => 0,
     make_top_shell => 0,
     make_main => 0,
diff --git a/test_regress/t/t_lint_edge_real.out b/test_regress/t/t_lint_edge_real.out
deleted file mode 100644
index bc9f0f0d5..000000000
--- a/test_regress/t/t_lint_edge_real.out
+++ /dev/null
@@ -1,5 +0,0 @@
-%Error: t/t_lint_edge_real.v:16:22: Edge event control not legal on real type (IEEE 1800-2017 6.12.1)
-                                  : ... In instance t
-   16 |    always @ (posedge rbad) $stop;
-      |                      ^~~~
-%Error: Exiting due to
diff --git a/test_regress/t/t_lint_edge_real_bad.out b/test_regress/t/t_lint_edge_real_bad.out
new file mode 100644
index 000000000..c3fbd266c
--- /dev/null
+++ b/test_regress/t/t_lint_edge_real_bad.out
@@ -0,0 +1,5 @@
+%Error: t/t_lint_edge_real_bad.v:16:22: Edge event control not legal on real type (IEEE 1800-2017 6.12.1)
+                                      : ... In instance t
+   16 |    always @ (posedge rbad) $stop;
+      |                      ^~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_lint_edge_real.pl b/test_regress/t/t_lint_edge_real_bad.pl
similarity index 100%
rename from test_regress/t/t_lint_edge_real.pl
rename to test_regress/t/t_lint_edge_real_bad.pl
diff --git a/test_regress/t/t_lint_edge_real.v b/test_regress/t/t_lint_edge_real_bad.v
similarity index 100%
rename from test_regress/t/t_lint_edge_real.v
rename to test_regress/t/t_lint_edge_real_bad.v
diff --git a/test_regress/t/t_lint_infinite.out b/test_regress/t/t_lint_infinite_bad.out
similarity index 53%
rename from test_regress/t/t_lint_infinite.out
rename to test_regress/t/t_lint_infinite_bad.out
index a47ba62d6..4599a677f 100644
--- a/test_regress/t/t_lint_infinite.out
+++ b/test_regress/t/t_lint_infinite_bad.out
@@ -1,11 +1,11 @@
-%Warning-INFINITELOOP: t/t_lint_infinite.v:10:7: Infinite loop (condition always true)
-                                               : ... In instance t
+%Warning-INFINITELOOP: t/t_lint_infinite_bad.v:10:7: Infinite loop (condition always true)
+                                                   : ... In instance t
    10 |       forever begin end
       |       ^~~~~~~
                        ... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest
                        ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message.
-%Warning-INFINITELOOP: t/t_lint_infinite.v:12:7: Infinite loop (condition always true)
-                                               : ... In instance t
+%Warning-INFINITELOOP: t/t_lint_infinite_bad.v:12:7: Infinite loop (condition always true)
+                                                   : ... In instance t
    12 |       for (reg [31:0] i=0; i>=0; i=i+1) begin end
       |       ^~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_lint_infinite.pl b/test_regress/t/t_lint_infinite_bad.pl
similarity index 100%
rename from test_regress/t/t_lint_infinite.pl
rename to test_regress/t/t_lint_infinite_bad.pl
diff --git a/test_regress/t/t_lint_infinite.v b/test_regress/t/t_lint_infinite_bad.v
similarity index 100%
rename from test_regress/t/t_lint_infinite.v
rename to test_regress/t/t_lint_infinite_bad.v
diff --git a/test_regress/t/t_lint_nullport.out b/test_regress/t/t_lint_nullport.out
deleted file mode 100644
index f08b86c22..000000000
--- a/test_regress/t/t_lint_nullport.out
+++ /dev/null
@@ -1,108 +0,0 @@
-%Warning-NULLPORT: t/t_lint_nullport.v:23:13: Null port on module (perhaps extraneous comma)
-   23 | module t5(a,);
-      |             ^
-                   ... For warning description see https://verilator.org/warn/NULLPORT?v=latest
-                   ... Use "/* verilator lint_off NULLPORT */" and lint_on around source to disable this message.
-%Warning-NULLPORT: t/t_lint_nullport.v:27:13: Null port on module (perhaps extraneous comma)
-   27 | module t6(a,,);
-      |             ^
-%Warning-NULLPORT: t/t_lint_nullport.v:27:14: Null port on module (perhaps extraneous comma)
-   27 | module t6(a,,);
-      |              ^
-%Warning-NULLPORT: t/t_lint_nullport.v:31:15: Null port on module (perhaps extraneous comma)
-   31 | module t7(a,b,);
-      |               ^
-%Warning-NULLPORT: t/t_lint_nullport.v:35:15: Null port on module (perhaps extraneous comma)
-   35 | module t8(a,b,,);
-      |               ^
-%Warning-NULLPORT: t/t_lint_nullport.v:35:16: Null port on module (perhaps extraneous comma)
-   35 | module t8(a,b,,);
-      |                ^
-%Warning-NULLPORT: t/t_lint_nullport.v:39:13: Null port on module (perhaps extraneous comma)
-   39 | module t9(a,,b);
-      |             ^
-%Warning-NULLPORT: t/t_lint_nullport.v:43:14: Null port on module (perhaps extraneous comma)
-   43 | module t10(a,,b,);
-      |              ^
-%Warning-NULLPORT: t/t_lint_nullport.v:43:17: Null port on module (perhaps extraneous comma)
-   43 | module t10(a,,b,);
-      |                 ^
-%Warning-NULLPORT: t/t_lint_nullport.v:47:14: Null port on module (perhaps extraneous comma)
-   47 | module t11(a,,b,,);
-      |              ^
-%Warning-NULLPORT: t/t_lint_nullport.v:47:17: Null port on module (perhaps extraneous comma)
-   47 | module t11(a,,b,,);
-      |                 ^
-%Warning-NULLPORT: t/t_lint_nullport.v:47:18: Null port on module (perhaps extraneous comma)
-   47 | module t11(a,,b,,);
-      |                  ^
-%Warning-NULLPORT: t/t_lint_nullport.v:51:12: Null port on module (perhaps extraneous comma)
-   51 | module t12(,a,,b);
-      |            ^
-%Warning-NULLPORT: t/t_lint_nullport.v:51:15: Null port on module (perhaps extraneous comma)
-   51 | module t12(,a,,b);
-      |               ^
-%Warning-NULLPORT: t/t_lint_nullport.v:55:12: Null port on module (perhaps extraneous comma)
-   55 | module t13(,a,,b,);
-      |            ^
-%Warning-NULLPORT: t/t_lint_nullport.v:55:15: Null port on module (perhaps extraneous comma)
-   55 | module t13(,a,,b,);
-      |               ^
-%Warning-NULLPORT: t/t_lint_nullport.v:55:18: Null port on module (perhaps extraneous comma)
-   55 | module t13(,a,,b,);
-      |                  ^
-%Warning-NULLPORT: t/t_lint_nullport.v:59:12: Null port on module (perhaps extraneous comma)
-   59 | module t14(,a,,b,,);
-      |            ^
-%Warning-NULLPORT: t/t_lint_nullport.v:59:15: Null port on module (perhaps extraneous comma)
-   59 | module t14(,a,,b,,);
-      |               ^
-%Warning-NULLPORT: t/t_lint_nullport.v:59:18: Null port on module (perhaps extraneous comma)
-   59 | module t14(,a,,b,,);
-      |                  ^
-%Warning-NULLPORT: t/t_lint_nullport.v:59:19: Null port on module (perhaps extraneous comma)
-   59 | module t14(,a,,b,,);
-      |                   ^
-%Warning-NULLPORT: t/t_lint_nullport.v:63:12: Null port on module (perhaps extraneous comma)
-   63 | module t15(,,a,,b);
-      |            ^
-%Warning-NULLPORT: t/t_lint_nullport.v:63:13: Null port on module (perhaps extraneous comma)
-   63 | module t15(,,a,,b);
-      |             ^
-%Warning-NULLPORT: t/t_lint_nullport.v:63:16: Null port on module (perhaps extraneous comma)
-   63 | module t15(,,a,,b);
-      |                ^
-%Warning-NULLPORT: t/t_lint_nullport.v:67:12: Null port on module (perhaps extraneous comma)
-   67 | module t16(,,a,,b,);
-      |            ^
-%Warning-NULLPORT: t/t_lint_nullport.v:67:13: Null port on module (perhaps extraneous comma)
-   67 | module t16(,,a,,b,);
-      |             ^
-%Warning-NULLPORT: t/t_lint_nullport.v:67:16: Null port on module (perhaps extraneous comma)
-   67 | module t16(,,a,,b,);
-      |                ^
-%Warning-NULLPORT: t/t_lint_nullport.v:67:19: Null port on module (perhaps extraneous comma)
-   67 | module t16(,,a,,b,);
-      |                   ^
-%Warning-NULLPORT: t/t_lint_nullport.v:71:12: Null port on module (perhaps extraneous comma)
-   71 | module t17(,,a,,b,,);
-      |            ^
-%Warning-NULLPORT: t/t_lint_nullport.v:71:13: Null port on module (perhaps extraneous comma)
-   71 | module t17(,,a,,b,,);
-      |             ^
-%Warning-NULLPORT: t/t_lint_nullport.v:71:16: Null port on module (perhaps extraneous comma)
-   71 | module t17(,,a,,b,,);
-      |                ^
-%Warning-NULLPORT: t/t_lint_nullport.v:71:19: Null port on module (perhaps extraneous comma)
-   71 | module t17(,,a,,b,,);
-      |                   ^
-%Warning-NULLPORT: t/t_lint_nullport.v:71:20: Null port on module (perhaps extraneous comma)
-   71 | module t17(,,a,,b,,);
-      |                    ^
-%Warning-NULLPORT: t/t_lint_nullport.v:75:12: Null port on module (perhaps extraneous comma)
-   75 | module t18(,);
-      |            ^
-%Warning-NULLPORT: t/t_lint_nullport.v:75:13: Null port on module (perhaps extraneous comma)
-   75 | module t18(,);
-      |             ^
-%Error: Exiting due to
diff --git a/test_regress/t/t_lint_nullport_bad.out b/test_regress/t/t_lint_nullport_bad.out
new file mode 100644
index 000000000..1c24a45d7
--- /dev/null
+++ b/test_regress/t/t_lint_nullport_bad.out
@@ -0,0 +1,108 @@
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:23:13: Null port on module (perhaps extraneous comma)
+   23 | module t5(a,);
+      |             ^
+                   ... For warning description see https://verilator.org/warn/NULLPORT?v=latest
+                   ... Use "/* verilator lint_off NULLPORT */" and lint_on around source to disable this message.
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:27:13: Null port on module (perhaps extraneous comma)
+   27 | module t6(a,,);
+      |             ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:27:14: Null port on module (perhaps extraneous comma)
+   27 | module t6(a,,);
+      |              ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:31:15: Null port on module (perhaps extraneous comma)
+   31 | module t7(a,b,);
+      |               ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:35:15: Null port on module (perhaps extraneous comma)
+   35 | module t8(a,b,,);
+      |               ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:35:16: Null port on module (perhaps extraneous comma)
+   35 | module t8(a,b,,);
+      |                ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:39:13: Null port on module (perhaps extraneous comma)
+   39 | module t9(a,,b);
+      |             ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:43:14: Null port on module (perhaps extraneous comma)
+   43 | module t10(a,,b,);
+      |              ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:43:17: Null port on module (perhaps extraneous comma)
+   43 | module t10(a,,b,);
+      |                 ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:47:14: Null port on module (perhaps extraneous comma)
+   47 | module t11(a,,b,,);
+      |              ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:47:17: Null port on module (perhaps extraneous comma)
+   47 | module t11(a,,b,,);
+      |                 ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:47:18: Null port on module (perhaps extraneous comma)
+   47 | module t11(a,,b,,);
+      |                  ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:51:12: Null port on module (perhaps extraneous comma)
+   51 | module t12(,a,,b);
+      |            ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:51:15: Null port on module (perhaps extraneous comma)
+   51 | module t12(,a,,b);
+      |               ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:55:12: Null port on module (perhaps extraneous comma)
+   55 | module t13(,a,,b,);
+      |            ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:55:15: Null port on module (perhaps extraneous comma)
+   55 | module t13(,a,,b,);
+      |               ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:55:18: Null port on module (perhaps extraneous comma)
+   55 | module t13(,a,,b,);
+      |                  ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:59:12: Null port on module (perhaps extraneous comma)
+   59 | module t14(,a,,b,,);
+      |            ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:59:15: Null port on module (perhaps extraneous comma)
+   59 | module t14(,a,,b,,);
+      |               ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:59:18: Null port on module (perhaps extraneous comma)
+   59 | module t14(,a,,b,,);
+      |                  ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:59:19: Null port on module (perhaps extraneous comma)
+   59 | module t14(,a,,b,,);
+      |                   ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:63:12: Null port on module (perhaps extraneous comma)
+   63 | module t15(,,a,,b);
+      |            ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:63:13: Null port on module (perhaps extraneous comma)
+   63 | module t15(,,a,,b);
+      |             ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:63:16: Null port on module (perhaps extraneous comma)
+   63 | module t15(,,a,,b);
+      |                ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:67:12: Null port on module (perhaps extraneous comma)
+   67 | module t16(,,a,,b,);
+      |            ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:67:13: Null port on module (perhaps extraneous comma)
+   67 | module t16(,,a,,b,);
+      |             ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:67:16: Null port on module (perhaps extraneous comma)
+   67 | module t16(,,a,,b,);
+      |                ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:67:19: Null port on module (perhaps extraneous comma)
+   67 | module t16(,,a,,b,);
+      |                   ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:71:12: Null port on module (perhaps extraneous comma)
+   71 | module t17(,,a,,b,,);
+      |            ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:71:13: Null port on module (perhaps extraneous comma)
+   71 | module t17(,,a,,b,,);
+      |             ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:71:16: Null port on module (perhaps extraneous comma)
+   71 | module t17(,,a,,b,,);
+      |                ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:71:19: Null port on module (perhaps extraneous comma)
+   71 | module t17(,,a,,b,,);
+      |                   ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:71:20: Null port on module (perhaps extraneous comma)
+   71 | module t17(,,a,,b,,);
+      |                    ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:75:12: Null port on module (perhaps extraneous comma)
+   75 | module t18(,);
+      |            ^
+%Warning-NULLPORT: t/t_lint_nullport_bad.v:75:13: Null port on module (perhaps extraneous comma)
+   75 | module t18(,);
+      |             ^
+%Error: Exiting due to
diff --git a/test_regress/t/t_lint_nullport.pl b/test_regress/t/t_lint_nullport_bad.pl
similarity index 100%
rename from test_regress/t/t_lint_nullport.pl
rename to test_regress/t/t_lint_nullport_bad.pl
diff --git a/test_regress/t/t_lint_nullport.v b/test_regress/t/t_lint_nullport_bad.v
similarity index 100%
rename from test_regress/t/t_lint_nullport.v
rename to test_regress/t/t_lint_nullport_bad.v
diff --git a/test_regress/t/t_runflag_errorlimit.out b/test_regress/t/t_runflag_errorlimit.out
deleted file mode 100644
index 223b5e2e5..000000000
--- a/test_regress/t/t_runflag_errorlimit.out
+++ /dev/null
@@ -1,7 +0,0 @@
-[0] %Error: t_runflag_errorlimit.v:9: Assertion failed in top.t: One
--Info: t/t_runflag_errorlimit.v:9: Verilog $stop, ignored due to +verilator+error+limit
-[0] %Error: t_runflag_errorlimit.v:10: Assertion failed in top.t: Two
--Info: t/t_runflag_errorlimit.v:10: Verilog $stop, ignored due to +verilator+error+limit
-[0] %Error: t_runflag_errorlimit.v:11: Assertion failed in top.t: Three
-%Error: t/t_runflag_errorlimit.v:11: Verilog $stop
-Aborting...
diff --git a/test_regress/t/t_runflag_errorlimit_bad.out b/test_regress/t/t_runflag_errorlimit_bad.out
new file mode 100644
index 000000000..7cf555ee9
--- /dev/null
+++ b/test_regress/t/t_runflag_errorlimit_bad.out
@@ -0,0 +1,7 @@
+[0] %Error: t_runflag_errorlimit_bad.v:9: Assertion failed in top.t: One
+-Info: t/t_runflag_errorlimit_bad.v:9: Verilog $stop, ignored due to +verilator+error+limit
+[0] %Error: t_runflag_errorlimit_bad.v:10: Assertion failed in top.t: Two
+-Info: t/t_runflag_errorlimit_bad.v:10: Verilog $stop, ignored due to +verilator+error+limit
+[0] %Error: t_runflag_errorlimit_bad.v:11: Assertion failed in top.t: Three
+%Error: t/t_runflag_errorlimit_bad.v:11: Verilog $stop
+Aborting...
diff --git a/test_regress/t/t_runflag_errorlimit.pl b/test_regress/t/t_runflag_errorlimit_bad.pl
similarity index 100%
rename from test_regress/t/t_runflag_errorlimit.pl
rename to test_regress/t/t_runflag_errorlimit_bad.pl
diff --git a/test_regress/t/t_runflag_errorlimit.v b/test_regress/t/t_runflag_errorlimit_bad.v
similarity index 100%
rename from test_regress/t/t_runflag_errorlimit.v
rename to test_regress/t/t_runflag_errorlimit_bad.v
diff --git a/test_regress/t/t_runflag_seed.pl b/test_regress/t/t_runflag_seed.pl
index 84674f3e9..71a259e41 100755
--- a/test_regress/t/t_runflag_seed.pl
+++ b/test_regress/t/t_runflag_seed.pl
@@ -15,12 +15,10 @@ compile(
 
 execute(
     all_run_flags => ["+verilator+seed+5 +SEED=fffffff4"],
-    fails => 0,
     );
 
 execute(
     all_run_flags => ["+verilator+seed+6 +SEED=fffffff2"],
-    fails => 0,
     );
 
 ok(1);
diff --git a/test_regress/t/t_std_identifier.out b/test_regress/t/t_std_identifier_bad.out
similarity index 58%
rename from test_regress/t/t_std_identifier.out
rename to test_regress/t/t_std_identifier_bad.out
index 1b970e684..ee490eb1c 100644
--- a/test_regress/t/t_std_identifier.out
+++ b/test_regress/t/t_std_identifier_bad.out
@@ -1,4 +1,4 @@
-%Error-PKGNODECL: t/t_std_identifier.v:16:20: Package/class 'std' not found, and needs to be predeclared (IEEE 1800-2017 26.3)
+%Error-PKGNODECL: t/t_std_identifier_bad.v:16:20: Package/class 'std' not found, and needs to be predeclared (IEEE 1800-2017 26.3)
    16 |     int baz = foo::std::bar;
       |                    ^~~
                   ... For error description see https://verilator.org/warn/PKGNODECL?v=latest
diff --git a/test_regress/t/t_std_identifier.pl b/test_regress/t/t_std_identifier_bad.pl
similarity index 100%
rename from test_regress/t/t_std_identifier.pl
rename to test_regress/t/t_std_identifier_bad.pl
diff --git a/test_regress/t/t_std_identifier.v b/test_regress/t/t_std_identifier_bad.v
similarity index 100%
rename from test_regress/t/t_std_identifier.v
rename to test_regress/t/t_std_identifier_bad.v
diff --git a/test_regress/t/t_trace_open_wrong_order.cpp b/test_regress/t/t_trace_open_wrong_order_bad.cpp
similarity index 88%
rename from test_regress/t/t_trace_open_wrong_order.cpp
rename to test_regress/t/t_trace_open_wrong_order_bad.cpp
index 56dae22c3..91945222f 100644
--- a/test_regress/t/t_trace_open_wrong_order.cpp
+++ b/test_regress/t/t_trace_open_wrong_order_bad.cpp
@@ -9,13 +9,14 @@
 #include <verilated.h>
 #include <verilated_vcd_c.h>
 
-#include "Vt_trace_open_wrong_order.h"
+#include "Vt_trace_open_wrong_order_bad.h"
+
 using namespace std;
 
 int main(int argc, char** argv) {
     VerilatedContext ctx;
     VerilatedVcdC tfp;
-    Vt_trace_open_wrong_order dut;
+    Vt_trace_open_wrong_order_bad dut;
     ctx.traceEverOn(true);
     tfp.open(VL_STRINGIFY(TEST_OBJ_DIR) "/dump.vcd");  // Error! shall put to the next line!
     dut.trace(&tfp, 99);  // Error!
diff --git a/test_regress/t/t_trace_open_wrong_order.pl b/test_regress/t/t_trace_open_wrong_order_bad.pl
similarity index 100%
rename from test_regress/t/t_trace_open_wrong_order.pl
rename to test_regress/t/t_trace_open_wrong_order_bad.pl
diff --git a/test_regress/t/t_trace_open_wrong_order.v b/test_regress/t/t_trace_open_wrong_order_bad.v
similarity index 100%
rename from test_regress/t/t_trace_open_wrong_order.v
rename to test_regress/t/t_trace_open_wrong_order_bad.v

From 675cc891a5d324210a66b9c665efd0da90a0bb81 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 2 Dec 2022 19:57:40 -0500
Subject: [PATCH 125/156] Tests: Add rerunnable(0)

---
 test_regress/driver.pl | 24 +++++++++++++++++++-----
 1 file changed, 19 insertions(+), 5 deletions(-)

diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 29e7b7c32..03018ac01 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -197,10 +197,11 @@ if ($opt_rerun && $runner->fail_count) {
         ok_cnt => $orig_runner->{ok_cnt},
         skip_cnt => $orig_runner->{skip_cnt});
     foreach my $test (@{$orig_runner->{fail_tests}}) {
-        $test->clean;
         # Reschedule test
+        $test->clean if $test->rerunnable;
         $runner->one_test(pl_filename => $test->{pl_filename},
-                          $test->{scenario} => 1);
+                          $test->{scenario} => 1,
+                          rerun_skipping => !$test->rerunnable);
     }
     $runner->wait_and_report;
 }
@@ -350,9 +351,15 @@ sub one_test {
              my $test = VTest->new(@params,
                                    running_id => $process->{running_id});
              $test->oprint("=" x 50, "\n");
-             unlink $test->{status_filename};
+             unlink $test->{status_filename} if !$params{rerun_skipping};
              $test->_prep;
-             $test->_read;
+             if ($params{rerun_skipping}) {
+                 print "  ---------- Earlier logfiles below; test was rerunnable = 0\n";
+                 system("cat $test->{obj_dir}/*.log");
+                 print "  ---------- Earlier logfiles above; test was rerunnable = 0\n";
+             } else {
+                 $test->_read;
+             }
              # Don't put anything other than _exit after _read,
              # as may call _exit via another path
              $test->_exit;
@@ -575,6 +582,7 @@ sub new {
         context_threads => 0,   # Number of threads to allocate in the context
         benchmark => $opt_benchmark,
         verbose => $opt_verbose,
+        rerunnable => 1,        # Rerun if fails
         run_env => '',
         # All compilers
         v_flags => [split(/\s+/,
@@ -1515,6 +1523,12 @@ sub pli_filename {
     return $self->{pli_filename};
 }
 
+sub rerunnable {
+    my $self = (ref $_[0] ? shift : $Self);
+    $self->{rerunnable} = shift if defined $_[0];
+    return $self->{rerunnable};
+}
+
 sub too_few_cores {
     my $threads = ::calc_threads($Vltmt_threads);
     return $threads < $Vltmt_threads;
@@ -2488,7 +2502,7 @@ sub file_contents {
         my $fh = IO::File->new("<$filename");
         if (!$fh) {
             $_File_Contents_Cache{$filename} = "_Already_Errored_";
-            $self->error("File_grep file not found: " . $filename . "\n");
+            $self->error("File_contents file not found: " . $filename . "\n");
             return $_File_Contents_Cache{$filename};
         }
         local $/; undef $/;

From 84c73686215e1c4511ec10b38deea60258cd0f80 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 3 Dec 2022 11:31:26 -0500
Subject: [PATCH 126/156] Rename std.sv and add to install.

---
 Makefile.in                          |  1 +
 include/{std.sv => verilated_std.sv} | 11 +++++++++++
 src/V3Global.cpp                     |  2 +-
 src/V3Options.cpp                    |  4 +++-
 4 files changed, 16 insertions(+), 2 deletions(-)
 rename include/{std.sv => verilated_std.sv} (89%)

diff --git a/Makefile.in b/Makefile.in
index cebc67a91..fdc785945 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -204,6 +204,7 @@ VL_INST_INC_BLDDIR_FILES = \
 # Files under srcdir, instead of build time
 VL_INST_INC_SRCDIR_FILES = \
 	include/*.[chv]* \
+	include/*.sv \
 	include/gtkwave/*.[chv]* \
 	include/vltstd/*.[chv]* \
 
diff --git a/include/std.sv b/include/verilated_std.sv
similarity index 89%
rename from include/std.sv
rename to include/verilated_std.sv
index 7b27bc98b..996bc951b 100644
--- a/include/std.sv
+++ b/include/verilated_std.sv
@@ -10,6 +10,17 @@
 // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 //
 //*************************************************************************
+///
+/// \file
+/// \brief Verilated IEEE std:: header
+///
+/// This file is included automatically by Verilator when a std::mailbox or
+/// std::semaphore is referenced.
+///
+/// This file is not part of the Verilated public-facing API.
+/// It is only for internal use.
+///
+//*************************************************************************
 
 // verilator lint_off DECLFILENAME
 // verilator lint_off TIMESCALEMOD
diff --git a/src/V3Global.cpp b/src/V3Global.cpp
index 73b083d83..c75b51785 100644
--- a/src/V3Global.cpp
+++ b/src/V3Global.cpp
@@ -67,7 +67,7 @@ void V3Global::readFiles() {
         // Parse the std package
         parser.parseFile(new FileLine{FileLine::commandLineFilename()},
                          V3Options::getStdPackagePath(), false,
-                         "Cannot find std.sv containing built-in std:: definitions: ");
+                         "Cannot find verilated_std.sv containing built-in std:: definitions:");
     }
 
     // Read libraries
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index ca7ee2f3f..688ad5bad 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -706,7 +706,9 @@ string V3Options::getenvVERILATOR_ROOT() {
     return var;
 }
 
-string V3Options::getStdPackagePath() { return getenvVERILATOR_ROOT() + "/include/std.sv"; }
+string V3Options::getStdPackagePath() {
+    return getenvVERILATOR_ROOT() + "/include/verilated_std.sv";
+}
 
 string V3Options::getSupported(const string& var) {
     // If update below, also update V3Options::showVersion()

From ea1b141d133b9a3b4d3c9d1820c8d5315f982f82 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 4 Dec 2022 17:30:51 -0500
Subject: [PATCH 127/156] Support probablity distribution functions.

---
 include/verilated_funcs.h          |  11 ++
 include/verilated_probdist.cpp     | 240 +++++++++++++++++++++++++++++
 src/V3AstNodeExpr.h                | 102 ++++++++++++
 src/V3EmitCInlines.cpp             |   8 +
 src/V3EmitCMake.cpp                |   3 +
 src/V3EmitMk.cpp                   |   1 +
 src/V3Global.h                     |   3 +
 src/V3LinkLValue.cpp               |  15 ++
 src/V3Width.cpp                    |  15 ++
 src/verilog.l                      |   7 +
 src/verilog.y                      |  14 ++
 test_regress/t/t_probdist.pl       |   4 +-
 test_regress/t/t_probdist.v        |  35 ++++-
 test_regress/t/t_probdist_bad.out  |  19 ---
 test_regress/t/t_probdist_bad.pl   |   4 +-
 test_regress/t/t_probdist_cmake.pl |  25 +++
 test_regress/t/t_verilated_all.v   |   9 +-
 17 files changed, 486 insertions(+), 29 deletions(-)
 create mode 100644 include/verilated_probdist.cpp
 delete mode 100644 test_regress/t/t_probdist_bad.out
 create mode 100755 test_regress/t/t_probdist_cmake.pl

diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h
index 7cf7604f6..fe6e98574 100644
--- a/include/verilated_funcs.h
+++ b/include/verilated_funcs.h
@@ -2155,6 +2155,17 @@ extern IData VL_ATOI_N(const std::string& str, int base) VL_PURE;
 
 extern IData VL_FGETS_NI(std::string& dest, IData fpi);
 
+//======================================================================
+// Dist functions
+
+extern IData VL_DIST_CHI_SQUARE(IData& seedr, IData udeg_of_free) VL_MT_SAFE;
+extern IData VL_DIST_ERLANG(IData& seedr, IData uk, IData umean) VL_MT_SAFE;
+extern IData VL_DIST_EXPONENTIAL(IData& seedr, IData umean) VL_MT_SAFE;
+extern IData VL_DIST_NORMAL(IData& seedr, IData umean, IData udeviation) VL_MT_SAFE;
+extern IData VL_DIST_POISSON(IData& seedr, IData umean) VL_MT_SAFE;
+extern IData VL_DIST_T(IData& seedr, IData udeg_of_free) VL_MT_SAFE;
+extern IData VL_DIST_UNIFORM(IData& seedr, IData ustart, IData uend) VL_MT_SAFE;
+
 //======================================================================
 // Conversion functions
 
diff --git a/include/verilated_probdist.cpp b/include/verilated_probdist.cpp
new file mode 100644
index 000000000..d0b5f39ed
--- /dev/null
+++ b/include/verilated_probdist.cpp
@@ -0,0 +1,240 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+//*************************************************************************
+//
+// Code available from: https://verilator.org
+//
+// Copyright 2003-2022 by Wilson Snyder. This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// Lesser General Public License Version 3 or the Perl Artistic License
+// Version 2.0.
+// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+//
+//=========================================================================
+///
+/// \file
+/// \brief Verilated probability distribution implementation code
+///
+/// Verilator always adds this file to the Makefile for the linker.
+///
+/// Those macro/function/variable starting or ending in _ are internal,
+/// however many of the other function/macros here are also internal.
+///
+//=========================================================================
+
+#include "verilated_config.h"
+#include "verilatedos.h"
+
+#include "verilated.h"
+
+//===========================================================================
+// Dist
+
+static double _vl_dbase_uniform(IData& seedr, int32_t start, int32_t end) VL_MT_SAFE {
+    union u_s {
+        float s;
+        unsigned stemp;
+    } u;
+
+    const double d = 0.00000011920928955078125;
+    if (VL_UNLIKELY(seedr == 0)) seedr = 259341593;
+
+    double a;
+    double b;
+    if (VL_UNCOVERABLE(start >= end)) {  // With current usage shound't occur
+        a = 0.0;  // LCOV_EXCL_LINE
+        b = 2147483647.0;  // LCOV_EXCL_LINE
+    } else {
+        a = static_cast<double>(start);
+        b = static_cast<double>(end);
+    }
+    seedr = 69069 * seedr + 1;
+    u.stemp = seedr;
+    u.stemp = (u.stemp >> 9) | 0x3f800000;
+
+    double c = static_cast<double>(u.s);
+    c = c + (c * d);
+    c = ((b - a) * (c - 1.0)) + a;
+    return c;
+}
+
+static double _vl_dbase_normal(IData& seedr, int32_t mean, int32_t deviation) VL_MT_SAFE {
+    double v1 = 0.0;
+    double v2 = 0.0;
+    double s = 1.0;
+    while ((s >= 1.0) || (s == 0.0)) {
+        v1 = _vl_dbase_uniform(seedr, -1, 1);
+        v2 = _vl_dbase_uniform(seedr, -1, 1);
+        s = v1 * v1 + v2 * v2;
+    }
+    s = v1 * std::sqrt(-2.0 * log(s) / s);
+    v1 = static_cast<double>(deviation);
+    v2 = static_cast<double>(mean);
+    return (s * v1 + v2);
+}
+
+static double _vl_dbase_exponential(IData& seedr, int32_t mean) VL_MT_SAFE {
+    double n = _vl_dbase_uniform(seedr, 0, 1);
+    if (n != 0) n = -log(n) * mean;
+    return n;
+}
+
+static double _vl_dbase_chi_square(IData& seedr, int32_t deg_of_free) VL_MT_SAFE {
+    double x;
+    if (deg_of_free % 2) {
+        x = _vl_dbase_normal(seedr, 0, 1);
+        x = x * x;
+    } else {
+        x = 0.0;
+    }
+    for (int32_t k = 2; k <= deg_of_free; k += 2) x = x + 2 * _vl_dbase_exponential(seedr, 1);
+    return x;
+}
+
+IData VL_DIST_CHI_SQUARE(IData& seedr, IData udf) VL_MT_SAFE {
+    const int32_t df = static_cast<int32_t>(udf);
+    if (VL_UNLIKELY(df <= 0)) {
+        // Chi_square distribution must have positive degree of freedom
+        return 0;
+    }
+    double r = _vl_dbase_chi_square(seedr, df);
+    int32_t i;
+    if (r >= 0) {
+        i = static_cast<int32_t>(r + 0.5);
+    } else {
+        r = -r;  // LCOV_EXCL_LINE
+        i = static_cast<int32_t>(r + 0.5);  // LCOV_EXCL_LINE
+        i = -i;  // LCOV_EXCL_LINE
+    }
+    return static_cast<IData>(i);
+}
+
+IData VL_DIST_ERLANG(IData& seedr, IData uk, IData umean) VL_MT_SAFE {
+    const int32_t k = static_cast<int32_t>(uk);
+    const int32_t mean = static_cast<int32_t>(umean);
+    if (VL_UNLIKELY(k <= 0)) {
+        // k-stage erlangian distribution must have positive k
+        return 0;
+    }
+    double x = 1.0;
+    for (int32_t i = 1; i <= k; i++) { x = x * _vl_dbase_uniform(seedr, 0, 1); }
+    const double a = static_cast<double>(mean);
+    const double b = static_cast<double>(k);
+    double r = -a * log(x) / b;
+    int32_t i;
+    if (r >= 0) {
+        i = static_cast<int32_t>(r + 0.5);
+    } else {
+        r = -r;
+        i = static_cast<int32_t>(r + 0.5);
+        i = -i;
+    }
+    return static_cast<IData>(i);
+}
+
+IData VL_DIST_EXPONENTIAL(IData& seedr, IData umean) VL_MT_SAFE {
+    const int32_t mean = static_cast<int32_t>(umean);
+    if (VL_UNLIKELY(mean <= 0)) {
+        // Exponential distribution must have a positive mean
+        return 0;
+    }
+    int32_t i;
+    double r = _vl_dbase_exponential(seedr, mean);
+    if (r >= 0) {
+        i = static_cast<int32_t>(r + 0.5);
+    } else {
+        r = -r;  // LCOV_EXCL_LINE
+        i = static_cast<int32_t>(r + 0.5);  // LCOV_EXCL_LINE
+        i = -i;  // LCOV_EXCL_LINE
+    }
+    return static_cast<IData>(i);
+}
+
+IData VL_DIST_NORMAL(IData& seedr, IData umean, IData usd) VL_MT_SAFE {
+    const int32_t mean = static_cast<int32_t>(umean);
+    const int32_t sd = static_cast<int32_t>(usd);
+    double r = _vl_dbase_normal(seedr, mean, sd);
+    int32_t i;
+    if (r >= 0) {
+        i = static_cast<int32_t>(r + 0.5);
+    } else {
+        r = -r;
+        i = static_cast<int32_t>(r + 0.5);
+        i = -i;
+    }
+    return static_cast<IData>(i);
+}
+
+IData VL_DIST_POISSON(IData& seedr, IData umean) VL_MT_SAFE {
+    const int32_t mean = static_cast<int32_t>(umean);
+    if (VL_UNLIKELY(mean <= 0)) {
+        // Poisson distribution must have a positive mean
+        return 0;
+    }
+    int32_t i = 0;
+    double q = -static_cast<double>(mean);
+    double p = exp(q);
+    q = _vl_dbase_uniform(seedr, 0, 1);
+    while (p < q) {
+        ++i;
+        q = _vl_dbase_uniform(seedr, 0, 1) * q;
+    }
+    return static_cast<IData>(i);
+}
+
+IData VL_DIST_T(IData& seedr, IData udf) VL_MT_SAFE {
+    const int32_t df = static_cast<int32_t>(udf);
+    if (VL_UNLIKELY(df <= 0)) {
+        // t distribution must have positive degree of freedom
+        return 0;
+    }
+    const double chi2 = _vl_dbase_chi_square(seedr, df);
+    const double div = chi2 / static_cast<double>(df);
+    const double root = std::sqrt(div);
+    double r = _vl_dbase_normal(seedr, 0, 1) / root;
+    int32_t i;
+    if (r >= 0) {
+        i = static_cast<int32_t>(r + 0.5);
+    } else {
+        r = -r;
+        i = static_cast<int32_t>(r + 0.5);
+        i = -i;
+    }
+    return static_cast<IData>(i);
+}
+
+IData VL_DIST_UNIFORM(IData& seedr, IData ustart, IData uend) VL_MT_SAFE {
+    int32_t start = static_cast<int32_t>(ustart);
+    int32_t end = static_cast<int32_t>(uend);
+    if (VL_UNLIKELY(start >= end)) return start;
+    int32_t i;
+    if (end != std::numeric_limits<int32_t>::max()) {
+        ++end;
+        const double r = _vl_dbase_uniform(seedr, start, end);
+        if (r >= 0) {
+            i = static_cast<int32_t>(r);
+        } else {
+            i = static_cast<int32_t>(r - 1);
+        }
+        if (i < start) i = start;
+        if (i >= end) i = end - 1;
+    } else if (start != std::numeric_limits<int32_t>::min()) {
+        --start;
+        const double r = _vl_dbase_uniform(seedr, start, end) + 1.0;
+        if (r >= 0) {
+            i = static_cast<int32_t>(r);
+        } else {
+            i = static_cast<int32_t>(r - 1);  // LCOV_EXCL_LINE
+        }
+        if (i <= start) i = start + 1;
+        if (i > end) i = end;
+    } else {
+        double r = (_vl_dbase_uniform(seedr, start, end) + 2147483648.0) / 4294967295.0;
+        r = r * 4294967296.0 - 2147483648.0;
+        if (r >= 0) {
+            i = static_cast<int32_t>(r);
+        } else {
+            i = static_cast<int32_t>(r - 1);
+        }
+    }
+    return static_cast<IData>(i);
+}
diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index c67a4335a..da8683b5c 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -112,6 +112,27 @@ protected:
 public:
     ASTGEN_MEMBERS_AstNodeBiComAsv;
 };
+class AstNodeDistBiop VL_NOT_FINAL : public AstNodeBiop {
+public:
+    AstNodeDistBiop(VNType t, FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
+        : AstNodeBiop{t, fl, lhsp, rhsp} {
+        dtypeSetSigned32();
+    }
+    ASTGEN_MEMBERS_AstNodeDistBiop;
+    bool cleanOut() const override { return false; }
+    bool cleanLhs() const override { return false; }
+    bool cleanRhs() const override { return false; }
+    bool sizeMattersLhs() const override { return false; }
+    bool sizeMattersRhs() const override { return false; }
+    int instrCount() const override { return INSTR_COUNT_DBL_TRIG; }
+    AstNodeExpr* cloneType(AstNodeExpr* lhsp, AstNodeExpr* rhsp) override {
+        V3ERROR_NA;
+        return nullptr;
+    }
+    void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override {
+        V3ERROR_NA;
+    }
+};
 class AstNodeSel VL_NOT_FINAL : public AstNodeBiop {
     // Single bit range extraction, perhaps with non-constant selection or array selection
     // @astgen alias op1 := fromp // Expression we are indexing into
@@ -363,6 +384,27 @@ public:
     int instrCount() const override { return INSTR_COUNT_BRANCH; }
     virtual AstNodeExpr* cloneType(AstNodeExpr* condp, AstNodeExpr* thenp, AstNodeExpr* elsep) = 0;
 };
+class AstNodeDistTriop VL_NOT_FINAL : public AstNodeTriop {
+public:
+    AstNodeDistTriop(VNType t, FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp,
+                     AstNodeExpr* thsp)
+        : AstNodeTriop{t, fl, lhsp, rhsp, thsp} {
+        dtypeSetSigned32();
+    }
+    ASTGEN_MEMBERS_AstNodeDistTriop;
+    bool cleanOut() const override { return false; }
+    bool cleanLhs() const override { return false; }
+    bool cleanRhs() const override { return false; }
+    bool cleanThs() const override { return false; }
+    bool sizeMattersLhs() const override { return false; }
+    bool sizeMattersRhs() const override { return false; }
+    bool sizeMattersThs() const override { return false; }
+    int instrCount() const override { return INSTR_COUNT_DBL_TRIG; }
+    void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs,
+                       const V3Number& ths) override {
+        V3ERROR_NA;
+    }
+};
 class AstNodeUniop VL_NOT_FINAL : public AstNodeExpr {
     // Unary expression
     // @astgen op1 := lhsp : AstNodeExpr
@@ -3532,6 +3574,40 @@ public:
     bool sizeMattersRhs() const override { return false; }
 };
 
+// === AstNodeDistBiop ===
+class AstDistChiSquare final : public AstNodeDistBiop {
+public:
+    AstDistChiSquare(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
+        : ASTGEN_SUPER_DistChiSquare(fl, lhsp, rhsp) {}
+    ASTGEN_MEMBERS_AstDistChiSquare;
+    string emitVerilog() override { return "%f$dist_chi_square(%l, %r)"; }
+    string emitC() override { return "VL_DIST_CHI_SQUARE(%li, %ri)"; }
+};
+class AstDistExponential final : public AstNodeDistBiop {
+public:
+    AstDistExponential(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
+        : ASTGEN_SUPER_DistExponential(fl, lhsp, rhsp) {}
+    ASTGEN_MEMBERS_AstDistExponential;
+    string emitVerilog() override { return "%f$dist_exponential(%l, %r)"; }
+    string emitC() override { return "VL_DIST_EXPONENTIAL(%li, %ri)"; }
+};
+class AstDistPoisson final : public AstNodeDistBiop {
+public:
+    AstDistPoisson(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
+        : ASTGEN_SUPER_DistPoisson(fl, lhsp, rhsp) {}
+    ASTGEN_MEMBERS_AstDistPoisson;
+    string emitVerilog() override { return "%f$dist_poisson(%l, %r)"; }
+    string emitC() override { return "VL_DIST_POISSON(%li, %ri)"; }
+};
+class AstDistT final : public AstNodeDistBiop {
+public:
+    AstDistT(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp)
+        : ASTGEN_SUPER_DistT(fl, lhsp, rhsp) {}
+    ASTGEN_MEMBERS_AstDistT;
+    string emitVerilog() override { return "%f$dist_t(%l, %r)"; }
+    string emitC() override { return "VL_DIST_T(%li, %ri)"; }
+};
+
 // === AstNodeSel ===
 class AstArraySel final : public AstNodeSel {
     void init(AstNode* fromp) {
@@ -4198,6 +4274,32 @@ public:
     }
 };
 
+// === AstNodeDistTriop ===
+class AstDistErlang final : public AstNodeDistTriop {
+public:
+    AstDistErlang(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, AstNodeExpr* thsp)
+        : ASTGEN_SUPER_DistErlang(fl, lhsp, rhsp, thsp) {}
+    ASTGEN_MEMBERS_AstDistErlang;
+    string emitVerilog() override { return "%f$dist_erlang(%l, %r, %t)"; }
+    string emitC() override { return "VL_DIST_ERLANG(%li, %ri, %ti)"; }
+};
+class AstDistNormal final : public AstNodeDistTriop {
+public:
+    AstDistNormal(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, AstNodeExpr* thsp)
+        : ASTGEN_SUPER_DistNormal(fl, lhsp, rhsp, thsp) {}
+    ASTGEN_MEMBERS_AstDistNormal;
+    string emitVerilog() override { return "%f$dist_normal(%l, %r, %t)"; }
+    string emitC() override { return "VL_DIST_NORMAL(%li, %ri, %ti)"; }
+};
+class AstDistUniform final : public AstNodeDistTriop {
+public:
+    AstDistUniform(FileLine* fl, AstNodeExpr* lhsp, AstNodeExpr* rhsp, AstNodeExpr* thsp)
+        : ASTGEN_SUPER_DistUniform(fl, lhsp, rhsp, thsp) {}
+    ASTGEN_MEMBERS_AstDistUniform;
+    string emitVerilog() override { return "%f$dist_uniform(%l, %r, %t)"; }
+    string emitC() override { return "VL_DIST_UNIFORM(%li, %ri, %ti)"; }
+};
+
 // === AstNodeUniop ===
 class AstAtoN final : public AstNodeUniop {
     // string.atoi(), atobin(), atohex(), atooct(), atoireal()
diff --git a/src/V3EmitCInlines.cpp b/src/V3EmitCInlines.cpp
index 24556fd5f..58cae781a 100644
--- a/src/V3EmitCInlines.cpp
+++ b/src/V3EmitCInlines.cpp
@@ -43,6 +43,14 @@ class EmitCInlines final : EmitCBaseVisitor {
         if (v3Global.opt.trace()) v3Global.needTraceDumper(true);
         iterateChildren(nodep);
     }
+    void visit(AstNodeDistBiop* nodep) override {
+        v3Global.setUsesProbDist();
+        iterateChildren(nodep);
+    }
+    void visit(AstNodeDistTriop* nodep) override {
+        v3Global.setUsesProbDist();
+        iterateChildren(nodep);
+    }
 
     //---------------------------------------
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp
index f6845df70..ca3a3d3ef 100644
--- a/src/V3EmitCMake.cpp
+++ b/src/V3EmitCMake.cpp
@@ -159,6 +159,9 @@ class CMakeEmitter final {
             global.emplace_back("${VERILATOR_ROOT}/include/" + v3Global.opt.traceSourceBase()
                                 + "_c.cpp");
         }
+        if (v3Global.usesProbDist()) {
+            global.emplace_back("${VERILATOR_ROOT}/include/verilated_probdist.cpp");
+        }
         if (v3Global.usesTiming()) {
             global.emplace_back("${VERILATOR_ROOT}/include/verilated_timing.cpp");
         }
diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp
index 26083c2f0..2964f0bc3 100644
--- a/src/V3EmitMk.cpp
+++ b/src/V3EmitMk.cpp
@@ -106,6 +106,7 @@ public:
                     if (v3Global.opt.trace()) {
                         putMakeClassEntry(of, v3Global.opt.traceSourceBase() + "_c.cpp");
                     }
+                    if (v3Global.usesProbDist()) putMakeClassEntry(of, "verilated_probdist.cpp");
                     if (v3Global.usesTiming()) putMakeClassEntry(of, "verilated_timing.cpp");
                     if (v3Global.opt.threads()) putMakeClassEntry(of, "verilated_threads.cpp");
                     if (v3Global.opt.usesProfiler()) {
diff --git a/src/V3Global.h b/src/V3Global.h
index bcbdc172f..7807d6f2b 100644
--- a/src/V3Global.h
+++ b/src/V3Global.h
@@ -107,6 +107,7 @@ class V3Global final {
     bool m_dpi = false;  // Need __Dpi include files
     bool m_hasEvents = false;  // Design uses SystemVerilog named events
     bool m_hasClasses = false;  // Design uses SystemVerilog classes
+    bool m_usesProbDist = false;  // Uses $dist_*
     bool m_usesStdPackage = false;  // Design uses the std package
     bool m_usesTiming = false;  // Design uses timing constructs
     bool m_hasForceableSignals = false;  // Need to apply V3Force pass
@@ -153,6 +154,8 @@ public:
     void setHasEvents() { m_hasEvents = true; }
     bool hasClasses() const { return m_hasClasses; }
     void setHasClasses() { m_hasClasses = true; }
+    bool usesProbDist() const { return m_usesProbDist; }
+    void setUsesProbDist() { m_usesProbDist = true; }
     bool usesStdPackage() const { return m_usesStdPackage; }
     void setUsesStdPackage() { m_usesStdPackage = true; }
     bool usesTiming() const { return m_usesTiming; }
diff --git a/src/V3LinkLValue.cpp b/src/V3LinkLValue.cpp
index 903f0a90c..692339ed3 100644
--- a/src/V3LinkLValue.cpp
+++ b/src/V3LinkLValue.cpp
@@ -250,6 +250,21 @@ private:
             iterateAndNextNull(nodep->fmtp());
         }
     }
+    void visit(AstNodeDistBiop* nodep) override {
+        VL_RESTORER(m_setRefLvalue);
+        m_setRefLvalue = VAccess::WRITE;
+        iterateAndNextNull(nodep->lhsp());
+        m_setRefLvalue = VAccess::NOCHANGE;
+        iterateAndNextNull(nodep->rhsp());
+    }
+    void visit(AstNodeDistTriop* nodep) override {
+        VL_RESTORER(m_setRefLvalue);
+        m_setRefLvalue = VAccess::WRITE;
+        iterateAndNextNull(nodep->lhsp());
+        m_setRefLvalue = VAccess::NOCHANGE;
+        iterateAndNextNull(nodep->rhsp());
+        iterateAndNextNull(nodep->thsp());
+    }
     void prepost_visit(AstNodeTriop* nodep) {
         VL_RESTORER(m_setRefLvalue);
         {
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 1c9ab3a85..a766baca8 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -773,6 +773,21 @@ private:
             }
         }
     }
+    void visit(AstNodeDistBiop* nodep) override {
+        if (m_vup->prelim()) {  // First stage evaluation
+            iterateCheckSigned32(nodep, "seed", nodep->lhsp(), BOTH);
+            iterateCheckSigned32(nodep, "RHS", nodep->rhsp(), BOTH);
+            nodep->dtypeSetSigned32();
+        }
+    }
+    void visit(AstNodeDistTriop* nodep) override {
+        if (m_vup->prelim()) {  // First stage evaluation
+            iterateCheckSigned32(nodep, "seed", nodep->lhsp(), BOTH);
+            iterateCheckSigned32(nodep, "RHS", nodep->rhsp(), BOTH);
+            iterateCheckSigned32(nodep, "THS", nodep->thsp(), BOTH);
+            nodep->dtypeSetSigned32();
+        }
+    }
     void visit(AstNodeStream* nodep) override {
         if (m_vup->prelim()) {
             iterateCheckSizedSelf(nodep, "LHS", nodep->lhsp(), SELF, BOTH);
diff --git a/src/verilog.l b/src/verilog.l
index 96e1d5718..b4b42635c 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -183,6 +183,13 @@ vnum    {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "$displayb"           { FL; return yD_DISPLAYB; }
   "$displayh"           { FL; return yD_DISPLAYH; }
   "$displayo"           { FL; return yD_DISPLAYO; }
+  "$dist_chi_square"    { FL; return yD_DIST_CHI_SQUARE; }
+  "$dist_erlang"        { FL; return yD_DIST_ERLANG; }
+  "$dist_exponential"   { FL; return yD_DIST_EXPONENTIAL; }
+  "$dist_normal"        { FL; return yD_DIST_NORMAL; }
+  "$dist_poisson"       { FL; return yD_DIST_POISSON; }
+  "$dist_t"             { FL; return yD_DIST_T; }
+  "$dist_uniform"       { FL; return yD_DIST_UNIFORM; }
   "$dumpall"            { FL; return yD_DUMPALL; }
   "$dumpfile"           { FL; return yD_DUMPFILE; }
   "$dumpflush"          { FL; return yD_DUMPFLUSH; }
diff --git a/src/verilog.y b/src/verilog.y
index 5b4c9cb96..8621e4e6b 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -776,6 +776,13 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
 %token<fl>              yD_DISPLAYB     "$displayb"
 %token<fl>              yD_DISPLAYH     "$displayh"
 %token<fl>              yD_DISPLAYO     "$displayo"
+%token<fl>              yD_DIST_CHI_SQUARE "$dist_chi_square"
+%token<fl>              yD_DIST_ERLANG  "$dist_erlang"
+%token<fl>              yD_DIST_EXPONENTIAL "$dist_exponential"
+%token<fl>              yD_DIST_NORMAL  "$dist_normal"
+%token<fl>              yD_DIST_POISSON "$dist_poisson"
+%token<fl>              yD_DIST_T       "$dist_t"
+%token<fl>              yD_DIST_UNIFORM "$dist_uniform"
 %token<fl>              yD_DUMPALL      "$dumpall"
 %token<fl>              yD_DUMPFILE     "$dumpfile"
 %token<fl>              yD_DUMPFLUSH    "$dumpflush"
@@ -4038,6 +4045,13 @@ system_f_call_or_t<nodeExprp>:      // IEEE: part of system_tf_call (can be task
                           BBUNSUP($11, "Unsupported: $countbits with more than 3 control fields"); }
         |       yD_COUNTONES '(' expr ')'               { $$ = new AstCountOnes{$1, $3}; }
         |       yD_DIMENSIONS '(' exprOrDataType ')'    { $$ = new AstAttrOf{$1, VAttrType::DIM_DIMENSIONS, $3}; }
+        |       yD_DIST_CHI_SQUARE '(' expr ',' expr ')'        { $$ = new AstDistChiSquare{$1, $3, $5}; }
+        |       yD_DIST_ERLANG '(' expr ',' expr ',' expr ')'   { $$ = new AstDistErlang{$1, $3, $5, $7}; }
+        |       yD_DIST_EXPONENTIAL '(' expr ',' expr ')'       { $$ = new AstDistExponential{$1, $3, $5}; }
+        |       yD_DIST_NORMAL '(' expr ',' expr ',' expr ')'   { $$ = new AstDistNormal{$1, $3, $5, $7}; }
+        |       yD_DIST_POISSON '(' expr ',' expr ')'   { $$ = new AstDistPoisson{$1, $3, $5}; }
+        |       yD_DIST_T '(' expr ',' expr ')'         { $$ = new AstDistT{$1, $3, $5}; }
+        |       yD_DIST_UNIFORM '(' expr ',' expr ',' expr ')'  { $$ = new AstDistUniform{$1, $3, $5, $7}; }
         |       yD_EXP '(' expr ')'                     { $$ = new AstExpD{$1, $3}; }
         |       yD_FELL '(' expr ')'                    { $$ = new AstFell{$1, $3}; }
         |       yD_FELL '(' expr ',' expr ')'           { $$ = $3; BBUNSUP($1, "Unsupported: $fell and clock arguments"); }
diff --git a/test_regress/t/t_probdist.pl b/test_regress/t/t_probdist.pl
index 43720dd0f..1aa73f80a 100755
--- a/test_regress/t/t_probdist.pl
+++ b/test_regress/t/t_probdist.pl
@@ -11,13 +11,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    fails => $Self->{vlt_all},
-    expect_filename => $Self->{golden_filename},
     );
 
 execute(
     check_finished => 1,
-    ) if !$Self->{vlt_all};
+    );
 
 ok(1);
 1;
diff --git a/test_regress/t/t_probdist.v b/test_regress/t/t_probdist.v
index ae5a62a6f..af8ef0ecf 100644
--- a/test_regress/t/t_probdist.v
+++ b/test_regress/t/t_probdist.v
@@ -13,7 +13,7 @@ module t(/*AUTOARG*/);
    integer sum;
 
    initial begin
-      // Illegal values
+      //=======
       seed = 1234;
       r = $dist_chi_square(seed, 5);
       `checkd(seed, 923940542);
@@ -21,7 +21,14 @@ module t(/*AUTOARG*/);
       sum = 1;
       repeat(20) sum += $dist_chi_square(seed, 5);
       `checkd(sum, 130);
+      sum = 1;
+      repeat(20) sum += $dist_chi_square(seed, -5);
+      `checkd(sum, 1);
+      sum = 1;
+      repeat(20) sum += $dist_chi_square(seed, 2);
+      `checkd(sum, 30);
 
+      //=======
       seed = 1234;
       r = $dist_erlang(seed, 5, 10);
       `checkd(seed, 1025211431);
@@ -29,7 +36,11 @@ module t(/*AUTOARG*/);
       sum = 1;
       repeat(20) sum += $dist_erlang(seed, 5, 10);
       `checkd(sum, 173);
+      sum = 1;
+      repeat(20) sum += $dist_erlang(seed, 5, -10);
+      `checkd(sum, -241);
 
+      //=======
       seed = 1234;
       r = $dist_exponential(seed, 5);
       `checkd(seed, 85231147);
@@ -38,6 +49,7 @@ module t(/*AUTOARG*/);
       repeat(20) sum += $dist_exponential(seed, 5);
       `checkd(sum, 104);
 
+      //=======
       seed = 1234;
       r = $dist_normal(seed, 5, 10);
       `checkd(seed, -1570070672);
@@ -46,6 +58,7 @@ module t(/*AUTOARG*/);
       repeat(20) sum += $dist_normal(seed, 5, 10);
       `checkd(sum, 114);
 
+      //=======
       seed = 1234;
       r = $dist_poisson(seed, 5);
       `checkd(seed, 418012337);
@@ -54,6 +67,7 @@ module t(/*AUTOARG*/);
       repeat(20) sum += $dist_poisson(seed, 5);
       `checkd(sum, 111);
 
+      //=======
       seed = 1234;
       r = $dist_t(seed, 5);
       `checkd(seed, -797481412);
@@ -62,6 +76,7 @@ module t(/*AUTOARG*/);
       repeat(20) sum += $dist_t(seed, 5);
       `checkd(sum, -2);
 
+      //=======
       seed = 1234;
       r = $dist_uniform(seed, 5, 10);
       `checkd(seed, 85231147);
@@ -70,6 +85,24 @@ module t(/*AUTOARG*/);
       repeat(20) sum += $dist_uniform(seed, 5, 10);
       `checkd(sum, 147);
 
+      seed = 1234;
+      r = $dist_uniform(seed, 10, 5);
+      `checkd(r, 10);
+      sum = 1;
+      repeat(20) sum += $dist_uniform(seed, -2147483648, -20);
+      `checkd(sum, 1768955681);
+      sum = 1;
+      repeat(20) sum += $dist_uniform(seed, 20, 2147483647);
+      `checkd(sum, 1534326415);
+      sum = 1;
+      repeat(20) sum += $dist_uniform(seed, -2147483648, 2147483647);
+      `checkd(sum, 1394525852);
+      seed = 0;
+      sum = 1;
+      repeat(20) sum += $dist_uniform(seed, -10, 100);
+      `checkd(seed, 1003647461);
+      `checkd(sum, 896);
+
       $write("*-* All Finished *-*\n");
       $finish;
    end
diff --git a/test_regress/t/t_probdist_bad.out b/test_regress/t/t_probdist_bad.out
deleted file mode 100644
index 9d7008ac9..000000000
--- a/test_regress/t/t_probdist_bad.out
+++ /dev/null
@@ -1,19 +0,0 @@
-%Error: t/t_probdist_bad.v:16:11: Unsupported or unknown PLI call: '$dist_chi_square'
-   16 |       r = $dist_chi_square(seed, 0);
-      |           ^~~~~~~~~~~~~~~~
-%Error: t/t_probdist_bad.v:18:11: Unsupported or unknown PLI call: '$dist_erlang'
-   18 |       r = $dist_erlang(seed, 0, 0);
-      |           ^~~~~~~~~~~~
-%Error: t/t_probdist_bad.v:20:11: Unsupported or unknown PLI call: '$dist_exponential'
-   20 |       r = $dist_exponential(seed, 0);
-      |           ^~~~~~~~~~~~~~~~~
-%Error: t/t_probdist_bad.v:23:11: Unsupported or unknown PLI call: '$dist_poisson'
-   23 |       r = $dist_poisson(seed, 0);
-      |           ^~~~~~~~~~~~~
-%Error: t/t_probdist_bad.v:25:11: Unsupported or unknown PLI call: '$dist_t'
-   25 |       r = $dist_t(seed, 0);
-      |           ^~~~~~~
-%Error: t/t_probdist_bad.v:27:11: Unsupported or unknown PLI call: '$dist_uniform'
-   27 |       r = $dist_uniform(seed, 10, 0);
-      |           ^~~~~~~~~~~~~
-%Error: Exiting due to
diff --git a/test_regress/t/t_probdist_bad.pl b/test_regress/t/t_probdist_bad.pl
index 43720dd0f..1aa73f80a 100755
--- a/test_regress/t/t_probdist_bad.pl
+++ b/test_regress/t/t_probdist_bad.pl
@@ -11,13 +11,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    fails => $Self->{vlt_all},
-    expect_filename => $Self->{golden_filename},
     );
 
 execute(
     check_finished => 1,
-    ) if !$Self->{vlt_all};
+    );
 
 ok(1);
 1;
diff --git a/test_regress/t/t_probdist_cmake.pl b/test_regress/t/t_probdist_cmake.pl
new file mode 100755
index 000000000..f9854219c
--- /dev/null
+++ b/test_regress/t/t_probdist_cmake.pl
@@ -0,0 +1,25 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+top_filename("t/t_probdist.v");
+
+compile(
+    verilator_make_gmake => 0,
+    verilator_make_cmake => 1,
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_verilated_all.v b/test_regress/t/t_verilated_all.v
index 2030b8ba8..14b2fab87 100644
--- a/test_regress/t/t_verilated_all.v
+++ b/test_regress/t/t_verilated_all.v
@@ -12,12 +12,15 @@ module t (/*AUTOARG*/
    input clk;
 
    integer cyc;
+   integer seed = 123;
 
    always @ (posedge clk) begin
       cyc <= cyc + 1;
-      if (cyc!=0) begin
-         if (cyc==10) begin
-            #5 $write("*-* All Finished *-*\n");
+      if (cyc != 0) begin
+         if (cyc == 10) begin
+            #5;
+            $display("dist: %f ", $dist_poisson(seed, 12));  // Get verilated_probdist.cpp
+            $write("*-* All Finished *-*\n");
             $finish;
          end
       end

From 87bb32fde157d7816991d487c2783be91114c148 Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Tue, 6 Dec 2022 13:14:29 +0100
Subject: [PATCH 128/156] Fix forks without any delayed statements (#3792)
 (#3801)

---
 src/V3Timing.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp
index 2ff9c4a85..195714a2b 100644
--- a/src/V3Timing.cpp
+++ b/src/V3Timing.cpp
@@ -746,6 +746,7 @@ private:
     }
     void visit(AstFork* nodep) override {
         if (nodep->user1SetOnce()) return;
+        v3Global.setUsesTiming();
         // Create a unique name for this fork
         nodep->name(m_forkNames.get(nodep));
         unsigned idx = 0;  // Index for naming begins

From 4b6e15d0eb3ab7f4c1860dc7ba80016b9c4aafa9 Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Tue, 6 Dec 2022 13:16:07 +0100
Subject: [PATCH 129/156] Fix non-blocking assignments in forks (#3781) (#3800)

---
 src/V3Delayed.cpp                  | 20 +++++++++++++++-----
 test_regress/t/t_timing_bug3781.pl | 28 ++++++++++++++++++++++++++++
 test_regress/t/t_timing_bug3781.v  | 30 ++++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+), 5 deletions(-)
 create mode 100755 test_regress/t/t_timing_bug3781.pl
 create mode 100644 test_regress/t/t_timing_bug3781.v

diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp
index ee78c41c5..62835fe89 100644
--- a/src/V3Delayed.cpp
+++ b/src/V3Delayed.cpp
@@ -101,6 +101,7 @@ private:
     bool m_inDly = false;  // True in delayed assignments
     bool m_inLoop = false;  // True in for loops
     bool m_inInitial = false;  // True in static initializers and initial blocks
+    bool m_inSuspendableOrFork = false;  // True in suspendable processes and forks
     bool m_ignoreBlkAndNBlk = false;  // Suppress delayed assignment BLKANDNBLK
     using VarMap = std::map<const std::pair<AstNodeModule*, std::string>, AstVar*>;
     VarMap m_modVarMap;  // Table of new var names created under module
@@ -311,7 +312,7 @@ private:
         AstVarScope* setvscp;
         AstAssignPre* setinitp = nullptr;
 
-        if (!m_procp->isSuspendable() && nodep->user3p()) {
+        if (!m_inSuspendableOrFork && nodep->user3p()) {
             // Simplistic optimization.  If the previous statement in same scope was also a =>,
             // then we told this nodep->user3 we can use its Vdlyvset rather than making a new one.
             // This is good for code like:
@@ -322,7 +323,7 @@ private:
             const string setvarname
                 = (string("__Vdlyvset__") + oldvarp->shortName() + "__v" + cvtToStr(modVecNum));
             setvscp = createVarSc(varrefp->varScopep(), setvarname, 1, nullptr);
-            if (!m_procp->isSuspendable()) {
+            if (!m_inSuspendableOrFork) {
                 // Suspendables reset __Vdlyvset__ in the AstAlwaysPost
                 setinitp = new AstAssignPre{
                     nodep->fileline(), new AstVarRef{nodep->fileline(), setvscp, VAccess::WRITE},
@@ -342,6 +343,8 @@ private:
         // This ensures that multiple assignments to the same memory will result
         // in correctly ordered code - the last assignment must be last.
         // It also has the nice side effect of assisting cache locality.
+        varrefp->user2Inc();  // Do not generate a warning for the blocking assignment
+                              // that uses this varref
         AstNodeExpr* selectsp = varrefp;
         for (int dimension = int(dimreadps.size()) - 1; dimension >= 0; --dimension) {
             selectsp = new AstArraySel{nodep->fileline(), selectsp, dimreadps[dimension]};
@@ -354,7 +357,7 @@ private:
         UINFO(9, "   For " << setvscp << endl);
         UINFO(9, "     & " << varrefp << endl);
         AstAlwaysPost* finalp = nullptr;
-        if (m_procp->isSuspendable()) {
+        if (m_inSuspendableOrFork) {
             finalp = VN_AS(varrefp->varScopep()->user3p(), AlwaysPost);
             if (!finalp) {
                 FileLine* const flp = nodep->fileline();
@@ -400,7 +403,7 @@ private:
             finalp->user4p(postLogicp);  // and the associated IF, as we may be able to reuse it
         }
         postLogicp->addThensp(new AstAssign{nodep->fileline(), selectsp, valreadp});
-        if (m_procp->isSuspendable()) {
+        if (m_inSuspendableOrFork) {
             FileLine* const flp = nodep->fileline();
             postLogicp->addThensp(new AstAssign{flp, new AstVarRef{flp, setvscp, VAccess::WRITE},
                                                 new AstConst{flp, 0}});
@@ -438,6 +441,8 @@ private:
         }
     }
     void visit(AstNodeProcedure* nodep) override {
+        VL_RESTORER(m_inSuspendableOrFork);
+        m_inSuspendableOrFork = nodep->isSuspendable();
         m_procp = nodep;
         m_timingDomains.clear();
         iterateChildren(nodep);
@@ -464,6 +469,11 @@ private:
             actp->sensesStorep(clockedDomain);
         }
     }
+    void visit(AstFork* nodep) override {
+        VL_RESTORER(m_inSuspendableOrFork);
+        m_inSuspendableOrFork = true;
+        iterateChildren(nodep);
+    }
     void visit(AstCAwait* nodep) override { m_timingDomains.insert(nodep->sensesp()); }
     void visit(AstFireEvent* nodep) override {
         UASSERT_OBJ(v3Global.hasEvents(), nodep, "Inconsistent");
@@ -518,7 +528,7 @@ private:
         const bool isArray = VN_IS(nodep->lhsp(), ArraySel)
                              || (VN_IS(nodep->lhsp(), Sel)
                                  && VN_IS(VN_AS(nodep->lhsp(), Sel)->fromp(), ArraySel));
-        if (m_procp->isSuspendable() || isArray) {
+        if (m_inSuspendableOrFork || isArray) {
             AstNodeExpr* const lhsp = nodep->lhsp();
             AstNodeExpr* const newlhsp = createDlyOnSet(nodep, lhsp);
             if (m_inLoop && isArray) {
diff --git a/test_regress/t/t_timing_bug3781.pl b/test_regress/t/t_timing_bug3781.pl
new file mode 100755
index 000000000..f86c4b944
--- /dev/null
+++ b/test_regress/t/t_timing_bug3781.pl
@@ -0,0 +1,28 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+if (!$Self->have_coroutines) {
+    skip("No coroutine support");
+}
+else {
+    compile(
+        verilator_flags2 => ["--exe --main --timing"],
+        make_main => 0,
+        );
+
+    execute(
+        check_finished => 1,
+        );
+}
+
+ok(1);
+1;
diff --git a/test_regress/t/t_timing_bug3781.v b/test_regress/t/t_timing_bug3781.v
new file mode 100644
index 000000000..aca002652
--- /dev/null
+++ b/test_regress/t/t_timing_bug3781.v
@@ -0,0 +1,30 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+    logic clk;
+    logic [7:0] data;
+    logic [3:0] ptr;
+    logic [7:0] mem[16];
+
+    initial begin
+        clk = 1'b0;
+        fork forever #5 clk = ~clk; join_none
+        ptr = '0;
+        #10 data = 1;
+        #10 if (mem[ptr] != data) $stop;
+        #10 data = 2;
+        #10 if (mem[ptr] != data) $stop;
+        #10 data = 3;
+        #10 if (mem[ptr] != data) $stop;
+        #10 $write("*-* All Finished *-*\n");
+        $finish;
+    end
+
+    always @(posedge clk) begin
+        mem[ptr] <= #1 data;
+    end
+endmodule

From 2dc0053ea48e720450e8b5fc8327c7587856d1cd Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 8 Dec 2022 07:23:53 -0500
Subject: [PATCH 130/156] Tests: rename

---
 test_regress/t/{t_timing_bug3781.pl => t_timing_dlyassign.pl} | 0
 test_regress/t/{t_timing_bug3781.v => t_timing_dlyassign.v}   | 1 +
 2 files changed, 1 insertion(+)
 rename test_regress/t/{t_timing_bug3781.pl => t_timing_dlyassign.pl} (100%)
 rename test_regress/t/{t_timing_bug3781.v => t_timing_dlyassign.v} (98%)

diff --git a/test_regress/t/t_timing_bug3781.pl b/test_regress/t/t_timing_dlyassign.pl
similarity index 100%
rename from test_regress/t/t_timing_bug3781.pl
rename to test_regress/t/t_timing_dlyassign.pl
diff --git a/test_regress/t/t_timing_bug3781.v b/test_regress/t/t_timing_dlyassign.v
similarity index 98%
rename from test_regress/t/t_timing_bug3781.v
rename to test_regress/t/t_timing_dlyassign.v
index aca002652..42cefffce 100644
--- a/test_regress/t/t_timing_bug3781.v
+++ b/test_regress/t/t_timing_dlyassign.v
@@ -4,6 +4,7 @@
 // any use, without warranty, 2022 by Antmicro Ltd.
 // SPDX-License-Identifier: CC0-1.0
 
+// bug3781
 module t;
     logic clk;
     logic [7:0] data;

From bcf58defe0e83be6fdf5a0e2a554648a6332e739 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 8 Dec 2022 07:30:23 -0500
Subject: [PATCH 131/156] Update include/gtkwave from upstream

---
 include/gtkwave/fstapi.c | 68 +++++++++++++++++++++++++++++-----------
 1 file changed, 49 insertions(+), 19 deletions(-)

diff --git a/include/gtkwave/fstapi.c b/include/gtkwave/fstapi.c
index 5e9529d44..11cb0c501 100644
--- a/include/gtkwave/fstapi.c
+++ b/include/gtkwave/fstapi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2009-2018 Tony Bybell.
+ * Copyright (c) 2009-2023 Tony Bybell.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -4130,26 +4130,35 @@ if(xc->do_rewind)
 if(!(isfeof=feof(xc->fh)))
         {
         int tag = fgetc(xc->fh);
+	int cl;
         switch(tag)
                 {
                 case FST_ST_VCD_SCOPE:
                         xc->hier.htyp = FST_HT_SCOPE;
                         xc->hier.u.scope.typ = fgetc(xc->fh);
                         xc->hier.u.scope.name = pnt = xc->str_scope_nam;
+			cl = 0;
                         while((ch = fgetc(xc->fh)))
                                 {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                 }; /* scopename */
-                        *pnt = 0;
-                        xc->hier.u.scope.name_length = pnt - xc->hier.u.scope.name;
+                        pnt[cl] = 0;
+                        xc->hier.u.scope.name_length = cl;
 
                         xc->hier.u.scope.component = pnt = xc->str_scope_comp;
+			cl = 0;
                         while((ch = fgetc(xc->fh)))
                                 {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                 }; /* scopecomp */
-                        *pnt = 0;
-                        xc->hier.u.scope.component_length = pnt - xc->hier.u.scope.component;
+                        pnt[cl] = 0;
+                        xc->hier.u.scope.component_length = cl;
                         break;
 
                 case FST_ST_VCD_UPSCOPE:
@@ -4161,12 +4170,16 @@ if(!(isfeof=feof(xc->fh)))
                         xc->hier.u.attr.typ = fgetc(xc->fh);
                         xc->hier.u.attr.subtype = fgetc(xc->fh);
                         xc->hier.u.attr.name = pnt = xc->str_scope_nam;
+			cl = 0;
                         while((ch = fgetc(xc->fh)))
                                 {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                 }; /* scopename */
-                        *pnt = 0;
-                        xc->hier.u.attr.name_length = pnt - xc->hier.u.scope.name;
+			pnt[cl] = 0;
+                        xc->hier.u.attr.name_length = cl;
 
                         xc->hier.u.attr.arg = fstReaderVarint64(xc->fh);
 
@@ -4221,12 +4234,16 @@ if(!(isfeof=feof(xc->fh)))
                         xc->hier.u.var.typ = tag;
                         xc->hier.u.var.direction = fgetc(xc->fh);
                         xc->hier.u.var.name = pnt = xc->str_scope_nam;
+			cl = 0;
                         while((ch = fgetc(xc->fh)))
                                 {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                 }; /* varname */
-                        *pnt = 0;
-                        xc->hier.u.var.name_length = pnt - xc->hier.u.var.name;
+                        pnt[cl] = 0;
+                        xc->hier.u.var.name_length = cl;
                         xc->hier.u.var.length = fstReaderVarint32(xc->fh);
                         if(tag == FST_VT_VCD_PORT)
                                 {
@@ -4273,6 +4290,7 @@ unsigned int num_signal_dyn = 65536;
 int attrtype, subtype;
 uint64_t attrarg;
 fstHandle maxhandle_scanbuild;
+int cl;
 
 if(!xc) return(0);
 
@@ -4355,11 +4373,15 @@ while(!feof(xc->fh))
                         scopetype = fgetc(xc->fh);
                         if((scopetype < FST_ST_MIN) || (scopetype > FST_ST_MAX)) scopetype = FST_ST_VCD_MODULE;
                         pnt = str;
+			cl = 0;
                         while((ch = fgetc(xc->fh)))
                                 {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_ATTR_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                 }; /* scopename */
-                        *pnt = 0;
+                        pnt[cl] = 0;
                         while(fgetc(xc->fh)) { }; /* scopecomp */
 
                         if(fv) fprintf(fv, "$scope %s %s $end\n", modtypes[scopetype], str);
@@ -4373,11 +4395,15 @@ while(!feof(xc->fh))
                         attrtype = fgetc(xc->fh);
                         subtype = fgetc(xc->fh);
                         pnt = str;
+			cl = 0;
                         while((ch = fgetc(xc->fh)))
                                 {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_ATTR_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                 }; /* attrname */
-                        *pnt = 0;
+                        pnt[cl] = 0;
 
                         if(!str[0]) { strcpy(str, "\"\""); }
 
@@ -4458,11 +4484,15 @@ while(!feof(xc->fh))
                         vartype = tag;
                         /* vardir = */ fgetc(xc->fh); /* unused in VCD reader, but need to advance read pointer */
                         pnt = str;
+			cl = 0;
                         while((ch = fgetc(xc->fh)))
                                 {
-                                *(pnt++) = ch;
+				if(cl <= FST_ID_NAM_ATTR_SIZ)
+					{
+					pnt[cl++] = ch;
+					}
                                 }; /* varname */
-                        *pnt = 0;
+                        pnt[cl] = 0;
                         len = fstReaderVarint32(xc->fh);
                         alias = fstReaderVarint32(xc->fh);
 

From 5aa935d170fd39571553a4fcc81821b4fdfa53e3 Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Fri, 9 Dec 2022 13:12:26 +0100
Subject: [PATCH 132/156] Internals: Add annotations for check attributes
 (#3803)

---
 include/verilatedos.h | 30 ++++++++++++++++++++++++++----
 1 file changed, 26 insertions(+), 4 deletions(-)

diff --git a/include/verilatedos.h b/include/verilatedos.h
index db9b18932..2e6e5cb49 100644
--- a/include/verilatedos.h
+++ b/include/verilatedos.h
@@ -148,7 +148,11 @@
 #endif
 
 // Comment tag that Function is pure (and thus also VL_MT_SAFE)
-#define VL_PURE
+#if defined(__clang__)
+# define VL_PURE __attribute__((annotate("PURE")))
+#else
+# define VL_PURE
+#endif
 // Comment tag that function is threadsafe
 #if defined(__clang__)
 # define VL_MT_SAFE __attribute__((annotate("MT_SAFE")))
@@ -157,9 +161,17 @@
 #endif
 // Comment tag that function is threadsafe, only
 // during normal operation (post-init)
-#define VL_MT_SAFE_POSTINIT
+#if defined(__clang__)
+# define VL_MT_SAFE_POSTINIT __attribute__((annotate("MT_SAFE_POSTINIT")))
+#else
+# define VL_MT_SAFE_POSTINIT
+#endif
 // Attribute that function is clang threadsafe and uses given mutex
-#define VL_MT_SAFE_EXCLUDES(mutex) VL_EXCLUDES(mutex)
+#if defined(__clang__)
+# define VL_MT_SAFE_EXCLUDES(mutex) __attribute__((annotate("MT_SAFE_EXCLUDES"))) VL_EXCLUDES(mutex)
+#else
+# define VL_MT_SAFE_EXCLUDES(mutex) VL_EXCLUDES(mutex)
+#endif
 // Comment tag that function is not threadsafe
 #if defined(__clang__)
 # define VL_MT_UNSAFE __attribute__((annotate("MT_UNSAFE")))
@@ -168,7 +180,17 @@
 #endif
 // Comment tag that function is not threadsafe
 // protected to make sure single-caller
-#define VL_MT_UNSAFE_ONE
+#if defined(__clang__)
+# define VL_MT_UNSAFE_ONE __attribute__((annotate("MT_UNSAFE_ONE")))
+#else
+# define VL_MT_UNSAFE_ONE
+#endif
+// Comment tag that function is entry point of parallelization
+#if defined(__clang__)
+# define VL_MT_START __attribute__((annotate("MT_START")))
+#else
+# define VL_MT_START
+#endif
 
 #ifndef VL_NO_LEGACY
 # define VL_ULL(c) (c##ULL)  // Add appropriate suffix to 64-bit constant (deprecated)

From fc2654f1f678c1768616c2b00abdcbb271c52911 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 9 Dec 2022 20:17:19 -0500
Subject: [PATCH 133/156] msg

---
 docs/guide/exe_verilator.rst | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst
index 21be8775f..d1efb3f25 100644
--- a/docs/guide/exe_verilator.rst
+++ b/docs/guide/exe_verilator.rst
@@ -29,10 +29,10 @@ Summary:
 .. option:: <file.a/.o/.so>
 
    Specifies optional object or library files to be linked in with the
-   Verilog code, as a shorthand for :vlopt:`-LDFLAGS \<file\>
-   <-LDFLAGS>`. The file path should either be absolute, or relative to
-   where the make will be executed from, or add to your makefile's VPATH
-   the appropriate directory to find the file.
+   Verilog code, as a shorthand for :vlopt:`-LDFLAGS \<file\>`. The file
+   path should either be absolute, or relative to where the make will be
+   executed from, or add to your makefile's VPATH the appropriate directory
+   to find the file.
 
    If any files are specified in this way, Verilator will include a make
    rule that uses these files when linking the module's executable.  This

From 0824ef377f9cdfae13b2c702d1bc2b83f048c2d9 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 9 Dec 2022 20:32:09 -0500
Subject: [PATCH 134/156] wip

---
 test_regress/t/t_dist_docs_style.pl | 65 +++++++++++++++++++++++++++++
 1 file changed, 65 insertions(+)
 create mode 100755 test_regress/t/t_dist_docs_style.pl

diff --git a/test_regress/t/t_dist_docs_style.pl b/test_regress/t/t_dist_docs_style.pl
new file mode 100755
index 000000000..0cda99082
--- /dev/null
+++ b/test_regress/t/t_dist_docs_style.pl
@@ -0,0 +1,65 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Primitive C++ style checker
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(dist => 1);
+
+my $root = "..";
+
+### Must trim output before and after our file list
+my %files = %{get_source_files($root)};
+
+foreach my $file (sort keys %files) {
+    my $filename = "$root/$file";
+    next if !-f $filename;  # git file might be deleted but not yet staged
+    next unless $file =~ /\.rst$/;
+
+    my $contents = file_contents($filename);
+
+    checkPattern($filename, $contents,
+                 qr/.*(?<!ref):\`[^`]+\n/,
+                 "tag:`...` should not be split between lines");
+}
+
+ok(1);
+1;
+
+sub get_source_files {
+    my $root = shift;
+    my $git_files = `cd $root && git ls-files`;
+    print "MF $git_files\n" if $Self->{verbose};
+    my %files;
+    foreach my $file (split /\s+/, $git_files) {
+        next if $file eq '';
+        $files{$file} |= 1;
+    }
+    return \%files;
+}
+
+sub checkPattern {
+    my $filename = shift;
+    my $contents = shift;
+    my $pattern = shift;
+    my $message = shift;
+
+    my $offset = 0;
+    my $buffer = $contents;
+    while ($buffer =~ s/.*?^($pattern)//sm) {
+        my $lineno = offset_to_lineno($contents, $offset + $-[-1]);
+        $offset += $+[1];
+        error("$filename:$lineno: $message");
+    }
+}
+
+sub offset_to_lineno {
+    my $contents = shift;
+    my $offset = shift;
+    my $count = (substr $contents, 0, $offset) =~ tr/\n//;
+    return $count + 1;
+}

From d61ad04f3289760c8f9ad8ecdf6459e83452ae02 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 9 Dec 2022 21:01:33 -0500
Subject: [PATCH 135/156] docs: Fix and test for AsciiDoc breaks (#3728)

---
 docs/guide/connecting.rst           |  4 +-
 docs/guide/example_cc.rst           |  6 +-
 docs/guide/example_dist.rst         |  2 +-
 docs/guide/exe_sim.rst              |  8 +--
 docs/guide/exe_verilator.rst        | 98 +++++++++++++++--------------
 docs/guide/extensions.rst           | 10 +--
 docs/guide/languages.rst            | 11 ++--
 docs/guide/simulating.rst           | 16 ++---
 docs/guide/verilating.rst           | 10 +--
 docs/guide/warnings.rst             | 35 ++++++-----
 test_regress/t/t_dist_docs_style.pl |  2 +-
 11 files changed, 106 insertions(+), 96 deletions(-)

diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst
index 16f569007..177af7520 100644
--- a/docs/guide/connecting.rst
+++ b/docs/guide/connecting.rst
@@ -51,8 +51,8 @@ also the instance of the top level instance in the design hierarchy (what
 you would refer to with :code:`$root` in SystemVerilog).  This meant that
 all internal variables that were implemented by Verilator in the root scope
 were accessible as members of the model class itself.  Note there were often
-many such variable due to module inlining, including :code:`/* verilator
-public_flat */` items.
+many such variable due to module inlining, including
+:code:`/* verilator public_flat */` items.
 
 This means that user code that accesses internal signals in the model
 (likely including :code:`/* verilator public_flat */` signals, as they are
diff --git a/docs/guide/example_cc.rst b/docs/guide/example_cc.rst
index 3d8662aba..41280015b 100644
--- a/docs/guide/example_cc.rst
+++ b/docs/guide/example_cc.rst
@@ -58,13 +58,13 @@ Breaking this command down:
    own compile rules, and run make yourself as we show in :ref:`Example
    SystemC Execution`.)
 
-#. :vlopt:`-j` `0' to Verilate using use as many CPU threads as the machine
-   has.
+#. :vlopt:`-j 0 <-j>` to Verilate using use as many CPU threads as the
+   machine has.
 
 #. :vlopt:`-Wall` so Verilator has stronger lint warnings
    enabled.
 
-#. An finally, :command:`our.v` which is our SystemVerilog design file.
+#. And finally, :command:`our.v` which is our SystemVerilog design file.
 
 Once Verilator completes we can see the generated C++ code under the
 :file:`obj_dir` directory.
diff --git a/docs/guide/example_dist.rst b/docs/guide/example_dist.rst
index 6e6947071..c68509e11 100644
--- a/docs/guide/example_dist.rst
+++ b/docs/guide/example_dist.rst
@@ -7,7 +7,7 @@ Examples in the Distribution
 ============================
 
 See the ``examples/`` directory that is part of the distribution, and
-is installed (in a OS-specific place, often in e.g.
+is installed (in an OS-specific place, often in e.g.
 ``/usr/local/share/verilator/examples``).  These examples include:
 
 examples/make_hello_binary
diff --git a/docs/guide/exe_sim.rst b/docs/guide/exe_sim.rst
index 03dd1d76e..48b85f4fe 100644
--- a/docs/guide/exe_sim.rst
+++ b/docs/guide/exe_sim.rst
@@ -82,10 +82,10 @@ Summary:
 
 .. option:: +verilator+rand+reset+<value>
 
-   When a model was Verilated using :vlopt:`--x-initial unique
-   <--x-initial>`, sets the simulation runtime initialization technique.  0
-   = Reset to zeros. 1 = Reset to all-ones.  2 = Randomize.  See
-   :ref:`Unknown States`.
+   When a model was Verilated using
+   :vlopt:`--x-initial unique <--x-initial>`, sets the simulation runtime
+   initialization technique.  0 = Reset to zeros. 1 = Reset to all-ones.  2
+   = Randomize.  See :ref:`Unknown States`.
 
 .. option:: +verilator+seed+<value>
 
diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst
index d1efb3f25..25534b23c 100644
--- a/docs/guide/exe_verilator.rst
+++ b/docs/guide/exe_verilator.rst
@@ -29,10 +29,10 @@ Summary:
 .. option:: <file.a/.o/.so>
 
    Specifies optional object or library files to be linked in with the
-   Verilog code, as a shorthand for :vlopt:`-LDFLAGS \<file\>`. The file
-   path should either be absolute, or relative to where the make will be
-   executed from, or add to your makefile's VPATH the appropriate directory
-   to find the file.
+   Verilog code, as a shorthand for
+   :vlopt:`-LDFLAGS \<file\> <-LDFLAGS>`. The file path should either be
+   absolute, or relative to where the make will be executed from, or add to
+   your makefile's VPATH the appropriate directory to find the file.
 
    If any files are specified in this way, Verilator will include a make
    rule that uses these files when linking the module's executable.  This
@@ -257,10 +257,11 @@ Summary:
 
 .. option:: -D<var>=<value>
 
-   Defines the given preprocessor symbol.  Similar to :vlopt:`+define
-   <+define+<var>>`, but does not allow multiple definitions with a single
-   option using plus signs. "+define" is fairly standard across Verilog
-   tools while "-D" is similar to :command:`gcc -D`.
+   Defines the given preprocessor symbol.  Similar to
+   :vlopt:`+define <+define+<var>>`, but does not allow multiple
+   definitions with a single option using plus signs. "+define" is fairly
+   standard across Verilog tools while "-D" is similar to
+   :command:`gcc -D`.
 
 .. option:: --debug
 
@@ -270,10 +271,10 @@ Summary:
      generally is a less-optimized binary with symbols present (so GDB can be used on it).
    * Enable debugging messages (equivalent to :vlopt:`--debugi 3 <--debugi>`).
    * Enable internal assertions (equivalent to :vlopt:`--debug-check`).
-   * Enable intermediate form dump files (equivalent to :vlopt:`--dumpi-tree 3
-     <--dumpi-tree>`).
-   * Leak to make node numbers unique (equivalent to :vlopt:`--debug-leak
-     <--no-debug-leak>`.
+   * Enable intermediate form dump files (equivalent to
+     :vlopt:`--dumpi-tree 3 <--dumpi-tree>`).
+   * Leak to make node numbers unique (equivalent to
+     :vlopt:`--debug-leak <--no-debug-leak>`.
    * Call abort() instead of exit() if there are any errors (so GDB can see
      the program state).
 
@@ -304,9 +305,10 @@ Summary:
 .. option:: --debugi-<srcfile> <level>
 
    Rarely needed - for developer use.  Set the specified Verilator source
-   file to the specified level (e.g. :vlopt:`--debugi-V3Width 9
-   <--debugi>`). Higher levels produce more detailed messages.  See
-   :vlopt:`--debug` for other implications of enabling debug.
+   file to the specified level (e.g.
+   :vlopt:`--debugi-V3Width 9 <--debugi>`). Higher levels produce more
+   detailed messages.  See :vlopt:`--debug` for other implications of
+   enabling debug.
 
 .. option:: --no-decoration
 
@@ -378,9 +380,9 @@ Summary:
    Rarely needed.  Enable dumping Ast .tree debug files with dumping level 3,
    which dumps the standard critical stages.  For details on the format see
    the Verilator Internals manual.  :vlopt:`--dump-tree` is enabled
-   automatically with :vlopt:`--debug`, so :vlopt:`--debug --no-dump-tree
-   <--dump-tree>` may be useful if the dump files are large and not
-   desired.
+   automatically with :vlopt:`--debug`, so
+   :vlopt:`--debug --no-dump-tree <--dump-tree>` may be useful if the dump
+   files are large and not desired.
 
 .. option:: --dump-tree-dot
 
@@ -392,7 +394,7 @@ Summary:
 
    Rarely needed - for developer use.  Replace AST node addresses with
    short identifiers in tree dumps to enhance readability.  Each unique
-   pointer value is mapped to a unique identifier, but note that this is
+   pointer value is mapped to an unique identifier, but note that this is
    not necessarily unique per node instance as an address might get reused
    by a newly allocated node after a node with the same address has been
    dumped then freed.
@@ -570,7 +572,7 @@ Summary:
 
    Rarely needed.  Suppress an unknown Verilator option for an option that
    takes no additional arguments.  This is used to allow scripts written
-   with pragmas for a later version of Verilator to run under a older
+   with pragmas for a later version of Verilator to run under an older
    version.  e.g. :code:`-future0 option --option` would on older versions
    that do not understand :code:`--option` or :code:`+option` suppress what
    would otherwise be an invalid option error, and on newer versions that
@@ -582,13 +584,14 @@ Summary:
 
    Rarely needed.  Suppress an unknown Verilator option for an option that
    takes an additional argument.  This is used to allow scripts written
-   with pragmas for a later version of Verilator to run under a older
+   with pragmas for a later version of Verilator to run under an older
    version.  e.g. :code:`-future1 option --option arg` would on older
-   versions that do not understand :code:`--option arg` or :code:`+option
-   arg` suppress what would otherwise be an invalid option error, and on
-   newer versions that implement :code:`--option arg`, :code:`-future1
-   option --option arg` would have the :code:`-future1 option` ignored and
-   the :code:`--option arg` would function appropriately.
+   versions that do not understand :code:`--option arg` or
+   :code:`+option arg` suppress what would otherwise be an invalid option
+   error, and on newer versions that implement :code:`--option arg`,
+   :code:`-future1 option --option arg` would have the
+   :code:`-future1 option` ignored and the :code:`--option arg` would function
+   appropriately.
 
 .. option:: -G<name>=<value>
 
@@ -711,9 +714,9 @@ Summary:
    methodologies. Default is an l2-name matching the top module. The
    default before Verilator 3.884 was ``--l2-name v``.
 
-   For example, the program :code:`module t; initial $display("%m");
-   endmodule` will show by default "t". With ``--l2-name v`` it will print
-   "v".
+   For example, the program
+   :code:`module t; initial $display("%m"); endmodule` will show by default
+   "t". With ``--l2-name v`` it will print "v".
 
 .. option:: --language <value>
 
@@ -855,8 +858,8 @@ Summary:
    Enables slow optimizations for the code Verilator itself generates (as
    opposed to :vlopt:`-CFLAGS -O3 <-CFLAGS>` which effects the C compiler's
    optimization.  :vlopt:`-O3` may improve simulation performance at the
-   cost of compile time.  This currently sets :vlopt:`--inline-mult -1
-   <--inline-mult>`.
+   cost of compile time.  This currently sets
+   :vlopt:`--inline-mult -1 <--inline-mult>`.
 
 .. option:: -O<optimization-letter>
 
@@ -1096,18 +1099,18 @@ Summary:
 .. option:: --public-flat-rw
 
    Declares all variables, ports and wires public as if they had
-   :code:`/*verilator public_flat_rw @
-   (<variable's_source_process_edge>)*/` metacomments.  This will make them
-   VPI accessible by their flat name, but not turn off module inlining.
-   This is particularly useful in combination with :vlopt:`--vpi`. This may
-   also in some rare cases result in mis-simulation of generated clocks.
-   Instead of this global option, marking only those signals that need
-   public_flat_rw is typically significantly better performing.
+   :code:`/*verilator public_flat_rw @ (<variable's_source_process_edge>)*/`
+   metacomments.  This will make them VPI accessible by their flat name,
+   but not turn off module inlining.  This is particularly useful in
+   combination with :vlopt:`--vpi`. This may also in some rare cases result
+   in mis-simulation of generated clocks.  Instead of this global option,
+   marking only those signals that need public_flat_rw is typically
+   significantly better performing.
 
 .. option:: -pvalue+<name>=<value>
 
-   Overwrites the given parameter(s) of the toplevel module. See :vlopt:`-G
-   <-G<name>>` for a detailed description.
+   Overwrites the given parameter(s) of the toplevel module. See
+   :vlopt:`-G <-G<name>>` for a detailed description.
 
 .. option:: --quiet-exit
 
@@ -1465,7 +1468,7 @@ Summary:
 
    Rarely needed.  Suppress unknown Verilator comments or warning messages
    with the given message code.  This is used to allow code written with
-   pragmas for a later version of Verilator to run under a older version;
+   pragmas for a later version of Verilator to run under an older version;
    add "-Wfuture-" arguments for each message code or comment that the new
    version supports which the older version does not support.
 
@@ -1753,15 +1756,16 @@ The grammar of configuration commands is as follows:
 
 .. option:: parallel_case -file "<filename>" -lines <lineno>
 
-   Same as :code:`//synopsys full_case` and :code:`//synopsys
-   parallel_case`. When these synthesis directives are discovered,
-   Verilator will either formally prove the directive to be true, or
-   failing that, will insert the appropriate code to detect failing cases
-   at simulation runtime and print an "Assertion failed" error message.
+   Same as :code:`//synopsys full_case` and
+   :code:`//synopsys parallel_case`. When these synthesis directives are
+   discovered, Verilator will either formally prove the directive to be
+   true, or failing that, will insert the appropriate code to detect
+   failing cases at simulation runtime and print an "Assertion failed"
+   error message.
 
 .. option:: hier_block -module "<modulename>"
 
-   Specifies that the module is a unit of hierarchical Verilation.  Note
+   Specifies that the module is an unit of hierarchical Verilation.  Note
    that the setting is ignored unless the :vlopt:`--hierarchical` option is
    specified.  See :ref:`Hierarchical Verilation`.
 
diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst
index 5cb0cf572..c3f5c6621 100644
--- a/docs/guide/extensions.rst
+++ b/docs/guide/extensions.rst
@@ -57,10 +57,10 @@ or "`ifdef`"'s may break other tools.
    Verilator does not use any text inside the quotes for
    ordering/scheduling.  If you need the $c to be called at a specific
    time, e.g. when a variable changes, then the $c must be under an
-   appropriate sensitivity statement, e.g. :code:`always @(posedge clk)
-   $c("func()")` to call it on every edge, or e.g. :code:`always @*
-   c("func(",a,")")` to call it when :code:`a` changes (the latter working
-   because :code:`a` is outside the quotes).
+   appropriate sensitivity statement, e.g.
+   :code:`always @(posedge clk) $c("func()")` to call it on every edge, or
+   e.g. :code:`always @* c("func(",a,")")` to call it when :code:`a`
+   changes (the latter working because :code:`a` is outside the quotes).
 
    If you will be reading or writing any Verilog variables inside the C++
    functions, the Verilog signals must be declared with
@@ -251,7 +251,7 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: /*verilator&32;hier_block*/
 
-   Specifies that the module is a unit of hierarchical Verilation.  This
+   Specifies that the module is an unit of hierarchical Verilation.  This
    metacomment must be between :code:`module module_name(...);` and
    :code:`endmodule`.  The module will not be inlined nor uniquified for
    each instance in hierarchical Verilation.  Note that the metacomment is
diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst
index e600dc314..21acd8ff6 100644
--- a/docs/guide/languages.rst
+++ b/docs/guide/languages.rst
@@ -80,10 +80,11 @@ string, and wreal.
 Synthesis Directive Assertion Support
 -------------------------------------
 
-With the :vlopt:`--assert` option, Verilator reads any :code:`//synopsys
-full_case` or :code:`//synopsys parallel_case` directives.  The same
-applies to any :code:`//ambit synthesis`, :code:`//cadence` or
-:code:`//pragma` directives of the same form.
+With the :vlopt:`--assert` option, Verilator reads any
+
+:code:`//synopsys full_case` or :code:`//synopsys parallel_case`
+directives.  The same applies to any :code:`//ambit synthesis`,
+:code:`//cadence` or :code:`//pragma` directives of the same form.
 
 When these synthesis directives are discovered, Verilator will either
 formally prove the directive to be true, or failing that, will insert the
@@ -369,7 +370,7 @@ and the address.  For non-power-of-2-sizes arrays, index 0 will be written.
 
 Reading a memory element that is outside the bounds specified for the array
 will give a width warning and wrap around the power-of-2 size.  For
-non-power-of-2 sizes, it will return a unspecified constant of the
+non-power-of-2 sizes, it will return an unspecified constant of the
 appropriate width.
 
 
diff --git a/docs/guide/simulating.rst b/docs/guide/simulating.rst
index 7209a0a19..271985836 100644
--- a/docs/guide/simulating.rst
+++ b/docs/guide/simulating.rst
@@ -18,12 +18,14 @@ Benchmarking & Optimization
 ===========================
 
 For best performance, run Verilator with the :vlopt:`-O3`
-:vlopt:`--x-assign fast <--x-assign>` :vlopt:`--x-initial fast
-<--x-initial>` :vlopt:`--noassert <--assert>` options.  The :vlopt:`-O3`
-option will require longer time to run Verilator, and :vlopt:`--x-assign
-fast <--x-assign>` :vlopt:`--x-initial fast <--x-assign>` may increase the
-risk of reset bugs in trade for performance; see the above documentation
-for these options.
+:vlopt:`--x-assign fast <--x-assign>`
+:vlopt:`--x-initial fast <--x-initial>`
+:vlopt:`--noassert <--assert>` options.  The :vlopt:`-O3`
+option will require longer time to run Verilator, and
+:vlopt:`--x-assign fast <--x-assign>`
+:vlopt:`--x-initial fast <--x-assign>`
+may increase the risk of reset bugs in trade for performance; see the above
+documentation for these options.
 
 If using Verilated multithreaded, use ``numactl`` to ensure you are using
 non-conflicting hardware resources. See :ref:`Multithreading`. Also
@@ -162,7 +164,7 @@ Line Coverage
 
 With :vlopt:`--coverage` or :vlopt:`--coverage-line`, Verilator will
 automatically add coverage analysis at each code flow change point (e.g. at
-branches).  At each such branch a unique counter is incremented.  At the
+branches).  At each such branch an unique counter is incremented.  At the
 end of a test, the counters along with the filename and line number
 corresponding to each counter are written into the coverage file.
 
diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst
index f041097d2..2f91bf7f8 100644
--- a/docs/guide/verilating.rst
+++ b/docs/guide/verilating.rst
@@ -239,17 +239,17 @@ physical core. For best performance use the :command:`numactl` program to
 (when the threading count fits) select unique physical cores on the same
 socket. The same applies for :vlopt:`--trace-threads` as well.
 
-As an example, if a model was Verilated with :vlopt:`--threads 4
-<--threads>`, we consult:
+As an example, if a model was Verilated with
+:vlopt:`--threads 4 <--threads>`, we consult:
 
 .. code-block:: bash
 
     egrep 'processor|physical id|core id' /proc/cpuinfo
 
 To select cores 0, 1, 2, and 3 that are all located on the same socket (0)
-but different physical cores.  (Also useful is :command:`numactl
---hardware`, or :command:`lscpu` but those doesn't show Hyperthreading
-cores.) Then we execute:
+but different physical cores.  (Also useful is
+:command:`numactl --hardware`, or :command:`lscpu` but those doesn't show
+hyperthreading cores.)  Then we execute:
 
 .. code-block:: bash
 
diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst
index 071fc01b8..db4344cd9 100644
--- a/docs/guide/warnings.rst
+++ b/docs/guide/warnings.rst
@@ -150,11 +150,11 @@ List Of Warnings
    practice. Verilator reports this as an error, because ignoring this
    warning may make Verilator simulations differ from other simulators.
 
-   It is generally safe to disable this error (with a :code:`// verilator
-   lint_off BLKANDNBLK` metacomment or the :code:`-Wno-BLKANDNBLK` option)
-   when one of the assignments is inside a public task, or when the
-   blocking and non-blocking assignments have non-overlapping bits and
-   structure members.
+   It is generally safe to disable this error (with a
+   :code:`// verilator lint_off BLKANDNBLK` metacomment or the
+   :code:`-Wno-BLKANDNBLK` option) when one of the assignments is inside a
+   public task, or when the blocking and non-blocking assignments have
+   non-overlapping bits and structure members.
 
    Generally, this is caused by a register driven by both combo logic and a
    flop:
@@ -383,8 +383,10 @@ List Of Warnings
    Verilog, but not SystemVerilog, a wire must be used as the target of
    continuous assignments.
 
-   This error is only reported when :vlopt:`--language 1364-1995
-   <--language>`, :vlopt:`--language 1364-2001 <--language>`, or
+   This error is only reported when
+
+   :vlopt:`--language 1364-1995 <--language>`,
+   :vlopt:`--language 1364-2001 <--language>`, or
    :vlopt:`--language 1364-2005 <--language>` is used.
 
    Ignoring this error will only suppress the lint check, it will simulate
@@ -483,7 +485,7 @@ List Of Warnings
    Error at simulation runtime when model did not properly settle.
 
    Verilator sometimes has to evaluate combinatorial logic multiple times,
-   usually around code where a UNOPTFLAT warning was issued, but disabled.
+   usually around code where an UNOPTFLAT warning was issued, but disabled.
 
    Faulty example:
 
@@ -499,12 +501,13 @@ List Of Warnings
 
    To debug this, first review any UNOPTFLAT warnings that were
    ignored.  Though typically it is safe to ignore UNOPTFLAT (at a
-   performance cost), at the time of issuing a UNOPTFLAT Verilator did not
+   performance cost), at the time of issuing an UNOPTFLAT Verilator did not
    know if the logic would eventually converge and assumed it would.
 
-   Next, run Verilator with :vlopt:`--prof-cfuncs -CFLAGS -DVL_DEBUG
-   <--prof-cfuncs>`.  Rerun the test.  Now just before the convergence
-   error you should see additional output similar to this:
+   Next, run Verilator with
+   :vlopt:`--prof-cfuncs -CFLAGS -DVL_DEBUG <--prof-cfuncs>`.  Rerun the
+   test.  Now just before the convergence error you should see additional
+   output similar to this:
 
    .. include:: ../../docs/gen/ex_DIDNOTCONVERGE_msg.rst
 
@@ -983,7 +986,7 @@ List Of Warnings
 
    Warns that a module has a pin which is not mentioned in an instance.  If
    a pin is not missing it should still be specified on the instance
-   declaration with a empty connection, using :code:`(.pin_name())`.
+   declaration with an empty connection, using :code:`(.pin_name())`.
 
    Ignoring this warning will only suppress the lint check, it will
    simulate correctly.
@@ -1161,7 +1164,7 @@ List Of Warnings
                               example.v:1:20: ... Location of previous definition, with value: 'def2'
 
    The best solution is to use a different name for the second macro.  If
-   this is not possible, add a undef to indicate the code is overriding the
+   this is not possible, add an undef to indicate the code is overriding the
    value. This will express the intent and should avoid future warnings on
    any linting tool:
 
@@ -1555,7 +1558,7 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that the code is comparing a unsigned value in a way that implies
+   Warns that the code is comparing an unsigned value in a way that implies
    it is signed, for example "X < 0" will always be false when X is
    unsigned.
 
@@ -1716,7 +1719,7 @@ List Of Warnings
 
    .. include:: ../../docs/gen/ex_VARHIDDEN_msg.rst
 
-   To resolve, rename the variable to a unique name.
+   To resolve, rename the variable to an unique name.
 
 
 .. option:: WAITCONST
diff --git a/test_regress/t/t_dist_docs_style.pl b/test_regress/t/t_dist_docs_style.pl
index 0cda99082..035c25176 100755
--- a/test_regress/t/t_dist_docs_style.pl
+++ b/test_regress/t/t_dist_docs_style.pl
@@ -23,7 +23,7 @@ foreach my $file (sort keys %files) {
     my $contents = file_contents($filename);
 
     checkPattern($filename, $contents,
-                 qr/.*(?<!ref):\`[^`]+\n/,
+                 qr/.*[a-z](?<!:ref):\`[^`]+\n/,
                  "tag:`...` should not be split between lines");
 }
 

From a0e7930036f7f6b0da9c81a40debeb539ac435ca Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 9 Dec 2022 21:06:27 -0500
Subject: [PATCH 136/156] docs: Fix spelling

---
 Changes                           | 12 ++++++------
 README.rst                        | 12 ++++++------
 docs/CONTRIBUTING.rst             |  7 +------
 docs/guide/extensions.rst         |  2 +-
 docs/internals.rst                |  8 ++++----
 docs/spelling.txt                 | 12 +++++++++++-
 include/verilated_cov.h           |  2 +-
 include/verilatedos.h             |  6 +++---
 src/.gdbinit                      |  2 +-
 src/V3AstNodeExpr.h               |  2 +-
 src/V3AstNodeOther.h              |  2 +-
 src/V3Gate.cpp                    |  2 +-
 src/V3Graph.h                     |  2 +-
 src/V3List.h                      |  8 ++++----
 src/V3OptionParser.cpp            |  2 +-
 src/verilog.y                     |  4 ++--
 test_regress/driver.pl            |  2 +-
 test_regress/t/t_extend_class_c.h |  2 +-
 18 files changed, 47 insertions(+), 42 deletions(-)

diff --git a/Changes b/Changes
index 63f6a978b..1cbddc1f2 100644
--- a/Changes
+++ b/Changes
@@ -75,7 +75,7 @@ Verilator 5.002 2022-10-29
 * Fix linker errors in user-facing timing functions (#3657). [Krzysztof Bieganski, Antmicro Ltd]
 * Fix null access on optimized-out fork statements (#3658). [Krzysztof Bieganski, Antmicro Ltd]
 * Fix VPI inline module naming mismatch (#3690) (#3694). [Jiuyang Liu]
-* Fix deadlock in timeprecision when using systemC (#3707). [Kamil Rakoczy, Antmicro Ltd]
+* Fix deadlock in timeprecision when using SystemC (#3707). [Kamil Rakoczy, Antmicro Ltd]
 * Fix width mismatch on inside operator (#3714). [Alex Torregrosa]
 
 
@@ -2987,7 +2987,7 @@ Verilator 3.502 2005-11-30 Stable
 
 * Fix local non-IO variables in public functions and tasks.
 * Fix bad lifetime optimization when same signal is assigned multiple
-  times in both branch of a if. [Danny Ding]
+  times in both branch of an if. [Danny Ding]
 
 
 Verilator 3.501 2005-11-16 Stable
@@ -3127,8 +3127,8 @@ Verilator 3.450 2005-07-12
 * $finish will no longer exit, but set Verilated::gotFinish().
   This enables support for final statements, and for other cleanup code.
   If this is undesired, redefine the vl_user_finish routine. Top level
-  loops should use Verilated::gotFinish() as a exit condition for their
-  loop, and then call top->final(). To prevent a infinite loop, a double
+  loops should use Verilated::gotFinish() as an exit condition for their
+  loop, and then call top->final(). To prevent an infinite loop, a double
   $finish will still exit; this may be removed in future releases.
 * Support SystemVerilog keywords $bits, $countones, $isunknown,
   $onehot, $onehot0, always_comb, always_ff, always_latch, finish.
@@ -3529,7 +3529,7 @@ Verilator 3.201-beta 2003-12-10
 **Major:**
 
 * BETA VERSION, USE 3.124 for stable release!
-* Version 3.2XX includes a all new back-end.
+* Version 3.2XX includes an all new back-end.
   This includes automatic inlining, flattening of signals between
   hierarchy, and complete ordering of statements. This results in
   60-300% execution speedups, though less pretty C++ output. Even
@@ -3558,7 +3558,7 @@ Verilator 3.124 2003-12-05
 
 **Major:**
 
-* A optimized executable will be made by default, in addition to a debug
+* An optimized executable will be made by default, in addition to a debug
   executable. Invoking Verilator with --debug will pick the debug version.
 
 **Minor:**
diff --git a/README.rst b/README.rst
index d46296d02..dbc308a47 100644
--- a/README.rst
+++ b/README.rst
@@ -29,7 +29,7 @@ Welcome to Verilator
    * - |verilator multithreaded performance|
      - **Fast**
         * Outperforms many closed-source commercial simulators
-        * Single- and multi-threaded output models
+        * Single- and multithreaded output models
    * - **Widely Used**
         * Wide industry and academic deployment
         * Out-of-the-box support from Arm, and RISC-V vendor IP
@@ -52,7 +52,7 @@ What Verilator Does
 Verilator is invoked with parameters similar to GCC or Synopsys's VCS.  It
 "Verilates" the specified Verilog or SystemVerilog code by reading it,
 performing lint checks, and optionally inserting assertion checks and
-coverage-analysis points. It outputs single- or multi-threaded .cpp and .h
+coverage-analysis points. It outputs single- or multithreaded .cpp and .h
 files, the "Verilated" code.
 
 These Verilated C++/SystemC files are then compiled by a C++ compiler
@@ -61,11 +61,11 @@ file to instantiate the Verilated model. Executing the resulting executable
 performs the design simulation. Verilator also supports linking Verilated
 generated libraries, optionally encrypted, into other simulators.
 
-Verilator may not be the best choice if you are expecting a full featured
+Verilator may not be the best choice if you are expecting a full-featured
 replacement for a closed-source Verilog simulator, need SDF annotation,
 mixed-signal simulation, or are doing a quick class project (we recommend
 `Icarus Verilog`_ for classwork.)  However, if you are looking for a path
-to migrate SystemVerilog to C++/SystemC, or want high speed simulation of
+to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of
 synthesizable designs containing limited verification constructs, Verilator
 is the tool for you.
 
@@ -86,7 +86,7 @@ Verilator has typically similar or better performance versus the
 closed-source Verilog simulators (Carbon Design Systems Carbonator,
 Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and
 Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on
-computes rather than licenses. Thus Verilator gives you the best
+computes rather than licenses. Thus, Verilator gives you the best
 cycles/dollar.
 
 
@@ -132,7 +132,7 @@ Related Projects
 - `GTKwave <http://gtkwave.sourceforge.net/>`_ - Waveform viewer for
   Verilator traces.
 
-- `Icarus Verilog`_ - Icarus is a full featured interpreted Verilog
+- `Icarus Verilog`_ - Icarus is a full-featured interpreted Verilog
   simulator. If Verilator does not support your needs, perhaps Icarus may.
 
 
diff --git a/docs/CONTRIBUTING.rst b/docs/CONTRIBUTING.rst
index d6cfd2fc3..15f2fed27 100644
--- a/docs/CONTRIBUTING.rst
+++ b/docs/CONTRIBUTING.rst
@@ -44,15 +44,10 @@ Did you write a patch that fixes a bug?
   - Have your patch include the addition of your name to `docs/CONTRIBUTORS
     <CONTRIBUTORS>`__ (preferred).
 
-  - Use "git -s" as part of your commit. This adds a "signed-of-by"
-    attribute which will certify your contribution as described in the
-    `Signed-of-By convention
-    <https://github.com/wking/signed-off-by/blob/master/Documentation/SubmittingPatches>`__.
-
   - Email, or post in an issue a statement that you certify your
     contributions.
 
-  - In any of these cases your name will be added to `docs/CONTRIBUTORS
+  - In any of these cases, your name will be added to `docs/CONTRIBUTORS
     <CONTRIBUTORS>`__ and you are agreeing all future contributions are
     also certified.
 
diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst
index c3f5c6621..24098c5ea 100644
--- a/docs/guide/extensions.rst
+++ b/docs/guide/extensions.rst
@@ -563,7 +563,7 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: $stacktrace
 
-   Called as a task, orint a stack trace.  Called as a function, return a
+   Called as a task, print a stack trace.  Called as a function, return a
    string with a stack trace.  This relies on the C++ system trace, which
    may give less meaningful results if the model was not compiled with
    debug symbols.  Also the data represents the C++ stack, the
diff --git a/docs/internals.rst b/docs/internals.rst
index 3c4a2404b..f4aa386a6 100644
--- a/docs/internals.rst
+++ b/docs/internals.rst
@@ -42,7 +42,7 @@ The main flow of Verilator can be followed by reading the Verilator.cpp
 4.  Functions, variable and other references are linked to their
     definitions.
 
-5.  Parameters are resolved and the design is elaborated.
+5.  Parameters are resolved, and the design is elaborated.
 
 6.  Verilator then performs many additional edits and optimizations on
     the hierarchical design. This includes coverage, assertions, X
@@ -149,8 +149,8 @@ an associated ``fanout``, ``color`` and ``rank``, which may be used in
 algorithms for ordering the graph. A generic ``user``/``userp`` member
 variable is also provided.
 
-Virtual methods are provided to specify the name, color, shape and style to
-be used in dot output. Typically users provide derived classes from
+Virtual methods are provided to specify the name, color, shape, and style
+to be used in dot output. Typically, users provide derived classes from
 ``V3GraphVertex`` which will reimplement these methods.
 
 Iterators are provided to access in and out edges. Typically these are used
@@ -994,7 +994,7 @@ Per-Instance Classes
 If we have multiple instances of the same module, and they partition
 differently (likely; we make no attempt to partition them the same) then
 the variable sort will be suboptimal for either instance. A possible
-improvement would be to emit a unique class for each instance of a module,
+improvement would be to emit an unique class for each instance of a module,
 and sort its variables optimally for that instance's code stream.
 
 
diff --git a/docs/spelling.txt b/docs/spelling.txt
index 3e1b7e7d3..c47f7dda6 100644
--- a/docs/spelling.txt
+++ b/docs/spelling.txt
@@ -225,6 +225,7 @@ Nalbantis
 Narayan
 Nauticus
 Newgard
+Nigam
 Nikana
 Niranjan
 Nitza
@@ -239,6 +240,7 @@ Patricio
 Petr
 Piechotka
 Piersall
+Platzer
 Plunkett
 Popolon
 Popov
@@ -253,6 +255,7 @@ Pullup
 Pulver
 Puri
 Questa
+Rachit
 Ralf
 Rapp
 Redhat
@@ -383,6 +386,7 @@ agrobman
 ahouska
 al
 ala
+alejandro
 algrobman
 andit
 ar
@@ -407,7 +411,6 @@ biguint
 biops
 bisonpre
 bitOpTree
-bitOpTree
 bitop
 bitstoreal
 blackbox
@@ -422,6 +425,7 @@ callValueCbs
 casex
 casez
 casted
+castro
 cb
 ccache
 ccall
@@ -462,6 +466,7 @@ cutable
 cygwin
 dM
 da
+danbone
 dat
 datadir
 datafiles
@@ -590,6 +595,7 @@ hierCMakeArgs
 hierMkArgs
 hierVer
 hx
+hyperthreading
 hyperthreads
 icecream
 idmap
@@ -649,6 +655,7 @@ makefiles
 manpages
 metacomment
 metacomments
+miree
 mis
 misconnected
 misconversion
@@ -657,6 +664,7 @@ mk
 mno
 modport
 modports
+mpb
 msg
 msvc
 mtask
@@ -696,6 +704,7 @@ nullptr
 onehot
 ooo
 oprofile
+ortegon
 oversubscription
 parallelized
 param
@@ -748,6 +757,7 @@ pwd
 qrq
 radix
 randc
+randcase
 rarr
 rdtsc
 reStructuredText
diff --git a/include/verilated_cov.h b/include/verilated_cov.h
index 01240f60f..bd92e064c 100644
--- a/include/verilated_cov.h
+++ b/include/verilated_cov.h
@@ -36,7 +36,7 @@
 class VerilatedCovImp;
 
 //=============================================================================
-/// Insert a item for coverage analysis.
+/// Insert an item for coverage analysis.
 /// The first argument is a pointer to the count to be dumped.
 /// The remaining arguments occur in pairs: A string key, and a value.
 /// The value may be a string, or another type which will be auto-converted to a string.
diff --git a/include/verilatedos.h b/include/verilatedos.h
index 2e6e5cb49..72f80d0e7 100644
--- a/include/verilatedos.h
+++ b/include/verilatedos.h
@@ -387,9 +387,9 @@ using ssize_t = uint32_t;  ///< signed size_t; returned from read()
 
 #define VL_BYTESIZE 8  ///< Bits in a CData / byte
 #define VL_SHORTSIZE 16  ///< Bits in a SData / short
-#define VL_IDATASIZE 32  ///< Bits in a IData / word
+#define VL_IDATASIZE 32  ///< Bits in an IData / word
 #define VL_QUADSIZE 64  ///< Bits in a QData / quadword
-#define VL_EDATASIZE 32  ///< Bits in a EData (WData entry)
+#define VL_EDATASIZE 32  ///< Bits in an EData (WData entry)
 #define VL_EDATASIZE_LOG2 5  ///< log2(VL_EDATASIZE)
 #define VL_CACHE_LINE_BYTES 64  ///< Bytes in a cache line (for alignment)
 
@@ -443,7 +443,7 @@ using ssize_t = uint32_t;  ///< signed size_t; returned from read()
 #define VL_BITWORD_E(bit) ((bit) >> VL_EDATASIZE_LOG2)  ///< Word number for a wide quantity
 #define VL_BITBIT_I(bit) ((bit) & VL_SIZEBITS_I)  ///< Bit number for a bit in a long
 #define VL_BITBIT_Q(bit) ((bit) & VL_SIZEBITS_Q)  ///< Bit number for a bit in a quad
-#define VL_BITBIT_E(bit) ((bit) & VL_SIZEBITS_E)  ///< Bit number for a bit in a EData
+#define VL_BITBIT_E(bit) ((bit) & VL_SIZEBITS_E)  ///< Bit number for a bit in an EData
 
 // Return true if data[bit] set; not 0/1 return, but 0/non-zero return.
 #define VL_BITISSET_I(data, bit) ((data) & (VL_UL(1) << VL_BITBIT_I(bit)))
diff --git a/src/.gdbinit b/src/.gdbinit
index b09fa6539..9ad13ac14 100644
--- a/src/.gdbinit
+++ b/src/.gdbinit
@@ -31,5 +31,5 @@ define watchedit
    watch AstNode::s_editCntGbl==$arg0
 end
 document watchedit
-  Verilator: Create watch on where a edit number is made
+  Verilator: Create watch on where an edit number is made
 end
diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index da8683b5c..5b2bb9d43 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -312,7 +312,7 @@ public:
     bool same(const AstNode*) const override { return true; }
 };
 class AstNodeTermop VL_NOT_FINAL : public AstNodeExpr {
-    // Terminal operator -- a operator with no "inputs"
+    // Terminal operator -- an operator with no "inputs"
 protected:
     AstNodeTermop(VNType t, FileLine* fl)
         : AstNodeExpr{t, fl} {}
diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index 74a14a238..e407dbf4a 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -2231,7 +2231,7 @@ public:
 
 // === AstNodeRange ===
 class AstBracketRange final : public AstNodeRange {
-    // Parser only concept "[lhsp]", a AstUnknownRange, QueueRange or Range,
+    // Parser only concept "[lhsp]", an AstUnknownRange, QueueRange or Range,
     // unknown until lhsp type is determined
     // @astgen op1 := elementsp : AstNode // Expr or DType
 public:
diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp
index ead1d325f..fe8fae672 100644
--- a/src/V3Gate.cpp
+++ b/src/V3Gate.cpp
@@ -283,7 +283,7 @@ public:
         for (GateVarRefList::const_iterator it = m_rhsVarRefs.begin(); it != m_rhsVarRefs.end();
              ++it) {
             if (m_lhsVarRef && m_lhsVarRef->varScopep() == (*it)->varScopep()) {
-                clearSimple("Circular logic\n");  // Oh my, we'll get a UNOPTFLAT much later.
+                clearSimple("Circular logic\n");  // Oh my, we'll get an UNOPTFLAT much later
             }
         }
         if (debug() >= 9 && !m_isSimple) nodep->dumpTree("-    gate!Ok: ");
diff --git a/src/V3Graph.h b/src/V3Graph.h
index e54e5d46c..8589a003c 100644
--- a/src/V3Graph.h
+++ b/src/V3Graph.h
@@ -115,7 +115,7 @@ public:
     /// (I.E. all loops will occur within each color, not between them.)
     void stronglyConnected(V3EdgeFuncP edgeFuncp);
 
-    /// Assign a ordering number to all vertexes in a tree.
+    /// Assign an ordering number to all vertexes in a tree.
     /// All nodes with no inputs will get rank 1
     void rank(V3EdgeFuncP edgeFuncp);
     void rank();
diff --git a/src/V3List.h b/src/V3List.h
index e7e524c6e..c32794cc2 100644
--- a/src/V3List.h
+++ b/src/V3List.h
@@ -64,7 +64,7 @@ private:
     T m_prevp = nullptr;  // Pointer to previous element, nullptr=beginning
     friend class V3List<T>;
     static V3ListEnt* baseToListEnt(void* newbasep, size_t offset) {
-        // "this" must be a element inside of *basep
+        // "this" must be an element inside of *basep
         // Use that to determine a structure offset, then apply to the new base
         // to get our new pointer information
         return (V3ListEnt*)(((uint8_t*)newbasep) + offset);
@@ -83,7 +83,7 @@ public:
     T prevp() const { return m_prevp; }
     // METHODS
     void pushBack(V3List<T>& listr, T newp) {
-        // "this" must be a element inside of *newp
+        // "this" must be an element inside of *newp
         // cppcheck-suppress thisSubtraction
         const size_t offset = (size_t)(uint8_t*)(this) - (size_t)(uint8_t*)(newp);
         m_nextp = nullptr;
@@ -93,7 +93,7 @@ public:
         listr.m_tailp = newp;
     }
     void pushFront(V3List<T>& listr, T newp) {
-        // "this" must be a element inside of *newp
+        // "this" must be an element inside of *newp
         // cppcheck-suppress thisSubtraction
         const size_t offset = (size_t)(uint8_t*)(this) - (size_t)(uint8_t*)(newp);
         m_nextp = listr.m_headp;
@@ -104,7 +104,7 @@ public:
     }
     // Unlink from side
     void unlink(V3List<T>& listr, T oldp) {
-        // "this" must be a element inside of *oldp
+        // "this" must be an element inside of *oldp
         // cppcheck-suppress thisSubtraction
         const size_t offset = (size_t)(uint8_t*)(this) - (size_t)(uint8_t*)(oldp);
         if (m_nextp) {
diff --git a/src/V3OptionParser.cpp b/src/V3OptionParser.cpp
index cc019b33d..7c26d1a86 100644
--- a/src/V3OptionParser.cpp
+++ b/src/V3OptionParser.cpp
@@ -74,7 +74,7 @@ struct V3OptionParser::Impl {
 #define V3OPTION_PARSER_DEF_ACT_CLASS(className, type, body, enType) \
     template <> \
     class V3OptionParser::Impl::className<type> final : public ActionBase<enType> { \
-        type* const m_valp; /* Pointer to a option variable*/ \
+        type* const m_valp; /* Pointer to an option variable*/ \
 \
     public: \
         explicit className(type* valp) \
diff --git a/src/verilog.y b/src/verilog.y
index 8621e4e6b..311e68a4c 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -991,9 +991,9 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"})
 %token<fl>              yP_SRIGHTEQ     ">>="
 %token<fl>              yP_SSRIGHTEQ    ">>>="
 
-// [* is not a operator, as "[ * ]" is legal
+// [* is not an operator, as "[ * ]" is legal
 // [= and [-> could be repitition operators, but to match [* we don't add them.
-// '( is not a operator, as "' (" is legal
+// '( is not an operator, as "' (" is legal
 
 //********************
 // Verilog op precedence
diff --git a/test_regress/driver.pl b/test_regress/driver.pl
index 03018ac01..a2a7899a1 100755
--- a/test_regress/driver.pl
+++ b/test_regress/driver.pl
@@ -1575,7 +1575,7 @@ sub _run {
     if ($param{verilator_run}) {
         # Gcov fails when parallel jobs write same data file,
         # so we make sure .gcda output dir is unique across all running jobs.
-        # We can't just put each one in a unique obj_dir as it uses too much disk.
+        # We can't just put each one in an unique obj_dir as it uses too much disk.
         # Must use absolute path as some execute()s have different PWD
         $ENV{GCOV_PREFIX_STRIP} = 99;
         $ENV{GCOV_PREFIX} = File::Spec->rel2abs("$FindBin::RealBin/obj_dist/gcov_$self->{running_id}");
diff --git a/test_regress/t/t_extend_class_c.h b/test_regress/t/t_extend_class_c.h
index a1cdd58dc..d1bd62610 100644
--- a/test_regress/t/t_extend_class_c.h
+++ b/test_regress/t/t_extend_class_c.h
@@ -12,6 +12,6 @@ public:
     t_extend_class_c() = default;
     ~t_extend_class_c() = default;
     // METHODS
-    // This function will be called from a instance created in Verilog
+    // This function will be called from an instance created in Verilog
     uint32_t my_math(uint32_t in) { return in + 1; }
 };

From a9ff0a0f32b8f9caf89af607c02e350e5fbbf8f6 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 9 Dec 2022 23:16:14 -0500
Subject: [PATCH 137/156] docs: Fix grammar

---
 README.rst                            |   6 +-
 docs/guide/changes.rst                |   2 +-
 docs/guide/contributors.rst           |  12 +-
 docs/guide/copyright.rst              |   4 +-
 docs/guide/example_common_install.rst |   2 +-
 docs/guide/overview.rst               |  20 +--
 docs/internals.rst                    | 224 +++++++++++++-------------
 7 files changed, 134 insertions(+), 136 deletions(-)

diff --git a/README.rst b/README.rst
index dbc308a47..02b0593e1 100644
--- a/README.rst
+++ b/README.rst
@@ -32,7 +32,7 @@ Welcome to Verilator
         * Single- and multithreaded output models
    * - **Widely Used**
         * Wide industry and academic deployment
-        * Out-of-the-box support from Arm, and RISC-V vendor IP
+        * Out-of-the-box support from Arm and RISC-V vendor IP
      - |verilator usage|
    * - |verilator community|
      - **Community Driven & Openly Licensed**
@@ -62,7 +62,7 @@ performs the design simulation. Verilator also supports linking Verilated
 generated libraries, optionally encrypted, into other simulators.
 
 Verilator may not be the best choice if you are expecting a full-featured
-replacement for a closed-source Verilog simulator, need SDF annotation,
+replacement for a closed-source Verilog simulator, needs SDF annotation,
 mixed-signal simulation, or are doing a quick class project (we recommend
 `Icarus Verilog`_ for classwork.)  However, if you are looking for a path
 to migrate SystemVerilog to C++/SystemC, or want high-speed simulation of
@@ -101,7 +101,7 @@ For more information:
 - `Verilator manual (HTML) <https://verilator.org/verilator_doc.html>`_,
   or `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_
 
-- `Subscribe to verilator announcements
+- `Subscribe to Verilator announcements
   <https://github.com/verilator/verilator-announce>`_
 
 - `Verilator forum <https://verilator.org/forum>`_
diff --git a/docs/guide/changes.rst b/docs/guide/changes.rst
index 3688dc00e..f8baf257a 100644
--- a/docs/guide/changes.rst
+++ b/docs/guide/changes.rst
@@ -10,7 +10,7 @@ Revision History
    "Revision History" in the sidebar.
 
 Changes are contained in the :file:`Changes` file of the distribution, and
-also summarized below.  To subscribe to new versions see `Verilator
+also summarized below.  To subscribe to new versions, see `Verilator
 Announcements <https://github.com/verilator/verilator-announce>`_.
 
 .. include:: ../_build/gen/Changes
diff --git a/docs/guide/contributors.rst b/docs/guide/contributors.rst
index 290619929..3d82e0b62 100644
--- a/docs/guide/contributors.rst
+++ b/docs/guide/contributors.rst
@@ -137,11 +137,11 @@ Historical Origins
 
 Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group at
 Digital Equipment Corporation.  The Verilog code that was converted to C
-was then merged with a C based CPU model of the Alpha processor and
-simulated in a C based environment called CCLI.
+was then merged with a C-based CPU model of the Alpha processor and
+simulated in a C-based environment called CCLI.
 
-In 1995 Verilator started being used also for Multimedia and Network
-Processor development inside Digital.  Duane Galbi took over active
+In 1995 Verilator started being also used for Multimedia and Network
+Processor development inside Digital.  Duane Galbi took over the active
 development of Verilator, and added several performance enhancements.  CCLI
 was still being used as the shell.
 
@@ -149,7 +149,7 @@ In 1998, through the efforts of existing DECies, mainly Duane Galbi,
 Digital graciously agreed to release the source code.  (Subject to the code
 not being resold, which is compatible with the GNU Public License.)
 
-In 2001, Wilson Snyder took the kit, and added a SystemC mode, and called
+In 2001, Wilson Snyder took the kit, added a SystemC mode, and called
 it Verilator2.  This was the first packaged public release.
 
 In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from
@@ -168,5 +168,5 @@ fork/join, delay handling, DFG performance optimizations, and other
 improvements.
 
 Currently, various language features and performance enhancements are added
-as the need arises, with a focus towards getting to full Universal
+as the need arises, with a focus on getting to complete Universal
 Verification Methodology (UVM, IEEE 1800.2-2017) support.
diff --git a/docs/guide/copyright.rst b/docs/guide/copyright.rst
index 50bccc55f..245141c1d 100644
--- a/docs/guide/copyright.rst
+++ b/docs/guide/copyright.rst
@@ -13,7 +13,7 @@ can redistribute it and/or modify the Verilator internals under the terms
 of either the GNU Lesser General Public License Version 3 or the Perl
 Artistic License Version 2.0.
 
-All Verilog and C++/SystemC code quoted within this documentation file are
-released as Creative Commons Public Domain (CC0).  Many example files and
+All Verilog and C++/SystemC code quoted within this documentation file is
+released as Creative Commons Public Domain (CC0). Many example files and
 test files are likewise released under CC0 into effectively the Public
 Domain as described in the files themselves.
diff --git a/docs/guide/example_common_install.rst b/docs/guide/example_common_install.rst
index 07697c4f3..c834a7cda 100644
--- a/docs/guide/example_common_install.rst
+++ b/docs/guide/example_common_install.rst
@@ -1,7 +1,7 @@
 .. Copyright 2003-2022 by Wilson Snyder.
 .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-First you need Verilator installed, see :ref:`Installation`. In brief, if
+First you need Verilator installed, see :ref:`Installation`.  In brief, if
 you installed Verilator using the package manager of your operating system,
 or did a :command:`make install` to place Verilator into your default path,
 you do not need anything special in your environment, and should not have
diff --git a/docs/guide/overview.rst b/docs/guide/overview.rst
index d69100814..3661883fb 100644
--- a/docs/guide/overview.rst
+++ b/docs/guide/overview.rst
@@ -8,8 +8,8 @@ Overview
 Welcome to Verilator!
 
 The Verilator package converts Verilog [#]_ and SystemVerilog [#]_ hardware
-description language (HDL) designs into a C++ or SystemC model that after
-compiling can be executed.  Verilator is not a traditional simulator, but a
+description language (HDL) designs into a C++ or SystemC model that, after
+compiling, can be executed.  Verilator is not a traditional simulator, but a
 compiler.
 
 Verilator is typically used as follows:
@@ -18,13 +18,13 @@ Verilator is typically used as follows:
 to GCC, or other simulators such as Cadence Verilog-XL/NC-Verilog, or
 Synopsys VCS.  Verilator reads the specified SystemVerilog code, lints it,
 optionally adds coverage and waveform tracing support, and compiles the
-design into a source level multithreaded C++ or SystemC "model".  The
+design into a source-level multithreaded C++ or SystemC "model".  The
 resulting model's C++ or SystemC code is output as .cpp and .h files. This
-is referred to as "Verilating" and the process is "to Verilate"; the output
-is a "Verilated" model.
+is referred to as "Verilating", and the process is "to Verilate"; the
+output is a "Verilated" model.
 
-2. For simulation, a small user written C++ wrapper file is required, the
-"wrapper".  This wrapper defines the C++ standard function "main()" which
+2. For simulation, a small-user written C++ wrapper file is required, the
+"wrapper".  This wrapper defines the C++ standard function "main()", which
 instantiates the Verilated model as a C++/SystemC object.
 
 3. The user C++ wrapper, the files created by Verilator, a "runtime
@@ -44,12 +44,12 @@ The best place to get started is to try the :ref:`Examples`.
 .. [#] Verilog is defined by the `Institute of Electrical and Electronics
        Engineers (IEEE) Standard for Verilog Hardware Description
        Language`, Std. 1364, released in 1995, 2001, and 2005.  The
-       Verilator documentation uses the shorthand e.g. "IEEE 1394-2005" to
-       refer to the e.g. 2005 version of this standard.
+       Verilator documentation uses the shorthand, e.g., "IEEE 1394-2005",
+       to refer to the e.g. 2005 version of this standard.
 
 .. [#] SystemVerilog is defined by the `Institute of Electrical and
        Electronics Engineers (IEEE) Standard for SystemVerilog - Unified
        Hardware Design, Specification, and Verification Language`, Standard
        1800, released in 2005, 2009, 2012, and 2017.  The Verilator
-       documentation uses the shorthand e.g. "IEEE 1800-2017" to refer to
+       documentation uses the shorthand e.g., "IEEE 1800-2017", to refer to
        the e.g. 2017 version of this standard.
diff --git a/docs/internals.rst b/docs/internals.rst
index f4aa386a6..47801dac1 100644
--- a/docs/internals.rst
+++ b/docs/internals.rst
@@ -39,12 +39,12 @@ The main flow of Verilator can be followed by reading the Verilator.cpp
 3.  Cells in the AST first linked, which will read and parse additional
     files as above.
 
-4.  Functions, variable and other references are linked to their
+4.  Functions, variable, and other references are linked to their
     definitions.
 
 5.  Parameters are resolved, and the design is elaborated.
 
-6.  Verilator then performs many additional edits and optimizations on
+6.  Verilator then performs additional edits and optimizations on
     the hierarchical design. This includes coverage, assertions, X
     elimination, inlining, constant propagation, and dead code
     elimination.
@@ -56,15 +56,15 @@ The main flow of Verilator can be followed by reading the Verilator.cpp
     a single scope and single VarScope for each variable. A module that
     occurs twice will have a scope for each occurrence, and two
     VarScopes for each variable. This allows optimizations to proceed
-    across the flattened design, while still preserving the hierarchy.
+    across the flattened design while still preserving the hierarchy.
 
 8.  Additional edits and optimizations proceed on the pseudo-flat
     design. These include module references, function inlining, loop
     unrolling, variable lifetime analysis, lookup table creation, always
-    splitting, and logic gate simplifications (pushing inverters, etc).
+    splitting, and logic gate simplifications (pushing inverters, etc.).
 
 9.  Verilator orders the code. Best case, this results in a single
-    "eval" function which has all always statements flowing from top to
+    "eval" function, which has all always statements flowing from top to
     bottom with no loops.
 
 10. Verilator mostly removes the flattening, so that code may be shared
@@ -95,14 +95,14 @@ this.
 
 Each ``AstNode`` has pointers to up to four children, accessed by the
 ``op1p`` through ``op4p`` methods. These methods are then abstracted in a
-specific Ast\* node class to a more specific name. For example with the
+specific Ast\* node class to a more specific name. For example, with the
 ``AstIf`` node (for ``if`` statements), ``thensp`` calls ``op2p`` to give the
 pointer to the AST for the "then" block, while ``elsesp`` calls ``op3p`` to
 give the pointer to the AST for the "else" block, or NULL if there is not
 one. These accessors are automatically generated by ``astgen`` after
 parsing the ``@astgen`` directives in the specific ``AstNode`` subclasses.
 
-``AstNode`` has the concept of a next and previous AST - for example the
+``AstNode`` has the concept of a next and previous AST - for example, the
 next and previous statements in a block. Pointers to the AST for these
 statements (if they exist) can be obtained using the ``back`` and ``next``
 methods.
@@ -136,7 +136,7 @@ the pass.
 
 A number of passes use graph algorithms, and the class ``V3Graph`` is
 provided to represent those graphs. Graphs are directed, and algorithms are
-provided to manipulate the graphs and to output them in `GraphViz
+provided to manipulate the graphs and output them in `GraphViz
 <https://www.graphviz.org>`__ dot format. ``V3Graph.h`` provides
 documentation of this class.
 
@@ -150,7 +150,7 @@ algorithms for ordering the graph. A generic ``user``/``userp`` member
 variable is also provided.
 
 Virtual methods are provided to specify the name, color, shape, and style
-to be used in dot output. Typically, users provide derived classes from
+to be used in dot output. Typically users provide derived classes from
 ``V3GraphVertex`` which will reimplement these methods.
 
 Iterators are provided to access in and out edges. Typically these are used
@@ -173,9 +173,9 @@ vertices. Edges have an associated ``weight`` and may also be made
 Accessors, ``fromp`` and ``top`` return the "from" and "to" vertices
 respectively.
 
-Virtual methods are provided to specify the label, color and style to be
+Virtual methods are provided to specify the label, color, and style to be
 used in dot output. Typically users provided derived classes from
-``V3GraphEdge`` which will reimplement these methods.
+``V3GraphEdge``, which will reimplement these methods.
 
 
 ``V3GraphAlg``
@@ -183,7 +183,7 @@ used in dot output. Typically users provided derived classes from
 
 This is the base class for graph algorithms. It implements a ``bool``
 method, ``followEdge`` which algorithms can use to decide whether an edge
-is followed. This method returns true if the graph edge has weight greater
+is followed. This method returns true if the graph edge has a weight greater
 than one and a user function, ``edgeFuncp`` (supplied in the constructor)
 returns ``true``.
 
@@ -194,11 +194,11 @@ provided and documented in ``V3GraphAlg.cpp``.
 ``DfgGraph``
 ^^^^^^^^^^^^^
 
-The data-flow graph based combinational logic optimizer (DFG optimizer)
+The data-flow graph-based combinational logic optimizer (DFG optimizer)
 converts an ``AstModule`` into a ``DfgGraph``. The graph represents the
 combinational equations (~continuous assignments) in the module, and for the
 duration of the DFG passes, it takes over the role of the represented
-``AstModule``. The ``DfgGraph`` keeps holds of the represented ``AstModule``,
+``AstModule``. The ``DfgGraph`` keeps hold of the represented ``AstModule``,
 and the ``AstModule`` retains all other logic that is not representable as a
 data-flow graph. At the end of optimization, the combinational logic
 represented by the ``DfgGraph`` is converted back into AST form and is
@@ -212,7 +212,7 @@ writing DFG passes easier.
 
 The ``DfgGraph`` represents combinational logic equations as a graph of
 ``DfgVertex`` vertices. Each sub-class of ``DfgVertex`` corresponds to an
-expression (a sub-class of ``AstNodeExpr``), a constanat, or a variable
+expression (a sub-class of ``AstNodeExpr``), a constant, or a variable
 reference. LValues and RValues referencing the same storage location are
 represented by the same ``DfgVertex``. Consumers of such vertices read as the
 LValue, writers of such vertices write the RValue. The bulk of the final
@@ -225,11 +225,11 @@ Scheduling
 
 Verilator implements the Active and NBA regions of the SystemVerilog scheduling
 model as described in IEEE 1800-2017 chapter 4, and in particular sections
-4.5 and Figure 4.1. The static (verilation time) scheduling of SystemVerilog
+4.5 and Figure 4.1. The static (Verilation time) scheduling of SystemVerilog
 processes is performed by code in the ``V3Sched`` namespace. The single
-entry-point to the scheduling algorithm is ``V3Sched::schedule``. Some
+entry point to the scheduling algorithm is ``V3Sched::schedule``. Some
 preparatory transformations important for scheduling are also performed in
-``V3Active`` and ``V3ActiveTop``. High level evaluation functions are
+``V3Active`` and ``V3ActiveTop``. High-level evaluation functions are
 constructed by ``V3Order``, which ``V3Sched`` invokes on subsets of the logic
 in the design.
 
@@ -267,8 +267,8 @@ The classes of logic we distinguish between are:
   below.
 
 - Clocked logic. Any process or construct that has an explicit sensitivity
-  list, with no implicit sensitivities is considered 'clocked' (or
-  'sequential') logic. This includes among other things ``always`` and
+  list, with no implicit sensitivities, is considered 'clocked' (or
+  'sequential') logic. This includes, among other things ``always`` and
   ``always_ff`` processes with an explicit sensitivity list.
 
 Note that the distinction between clocked logic and combinational logic is only
@@ -321,7 +321,7 @@ At the highest level, ordering is performed by ``V3Order::order``, which is
 invoked by ``V3Sched::schedule`` on various subsets of the combinational and
 clocked logic as described below. The important thing to highlight now is that
 ``V3Order::order`` operates by assuming that the state of all variables driven
-by combinational logic are consistent with that combinational logic. While this
+by combinational logic is consistent with that combinational logic. While this
 might seem subtle, it is very important, so here is an example:
 
 ::
@@ -335,7 +335,7 @@ first, and all downstream combinational logic (like the assignment to ``d``)
 will execute after the clocked logic that drives inputs to the combinational
 logic, in data-flow (or dependency) order. At the end of the evaluation step,
 this ordering restores the invariant that variables driven by combinational
-logic are consistent with that combinational logic (i.e.: the circuit is in a
+logic are consistent with that combinational logic (i.e., the circuit is in a
 settled/steady state).
 
 One of the most important optimizations for performance is to only evaluate
@@ -344,12 +344,12 @@ point in evaluating the above assignment to ``d`` on a negative edge of the
 clock signal. Verilator does this by pushing the combinational logic into the
 same (possibly multiple) event domains as the logic driving the inputs to that
 combinational logic, and only evaluating the combinational logic if at least
-one driving domains have been triggered. The impact of this activity gating is
+one driving domain has been triggered. The impact of this activity gating is
 very high (observed 100x slowdown on large designs when turning it off), it is
 the reason we prefer to convert clocked logic to combinational logic in
 ``V3Active`` whenever possible.
 
-The ordering procedure described above works straight forward unless there are
+The ordering procedure described above works straightforward unless there are
 combinational logic constructs that are circularly dependent (a.k.a.: the
 UNOPTFLAT warning). Combinational scheduling loops can arise in sound
 (realizable) circuits as Verilator considers each SystemVerilog process as a
@@ -369,7 +369,7 @@ To achieve this, ``V3Sched::schedule`` calls ``V3Sched::breakCycles``, which
 builds a dependency graph of all combinational logic in the design, and then
 breaks all combinational cycles by converting all combinational logic that
 consumes a variable driven via a 'back-edge' into hybrid logic. Here
-'back-edge' just means a graph edge that points from a higher rank vertex to a
+'back-edge' just means a graph edge that points from a higher-rank vertex to a
 lower rank vertex in some consistent ranking of the directed graph. Variables
 driven via a back-edge in the dependency graph are marked, and all
 combinational logic that depends on such variables is converted into hybrid
@@ -382,7 +382,7 @@ logic, with two exceptions:
 - Explicit sensitivities of hybrid logic are ignored for the purposes of
   data-flow ordering with respect to other combinational or hybrid logic. I.e.:
   an explicit sensitivity suppresses the implicit sensitivity on the same
-  variable. This cold also be interpreted as ordering the hybrid logic as if
+  variable. This could also be interpreted as ordering the hybrid logic as if
   all variables listed as explicit sensitivities were substituted as constants
   with their current values.
 
@@ -396,7 +396,7 @@ explicit sensitivities are triggered.
 
 The effect of this transformation is that ``V3Order`` can proceed as if there
 are no combinational cycles (or alternatively, under the assumption that the
-back-edge driven variables don't change during one evaluation pass). The
+back-edge-driven variables don't change during one evaluation pass). The
 evaluation loop invoking the ordered code, will then re-invoke it on a follow
 on iteration, if any of the explicit sensitivities of hybrid logic have
 actually changed due to the previous invocation, iterating until all the
@@ -422,8 +422,8 @@ combinationally driven variables are consistent with the combinational logic.
 
 To achieve this, we invoke ``V3Order::order`` on all of the combinational and
 hybrid logic, and iterate the resulting evaluation function until no more
-hybrid logic is triggered. This yields the `_eval_settle` function which is
-invoked at the beginning of simulation, after the `_eval_initial`.
+hybrid logic is triggered. This yields the `_eval_settle` function, which is
+invoked at the beginning of simulation after the `_eval_initial`.
 
 
 Partitioning logic for correct NBA updates
@@ -432,17 +432,17 @@ Partitioning logic for correct NBA updates
 ``V3Order`` can order logic corresponding to non-blocking assignments (NBAs) to
 yield correct simulation results, as long as all the sensitivity expressions of
 clocked logic triggered in the Active scheduling region of the current time
-step are known up front. I.e.: the ordering of NBA updates is only correct if
+step are known up front. I.e., the ordering of NBA updates is only correct if
 derived clocks that are computed in an Active region update (that is, via a
 blocking or continuous assignment) are known up front.
 
 We can ensure this by partitioning the logic into two regions. Note these
-regions are a concept of the Verilator scheduling algorithm and they do not
+regions are a concept of the Verilator scheduling algorithm, and they do not
 directly correspond to the similarly named SystemVerilog scheduling regions
 as defined in the standard:
 
 - All logic (clocked, combinational and hybrid) that transitively feeds into,
-  or drives, via a non-blocking or continuous assignments (or via any update
+  or drives via a non-blocking or continuous assignments (or via any update
   that SystemVerilog executes in the Active scheduling region), a variable that
   is used in the explicit sensitivity list of some clocked or hybrid logic, is
   assigned to the 'act' region.
@@ -450,10 +450,10 @@ as defined in the standard:
 - All other logic is assigned to the 'nba' region.
 
 For completeness, note that a subset of the 'act' region logic, specifically,
-the logic related to the pre-assignments of NBA updates (i.e.: AstAssignPre
+the logic related to the pre-assignments of NBA updates (i.e., AstAssignPre
 nodes), is handled separately, but is executed as part of the 'act' region.
 
-Also note that all logic representing the committing of an NBA (i.e.: Ast*Post)
+Also note that all logic representing the committing of an NBA (i.e., Ast*Post)
 nodes) will be in the 'nba' region. This means that the evaluation of the 'act'
 region logic will not commit any NBA updates. As a result, the 'act' region
 logic can be iterated to compute all derived clock signals up front.
@@ -462,7 +462,7 @@ The correspondence between the SystemVerilog Active and NBA scheduling regions,
 and the internal 'act' and 'nba' regions, is that 'act' contains all Active
 region logic that can compute a clock signal, while 'nba' contains all other
 Active and NBA region logic. For example, if the only clocks in the design are
-top level inputs, then 'act' will be empty, and 'nba' will contain the whole of
+top-level inputs, then 'act' will be empty, and 'nba' will contain the whole of
 the design.
 
 The partitioning described above is performed by ``V3Sched::partition``.
@@ -475,10 +475,10 @@ We will separately invoke ``V3Order::order`` on the 'act' and 'nba' region
 logic.
 
 Combinational logic that reads variables driven from both 'act' and 'nba'
-region logic has the problem of needing to be re-evaluated even if only one of
+region logic has the problem of needing to be reevaluated even if only one of
 the regions updates an input variable. We could pass additional trigger
 expressions between the regions to make sure combinational logic is always
-re-evaluated, or we can replicate combinational logic that is driven from
+reevaluated, or we can replicate combinational logic that is driven from
 multiple regions, by copying it into each region that drives it. Experiments
 show this simple replication works well performance-wise (and notably
 ``V3Combine`` is good at combining the replicated code), so this is what we do
@@ -506,7 +506,7 @@ the top level `_eval` function, which on the high level has the form:
 
 ::
   void _eval() {
-    // Update combinational logic dependent on top level inptus ('ico' region)
+    // Update combinational logic dependent on top level inputs ('ico' region)
     while (true) {
       _eval__triggers__ico();
       // If no 'ico' region trigger is active
@@ -534,7 +534,7 @@ the top level `_eval` function, which on the high level has the form:
       // If no 'nba' region trigger is active
       if (!nba_triggers.any()) break;
 
-      // Evaluate all other Active region logic, and commti NBAs
+      // Evaluate all other Active region logic, and commit NBAs
       _eval_nba();
     }
   }
@@ -628,7 +628,7 @@ coroutines ``co_await`` its ``join`` function, and forked ones call ``done``
 when they're finished. Once the required number of coroutines (set using
 ``setCounter``) finish execution, the forking coroutine is resumed.
 
-Awaitable utilities
+Awaitable Utilities
 ^^^^^^^^^^^^^^^^^^^
 
 There are also two small utility awaitable types:
@@ -639,7 +639,7 @@ There are also two small utility awaitable types:
 * ``VlForever`` is used for blocking a coroutine forever. See the `Timing pass`
   section for more detail.
 
-Timing pass
+Timing Pass
 ^^^^^^^^^^^
 
 The visitor in ``V3Timing.cpp`` transforms each timing control into a ``co_await``.
@@ -668,7 +668,7 @@ before them and stored in temporary variables.
 and then await changes in variables used in the condition. If the condition is
 always false, the ``wait`` statement is replaced by a ``co_await`` on a
 ``VlForever``. This is done instead of a return in case the ``wait`` is deep in
-a call stack (otherwise the coroutine's caller would continue execution).
+a call stack (otherwise, the coroutine's caller would continue execution).
 
 Each sub-statement of a ``fork`` is put in an ``AstBegin`` node for easier
 grouping. In a later step, each of these gets transformed into a new, separate
@@ -748,7 +748,7 @@ doesn't suspend the forking process.
 
 In forked processes, references to local variables are only allowed in
 ``fork..join``, as this is the only case that ensures the lifetime of these
-locals is at least as long as the execution of the forked processes. This is
+locals are at least as long as the execution of the forked processes. This is
 where ``VlNow`` is used, to ensure the locals are moved to the heap before they
 are passed by reference to the forked processes.
 
@@ -770,7 +770,7 @@ graph, while maintaining as much available parallelism as possible. Often
 the partitioner can transform an input graph with millions of nodes into a
 coarsened execution graph with a few dozen nodes, while maintaining enough
 parallelism to take advantage of a modern multicore CPU. Runtime
-synchronization cost is not prohibitive with so few nodes.
+synchronization cost is reasonable with so few nodes.
 
 
 Partitioning
@@ -789,7 +789,7 @@ The available parallelism or "par-factor" of a DAG is the total cost to
 execute all nodes, divided by the cost to execute the longest critical path
 through the graph. This is the speedup you would get from running the graph
 in parallel, if given infinite CPU cores available and communication and
-synchronization are zero.
+synchronization is zero.
 
 
 Macro Task
@@ -847,7 +847,7 @@ synchronization costs.
 Verilator's cost estimates are assigned by ``InstrCountVisitor``.  This
 class is perhaps the most fragile piece of the multithread
 implementation. It's easy to have a bug where you count something cheap
-(eg. accessing one element of a huge array) as if it were expensive (eg.
+(e.g. accessing one element of a huge array) as if it were expensive (eg.
 by counting it as if it were an access to the entire array.) Even without
 such gross bugs, the estimates this produce are only loosely predictive of
 actual runtime cost. Multithread performance would be better with better
@@ -879,13 +879,13 @@ fragmentation.
 Locating Variables for Best Spatial Locality
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
-After scheduling all code, we attempt to locate variables in memory such
+After scheduling all code, we attempt to locate variables in memory, such
 that variables accessed by a single macro-task are close together in
 memory. This provides "spatial locality" - when we pull in a 64-byte cache
 line to access a 2-byte variable, we want the other 62 bytes to be ones
 we'll also likely access soon, for best cache performance.
 
-This turns out to be critical for performance. It should allow Verilator
+This is critical for performance. It should allow Verilator
 to scale to very large models. We don't rely on our working set fitting
 in any CPU cache; instead we essentially "stream" data into caches from
 memory. It's not literally streaming, where the address increases
@@ -904,7 +904,7 @@ The footprint ordering is literally the traveling salesman problem, and
 we use a TSP-approximation algorithm to get close to an optimal sort.
 
 This is an old idea. Simulators designed at DEC in the early 1990s used
-similar techniques to optimize both single-thread and multi-thread
+similar techniques to optimize both single-thread and multithread
 modes. (Verilator does not optimize variable placement for spatial
 locality in serial mode; that is a possible area for improvement.)
 
@@ -918,7 +918,7 @@ Wave Scheduling
 
 To allow the Verilated model to run in parallel with the testbench, it
 might be nice to support "wave" scheduling, in which work on a cycle begins
-before ``eval()`` is called or continues after ``eval()`` returns. For now
+before ``eval()`` is called or continues after ``eval()`` returns. For now,
 all work on a cycle happens during the ``eval()`` call, leaving Verilator's
 threads idle while the testbench (everything outside ``eval()``) is
 working. This would involve fundamental changes within the partitioner,
@@ -929,7 +929,7 @@ Efficient Dynamic Scheduling
 """"""""""""""""""""""""""""
 
 To scale to more than a few threads, we may revisit a fully dynamic
-scheduler. For large (>16 core) systems it might make sense to dedicate an
+scheduler. For large (>16 core) systems, it might make sense to dedicate an
 entire core to scheduling, so that scheduler data structures would fit in
 its L1 cache and thus the cost of traversing priority-ordered ready lists
 would not be prohibitive.
@@ -983,7 +983,7 @@ Performance Regression
 """"""""""""""""""""""
 
 It would be nice if we had a regression of large designs, with some
-diversity of design styles, to test on both single- and multi-threaded
+diversity of design styles, to test on both single- and multithreaded
 modes. This would help to avoid performance regressions, and also to
 evaluate the optimizations while minimizing the impact of parasitic noise.
 
@@ -992,7 +992,7 @@ Per-Instance Classes
 """"""""""""""""""""
 
 If we have multiple instances of the same module, and they partition
-differently (likely; we make no attempt to partition them the same) then
+differently (likely; we make no attempt to partition them the same), then
 the variable sort will be suboptimal for either instance. A possible
 improvement would be to emit an unique class for each instance of a module,
 and sort its variables optimally for that instance's code stream.
@@ -1011,17 +1011,17 @@ until all signals are stable.
 On other evaluations, the Verilated code detects what input signals have
 changes. If any are clocks, it calls the appropriate sequential functions
 (from ``always @ posedge`` statements). Interspersed with sequential
-functions it calls combo functions (from ``always @*``).  After this is
+functions, it calls combo functions (from ``always @*``).  After this is
 complete, it detects any changes due to combo loops or internally generated
 clocks, and if one is found must reevaluate the model again.
 
 For SystemC code, the ``eval()`` function is wrapped in a SystemC
-``SC_METHOD``, sensitive to all inputs. (Ideally it would only be sensitive
+``SC_METHOD``, sensitive to all inputs. (Ideally, it would only be sensitive
 to clocks and combo inputs, but tracing requires all signals to cause
 evaluation, and the performance difference is small.)
 
 If tracing is enabled, a callback examines all variables in the design for
-changes, and writes the trace for each change. To accelerate this process
+changes, and writes the trace for each change. To accelerate this process,
 the evaluation process records a bitmask of variables that might have
 changed; if clear, checking those signals for changes may be skipped.
 
@@ -1045,7 +1045,7 @@ is appreciated if you could match our style:
 
 - Use "mixedCapsSymbols" instead of "underlined_symbols".
 
-- Uas a "p" suffix on variables that are pointers, e.g. "nodep".
+- Use a "p" suffix on variables that are pointers, e.g., "nodep".
 
 - Comment every member variable.
 
@@ -1057,12 +1057,12 @@ using clang-format version 10.0.0, and yapf for python, and is
 automatically corrected in the CI actions. For those manually formatting C
 code:
 
-- Use 4 spaces per level, and no tabs.
+- Use four spaces per level, and no tabs.
 
-- Use 2 spaces between the end of source and the beginning of a
+- Use two spaces between the end of source and the beginning of a
   comment.
 
-- Use 1 space after if/for/switch/while and similar keywords.
+- Use one space after if/for/switch/while and similar keywords.
 
 - No spaces before semicolons, nor between a function's name and open
   parenthesis (only applies to functions; if/else has a following space).
@@ -1073,8 +1073,8 @@ The ``astgen`` Script
 
 The ``astgen`` script is used to generate some of the repetitive C++ code
 related to the ``AstNode`` type hierarchy. An example is the abstract ``visit``
-methods in ``VNVisitor``. There are other uses, please see the ``*__gen*``
-files in the bulid directories and the ``astgen`` script itself for details.  A
+methods in ``VNVisitor``. There are other uses; please see the ``*__gen*``
+files in the bulid directories and the ``astgen`` script for details.  A
 description of the more advanced features of ``astgen`` are provided here.
 
 
@@ -1099,7 +1099,7 @@ sub-class definitions are parsed and contribute to the code generated by
 ``astgen``. The general syntax is ``@astgen <keywords> := <description>``,
 where ``<keywords>`` determines what is being defined, and ``<description>`` is
 a ``<keywords>`` dependent description of the definition. The list of
-``@astgen`` directives is as follows:
+``@astgen`` directives are as follows:
 
 
 ``op<N>`` operand  directives
@@ -1128,7 +1128,7 @@ An example of the full syntax of the directive is
 
 ``astnode`` generates accessors for the child nodes based on these directives.
 For non-list children, the names of the getter and setter both are that of the
-given ``<identifier>``. For list type children, the getter is ``<identifier>``,
+given ``<identifier>``. For list-type children, the getter is ``<identifier>``,
 and instead of the setter, there an ``add<Identifier>`` method is generated
 that appends new nodes (or lists of nodes) to the child list.
 
@@ -1185,10 +1185,10 @@ and applies the visit method of the ``VNVisitor`` to the invoking AstNode
 instance (i.e. ``this``).
 
 One possible difficulty is that a call to ``accept`` may perform an edit
-which destroys the node it receives as argument. The
+which destroys the node it receives as an argument. The
 ``acceptSubtreeReturnEdits`` method of ``AstNode`` is provided to apply
 ``accept`` and return the resulting node, even if the original node is
-destroyed (if it is not destroyed it will just return the original node).
+destroyed (if it is not destroyed, it will just return the original node).
 
 The behavior of the visitor classes is achieved by overloading the
 ``visit`` function for the different ``AstNode`` derived classes. If a
@@ -1212,7 +1212,7 @@ There are three ways data is passed between visitor functions.
    it's cleared. Children under an ``AstModule`` will see it set, while
    nodes elsewhere will see it clear. If there can be nested items (for
    example an ``AstFor`` under an ``AstFor``) the variable needs to be
-   save-set-restored in the ``AstFor`` visitor, otherwise exiting the
+   save-set-restored in the ``AstFor`` visitor; otherwise exiting the
    lower for will lose the upper for's setting.
 
 2. User attributes. Each ``AstNode`` (**Note.** The AST node, not the
@@ -1243,14 +1243,14 @@ There are three ways data is passed between visitor functions.
    These comments are important to make sure a ``user#()`` on a given
    ``AstNode`` type is never being used for two different purposes.
 
-   Note that calling ``user#ClearTree`` is fast, it doesn't walk the
+   Note that calling ``user#ClearTree`` is fast; it doesn't walk the
    tree, so it's ok to call fairly often. For example, it's commonly
    called on every module.
 
 3. Parameters can be passed between the visitors in close to the
    "normal" function caller to callee way. This is the second ``vup``
    parameter of type ``AstNUser`` that is ignored on most of the visitor
-   functions. V3Width does this, but it proved more messy than the above
+   functions. V3Width does this, but it proved messier than the above
    and is deprecated. (V3Width was nearly the first module written.
    Someday this scheme may be removed, as it slows the program down to
    have to pass vup everywhere.)
@@ -1305,7 +1305,7 @@ change. For example:
    iterateAndNextNull(nodep->lhsp());
 
 Will work fine, as even if the first iterate causes a new node to take
-the place of the ``lhsp()``, that edit will update ``nodep->lhsp()`` and
+the place of the ``lhsp()``, that edit will update ``nodep->lhsp()``, and
 the second call will correctly see the change. Alternatively:
 
 ::
@@ -1318,8 +1318,8 @@ the second call will correctly see the change. Alternatively:
 
 This will cause bugs or a core dump, as lp is a dangling pointer. Thus
 it is advisable to set lhsp=NULL shown in the \*'s above to make sure
-these dangles are avoided. Another alternative used in special cases
-mostly in V3Width is to use acceptSubtreeReturnEdits, which operates on
+these dangles are avoided. Another alternative used in special cases,
+mostly in V3Width, is to use acceptSubtreeReturnEdits, which operates on
 a single node and returns the new pointer if any. Note
 acceptSubtreeReturnEdits does not follow ``nextp()`` links.
 
@@ -1332,7 +1332,7 @@ Identifying Derived Classes
 ---------------------------
 
 A common requirement is to identify the specific ``AstNode`` class we
-are dealing with. For example a visitor might not implement separate
+are dealing with. For example, a visitor might not implement separate
 ``visit`` methods for ``AstIf`` and ``AstGenIf``, but just a single
 method for the base class:
 
@@ -1355,7 +1355,7 @@ use:
 Additionally the ``VN_CAST`` method converts pointers similar to C++
 ``dynamic_cast``. This either returns a pointer to the object cast to
 that type (if it is of class ``SOMETYPE``, or a derived class of
-``SOMETYPE``) or else NULL. (However, for true/false tests use ``VN_IS``
+``SOMETYPE``) or else NULL. (However, for true/false tests, use ``VN_IS``
 as that is faster.)
 
 
@@ -1364,13 +1364,13 @@ as that is faster.)
 Testing
 =======
 
-For an overview of how to write a test see the BUGS section of the
+For an overview of how to write a test, see the BUGS section of the
 `Verilator Manual <https://verilator.org/verilator_doc.html>`_.
 
 It is important to add tests for failures as well as success (for
 example to check that an error message is correctly triggered).
 
-Tests that fail should by convention have the suffix ``_bad`` in their
+Tests that fail should, by convention have the suffix ``_bad`` in their
 name, and include ``fails = 1`` in either their ``compile`` or
 ``execute`` step as appropriate.
 
@@ -1378,11 +1378,11 @@ name, and include ``fails = 1`` in either their ``compile`` or
 Preparing to Run Tests
 ----------------------
 
-For all tests to pass you must install the following packages:
+For all tests to pass, you must install the following packages:
 
 -  SystemC to compile the SystemC outputs, see http://systemc.org
 
--  Parallel::Forker from CPAN to run tests in parallel, you can install
+-  Parallel::Forker from CPAN to run tests in parallel; you can install
    this with e.g. "sudo cpan install Parallel::Forker".
 
 -  vcddiff to find differences in VCD outputs. See the readme at
@@ -1417,9 +1417,9 @@ This can be changed using the ``top_filename`` subroutine, for example
 
    top_filename("t/t_myothertest.v");
 
-By default all tests will run with major simulators (Icarus Verilog, NC,
-VCS, ModelSim, etc) as well as Verilator, to allow results to be
-compared. However if you wish a test only to be used with Verilator, you
+By default, all tests will run with major simulators (Icarus Verilog, NC,
+VCS, ModelSim, etc.) as well as Verilator, to allow results to be
+compared. However, if you wish a test only to be used with Verilator, you
 can use the following:
 
 ::
@@ -1435,7 +1435,7 @@ Of the many options that can be set through arguments to ``compiler`` and
 ``fails``
   Set to 1 to indicate that the compilation or execution is intended to fail.
 
-For example the following would specify that compilation requires two
+For example, the following would specify that compilation requires two
 defines and is expected to fail.
 
 ::
@@ -1452,15 +1452,15 @@ Regression Testing for Developers
 Developers will also want to call ./configure with two extra flags:
 
 ``--enable-ccwarn``
-   Causes the build to stop on warnings as well as errors. A good way to
-   ensure no sloppy code gets added, however it can be painful when it
+   This causes the build to stop on warnings as well as errors. A good way
+   to ensure no sloppy code gets added; however it can be painful when it
    comes to testing, since third party code used in the tests (e.g.
    SystemC) may not be warning free.
 
 ``--enable-longtests``
    In addition to the standard C, SystemC examples, also run the tests
    in the ``test_regress`` directory when using *make test*'. This is
-   disabled by default as SystemC installation problems would otherwise
+   disabled by default, as SystemC installation problems would otherwise
    falsely indicate a Verilator problem.
 
 When enabling the long tests, some additional PERL modules are needed,
@@ -1477,7 +1477,7 @@ There are some traps to avoid when running regression tests
 
 - Not all Linux systems install Perldoc by default. This is needed for the
   ``--help`` option to Verilator, and also for regression testing.  This
-  can be installed using cpan:
+  can be installed using CPAN:
 
   ::
 
@@ -1489,8 +1489,8 @@ There are some traps to avoid when running regression tests
 
 - Running regression may exhaust resources on some Linux systems,
   particularly file handles and user processes. Increase these to
-  respectively 16,384 and 4,096. The method of doing this is system
-  dependent, but on Fedora Linux it would require editing the
+  respectively 16,384 and 4,096. The method of doing this is
+  system-dependent, but on Fedora Linux it would require editing the
   ``/etc/security/limits.conf`` file as root.
 
 
@@ -1510,7 +1510,7 @@ Continuous Integration
 
 Verilator uses GitHub Actions which automatically tests the master branch
 for test failures on new commits. It also runs a daily cron job to validate
-all of the tests against different OS and compiler versions.
+all tests against different OS and compiler versions.
 
 Developers can enable Actions on their GitHub repository so that the CI
 environment can check their branches too by enabling the build workflow:
@@ -1555,7 +1555,7 @@ debug level 5, with the V3Width.cpp file at level 9.
 --debug
 -------
 
-When you run with ``--debug`` there are two primary output file types
+When you run with ``--debug``, there are two primary output file types
 placed into the obj_dir, .tree and .dot files.
 
 
@@ -1572,7 +1572,7 @@ output, for example:
    dot -Tps -o ~/a.ps obj_dir/Vtop_foo.dot
 
 You can then print a.ps. You may prefer gif format, which doesn't get
-scaled so can be more useful with large graphs.
+scaled so it can be more useful with large graphs.
 
 For interactive graph viewing consider `xdot
 <https://github.com/jrfonseca/xdot.py>`__ or `ZGRViewer
@@ -1617,21 +1617,21 @@ field in the section below.
 +---------------+--------------------------------------------------------+
 | ``w32``       | The data-type width() is 32 bits.                      |
 +---------------+--------------------------------------------------------+
-| ``out_wide``  | The name() of the node, in this case the name of the   |
+| ``out_wide``  | The name() of the node, in this case, the name of the  |
 |               | variable.                                              |
 +---------------+--------------------------------------------------------+
 | ``[O]``       | Flags which vary with the type of node, in this        |
-|               | case it means the variable is an output.               |
+|               | case, it means the variable is an output.              |
 +---------------+--------------------------------------------------------+
 
-In more detail the following fields are dumped common to all nodes. They
+In more detail, the following fields are dumped common to all nodes. They
 are produced by the ``AstNode::dump()`` method:
 
 Tree Hierarchy
    The dump lines begin with numbers and colons to indicate the child
    node hierarchy. As noted above, ``AstNode`` has lists of items at the
    same level in the AST, connected by the ``nextp()`` and ``prevp()``
-   pointers. These appear as nodes at the same level. For example after
+   pointers. These appear as nodes at the same level. For example, after
    inlining:
 
    ::
@@ -1655,20 +1655,20 @@ Address of the node
    with the debugger. If the actual address values are not important,
    then using the ``--dump-tree-addrids`` option will convert address
    values to short identifiers of the form ``([A-Z]*)``, which is
-   hopefully easier for the reader to cross reference throughout the
+   hopefully easier for the reader to cross-reference throughout the
    dump.
 
 Last edit number
    Of the form ``<ennnn>`` or ``<ennnn#>`` , where ``nnnn`` is the
    number of the last edit to modify this node. The trailing ``#``
-   indicates the node has been edited since the last tree dump (which
-   typically means in the last refinement or optimization pass). GDB can
-   watch for this, see << /Debugging >>.
+   indicates the node has been edited since the last tree dump
+   (typically in the last refinement or optimization pass). GDB can
+   watch for this; see << /Debugging >>.
 
 Source file and line
    Of the form ``{xxnnnn}``, where C{xx} is the filename letter (or
    letters) and ``nnnn`` is the line number within that file. The first
-   file is ``a``, the 26th is ``z``, the 27th is ``aa`` and so on.
+   file is ``a``, the 26th is ``z``, the 27th is ``aa``, and so on.
 
 User pointers
    Shows the value of the node's user1p...user5p, if non-NULL.
@@ -1683,7 +1683,7 @@ Data type
 
    -  ``s`` if the node is signed.
 
-   -  ``d`` if the node is a double (i.e a floating point entity).
+   -  ``d`` if the node is a double (i.e. a floating point entity).
 
    -  ``w`` always present, indicating this is the width field.
 
@@ -1693,9 +1693,9 @@ Data type
       width.
 
 Name of the entity represented by the node if it exists
-   For example for a ``VAR`` it is the name of the variable.
+   For example, for a ``VAR`` is the name of the variable.
 
-Many nodes follow these fields with additional node specific
+Many nodes follow these fields with additional node-specific
 information. Thus the ``VARREF`` node will print either ``[LV]`` or
 ``[RV]`` to indicate a left value or right value, followed by the node
 of the variable being referred to. For example:
@@ -1710,7 +1710,7 @@ type in question to determine additional fields that may be printed.
 The ``MODULE`` has a list of ``CELLINLINE`` nodes referred to by its
 ``op1p()`` pointer, connected by ``nextp()`` and ``prevp()`` pointers.
 
-Similarly the ``NETLIST`` has a list of modules referred to by its
+Similarly, the ``NETLIST`` has a list of modules referred to by its
 ``op1p()`` pointer.
 
 
@@ -1728,7 +1728,7 @@ Debugging with GDB
 ------------------
 
 The test_regress/driver.pl script accepts ``--debug --gdb`` to start
-Verilator under gdb and break when an error is hit or the program is about
+Verilator under gdb and break when an error is hit, or the program is about
 to exit. You can also use ``--debug --gdbbt`` to just backtrace and then
 exit gdb. To debug the Verilated executable, use ``--gdbsim``.
 
@@ -1805,7 +1805,7 @@ backtrace. You will typically see a frame sequence something like:
 Adding a New Feature
 ====================
 
-Generally what would you do to add a new feature?
+Generally, what would you do to add a new feature?
 
 1. File an issue (if there isn't already) so others know what you're
    working on.
@@ -1823,7 +1823,7 @@ Generally what would you do to add a new feature?
    Ordering of definitions is enforced by ``astgen``.
 
 5. Now you can run "test_regress/t/t_<newtestcase>.pl --debug" and it'll
-   probably fail but you'll see a
+   probably fail, but you'll see a
    "test_regress/obj_dir/t_<newtestcase>/*.tree" file which you can examine
    to see if the parsing worked. See also the sections above on debugging.
 
@@ -1833,12 +1833,12 @@ Generally what would you do to add a new feature?
 Adding a New Pass
 -----------------
 
-For more substantial changes you may need to add a new pass. The simplest
+For more substantial changes, you may need to add a new pass. The simplest
 way to do this is to copy the ``.cpp`` and ``.h`` files from an existing
 pass. You'll need to add a call into your pass from the ``process()``
 function in ``src/verilator.cpp``.
 
-To get your pass to build you'll need to add its binary filename to the
+To get your pass to build, you'll need to add its binary filename to the
 list in ``src/Makefile_obj.in`` and reconfigure.
 
 
@@ -1854,11 +1854,9 @@ IEEE 1800-2017 3.3 modules within modules
 IEEE 1800-2017 6.12 "shortreal"
     Little/no tool support, and easily promoted to real.
 IEEE 1800-2017 11.11 Min, typ, max
-    No SDF support so will always use typical.
+    No SDF support, so will always use typical.
 IEEE 1800-2017 11.12 "let"
-    Little/no tool support, makes difficult to implement parsers.
-IEEE 1800-2017 20.15 Probabilistic functions
-    Little industry use.
+    Little/no tool support, makes it difficult to implement parsers.
 IEEE 1800-2017 20.16 Stochastic analysis
     Little industry use.
 IEEE 1800-2017 20.17 PLA modeling

From b6cdae30f6b9dc9eef44a73831db5687ccbcd864 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 10 Dec 2022 20:09:47 -0500
Subject: [PATCH 138/156] docs: Fix grammar.

---
 bin/verilator                          |  16 +-
 ci/docker/run/README.rst               |   5 +-
 docs/guide/contributors.rst            |  29 +-
 docs/guide/environment.rst             |   8 +-
 docs/guide/example_binary.rst          |  10 +-
 docs/guide/example_cc.rst              |  15 +-
 docs/guide/exe_verilator.rst           | 503 +++++++++++-----------
 docs/guide/exe_verilator_coverage.rst  |  35 +-
 docs/guide/exe_verilator_gantt.rst     |  23 +-
 docs/guide/exe_verilator_profcfunc.rst |   8 +-
 docs/guide/extensions.rst              | 157 ++++---
 docs/guide/faq.rst                     | 156 +++----
 docs/guide/files.rst                   |  10 +-
 docs/guide/install.rst                 |  34 +-
 docs/guide/languages.rst               | 155 ++++---
 docs/guide/overview.rst                |  12 +-
 docs/guide/simulating.rst              | 231 +++++-----
 docs/guide/verilating.rst              | 164 ++++---
 docs/guide/warnings.rst                | 574 +++++++++++++------------
 docs/spelling.txt                      |   3 +
 20 files changed, 1072 insertions(+), 1076 deletions(-)

diff --git a/bin/verilator b/bin/verilator
index c78b8c2d5..be1156d0f 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -287,7 +287,7 @@ detailed descriptions of these arguments.
 
 =for VL_SPHINX_EXTRACT "_build/gen/args_verilator.rst"
 
-    <file.v>                    Verilog package, module and top module filenames
+    <file.v>                    Verilog package, module, and top module filenames
     <file.c/cc/cpp>             Optional C++ files to compile in
     <file.a/o/so>               Optional C++ files to link in
 
@@ -379,7 +379,7 @@ detailed descriptions of these arguments.
     --MP                        Create phony dependency targets
      +notimingchecks            Ignored
      -O0                        Disable optimizations
-     -O3                        High performance optimizations
+     -O3                        High-performance optimizations
      -O<optimization-letter>    Selectable optimizations
      -o <executable>            Name of final executable
     --no-order-clock-delay      Disable ordering clock enable assignments
@@ -387,14 +387,14 @@ detailed descriptions of these arguments.
     --output-split-cfuncs <statements>   Split model functions
     --output-split-ctrace <statements>   Split tracing functions
      -P                         Disable line numbers and blanks with -E
-    --pins-bv <bits>            Specify types for top level ports
-    --pins-sc-biguint           Specify types for top level ports
-    --pins-sc-uint              Specify types for top level ports
-    --pins-uint8                Specify types for top level ports
+    --pins-bv <bits>            Specify types for top-level ports
+    --pins-sc-biguint           Specify types for top-level ports
+    --pins-sc-uint              Specify types for top-level ports
+    --pins-uint8                Specify types for top-level ports
     --no-pins64                 Don't use uint64_t's for 33-64 bit sigs
     --pipe-filter <command>     Filter all input through a script
     --pp-comments               Show preprocessor comments with -E
-    --prefix <topname>          Name of top level class
+    --prefix <topname>          Name of top-level class
     --private                   Debugging; see docs
     --prof-c                    Compile C++ code with profiling
     --prof-cfuncs               Name functions for profiling
@@ -426,7 +426,7 @@ detailed descriptions of these arguments.
     --timescale <timescale>     Sets default timescale
     --timescale-override <timescale>  Overrides all timescales
     --top <topname>             Alias of --top-module
-    --top-module <topname>      Name of top level input module
+    --top-module <topname>      Name of top-level input module
     --trace                     Enable waveform creation
     --trace-coverage            Enable tracing of coverage
     --trace-depth <levels>      Depth of tracing
diff --git a/ci/docker/run/README.rst b/ci/docker/run/README.rst
index ccd5709a7..dd778f4fb 100644
--- a/ci/docker/run/README.rst
+++ b/ci/docker/run/README.rst
@@ -62,12 +62,11 @@ Internals
 ---------
 
 The Dockerfile builds Verilator and removes the tree when completed to
-reduce the image size. The entrypoint is set as a wrapper script
+reduce the image size. The entrypoint is a wrapper script
 (``verilator-wrap.sh``). That script 1. calls Verilator, and 2. copies the
 Verilated runtime files to the ``obj_dir`` or the ``-Mdir``
 respectively. This allows the user to have the files to they may later
 build the C++ output with the matching runtime files. The wrapper also
 patches the Verilated Makefile accordingly.
 
-There is also a hook defined that is run by docker hub via automated
-builds.
+A hook is also defined and run by Docker Hub via automated builds.
diff --git a/docs/guide/contributors.rst b/docs/guide/contributors.rst
index 3d82e0b62..b743bddc5 100644
--- a/docs/guide/contributors.rst
+++ b/docs/guide/contributors.rst
@@ -11,7 +11,7 @@ Authors
 When possible, please instead report bugs at `Verilator Issues
 <https://verilator.org/issues>`_.
 
-Primary author is Wilson Snyder <wsnyder@wsnyder.org>.
+The primary author is Wilson Snyder <wsnyder@wsnyder.org>.
 
 Major concepts by Paul Wasson, Duane Galbi, John Coiner, Geza Lore, Yutetsu
 Takatsukasa, and Jie Xu.
@@ -22,18 +22,18 @@ Contributors
 
 Many people have provided ideas and other assistance with Verilator.
 
-Verilator is receiving major development support from the `CHIPS Alliance
-<https://chipsalliance.org>`_, `Antmicro Ltd <https://antmicro.com>`_ and
-`Shunyao CAD <https://shunyaocad.com>`_.
+Verilator is receiving significant development support from the `CHIPS
+Alliance <https://chipsalliance.org>`_, `Antmicro Ltd
+<https://antmicro.com>`_ and `Shunyao CAD <https://shunyaocad.com>`_.
 
 Previous major corporate sponsors of Verilator, by providing significant
-contributions of time or funds included include: Atmel Corporation, Cavium
+contributions of time or funds include: Atmel Corporation, Cavium
 Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd.,
 Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune
 Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc.,
 SiCortex Inc, and Shunyao CAD.
 
-The people who have contributed major functionality are: Krzysztof
+The contributors of major functionality are: Krzysztof
 Bieganski, Byron Bradley, Jeremy Bennett, Lane Brooks, John Coiner, Duane
 Galbi, Geza Lore, Todd Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu,
 and Wilson Snyder.  Major testers included Jeff Dutton, Jonathon Donaldson,
@@ -129,8 +129,9 @@ Jeff Winston, Joshua Wise, Clifford Wolf, Tobias Wolfel, Johan Wouters,
 Paul Wright, Junyi Xi, Ding Xiaoliang, Jie Xu, Mandy Xu, Yinan Xu, Luke
 Yang, Amir Yazdanbakhsh, Keyi Zhang, and Xi Zhang.
 
-Thanks to them, and all those we've missed including above, or wished to
-remain anonymous.
+Thanks to them, and all those we've missed mentioning above, and to those
+whom have wished to remain anonymous.
+
 
 Historical Origins
 ==================
@@ -140,10 +141,10 @@ Digital Equipment Corporation.  The Verilog code that was converted to C
 was then merged with a C-based CPU model of the Alpha processor and
 simulated in a C-based environment called CCLI.
 
-In 1995 Verilator started being also used for Multimedia and Network
-Processor development inside Digital.  Duane Galbi took over the active
-development of Verilator, and added several performance enhancements.  CCLI
-was still being used as the shell.
+In 1995 Verilator started being used for Multimedia and Network Processor
+development inside Digital.  Duane Galbi took over the active development
+of Verilator, and added several performance enhancements, and CCLI was
+still being used as the shell.
 
 In 1998, through the efforts of existing DECies, mainly Duane Galbi,
 Digital graciously agreed to release the source code.  (Subject to the code
@@ -168,5 +169,5 @@ fork/join, delay handling, DFG performance optimizations, and other
 improvements.
 
 Currently, various language features and performance enhancements are added
-as the need arises, with a focus on getting to complete Universal
-Verification Methodology (UVM, IEEE 1800.2-2017) support.
+as the need arises, focusing on completing Universal Verification
+Methodology (UVM, IEEE 1800.2-2017) support.
diff --git a/docs/guide/environment.rst b/docs/guide/environment.rst
index 99c283e6b..99ef9767c 100644
--- a/docs/guide/environment.rst
+++ b/docs/guide/environment.rst
@@ -10,7 +10,7 @@ associated programs.
 .. option:: LD_LIBRARY_PATH
 
    A generic Linux/OS variable specifying what directories have shared
-   object (.so) files.  This path should include SystemC and any other
+   object (.so) files.  This path should include SystemC and other
    shared objects needed at simulation runtime.
 
 .. option:: MAKE
@@ -54,14 +54,14 @@ associated programs.
 
 .. option:: SYSTEMC_INCLUDE
 
-   If set, specifies the directory containing the systemc.h header file. If
-   not specified, it will come from a default optionally specified at
+   If set, specifies the directory containing the systemc.h header file.
+   If not specified, it will come from a default optionally specified at
    configure time (before Verilator was compiled), or computed from
    SYSTEMC/include.
 
 .. option:: SYSTEMC_LIBDIR
 
-   If set, specifies the directory containing the libsystemc.a library. If
+   If set, specifies the directory containing the libsystemc.a library.  If
    not specified, it will come from a default optionally specified at
    configure time (before Verilator was compiled), or computed from
    SYSTEMC/lib-SYSTEMC_ARCH.
diff --git a/docs/guide/example_binary.rst b/docs/guide/example_binary.rst
index 0cb1514be..fbcda7e86 100644
--- a/docs/guide/example_binary.rst
+++ b/docs/guide/example_binary.rst
@@ -42,7 +42,7 @@ Breaking this command down:
 #. :vlopt:`-Wall` so Verilator has stronger lint warnings
    enabled.
 
-#. An finally, :command:`our.v` which is our SystemVerilog design file.
+#. An finally, :command:`our.v`, which is our SystemVerilog design file.
 
 And now we run it:
 
@@ -57,7 +57,7 @@ And we get as output:
      Hello World
      - our.v:2: Verilog $finish
 
-Really, you're better off using a Makefile to run the steps for you so when
-your source changes it will automatically run all of the appropriate steps.
-To aid this Verilator can create a makefile dependency file.  For examples
-that do this see the :file:`examples` directory in the distribution.
+You're better off using a Makefile to run the steps for you, so when your
+source changes, it will automatically run all of the appropriate steps.  To
+aid this, Verilator can create a makefile dependency file.  For examples
+that do this, see the :file:`examples` directory in the distribution.
diff --git a/docs/guide/example_cc.rst b/docs/guide/example_cc.rst
index 41280015b..bc4e578f2 100644
--- a/docs/guide/example_cc.rst
+++ b/docs/guide/example_cc.rst
@@ -12,7 +12,7 @@ of what this C++ code is doing, see
 
 .. include:: example_common_install.rst
 
-Now, let's create an example Verilog, and C++ wrapper file:
+Now, let's create an example Verilog and C++ wrapper file:
 
 .. code-block:: bash
 
@@ -39,7 +39,7 @@ Now, let's create an example Verilog, and C++ wrapper file:
        }
      EOF
 
-Now we run Verilator on our little example.
+Now we run Verilator on our little example;
 
 .. code-block:: bash
 
@@ -47,8 +47,7 @@ Now we run Verilator on our little example.
 
 Breaking this command down:
 
-#. :vlopt:`--cc` to get C++ output (versus e.g. SystemC
-   or only linting).
+#. :vlopt:`--cc` to get C++ output (versus e.g., SystemC, or only linting).
 
 #. :vlopt:`--exe`, along with our :command:`sim_main.cpp` wrapper file, so
    the build will create an executable instead of only a library.
@@ -89,7 +88,7 @@ And we get as output:
      Hello World
      - our.v:2: Verilog $finish
 
-Really, you're better off using a Makefile to run the steps for you so when
-your source changes it will automatically run all of the appropriate steps.
-To aid this Verilator can create a makefile dependency file.  For examples
-that do this see the :file:`examples` directory in the distribution.
+You're better off using a Makefile to run the steps for you, so when your
+source changes, it will automatically run all of the appropriate steps.  To
+aid this, Verilator can create a makefile dependency file.  For examples
+that do this, see the :file:`examples` directory in the distribution.
diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst
index 25534b23c..2ba344e72 100644
--- a/docs/guide/exe_verilator.rst
+++ b/docs/guide/exe_verilator.rst
@@ -4,8 +4,7 @@
 verilator Arguments
 ===================
 
-The following are the arguments that may be passed to the "verilator"
-executable.
+The following arguments may be passed to the "verilator" executable.
 
 Summary:
 
@@ -28,11 +27,11 @@ Summary:
 
 .. option:: <file.a/.o/.so>
 
-   Specifies optional object or library files to be linked in with the
+   Specifies optional object or library files to be linked with the
    Verilog code, as a shorthand for
    :vlopt:`-LDFLAGS \<file\> <-LDFLAGS>`. The file path should either be
-   absolute, or relative to where the make will be executed from, or add to
-   your makefile's VPATH the appropriate directory to find the file.
+   absolute, or relative to where the make will be executed from, or add
+   the appropriate directory to your makefile's VPATH to find the file.
 
    If any files are specified in this way, Verilator will include a make
    rule that uses these files when linking the module's executable.  This
@@ -79,8 +78,8 @@ Summary:
 
       ```begin_keywords`` is a SystemVerilog construct, which specifies
       *only* the set of keywords to be recognized. This also controls some
-      error messages that vary between language standards.  Note at present
-      Verilator tends to be overly permissive, e.g. it will accept many
+      error messages that vary between language standards.  At present,
+      Verilator tends to be overly permissive, e.g., it will accept many
       grammar and other semantic extensions which might not be legal when
       set to an older standard.
 
@@ -92,7 +91,7 @@ Summary:
 
    After every $display or $fdisplay, flush the output stream.  This
    ensures that messages will appear immediately but may reduce
-   performance. For best performance call :code:`fflush(stdout)`
+   performance. For best performance, call :code:`fflush(stdout)`
    occasionally in the C++ main loop.  Defaults to off, which will buffer
    output as provided by the normal C/C++ standard library IO.
 
@@ -101,8 +100,8 @@ Summary:
    Black box any unknown $system task or function calls.  System tasks will
    become no-operations, and system functions will be replaced with unsized
    zero.  Arguments to such functions will be parsed, but not otherwise
-   checked.  This prevents errors when linting in the presence of company
-   specific PLI calls.
+   checked.  This prevents errors when linting in the presence of
+   company-specific PLI calls.
 
    Using this argument will likely cause incorrect simulation.
 
@@ -110,7 +109,7 @@ Summary:
 
    Black box some unsupported language features, currently UDP tables, the
    cmos and tran gate primitives, deassign statements, and mixed edge
-   errors.  This may enable linting the rest of the design even when
+   errors.  This may enable linting of the rest of the design even when
    unsupported constructs are present.
 
    Using this argument will likely cause incorrect simulation.
@@ -133,10 +132,10 @@ Summary:
 
    Rarely needed.  When a dependency (.d) file is created, this filename
    will become a source dependency, such that a change in this binary will
-   have make rebuild the output files.  Defaults to the full path to the
-   Verilator binary.
+   have ``make`` rebuild the output files.  Defaults to the full path to
+   the Verilator binary.
 
-   This option was named `--bin` prior to version 4.228.
+   This option was named `--bin` before version 4.228.
 
 .. option:: --build-jobs [<value>]
 
@@ -149,46 +148,46 @@ Summary:
 
 .. option:: --cc
 
-   Specifies C++ without SystemC output mode; see also :vlopt:`--sc`
+   Specify C++ without SystemC output mode; see also the :vlopt:`--sc`
    option.
 
 .. option:: --cdc
 
    Permanently experimental.  Perform some clock domain crossing checks and
    issue related warnings (CDCRSTLOGIC) and then exit; if warnings other
-   than CDC warnings are needed make a second run with
+   than CDC warnings are needed, make a second run with
    :vlopt:`--lint-only`.  Additional warning information is also written to
    the file :file:`<prefix>__cdc.txt`.
 
-   Currently only checks some items that other CDC tools missed; if you
-   have interest in adding more traditional CDC checks, please contact the
+   Currently only checks some items that other CDC tools missed; if you are
+   interested in adding more traditional CDC checks, please contact the
    authors.
 
 .. option:: -CFLAGS <flags>
 
    Add specified C compiler argument to the generated makefiles. For
-   multiple flags either pass them as a single argument with space
+   multiple flags, either pass them as a single argument with space
    separators quoted in the shell (:command:`-CFLAGS "-a -b"`), or use
    multiple -CFLAGS options (:command:`-CFLAGS -a -CFLAGS -b`).
 
-   When make is run on the generated makefile these will be passed to the
+   When make is run on the generated makefile, these will be passed to the
    C++ compiler (g++/clang++/msvc++).
 
 .. option:: --clk <signal-name>
 
    With :vlopt:`--clk`, the specified signal is marked as a clock signal.
 
-   The provided signal-name is specified using a RTL hierarchy path. For
+   The provided signal name is specified using a RTL hierarchy path. For
    example, v.foo.bar.  If the signal is the input to top-module, then
    directly provide the signal name. Alternatively, use a
    :option:`/*verilator&32;clocker*/` metacomment in RTL file to mark the
    signal directly.
 
-   If clock signals are assigned to vectors and then later used as
-   individual bits, Verilator will attempt to decompose the vector and
-   connect the single-bit clock signals.
+   If clock signals are assigned to vectors and later used as individual
+   bits, Verilator will attempt to decompose the vector and connect the
+   single-bit clock signals.
 
-   In versions prior to 5.000, the clocker attribute is useful in cases where
+   In versions before 5.000, the clocker attribute is useful in cases where
    Verilator does not properly distinguish clock signals from other data
    signals. Using clocker will cause the signal indicated to be considered a
    clock, and remove it from the combinatorial logic reevaluation checking
@@ -196,23 +195,23 @@ Summary:
 
 .. option:: --no-clk <signal-name>
 
-   Prevent the specified signal from being marked as clock. See
+   Prevent the specified signal from being marked as a clock. See
    :vlopt:`--clk`.
 
 .. option:: --compiler <compiler-name>
 
    Enables workarounds for the specified C++ compiler (list below).
-   Currently this does not change any performance tuning options, but it may
+   This does not change any performance tuning options, but it may
    in the future.
 
    clang
      Tune for clang.  This may reduce execution speed as it enables several
      workarounds to avoid silly hard-coded limits in clang.  This includes
-     breaking deep structures as for msvc as described below.
+     breaking deep structures as for msvc, as described below.
 
    gcc
      Tune for GNU C++, although generated code should work on almost any
-     compliant C++ compiler.  Currently the default.
+     compliant C++ compiler.  Currently, the default.
 
    msvc
      Tune for Microsoft Visual C++.  This may reduce execution speed as it
@@ -228,7 +227,7 @@ Summary:
 
 .. option:: --coverage
 
-   Enables all forms of coverage, alias for :vlopt:`--coverage-line`
+   Enables all forms of coverage, an alias for :vlopt:`--coverage-line`
    :vlopt:`--coverage-toggle` :vlopt:`--coverage-user`.
 
 .. option:: --coverage-line
@@ -237,7 +236,7 @@ Summary:
 
 .. option:: --coverage-max-width <width>
 
-   Rarely needed.  Specify the maximum bit width of a signal that is
+   Rarely needed.  Specify the maximum bit width of a signal
    subject to toggle coverage.  Defaults to 256, as covering large vectors
    may greatly slow coverage simulations.
 
@@ -253,21 +252,21 @@ Summary:
 
 .. option:: --coverage-user
 
-   Enables adding user inserted functional coverage.  See :ref:`User Coverage`.
+   Enables adding user-inserted functional coverage.  See :ref:`User Coverage`.
 
 .. option:: -D<var>=<value>
 
    Defines the given preprocessor symbol.  Similar to
    :vlopt:`+define <+define+<var>>`, but does not allow multiple
-   definitions with a single option using plus signs. "+define" is fairly
-   standard across Verilog tools while "-D" is similar to
+   definitions with a single option using plus signs. "+define" is relatively
+   standard across Verilog tools, while "-D" is similar to
    :command:`gcc -D`.
 
 .. option:: --debug
 
    Run under debug.
 
-   * Select the debug executable of Verilator (if available), this
+   * Select the debug executable of Verilator (if available).  This
      generally is a less-optimized binary with symbols present (so GDB can be used on it).
    * Enable debugging messages (equivalent to :vlopt:`--debugi 3 <--debugi>`).
    * Enable internal assertions (equivalent to :vlopt:`--debug-check`).
@@ -286,7 +285,7 @@ Summary:
 
 .. option:: --no-debug-leak
 
-   In :vlopt:`--debug` mode, by default Verilator intentionally leaks
+   In :vlopt:`--debug` mode, by default, Verilator intentionally leaks
    AstNode instances instead of freeing them, so that each node pointer is
    unique in the resulting tree files and dot files.
 
@@ -294,18 +293,18 @@ Summary:
    Verilating large models in :vlopt:`--debug` mode.
 
    Outside of :vlopt:`--debug` mode, AstNode instances should never be
-   leaked and this option has no effect.
+   leaked, and this option has no effect.
 
 .. option:: --debugi <level>
 
-   Rarely needed - for developer use.  Set internal debugging level
+   Rarely needed - for developer use.  Set the internal debugging level
    globally to the specified debug level (1-10). Higher levels produce more
    detailed messages.
 
 .. option:: --debugi-<srcfile> <level>
 
    Rarely needed - for developer use.  Set the specified Verilator source
-   file to the specified level (e.g.
+   file to the specified level (e.g.,
    :vlopt:`--debugi-V3Width 9 <--debugi>`). Higher levels produce more
    detailed messages.  See :vlopt:`--debug` for other implications of
    enabling debug.
@@ -313,13 +312,13 @@ Summary:
 .. option:: --no-decoration
 
    When creating output Verilated code, minimize comments, white space,
-   symbol names and other decorative items, at the cost of greatly reduced
+   symbol names, and other decorative items, at the cost of reduced
    readability. This may assist C++ compile times. This will not typically
    change the ultimate model's performance, but may in some cases.
 
 .. option:: --default-language <value>
 
-   Select the language to be used by default when first processing each
+   Select the language used by default when first processing each
    Verilog file.  The language value must be "VAMS", "1364-1995",
    "1364-2001", "1364-2001-noconfig", "1364-2005", "1800-2005",
    "1800-2009", "1800-2012", "1800-2017", or "1800+VAMS".
@@ -331,7 +330,7 @@ Summary:
    The :vlopt:`--default-language` is only recommended for legacy code
    using the same language in all source files, as the preferable option is
    to edit the code to repair new keywords, or add appropriate
-   :code:`\`begin_keywords`. For legacy mixed language designs, the various
+   :code:`\`begin_keywords`. For legacy mixed-language designs, the various
    ``+<lang>ext+`` options should be used.
 
    If no language is specified, either by this option or ``+<lang>ext+``
@@ -343,13 +342,13 @@ Summary:
 .. option:: +define+<var>=<value>[+<var2>=<value2>][...]
 
    Defines the given preprocessor symbol, or multiple symbols if separated
-   by plus signs.  Similar to :vlopt:`-D <-D<var>>`; +define is fairly
+   by plus signs.  Similar to :vlopt:`-D <-D<var>>`; +define is relatively
    standard across Verilog tools while :vlopt:`-D <-D<var>>` is similar to
    :command:`gcc -D`.
 
 .. option:: --dpi-hdr-only
 
-   Only generate the DPI header file.  This option has no effect on the
+   Only generate the DPI header file.  This option does not affect on the
    name or location of the emitted DPI header file, it is output in
    :vlopt:`--Mdir` as it would be without this option.
 
@@ -378,7 +377,7 @@ Summary:
 .. option:: --dump-tree
 
    Rarely needed.  Enable dumping Ast .tree debug files with dumping level 3,
-   which dumps the standard critical stages.  For details on the format see
+   which dumps the standard critical stages.  For details on the format, see
    the Verilator Internals manual.  :vlopt:`--dump-tree` is enabled
    automatically with :vlopt:`--debug`, so
    :vlopt:`--debug --no-dump-tree <--dump-tree>` may be useful if the dump
@@ -394,10 +393,10 @@ Summary:
 
    Rarely needed - for developer use.  Replace AST node addresses with
    short identifiers in tree dumps to enhance readability.  Each unique
-   pointer value is mapped to an unique identifier, but note that this is
+   pointer value is mapped to a unique identifier, but note that this is
    not necessarily unique per node instance as an address might get reused
    by a newly allocated node after a node with the same address has been
-   dumped then freed.
+   dumped and then freed.
 
 .. option:: --dump-<srcfile>
 
@@ -406,7 +405,7 @@ Summary:
 
 .. option:: --dumpi-dfg <level>
 
-   Rarely needed - for developer use.  Set internal DfgGraph dumping level
+   Rarely needed - for developer use.  Set the internal DfgGraph dumping level
    globally to the specified value.
 
 .. option:: --dumpi-graph <level>
@@ -422,9 +421,9 @@ Summary:
 .. option:: --dumpi-<srcfile> <level>
 
    Rarely needed - for developer use. Set the dumping level in the
-   specified Verilator source file to the specified value (e.g.
+   specified Verilator source file to the specified value (e.g.,
    `--dumpi-V3Order 9`).  Level 0 disables dumps and is equivalent to
-   `--no-dump-<srcfile>`.  Level 9 enables dumping of everything.
+   `--no-dump-<srcfile>`.  Level 9 enables the dumping of everything.
 
 .. option:: -E
 
@@ -441,7 +440,7 @@ Summary:
    After this number of errors are encountered during Verilator run, exit.
    Warnings are not counted in this limit.  Defaults to 50.
 
-   Does not affect simulation runtime errors, for those see
+   It does not affect simulation runtime errors, for those, see
    :vlopt:`+verilator+error+limit+\<value\>`.
 
 .. option:: --exe
@@ -461,16 +460,16 @@ Summary:
    Read the specified file, and act as if all text inside it was specified
    as command line arguments.  Any relative paths are relative to the
    directory containing the specified file.  See also :vlopt:`-f`
-   option. Note :option:`-F` is fairly standard across Verilog tools.
+   option. Note :option:`-F` is relatively standard across Verilog tools.
 
 .. option:: -f <file>
 
    Read the specified file, and act as if all text inside it was specified
    as command line arguments.  Any relative paths are relative to the
    current directory.  See also :vlopt:`-F` option. Note :option:`-f` is
-   fairly standard across Verilog tools.
+   relatively standard across Verilog tools.
 
-   The file may contain :code:`//` comments which are ignored to the end of
+   The file may contain :code:`//` comments which are ignored until the end of
    the line.  It may also contain :code:`/* .. */` comments which are
    ignored, be cautious that wildcards are not handled in -f files, and
    that :code:`directory/*` is the beginning of a comment, not a wildcard.
@@ -488,9 +487,9 @@ Summary:
 
 .. option:: --flatten
 
-   Force flattening of the design's hierarchy, with all modules, tasks and
-   functions inlined. Typically used with :vlopt:`--xml-only`. Note
-   flattening large designs may require significant CPU time, memory and
+   Force flattening of the design's hierarchy, with all modules, tasks, and
+   functions inlined. Typically used with :vlopt:`--xml-only`.
+   Flattening large designs may require significant CPU time, memory and
    storage.
 
 .. option:: -fno-acyc-simp
@@ -515,7 +514,7 @@ Summary:
 
 .. option:: -fno-dfg
 
-   Disable all use of the DFG based combinational logic optimizer.
+   Disable all use of the DFG-based combinational logic optimizer.
    Alias for :vlopt:`-fno-dfg-pre-inline` and :vlopt:`-fno-dfg-post-inline`.
 
 .. option:: -fno-dfg-peephole
@@ -571,7 +570,7 @@ Summary:
 .. option:: -future0 <option>
 
    Rarely needed.  Suppress an unknown Verilator option for an option that
-   takes no additional arguments.  This is used to allow scripts written
+   takes no additional arguments.  This allows scripts written
    with pragmas for a later version of Verilator to run under an older
    version.  e.g. :code:`-future0 option --option` would on older versions
    that do not understand :code:`--option` or :code:`+option` suppress what
@@ -583,7 +582,7 @@ Summary:
 .. option:: -future1 <option>
 
    Rarely needed.  Suppress an unknown Verilator option for an option that
-   takes an additional argument.  This is used to allow scripts written
+   takes an additional argument.  This allows scripts written
    with pragmas for a later version of Verilator to run under an older
    version.  e.g. :code:`-future1 option --option arg` would on older
    versions that do not understand :code:`--option arg` or
@@ -595,33 +594,33 @@ Summary:
 
 .. option:: -G<name>=<value>
 
-   Overwrites the given parameter of the toplevel module. The value is
+   Overwrites the given parameter of the top-level module. The value is
    limited to basic data literals:
 
    Verilog integer literals
      The standard Verilog integer literals are supported, so values like
-     32'h8, 2'b00, 4 etc. are allowed. Care must be taken that the single
-     quote (I') is properly escaped in an interactive shell, e.g.,
+     32'h8, 2'b00, 4, etc., are allowed. Care must be taken that the single
+     quote (I') is appropriately escaped in an interactive shell, e.g.,
      as :code:`-GWIDTH=8'hx`.
 
    C integer literals
      It is also possible to use C integer notation, including hexadecimal
-     (0x..), octal (0..) or binary (0b..) notation.
+     (0x..), octal (0..), or binary (0b..) notation.
 
    Double literals
      Double literals must be one of the following styles:
-      - contains a dot (.) (e.g. 1.23)
-      - contains an exponent (e/E) (e.g. 12e3)
-      - contains p/P for hexadecimal floating point in C99 (e.g. 0x123.ABCp1)
+      - contains a dot (.) (e.g., :code:`1.23`)
+      - contains an exponent (e/E) (e.g. :code:`12e3`)
+      - contains p/P for hexadecimal floating point in C99 (e.g. :code:`0x123.ABCp1`)
 
    Strings
      Strings must be in double quotes (""). They must be escaped properly
-     on the command line, e.g. as :code:`-GSTR="\"My String\""` or
+     on the command line, e.g., as :code:`-GSTR="\"My String\""` or
      :code:`-GSTR='"My String"'`.
 
 .. option:: --gate-stmts <value>
 
-   Rarely needed.  Set the maximum number of statements that may be present
+   Rarely needed.  Set the maximum number of statements present
    in an equation for the gate substitution optimization to inline that
    equation.
 
@@ -632,8 +631,8 @@ Summary:
 
 .. option:: --gdbbt
 
-   If :vlopt:`--debug` is specified, run Verilator underneath a GDB process
-   and print a backtrace on exit, then exit GDB immediately.  Without
+   If :vlopt:`--debug` is specified, run Verilator underneath a GDB process,
+   print a backtrace on exit, and then exit GDB immediately.  Without
    :vlopt:`--debug` or if GDB doesn't seem to work, this flag is ignored.
    Intended for easy creation of backtraces by users; otherwise see the
    :vlopt:`--gdb` option.
@@ -647,14 +646,14 @@ Summary:
 
    If the variable is declared in the environment, print it and exit
    immediately. Otherwise, if it's built into Verilator
-   (e.g. VERILATOR_ROOT), print that and exit immediately. Otherwise, print
+   (e.g., VERILATOR_ROOT), print that and exit immediately. Otherwise, print
    a newline and exit immediately. This can be useful in makefiles. See
    also :vlopt:`-V`, and the various :file:`*.mk` files.
 
 .. option:: --get-supported <feature>
 
    If the given feature is supported, print "1" and exit
-   immediately. Otherwise, print a newline and exit immediately. This can
+   immediately; otherwise, print a newline and exit immediately. This can
    be useful in makefiles. See also :vlopt:`-V`, and the various
    :file:`*.mk` files.
 
@@ -666,7 +665,7 @@ Summary:
 
 .. option:: --hierarchical
 
-   Enable hierarchical Verilation otherwise
+   Enable hierarchical Verilation; otherwise, the
    :option:`/*verilator&32;hier_block*/` metacomment is ignored.  See
    :ref:`Hierarchical Verilation`.
 
@@ -677,7 +676,7 @@ Summary:
 .. option:: --if-depth <value>
 
    Rarely needed.  Set the depth at which the IFDEPTH warning will fire,
-   defaults to 0 which disables this warning.
+   defaults to 0, which disables this warning.
 
 .. option:: +incdir+<dir>
 
@@ -685,20 +684,21 @@ Summary:
 
 .. option:: --inline-mult <value>
 
-   Tune the inlining of modules.  The default value of 2000 specifies that up
-   to 2000 new operations may be added to the model by inlining, if more than
-   this number of operations would result, the module is not inlined.  Larger
-   values, or a value < 1 will inline everything, will lead to longer compile
-   times, but potentially faster simulation speed.  This setting is ignored
-   for very small modules; they will always be inlined, if allowed.
+   Tune the inlining of modules.  The default value of 2000 specifies that
+   up to 2000 new operations may be added to the model by inlining. If more
+   than this number of operations would result, the module is not inlined.
+   Larger values, or a value < 1 which will inline everything, leads to
+   longer compile times, but potentially faster simulation speed.  This
+   setting is ignored for very small modules; they will always be inlined,
+   if allowed.
 
 .. option:: --instr-count-dpi <value>
 
-   Assumed dynamic instruction count of the average DPI import. This is used
-   by the partitioning algorithm when creating a multithread model. The
-   default value is 200. Adjusting this to an appropriate value can yield
-   performance improvements in multithreaded models. Ignored when creating a
-   single threaded model.
+   Tune the assumed dynamic instruction count of the average DPI
+   import. This is used by the partitioning algorithm when creating a
+   multithread model. The default value is 200. Adjusting this to an
+   appropriate value can yield performance improvements in multithreaded
+   models. Ignored when creating a single-threaded model.
 
 .. option:: -j [<value>]
 
@@ -711,7 +711,7 @@ Summary:
 
    Instead of using the module name when showing Verilog scope, use the
    name provided. This allows simplifying some Verilator-embedded modeling
-   methodologies. Default is an l2-name matching the top module. The
+   methodologies. The default is an l2-name matching the top module, and the
    default before Verilator 3.884 was ``--l2-name v``.
 
    For example, the program
@@ -726,11 +726,11 @@ Summary:
 .. option:: -LDFLAGS <flags>
 
    Add specified C linker arguments to the generated makefiles.  For multiple
-   flags either pass them as a single argument with space separators quoted
+   flags, either pass them as a single argument with space separators quoted
    in the shell (``-LDFLAGS "-a -b"``), or use multiple -LDFLAGS arguments
    (``-LDFLAGS -a -LDFLAGS -b``).
 
-   When make is run on the generated makefile these will be passed to the
+   When make is run on the generated makefile, these will be passed to the
    C++ linker (ld) **after** the primary file being linked.  This flag is
    called :vlopt:`-LDFLAGS` as that's the traditional name in simulators;
    it's would have been better called LDLIBS as that's the Makefile
@@ -740,15 +740,15 @@ Summary:
 
 .. option:: --lib-create <name>
 
-   Produces C++, Verilog wrappers and a Makefile which can in turn produce
-   a DPI library which can be used by Verilator or other simulators along
+   Produces C++, Verilog wrappers, and a Makefile which can produce
+   a DPI library that can be used by Verilator or other simulators along
    with the corresponding Verilog wrapper.  The Makefile will build both a
    static and dynamic version of the library named :file:`lib<name>.a` and
    :file:`lib<name>.so` respectively.  This is done because some simulators
    require a dynamic library, but the static library is arguably easier to
    use if possible.  :vlopt:`--protect-lib` implies :vlopt:`--protect-ids`.
 
-   When using :vlopt:`--lib-create` it is advised to also use
+   When using :vlopt:`--lib-create`, it is advised to also use
    :vlopt:`--timescale-override /1fs <--timescale-override>` to ensure the
    model has a time resolution that is always compatible with the time
    precision of the upper instantiating module.
@@ -760,8 +760,8 @@ Summary:
 .. option:: +libext+<ext>[+<ext>][...]
 
    Specify the extensions that should be used for finding modules.  If for
-   example module "my" is referenced, look in :file:`my.<ext>`.  Note
-   "+libext+" is fairly standard across Verilog tools.  Defaults to
+   example, module "my" is referenced, look in :file:`my.<ext>`.  Note
+   "+libext+" is relatively standard across Verilog tools.  Defaults to
    ".v+.sv".
 
 .. option:: --lint-only
@@ -769,10 +769,10 @@ Summary:
    Check the files for lint violations only, do not create any other
    output.
 
-   You may also want the :vlopt:`-Wall` option to enable messages that are
+   You may also want the :vlopt:`-Wall` option to enable messages
    considered stylistic and not enabled by default.
 
-   If the design is not to be completely Verilated see also the
+   If the design is not to be completely Verilated, see also the
    :vlopt:`--bbox-sys` and :vlopt:`--bbox-unsup` options.
 
 .. option:: --make <build-tool>
@@ -781,17 +781,17 @@ Summary:
 
    Supported values are ``gmake`` for GNU Make and ``cmake`` for CMake.
    Both can be specified together.  If no build tool is specified, gmake is
-   assumed.  The executable of gmake can be configured via environment
-   variable "MAKE".
+   assumed.  The executable of gmake can be configured via the environment
+   variable :option:`MAKE`.
 
-   When using :vlopt:`--build` Verilator takes over the responsibility of
+   When using :vlopt:`--build`, Verilator takes over the responsibility of
    building the model library/executable.  For this reason :option:`--make`
    cannot be specified when using :vlopt:`--build`.
 
 .. option:: -MAKEFLAGS <string>
 
    When using :vlopt:`--build`, add the specified argument to the invoked
-   make command line.  For multiple flags either pass them as a single
+   make command line.  For multiple flags, either pass them as a single
    argument with space separators quoted in the shell (e.g.  ``-MAKEFLAGS
    "-a -b"``), or use multiple -MAKEFLAGS arguments
    (e.g. ``-MAKEFLAGS -l -MAKEFLAGS -k``). Use of this option should not be
@@ -801,9 +801,9 @@ Summary:
 
    Generates a top-level C++ main() file that supports parsing arguments,
    but does not drive any inputs.  This is sufficient to use for top-level
-   SystemVerilog designs that has no inputs.
+   SystemVerilog designs that have no inputs.
 
-   This option can also be used once to generate a main .cpp file as a
+   This option can also be used once to generate the main .cpp file as a
    starting point for editing.  Copy it outside the obj directory, manually
    edit, and then pass the filename on later Verilator command line
    invocations.
@@ -817,7 +817,7 @@ Summary:
 
 .. option:: --max-num-width <value>
 
-   Set the maximum number literal width (e.g. in 1024'd22 this it the
+   Set the maximum number literal width (e.g., in 1024'd22 this
    1024).  Defaults to 64K.
 
 .. option:: --Mdir <directory>
@@ -825,19 +825,19 @@ Summary:
    Specifies the name of the Make object directory.  All generated files
    will be placed in this directory.  If not specified, "obj_dir" is used.
    The directory is created if it does not exist and the parent directories
-   exist; otherwise manually create the Mdir before calling Verilator.
+   exist; otherwise, manually create the Mdir before calling Verilator.
 
 .. option:: --MMD
 
 .. option:: --no-MMD
 
-   Enable/disable creation of .d dependency files, used for make dependency
+   Enable/disable the creation of .d dependency files, used for make dependency
    detection, similar to gcc -MMD option.  By default this option is
    enabled for :vlopt:`--cc` or :vlopt:`--sc` modes.
 
 .. option:: --mod-prefix <topname>
 
-   Specifies the name to prepend to all lower level classes.  Defaults to
+   Specifies the name to prepend to all lower-level classes.  Defaults to
    the same as :vlopt:`--prefix`.
 
 .. option:: --MP
@@ -856,16 +856,16 @@ Summary:
 .. option:: -O3
 
    Enables slow optimizations for the code Verilator itself generates (as
-   opposed to :vlopt:`-CFLAGS -O3 <-CFLAGS>` which effects the C compiler's
+   opposed to :vlopt:`-CFLAGS -O3 <-CFLAGS>` which affects the C compiler's
    optimization.  :vlopt:`-O3` may improve simulation performance at the
    cost of compile time.  This currently sets
    :vlopt:`--inline-mult -1 <--inline-mult>`.
 
 .. option:: -O<optimization-letter>
 
-   Rarely needed.  Enables or disables a specific optimizations, with the
+   Rarely needed.  Enables or disables specific optimizations, with the
    optimization selected based on the letter passed.  A lowercase letter
-   disables an optimization, an upper case letter enables it.  This option
+   disables an optimization, an uppercase letter enables it.  This option
    is deprecated and the various `-f<optimization>` arguments should be
    used instead.
 
@@ -878,7 +878,7 @@ Summary:
 
    Deprecated and has no effect (ignored).
 
-   In versions prior to 5.000:
+   In versions before 5.000:
 
    Rarely needed.  Disables a bug fix for ordering of clock enables with
    delayed assignments.  This option should only be used when suggested by
@@ -890,7 +890,7 @@ Summary:
    C++ file exceeds the specified number of operations, a new file will be
    created at the next function boundary.  In addition, if the total output
    code size exceeds the specified value, VM_PARALLEL_BUILDS will be set to
-   1 by default in the generated make files, making parallel compilation
+   1 by default in the generated makefiles, making parallel compilation
    possible. Using :vlopt:`--output-split` should have only a trivial
    impact on model performance. But can greatly improve C++ compilation
    speed. The use of "ccache" (set for you if present at configure time) is
@@ -915,7 +915,7 @@ Summary:
 
 .. option:: --output-split-ctrace <statements>
 
-   Similar to :vlopt:`--output-split-cfuncs`, enables splitting trace
+   Similar to :vlopt:`--output-split-cfuncs`, it enables splitting trace
    functions in the output .cpp files into multiple functions.
 
    Defaults to the value of :vlopt:`--output-split`, unless explicitly
@@ -928,7 +928,7 @@ Summary:
 
 .. option:: --pins-bv <width>
 
-   Specifies SystemC inputs/outputs of greater than or equal to <width>
+   Specifies SystemC inputs/outputs greater than or equal to <width>
    bits wide should use sc_bv's instead of uint32/uint64_t's.  The
    default is "--pins-bv 65", and the value must be less than or equal
    to 65.  Versions before Verilator 3.671 defaulted to "--pins-bv 33".
@@ -938,14 +938,14 @@ Summary:
 
 .. option:: --pins-sc-uint
 
-   Specifies SystemC inputs/outputs of greater than 2 bits wide should use
+   Specifies SystemC inputs/outputs greater than 2 bits wide should use
    sc_uint between 2 and 64.  When combined with the
    :vlopt:`--pins-sc-biguint` combination, it results in sc_uint being used
    between 2 and 64 and sc_biguint being used between 65 and 512.
 
 .. option:: --pins-sc-biguint
 
-   Specifies SystemC inputs/outputs of greater than 65 bits wide should use
+   Specifies SystemC inputs/outputs greater than 65 bits wide should use
    sc_biguint between 65 and 512, and sc_bv from 513 upwards.  When
    combined with the :vlopt:`--pins-sc-uint` combination, it results in
    sc_uint being used between 2 and 64 and sc_biguint being used between 65
@@ -953,7 +953,7 @@ Summary:
 
 .. option:: --pins-uint8
 
-   Specifies SystemC inputs/outputs that are smaller than the
+   Specifies SystemC inputs/outputs smaller than the
    :vlopt:`--pins-bv` setting and 8 bits or less should use uint8_t instead
    of uint32_t.  Likewise pins of width 9-16 will use uint16_t instead of
    uint32_t.
@@ -984,7 +984,7 @@ Summary:
    terminates.  See the file:`t/t_pipe_filter` test for an example.
 
    To debug the output of the filter, try using the :vlopt:`-E` option to
-   see preprocessed output.
+   see the preprocessed output.
 
 .. option:: --pp-comments
 
@@ -992,19 +992,19 @@ Summary:
 
 .. option:: --prefix <topname>
 
-   Specifies the name of the top level class and makefile.  Defaults to V
+   Specifies the name of the top-level class and makefile.  Defaults to V
    prepended to the name of the :vlopt:`--top` option, or V prepended to
    the first Verilog filename passed on the command line.
 
 .. option:: --private
 
-   Opposite of :vlopt:`--public`.  Is the default; this option exists for
+   Opposite of :vlopt:`--public`.  This is the default; this option exists for
    backwards compatibility.
 
 .. option:: --prof-c
 
    When compiling the C++ code, enable the compiler's profiling flag
-   (e.g. :code:`g++ -pg`). See :ref:`Profiling`.
+   (e.g., :code:`g++ -pg`). See :ref:`Profiling`.
 
    Using :vlopt:`--prof-cfuncs` also enables :vlopt:`--prof-c`.
 
@@ -1012,9 +1012,9 @@ Summary:
 
    Modify the created C++ functions to support profiling.  The functions
    will be minimized to contain one "basic" statement, generally a single
-   always block or wire statement.  (Note this will slow down the
+   always block or wire statement.  (This may slow down the
    executable by ~5%.)  Furthermore, the function name will be suffixed
-   with the basename of the Verilog module and line number the statement
+   with the basename of the Verilog module and the line number the statement
    came from.  This allows gprof or oprofile reports to be correlated with
    the original Verilog source statements. See :ref:`Profiling`.
 
@@ -1027,8 +1027,9 @@ Summary:
 
 .. option:: --prof-pgo
 
-   Enable collection of profiling data for profile guided Verilation. Currently
-   this is only useful with :vlopt:`--threads`. See :ref:`Thread PGO`.
+   Enable collection of profiling data for profile-guided
+   Verilation. Currently, this is only useful with :vlopt:`--threads`. See
+   :ref:`Thread PGO`.
 
 .. option:: --prof-threads
 
@@ -1037,19 +1038,19 @@ Summary:
 .. option:: --protect-ids
 
    Hash any private identifiers (variable, module, and assertion block
-   names that are not on the top level) into hashed random-looking
+   names that are not on the top-level) into hashed random-looking
    identifiers, resulting after compilation in protected library binaries
    that expose less design information.  This hashing uses the provided or
-   default :vlopt:`--protect-key`, see important details there.
+   default :vlopt:`--protect-key`; see important details there.
 
    Verilator will also create a :file:`<prefix>__idmap.xml` file which
    contains the mapping from the hashed identifiers back to the original
    identifiers. This idmap file is to be kept private, and is to assist
-   mapping any simulation runtime design assertions, coverage, or trace
+   in mapping any simulation runtime design assertions, coverage, or trace
    information, which will report the hashed identifiers, back to the
    original design's identifier names.
 
-   Using DPI imports/exports is allowed and generally relatively safe in
+   Using DPI imports/exports are allowed and generally relatively safe in
    terms of information disclosed, which is limited to the DPI function
    prototypes.  Use of the VPI is not recommended as many design details
    may be exposed, and an INSECURE warning will be issued.
@@ -1086,7 +1087,7 @@ Summary:
 
 .. option:: --public
 
-   This is only for historical debug use.  Using it may result in
+   This is only for historical debugging use and using it may result in
    mis-simulation of generated clocks.
 
    Declares all signals and modules public.  This will turn off signal
@@ -1098,7 +1099,7 @@ Summary:
 
 .. option:: --public-flat-rw
 
-   Declares all variables, ports and wires public as if they had
+   Declares all variables, ports, and wires public as if they had
    :code:`/*verilator public_flat_rw @ (<variable's_source_process_edge>)*/`
    metacomments.  This will make them VPI accessible by their flat name,
    but not turn off module inlining.  This is particularly useful in
@@ -1109,7 +1110,7 @@ Summary:
 
 .. option:: -pvalue+<name>=<value>
 
-   Overwrites the given parameter(s) of the toplevel module. See
+   Overwrites the given parameter(s) of the top-level module. See
    :vlopt:`-G <-G<name>>` for a detailed description.
 
 .. option:: --quiet-exit
@@ -1127,25 +1128,25 @@ Summary:
 
    Rarely needed. Verilator attempts to turn some common sequences of
    statements into loops in the output. This argument specifies the minimum
-   number of iterations the resulting loop needs to have in order to perform
-   this transformation. Default limit is 40. A smaller number may slightly
-   improve C++ compilation time on designs where these sequences are common,
-   however effect on model performance requires benchmarking.
+   number of iterations the resulting loop needs to have to perform this
+   transformation. The default limit is 40. A smaller number may slightly
+   improve C++ compilation time on designs where these sequences are
+   common; however, the effect on model performance requires benchmarking.
 
 .. option:: --report-unoptflat
 
-   Extra diagnostics for UNOPTFLAT warnings. This includes for each loop,
-   the 10 widest variables in the loop, and the 10 most fanned out
-   variables in the loop. These are candidates for splitting into multiple
-   variables to break the loop.
+   Enable extra diagnostics for :option:`UNOPTFLAT` warnings. This
+   includes, for each loop, the ten widest variables in the loop, and the
+   ten most fanned-out variables in the loop. These are candidates for
+   splitting into multiple variables to break the loop.
 
-   In addition produces a GraphViz DOT file of the entire strongly
+   In addition, produces a GraphViz DOT file of the entire strongly
    connected components within the source associated with each loop. This
    is produced irrespective of whether :vlopt:`--dump-tree` is set. Such
-   graphs may help in analyzing the problem, but can be very large indeed.
+   graphs may help analyze the problem, but can be very large.
 
-   Various commands exist for viewing and manipulating DOT files. For
-   example the "dot" command can be used to convert a DOT file to a PDF for
+   Various commands exist for viewing and manipulating DOT files, for
+   example, the "dot" command can convert a DOT file to a PDF for
    printing. For example:
 
    .. code-block:: bash
@@ -1164,8 +1165,8 @@ Summary:
 
 .. option:: --rr
 
-   Run Verilator and record with the :command:`rr` command.  See:
-   rr-project.org.
+   Run Verilator and record with the :command:`rr` command.  See
+   `https://rr-project.org <https://rr-project.org>`_.
 
 .. option:: --savable
 
@@ -1182,7 +1183,7 @@ Summary:
 
    Rarely needed.  Disables or enables skipping execution of Verilator if
    all source files are identical, and all output files exist with newer
-   dates.  By default this option is enabled for :vlopt:`--cc` or
+   dates.  By default, this option is enabled for :vlopt:`--cc` or
    :vlopt:`--sc` modes only.
 
 .. option:: --stats
@@ -1198,17 +1199,17 @@ Summary:
 
 .. option:: --structs-packed
 
-   Converts all unpacked structures to packed structures and issues a
-   UNPACKED warning.  Currently this is the default and
+   Converts all unpacked structures to packed structures and issues an
+   :option:`UNPACKED` warning.  Currently, this is the default, and
    :vlopt:`--no-structs-packed <--structs-packed>` will not work.
-   Specifying this option allows for forward compatibility when a future
+   Specifying this option allows forward compatibility when a future
    version of Verilator no longer always packs unpacked structures.
 
 .. option:: -sv
 
    Specifies SystemVerilog language features should be enabled; equivalent
    to :vlopt:`--language 1800-2017 <--language>`.  This option is selected
-   by default, it exists for compatibility with other simulators.
+   by default; it exists for compatibility with other simulators.
 
 .. option:: +systemverilogext+<ext>
 
@@ -1216,7 +1217,7 @@ Summary:
 
 .. option:: --threads <threads>
 
-   With "--threads 1", the default, the generated model is single threaded
+   With "--threads 1", the default, the generated model is single-threaded
    but may run in a multithreaded environment. With "--threads N",
    where N >= 2, the model is generated to run multithreaded on up to N
    threads. See :ref:`Multithreading`. This option also applies to
@@ -1226,7 +1227,7 @@ Summary:
 
    Deprecated and has no effect (ignored).
 
-   In versions prior to 5.004, created a model which was not thread safe.
+   In versions before 5.004, created a model which was not thread-safe.
 
 .. option:: --threads-dpi all
 
@@ -1235,21 +1236,21 @@ Summary:
 .. option:: --threads-dpi pure
 
    When using :vlopt:`--threads`, controls which DPI imported tasks and
-   functions are considered thread safe.
+   functions are considered thread-safe.
 
    With "--threads-dpi all",
-     Enable Verilator to assume all DPI imports are threadsafe, and to use
+     Enable Verilator to assume all DPI imports are thread-safe, and to use
      thread-local storage for communication with DPI, potentially improving
      performance. Any DPI libraries need appropriate mutexes to avoid
      undefined behavior.
 
    With "--threads-dpi none",
-     Verilator assume DPI imports are not thread safe, and Verilator will
+     Verilator assumes DPI imports are not thread-safe, and Verilator will
      serialize calls to DPI imports by default, potentially harming
      performance.
 
    With "--threads-dpi pure", the default,
-     Verilator assumes DPI pure imports are threadsafe, but non-pure DPI
+     Verilator assumes DPI pure imports are thread-safe, but non-pure DPI
      imports are not.
 
    See also :vlopt:`--instr-count-dpi` option.
@@ -1262,7 +1263,7 @@ Summary:
 
 .. option:: --timescale <timeunit>/<timeprecision>
 
-   Sets default timescale, timeunit and timeprecision for when "`timescale"
+   Sets default timeunit and timeprecision when "`timescale"
    does not occur before a given module.  Default is "1ps/1ps" (to match
    SystemC).  This is overridden by :vlopt:`--timescale-override`.
 
@@ -1275,8 +1276,8 @@ Summary:
 
    The time precision must be consistent with SystemC's
    "sc_set_time_resolution()", or the C++ code instantiating the Verilated
-   module.  As "1fs" is the finest time precision it may be desirable to
-   always use a precision of "1fs".
+   module.  As "1fs" is the finest time precision, it may be desirable
+   always to use a precision of "1fs".
 
 .. option:: --timing
 
@@ -1284,16 +1285,16 @@ Summary:
 
    Enables/disables support for timing constructs such as delays, event
    controls (unless it's at the top of a process), wait statements, and joins.
-   When disabled, timing control constructs are ignored the same way as they
-   were in earlier versions of Verilator. Enabling this feature requires a C++
+   When disabled, timing control constructs are ignored the same way as
+   in earlier versions of Verilator. Enabling this feature requires a C++
    compiler with coroutine support (GCC 10, Clang 5, or newer).
 
 .. option:: --top <topname>
 
 .. option:: --top-module <topname>
 
-   When the input Verilog contains more than one top level module,
-   specifies the name of the Verilog module to become the top level module,
+   When the input Verilog contains more than one top-level module,
+   it specifies the name of the module to become the top-level module,
    and sets the default for :vlopt:`--prefix` if not explicitly specified.
    This is not needed with standard designs with only one top.  See also
    :option:`MULTITOP` warning.
@@ -1304,14 +1305,14 @@ Summary:
    :vlopt:`--trace-fst`.
 
    Verilator will generate additional :file:`<prefix>__Trace*.cpp` files
-   that will need to be compiled.  In addition :file:`verilated_vcd_sc.cpp`
+   must be compiled.  In addition :file:`verilated_vcd_sc.cpp`
    (for SystemC traces) or :file:`verilated_vcd_c.cpp` (for both) must be
-   compiled and linked in.  If using the Verilator generated Makefiles,
+   compiled and linked in.  If using the Verilator-generated Makefiles,
    these files will be added to the source file lists for you.  If you are
    not using the Verilator Makefiles, you will need to add these to your
    Makefile manually.
 
-   Having tracing compiled in may result in some small performance losses,
+   Having tracing compiled in may result in small performance losses,
    even when tracing is not turned on during model execution.
 
    When using :vlopt:`--threads`, VCD tracing is parallelized, using the
@@ -1326,17 +1327,17 @@ Summary:
    additional signals added, as the original signals being toggle-analyzed
    are already visible.
 
-   The added signal will be a 32-bit value which will increment on each
-   coverage occurrence. Due to this, this option may greatly increase trace
+   The added signal will be a 32-bit value, incrementing on each coverage
+   occurrence. Due to this, this option may significantly increase trace
    file sizes and reduce simulation speed.
 
 .. option:: --trace-depth <levels>
 
-   Specify the number of levels deep to enable tracing, for example
-   :vlopt:`--trace-depth 1 <--trace-depth>` to only see the top level's
+   Specify the number of levels deep to enable tracing, for example,
+   :vlopt:`--trace-depth 1 <--trace-depth>` to only see the top-level
    signals.  Defaults to the entire model.  Using a small number will
-   decrease visibility, but greatly improve simulation performance and
-   trace file size.
+   decrease visibility, but significantly improve simulation performance
+   and trace file size.
 
 .. option:: --trace-fst
 
@@ -1363,7 +1364,7 @@ Summary:
 
    Enable tracing to show the name of packed structure, union, and packed
    array fields, rather than a single combined packed bus.  Due to VCD file
-   format constraints this may result in significantly slower trace times
+   format constraints, this may result in significantly slower trace times
    and larger trace files.
 
 .. option:: --trace-threads *threads*
@@ -1379,7 +1380,7 @@ Summary:
 .. option:: --trace-underscore
 
    Enable tracing of signals or modules that start with an
-   underscore. Normally, these signals are not output during tracing.  See
+   underscore. Otherwise, these signals are not output during tracing.  See
    also :vlopt:`--coverage-underscore` option.
 
 .. option:: -U<var>
@@ -1403,8 +1404,8 @@ Summary:
 
 .. option:: --unused-regexp *regexp*
 
-   Rarely needed.  Specifies a simple regexp with \* and ? that if a signal
-   name matches will suppress the UNUSED warning.  Defaults to
+   Rarely needed.  Specifies a simple regexp with \* and ? that, if a signal
+   name matches, will suppress the :option:`UNUSED` warning.  Defaults to
    "\*unused\*".  Setting it to "" disables matching.
 
 .. option:: -V
@@ -1416,13 +1417,13 @@ Summary:
 .. option:: -v *filename*
 
    Read the filename as a Verilog library.  Any modules in the file may be
-   used to resolve instances in the top level module, else ignored.  Note
-   "-v" is fairly standard across Verilog tools.
+   used to resolve instances in the top-level module, otherwise, they are
+   ignored.  Note "-v" is relatively standard across Verilog tools.
 
 .. option:: --no-verilate
 
-   When using :vlopt:`--build`, disable generation of C++/SystemC code, and
-   execute only the build. This can be useful for rebuilding Verilated code
+   When using :vlopt:`--build`, disable the generation of C++/SystemC code, and
+   execute only the build. This can be useful for rebuilding the Verilated code
    produced by a previous invocation of Verilator.
 
 .. option:: +verilog1995ext+<ext>
@@ -1439,12 +1440,12 @@ Summary:
 
 .. option:: --vpi
 
-   Enable use of VPI and linking against the :file:`verilated_vpi.cpp` files.
+   Enable the use of VPI and linking against the :file:`verilated_vpi.cpp` files.
 
 .. option:: --waiver-output *filename*
 
-   Generate a waiver file which contains all waiver statements to suppress
-   the warnings emitted during this Verilator run. This in particular is
+   Generate a waiver file that contains all waiver statements to suppress
+   the warnings emitted during this Verilator run. This, in particular, is
    useful as a starting point for solving linter warnings or suppressing
    them systematically.
 
@@ -1454,15 +1455,15 @@ Summary:
 
 .. option:: -Wall
 
-   Enable all code style warnings, including code style warnings that are
-   normally disabled by default. Equivalent to :vlopt:`-Wwarn-lint`
+   Enable all code-style warnings, including style warnings that are
+   typically disabled by default. Equivalent to :vlopt:`-Wwarn-lint`
    :vlopt:`-Wwarn-style`.  Excludes some specialty warnings.
 
 .. option:: -Werror-<message>
 
    Promote the specified warning message into an error message.  This is
    generally to discourage users from violating important site-wide rules,
-   for example "-Werror-NOUNOPTFLAT".
+   for example, "-Werror-NOUNOPTFLAT".
 
 .. option:: -Wfuture-<message>
 
@@ -1470,32 +1471,32 @@ Summary:
    with the given message code.  This is used to allow code written with
    pragmas for a later version of Verilator to run under an older version;
    add "-Wfuture-" arguments for each message code or comment that the new
-   version supports which the older version does not support.
+   version supports, which the older version does not support.
 
 .. option:: -Wno-<message>
 
    Disable the specified warning/error message.  This will override any
-   lint_on directives in the source, i.e. the warning will still not be
+   lint_on directives in the source, i.e., the warning will still not be
    printed.
 
 .. option:: -Wno-context
 
    Disable showing the suspected context of the warning message by quoting
    the source text at the suspected location.  This can be used to appease
-   tools which process the warning messages but may get confused by lines
-   from the original source.
+   tools that process the warning messages but may get confused by lines
+   quoted from the source.
 
 .. option:: -Wno-fatal
 
    When warnings are detected, print them, but do not terminate Verilator.
 
-   Having warning messages in builds can be sloppy.  It is recommended you
-   cleanup your code, use inline lint_off, or use ``-Wno-...`` options
-   rather than using this option.
+   Having warning messages in builds can be sloppy.  You should cleanup
+   your code, use inline lint_off, or use ``-Wno-...`` options rather than
+   using this option.
 
 .. option:: -Wno-lint
 
-   Disable all lint related warning messages, and all style warnings.  This is
+   Disable all lint-related warning messages, and all style warnings.  This is
    equivalent to ``-Wno-ALWCOMBORDER -Wno-BSSPACE -Wno-CASEINCOMPLETE
    -Wno-CASEOVERLAP -Wno-CASEX -Wno-CASTCONST -Wno-CASEWITHX -Wno-CMPCONST -Wno-COLONPLUS
    -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINCONNECTEMPTY
@@ -1503,13 +1504,13 @@ Summary:
    -Wno-UNUSEDGENVAR -Wno-UNUSEDPARAM -Wno-UNUSEDSIGNAL
    -Wno-WIDTH`` plus the list shown for Wno-style.
 
-   It is strongly recommended you cleanup your code rather than using this
-   option, it is only intended to be use when running test-cases of code
+   It is strongly recommended that you clean up your code rather than using this
+   option; it is only intended to be used when running test-cases of code
    received from third parties.
 
 .. option:: -Wno-style
 
-   Disable all code style related warning messages (note by default they are
+   Disable all code style related warning messages (note that by default, they are
    already disabled).  This is equivalent to ``-Wno-DECLFILENAME -Wno-DEFPARAM
    -Wno-EOFNEWLINE -Wno-IMPORTSTAR -Wno-INCABSPATH -Wno-PINCONNECTEMPTY
    -Wno-PINNOCONNECT -Wno-SYNCASYNCNET -Wno-UNDRIVEN
@@ -1520,7 +1521,7 @@ Summary:
 
    Warn on any construct demanded by IEEE, and disable all Verilator
    extensions that may interfere with IEEE compliance to the standard
-   defined with :vlopt:`--default-language` (etc).  Similar to
+   defined with :vlopt:`--default-language`, etc.  Similar to
    :command:`gcc -Wpedantic`.  Rarely used, and intended only for strict
    compliance tests.
 
@@ -1530,7 +1531,7 @@ Summary:
 
 .. option:: -Wwarn-lint
 
-   Enable all lint related warning messages (note by default they are already
+   Enable all lint-related warning messages (note that by default, they are already
    enabled), but do not affect style messages.  This is equivalent to
    ``-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE -Wwarn-CASEINCOMPLETE
    -Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASTCONST -Wwarn-CASEWITHX -Wwarn-CMPCONST
@@ -1539,7 +1540,7 @@ Summary:
 
 .. option:: -Wwarn-style
 
-   Enable all code style related warning messages.  This is equivalent to
+   Enable all code style-related warning messages.  This is equivalent to
    ``-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-EOFNEWLINE
    -Wwarn-INCABSPATH -Wwarn-PINNOCONNECT -Wwarn-SYNCASYNCNET -Wwarn-UNDRIVEN
    -Wwarn-UNUSEDGENVAR -Wwarn-UNUSEDPARAM -Wwarn-UNUSEDSIGNAL -Wwarn-VARHIDDEN``.
@@ -1560,21 +1561,21 @@ Summary:
    as active high logic will fire. Using "--x-assign unique" will result in
    all explicit Xs being replaced by a constant value determined at
    runtime. The value is determined by calling a function at initialization
-   time. This enables randomization of Xs with different seeds on different
+   time. This enables the randomization of Xs with different seeds on different
    executions. This method is the slowest, but safest for finding reset
    bugs.
 
    If using "--x-assign unique", you may want to seed your random number
    generator such that each regression run gets a different randomization
    sequence. The simplest is to use the :vlopt:`+verilator+seed+\<value\>`
-   runtime option.  Alternatively use the system's :code:`srand48()` or for
+   runtime option.  Alternatively, use the system's :code:`srand48()` or for
    Windows :code:`srand()` function to do this.  You'll probably also want
    to print any seeds selected, and code to enable rerunning with that same
    seed so you can reproduce bugs.
 
    .. note::
 
-      This option applies only to values which are explicitly written as X
+      This option applies only to values explicitly written as X
       in modules (not classes) in the Verilog source code. Initial values
       of clocks are set to 0 unless `--x-initial-edge` is
       specified. Initial values of all other state holding variables are
@@ -1586,7 +1587,7 @@ Summary:
 
 .. option:: --x-initial unique (default)
 
-   Controls the two-state value that is used to initialize variables that
+   Controls the two-state value used to initialize variables that
    are not otherwise initialized.
 
    "--x-initial 0",
@@ -1594,8 +1595,8 @@ Summary:
 
    "--x-initial unique", the default,
      initializes variables using a function, which determines the value to
-     use each initialization. This gives greatest flexibility and allows
-     finding reset bugs.  See :ref:`Unknown states`.
+     use for each initialization. This gives the greatest flexibility and
+     allows for finding reset bugs.  See :ref:`Unknown states`.
 
    "--x-initial fast",
      is best for performance, and initializes all variables to a state
@@ -1605,13 +1606,13 @@ Summary:
 
    .. note::
 
-      This option applies only to initial values of variables. Initial
+      This option applies only to the initial values of variables. Initial
       values of clocks are set to 0 unless :vlopt:`--x-initial-edge` is
       specified.
 
 .. option:: --x-initial-edge
 
-   Enables emulation of event driven simulators which generally trigger an
+   Enables emulation of event-driven simulators, which generally trigger an
    edge on a transition from X to 1 (posedge) or X to 0 (negedge). Thus the
    following code, where :code:`rst_n` is uninitialized would set
    :code:`res_n` to :code:`1'b1` when :code:`rst_n` is first set to zero:
@@ -1629,14 +1630,14 @@ Summary:
    In Verilator, by default, uninitialized clocks are given a value of
    zero, so the above :code:`always` block would not trigger.
 
-   While it is not good practice, there are some designs that rely on X
-   rarr 0 triggering a negedge, particularly in reset sequences. Using
-   :vlopt:`--x-initial-edge` with Verilator will replicate this
-   behavior. It will also ensure that X rarr 1 triggers a posedge.
+   While it is not good practice, some designs rely on X->0 triggering a
+   negedge, particularly in reset sequences. Using
+   :vlopt:`--x-initial-edge` will replicate this behavior. It will also
+   ensure that X->1 triggers a posedge.
 
    .. note::
 
-      Using this option can affect convergence, andit may be necessary to
+      Using this option can affect convergence, and it may be necessary to
       use :vlopt:`--converge-limit` to increase the number of convergence
       iterations. This may be another indication of problems with the
       modeled design that should be addressed.
@@ -1651,21 +1652,22 @@ Summary:
 
 .. option:: --xml-output <filename>
 
-   Filename for XML output file. Using this option automatically sets
-   :vlopt:`--xml-only`.
+   Specifies the filename for the XML output file. Using this option
+   automatically sets :vlopt:`--xml-only`.
 
 .. option:: -y <dir>
 
-   Add the directory to the list of directories that should be searched for
+   Add the directory to the list of directories that should be searched to find
    include files or libraries.  The three flags :vlopt:`-y`,
-   :vlopt:`+incdir+\<dir\>` and :vlopt:`-I\<dir\>` have similar effect;
-   :vlopt:`+incdir+\<dir\>` and :vlopt:`-y` are fairly standard across
+   :vlopt:`+incdir+\<dir\>` and :vlopt:`-I\<dir\>` have a similar effect;
+   :vlopt:`+incdir+\<dir\>` and :vlopt:`-y` are relatively standard across
    Verilog tools while :vlopt:`-I\<dir\>` is used by many C++ compilers.
 
    Verilator defaults to the current directory "-y ." and any specified
-   :vlopt:`--Mdir`, though these default paths are used after any user
-   specified directories.  This allows '-y "$(pwd)"' to be used if absolute
-   filenames are desired for error messages instead of relative filenames.
+   :vlopt:`--Mdir`, though these default paths are used after any
+   user-specified directories.  This allows '-y "$(pwd)"' to be used if
+   absolute filenames are desired for error messages instead of relative
+   filenames.
 
 
 .. _Configuration Files:
@@ -1688,7 +1690,7 @@ This disables WIDTH warnings globally, and CASEX for a specific file.
 
 Configuration files are fed through the normal Verilog preprocessor prior
 to parsing, so "\`ifdef", "\`define", and comments may be used as if the
-configuration file was normal Verilog code.
+configuration file was standard Verilog code.
 
 Note that file or line-specific configuration only applies to files read
 after the configuration file. It is therefore recommended to pass the
@@ -1698,7 +1700,7 @@ The grammar of configuration commands is as follows:
 
 .. option:: `verilator_config
 
-   Take remaining text and treat it as Verilator configuration commands.
+   Take the remaining text and treat it as Verilator configuration commands.
 
 .. option:: coverage_on  [-file "<filename>" [-lines <line> [ - <line> ]]]
 
@@ -1713,10 +1715,10 @@ The grammar of configuration commands is as follows:
 
    Deprecated and has no effect (ignored).
 
-   In versions prior to 5.000:
+   In versions before 5.000:
 
-   Indicate the signal is used to gate a clock, and the user takes
-   responsibility for insuring there are no races related to it.
+   Indicates that the signal is used to gate a clock, and the user takes
+   responsibility for ensuring there are no races related to it.
 
    Same as :option:`/*verilator&32;clock_enable*/` metacomment.
 
@@ -1728,9 +1730,9 @@ The grammar of configuration commands is as follows:
 
 .. option:: no_clocker -module "<modulename>" [-function "<funcname>"] -var "<signame>"
 
-   Indicates that the signal is used as clock or not. This information is
-   used by Verilator to mark the signal and any derived signals as
-   clocker.  See :vlopt:`--clk`.
+   Indicates whether the signal is used as clock or not. Verilator uses
+   this information to mark the signal and any derived signals as clocker.
+   See :vlopt:`--clk`.
 
    Same as :option:`/*verilator&32;clocker*/` metacomment.
 
@@ -1739,7 +1741,7 @@ The grammar of configuration commands is as follows:
 .. option:: coverage_block_off -file "<filename>" -line <lineno>
 
    Specifies the entire begin/end block should be ignored for coverage
-   analysis purposes.  Can either be specified as a named block or as a
+   analysis purposes.  It can either be specified as a named block or as a
    filename and line number.
 
    Same as :option:`/*verilator&32;coverage_block_off*/` metacomment.
@@ -1747,7 +1749,7 @@ The grammar of configuration commands is as follows:
 .. option:: forceable -module "<modulename>" -var "<signame>"
 
    Generate public `<signame>__VforceEn` and `<signame>__VforceVal` signals
-   that can be used to force/release a signal from C++ code. The force control
+   that can force/release a signal from C++ code. The force control
    signals are created as :option:`public_flat` signals.
 
    Same as :option:`/*verilator&32;forceable*/` metacomment.
@@ -1759,7 +1761,7 @@ The grammar of configuration commands is as follows:
    Same as :code:`//synopsys full_case` and
    :code:`//synopsys parallel_case`. When these synthesis directives are
    discovered, Verilator will either formally prove the directive to be
-   true, or failing that, will insert the appropriate code to detect
+   true, or, failing that, will insert the appropriate code to detect
    failing cases at simulation runtime and print an "Assertion failed"
    error message.
 
@@ -1780,12 +1782,9 @@ The grammar of configuration commands is as follows:
 
 .. option:: isolate_assignments -module "<modulename>" -function "<fname>"
 
-   Used to indicate the assignments to this signal in any blocks should be
-   isolated into new blocks.  When there is a large combinatorial block
-   that is resulting in an UNOPTFLAT warning, attaching this to the signal
-   causing a false loop may clear up the problem.
-
-   Same as :option:`/*verilator&32;isolate_assignments*/` metacomment.
+   Used to indicate that the assignments to this signal in any blocks
+   should be isolated into new blocks.  Same as
+   :option:`/*verilator&32;isolate_assignments*/` metacomment.
 
 .. option:: no_inline -module "<modulename>"
 
@@ -1822,12 +1821,12 @@ The grammar of configuration commands is as follows:
    :vlopt:`-Wno-lint`) are enabled/disabled.  This will override all later
    lint warning enables for the specified region.
 
-   If -match is set the linter warnings are matched against this (wildcard)
-   string and are waived in case they match and iff rule and file (with
-   wildcard) also match.
+   If -match is set, the linter warnings are matched against this
+   (wildcard) string and are waived in case they match, provided with the
+   rule and file also match.
 
    In previous versions -rule was named -msg. The latter is deprecated, but
-   still works with a deprecation info, it may be removed in future
+   still works with a deprecation info; it may be removed in future
    versions.
 
 .. option:: public [-module "<modulename>"] [-task/-function "<taskname>"]  -var "<signame>"
@@ -1840,8 +1839,8 @@ The grammar of configuration commands is as follows:
 
    Sets the variable to be public.  Same as
    :option:`/*verilator&32;public*/` or
-   :option:`/*verilator&32;public_flat*/`, etc, metacomments. See
-   e.g. :ref:`VPI Example`.
+   :option:`/*verilator&32;public_flat*/`, etc., metacomments. See
+   also :ref:`VPI Example`.
 
 .. option:: profile_data -mtask "<mtask_hash>" -cost <cost_value>
 
@@ -1854,7 +1853,7 @@ The grammar of configuration commands is as follows:
 .. option:: sc_bv -module "<modulename>" [-function "<funcname>"] -var "<signame>"
 
    Sets the port to be of :code:`sc_bv<{width}>` type, instead of bool,
-   uint32_t or uint64_t.  Same as :option:`/*verilator&32;sc_bv*/`
+   uint32_t, or uint64_t.  Same as :option:`/*verilator&32;sc_bv*/`
    metacomment.
 
 .. option:: sformat [-module "<modulename>"] [-task "<taskname>"] -var "<signame>"
@@ -1862,9 +1861,9 @@ The grammar of configuration commands is as follows:
 .. option:: sformat [-module "<modulename>"] [-function "<funcname>"] -var "<signame>"
 
    Must be applied to the final argument of type :code:`input string` of a
-   function or task to indicate the function or task should pass all
-   remaining arguments through $sformatf.  This allows creation of DPI
-   functions with $display like behavior.  See the
+   function or task to indicate that the function or task should pass all
+   remaining arguments through $sformatf.  This allows the creation of DPI
+   functions with $display-like behavior.  See the
    :file:`test_regress/t/t_dpi_display.v` file for an example.
 
    Same as :option:`/*verilator&32;sformat*/` metacomment.
@@ -1875,7 +1874,7 @@ The grammar of configuration commands is as follows:
 
    Break the variable into multiple pieces typically to resolve UNOPTFLAT
    performance issues. Typically the variables to attach this to are
-   recommended by Verilator itself, see :option:`UNOPTFLAT`.
+   recommended by Verilator itself; see :option:`UNOPTFLAT`.
 
    Same as :option:`/*verilator&32;split_var*/` metacomment.
 
@@ -1914,10 +1913,10 @@ The grammar of configuration commands is as follows:
 
    With -scope enable/disable waveform tracing for the specified scope (or
    wildcard with '\*' or '?'), and optional --levels number of levels
-   below.  These controls only take place after other file/line/module
-   based controls have indicated the signal should be traced.
+   below.  These controls only operate after other file/line/module-based
+   controls have indicated the signal should be traced.
 
    With -levels (used with -scope), the number of levels below that
    scope which the rule is to match, where 0 means all levels below, 1
-   the exact level as the provided scope, and 2 meaning an additional
+   the exact level as the provided scope, and 2 means an additional
    level of children below the provided scope, etc.
diff --git a/docs/guide/exe_verilator_coverage.rst b/docs/guide/exe_verilator_coverage.rst
index 2bd93e7c0..a041b5064 100644
--- a/docs/guide/exe_verilator_coverage.rst
+++ b/docs/guide/exe_verilator_coverage.rst
@@ -12,8 +12,8 @@ coverage points exist on the same source code line, additional lines will
 be inserted to report the additional points.
 
 Additional Verilog-XL-style standard arguments specify the search paths
-necessary to find the source code that the coverage analysis was performed
-on.
+necessary to find the source code on which the coverage analysis was
+performed.
 
 To filter those items to be included in coverage, you may read
 logs/coverage.dat into an editor and do a M-x keep-lines to include only
@@ -24,7 +24,7 @@ statement to the appropriate statement block, or see
 :option:`/*verilator&32;coverage_off*/`.  This will remove the coverage
 points after the model is re-Verilated.
 
-For an overview of use of verilator_coverage, see :ref:`Coverage Analysis`.
+For an overview of the use of verilator_coverage, see :ref:`Coverage Analysis`.
 
 
 verilator_coverage Example Usage
@@ -50,25 +50,25 @@ verilator_coverage Arguments
 .. option:: <filename>
 
 Specifies the input coverage data file.  Multiple filenames may be provided
-to read multiple inputs.  If no data file is specified, by default
+to read multiple inputs.  If no data file is specified, by default,
 "coverage.dat" will be read.
 
 .. option:: --annotate <output_directory>
 
-Specifies the directory name that source files with annotated coverage data
-should be written to.
+Specifies the directory name to which source files with annotated coverage
+data should be written.
 
 .. option:: --annotate-all
 
 Specifies all files should be shown.  By default, only those source files
-which have low coverage are written to the output directory.
+with low coverage are written to the output directory.
 
 .. option:: --annotate-min <count>
 
 Specifies if the coverage point does not include the count number of
 coverage hits, then the coverage point will be considered above the
 threshold, and the coverage report will put a "%" to indicate the coverage
-is not sufficient.  Defaults to 10.
+is insufficient.  Defaults to 10.
 
 .. option:: --help
 
@@ -78,12 +78,12 @@ Displays a help summary, the program version, and exits.
 
 Prints an experimental report listing the relative importance of each test
 in covering all of the coverage points.  The report shows "Covered" which
-indicates the number of points that test covers; a test is considered to
+indicates the number of points the test covers; a test is considered to
 cover a point if it has a bucket count of at least 1. The "rank" column has
-a higher number t indicate the test is more important, and rank 0 means the
+a higher number t indicate the test is more critical, and rank 0 means the
 test does not need to be run to cover the points.  "RankPts" indicates the
 number of coverage points this test will contribute to overall coverage if
-all tests are run in the order of highest to lowest rank.
+all tests are run in the order of highest to the lowest rank.
 
 .. option:: --unlink
 
@@ -98,8 +98,8 @@ Displays program version and exits.
 
 Specifies the aggregate coverage results, summed across all the files,
 should be written to the given filename in verilator_coverage data format.
-This is useful for use in scripts to combine many coverage data files
-(likely generated from random test runs) into one master coverage file.
+This is useful in scripts to combine many coverage data files (likely
+generated from random test runs) into one master coverage file.
 
 .. option:: --write-info <filename.info>
 
@@ -108,7 +108,8 @@ should be written to the given filename in :command:`lcov` .info format.
 This may be used to feed into :command:`lcov` to aggregate or generate
 reports.
 
-The info format loses data compared to the Verilator coverage data format;
-the info will all forms of coverage converted to line style coverage, and
-if there are multiple coverage points on a single line, the minimum
-coverage across those points will be used to report coverage of the line.
+Converting from the Verilator coverage data format to the info format is
+lossy; the info will have all forms of coverage merged line coverage, and
+if there are multiple coverage points on a single line they will merge.
+The minimum coverage across all merged points will be used to report
+coverage of the line.
diff --git a/docs/guide/exe_verilator_gantt.rst b/docs/guide/exe_verilator_gantt.rst
index c7054214b..3c933407d 100644
--- a/docs/guide/exe_verilator_gantt.rst
+++ b/docs/guide/exe_verilator_gantt.rst
@@ -5,16 +5,16 @@ verilator_gantt
 ===============
 
 Verilator_gantt creates a visual representation to help analyze Verilator
-multithreaded simulation performance, by showing when each macro-task
-starts and ends, and showing when each thread is busy or idle.
+multithreaded simulation performance by showing when each macro-task
+starts, ends, and when each thread is busy or idle.
 
-For an overview of use of verilator_gantt, see :ref:`Profiling`.
+For an overview of the use of verilator_gantt, see :ref:`Profiling`.
 
 Gantt Chart VCD
 ---------------
 
 Verilated_gantt creates a value change dump (VCD) format dump file which
-may be viewed in a waveform viewer (e.g. C<GTKWave>):
+may be viewed in a waveform viewer (e.g., C<GTKWave>):
 
 .. figure:: figures/fig_gantt_min.png
 
@@ -27,9 +27,8 @@ time tick of the system's high-performance counter.
 Gantt Chart VCD Signals
 -----------------------
 
-In waveforms there are the following signals. In GTKWave, using a data
-format of "decimal" will remove the leading zeros and make the traces
-easier to read.
+In waveforms, there are the following signals. In GTKWave, use "decimal"
+data format to remove the leading zeros and make the traces easier to read.
 
 evals
   Increments each time when eval_step was measured to be active.  This
@@ -37,12 +36,12 @@ evals
 
 eval_loop
   Increments each time when the evaluation loop within eval_step was
-  measured to be active.  For best performance there is only a single
-  evaluation loop within each eval_step call, that is the eval_loop
+  measured to be active.  For best performance, there is only a single
+  evaluation loop within each eval_step call; that is, the eval_loop
   waveform looks identical to the evals waveform.
 
 measured_parallelism
-  The number of mtasks active at this time, for best performance this will
+  The number of mtasks active at this time, for best performance, this will
   match the thread count. In GTKWave, use a data format of "analog step" to
   view this signal.
 
@@ -72,7 +71,7 @@ verilator_gantt Arguments
 
 .. option:: <filename>
 
-The filename to read data from, defaults to "profile_exec.dat".
+The filename to read data from; the default is "profile_exec.dat".
 
 .. option:: --help
 
@@ -84,4 +83,4 @@ Disables creating a .vcd file.
 
 .. option:: --vcd <filename>
 
-Sets the output filename for vcd dump. Default is "verilator_gantt.vcd".
+Sets the output filename for vcd dump; the default is "verilator_gantt.vcd".
diff --git a/docs/guide/exe_verilator_profcfunc.rst b/docs/guide/exe_verilator_profcfunc.rst
index 408db9e76..b33a5f5fc 100644
--- a/docs/guide/exe_verilator_profcfunc.rst
+++ b/docs/guide/exe_verilator_profcfunc.rst
@@ -6,14 +6,14 @@ verilator_profcfunc
 
 Verilator_profcfunc reads a profile report created by gprof.  The names of
 the functions are then transformed, assuming the user used Verilator's
---prof-cfuncs, and a report printed showing the percentage of time, etc, in
-each Verilog block.
+--prof-cfuncs, and a report printed showing the percentage of the time,
+etc., in each Verilog block.
 
 Due to rounding errors in gprof reports, the input report's percentages may
-not total to 100%.  In the verilator_profcfunc report this will get
+not total 100%.  In the verilator_profcfunc report this will get
 reported as a rounding error.
 
-For an overview of use of verilator_profcfunc, see :ref:`Profiling`.
+For an overview of the use of verilator_profcfunc, see :ref:`Profiling`.
 
 verilator_profcfunc Arguments
 -----------------------------
diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst
index 24098c5ea..03c2f4f47 100644
--- a/docs/guide/extensions.rst
+++ b/docs/guide/extensions.rst
@@ -12,14 +12,14 @@ or "`ifdef`"'s may break other tools.
 .. option:: `__FILE__
 
    The :option:`\`__FILE__` define expands to the current filename as a
-   string, like C++'s __FILE__.  This Verilator feature added in 2006 was
-   incorporated into the IEEE 1800-2009 standard.
+   string, like C++'s __FILE__.  This Verilator feature, added in 2006, was
+   incorporated into IEEE 1800-2009.
 
 .. option:: `__LINE__
 
    The :option:`\`__LINE__` define expands to the current filename as a
    string, like C++'s __LINE__.  This Verilator feature added in 2006 was
-   incorporated into the IEEE 1800-2009 standard.
+   incorporated into IEEE 1800-2009.
 
 .. option:: `error [string]
 
@@ -27,7 +27,7 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: """ [string] """
 
-   A triple-quoted block specifies a string which may include newlines and
+   A triple-quoted block specifies a string that may include newlines and
    single quotes.  This extension is experimental and may be removed
    without deprecation.
 
@@ -51,24 +51,24 @@ or "`ifdef`"'s may break other tools.
    rather than hard-coding variable names in the string
    :code:`$c("func(a)")`, instead pass the variable as an expression
    ::code:`$c("func(",a,")")`.  This will allow the call to work inside
-   Verilog functions where the variable is flattened out, and also enable
-   other optimizations.
+   Verilog functions where the variable is flattened out and enable other
+   optimizations.
 
    Verilator does not use any text inside the quotes for
    ordering/scheduling.  If you need the $c to be called at a specific
-   time, e.g. when a variable changes, then the $c must be under an
-   appropriate sensitivity statement, e.g.
-   :code:`always @(posedge clk) $c("func()")` to call it on every edge, or
-   e.g. :code:`always @* c("func(",a,")")` to call it when :code:`a`
+   time, e.g., when a variable changes, then the $c must be under an
+   appropriate sensitivity statement, e.g.,
+   :code:`always @(posedge clk) $c("func()")` to call it on every edge, or,
+   e.g., :code:`always @* c("func(",a,")")` to call it when :code:`a`
    changes (the latter working because :code:`a` is outside the quotes).
 
    If you will be reading or writing any Verilog variables inside the C++
    functions, the Verilog signals must be declared with
    :option:`/*verilator&32;public*/` metacomments.
 
-   You may also append an arbitrary number to $c, generally the width of
-   the output; :code:`signal_32_bits = $c32("...");`.  This allows for
-   compatibility with other simulators which require a differently named
+   You may also append a number to $c, which specifies the bit width of
+   the output, e.g., :code:`signal_32_bits = $c32("...");`.  This allows for
+   compatibility with other simulators, which require a differently named
    PLI function name for each different output width.
 
 .. option:: $display, $write, $fdisplay, $fwrite, $sformat, $swrite
@@ -76,8 +76,8 @@ or "`ifdef`"'s may break other tools.
    Format arguments may use C fprintf sizes after the % escape.  Per the
    Verilog standard, %x prints a number with the natural width, and %0x
    prints a number with minimum width.  Verilator extends this so %5x
-   prints 5 digits per the C standard (this is unspecified in Verilog, but
-   was incorporated into the 1800-2009).
+   prints 5 digits per the C standard. This extension was standardized into
+   1800-2009.
 
 .. option:: $timeprecision
 
@@ -92,55 +92,55 @@ or "`ifdef`"'s may break other tools.
 .. option:: `coverage_block_off
 
    Specifies the entire begin/end block should be ignored for coverage
-   analysis.  Must be inside a code block, e.g. within a begin/end pair.
+   analysis.  Must be inside a code block, e.g., within a begin/end pair.
    Same as :option:`coverage_block_off` in :ref:`Configuration Files`.
 
 .. option:: `systemc_header
 
-   Take remaining text up to the next :option:`\`verilog` or
+   Take the remaining text up to the next :option:`\`verilog` or
    :option:`\`systemc_... <\`systemc_header>` mode switch and place it
    verbatim into the output .h file's header.  Must be placed as a module
-   item, e.g. directly inside a module/endmodule pair. Despite the name of
+   item, e.g., directly inside a module/endmodule pair. Despite the name of
    this macro, this also works in pure C++ code.
 
 .. option:: `systemc_ctor
 
-   Take remaining text up to the next :option:`\`verilog` or
+   Take the remaining text up to the next :option:`\`verilog` or
    :option:`\`systemc_... <\`systemc_header>` mode switch and place it
    verbatim into the C++ class constructor.  Must be placed as a module
-   item, e.g. directly inside a module/endmodule pair. Despite the name of
+   item, e.g., directly inside a module/endmodule pair. Despite the name of
    this macro, this also works in pure C++ code.
 
 .. option:: `systemc_dtor
 
-   Take remaining text up to the next :option:`\`verilog` or
+   Take the remaining text up to the next :option:`\`verilog` or
    :option:`\`systemc_... <\`systemc_header>` mode switch and place it
    verbatim into the C++ class destructor.  Must be placed as a module
-   item, e.g. directly inside a module/endmodule pair. Despite the name of
+   item, e.g., directly inside a module/endmodule pair. Despite the name of
    this macro, this also works in pure C++ code.
 
 .. option:: `systemc_interface
 
-   Take remaining text up to the next :option:`\`verilog` or
+   Take the remaining text up to the next :option:`\`verilog` or
    :option:`\`systemc_... <\`systemc_header>` mode switch and place it
    verbatim into the C++ class interface.  Must be placed as a module item,
-   e.g. directly inside a module/endmodule pair. Despite the name of this
+   e.g., directly inside a module/endmodule pair. Despite the name of this
    macro, this also works in pure C++ code.
 
 .. option:: `systemc_imp_header
 
-   Take remaining text up to the next :option:`\`verilog` or
+   Take the remaining text up to the next :option:`\`verilog` or
    :option:`\`systemc_... <\`systemc_header>` mode switch and place it
    verbatim into the header of all files for this C++ class implementation.
-   Must be placed as a module item, e.g. directly inside a module/endmodule
+   Must be placed as a module item, e.g., directly inside a module/endmodule
    pair. Despite the name of this macro, this also works in pure C++ code.
 
 .. option:: `systemc_implementation
 
-   Take remaining text up to the next :option:`\`verilog` or
+   Take the remaining text up to the next :option:`\`verilog` or
    :option:`\`systemc_... <\`systemc_header>` mode switch and place it
    verbatim into a single file of the C++ class implementation.  Must be
-   placed as a module item, e.g. directly inside a module/endmodule
+   placed as a module item, e.g., directly inside a module/endmodule
    pair. Despite the name of this macro, this also works in pure C++ code.
 
    If you will be reading or writing any Verilog variables in the C++
@@ -150,7 +150,7 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: `SYSTEMVERILOG
 
-   The SYSTEMVERILOG, SV_COV_START and related standard defines are set by
+   The SYSTEMVERILOG, SV_COV_START, and related standard defines are set by
    default when :vlopt:`--language <--language>` is "1800-\*".
 
 .. option:: `VERILATOR
@@ -164,13 +164,13 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: `verilator_config
 
-   Take remaining text up to the next :option:`\`verilog` mode switch and
+   Take the remaining text up to the next :option:`\`verilog` mode switch and
    treat it as Verilator configuration commands.  See :ref:`Configuration Files`.
 
 .. option:: `VERILATOR_TIMING
 
    The VERILATOR_TIMING define is set when :vlopt:`--timing` is used to
-   allow an "\`ifdef" of code dependent on this feature.  Note this define
+   allow an "\`ifdef" of code dependent on this feature.  Note that this define
    is not affected by the :option:`timing_off` configuration file option
    nor timing metacomments.
 
@@ -185,10 +185,10 @@ or "`ifdef`"'s may break other tools.
 
    Deprecated and has no effect (ignored).
 
-   In versions prior to 5.000:
+   In versions before 5.000:
 
    Used after a signal declaration to indicate the signal is used to gate a
-   clock, and the user takes responsibility for insuring there are no races
+   clock, and the user is responsible for ensuring there are no races
    related to it. (Typically by adding a latch, and running static timing
    analysis.) For example:
 
@@ -209,7 +209,7 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: /*verilator&32;no_clocker*/
 
-   Specifies that the signal is used as clock or not. See :vlopt:`--clk`.
+   Specifies whether the signal is used as clock or not. See :vlopt:`--clk`.
 
    Same as :option:`clocker` and :option:`no_clocker` in configuration
    files.
@@ -223,12 +223,12 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: /*verilator&32;coverage_off*/
 
-   Specifies that following lines of code should have coverage disabled.
+   Specifies that that following lines of code should have coverage disabled.
    Often used to ignore an entire module for coverage analysis purposes.
 
 .. option:: /*verilator&32;coverage_on*/
 
-   Specifies that following lines of code should have coverage re-enabled
+   Specifies that that following lines of code should have coverage re-enabled
    (if appropriate :vlopt:`--coverage` flags are passed) after being
    disabled earlier with :option:`/*verilator&32;coverage_off*/`.
 
@@ -236,7 +236,7 @@ or "`ifdef`"'s may break other tools.
 
    Specifies that the signal (net or variable) should be made forceable from
    C++ code by generating public `<signame>__VforceEn` and
-   `<signame>__VforceVal` signals The force control signals are created as
+   `<signame>__VforceVal` signals. The force control signals are created as
    :option:`public_flat` signals.
 
    To force a marked signal from C++, set the corresponding `__VforceVal`
@@ -251,7 +251,7 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: /*verilator&32;hier_block*/
 
-   Specifies that the module is an unit of hierarchical Verilation.  This
+   Specifies that the module is a unit of hierarchical Verilation.  This
    metacomment must be between :code:`module module_name(...);` and
    :code:`endmodule`.  The module will not be inlined nor uniquified for
    each instance in hierarchical Verilation.  Note that the metacomment is
@@ -272,10 +272,10 @@ or "`ifdef`"'s may break other tools.
 .. option:: /*verilator&32;isolate_assignments*/
 
    Used after a signal declaration to indicate the assignments to this
-   signal in any blocks should be isolated into new blocks.  When there is
-   a large combinatorial block that is resulting in an ``UNOPTFLAT``
-   warning, attaching this to the signal causing a false loop may clear up
-   the problem.
+   signal in any blocks should be isolated into new blocks.  When large
+   combinatorial block results in a :option:`UNOPTFLAT` warning, attaching
+   this to the signal that was causing a false loop may work around the
+   warning.
 
    IE, with the following:
 
@@ -329,7 +329,7 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: /*verilator&32;lint_save*/
 
-   Push the current state of what lint messages are turned on or turned off
+   Push the current state of what lint messages are turned on or off
    to a stack.  Later meta-comments may then lint_on or lint_off specific
    messages, then return to the earlier message state by using
    :code:`/*verilator&32;lint_restore*/`.  For example:
@@ -341,8 +341,8 @@ or "`ifdef`"'s may break other tools.
          ...  // code needing WIDTH turned off
          // verilator lint_restore
 
-   If WIDTH was on before the lint_off, it will now be restored to on, and
-   if it was off before the lint_off it will remain off.
+   If WIDTH was on before the lint_off, it would now be restored to on, and
+   if it was off before the lint_off it would remain off.
 
 .. option:: /*verilator&32;no_inline_module*/
 
@@ -386,13 +386,12 @@ or "`ifdef`"'s may break other tools.
 
    Used after an input, output, register, or wire declaration to indicate
    the signal should be declared so that C code may read or write the value
-   of the signal.  This will also declare this module public, otherwise use
+   of the signal.  This will also declare this module public; otherwise, use
    :code:`/*verilator&32;public_flat*/`.
 
-   Instead of using public variables, consider instead making a DPI or
-   public function that accesses the variable.  This is nicer as it
-   provides an obvious entry point that is also compatible across
-   simulators.
+   Instead of using public variables, consider making a DPI or public
+   function that accesses the variable.  This is nicer as it provides an
+   obvious entry point compatible across simulators.
 
    Same as :option:`public` configuration file option.
 
@@ -402,7 +401,7 @@ or "`ifdef`"'s may break other tools.
    indicate the function or task should be made into a C++ function, public
    to outside callers.  Public tasks will be declared as a void C++
    function, public functions will get the appropriate non-void (bool,
-   uint32_t, etc) return type.  Any input arguments will become C++
+   uint32_t, etc.) return type.  Any input arguments will become C++
    arguments to the function.  Any output arguments will become C++
    reference arguments.  Any local registers/integers will become function
    automatic variables on the stack.
@@ -440,10 +439,10 @@ or "`ifdef`"'s may break other tools.
 .. option:: /*verilator&32;public_flat_rw @(<edge_list>)*/ (on variable)
 
    Used after an input, output, register, or wire declaration to indicate
-   the signal should be declared public_flat_rd (see above), and also
-   writable, where writes should be considered to have the timing specified
-   by the given sensitivity edge list.  Set for all variables, ports and
-   wires using the :vlopt:`--public-flat-rw` option.
+   the signal should be declared public_flat_rd (see above), and writable,
+   where writes should be considered to have the timing specified by the
+   given sensitivity edge list. Use of this is implied when using the
+   :vlopt:`--public-flat-rw` option.
 
    Same as :option:`public_flat_rw` configuration file option.
 
@@ -452,8 +451,8 @@ or "`ifdef`"'s may break other tools.
    Used after a module statement to indicate the module should not be
    inlined (unless specifically requested) so that C code may access the
    module.  Verilator automatically sets this attribute when the module
-   contains any public signals or \`systemc_ directives.  Also set for all
-   modules when using the :vlopt:`--public` option.
+   contains public signals or \`systemc_ directives.  Use of this is
+   implied when using the :vlopt:`--public` option.
 
    Same as :option:`public` configuration file option.
 
@@ -462,27 +461,26 @@ or "`ifdef`"'s may break other tools.
    Deprecated and ignored.  Previously used after an input declaration to
    indicate the signal should be declared in SystemC as a sc_clock instead
    of a bool.  This was needed in SystemC 1.1 and 1.2 only; versions 2.0
-   and later do not require clock pins to be sc_clocks and this is no
+   and later do not require clock pins to be sc_clocks, and this is no
    longer needed and is ignored.
 
 .. option:: /*verilator&32;sc_bv*/
 
    Used after a port declaration.  It sets the port to be of
-   :code:`sc_bv<{width}>` type, instead of bool, uint32_t or uint64_t.
+   :code:`sc_bv<{width}>` type, instead of bool, uint32_t, or uint64_t.
    This may be useful if the port width is parameterized and the
-   instantiating C++ code wants to always have a sc_bv so it can accept any
-   width.  In general you should avoid using this attribute when not
-   necessary as with increasing usage of sc_bv the performance decreases
-   significantly.
+   instantiating C++ code always wants to have a sc_bv accept any width.
+   In general, you should avoid using this attribute when unnecessary, as
+   the performance decreases significantly with increasing usage of sc_bv.
 
    Same as :option:`sc_bv` configuration file option.
 
 .. option:: /*verilator&32;sformat*/
 
    Attached to the final argument of type "input string" of a function or
-   task to indicate the function or task should pass all remaining
+   task to indicate that the function or task should pass all remaining
    arguments through $sformatf.  This allows creation of DPI functions with
-   $display like behavior.  See the :file:`test_regress/t/t_dpi_display.v`
+   $display-like behavior.  See the :file:`test_regress/t/t_dpi_display.v`
    file for an example.
 
    Same as :option:`sformat` configuration file option.
@@ -492,7 +490,7 @@ or "`ifdef`"'s may break other tools.
    Attached to a variable or a net declaration to break the variable into
    multiple pieces typically to resolve ``UNOPTFLAT`` performance issues.
    Typically the variables to attach this to are recommended by Verilator
-   itself, see :option:`UNOPTFLAT`.
+   itself; see :option:`UNOPTFLAT`.
 
    For example, Verilator will internally convert a variable with the
    metacomment such as:
@@ -509,12 +507,12 @@ or "`ifdef`"'s may break other tools.
          logic [7:0] x__BRA__1__KET__ /*verilator split_var*/;
 
    Note that the generated packed variables retain the split_var
-   metacomment because they may be split into further smaller pieces
-   according to the access patterns.
+   metacomment because they may be split into smaller pieces according to
+   the access patterns.
 
    This only supports unpacked arrays, packed arrays, and packed structs of
-   integer types (reg, logic, bit, byte, int...); otherwise if a split was
-   requested but cannot occur a SPLITVAR warning is issued.  Splitting
+   integer types (reg, logic, bit, byte, int...); otherwise, if a split was
+   requested but cannot occur, a SPLITVAR warning is issued.  Splitting
    large arrays may slow down the Verilation speed, so use this only on
    variables that require it.
 
@@ -551,10 +549,10 @@ or "`ifdef`"'s may break other tools.
 
 .. option:: /*verilator&32;tracing_off*/
 
-   Disable waveform tracing for all future signals that are declared in
-   this module, or instances below this module.  Often this is placed just
-   after a primitive's module statement, so that the entire module and
-   instances below it are not traced.
+   Disable waveform tracing for all future signals declared in this module,
+   or instances below this module.  Often this is placed just after a
+   primitive's module statement, so that the entire module and instances
+   below it are not traced.
 
 .. option:: /*verilator&32;tracing_on*/
 
@@ -565,9 +563,8 @@ or "`ifdef`"'s may break other tools.
 
    Called as a task, print a stack trace.  Called as a function, return a
    string with a stack trace.  This relies on the C++ system trace, which
-   may give less meaningful results if the model was not compiled with
-   debug symbols.  Also the data represents the C++ stack, the
-   SystemVerilog functions/tasks involved may be renamed and/or inlined
-   before becoming the C++ functions that may be visible in the stack
-   trace.  This extension is experimental and may be removed without
-   deprecation.
+   may give less meaningful results if the model is not compiled with debug
+   symbols.  Also, the data represents the C++ stack; the SystemVerilog
+   functions/tasks involved may be renamed and/or inlined before becoming
+   the C++ functions that may be visible in the stack trace.  This
+   extension is experimental and may be removed without deprecation.
diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst
index 46d52a3b5..8ca36573c 100644
--- a/docs/guide/faq.rst
+++ b/docs/guide/faq.rst
@@ -14,8 +14,8 @@ Can I contribute?
 """""""""""""""""
 
 Please contribute!  Just submit a pull request, or raise an issue to
-discuss if looking for something to help on.  For more information see our
-contributor agreement.
+discuss if you are looking for something to help on.  For more information
+see our contributor agreement.
 
 
 How widely is Verilator used?
@@ -24,7 +24,7 @@ How widely is Verilator used?
 Verilator is used by many of the largest silicon design companies, large
 organizations such as CERN, and even by college student projects.
 
-Verilator is one of the "big 4" simulators, meaning one of the 4 main
+Verilator is one of the "big 4" simulators, meaning one of the four leading
 SystemVerilog simulators available, namely the closed-source products Synopsys
 VCS (tm), Mentor Questa/ModelSim (tm), Cadence
 Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator.
@@ -35,8 +35,8 @@ simulators.
 Does Verilator run under Windows?
 """""""""""""""""""""""""""""""""
 
-Yes, ideally run Ubuntu under Windows Subsystem for Linux (WSL2).
-Alternatively use Cygwin, though this tends to be slower and is not
+Yes, ideally, run Ubuntu under Windows Subsystem for Linux (WSL2).
+Alternatively, use Cygwin, though this tends to be slower and is not
 regularly tested.  Verilated output also compiles under Microsoft Visual
 C++, but this is also not regularly tested.
 
@@ -58,14 +58,14 @@ How can it be faster than (name-a-big-3-closed-source-simulator)?
 Generally, the implied part of the question is "... with all of the
 manpower they can put into developing it."
 
-Most simulators have to be compliant with the complete IEEE 1364 (Verilog)
-and IEEE 1800 (SystemVerilog) standards, meaning they have to be event
-driven.  This prevents them from being able to reorder blocks and make
-netlist-style optimizations, which are where most of the gains come from.
+Most simulators must comply with the complete IEEE 1364 (Verilog) and IEEE
+1800 (SystemVerilog) standards, meaning they have to be event-driven.  This
+prevents them from being able to reorder blocks and make netlist-style
+optimizations, which are where most of the gains come from.
 
 You should not be scared by non-compliance.  Your synthesis tool isn't
 compliant with the whole standard to start with, so your simulator need not
-be either.  Verilator is closer to the synthesis interpretation, so this is
+be either.  Verilator is closer to the synthesis interpretation, which is
 a good thing for getting working silicon.
 
 
@@ -81,17 +81,17 @@ the licenses for details.
 
 Some examples:
 
-* Any SystemVerilog or other input fed into Verilator remain your own.
+* Any SystemVerilog or other input fed into Verilator remains your own.
 
 * Any of your VPI/DPI C++ routines that Verilator calls remain your own.
 
-* Any of your main() C++ code that calls into Verilator remain your own.
+* Any of your main() C++ code that calls into Verilator remains your own.
 
-* If you change Verilator itself, for example changing or adding a file
+* If you change Verilator itself, for example, changing or adding a file
   under the src/ directory in the repository, you must make the source code
   available under the GNU Lesser Public License.
 
-* If you change a header Verilator provides, for example under include/ in
+* If you change a header Verilator provides, for example, under include/ in
   the repository, you must make the source code available under the GNU
   Lesser Public License.
 
@@ -101,9 +101,9 @@ license also allows you to modify Verilator for internal use without
 distributing the modified version.  But please contribute back to the
 community!
 
-Under both license you can offer a commercial product that is based on
-Verilator either directly or embedded within.  However under both licenses,
-any changes you make to Verilator for such a product must be open sourced.
+Under both licenses, you can offer a commercial product based on
+Verilator directly or embedded within.  However, under both licenses,
+any changes you make to Verilator for such a product must be open-sourced.
 
 As is standard with Open Source, contributions back to Verilator will be
 placed under the Verilator copyright and LGPL/Artistic license.  Small test
@@ -114,11 +114,11 @@ and large tests under the LGPL/Artistic, unless requested otherwise.
 Why is running Verilator (to create a model) so slow?
 """""""""""""""""""""""""""""""""""""""""""""""""""""
 
-Verilator may require more memory than the resulting simulator will
-require, as Verilator internally creates all of the state of the resulting
-generated simulator in order to optimize it.  If it takes more than a few
+Verilator may require more memory than the resulting simulation,
+as Verilator internally creates all of the state of the resulting
+generated simulator to optimize it.  If it takes more than a few
 minutes or so (and you're not using :vlopt:`--debug` since debug mode is
-disk bound), see if your machine is paging; most likely you need to run it
+disk bound), see if your machine is paging; most likely, you need to run it
 on a machine with more memory. Very large designs are known to have topped
 64 GB resident set size.  Alternatively, see :ref:`Hierarchical Verilation`.
 
@@ -128,14 +128,14 @@ How do I generate waveforms (traces) in C++?
 
 See also the next question for tracing in SystemC mode.
 
-A. Pass the :vlopt:`--trace` option to Verilator, and in your top level C
+A. Pass the :vlopt:`--trace` option to Verilator, and in your top-level C
    code, call ``Verilated::traceEverOn(true)``.  Then you may use
-   ``$dumpfile`` and ``$dumpvars`` to enable traces, same as with any
+   ``$dumpfile`` and ``$dumpvars`` to enable traces, the same as with any
    Verilog simulator. See ``examples/make_tracing_c`` in the distribution.
 
 B. Or, for finer-grained control, or C++ files with multiple Verilated
-   modules you may also create the trace purely from C++.  Create a
-   VerilatedVcdC object, and in your main loop right after ``eval()`` call
+   modules, you may also create the trace purely from C++.  Create a
+   VerilatedVcdC object, and in your main loop, right after ``eval()`` call
    ``trace_object->dump(contextp->time())`` every time step, and finally
    call ``trace_object->close()``.
 
@@ -163,8 +163,8 @@ B. Or, for finer-grained control, or C++ files with multiple Verilated
 
 You also need to compile :file:`verilated_vcd_c.cpp` and add it to your
 link, preferably by adding the dependencies in your Makefile's
-:code:`$(VK_GLOBAL_OBJS)` link rule.  This is done for you if using the
-Verilator :vlopt:`--exe` option.
+:code:`$(VK_GLOBAL_OBJS)` link rule.  This is done for you if you are using
+the Verilator :vlopt:`--binary` or :vlopt:`--exe` option.
 
 you can call :code:`trace_object->trace()` on multiple Verilated objects
 with the same trace file if you want all data to land in the same output
@@ -174,22 +174,22 @@ file.
 How do I generate waveforms (traces) in SystemC?
 """"""""""""""""""""""""""""""""""""""""""""""""
 
-A. Pass the :vlopt:`--trace` option to Verilator, and in your top level
+A. Pass the :vlopt:`--trace` option to Verilator, and in your top-level
    :code:`sc_main()`, call :code:`Verilated::traceEverOn(true)`.  Then you
-   may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, same as
-   with any Verilog simulator, see the non-SystemC example in
+   may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, as
+   with any Verilog simulator; see the non-SystemC example in
    :file:`examples/make_tracing_c`. This will trace only the module
    containing the :code:`$dumpvar`.
 
 B. Or, you may create a trace purely from SystemC, which may trace all
    Verilated designs in the SystemC model. Create a VerilatedVcdSc object
-   as you would create a normal SystemC trace file.  For an example, see
+   as you would create a standard SystemC trace file.  For an example, see
    the call to ``VerilatedVcdSc`` in the
    :file:`examples/make_tracing_sc/sc_main.cpp` file of the distribution,
    and below.
 
-C. Alternatively you may use the C++ trace mechanism described in the
-   previous question, note the timescale and timeprecision will be
+C. Alternatively, you may use the C++ trace mechanism described in the
+   previous question; note that the timescale and timeprecision will be
    inherited from your SystemC settings.
 
    .. code-block:: C++
@@ -214,13 +214,14 @@ C. Alternatively you may use the C++ trace mechanism described in the
 You also need to compile :file:`verilated_vcd_sc.cpp` and
 :file:`verilated_vcd_c.cpp` and add them to your link, preferably by adding
 the dependencies in your Makefile's :code:`$(VK_GLOBAL_OBJS)` link rule.
-This is done for you if using the Verilator :vlopt:`--exe` option.
+This is done for you if you are using the Verilator :vlopt:`--binary` or
+:vlopt:`--exe` option.
 
 You can call :code:`->trace()` on multiple Verilated objects with the same
 trace file if you want all data to land in the same output file.
 
 When using SystemC 2.3, the SystemC library must have been built with the
-experimental simulation phase callback based tracing disabled. This is
+experimental simulation phase callback-based tracing disabled. This is
 disabled by default when building SystemC with its configure based build
 system, but when building SystemC with CMake, you must pass
 ``-DENABLE_PHASE_CALLBACKS_TRACING=OFF`` to disable this feature.
@@ -242,7 +243,7 @@ Or, in C++ change the include described in the VCD example above:
       VerilatedFstC* tfp = new VerilatedFstC;
 
 
-Or, in SystemC change the include described in the VCD example above:
+Or, in SystemC, change the include described in the VCD example above:
 
 .. code-block:: C++
 
@@ -250,17 +251,16 @@ Or, in SystemC change the include described in the VCD example above:
       VerilatedFstC* tfp = new VerilatedFstSc;
 
 
-Note that currently supporting both FST and VCD in a single simulation is
-impossible, but such requirement should be rare.  You can however ifdef
-around the trace format in your C++ main loop, and select VCD or FST at
-build time, should you require.
+Currently, supporting FST and VCD in a single simulation is impossible, but
+such requirement should be rare.  You can however ifdef around the trace
+format in your C++ main loop, and select VCD or FST at compile time.
 
 
 How do I view waveforms (aka dumps or traces)?
 """"""""""""""""""""""""""""""""""""""""""""""
 
 Verilator creates standard VCD (Value Change Dump) and FST files.  VCD
-files are viewable with the open source GTKWave (recommended) or Dinotrace
+files are viewable with the open-source GTKWave (recommended), or Dinotrace
 (legacy) programs, or any of the many closed-source offerings; FST is
 supported only by GTKWave.
 
@@ -273,20 +273,20 @@ A. Instead of calling ``VerilatedVcdC->open`` or ``$dumpvars`` at the
    tracing to begin.
 
 B. Add the :option:`/*verilator&32;tracing_off*/` metacomment to any very
-   low level modules you never want to trace (such as perhaps library
+   low-level modules you never want to trace (such as perhaps library
    cells).
 
-C. Use the :vlopt:`--trace-depth` option to limit the depth of tracing, for
-   example :vlopt:`--trace-depth 1 <--trace-depth>` to see only the top
-   level signals.
+C. Use the :vlopt:`--trace-depth` option to limit the tracing depth, for
+   example :vlopt:`--trace-depth 1 <--trace-depth>` to see only the
+   top-level signals.
 
 D. You can also consider using FST tracing instead of VCD. FST dumps are a
    fraction of the size of the equivalent VCD. FST tracing can be slower
    than VCD tracing, but it might be the only option if the VCD file size
    is prohibitively large.
 
-E. Be sure you write your trace files to a local solid-state drive, instead
-   of to a network drive.  Network drives are generally far slower.
+E. Write your trace files to a machine-local solid-state drive instead of a
+   network drive.  Network drives are generally far slower.
 
 
 Where is the translate_off command?  (How do I ignore a construct?)
@@ -313,7 +313,7 @@ Why do I get "unexpected 'do'" or "unexpected 'bit'" errors?
 
 The words \ ``do``\ , \ ``bit``\ , \ ``ref``\ , \ ``return``\ , and others
 are reserved keywords in SystemVerilog.  Older Verilog code might use these
-as identifiers.  You should change your code to not use them to ensure it
+as identifiers, and you should change your code to not use them to ensure it
 works with newer tools.  Alternatively, surround them by the Verilog
 2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code.
 
@@ -325,7 +325,7 @@ works with newer tools.  Alternatively, surround them by the Verilog
    `end_keywords
 
 
-If you want the whole design to be parsed as Verilog 2001, see the
+If you want the whole design parsed as Verilog 2001, see the
 :vlopt:`--default-language` option.
 
 
@@ -342,11 +342,11 @@ Why do I get "undefined reference to sc_time_stamp()?
 
 In Verilator 4.200 and later, using the timeInc function is recommended
 instead.  See the :ref:`Connecting to C++` examples.  Some linkers (MSVC++)
-still require :code:`sc_time_stamp()` to be defined, either define this
+still require :code:`sc_time_stamp()` to be defined; either define this
 with :code:`double sc_time_stamp() { return 0; }` or compile the Verilated
 code with :code:`-CFLAGS -DVL_TIME_CONTEXT`.
 
-Prior to Verilator 4.200, the :code:`sc_time_stamp()` function needs to be
+Before Verilator 4.200, the :code:`sc_time_stamp()` function needs to be
 defined in C++ (non SystemC) to return the current simulation time.
 
 
@@ -369,17 +369,17 @@ also use the "import DPI" SystemVerilog feature to call C code (see the
 chapter above).  There is also limited VPI access to public signals.
 
 If you want something more complex, since Verilator emits standard C++
-code, you can write your own C++ routines that can access and modify signal
+code, you can write C++ routines that can access and modify signal
 values without needing any PLI interface code, and call it with
 $c("{any_c++_statement}").
 
 See the :ref:`Connecting` section.
 
 
-How do I make a Verilog module that contain a C++ object?
-"""""""""""""""""""""""""""""""""""""""""""""""""""""""""
+How do I make a Verilog module that contains a C++ object?
+""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
-You need to add the object to the structure that Verilator creates, then
+You need to add the object to the structure Verilator creates, then
 use $c to call a method inside your object.  The
 :file:`test_regress/t/t_extend_class` files in the distribution show an
 example of how to do this.
@@ -388,9 +388,9 @@ example of how to do this.
 How do I get faster build times?
 """"""""""""""""""""""""""""""""
 
-* When running make, pass the make variable VM_PARALLEL_BUILDS=1 so that
+* When running make, pass the make variable VM_PARALLEL_BUILDS=1, so that
   builds occur in parallel. Note this is now set by default if an output
-  file was large enough to be split due to the :vlopt:`--output-split`
+  file is large enough to be split due to the :vlopt:`--output-split`
   option.
 
 * Verilator emits any infrequently executed "cold" routines into separate
@@ -401,17 +401,17 @@ How do I get faster build times?
 * Use a recent compiler.  Newer compilers tend to be faster.
 
 * Compile in parallel on many machines and use caching; see the web for the
-  ccache, distcc and icecream packages. ccache will skip GCC runs between
+  ccache, distcc, and icecream packages. ccache will skip GCC runs between
   identical source builds, even across different users.  If ccache was
-  installed when Verilator was built it is used, or see OBJCACHE
+  installed when Verilator was built, it is used, or see OBJCACHE
   environment variable to override this. Also see the
-  :vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`
+  :vlopt:`--output-split` option and :ref: `Profiling ccache efficiency`.
 
-* To reduce the compile time of classes that use a Verilated module (e.g. a
+* To reduce the compile time of classes that use a Verilated module (e.g., a
   top CPP file) you may wish to add a
-  :option:`/*verilator&32;no_inline_module*/` metacomment to your top level
+  :option:`/*verilator&32;no_inline_module*/` metacomment to your top-level
   module. This will decrease the amount of code in the model's Verilated
-  class, improving compile times of any instantiating top level C++ code,
+  class, improving compile times of any instantiating top-level C++ code,
   at a relatively small cost of execution performance.
 
 * Use :ref:`hierarchical verilation`.
@@ -421,7 +421,7 @@ Why do so many files need to recompile when I add a signal?
 """""""""""""""""""""""""""""""""""""""""""""""""""""""""""
 
 Adding a new signal requires the symbol table to be recompiled.  Verilator
-uses one large symbol table, as that results in 2-3 less assembly
+uses one large symbol table, resulting in 2-3 fewer assembly
 instructions for each signal access.  This makes the execution time 10-15%
 faster, but can result in more compilations when something changes.
 
@@ -449,8 +449,8 @@ How do I access signals in C?
 
 The best thing to do is to make a SystemVerilog "export DPI" task or
 function that accesses that signal, as described in the DPI chapter in the
-manual and DPI tutorials on the web.  This will allow Verilator to better
-optimize the model and should be portable across simulators.
+manual and DPI tutorials on the web.  This will allow Verilator to
+optimize the model better and should be portable across simulators.
 
 If you really want raw access to the signals, declare the signals you will
 be accessing with a :option:`/*verilator&32;public*/` metacomment before
@@ -459,17 +459,17 @@ the signal, as you would any other member variable.
 
 Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t),
 16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or
-64-bit unsigned long longs (uint64_t) that fits the width of the signal.
+64-bit unsigned long longs (uint64_t) that fit the width of the signal.
 Generally, you can use just uint32_t's for 1 to 32 bits, or uint64_t for
 1 to 64 bits, and the compiler will properly up-convert smaller entities.
-Note even signed ports are declared as unsigned; you must sign extend
+Note that even signed ports are declared as unsigned; you must sign extend
 yourself to the appropriate signal width.
 
 Signals wider than 64 bits are stored as an array of 32-bit uint32_t's.
-Thus to read bits 31:0, access signal[0], and for bits 63:32, access
-signal[1].  Unused bits (for example bit numbers 65-96 of a 65-bit vector)
-will always be zero.  If you change the value you must make sure to pack
-zeros in the unused bits or core-dumps may result, because Verilator strips
+Thus, to read bits 31:0, access signal[0], and for bits 63:32, access
+signal[1].  Unused bits (for example, bit numbers 65-96 of a 65-bit vector)
+will always be zero.  If you change the value, you must pack
+zeros in the unused bits, or core-dumps may result because Verilator strips
 array bound checks where it believes them to be unnecessary to improve
 performance.
 
@@ -490,16 +490,16 @@ From the sc_main.cpp file, you'd then:
 
 
 In this example, clk is a bool you can read or set as any other variable.
-The value of normal signals may be set, though clocks shouldn't be changed
-by your code or you'll get strange results.
+The value of normal signals may be set, though your code shouldn't change
+clocks, or you'll get strange results.
 
 
 Should a module be in Verilog or SystemC?
 """""""""""""""""""""""""""""""""""""""""
 
-Sometimes there is a block that only interconnects instances, and have a
-choice as to if you write it in Verilog or SystemC.  Everything else being
-equal, best performance is when Verilator sees all of the design.  So, look
+Sometimes there is a block that only interconnects instances, and you have a
+choice if you write it in Verilog or SystemC.  Everything else being
+equal, the best performance is when Verilator sees all of the design.  So, look
 at the hierarchy of your design, labeling instances as to if they are
 SystemC or Verilog.  Then:
 
@@ -510,6 +510,6 @@ SystemC or Verilog.  Then:
 
 * A module with only Verilog instances below can be either, but for best
   performance should be Verilog.  (The exception is if you have a design
-  that is instantiated many times; in this case Verilating one of the lower
+  that is instantiated many times; in this case, Verilating one of the lower
   modules and instantiating that Verilated instances multiple times into a
   SystemC module *may* be faster.)
diff --git a/docs/guide/files.rst b/docs/guide/files.rst
index 2b797c62a..ffd33a7b8 100644
--- a/docs/guide/files.rst
+++ b/docs/guide/files.rst
@@ -59,13 +59,13 @@ For --cc/--sc, it creates:
    * - *{prefix}*\ .cpp
      - Model C++ file
    * - *{prefix}*\ ___024root.h
-     - Top level (SystemVerilog $root) internal header file
+     - Top-level internal header file (from SystemVerilog $root)
    * - *{prefix}*\ ___024root.cpp
-     - Top level (SystemVerilog $root) internal C++ file
+     - Top-level internal C++ file (from SystemVerilog $root)
    * - *{prefix}*\ ___024root\ *{__n}*\ .cpp
-     - Additional top level internal C++ files
+     - Additional top-level internal C++ files
    * - *{prefix}*\ ___024root\ *{__DepSet_hash__n}*\ .cpp
-     - Additional top level internal C++ files (hashed to reduce build times)
+     - Additional top-level internal C++ files (hashed to reduce build times)
    * - *{prefix}*\ ___024root__Slow\ *{__n}*\ .cpp
      - Infrequent cold routines
    * - *{prefix}*\ ___024root\ *{__DepSet_hash__n}*\ .cpp
@@ -106,7 +106,7 @@ For --hierarchy mode, it creates:
    * - *{prefix}*\ __hier.dir
      - Directory to store .dot, .vpp, .tree of top module (from --hierarchy)
 
-In certain debug and other modes, it also creates:
+In specific debug and other modes, it also creates:
 
 .. list-table::
 
diff --git a/docs/guide/install.rst b/docs/guide/install.rst
index 31d553094..bb519adf8 100644
--- a/docs/guide/install.rst
+++ b/docs/guide/install.rst
@@ -16,14 +16,14 @@ Package Manager Quick Install
 
 Using a distribution's package manager is the easiest way to get
 started. (Note packages are unlikely to have the most recent version, so
-:ref:`Git Install`, might be a better alternative.) To install as a
+:ref:`Git Install` might be a better alternative.) To install as a
 package:
 
 ::
 
    apt-get install verilator   # On Ubuntu
 
-For other distributions refer to `Repology Verilator Distro Packages
+For other distributions, refer to `Repology Verilator Distro Packages
 <https://repology.org/project/verilator>`__.
 
 .. _Git Install:
@@ -31,8 +31,8 @@ For other distributions refer to `Repology Verilator Distro Packages
 Git Quick Install
 =================
 
-Installing Verilator from Git provides the most flexibility. For additional
-options and details see :ref:`Detailed Build Instructions` below.
+Installing Verilator from Git provides the most flexibility; for additional
+options and details, see :ref:`Detailed Build Instructions` below.
 
 In brief, to install from git:
 
@@ -68,7 +68,7 @@ In brief, to install from git:
 Detailed Build Instructions
 ===========================
 
-This section describes details of the build process, and assumes you are
+This section describes details of the build process and assumes you are
 building from Git. For using a pre-built binary for your Linux
 distribution, see instead :ref:`Package Manager Quick Install`.
 
@@ -77,11 +77,11 @@ OS Requirements
 ---------------
 
 Verilator is developed and has primary testing on Ubuntu, with additional
-testing on FreeBSD and Apple OS-X. Versions have also built on Red Hat
-Linux, and other flavors of GNU/Linux-ish platforms. Verilator also works
-on Windows Subsystem for Linux (WSL2), Windows under Cygwin, and Windows
-under MinGW (gcc -mno-cygwin). Verilated output (not Verilator itself)
-compiles under all the options above, plus using MSVC++.
+testing on FreeBSD and Apple OS-X. Versions have also been built on Red Hat
+Linux, other flavors of GNU/Linux-ish platforms, Windows Subsystem for
+Linux (WSL2), Windows under Cygwin, and Windows under MinGW (gcc
+-mno-cygwin). Verilated output (not Verilator itself) compiles under all
+the options above, plus using MSVC++.
 
 
 Install Prerequisites
@@ -153,13 +153,13 @@ required at Verilator build time.
 Obtain Sources
 --------------
 
-Get the sources from the git repository: (You need do this only once,
+Get the sources from the git repository: (You need to do this only once,
 ever.)
 
 ::
 
    git clone https://github.com/verilator/verilator   # Only first time
-   ## Note the URL above is not a page you can see with a browser, it's for git only
+   ## Note the URL above is not a page you can see with a browser; it's for git only
 
 Enter the checkout and determine what version/branch to use:
 
@@ -186,7 +186,7 @@ Create the configuration script:
 Eventual Installation Options
 -----------------------------
 
-Before configuring the build, you have to decide how you're going to
+Before configuring the build, you must decide how you're going to
 eventually install Verilator onto your system. Verilator will be compiling
 the current value of the environment variables :option:`VERILATOR_ROOT`,
 :option:`SYSTEMC_INCLUDE`, and :option:`SYSTEMC_LIBDIR` as defaults into
@@ -220,8 +220,8 @@ the path to all needed files.
 
 You may eventually be installing onto a project/company-wide "CAD" tools
 disk that may support multiple versions of every tool. Tell configure the
-eventual destination directory name.  We recommend the destination location
-include the Verilator version name:
+eventual destination directory name.  We recommend that the destination
+location include the Verilator version name:
 
 ::
 
@@ -255,7 +255,7 @@ as most GNU tools support:
    unsetenv VERILATOR_ROOT   # if your shell is csh
    ./configure --prefix /opt/verilator-VERSION
 
-Then after installing (below steps) you will need to add
+Then after installing (below steps), you will need to add
 ``/opt/verilator-VERSION/bin`` to your ``$PATH`` environment variable.
 
 
@@ -271,7 +271,7 @@ configure's default system paths:
    unsetenv VERILATOR_ROOT   # if your shell is csh
    ./configure
 
-Then after installing (below) the binaries should be in a location that is
+Then after installing (below), the binaries should be in a location
 already in your ``$PATH`` environment variable.
 
 
diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst
index 21acd8ff6..64a623030 100644
--- a/docs/guide/languages.rst
+++ b/docs/guide/languages.rst
@@ -41,7 +41,7 @@ union, var, void, priority case/if, and unique case/if.
 It also supports .name and .\* interconnection.
 
 Verilator partially supports concurrent assert and cover statements; see
-the enclosed coverage tests for the syntax which is allowed.
+the enclosed coverage tests for the allowed syntax.
 
 Verilator has limited support for class and related object-oriented
 constructs.
@@ -58,8 +58,8 @@ function call-like preprocessor defines, default define arguments,
 SystemVerilog 2017 (IEEE 1800-2017) Support
 -------------------------------------------
 
-Verilator supports the 2017 "for" loop constructs, and several minor
-cleanups IEEE made in 1800-2017.
+Verilator supports the 2017 "for" loop constructs and several cleanups IEEE
+made in 1800-2017.
 
 
 Verilog AMS Support
@@ -67,14 +67,13 @@ Verilog AMS Support
 
 Verilator implements a very small subset of Verilog AMS (Verilog Analog and
 Mixed-Signal Extensions) with the subset corresponding to those VMS
-keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009
-languages.
+keywords with near-equivalents in Verilog 2005 or SystemVerilog 2017.
 
 AMS parsing is enabled with :vlopt:`--language VAMS <--language>` or
 :vlopt:`--language 1800+VAMS <--language>`.
 
-At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt,
-string, and wreal.
+Verilator implements ceil, exp, floor, ln, log, pow, sqrt, string, and
+wreal.
 
 
 Synthesis Directive Assertion Support
@@ -87,12 +86,12 @@ directives.  The same applies to any :code:`//ambit synthesis`,
 :code:`//cadence` or :code:`//pragma` directives of the same form.
 
 When these synthesis directives are discovered, Verilator will either
-formally prove the directive to be true, or failing that, will insert the
+formally prove the directive to be true, or, failing that, will insert the
 appropriate code to detect failing cases at simulation runtime and print an
 "Assertion failed" error message.
 
 Verilator likewise also asserts any "unique" or "priority" SystemVerilog
-keywords on case statement, as well as "unique" on if statements.  However,
+keywords on case statements, as well as "unique" on if statements.  However,
 "priority if" is currently ignored.
 
 
@@ -109,7 +108,7 @@ With :vlopt:`--timing`, all timing controls are supported:
 
 as well as all flavors of :code:`fork`.
 
-Compiling a verilated design that makes use of these features requires a
+Compiling a Verilated design that uses these features requires a
 compiler with C++20 coroutine support, e.g. Clang 5, GCC 10, or newer.
 
 :code:`#0` delays cause Verilator to issue the :option:`ZERODLY` warning, as
@@ -125,11 +124,11 @@ always the one chosen. Such expressions cause the :option:`MINTYPMAX` warning.
 
 Another consequence of using :vlopt:`--timing` is that the :vlopt:`--main`
 option generates a main file with a proper timing eval loop, eliminating the
-need for writing any driving C++ code. You can then simply compile the
+need for writing any driving C++ code. You can simply compile the
 simulation (perhaps using :vlopt:`--build`) and run it.
 
 With :vlopt:`--no-timing`, all timing controls cause the :option:`NOTIMING`
-error, with the exception of:
+error, except:
 
 * delay statements – they are ignored (as they are in synthesis), though they
   do issue a :option:`STMTDLY` warning,
@@ -138,16 +137,15 @@ error, with the exception of:
 * net delays – they are ignored,
 * event controls at the top of the procedure,
 
-Forks cause this error as well, with the exception of:
+Forks cause this error as well, except:
 
 * forks with no statements,
 * :code:`fork..join` or :code:`fork..join_any` with one statement,
 * forks with :vlopt:`--bbox-unsup`.
 
-If neither :vlopt:`--timing` nor :vlopt:`--no-timing` is specified, all timing
-controls cause the :option:`NEEDTIMINGOPT` error, with the exception of event
-controls at the top of the process. Forks cause this error as well, with the
-exception of:
+If neither :vlopt:`--timing` nor :vlopt:`--no-timing` is specified, all
+timing controls cause the :option:`NEEDTIMINGOPT` error, except event
+controls at the top of the process. Forks cause this error as well, except:
 
 * forks with no statements,
 * :code:`fork..join` or :code:`fork..join_any` with one statement,
@@ -175,15 +173,15 @@ Synthesis Subset
 
 Verilator supports the Synthesis subset with other verification constructs
 being added over time. Verilator also simulates events as Synopsys's Design
-Compiler would; namely given a block of the form:
+Compiler would, namely given a block of the form:
 
 .. code-block:: sv
 
         always @(x) y = x & z;
 
-This will recompute y when there is even a potential for change in x or a
-change in z, that is when the flops computing x or z evaluate (which is
-what Design Compiler will synthesize.)  A compliant simulator would only
+This will recompute y when there is a potential for change in x or a change
+in z; that is when the flops computing x or z evaluate (which is what
+Design Compiler will synthesize.)  A compliant simulator will only
 calculate y if x changes.  We recommend using always_comb to make the code
 run the same everywhere.  Also avoid putting $displays in combo blocks, as
 they may print multiple times when not desired, even on compliant
@@ -196,7 +194,7 @@ Signal Naming
 To avoid conflicts with C symbol naming, any character in a signal name
 that is not alphanumeric nor a single underscore will be replaced by __0hh
 where hh is the hex code of the character. To avoid conflicts with
-Verilator's internal symbols, any double underscore are replaced with
+Verilator's internal symbols, any double underscore is replaced with
 ___05F (5F is the hex code of an underscore.)
 
 
@@ -211,14 +209,13 @@ Class
 -----
 
 Verilator class support is limited but in active development.  Verilator
-supports members, and methods. Verilator does not support class static
-members, class extend, or class parameters.
+supports members, methods, class extend, and class parameters.
 
 
 Dotted cross-hierarchy references
 ---------------------------------
 
-Verilator supports dotted references to variables, functions and tasks in
+Verilator supports dotted references to variables, functions, and tasks in
 different modules. The portion before the dot must have a constant value;
 for example a[2].b is acceptable, while a[x].b is generally not.
 
@@ -232,7 +229,7 @@ code.
 Latches
 -------
 
-Verilator is optimized for edge sensitive (flop based) designs.  It will
+Verilator is optimized for edge-sensitive (flop-based) designs.  It will
 attempt to do the correct thing for latches, but most performance
 optimizations will be disabled around the latch.
 
@@ -252,38 +249,38 @@ unsupported.
 Unknown States
 --------------
 
-Verilator is mostly a two state simulator, not a four state simulator.
-However, it has two features which uncover most initialization bugs
-(including many that a four state simulator will miss.)
+Verilator is mostly a two-state simulator, not a four-state simulator.
+However, it has two features that uncover most initialization bugs
+(including many that a four-state simulator will miss.)
 
 Identity comparisons (=== or !==) are converted to standard ==/!= when
 neither side is a constant.  This may make the expression yield a different
-result compared to a four state simulator.  An === comparison to X will
+result than a four-state simulator.  An === comparison to X will
 always be false, so that Verilog code which checks for uninitialized logic
 will not fire.
 
-Assigning X to a variable will actually assign a constant value as
-determined by the :vlopt:`--x-assign` option.  This allows runtime
-randomization, thus if the value is actually used, the random value should
-cause downstream errors.  Integers also get randomized, even though the
-Verilog 2001 specification says they initialize to zero.  Note however that
-randomization happens at initialization time and hence during a single
-simulation run, the same constant (but random) value will be used every
-time the assignment is executed.
+Assigning X to a variable will assign a constant value as determined by the
+:vlopt:`--x-assign` option.  This allows runtime randomization; thus, if
+the value is used, the random value should cause downstream errors.
+Integers also get randomized, even though the Verilog 2001 specification
+says they initialize to zero.  However, randomization happens at
+initialization time; hence, during a single simulation run, the same
+constant (but random) value will be used every time the assignment is
+executed.
 
 All variables, depending on :vlopt:`--x-initial` setting, are typically
-randomly initialized using a function.  By running several random
-simulation runs you can determine that reset is working correctly.  On the
-first run, have the function initialize variables to zero.  On the second,
-have it initialize variables to one.  On the third and following runs have
-it initialize them randomly.  If the results match, reset works.  (Note
-this is what the hardware will really do.)  In practice, just setting all
-variables to one at startup finds most problems (since typically control
-signals are active-high).
+randomly initialized using a function.  You can determine that reset is
+working correctly by running several random simulation runs.  On the first
+run, have the function initialize variables to zero.  On the second, have
+it initialize variables to one.  On the third and following runs, have it
+initialize them randomly.  If the results match, reset works.  (Note that
+this is what the hardware will do.)  In practice, setting all variables to
+one at startup finds the most problems (since control signals are typically
+active-high).
 
 :vlopt:`--x-assign` applies to variables explicitly initialized or assigned
 an X. Uninitialized clocks are initialized to zero, while all other state
-holding variables are initialized to a random value.  Event driven
+holding variables are initialized to a random value.  Event-driven
 simulators will generally trigger an edge on a transition from X to 1
 (posedge) or X to 0 (negedge). However, by default, since clocks are
 initialized to zero, Verilator will not trigger an initial negedge. Some
@@ -319,19 +316,19 @@ External logic will be needed to combine these signals with any external
 drivers.
 
 Tristate drivers are not supported inside functions and tasks; an inout
-there will be considered a two state variable that is read and written
-instead of a four state variable.
+there will be considered a two-state variable that is read and written
+instead of a four-state variable.
 
 
 Functions & Tasks
 -----------------
 
 All functions and tasks will be inlined (will not become functions in C.)
-The only support provided is for simple statements in tasks (which may
+The only support provided is simple statements in tasks (which may
 affect global variables).
 
 Recursive functions and tasks are not supported.  All inputs and outputs
-are automatic, as if they had the Verilog 2001 "automatic" keyword
+are automatic as if they had the Verilog 2001 "automatic" keyword
 prepended.  (If you don't know what this means, Verilator will do what you
 probably expect, what C does. The default behavior of Verilog is
 different.)
@@ -363,13 +360,13 @@ error for more information.
 Array Out of Bounds
 -------------------
 
-Writing a memory element that is outside the bounds specified for the array
-may cause a different memory element inside the array to be written
-instead.  For power-of-2 sized arrays, Verilator will give a width warning
-and the address.  For non-power-of-2-sizes arrays, index 0 will be written.
+Writing a memory element outside the bounds specified for the array may
+cause a different memory element inside the array to be written instead.
+For power-of-2 sized arrays, Verilator will give a width warning and the
+address.  For non-power-of-2-sizes arrays, index 0 will be written.
 
-Reading a memory element that is outside the bounds specified for the array
-will give a width warning and wrap around the power-of-2 size.  For
+Reading a memory element outside the bounds specified for the array will
+give a width warning and wrap around the power-of-2 size.  For
 non-power-of-2 sizes, it will return an unspecified constant of the
 appropriate width.
 
@@ -390,14 +387,14 @@ Force statement
 ---------------
 
 Verilator supports the procedural `force` (and corresponding `release`)
-statement. The behavior of the `force` statement however does not entirely
-comply with the IEEE 1800 SystemVerilog standard. According to the standard,
+statement. However, the behavior of the `force` statement does not entirely
+comply with IEEE 1800. According to the standard,
 when a procedural statement of the form `force a = b;` is executed, the
-simulation should behave as if from that point forwards, a continuous
-assignment `assign a = b;` have been added to override the drivers of `a`.
-More specifically: the value of `a` should be updated, whenever the value of
-`b` changes, all the way until a `release a;` statement is executed.
-Verilator instead evaluates the current value of `b` at the time the `force`
+simulation should behave as if, from that point forwards, a continuous
+assignment `assign a = b;` has been added to override the drivers of `a`.
+More specifically: the value of `a` should be updated whenever the value of
+`b` changes, until a `release a;` statement is executed.
+Verilator instead evaluates the current value of `b` when the `force`
 statement is executed, and forces `a` to that value, without updating it
 until a new `force` or `release` statement is encountered that applies to
 `a`. This non-standard behavior is nevertheless consistent with some other
@@ -407,7 +404,7 @@ simulators.
 Encrypted Verilog
 -----------------
 
-Open source simulators like Verilator are unable to use encrypted RTL
+Open-source simulators like Verilator cannot use encrypted RTL
 (i.e. IEEE P1735).  Talk to your IP vendor about delivering IP blocks via
 Verilator's :vlopt:`--protect-lib` feature.
 
@@ -448,12 +445,12 @@ This section describes specific limitations for each language keyword.
   certain limited cases.
 
 '{} operator
-  Assignment patterns with order based, default, constant integer (array)
+  Assignment patterns with an order based, default, constant integer (array)
   or member identifier (struct/union) keys are supported.  Data type keys
-  and keys which are computed from a constant expression are not supported.
+  and keys computed from a constant expression are not supported.
 
 \`uselib
-  Uselib, a vendor specific library specification method, is ignored along
+  Uselib, a vendor-specific library specification method, is ignored along
   with anything following it until the end of that line.
 
 cast operator
@@ -461,8 +458,8 @@ cast operator
   unsigned, not arrays nor structs.
 
 chandle
-  Treated as a "longint"; does not yet warn about operations that are
-  specified as illegal on chandles.
+  Treated as a "longint"; does not yet warn about operations specified as
+  illegal on chandles.
 
 disable
   Disable statements may be used only if the block being disabled is a
@@ -475,7 +472,7 @@ inside
   upper bound.  Case inside and case matches are also unsupported.
 
 interface
-  Interfaces and modports, including with generated data types are
+  Interfaces and modports, including generated data types are
   supported.  Generate blocks around modports are not supported, nor are
   virtual interfaces nor unnamed interfaces.
 
@@ -487,25 +484,25 @@ specify specparam
   All specify blocks and timing checks are ignored.
 
 uwire
-  Verilator does not perform warning checking on uwires, it treats the
+  Verilator does not perform warning checking on uwires; it treats the
   uwire keyword as if it were the normal wire keyword.
 
 $bits, $countbits, $countones, $finish, $isunknown, $onehot, $onehot0, $signed, $stime, $stop, $time, $unsigned,
   Generally supported.
 
 $dump/$dumpports and related
-  $dumpfile or $dumpports will create a VCD or FST file (which is based on
+  $dumpfile or $dumpports will create a VCD or FST file (based on
   the :vlopt:`--trace` option given when the model was Verilated). This
   will take effect starting at the next eval() call.  If you have multiple
-  Verilated designs under the same C model, then this will dump signals
+  Verilated designs under the same C model, this will dump signals
   only from the design containing the $dumpvars.
 
   $dumpvars and $dumpports module identifier is ignored; the traced
   instances will always start at the top of the design. The levels argument
-  is also ignored, use tracing_on/tracing_off pragmas instead.
+  is also ignored; use tracing_on/tracing_off pragmas instead.
 
   $dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename
-  argument is ignored, only a single trace file may be active at once.
+  argument is ignored; only a single trace file may be active at once.
 
   $dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and
   $dumplimit/$dumpportlimit are currently ignored.
@@ -514,7 +511,7 @@ $error, $fatal, $info, $warning.
   Generally supported.
 
 $exit, $finish, $stop
-  The rarely used optional parameter to $finish and $stop is ignored. $exit
+  The rarely used optional parameter to $finish and $stop is ignored; $exit
   is aliased to $finish.
 
 $fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite, $fscanf, $sscanf
@@ -530,8 +527,8 @@ $random, $urandom, $urandom_range
   per object for random stability of $urandom/$urandom_range.
 
 $readmemb, $readmemh
-  Read memory commands are supported.  Note Verilator and the Verilog
-  specification does not include support for readmem to multi-dimensional
+  Read memory commands are supported.  Verilator and the Verilog
+  specification do not include support for readmem to multi-dimensional
   arrays.
 
 $test$plusargs, $value$plusargs
diff --git a/docs/guide/overview.rst b/docs/guide/overview.rst
index 3661883fb..85198aeaa 100644
--- a/docs/guide/overview.rst
+++ b/docs/guide/overview.rst
@@ -9,13 +9,13 @@ Welcome to Verilator!
 
 The Verilator package converts Verilog [#]_ and SystemVerilog [#]_ hardware
 description language (HDL) designs into a C++ or SystemC model that, after
-compiling, can be executed.  Verilator is not a traditional simulator, but a
+compiling, can be executed.  Verilator is not a traditional simulator but a
 compiler.
 
 Verilator is typically used as follows:
 
 1. The :command:`verilator` executable is invoked with parameters similar
-to GCC, or other simulators such as Cadence Verilog-XL/NC-Verilog, or
+to GCC or other simulators such as Cadence Verilog-XL/NC-Verilog, or
 Synopsys VCS.  Verilator reads the specified SystemVerilog code, lints it,
 optionally adds coverage and waveform tracing support, and compiles the
 design into a source-level multithreaded C++ or SystemC "model".  The
@@ -28,10 +28,10 @@ output is a "Verilated" model.
 instantiates the Verilated model as a C++/SystemC object.
 
 3. The user C++ wrapper, the files created by Verilator, a "runtime
-library" provided by Verilator, and if applicable SystemC libraries are
+library" provided by Verilator, and, if applicable SystemC libraries are
 then compiled using a C++ compiler to create a simulation executable.
 
-4. The resulting executable will perform the actual simulation, during
+4. The resulting executable will perform the actual simulation during
 "simulation runtime".
 
 5. If appropriately enabled, the executable may also generate waveform
@@ -45,11 +45,11 @@ The best place to get started is to try the :ref:`Examples`.
        Engineers (IEEE) Standard for Verilog Hardware Description
        Language`, Std. 1364, released in 1995, 2001, and 2005.  The
        Verilator documentation uses the shorthand, e.g., "IEEE 1394-2005",
-       to refer to the e.g. 2005 version of this standard.
+       to refer to the, e.g., 2005 version of this standard.
 
 .. [#] SystemVerilog is defined by the `Institute of Electrical and
        Electronics Engineers (IEEE) Standard for SystemVerilog - Unified
        Hardware Design, Specification, and Verification Language`, Standard
        1800, released in 2005, 2009, 2012, and 2017.  The Verilator
        documentation uses the shorthand e.g., "IEEE 1800-2017", to refer to
-       the e.g. 2017 version of this standard.
+       the, e.g., 2017 version of this standard.
diff --git a/docs/guide/simulating.rst b/docs/guide/simulating.rst
index 271985836..94966afb2 100644
--- a/docs/guide/simulating.rst
+++ b/docs/guide/simulating.rst
@@ -7,7 +7,7 @@
 Simulating (Verilated-Model Runtime)
 ************************************
 
-This section describes items related to simulating, that is, the use of a
+This section describes items related to simulating, that is, using a
 Verilated model's executable.  For the runtime arguments to a simulated
 model, see :ref:`Simulation Runtime Arguments`.
 
@@ -21,29 +21,29 @@ For best performance, run Verilator with the :vlopt:`-O3`
 :vlopt:`--x-assign fast <--x-assign>`
 :vlopt:`--x-initial fast <--x-initial>`
 :vlopt:`--noassert <--assert>` options.  The :vlopt:`-O3`
-option will require longer time to run Verilator, and
+option will require a longer time to run Verilator, and
 :vlopt:`--x-assign fast <--x-assign>`
 :vlopt:`--x-initial fast <--x-assign>`
 may increase the risk of reset bugs in trade for performance; see the above
 documentation for these options.
 
-If using Verilated multithreaded, use ``numactl`` to ensure you are using
-non-conflicting hardware resources. See :ref:`Multithreading`. Also
-consider using profile-guided optimization, see :ref:`Thread PGO`.
+If using Verilated multithreaded, use ``numactl`` to ensure you use
+non-conflicting hardware resources. See :ref:`Multithreading`. Also,
+consider using profile-guided optimization; see :ref:`Thread PGO`.
 
 Minor Verilog code changes can also give big wins.  You should not have any
-UNOPTFLAT warnings from Verilator.  Fixing these warnings can result in
-huge improvements; one user fixed their one UNOPTFLAT warning by making a
-simple change to a clock latch used to gate clocks and gained a 60%
-performance improvement.
+:option:`UNOPTFLAT` warnings from Verilator.  Fixing these warnings can
+result in huge improvements; one user fixed their one UNOPTFLAT warning by
+making a simple change to a clocked latch used to gate clocks and gained a
+60% performance improvement.
 
-Beyond that, the performance of a Verilated model depends mostly on your
-C++ compiler and size of your CPU's caches. Experience shows that large
-models are often limited by the size of the instruction cache, and as such
-reducing code size if possible can be beneficial.
+Beyond that, the performance of a Verilated model depends primarily on your
+C++ compiler and the size of your CPU's caches. Experience shows that the
+instruction cache size often limits large models, and reducing code size,
+if possible, can be beneficial.
 
 The supplied $VERILATOR_ROOT/include/verilated.mk file uses the OPT,
-OPT_FAST, OPT_SLOW and OPT_GLOBAL variables to control optimization. You
+OPT_FAST, OPT_SLOW, and OPT_GLOBAL variables to control optimization. You
 can set these when compiling the output of Verilator with Make, for
 example:
 
@@ -51,17 +51,17 @@ example:
 
      make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a
 
-OPT_FAST specifies optimization options for those parts of the model that
-are on the fast path. This is mostly code that is executed every
-cycle. OPT_SLOW applies to slow-path code, which executes rarely, often
-only once at the beginning or end of simulation. Note that OPT_SLOW is
+OPT_FAST specifies optimization options for those parts of the model
+on the fast path. This is mostly code that is executed every
+cycle. OPT_SLOW applies to slow-path code, which rarely executes, often
+only once at the beginning or end of the simulation. OPT_SLOW is
 ignored if VM_PARALLEL_BUILDS is not 1, in which case all generated code
 will be compiled in a single compilation unit using OPT_FAST. See also the
 Verilator :vlopt:`--output-split` option. The OPT_GLOBAL variable applies
 to common code in the runtime library used by Verilated models (shipped in
 $VERILATOR_ROOT/include). Additional C++ files passed on the verilator
 command line use OPT_FAST. The OPT variable applies to all compilation
-units in addition to the specific "OPT" variables described above.
+units and the specific "OPT" variables described above.
 
 You can also use the :vlopt:`-CFLAGS` and/or :vlopt:`-LDFLAGS` options on
 the verilator command line to pass arguments directly to the compiler or
@@ -70,53 +70,53 @@ linker.
 The default values of the "OPT" variables are chosen to yield good
 simulation speed with reasonable C++ compilation times. To this end,
 OPT_FAST is set to "-Os" by default. Higher optimization such as "-O2" or
-"-O3" may help (though often they provide only a very small performance
-benefit), but compile times may be excessively large even with medium sized
+"-O3" may help (though often they provide only a minimal performance
+benefit), but compile times may be excessively large even with medium-sized
 designs. Compilation times can be improved at the expense of simulation
-speed by reducing optimization, for example with OPT_FAST="-O0". Often good
-simulation speed can be achieved with OPT_FAST="-O1 -fstrict-aliasing" but
-with improved compilation times. Files controlled by OPT_SLOW have little
-effect on performance and therefore OPT_SLOW is empty by default
-(equivalent to "-O0") for improved compilation speed. In common use-cases
+speed by reducing optimization, for example, with OPT_FAST="-O0". Often
+good simulation speed can be achieved with OPT_FAST="-O1 -fstrict-aliasing"
+but with improved compilation times.  Files controlled by OPT_SLOW have
+little effect on performance, and therefore OPT_SLOW is empty by default
+(equivalent to "-O0") for improved compilation speed. In common use cases,
 there should be little benefit in changing OPT_SLOW.  OPT_GLOBAL is set to
-"-Os" by default and there should rarely be a need to change it. As the
-runtime library is small in comparison to a lot of Verilated models,
-disabling optimization on the runtime library should not have a serious
-effect on overall compilation time, but may have detrimental effect on
-simulation speed, especially with tracing. In addition to the above, for
-best results use OPT="-march=native", the latest Clang compiler (about 10%
-faster than GCC), and link statically.
+"-Os" by default, and there should rarely be a need to change it. As the
+runtime library is small compared to many Verilated models, disabling
+optimization on the runtime library should not seriously affect overall
+compilation time but may have a detrimental effect on simulation speed,
+especially with tracing. In addition to the above, for best results, use
+OPT="-march=native", the latest Clang compiler (about 10% faster than GCC),
+and link statically.
 
-Generally the answer to which optimization level gives the best user
-experience depends on the use case and some experimentation can pay
+Generally, the answer to which optimization level gives the best user
+experience depends on the use case, and some experimentation can pay
 dividends. For a speedy debug cycle during development, especially on large
 designs where C++ compilation speed can dominate, consider using lower
-optimization to get to an executable faster. For throughput oriented use
-cases, for example regressions, it is usually worth spending extra
+optimization to get to an executable faster. For throughput-oriented use
+cases, for example, regressions, it is usually worth spending extra
 compilation time to reduce total CPU time.
 
 If you will be running many simulations on a single model, you can
-investigate profile guided optimization. See :ref:`Compiler PGO`.
+investigate profile-guided optimization. See :ref:`Compiler PGO`.
 
-Modern compilers also support link-time optimization (LTO), which can help
+Modern compilers also support link-time optimization (LTO), which can help,
 especially if you link in DPI code. To enable LTO on GCC, pass "-flto" in
-both compilation and link. Note LTO may cause excessive compile times on
-large designs.
+both compilation and link. Note that LTO may cause excessive compile times
+on large designs.
 
 Unfortunately, using the optimizer with SystemC files can result in
 compilation taking several minutes. (The SystemC libraries have many little
 inlined functions that drive the compiler nuts.)
 
-If you are using your own makefiles, you may want to compile the Verilated
+If using your own makefiles, you may want to compile the Verilated
 code with ``--MAKEFLAGS -DVL_INLINE_OPT=inline``. This will inline
-functions, however this requires that all cpp files be compiled in a single
+functions; however, this requires that all cpp files be compiled in a single
 compiler run.
 
 You may uncover further tuning possibilities by profiling the Verilog code.
 See :ref:`profiling`.
 
 When done optimizing, please let the author know the results.  We like to
-keep tabs on how Verilator compares, and may be able to suggest additional
+keep tabs on how Verilator compares and may be able to suggest additional
 improvements.
 
 
@@ -143,14 +143,14 @@ Functional Coverage
 -------------------
 
 With :vlopt:`--coverage` or :vlopt:`--coverage-user`, Verilator will
-translate functional coverage points which the user has inserted manually
-into the SystemVerilog design, into the Verilated model.
+translate functional coverage points the user has inserted manually win
+SystemVerilog code through into the Verilated model.
 
 Currently, all functional coverage points are specified using SystemVerilog
-assertion syntax which must be separately enabled with :vlopt:`--assert`.
+assertion syntax, which must be separately enabled with :vlopt:`--assert`.
 
 For example, the following SystemVerilog statement will add a coverage
-point, under the coverage name "DefaultClock":
+point under the coverage name "DefaultClock":
 
 .. code-block:: sv
 
@@ -163,13 +163,13 @@ Line Coverage
 -------------
 
 With :vlopt:`--coverage` or :vlopt:`--coverage-line`, Verilator will
-automatically add coverage analysis at each code flow change point (e.g. at
-branches).  At each such branch an unique counter is incremented.  At the
-end of a test, the counters along with the filename and line number
-corresponding to each counter are written into the coverage file.
+automatically add coverage analysis at each code flow change point (e.g.,
+at branches).  At each such branch, a counter is incremented.  At the end
+of a test, the counters, filename, and line number corresponding to each
+counter are written into the coverage file.
 
-Verilator automatically disables coverage of branches that have a $stop in
-them, as it is assumed $stop branches contain an error check that should
+Verilator automatically disables coverage of branches with a $stop in
+them, as it is assumed that $stop branches contain an error check that should
 not occur.  A :option:`/*verilator&32;coverage_block_off*/` metacomment
 will perform a similar function on any code in that block or below, or
 :option:`/*verilator&32;coverage_off*/` and
@@ -177,8 +177,9 @@ will perform a similar function on any code in that block or below, or
 respectively around a block of code.
 
 Verilator may over-count combinatorial (non-clocked) blocks when those
-blocks receive signals which have had the UNOPTFLAT warning disabled; for
-most accurate results do not disable this warning when using coverage.
+blocks receive signals which have had the :option:`UNOPTFLAT` warning
+disabled; for the most accurate results, do not disable this warning when
+using coverage.
 
 
 .. _Toggle Coverage:
@@ -189,8 +190,8 @@ Toggle Coverage
 With :vlopt:`--coverage` or :vlopt:`--coverage-toggle`, Verilator will
 automatically add toggle coverage analysis  into the Verilated model.
 
-Every bit of every signal in a module has a counter inserted.  The counter
-will increment on every edge change of the corresponding bit.
+Every bit of every signal in a module has a counter inserted, and the
+counter will increment on every edge change of the corresponding bit.
 
 Signals that are part of tasks or begin/end blocks are considered local
 variables and are not covered.  Signals that begin with underscores (see
@@ -198,17 +199,17 @@ variables and are not covered.  Signals that begin with underscores (see
 total storage across all dimensions, see :vlopt:`--coverage-max-width`) are
 also not covered.
 
-Hierarchy is compressed, such that if a module is instantiated multiple
-times, coverage will be summed for that bit across **all** instantiations
-of that module with the same parameter set.  A module instantiated with
-different parameter values is considered a different module, and will get
-counted separately.
+Hierarchy is compressed, so if a module is instantiated multiple times,
+coverage will be summed for that bit across **all** instantiations of that
+module with the same parameter set.  A module instantiated with different
+parameter values is considered a different module and will get counted
+separately.
 
 Verilator makes a minimally-intelligent decision about what clock domain
 the signal goes to, and only looks for edges in that clock domain.  This
-means that edges may be ignored if it is known that the edge could never be
-seen by the receiving logic.  This algorithm may improve in the future.
-The net result is coverage may be lower than what would be seen by looking
+means that edges may be ignored if it is known that the receiving logic
+could never see the edge.  This algorithm may improve in the future. The
+net result is that coverage may be lower than what would be seen by looking
 at traces, but the coverage is a more accurate representation of the
 quality of stimulus into the design.
 
@@ -226,7 +227,7 @@ signals that do not need toggle analysis, such as RAMs and register files.
 Coverage Collection
 -------------------
 
-When any coverage flag was used to Verilate, Verilator will add appropriate
+When any coverage flag is used to Verilate, Verilator will add appropriate
 coverage point insertions into the model and collect the coverage data.
 
 To get the coverage data from the model, in the user wrapper code,
@@ -239,23 +240,23 @@ Run each of your tests in different directories, potentially in parallel.
 Each test will create a :file:`logs/coverage.dat` file.
 
 After running all of the tests, execute the :command:`verilator_coverage`
-command, passing arguments pointing to the filenames of all of the
-individual coverage files.  :command:`verilator_coverage` will reads the
+command, passing arguments pointing to the filenames of all the
+individual coverage files.  :command:`verilator_coverage` will read the
 :file:`logs/coverage.dat` file(s), and create an annotated source code
 listing showing code coverage details.
 
-:command:`verilator_coverage` may also be used for test grading, that is
-computing which tests are important to fully cover the design.
+:command:`verilator_coverage` may also be used for test grading, computing
+which tests are important to give full verification coverage on the design.
 
 For an example, see the :file:`examples/make_tracing_c/logs` directory.
 Grep for lines starting with '%' to see what lines Verilator believes need
 more coverage.
 
-Additional options of :command:`verilator_coverage` allow for merging of
-coverage data files or other transformations.
+Additional options of :command:`verilator_coverage` allow for the merging
+of coverage data files or other transformations.
 
 Info files can be written by verilator_coverage for import to
-:command:`lcov`.  This enables use of :command:`genhtml` for HTML reports
+:command:`lcov`.  This enables using :command:`genhtml` for HTML reports
 and importing reports to sites such as `https://codecov.io
 <https://codecov.io>`_.
 
@@ -276,7 +277,7 @@ To use profiling:
 #. Build and run the simulation model.
 #. The model will create gmon.out.
 #. Run :command:`gprof` to see where in the C++ code the time is spent.
-#. Run the gprof output through the :command:`verilator_profcfunc` program
+#. Run the gprof output through the :command:`verilator_profcfunc` program,
    and it will tell you what Verilog line numbers on which most of the time
    is being spent.
 
@@ -286,7 +287,7 @@ To use profiling:
 Execution Profiling
 ===================
 
-For performance optimization, it is useful to see statistics and visualize how
+For performance optimization, it is helpful to see statistics and visualize how
 execution time is distributed in a verilated model.
 
 With the :vlopt:`--prof-exec` option, Verilator will:
@@ -296,14 +297,13 @@ With the :vlopt:`--prof-exec` option, Verilator will:
 * Add code to save profiling data in non-human-friendly form to the file
   specified with :vlopt:`+verilator+prof+exec+file+\<filename\>`.
 
-* In multi-threaded models, add code to record the start and end time of each
-  macro-task across a number of calls to eval. (What is a macro-task?  See the
+* In multithreaded models, add code to record each macro-task's start and
+  end time across several calls to eval. (What is a macro-task?  See the
   Verilator internals document (:file:`docs/internals.rst` in the
   distribution.)
 
 The :command:`verilator_gantt` program may then be run to transform the
-saved profiling file into a nicer visual format and produce some related
-statistics.
+saved profiling file into a visual format and produce related statistics.
 
 .. figure:: figures/fig_gantt_min.png
 
@@ -311,11 +311,11 @@ statistics.
 
    The measured_parallelism shows the number of CPUs being used at a given moment.
 
-   The cpu_thread section shows which thread is executing on each of the physical CPUs.
+   The cpu_thread section shows which thread is executing on each physical CPU.
 
    The thread_mtask section shows which macro-task is running on a given thread.
 
-For more information see :command:`verilator_gantt`.
+For more information, see :command:`verilator_gantt`.
 
 
 .. _Profiling ccache efficiency:
@@ -323,12 +323,11 @@ For more information see :command:`verilator_gantt`.
 Profiling ccache efficiency
 ===========================
 
-The Verilator generated Makefile provides support for basic profiling of
-ccache behavior during the build. This can be used to track down files that
-might be unnecessarily rebuilt, though as of today even small code changes
-will usually require rebuilding a large number of files. Improving ccache
-efficiency during the edit/compile/test loop is an active area of
-development.
+The Verilator-generated Makefile supports basic profiling of ccache
+behavior during the build. This can be used to track down files that might
+be unnecessarily rebuilt, though as of today, even minor code changes will
+usually require rebuilding a large number of files. Improving ccache
+efficiency during the edit/compile/test loop is an active development area.
 
 To get a basic report of how well ccache is doing, add the `ccache-report`
 target when invoking the generated Makefile:
@@ -352,17 +351,17 @@ releases.
 Save/Restore
 ============
 
-The intermediate state of a Verilated model may be saved, so that it may
+The intermediate state of a Verilated model may be saved so that it may
 later be restored.
 
 To enable this feature, use :vlopt:`--savable`.  There are limitations in
 what language features are supported along with :vlopt:`--savable`; if you
-attempt to use an unsupported feature Verilator will throw an error.
+attempt to use an unsupported feature, Verilator will throw an error.
 
 To use save/restore, the user wrapper code must create a VerilatedSerialize
-or VerilatedDeserialze object then calling the :code:`<<` or :code:`>>`
-operators on the generated model and any other data the process needs
-saved/restored.  These functions are not thread safe, and are typically
+or VerilatedDeserialze object and then call the :code:`<<` or :code:`>>`
+operators on the generated model and any other data the process needs to be
+saved/restored.  These functions are not thread-safe and are typically
 called only by a main thread.
 
 For example:
@@ -372,7 +371,7 @@ For example:
      void save_model(const char* filenamep) {
          VerilatedSave os;
          os.open(filenamep);
-         os << main_time;  // user code must save the timestamp, etc
+         os << main_time;  // user code must save the timestamp
          os << *topp;
      }
      void restore_model(const char* filenamep) {
@@ -387,11 +386,11 @@ Profile-Guided Optimization
 ===========================
 
 Profile-guided optimization is the technique where profiling data is
-collected by running your simulation executable, then this information is
+collected by running your simulation executable; then this information is
 used to guide the next Verilation or compilation.
 
-There are two forms of profile-guided optimizations.  Unfortunately for
-best results they must each be performed from the highest level code to the
+There are two forms of profile-guided optimizations.  Unfortunately, for
+best results, they must each be performed from the highest level code to the
 lowest, which means performing them separately and in this order:
 
 * :ref:`Thread PGO`
@@ -399,7 +398,7 @@ lowest, which means performing them separately and in this order:
 
 Other forms of PGO may be supported in the future, such as clock and reset
 toggle rate PGO, branch prediction PGO, statement execution time PGO, or
-others as they prove beneficial.
+others, as they prove beneficial.
 
 
 .. _Thread PGO:
@@ -407,7 +406,7 @@ others as they prove beneficial.
 Thread Profile-Guided Optimization
 ----------------------------------
 
-Verilator supports profile-guided optimization (Verilation) of multi-threaded
+Verilator supports profile-guided optimization (Verilation) of multithreaded
 models (Thread PGO) to improve performance.
 
 When using multithreading, Verilator computes how long macro tasks take and
@@ -425,24 +424,24 @@ optimization.
 Run the model executable. When the executable exits, it will create a
 profile.vlt file.
 
-Rerun Verilator, optionally omitting the :vlopt:`--prof-pgo` option,
-and adding the profile.vlt generated earlier to the command line.
+Rerun Verilator, optionally omitting the :vlopt:`--prof-pgo` option and
+adding the :file:`profile.vlt` generated earlier to the command line.
 
-Note there is no Verilator equivalent to GCC's --fprofile-use. Verilator's
-profile data file (profile.vlt) can be placed on the verilator command line
-directly without any prefix.
+Note there is no Verilator equivalent to GCC's --fprofile-use.  Verilator's
+profile data file (:file:`profile.vlt`) can be placed directly on the
+verilator command line without any option prefix.
 
 If results from multiple simulations are to be used in generating the
 optimization, multiple simulation's profile.vlt may be concatenated
-externally, or each of the files may be fed as separate command line
-options into Verilator.  Verilator will sum the profile results, so a
-longer running test will have proportionally more weight for optimization
-than a shorter running test.
+externally, or each file may be fed as separate command line options into
+Verilator.  Verilator will sum the profile results, so a long-running test
+will have more weight for optimization proportionally than a
+shorter-running test.
 
-If you provide any profile feedback data to Verilator, and it cannot use
+If you provide any profile feedback data to Verilator and it cannot use
 it, it will issue the :option:`PROFOUTOFDATE` warning that threads were
 scheduled using estimated costs.  This usually indicates that the profile
-data was generated from different Verilog source code than Verilator is
+data was generated from a different Verilog source code than Verilator is
 currently running against. Therefore, repeat the data collection phase to
 create new profiling data, then rerun Verilator with the same input source
 files and that new profiling data.
@@ -454,12 +453,12 @@ Compiler Profile-Guided Optimization
 ------------------------------------
 
 GCC and Clang support compiler profile-guided optimization (PGO). This
-optimizes any C/C++ program including Verilated code.  Using compiler PGO
+optimizes any C/C++ program, including Verilated code.  Using compiler PGO
 typically yields improvements of 5-15% on both single-threaded and
-multi-threaded models.
+multithreaded models.
 
-To use compiler PGO with GCC or Clang, please see the appropriate compiler
-documentation.  The process in GCC 10 was as follows:
+Please see the appropriate compiler documentation to use PGO with GCC or
+Clang.  The process in GCC 10 was as follows:
 
 1. Compile the Verilated model with the compiler's "-fprofile-generate"
    flag:
@@ -469,7 +468,7 @@ documentation.  The process in GCC 10 was as follows:
       verilator [whatever_flags] --make \
           -CFLAGS -fprofile-generate -LDFLAGS -fprofile-generate
 
-   or, if calling make yourself, add -fprofile-generate appropriately to your
+   Or, if calling make yourself, add -fprofile-generate appropriately to your
    Makefile.
 
 2. Run your simulation. This will create \*.gcda file(s) in the same
@@ -496,6 +495,6 @@ documentation.  The process in GCC 10 was as follows:
    or, if calling make yourself, add these CFLAGS switches appropriately to
    your Makefile.
 
-Clang and GCC also support -fauto-profile which uses sample-based
+Clang and GCC also support -fauto-profile, which uses sample-based
 feedback-directed optimization.  See the appropriate compiler
 documentation.
diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst
index 2f91bf7f8..f50303b0d 100644
--- a/docs/guide/verilating.rst
+++ b/docs/guide/verilating.rst
@@ -8,7 +8,7 @@ Verilating
 Verilator may be used in five major ways:
 
 * With the :vlopt:`--cc` or :vlopt:`--sc` options, Verilator will translate
-  the design into C++ or SystemC code respectively.  See :ref:`C++ and
+  the design into C++ or SystemC code, respectively.  See :ref:`C++ and
   SystemC Generation`.
 
 * With the :vlopt:`--lint-only` option, Verilator will lint the design to
@@ -19,8 +19,8 @@ Verilator may be used in five major ways:
   :file:`docs/xml.rst` in the distribution.
 
 * With the :vlopt:`-E` option, Verilator will preprocess the code according
-  to IEEE preprocessing rules, and write the output to standard out. This
-  is useful to feed other tools, and to debug how "\`define" statements are
+  to IEEE preprocessing rules and write the output to standard out. This
+  is useful to feed other tools and to debug how "\`define" statements are
   expanded.
 
 
@@ -34,10 +34,10 @@ Verilator will translate a SystemVerilog design into C++ with the
 
 When using these options:
 
-#. Verilator reads the input Verilog code, determines all "top modules" that
-   is modules or programs that are not used as instances under other cells.
-   If :vlopt:`--top-module` is used, then that determines the top module and
-   all other top modules are removed, otherwise a :vlopt:`MULTITOP` warning
+#. Verilator reads the input Verilog code and determines all "top modules", that
+   is, modules or programs that are not used as instances under other cells.
+   If :vlopt:`--top-module` is used, then that determines the top module, and
+   all other top modules are removed; otherwise a :vlopt:`MULTITOP` warning
    is given.
 
 #. Verilator writes the C++/SystemC code to output files into the
@@ -46,13 +46,13 @@ When using these options:
    top module.
 
 #. If :vlopt:`--exe` is used, Verilator creates makefiles to generate a
-   simulation executable, otherwise it creates makefiles to generate an
+   simulation executable, otherwise, it creates makefiles to generate an
    archive (.a) containing the objects.
 
 #. If :vlopt:`--build` option was used, it calls :ref:`GNU Make` or
    :ref:`CMake` to build the model.
 
-Once a model is built it is then typically run, see :ref:`Simulating`.
+Once a model is built, it is then typically run, see :ref:`Simulating`.
 
 
 .. _Hierarchical Verilation:
@@ -60,14 +60,14 @@ Once a model is built it is then typically run, see :ref:`Simulating`.
 Hierarchical Verilation
 =======================
 
-Large designs may take long (e.g. 10+ minutes) and huge memory (e.g. 100+
+Large designs may take long (e.g., 10+ minutes) and huge memory (e.g., 100+
 GB) to Verilate.  In hierarchical mode, the user manually selects some
 large lower-level hierarchy blocks to separate from the larger design. For
-example a core may be the hierarchy block, and separated out of a
-multi-core SoC.
+example, a core may be the hierarchy block separated out of a multi-core
+SoC design.
 
 Verilator is run in hierarchical mode on the whole SoC.  Verilator will
-make two models, one for the CPU hierarchy block, and one for the SoC.  The
+make two models, one for the CPU hierarchy block and one for the SoC.  The
 Verilated code for the SoC will automatically call the CPU Verilated model.
 
 The current hierarchical Verilation is based on :vlopt:`--lib-create`. Each
@@ -78,16 +78,16 @@ blocks will see a tiny wrapper generated by :vlopt:`--lib-create`.
 Usage
 -----
 
-Users need to mark one or more moderate size module as hierarchy block(s).
+Users need to mark one or more moderate-size modules as hierarchy block(s).
 There are two ways to mark a module:
 
 * Write :option:`/*verilator&32;hier_block*/` metacomment in HDL code.
 
-* Add a :option:`hier_block` line in a the :ref:`Configuration Files`.
+* Add a :option:`hier_block` line in the :ref:`Configuration Files`.
 
-Then pass the :vlopt:`--hierarchical` option to Verilator
+Then pass the :vlopt:`--hierarchical` option to Verilator.
 
-Compilation is the same as when not using hierarchical mode.
+The compilation is the same as when not using hierarchical mode.
 
 .. code-block:: bash
 
@@ -97,21 +97,20 @@ Compilation is the same as when not using hierarchical mode.
 Limitations
 -----------
 
-Hierarchy blocks have some limitations including:
+Hierarchy blocks have some limitations, including:
 
-* The hierarchy block cannot be accessed using dot (.) from upper module(s)
-  or other hierarchy blocks.
+* The hierarchy block cannot be accessed using dot (.) from the upper
+  module(s) or other hierarchy blocks.
 
 * Signals in the block cannot be traced.
 
 * Modport cannot be used at the hierarchical block boundary.
 
-* The simulation speed is likely to not be as fast as flat Verilation, in
-  which all modules are globally scheduled.
+* The simulation speed is likely not as fast as flat Verilation, in which
+  all modules are globally scheduled.
 
-* Generated clocks may not work correctly if they are generated in the
-  hierarchical model and pass up into another hierarchical model or the top
-  module.
+* Generated clocks may not work correctly if generated in the hierarchical
+  model and passed into another hierarchical model or the top module.
 
 * Delays are not allowed in hierarchy blocks.
 
@@ -130,8 +129,8 @@ Overlapping Verilation and Compilation
 --------------------------------------
 
 Verilator needs to run 2 + *N* times in hierarchical Verilation, where *N*
-is the number of hierarchy blocks. One of the two is for the top module
-which refers wrappers of all other hierarchy blocks.  The second one of the
+is the number of hierarchy blocks. One of the two is for the top module,
+which refers to the wrappers of all other hierarchy blocks.  The second of the
 two is the initial run that searches modules marked with
 :option:`/*verilator&32;hier_block*/` metacomment and creates a plan and
 write in :file:`{prefix}_hier.mk`.  This initial run internally invokes
@@ -153,19 +152,19 @@ Verilator supports cross-compiling Verilated code.  This is generally used
 to run Verilator on a Linux system and produce C++ code that is then compiled
 on Windows.
 
-Cross compilation involves up to three different OSes.  The build system is
-where you configured and compiled Verilator, the host system where you run
-Verilator, and the target system where you compile the Verilated code and
-run the simulation.
+Cross-compilation involves up to three different OSes.  The build system is
+where you configure and compile Verilator, the host system is where you run
+Verilator, and the target system is where you compile the Verilated code
+and run the simulation.
 
-Currently, Verilator requires the build and host system type to be the
+Verilator requires the build and host system types to be the
 same, though the target system type may be different.  To support this,
 :command:`./configure` and make Verilator on the build system.  Then, run
 Verilator on the host system.  Finally, the output of Verilator may be
 compiled on the different target system.
 
 To support this, none of the files that Verilator produces will reference
-any configure generated build-system specific files, such as
+any configure-generated build-system-specific files, such as
 :file:`config.h` (which is renamed in Verilator to :file:`config_build.h`
 to reduce confusion.)  The disadvantage of this approach is that
 :file:`include/verilatedos.h` must self-detect the requirements of the
@@ -183,29 +182,29 @@ Multithreading
 
 Verilator supports multithreaded simulation models.
 
-With :vlopt:`--threads 1 <--threads>`, the generated model is single
-threaded, however the support libraries are multithread safe. This allows
-different instantiations of model(s) to potentially each be run under a
-different thread. All threading is the responsibility of the user's C++
-testbench.
+With :vlopt:`--threads 1 <--threads>`, the generated model is
+single-threaded; however, the support libraries are multithread safe. This
+allows different instantiations of the model(s) to potentially each be run
+under a different thread. All threading is the responsibility of the user's
+C++ testbench.
 
 With :vlopt:`--threads {N} <--threads>`, where N is at least 2, the
 generated model will be designed to run in parallel on N threads. The
 thread calling eval() provides one of those threads, and the generated
 model will create and manage the other N-1 threads. It's the client's
 responsibility not to oversubscribe the available CPU cores. Under CPU
-oversubscription, the Verilated model should not livelock nor deadlock,
+oversubscription, the Verilated model should not livelock nor deadlock;
 however, you can expect performance to be far worse than it would be with
-proper ratio of threads and CPU cores.
+the proper ratio of threads and CPU cores.
 
 The thread used for constructing a model must be the same thread that calls
-:code:`eval()` into the model, this is called the "eval thread". The thread
-used to perform certain global operations such as saving and tracing must
-be done by a "main thread". In most cases the eval thread and main thread
+:code:`eval()` into the model; this is called the "eval thread". The thread
+used to perform certain global operations, such as saving and tracing, must
+be done by a "main thread". In most cases, the eval thread and main thread
 are the same thread (i.e. the user's top C++ testbench runs on a single
 thread), but this is not required.
 
-When making frequent use of DPI imported functions in a multi-threaded
+When making frequent use of DPI imported functions in a multithreaded
 model, it may be beneficial to performance to adjust the
 :vlopt:`--instr-count-dpi` option based on some experimentation. This
 influences the partitioning of the model by adjusting the assumed execution
@@ -218,24 +217,24 @@ with :vlopt:`--threads`, and is executed on the same thread pool as the model.
 The :vlopt:`--trace-threads` options can be used with :vlopt:`--trace-fst`
 to offload FST tracing using multiple threads. If :vlopt:`--trace-threads` is
 given without :vlopt:`--threads`, then :vlopt:`--trace-threads` will imply
-:vlopt:`--threads 1 <--threads>`, i.e.: the support libraries will be
+:vlopt:`--threads 1 <--threads>`, i.e., the support libraries will be
 thread safe.
 
 With :vlopt:`--trace-threads 0 <--trace-threads>`, trace dumps are produced
-on the main thread. This again gives the highest single thread performance.
+on the main thread. This again gives the highest single-thread performance.
 
 With :vlopt:`--trace-threads {N} <--trace-threads>`, where N is at least 1,
 up to N additional threads will be created and managed by the trace files
-(e.g.: VerilatedFstC), to offload construction of the trace dump. The main
+(e.g., VerilatedFstC), to offload construction of the trace dump. The main
 thread will be released to proceed with execution as soon as possible, though
-some blocking of the main thread is still necessary while capturing the
+some main thread blocking is still necessary while capturing the
 trace. FST tracing can utilize up to 2 offload threads, so there is no use
 of setting :vlopt:`--trace-threads` higher than 2 at the moment.
 
 When running a multithreaded model, the default Linux task scheduler often
-works against the model, by assuming threads are short lived, and thus
-often schedules threads using multiple hyperthreads within the same
-physical core. For best performance use the :command:`numactl` program to
+works against the model by assuming short-lived threads and thus
+it often schedules threads using multiple hyperthreads within the same
+physical core. For best performance, use the :command:`numactl` program to
 (when the threading count fits) select unique physical cores on the same
 socket. The same applies for :vlopt:`--trace-threads` as well.
 
@@ -247,8 +246,8 @@ As an example, if a model was Verilated with
     egrep 'processor|physical id|core id' /proc/cpuinfo
 
 To select cores 0, 1, 2, and 3 that are all located on the same socket (0)
-but different physical cores.  (Also useful is
-:command:`numactl --hardware`, or :command:`lscpu` but those doesn't show
+but have different physical cores.  (Also useful is
+:command:`numactl --hardware`, or :command:`lscpu`, but those don't show
 hyperthreading cores.)  Then we execute:
 
 .. code-block:: bash
@@ -256,8 +255,8 @@ hyperthreading cores.)  Then we execute:
     numactl -m 0 -C 0,1,2,3 -- verilated_executable_name
 
 This will limit memory to socket 0, and threads to cores 0, 1, 2, 3,
-(presumably on socket 0) optimizing performance.  Of course this must be
-adjusted if you want another simulator using e.g. socket 1, or if you
+(presumably on socket 0), optimizing performance.  Of course, this must be
+adjusted if you want another simulator to use, e.g., socket 1, or if you
 Verilated with a different number of threads.  To see what CPUs are
 actually used, use :vlopt:`--prof-exec`.
 
@@ -265,19 +264,19 @@ actually used, use :vlopt:`--prof-exec`.
 Multithreaded Verilog and Library Support
 -----------------------------------------
 
-$display/$stop/$finish are delayed until the end of an eval() call in order
+$display/$stop/$finish are delayed until the end of an eval() call
 to maintain ordering between threads. This may result in additional tasks
 completing after the $stop or $finish.
 
-If using :vlopt:`--coverage`, the coverage routines are fully thread safe.
+If using :vlopt:`--coverage`, the coverage routines are fully thread-safe.
 
-If using the DPI, Verilator assumes pure DPI imports are thread safe,
+If using the DPI, Verilator assumes pure DPI imports are thread-safe,
 balancing performance versus safety. See :vlopt:`--threads-dpi`.
 
 If using :vlopt:`--savable`, the save/restore classes are not multithreaded
 and must be called only by the eval thread.
 
-If using :vlopt:`--sc`, the SystemC kernel is not thread safe, therefore
+If using :vlopt:`--sc`, the SystemC kernel is not thread-safe; therefore,
 the eval thread and main thread must be the same.
 
 If using :vlopt:`--trace`, the tracing classes must be constructed and
@@ -297,8 +296,8 @@ Verilator defaults to creating GNU Make makefiles for the model.  Verilator
 will call make automatically when the :vlopt:'--build' option is used.
 
 If calling Verilator from a makefile, the :vlopt:'-MMD' option will create
-a dependency file which will allow Make to only run Verilator if input
-Verilog files change.
+a dependency file, allowing Make to only run Verilator if input Verilog
+files change.
 
 .. _CMake:
 
@@ -307,8 +306,8 @@ CMake
 
 Verilator can be run using CMake, which takes care of both running
 Verilator and compiling the output. There is a CMake example in the
-examples/ directory. The following is a minimal CMakeLists.txt that would
-build the code listed in :ref:`Example C++ Execution`
+:file:`examples/` directory. The following is a minimal CMakeLists.txt that
+would build the code listed in :ref:`Example C++ Execution`
 
 .. code-block:: CMake
 
@@ -320,8 +319,8 @@ build the code listed in :ref:`Example C++ Execution`
 :code:`find_package` will automatically find an installed copy of
 Verilator, or use a local build if VERILATOR_ROOT is set.
 
-It is recommended to use CMake >= 3.12 and the Ninja generator, though
-other combinations should work. To build with CMake, change to the folder
+Using CMake >= 3.12 and the Ninja generator is recommended, though other
+combinations should work. To build with CMake, change to the folder
 containing CMakeLists.txt and run:
 
 .. code-block:: bash
@@ -340,14 +339,14 @@ Or to build with your system default generator:
      cmake ..
      cmake --build .
 
-If you're building the example you should have an executable to run:
+If you're building the example, you should have an executable to run:
 
 .. code-block:: bash
 
      ./Vour
 
-The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT and
-VERILATOR_BIN to the appropriate values, and also creates a verilate()
+The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT,
+and VERILATOR_BIN to the appropriate values and creates a verilate()
 function. verilate() will automatically create custom commands to run
 Verilator and add the generated C++ sources to the target specified.
 
@@ -362,14 +361,14 @@ Verilate in CMake
               [OPT_GLOBAL ..] [DIRECTORY dir] [THREADS num]
               [TRACE_THREADS num] [VERILATOR_ARGS ...])
 
-Lowercase and ... should be replaced with arguments, the uppercase parts
-delimit the arguments and can be passed in any order, or left out entirely
+Lowercase and ... should be replaced with arguments; the uppercase parts
+delimit the arguments and can be passed in any order or left out entirely
 if optional.
 
 verilate(target ...) can be called multiple times to add other Verilog
 modules to an executable or library target.
 
-When generating Verilated SystemC sources, you should also include the
+When generating Verilated SystemC sources, you should list the
 SystemC include directories and link to the SystemC libraries.
 
 .. describe:: target
@@ -379,7 +378,7 @@ SystemC include directories and link to the SystemC libraries.
 .. describe:: COVERAGE
 
    Optional. Enables coverage if present, equivalent to "VERILATOR_ARGS
-   --coverage"
+   --coverage".
 
 .. describe:: DIRECTORY
 
@@ -407,22 +406,22 @@ SystemC include directories and link to the SystemC libraries.
 .. describe:: PREFIX
 
    Optional. Sets the Verilator output prefix. Defaults to the name of the
-   first source file with a "V" prepended. Must be unique in each call to
-   verilate(), so this is necessary if you build a module multiple times
-   with different parameters. Must be a valid C++ identifier, i.e. contains
-   no white space and only characters A-Z, a-z, 0-9 or _.
+   first source file with a "V" prepended. It must be unique in each call
+   to verilate(), so this is necessary if you build a module multiple times
+   with different parameters. It must be a valid C++ identifier, i.e., it
+   contains no white space and only characters A-Z, a-z, 0-9 or _.
 
 .. describe:: SOURCES
 
-   List of Verilog files to Verilate. Must have at least one file.
+   List of Verilog files to Verilate. You must provide at least one file.
 
 .. describe:: SYSTEMC
 
    Optional. Enables SystemC mode, defaults to C++ if not specified.
 
    When using Accellera's SystemC with CMake support, a CMake target is
-   available that simplifies the SystemC steps. This will only work if the
-   SystemC installation can be found by CMake. This can be configured by
+   available that simplifies the SystemC steps. This will only work if
+   CMake can find the SystemC installation, and this can be configured by
    setting the CMAKE_PREFIX_PATH variable during CMake configuration.
 
    Don't forget to set the same C++ standard for the Verilated sources as
@@ -431,12 +430,11 @@ SystemC include directories and link to the SystemC libraries.
 
 .. describe:: THREADS
 
-   Optional. Generated a multi-threaded model, same as "--threads".
+   Optional. Enable a multithreaded model; see :vlopt:`--threads`.
 
 .. describe:: TRACE_THREADS
 
-   Optional. Generated multi-threaded FST trace dumping, same as
-   "--trace-threads".
+   Optional. Enable multithreaded FST trace; see :vlopt:`--trace-threads`.
 
 .. describe:: TOP_MODULE
 
@@ -456,7 +454,7 @@ SystemC include directories and link to the SystemC libraries.
 .. describe:: VERILATOR_ARGS
 
    Optional. Extra arguments to Verilator. Do not specify :vlopt:`--Mdir`
-   or :vlopt:`--prefix` here, use DIRECTORY or PREFIX.
+   or :vlopt:`--prefix` here; use DIRECTORY or PREFIX.
 
 
 SystemC Link in CMake
diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst
index db4344cd9..3e5c8645a 100644
--- a/docs/guide/warnings.rst
+++ b/docs/guide/warnings.rst
@@ -12,7 +12,7 @@ Disabling Warnings
 
 Warnings may be disabled in multiple ways:
 
-#. Disable the warning in the source code.  When the warning is printed it
+#. Disable the warning in the source code.  When the warning is printed, it
    will include a warning code.  Surround the offending line with a
    :code:`/*verilator&32;lint_off*/` and :code:`/*verilator&32;lint_on*/`
    metacomment pair:
@@ -24,8 +24,8 @@ Warnings may be disabled in multiple ways:
          // verilator lint_on UNSIGNED
 
 #. Disable the warning using :ref:`Configuration Files` with a
-   :option:`lint_off` command.  This is useful when a script is suppressing
-   warnings and the Verilog source should not be changed.  This method also
+   :option:`lint_off` command.  This is useful when a script suppresses
+   warnings, and the Verilog source should not be changed.  This method also
    allows matching on the warning text.
 
    .. code-block:: sv
@@ -36,7 +36,7 @@ Warnings may be disabled in multiple ways:
    :code:`-Wno-{warning-code}` option.  This should be avoided, as it
    removes all checking across the designs, and prevents other users from
    compiling your code without knowing the magic set of disables needed to
-   successfully compile your design.
+   compile your design successfully.
 
 
 Error And Warning Format
@@ -50,10 +50,10 @@ expression:
          %(Error|Warning)(-[A-Z0-9_]+)?: ((\S+):(\d+):((\d+):)? )?.*
 
 
-Errors and warning start with a percent sign (historical heritage from
-Digital Equipment Corporation).  Some errors or warning have a code
+Errors and warnings start with a percent sign (historical heritage from
+Digital Equipment Corporation).  Some errors or warnings have a code
 attached, with meanings described below.  Some errors also have a filename,
-line number and optional column number (starting at column 1 to match GCC).
+line number, and optional column number (starting at column 1 to match GCC).
 
 Following the error message, Verilator will typically show the user's
 source code corresponding to the error, prefixed by the line number and a "
@@ -66,14 +66,14 @@ List Of Warnings
 
 .. option:: Internal Error
 
-   This error should never occur first, though may occur if earlier
+   This error should never occur first, though it may occur if earlier
    warnings or error messages have corrupted the program.  If there are no
    other warnings or errors, submit a bug report.
 
 
 .. option:: Unsupported: ....
 
-   This error indicates that the code is using a Verilog language construct
+   This error indicates that the code uses a Verilog language construct
    that is not yet supported in Verilator.  See the Limitations chapter.
 
 
@@ -81,7 +81,7 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that an :code:`always_comb` block has a variable which is set
+   Warns that an :code:`always_comb` block has a variable that is set
    after it is used.  This may cause simulation-synthesis mismatches, as
    not all simulators allow this ordering.
 
@@ -92,7 +92,7 @@ List Of Warnings
             b = 1;
          end
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -109,8 +109,8 @@ List Of Warnings
          assign #100 a = b;
 
    Ignoring this warning may make Verilator simulations differ from other
-   simulators, however at one point this was a common style so disabled by
-   default as a code style warning.
+   simulators; however, this was a common style at one point, so disabled
+   by default as a code-style warning.
 
    This warning is issued only if Verilator is run with :vlopt:`--no-timing`.
 
@@ -119,7 +119,7 @@ List Of Warnings
 
    .. TODO better example
 
-   Error that an assignment is being made to an input signal.  This is
+   An error that an assignment is being made to an input signal.  This is
    almost certainly a mistake, though technically legal.
 
    .. code-block:: sv
@@ -127,27 +127,27 @@ List Of Warnings
          input a;
          assign a = 1'b1;
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
 .. option:: BADSTDPRAGMA
 
-   Error that a pragma is badly formed, when that pragma is defined by IEEE
-   1800-2017.  For example, an empty pragma line, or an incorrect specified
-   'pragma protect'.  Note that 3rd party pragmas not defined by IEEE
-   1800-2017 are ignored.
+   An error that a pragma is badly formed, for pragmas defined by IEEE
+   1800-2017.  For example, an empty pragma line, or an incorrectly used
+   'pragma protect'.  Third-party pragmas not defined by IEEE 1800-2017 are
+   ignored.
 
 
 .. option:: BLKANDNBLK
 
    .. TODO better example
 
-   BLKANDNBLK is an error that a variable comes from a mix of blocking and
+   BLKANDNBLK is an error that a variable is driven by a mix of blocking and
    non-blocking assignments.
 
-   This is not illegal in SystemVerilog, but a violation of good coding
-   practice. Verilator reports this as an error, because ignoring this
+   This is not illegal in SystemVerilog but a violation of good coding
+   practice. Verilator reports this as an error because ignoring this
    warning may make Verilator simulations differ from other simulators.
 
    It is generally safe to disable this error (with a
@@ -165,7 +165,7 @@ List Of Warnings
          always @(posedge clk)  foo[0] <= ...
          always_comb foo[1] = ...
 
-   Instead use a different register for the flop:
+   Instead, use a different register for the flop:
 
    .. code-block:: sv
 
@@ -202,7 +202,7 @@ List Of Warnings
 
    This message is only seen on large or complicated loops because
    Verilator generally unrolls small loops.  You may want to try increasing
-   :vlopt:`--unroll-count` (and occasionally :vlopt:`--unroll-stmts`) which
+   :vlopt:`--unroll-count` (and occasionally :vlopt:`--unroll-stmts`), which
    will raise the small loop bar to avoid this error.
 
 
@@ -211,17 +211,17 @@ List Of Warnings
    .. TODO better example
 
    This indicates that a blocking assignment (=) is used in a sequential
-   block.  Generally non-blocking/delayed assignments (<=) are used in
+   block.  Generally, non-blocking/delayed assignments (<=) are used in
    sequential blocks, to avoid the possibility of simulator races.  It can
    be reasonable to do this if the generated signal is used ONLY later in
-   the same block, however this style is generally discouraged as it is
+   the same block; however, this style is generally discouraged as it is
    error prone.
 
    .. code-block:: sv
 
          always @(posedge clk)  foo = ...;  //<--- Warning
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
    Other tools with similar warnings: Verible's always-ff-non-blocking,
@@ -234,12 +234,12 @@ List Of Warnings
    .. TODO better example
 
    Warns that a backslash is followed by a space then a newline. Likely the
-   intent was to have a backslash directly followed by a newline (e.g. when
-   making a "\`define") and there's accidentally white space at the end of
-   the line.  If the space is not accidental, suggest removing the
-   backslash in the code as it serves no function.
+   intent was to have a backslash directly followed by a newline (e.g.,
+   when making a "\`define"), and there's accidentally white space at the
+   end of the line.  If the space is not accidental, suggest removing the
+   backslash in the code, as it serves no function.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -247,19 +247,19 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that inside a case statement there is a stimulus pattern for which
-   there is no case item specified.  This is bad style, if a case is
+   Warns that inside a case statement, there is a stimulus pattern for
+   which no case item is provided.  This is bad style; if a case is
    impossible, it's better to have a :code:`default: $stop;` or just
    :code:`default: ;` so that any design assumption violations will be
-   discovered in simulation.
+   discovered in the simulation.
 
    Unique case statements that select on an enumerated variable, where all
    of the enumerated values are covered by case items, are considered
-   complete even if illegal non-enumerated values are not covered by the
-   case statement.  To check that illegal values are not hit, use
-   :vlopt:`--assert` (see IEEE 1800-2017 12.5.3).
+   complete even if the case statement does not cover illegal
+   non-enumerated values (IEEE 1800-2017 12.5.3).  To check that illegal
+   values are not hit, use :vlopt:`--assert`.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -267,12 +267,12 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that inside a case statement has case values which are detected to
-   be overlapping.  This is bad style, as moving the order of case values
-   will cause different behavior.  Generally the values can be respecified
-   to not overlap.
+   Warns that a case statement has case values detected to be overlapping.
+   This is bad style, as moving the order of case values will cause
+   different behavior.  Generally the values can be respecified not to
+   overlap.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -280,12 +280,12 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that a case statement contains a constant with a ``x`` .
-   Verilator is two-state so interpret such items as always false.  Note a
-   common error is to use a ``X`` in a case or casez statement item; often
+   Warns that a case statement contains a constant with an ``x`` .
+   Verilator is two-state so interpret such items as always false.  Note that a
+   frequent error is to use a ``X`` in a case or casez statement item; often,
    what the user instead intended is to use a casez with ``?`` .
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -298,7 +298,7 @@ List Of Warnings
    `http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf
    <http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf>`_
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -307,17 +307,17 @@ List Of Warnings
    .. TODO better example
 
    Warns that a dynamic cast ($cast) is unnecessary as the $cast will
-   always succeed or fail.  If it will always fail, the $cast is
-   useless. If it will always succeed a static cast may be preferred.
+   always succeed or fail.  If it will always fail, the $cast is useless,
+   and if it will always succeed, a static cast may be preferred.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.  On other simulators, not fixing CASTCONST may
    result in decreased performance.
 
 
 .. option:: CDCRSTLOGIC
 
-   With :vlopt:`--cdc` only, warns that asynchronous flop reset terms come
+   With :vlopt:`--cdc` only, it warns that asynchronous flop reset terms come
    from other than primary inputs or flopped outputs, creating the
    potential for reset glitches.
 
@@ -326,10 +326,10 @@ List Of Warnings
 
    Historical, never issued since version 5.000.
 
-   Warned that clock signal was mixed used with/as data signal. The
-   checking for this warning was enabled only if user has explicitly marked
-   some signal as clocker using command line option or in-source meta
-   comment (see :vlopt:`--clk`).
+   Warned that clock signal was mixed used with/as a data signal. The
+   checking for this warning was enabled only if the user has explicitly
+   marked some signal as clocker using the command line option or in-source
+   meta comment (see :vlopt:`--clk`).
 
    The warning could be disabled without affecting the simulation
    result. But it was recommended to check the warning as it may have
@@ -341,20 +341,20 @@ List Of Warnings
    .. TODO better example
 
    Warns that the code is comparing a value in a way that will always be
-   constant.  For example :code:`X > 1` will always be true when X is a
+   constant.  For example, :code:`X > 1` will always be true when X is a
    single bit wide.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
 .. option:: COLONPLUS
 
    Warns that a :code:`:+` is seen. Likely the intent was to use :code:`+:`
-   to select a range of bits. If the intent was a range that is explicitly
-   positive, suggest adding a space, e.g. use :code:`: +`.
+   to select a range of bits. If the intent was an explicitly positive
+   range, suggest adding a space, e.g., use :code:`: +`.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -379,7 +379,7 @@ List Of Warnings
 
    .. TODO better example
 
-   Error that a continuous assignment is setting a reg. According to IEEE
+   An error that a continuous assignment is setting a reg. According to IEEE
    Verilog, but not SystemVerilog, a wire must be used as the target of
    continuous assignments.
 
@@ -389,7 +389,7 @@ List Of Warnings
    :vlopt:`--language 1364-2001 <--language>`, or
    :vlopt:`--language 1364-2005 <--language>` is used.
 
-   Ignoring this error will only suppress the lint check, it will simulate
+   Ignoring this error will only suppress the lint check; it will simulate
    correctly.
 
 
@@ -398,28 +398,28 @@ List Of Warnings
    .. TODO better example
 
    Warns that a module or other declaration's name doesn't match the
-   filename with path and extension stripped that it is declared in.  The
-   filename a modules/interfaces/programs is declared in should match the
-   name of the module etc. so that :vlopt:`-y` option directory searching
+   filename with the path and extension stripped that it is declared in.  The
+   filename a module/interface/program is declared in should match the
+   name of the module etc., so that :vlopt:`-y` option directory searching
    will work.  This warning is printed for only the first mismatching
    module in any given file, and :vlopt:`-v` library files are ignored.
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
 
 .. option:: DEFPARAM
 
-   Warns that the :code:`defparam` statement was deprecated in Verilog 2001
+   Warns that the :code:`defparam` statement was deprecated in IEEE 1364-2001,
    and all designs should now be using the :code:`#(...)` format to specify
    parameters.
 
-   Defparams may be defined far from the instantiation that is affected by
+   Defparams may be defined far from the instantiation affected by
    the defparam, affecting readability. Defparams have been formally
    deprecated since IEEE 1800-2005 25.2 and may not work in future language
    versions.
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
    Faulty example:
@@ -465,9 +465,9 @@ List Of Warnings
 
    Warning that a Verilator metacomment, or configuration file command uses
    syntax that has been deprecated.  Upgrade the code to the replacement
-   that should be suggested by the warning message.
+   typically suggested by the warning message.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -476,16 +476,17 @@ List Of Warnings
    Historical, never issued since version 3.862.
 
    Was an error when Verilator tried to deal with a combinatorial loop that
-   could not be flattened, and which involves a datatype which Verilator
+   could not be flattened, and which involves a datatype that Verilator
    could not handle, such as an unpacked struct or a large unpacked array.
 
 
 .. option:: DIDNOTCONVERGE
 
-   Error at simulation runtime when model did not properly settle.
+   Error at simulation runtime when model did not correctly settle.
 
    Verilator sometimes has to evaluate combinatorial logic multiple times,
-   usually around code where an UNOPTFLAT warning was issued, but disabled.
+   usually around code where an :option:`UNOPTFLAT` warning was issued but
+   disabled.
 
    Faulty example:
 
@@ -495,28 +496,28 @@ List Of Warnings
 
    .. include:: ../../docs/gen/ex_DIDNOTCONVERGE_nodbg_msg.rst
 
-   This is because the signals keep toggling even with out time
+   This is because the signals keep toggling even without time
    passing. Thus to prevent an infinite loop, the Verilated executable
    gives the DIDNOTCONVERGE error.
 
-   To debug this, first review any UNOPTFLAT warnings that were
-   ignored.  Though typically it is safe to ignore UNOPTFLAT (at a
-   performance cost), at the time of issuing an UNOPTFLAT Verilator did not
+   To debug this, first, review any UNOPTFLAT warnings that were
+   ignored.  Though typically, it is safe to ignore UNOPTFLAT (at a
+   performance cost), at the time of issuing a UNOPTFLAT Verilator did not
    know if the logic would eventually converge and assumed it would.
 
    Next, run Verilator with
    :vlopt:`--prof-cfuncs -CFLAGS -DVL_DEBUG <--prof-cfuncs>`.  Rerun the
-   test.  Now just before the convergence error you should see additional
+   test.  Now just before the convergence error, you should see additional
    output similar to this:
 
    .. include:: ../../docs/gen/ex_DIDNOTCONVERGE_msg.rst
 
-   The CHANGE line means that on the given filename and line number that
-   drove a signal, the signal 'a' kept changing. Inspect the code that
-   modifies these signals.  Note if many signals are getting printed then
-   most likely all of them are oscillating.  It may also be that e.g. "a"
-   may be oscillating, then "a" feeds signal "c" which then is also
-   reported as oscillating.
+   The CHANGE line means that the signal 'a' kept changing on the given
+   filename and line number that drove the signal. Inspect the code that
+   modifies these signals.  Note that if many signals are getting printed,
+   then most likely, all of them are oscillating.  It may also be that,
+   e.g. "a" may be oscillating, then "a" feeds signal "c", which then is
+   also reported as oscillating.
 
    One way DIDNOTCONVERGE may occur is flops are built out of gate
    primitives. Verilator does not support building flops or latches out of
@@ -527,7 +528,7 @@ List Of Warnings
    clocks if Verilator is run with :vlopt:`--no-timing`. In this mode,
    Verilator ignores the delays and gives an :option:`ASSIGNDLY` or
    :option:`STMTDLY` warning.  If these were suppressed, due to the absence of
-   the delay, the code may now oscillate.
+   the delay, the design might oscillate.
 
    Finally, rare, more difficult cases can be debugged like a C++ program;
    either enter :command:`gdb` and use its tracing facilities, or edit the
@@ -536,21 +537,21 @@ List Of Warnings
 
 .. option:: ENDCAPSULATED
 
-   Warns that a class member is declared is local or protected, but is
-   being accessed from outside that class (if local) or a derived class
-   (if protected).
+   Warns that a class member is declared :code:`local` or
+   :code:`protected`, but is being accessed from outside that class (if
+   local) or a derived class (if protected).
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
 .. option:: ENDLABEL
 
-   Error that a label attached to a "end"-something statement does not
+   An error that a label attached to a "end"-something statement does not
    match the label attached to the block start.
 
-   This error is required by IEEE. Ignoring this warning will only suppress
-   the lint check, it will simulate correctly.
+   IEEE requires this error. Ignoring this warning will only suppress the
+   lint check; it will simulate correctly.
 
    Faulty example:
 
@@ -567,7 +568,7 @@ List Of Warnings
 
          %Error-ENDLABEL: example.v:2:13: End label 'not_mine' does not match begin label 'mine'
 
-   To repair either fix the end label's name, or remove entirely.
+   To repair, either fix the end label's name, or remove it entirely.
 
    .. code-block:: sv
       :linenos:
@@ -583,9 +584,9 @@ List Of Warnings
 
 .. option:: ENUMVALUE
 
-   Error that an enum data type value is being assigned from another data
+   An error that an enum data type value is being assigned from another data
    type that is not implicitly assignment compatible with that enumerated
-   type.  This error is required by IEEE, but it may be disabled.
+   type.  IEEE requires this error, but it may be disabled.
 
    Faulty example:
 
@@ -605,7 +606,7 @@ List Of Warnings
          typedef enum { ZERO } e_t;
          initial e_t en = ZERO;  //<--- Repaired
 
-   Or, alternatively use a static cast:
+   Alternatively use a static cast:
 
    .. code-block:: sv
       :linenos:
@@ -618,12 +619,12 @@ List Of Warnings
 .. option:: EOFNEWLINE
 
    Warns that a file does not end in a newline.  POSIX defines that a line
-   must end in newline, as otherwise for example :command:`cat` with the
+   must end in a newline, as otherwise, for example :command:`cat` with the
    file as an argument may produce undesirable results.
 
    Repair by appending a newline to the end of the file.
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
    Other tools with similar warnings: Verible's posix-eof, "File must end
@@ -634,8 +635,8 @@ List Of Warnings
 
    Historical, never issued since version 5.000.
 
-   Indicated that the specified signal was generated inside the model, and
-   was also being used as a clock.
+   Indicated that the specified signal was generated inside the model and
+   used as a clock.
 
 
 .. option:: HIERBLOCK
@@ -649,18 +650,19 @@ List Of Warnings
 
    Warns that if/if else statements have exceeded the depth specified with
    :vlopt:`--if-depth`, as they are likely to result in slow priority
-   encoders.  Statements below unique and priority if statements are
-   ignored.  Solutions include changing the code to a case statement, or a
-   SystemVerilog :code:`unique if` or :code:`priority if`.
+   encoders.  Statements below unique and priority :code:`if` statements
+   are ignored.  Solutions include changing the code to a case statement,
+   or using a SystemVerilog :code:`unique if` or :code:`priority if`
+   statement.
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
 
 .. option:: IGNOREDRETURN
 
    Warns that a non-void function is being called as a task, and hence the
-   return value is being ignored. This warning is required by IEEE.
+   return value is being ignored. IEEE requires this warning.
 
    .. code-block:: sv
       :linenos:
@@ -691,7 +693,7 @@ List Of Warnings
 
          initial void'(function_being_called_as_task());  //<--- Repaired
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -699,26 +701,26 @@ List Of Warnings
 
    Historical, never issued since version 5.000.
 
-   Warned that the scheduling of the model is not absolutely perfect, and
-   some manual code edits may result in faster performance.  This warning
-   defaulted to off, was not part of -Wall, and had to be turned on
-   explicitly before the top module statement is processed.
+   Warned that the scheduling of the model is not perfect, and some manual
+   code edits may result in faster performance.  This warning defaulted to
+   off, was not part of :vlopt:`-Wall`, and had to be turned on explicitly
+   before the top module statement was processed.
 
 
 .. option:: IMPLICIT
 
    .. TODO better example
 
-   Warns that a wire is being implicitly declared (it is a single bit wide
+   Warns that a wire is being implicitly declared (it is a single-bit wide
    output from a sub-module.)  While legal in Verilog, implicit
-   declarations only work for single bit wide signals (not buses), do not
+   declarations only work for single-bit wide signals (not buses), do not
    allow using a signal before it is implicitly declared by an instance,
    and can lead to dangling nets.  A better option is the
    :code:`/*AUTOWIRE*/` feature of Verilog-Mode for Emacs, available from
    `https://www.veripool.org/verilog-mode
    <https://www.veripool.org/verilog-mode>`_
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
    Other tools with similar warnings: Icarus Verilog's implicit, "warning:
@@ -731,11 +733,11 @@ List Of Warnings
 
    Warns that an :code:`import {package}::*` statement is in $unit
    scope. This causes the imported symbols to pollute the global namespace,
-   defeating much of the purpose of having a package. Generally
-   :code:`import ::*` should only be used inside a lower scope such as a
+   defeating much of the purpose of having a package. Generally,
+   :code:`import ::*` should only be used inside a lower scope, such as a
    package or module.
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
 
@@ -745,7 +747,7 @@ List Of Warnings
 
    Warns that a task or function that has been marked with a
    :option:`/*verilator&32;no_inline_task*/` metacomment, but it references
-   variables that are not local to the task.  Verilator cannot schedule
+   variables that are not local to the task, and Verilator cannot schedule
    these variables correctly.
 
    Ignoring this warning may make Verilator simulations differ from other
@@ -759,11 +761,11 @@ List Of Warnings
    Warns that an "\`include" filename specifies an absolute path.  This
    means the code will not work on any other system with a different file
    system layout.  Instead of using absolute paths, relative paths
-   (preferably without any directory specified whatsoever) should be used,
+   (preferably without any directory specified) should be used,
    and +incdir used on the command line to specify the top include source
    directories.
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
 
@@ -771,14 +773,15 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that a while or for statement has a condition that is always true.
-   and thus results in an infinite loop if the statement ever executes.
+   Warns that a :code:`while` or :code:`for` statement has a condition that
+   is always true, and thus results in an infinite loop if the statement
+   ever executes.
 
    This might be unintended behavior if Verilator is run with
    :vlopt:`--no-timing` and the loop body contains statements that would make
    time pass otherwise.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly (i.e. hang due to the infinite loop).
 
 
@@ -786,9 +789,9 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that the code has a delayed assignment inside of an initial or
-   final block.  If this message is suppressed, Verilator will convert this
-   to a non-delayed assignment.  See also :option:`COMBDLY`.
+   Warns that the code has a delayed assignment inside of an :code:`initial`
+   or :code:`final` block.  If this message is suppressed, Verilator will
+   convert this to a non-delayed assignment.  See also :option:`COMBDLY`.
 
    Ignoring this warning may make Verilator simulations differ from other
    simulators.
@@ -796,12 +799,12 @@ List Of Warnings
 
 .. option:: INSECURE
 
-   Warns that the combination of options selected may be defeating the
+   Warns that the combination of selected options may defeat the
    attempt to protect/obscure identifiers or hide information in the model.
    Correct the options provided, or inspect the output code to see if the
    information exposed is acceptable.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -815,7 +818,7 @@ List Of Warnings
    keyword instead.  The warning may be disabled with a lint_off pragma
    around the always block.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -828,12 +831,12 @@ List Of Warnings
    standard, and little numbering is now thus often due to simple oversight
    instead of intent.
 
-   Also warns that an instance is declared with little endian range
-   (i.e. [0:7] or [7]) and is connected to a N-wide signal. Based on IEEE
-   the bits will likely be backwards from what people may expect
-   (i.e. instance [0] will connect to signal bit [N-1] not bit [0]).
+   It also warns that an instance is declared with little endian range
+   (i.e. [0:7] or [7]) and is connected to an N-wide signal. Based on IEEE
+   the bits will likely be backward from what people may expect
+   (i.e., instance [0] will connect to signal bit [N-1] not bit [0]).
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -844,14 +847,14 @@ List Of Warnings
          #(3:5:8) clk = ~clk;
 
    Warns that minimum, typical, and maximum delay expressions are currently
-   unsupported. Only the typical delay value is used by Verilator.
+   unsupported. Verilator uses only the typical delay value.
 
 
 .. option:: MODDUP
 
    .. TODO better example
 
-   Warns that a module has multiple definitions.  Generally this indicates
+   Warns that a module has multiple definitions.  Generally, this indicates
    a coding error, or a mistake in a library file, and it's good practice
    to have one module per file (and only put each file once on the command
    line) to avoid these issues.  For some gate level netlists duplicates
@@ -863,9 +866,9 @@ List Of Warnings
 
 .. option:: MULTIDRIVEN
 
-   Warns that the specified signal comes from multiple always blocks each
-   with different clocking. This warning does not look at individual bits
-   (see example below).
+   Warns that the specified signal comes from multiple :code:`always`
+   blocks, each with different clocking. This warning does not look at
+   individual bits (see the example below).
 
    This is considered bad style, as the consumer of a given signal may be
    unaware of the inconsistent clocking, causing clock domain crossing
@@ -879,8 +882,8 @@ List Of Warnings
 
    .. include:: ../../docs/gen/ex_MULTIDRIVEN_msg.rst
 
-   Ignoring this warning will only slow simulations, it will simulate
-   correctly.  It may however cause longer simulation runtimes due to
+   Ignoring this warning will only slow simulations; it will simulate
+   correctly.  It may, however, cause longer simulation runtimes due to
    reduced optimizations.
 
 
@@ -888,40 +891,41 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that there are multiple top level modules, that is modules not
-   instantiated by any other module, and both modules were put on the
-   command line (not in a library). Three likely cases:
+   Warns that multiple top-level modules are not instantiated by any other
+   module, and both modules were put on the command line (not in a
+   library). Three likely cases:
 
    1. A single module is intended to be the top. This warning then occurs
-   because some low level instance is being read in, but is not really
-   needed as part of the design.  The best solution for this situation is
-   to ensure that only the top module is put on the command line without
-   any flags, and all remaining library files are read in as libraries with
+   because some low-level instance is being read in but is not needed as
+   part of the design.  The best solution for this situation is to ensure
+   that only the top module is put on the command line without any flags,
+   and all remaining library files are read in as libraries with
    :vlopt:`-v`, or are automatically resolved by having filenames that
    match the module names.
 
    2. A single module is intended to be the top, the name of it is known,
    and all other modules should be ignored if not part of the design.  The
-   best solution is to use the :vlopt:`--top` option to specify the top module's
-   name. All other modules that are not part of the design will be for the
-   most part ignored (they must be clean in syntax and their contents will
-   be removed as part of the Verilog module elaboration process.)
+   best solution is to use the :vlopt:`--top` option to specify the top
+   module's name. All other modules that are not part of the design will be
+   for the most part, ignored (they must be clean in syntax, and their
+   contents will be removed as part of the Verilog module elaboration
+   process.)
 
-   3. Multiple modules are intended to be design tops, e.g. when linting a
+   3. Multiple modules are intended to be design tops, e.g., when linting a
    library file.  As multiple modules are desired, disable the MULTITOP
    warning.  All input/outputs will go uniquely to each module, with any
    conflicting and identical signal names being made unique by adding a
    prefix based on the top module name followed by __02E (a
    Verilator-encoded ASCII ".").  This renaming is done even if the two
-   modules' signals seem identical, e.g. multiple modules with a "clk"
+   modules' signals seem identical, e.g., multiple modules with a "clk"
    input.
 
 
 .. option:: NEEDTIMINGOPT
 
-    Error when a timing-related construct, such as an event control or delay,
-    has been encountered, without specifying how Verilator should handle it
-    (neither :vlopt:`--timing` nor :vlopt:`--no-timing` option was provided).
+   Error when a timing-related construct, such as an event control or delay,
+   has been encountered, without specifying how Verilator should handle it
+   (neither :vlopt:`--timing` nor :vlopt:`--no-timing` option was provided).
 
 
 .. option:: NOLATCH
@@ -932,7 +936,7 @@ List Of Warnings
    may be disabled with a lint_off pragma around the always block, but
    recoding using a regular always may be more appropriate.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
@@ -946,11 +950,11 @@ List Of Warnings
 .. option:: NULLPORT
 
    Warns that a null port was detected in the module definition port
-   list. Null ports are empty placeholders, i.e. either one ore more commas
+   list. Null ports are empty placeholders, i.e., either one or more commas
    at the beginning or the end of a module port list, or two or more
    consecutive commas in the middle of a module port list. A null port
    cannot be accessed within the module, but when instantiating the module
-   by port order, it is treated like a regular port and any wire connected
+   by port order, it is treated like a regular port, and any wire connected
    to it is left unconnected. For example:
 
    .. code-block:: sv
@@ -961,22 +965,22 @@ List Of Warnings
           (a_named_port, );  //<--- Warning
 
    This is considered a warning because null ports are rarely used, and is
-   mostly the result of a typing error such as a dangling comma at the end
-   of a port list.
+   commonly the result of a typing error, such as a dangling comma at the
+   end of a port list.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 .. option:: PINCONNECTEMPTY
 
    .. TODO better example
 
-   Warns that an instance has a pin which is connected to
-   :code:`.pin_name()`, e.g. not another signal, but with an explicit
+   Warns that an instance has a pin that is connected to
+   :code:`.pin_name()`, e.g., not another signal, but with an explicit
    mention of the pin.  It may be desirable to disable PINCONNECTEMPTY, as
-   this indicates intention to have a no-connect.
+   this indicates the intention to have a no-connect.
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
 
@@ -984,11 +988,11 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that a module has a pin which is not mentioned in an instance.  If
+   Warns that a module has a pin that is not mentioned in an instance.  If
    a pin is not missing it should still be specified on the instance
-   declaration with an empty connection, using :code:`(.pin_name())`.
+   declaration with an empty connection using :code:`(.pin_name())`.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
    Other tools with similar warnings: Icarus Verilog's portbind, "warning:
@@ -1000,16 +1004,16 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that an instance has a pin which is not connected to another
+   Warns that an instance has a pin that is not connected to another
    signal.
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
 
 .. option:: PINNOTFOUND
 
-   Warns that an instance port or Parameter was not found in the module
+   Warns that an instance port or parameter was not found in the module
    being instantiated. Note that Verilator raises these errors also on
    instances that should be disabled by generate/if/endgenerate constructs:
 
@@ -1031,8 +1035,8 @@ List Of Warnings
        endmodule
 
    In the example above, b is instantiated with a port named x, but module
-   b has no such port. In the next line, b is instantiated again with a
-   nonexistent parameter PX. Technically, this code is incorrect because of
+   b has no such port. In the following line, b is instantiated with a
+   nonexistent PX parameter. Technically, this code is incorrect because of
    this, but other tools may ignore it because module b is not instantiated
    due to the generate/if condition being false.
 
@@ -1056,7 +1060,7 @@ List Of Warnings
          assign out = '1;
        endmodule
 
-   In the example above, out is an output but is connected to a constant
+   In the example above, out is an output but is connected to a constant,
    implying it is an input.
 
    This error may be disabled with a lint_off PORTSHORT metacomment.
@@ -1066,8 +1070,8 @@ List Of Warnings
 
    .. TODO better example
 
-   Error that a package/class appears to have been referenced that has not
-   yet been declared.  According to IEEE 1800-2017 26.3 all packages must
+   An error that a package/class appears to have been referenced that has not
+   yet been declared.  According to IEEE 1800-2017 26.3, all packages must
    be declared before being used.
 
 
@@ -1075,30 +1079,30 @@ List Of Warnings
 
    .. TODO better example
 
-   Error that a procedural assignment is setting a wire. According to IEEE,
+   An error that a procedural assignment is setting a wire. According to IEEE,
    a var/reg must be used as the target of procedural assignments.
 
 
 .. option:: PROFOUTOFDATE
 
-   Warns that threads were scheduled using estimated costs, despite the
-   fact that data was provided from profile-guided optimization (see
+   Warns that threads were scheduled using estimated costs, even though
+   that data was provided from profile-guided optimization (see
    :ref:`Thread PGO`) as fed into Verilator using the
    :option:`profile_data` configuration file option.  This usually
-   indicates that the profile data was generated from different Verilog
+   indicates that the profile data was generated from a different Verilog
    source code than Verilator is currently running against.
 
    It is recommended to create new profiling data, then rerun Verilator
    with the same input source files and that new profiling data.
 
-   Ignoring this warning may only slow simulations, it will simulate
+   Ignoring this warning may only slow simulations; it will simulate
    correctly.
 
 
 .. option:: PROTECTED
 
    Warning that a 'pragma protected' section was encountered. The code
-   inside the protected region will be partly checked for correctness, but is
+   inside the protected region will be partly checked for correctness but is
    otherwise ignored.
 
    Suppressing the warning may make Verilator differ from a simulator that
@@ -1107,8 +1111,8 @@ List Of Warnings
 
 .. option:: RANDC
 
-   Warns that the :code:`randc` keyword is currently unsupported, and that
-   it is being converted to :code:`rand`.
+   Warns that the :code:`randc` keyword is unsupported and being converted
+   to :code:`rand`.
 
 
 .. option:: REALCVT
@@ -1164,7 +1168,7 @@ List Of Warnings
                               example.v:1:20: ... Location of previous definition, with value: 'def2'
 
    The best solution is to use a different name for the second macro.  If
-   this is not possible, add an undef to indicate the code is overriding the
+   this is infeasible, add an undef to indicate that the code overriding the
    value. This will express the intent and should avoid future warnings on
    any linting tool:
 
@@ -1203,8 +1207,8 @@ List Of Warnings
          wire vec[6:0];
          initial out = vec[7];  //<--- Warning (there is no [7])
 
-   Verilator will assume zero for this value, instead of X.  Note that in
-   some cases this warning may be false, when a condition upstream or
+   Verilator will assume zero for this value instead of X.  Note that in
+   some cases, this warning may be false, when a condition upstream or
    downstream of the access means the access out of bounds will never
    execute or be used.
 
@@ -1226,7 +1230,7 @@ List Of Warnings
 
 .. option:: SHORTREAL
 
-   Warns that Verilator does not support :code:`shortreal` and they will be
+   Warns that Verilator does not support :code:`shortreal`, and they will be
    automatically promoted to :code:`real`.
 
    .. code-block:: sv
@@ -1246,8 +1250,8 @@ List Of Warnings
          real sig;  //<--- Repaired
 
    Ignoring this warning may make Verilator simulations differ from other
-   simulators, if the increased precision of real affects your model or DPI
-   calls.
+   simulators if the increased precision of :code:`real` affects the
+   modeled values, or DPI calls.
 
 
 .. option:: SPLITVAR
@@ -1255,23 +1259,23 @@ List Of Warnings
    Warns that a variable with a :option:`/*verilator&32;split_var*/`
    metacomment was not split.  Some possible reasons for this are:
 
-   * The datatype of the variable is not supported for splitting. (e.g. is
+   * The datatype of the variable is not supported for splitting. (e.g., is
      a real).
 
    * The access pattern of the variable can not be determined
-     statically. (e.g. is accessed as a memory).
+     statically. (e.g., is accessed as a memory).
 
    * The index of the array exceeds the array size.
 
-   * The variable is accessed from outside using dotted reference.
-     (e.g. top.instance0.variable0 = 1).
+   * The variable is accessed from outside using a dotted reference.
+     (e.g. :code:`top.instance0.variable0 = 1`).
 
    * The variable is not declared in a module, but in a package or an
      interface.
 
    * The variable is a parameter, localparam, genvar, or queue.
 
-   * The variable is tristate or bidirectional. (e.g. inout or ref).
+   * The variable is tristate or bidirectional. (e.g., :code:`inout`).
 
 
 .. option:: STMTDLY
@@ -1292,7 +1296,7 @@ List Of Warnings
    This warning is issued only if Verilator is run with :vlopt:`--no-timing`.
    All delays on statements are ignored in this mode.  In many cases ignoring a
    delay might be harmless, but if the delayed statement is, as in this
-   example, used to cause some important action at a later time, it might be an
+   example, used to cause some important action later, it might be an
    important difference.
 
    Some possible workarounds:
@@ -1300,7 +1304,7 @@ List Of Warnings
    * Move the delayed statement into the C++ wrapper file, where the
      stimulus and clock generation can be done in C++.
 
-   * Convert the statement into a FSM, or other statement that tests
+   * Convert the statement into an FSM, or other statement that tests
      against $time.
 
    * Run Verilator with :vlopt:`--timing`.
@@ -1308,10 +1312,9 @@ List Of Warnings
 
 .. option:: SYMRSVDWORD
 
-   Warning that a symbol matches a C++ reserved word and using this as a
+   Warning that a symbol matches a C++ reserved word, and using this as a
    symbol name would result in odd C++ compiler errors.  You may disable
-   this warning, but the symbol will be renamed by Verilator to avoid the
-   conflict.
+   this warning, but Verilator will rename the symbol to avoid conflict.
 
 
 .. option:: SYNCASYNCNET
@@ -1319,21 +1322,20 @@ List Of Warnings
    .. TODO better example
 
    Warns that the specified net is used in at least two different always
-   statements with posedge/negedges (i.e. a flop).  One usage has the
+   statements with posedge/negedges (i.e., a flop).  One usage has the
    signal in the sensitivity list and body, probably as an async reset, and
-   the other usage has the signal only in the body, probably as a sync
-   reset.  Mixing sync and async resets is usually a mistake.  The warning
-   may be disabled with a lint_off pragma around the net, or either flopped
-   block.
+   the other has the signal only in the body, probably as a sync reset.
+   Mixing sync and async resets is usually a mistake.  The warning may be
+   disabled with a lint_off pragma around the net or flopped block.
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
 
 .. option:: TASKNSVAR
 
    Error when a call to a task or function has an inout from that task tied
-   to a non-simple signal.  Instead connect the task output to a temporary
+   to a non-simple signal.  Instead, connect the task output to a temporary
    signal of the appropriate width, and use that signal to set the
    appropriate expression as the next statement.  For example:
 
@@ -1366,11 +1368,11 @@ List Of Warnings
 .. option:: TICKCOUNT
 
    Warns that the number of ticks to delay a $past variable is greater
-   than 10.  At present Verilator effectively creates a flop for each
-   delayed signals, and as such any large counts may lead to large design
+   than 10.  At present, Verilator effectively creates a flop for each
+   delayed signal, and as such, any large counts may lead to large design
    size increases.
 
-   Ignoring this warning will only slow simulations, it will simulate
+   Ignoring this warning will only slow simulations; it will simulate
    correctly.
 
 
@@ -1378,10 +1380,10 @@ List Of Warnings
 
    Warns that "\`timescale" is used in some but not all modules.
 
-   This may be disabled similar to other warnings.  Ignoring this warning
+   This may be disabled, similar to other warnings.  Ignoring this warning
    may result in a module having an unexpected timescale.
 
-   IEEE recommends this be an error, for that behavior use
+   IEEE recommends this be an error; for that behavior, use
    :vlopt:`-Werror-TIMESCALEMOD <-Werror-\<message\>>`.
 
    Faulty example:
@@ -1410,7 +1412,7 @@ List Of Warnings
 
          `include "timescale.vh"
 
-   Then in that file set the timescale.
+   Then in that file, set the timescale.
 
    Other tools with similar warnings: Icarus Verilog's timescale, "warning:
    Some design elements have no explicit time unit and/or time
@@ -1422,11 +1424,11 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that the specified signal has no source.  Verilator is fairly
+   Warns that the specified signal has no source.  Verilator is relatively
    liberal in the usage calculations; making a signal public, or setting
    only a single array element marks the entire signal as driven.
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
    Other tools with similar warnings: Odin's "[NETLIST] This output is
@@ -1440,7 +1442,7 @@ List Of Warnings
    Warned that due to some construct, optimization of the specified signal
    or block was disabled.
 
-   Ignoring this warning only slowed simulations, it simulated correctly.
+   Ignoring this warning only slowed simulations; it simulated correctly.
 
 
 .. option:: UNOPTFLAT
@@ -1449,14 +1451,13 @@ List Of Warnings
 
    Warns that due to some construct, optimization of the specified signal
    is disabled.  The signal reported includes a complete scope to the
-   signal; it may be only one particular usage of a multiply instantiated
+   signal; it may be only one particular usage of a multiply-instantiated
    block.  The construct should be cleaned up to improve simulation
-   performance; two times better performance may be possible by fixing
-   these warnings.
+   performance.
 
    Often UNOPTFLAT is caused by logic that isn't truly circular as viewed by
-   synthesis which analyzes interconnection per-bit, but is circular to
-   simulation which analyzes per-bus.
+   synthesis, which analyzes interconnection per bit, but is circular to
+   the IEEE event model which analyzes per-signal.
 
    Faulty example:
 
@@ -1465,45 +1466,46 @@ List Of Warnings
          wire [2:0] x = {x[1:0], shift_in};
 
    This statement needs to be evaluated multiple times, as a change in
-   :code:`shift_in` requires "x" to be computed 3 times before it becomes
+   :code:`shift_in` requires "x" to be computed three times before it becomes
    stable.  This is because a change in "x" requires "x" itself to change
-   value, which causes the warning.
+   its value, which causes the warning.
 
-   For significantly better performance, split this into 2 separate signals:
+   For significantly better performance, split this into two separate signals:
 
    .. code-block:: sv
 
          wire [2:0] xout = {x[1:0], shift_in};
 
-   and change all receiving logic to instead receive "xout".
+   And change all receiving logic to instead receive "xout".
    Alternatively, change it to:
 
    .. code-block:: sv
 
          wire [2:0] x = {xin[1:0], shift_in};
 
-   and change all driving logic to instead drive "xin".
+   And change all driving logic to drive "xin" instead.
 
-   With this change this assignment needs to be evaluated only once.  These
-   sort of changes may also speed up your traditional event driven
+   With this change, this assignment needs to be evaluated only once.
+   These sorts of changes may also speed up your traditional event-driven
    simulator, as it will result in fewer events per cycle.
 
    The most complicated UNOPTFLAT path we've seen was due to low bits of a
-   bus being generated from an always statement that consumed high bits of
-   the same bus processed by another series of always blocks.  The fix is
-   the same; split it into two separate signals generated from each block.
+   bus generated from an always statement that consumed high bits of the
+   same bus processed by another series of always blocks.  The fix is the
+   same; split it into two separate signals generated from each block.
 
    Occasionally UNOPTFLAT may be indicated when there is a true
-   circulation.  e.g. if trying to implement a flop or latch using
-   individual gate primitives.  If UNOPTFLAT is suppressed the code may get
-   a DIDNOTCONVERGE error. Verilator does not support building flops or
+   circulation.  e.g., if trying to implement a flop or latch using
+   individual gate primitives.  If UNOPTFLAT is suppressed, the code may
+   get a DIDNOTCONVERGE error. Verilator does not support building flops or
    latches out of gate primitives, and any such code must change to use
-   behavioral constructs (e.g. always_ff and always_latch).
+   behavioral constructs (e.g., :code:`always_ff` and
+   :code:`always_latch`).
 
    Another way to resolve this warning is to add a
    :option:`/*verilator&32;split_var*/` metacomment described above. This
    will cause the variable to be split internally, potentially resolving
-   the conflict. If you run with `--report-unoptflat` Verilator will
+   the conflict. If you run with :vlopt:`--report-unoptflat`, Verilator will
    suggest possible candidates for :option:`/*verilator&32;split_var*/`.
 
    The UNOPTFLAT warning may also occur where outputs from a block of logic
@@ -1511,7 +1513,7 @@ List Of Warnings
    the :option:`/*verilator&32;isolate_assignments*/` metacomment described
    above.
 
-   Prior to version 5.000, the UNOPTFLAT warning may also have been due to
+   Before version 5.000, the UNOPTFLAT warning may also have been due to
    clock enables, identified from the reported path going through a clock
    gating instance.  To fix these, the clock_enable meta comment was used.
 
@@ -1520,7 +1522,7 @@ List Of Warnings
    split up, and a graph of all the nodes connected in the loop. See the
    Arguments section for more details.
 
-   Ignoring this warning will only slow simulations, it will simulate
+   Ignoring this warning will only slow simulations; it will simulate
    correctly.
 
 
@@ -1528,18 +1530,18 @@ List Of Warnings
 
    .. TODO better example
 
-   Warns that the thread scheduler was unable to partition the design to
-   fill the requested number of threads.
+   Warns that the thread scheduler could not partition the design to fill
+   the requested number of threads.
 
    One workaround is to request fewer threads with :vlopt:`--threads`.
 
    Another possible workaround is to allow more MTasks in the simulation
-   runtime, by increasing the value of :vlopt:`--threads-max-mtasks`. More
+   runtime by increasing the value of :vlopt:`--threads-max-mtasks`. More
    MTasks will result in more communication and synchronization overhead at
    simulation runtime; the scheduler attempts to minimize the number of
    MTasks for this reason.
 
-   Ignoring this warning will only slow simulations, it will simulate
+   Ignoring this warning will only slow simulations; it will simulate
    correctly.
 
 
@@ -1549,7 +1551,7 @@ List Of Warnings
 
    Ignoring this warning will make Verilator treat the structure as packed,
    which may make Verilator simulations differ from other simulators. This
-   downgrading may also result what would normally be a legal unpacked
+   downgrading may also result in what would typically be a legal unpacked
    struct/array inside an unpacked struct/array becoming an illegal
    unpacked struct/array inside a packed struct/array.
 
@@ -1559,26 +1561,26 @@ List Of Warnings
    .. TODO better example
 
    Warns that the code is comparing an unsigned value in a way that implies
-   it is signed, for example "X < 0" will always be false when X is
+   it is signed; for example :code:`X < 0` will always be false when X is
    unsigned.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
 
 .. option:: UNSUPPORTED
 
-   Error that a construct might be legal according to IEEE but is not
+   An error that a construct might be legal according to IEEE but is not
    currently supported by Verilator.
 
-   A typical workaround is to rewrite the construct into a simpler and more
-   common alternative language construct.
+   A typical workaround is to rewrite the construct into a more common
+   alternative language construct.
 
-   Alternatively, check if the construct is supported by other tools, and
-   if so please consider submitting a github pull request against the
-   Verilator sources to implement the missing unsupported feature.
+   Alternatively, check if other tools support the construct, and if so,
+   please consider submitting a github pull request against the Verilator
+   sources to implement the missing unsupported feature.
 
-   This error may be ignored with :vlopt:`--bbox-unsup`, however this will
+   This error may be ignored with :vlopt:`--bbox-unsup`, however, this will
    make the design simulate incorrectly and is only intended for lint
    usage; see the details under :vlopt:`--bbox-unsup`.
 
@@ -1586,7 +1588,8 @@ List Of Warnings
 .. option:: UNUSED
 
    Disabling/enabling UNUSED is equivalent to disabling/enabling the
-   `UNUSEDGENVAR`, `UNUSEDPARAM` and `UNUSEDSIGNAL` warnings.
+   :option:`UNUSEDGENVAR`, :option:`UNUSEDPARAM`, and
+   :option:`UNUSEDSIGNAL` warnings.
 
    Never issued since version 5.000.  Historically warned that a variable,
    parameter, or signal was unused.
@@ -1610,12 +1613,12 @@ List Of Warnings
    .. TODO better example
 
    Warns that the specified signal is never used/consumed.
-   Verilator is fairly liberal in the usage calculations; making a signal
+   Verilator is relatively liberal in the usage calculations; making a signal
    public, a signal matching the :vlopt:`--unused-regexp` option (default
    "\*unused\*" or accessing only a single array element marks the entire
    signal as used.
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
    A recommended style for unused nets is to put at the bottom of a file
@@ -1631,12 +1634,12 @@ List Of Warnings
    The reduction AND and constant zeros mean the net will always be zero,
    so won't use simulation runtime.  The redundant leading and trailing
    zeros avoid syntax errors if there are no signals between them.  The
-   magic name "unused" (controlled by :vlopt:`--unused-regexp` option) is
-   recognized by Verilator and suppresses warnings; if using other lint
-   tools, either teach it to the tool to ignore signals with "unused" in
-   the name, or put the appropriate lint_off around the wire.  Having
-   unused signals in one place makes it easy to find what is unused, and
-   reduces the number of lint_off pragmas, reducing bugs.
+   magic name "unused" (controlled by the :vlopt:`--unused-regexp` option)
+   is recognized by Verilator and suppresses warnings; if using other lint
+   tools, either teach the tool to ignore signals with "unused" in the
+   name, or put the appropriate lint_off around the wire.  Having unused
+   signals in one place makes it easy to find what is unused and reduces
+   the number of lint_off pragmas, reducing bugs.
 
 
 .. option:: USERERROR
@@ -1674,7 +1677,8 @@ List Of Warnings
 .. option:: USERINFO
 
    A SystemVerilog elaboration-time assertion print was executed.  This is
-   not an error nor warning.  IEEE 1800-2017 20.11 requires this behavior.
+   not an error or warning, and IEEE 1800-2017 20.11 requires this
+   behavior.
 
    Example:
 
@@ -1704,11 +1708,11 @@ List Of Warnings
 .. option:: VARHIDDEN
 
    Warns that a task, function, or begin/end block is declaring a variable
-   by the same name as a variable in the upper level module or begin/end
+   by the same name as a variable in the upper-level module or begin/end
    block (thus hiding the upper variable from being able to be used.)
    Rename the variable to avoid confusion when reading the code.
 
-   Disabled by default as this is a code style warning; it will simulate
+   Disabled by default as this is a code-style warning; it will simulate
    correctly.
 
    Faulty example:
@@ -1719,7 +1723,7 @@ List Of Warnings
 
    .. include:: ../../docs/gen/ex_VARHIDDEN_msg.rst
 
-   To resolve, rename the variable to an unique name.
+   To resolve this, rename the variable to an unique name.
 
 
 .. option:: WAITCONST
@@ -1734,36 +1738,36 @@ List Of Warnings
 
 .. option:: WIDTH
 
-   Warns that based on width rules of Verilog:
+   Warns that based on the width rules of Verilog:
 
-   * Two operands have different widths, e.g. adding a 2-bit and 5-bit
+   * Two operands have different widths, e.g., adding a 2-bit and 5-bit
      number.
 
    * A part select has a different size then needed to index into the
-     packed or unpacked array (etc).
+     packed or unpacked array, etc.
 
    Verilator attempts to track the minimum width of unsized constants
    and will suppress the warning when the minimum width is appropriate to
    fit the required size.
 
-   Ignoring this warning will only suppress the lint check, it will
+   Ignoring this warning will only suppress the lint check; it will
    simulate correctly.
 
    The recommendation is to fix these issues by:
 
-   * Resizing the variable or constant to match the needed size for the
-     expression.  E.g. :code:`2'd2` instead of :code:`3'd2`.
+   * Resize the variable or constant to match the needed size for the
+     expression.  E.g., :code:`2'd2` instead of :code:`3'd2`.
 
-   * Using :code:`'0` or :code:`'1` which automatically resize in an
+   * Using :code:`'0` or :code:`'1`, which automatically resize in an
      expression.
 
-   * Using part selects to narrow a variable. E.g. :code:`too_wide[1:0]`.
+   * Using part selects to narrow a variable; e.g., :code:`too_wide[1:0]`.
 
-   * Using concatenate to widen a variable. E.g. :code:`{1'b1, too_narrow}`.
+   * Using concatenate to widen a variable; e.g., :code:`{1'b1, too_narrow}`.
 
-   * Using cast to resize a variable. E.g. :code:`23'(wrong_sized)`.
+   * Using cast to resize a variable; e.g., :code:`23'(wrong_sized)`.
 
-   For example this is a missized index:
+   For example, this is a missized index:
 
    .. include:: ../../docs/gen/ex_WIDTH_1_faulty.rst
 
@@ -1778,10 +1782,10 @@ List Of Warnings
 
 .. option:: WIDTHCONCAT
 
-   Warns that based on width rules of Verilog, a concatenate or replication
-   has an indeterminate width.  In most cases this violates the Verilog
-   rule that widths inside concatenates and replicates must be sized, and
-   should be fixed in the code.
+   Warns that based on the width rules of Verilog, a concatenate, or
+   replication has an indeterminate width.  In most cases, this violates
+   the Verilog rule that widths inside concatenates and replicates must be
+   sized and should be fixed in the code.
 
    Faulty example:
 
@@ -1796,7 +1800,7 @@ List Of Warnings
          parameter PAR = 1;
          wire [63:0] concat = {PAR, PAR};
 
-   The correct fix is to either size the 1 (:code:`32'h1`), or add the
+   The correct fix is to either size the 1 (:code:`32'h1`), add the
    width to the parameter definition (:code:`parameter [31:0]`), or add the
    width to the parameter usage (:code:`{PAR[31:0], PAR[31:0]}`).
 
diff --git a/docs/spelling.txt b/docs/spelling.txt
index c47f7dda6..a8b15ca87 100644
--- a/docs/spelling.txt
+++ b/docs/spelling.txt
@@ -45,6 +45,7 @@ Cochrane
 Cuan
 Cygwin
 DErrico
+DFG
 Da
 Danilo
 Dannoritzer
@@ -606,6 +607,7 @@ ifndef
 impot
 incdir
 includer
+incrementing
 inferfaces
 inhibitSim
 initarray
@@ -646,6 +648,7 @@ localparams
 localtime
 logicals
 longint
+lossy
 lsb
 lvalue
 lxt

From 86e3c02339c48b81ce8673e0c4adeb41d0bdd000 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 11 Dec 2022 09:43:42 -0500
Subject: [PATCH 139/156] Internal: Remove stale make rule (#3811).

---
 src/Makefile_obj.in | 26 ++++++++++----------------
 1 file changed, 10 insertions(+), 16 deletions(-)

diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in
index 616b9c43e..a0f995f8f 100644
--- a/src/Makefile_obj.in
+++ b/src/Makefile_obj.in
@@ -157,7 +157,7 @@ RAW_OBJS = \
 	V3Assert.o \
 	V3AssertPre.o \
 	V3Ast.o	\
-	V3AstNodes.o	\
+	V3AstNodes.o \
 	V3Begin.o \
 	V3Branch.o \
 	V3Broken.o \
@@ -188,7 +188,6 @@ RAW_OBJS = \
 	V3DfgPasses.o \
 	V3DfgPeephole.o \
 	V3DupFinder.o \
-	V3Timing.o \
 	V3EmitCBase.o \
 	V3EmitCConstPool.o \
 	V3EmitCFunc.o \
@@ -210,8 +209,8 @@ RAW_OBJS = \
 	V3Gate.o \
 	V3Global.o \
 	V3Graph.o \
-	V3GraphAlg.o \
 	V3GraphAcyc.o \
+	V3GraphAlg.o \
 	V3GraphPathChecker.o \
 	V3GraphTest.o \
 	V3Hash.o \
@@ -224,8 +223,8 @@ RAW_OBJS = \
 	V3LifePost.o \
 	V3LinkCells.o \
 	V3LinkDot.o \
-	V3LinkJump.o \
 	V3LinkInc.o \
+	V3LinkJump.o \
 	V3LinkLValue.o \
 	V3LinkLevel.o \
 	V3LinkParse.o \
@@ -239,7 +238,11 @@ RAW_OBJS = \
 	V3Order.o \
 	V3Os.o \
 	V3Param.o \
+	V3ParseGrammar.o \
+	V3ParseImp.o \
+	V3ParseLex.o \
 	V3Partition.o \
+	V3PreProc.o \
 	V3PreShell.o \
 	V3Premit.o \
 	V3ProtectLib.o \
@@ -260,12 +263,13 @@ RAW_OBJS = \
 	V3StatsReport.o \
 	V3String.o \
 	V3Subst.o \
+	V3TSP.o \
 	V3Table.o \
 	V3Task.o \
+	V3Timing.o \
 	V3Trace.o \
 	V3TraceDecl.o \
 	V3Tristate.o \
-	V3TSP.o \
 	V3Undriven.o \
 	V3Unknown.o \
 	V3Unroll.o \
@@ -274,13 +278,6 @@ RAW_OBJS = \
 	V3Width.o \
 	V3WidthSel.o \
 
-# Non-concatable
-NC_OBJS += \
-	V3ParseImp.o \
-	V3ParseGrammar.o \
-	V3ParseLex.o \
-	V3PreProc.o \
-
 # verilator_coverage
 VLCOV_OBJS = \
 	VlcMain.o \
@@ -311,15 +308,12 @@ ASTGENFLAGS += $(foreach f,$(DFG_DEFS),--dfgdef $f)
 
 ifeq ($(VL_VLCOV),)
 PREDEP_H = V3Ast__gen_forward_class_decls.h
-OBJS += $(RAW_OBJS) $(NC_OBJS)
+OBJS += $(RAW_OBJS)
 else
 PREDEP_H =
 OBJS += $(VLCOV_OBJS)
 endif
 
-V3__CONCAT.cpp: $(addsuffix .cpp, $(basename $(RAW_OBJS)))
-	$(PERL) $(srcdir)/../bin/verilator_includer $^ > $@
-
 $(TGT): $(PREDEP_H) $(OBJS)
 	@echo "      Linking $@..."
 	${LINK} ${LDFLAGS} -o $@ $(OBJS) $(CCMALLOC) ${LIBS}

From 3f4d4dec773bd1a1c0a7c0bebbfc866395476254 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 11 Dec 2022 11:50:22 -0500
Subject: [PATCH 140/156] Fix ENUMVALUE on typedef (#3777)

---
 Changes                              |  2 +-
 src/V3Width.cpp                      | 39 ++++++++++++++++------------
 test_regress/t/t_cast_param_logic.pl | 17 ++++++++++++
 test_regress/t/t_cast_param_logic.v  | 20 ++++++++++++++
 4 files changed, 61 insertions(+), 17 deletions(-)
 create mode 100755 test_regress/t/t_cast_param_logic.pl
 create mode 100644 test_regress/t/t_cast_param_logic.v

diff --git a/Changes b/Changes
index 1cbddc1f2..fbba7fd90 100644
--- a/Changes
+++ b/Changes
@@ -19,7 +19,7 @@ Verilator 5.003 devel
 * Support pre_randomize and post_randomize.
 * Support $timeunit and $timeprecision.
 * Support assignment expressions.
-* Add ENUMVALUE warning when value misused for enum (#726).
+* Add ENUMVALUE warning when value misused for enum (#726) (#3777).
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Change ENDLABEL from warning into an error.
 * Deprecate verilated_fst_sc.cpp and verilated_vcd_sc.cpp.
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index a766baca8..2632f7679 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1941,6 +1941,7 @@ private:
             // if (debug()) nodep->backp()->dumpTree("-  CastOutUpUp: ");
         }
         if (m_vup->final()) {
+            // if (debug()) nodep->dumpTree(cout, "-  CastFPit: ");
             iterateCheck(nodep, "value", nodep->fromp(), SELF, FINAL, nodep->fromp()->dtypep(),
                          EXTEND_EXP, false);
             AstNode* const underp = nodep->fromp()->unlinkFrBack();
@@ -6966,28 +6967,20 @@ private:
         toDtp = toDtp->skipRefToEnump();
         fromDtp = fromDtp->skipRefToEnump();
         if (toDtp == fromDtp) return COMPATIBLE;
-        const AstNodeDType* fromBaseDtp = fromDtp;
-        while (const AstPackArrayDType* const packp = VN_CAST(fromBaseDtp, PackArrayDType)) {
-            fromBaseDtp = packp->subDTypep();
-            while (const AstRefDType* const refp = VN_CAST(fromBaseDtp, RefDType)) {
-                fromBaseDtp = refp->refDTypep();
-            }
-        }
+
+        // UNSUP unpacked struct/unions (treated like BasicDType)
+        const AstNodeDType* fromBaseDtp = computeCastableBase(fromDtp);
         const bool fromNumericable = VN_IS(fromBaseDtp, BasicDType)
                                      || VN_IS(fromBaseDtp, EnumDType)
                                      || VN_IS(fromBaseDtp, NodeUOrStructDType);
 
-        const AstNodeDType* toBaseDtp = toDtp;
-        while (const AstPackArrayDType* const packp = VN_CAST(toBaseDtp, PackArrayDType)) {
-            toBaseDtp = packp->subDTypep();
-            while (const AstRefDType* const refp = VN_CAST(toBaseDtp, RefDType)) {
-                toBaseDtp = refp->refDTypep();
-            }
-        }
+        const AstNodeDType* toBaseDtp = computeCastableBase(toDtp);
         const bool toNumericable
             = VN_IS(toBaseDtp, BasicDType) || VN_IS(toBaseDtp, NodeUOrStructDType);
-        // UNSUP unpacked struct/unions (treated like BasicDType)
-        if (toNumericable) {
+
+        if (toBaseDtp == fromBaseDtp) {
+            return COMPATIBLE;
+        } else if (toNumericable) {
             if (fromNumericable) return COMPATIBLE;
         } else if (VN_IS(toDtp, EnumDType)) {
             if (VN_IS(fromBaseDtp, EnumDType) && toDtp->sameTree(fromDtp)) return ENUM_IMPLICIT;
@@ -7010,6 +7003,20 @@ private:
         }
         return castable;
     }
+    static const AstNodeDType* computeCastableBase(const AstNodeDType* nodep) {
+        while (true) {
+            if (const AstPackArrayDType* const packp = VN_CAST(nodep, PackArrayDType)) {
+                nodep = packp->subDTypep();
+                continue;
+            } else if (const AstNodeDType* const refp = nodep->skipRefToEnump()) {
+                if (refp != nodep) {
+                    nodep = refp;
+                    continue;
+                }
+            }
+            return nodep;
+        }
+    }
 
     //----------------------------------------------------------------------
     // METHODS - special type detection
diff --git a/test_regress/t/t_cast_param_logic.pl b/test_regress/t/t_cast_param_logic.pl
new file mode 100755
index 000000000..09b2ce4eb
--- /dev/null
+++ b/test_regress/t/t_cast_param_logic.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_cast_param_logic.v b/test_regress/t/t_cast_param_logic.v
new file mode 100644
index 000000000..d452b0eb5
--- /dev/null
+++ b/test_regress/t/t_cast_param_logic.v
@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t
+  #(
+    parameter type data_t = logic
+    )
+   (
+    input data_t[7:0] in_data
+    );
+
+    typedef data_t[7:0] in_data_t;
+
+    in_data_t out_data;
+    always_comb out_data = in_data_t'(in_data);
+
+endmodule

From 86b07423a935c4a0e8e8bdc687ca6bb235e9a3c5 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 11 Dec 2022 13:28:24 -0500
Subject: [PATCH 141/156] Fix ENUMVALUE on parameter (#3777).

---
 src/V3AstNodeExpr.h                 | 15 +++++++++++++++
 src/V3Width.cpp                     | 21 ++++++++++++++-------
 src/V3WidthCommit.h                 |  7 +++++++
 test_regress/t/t_cast_param_type.pl | 17 +++++++++++++++++
 test_regress/t/t_cast_param_type.v  | 23 +++++++++++++++++++++++
 test_regress/t/t_debug_emitv.out    |  2 +-
 6 files changed, 77 insertions(+), 8 deletions(-)
 create mode 100755 test_regress/t/t_cast_param_type.pl
 create mode 100644 test_regress/t/t_cast_param_type.v

diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index 5b2bb9d43..185ac1484 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -4426,6 +4426,21 @@ public:
     bool sizeMattersLhs() const override { return false; }
     int instrCount() const override { return widthInstrs() * 16; }
 };
+class AstCastWrap final : public AstNodeUniop {
+    // A cast which has been expanded and the LHSP does all the lifting
+    // This remains until V3Width final commit pass to suppress ENUMVALUE warnings
+public:
+    AstCastWrap(FileLine* fl, AstNodeExpr* lhsp)
+        : ASTGEN_SUPER_CastWrap(fl, lhsp) {}
+    ASTGEN_MEMBERS_AstCastWrap;
+    void numberOperate(V3Number& out, const V3Number& lhs) override { out.opAssign(lhs); }
+    string emitVerilog() override { return "(%l)"; }
+    string emitC() override { V3ERROR_NA_RETURN(""); }
+    bool cleanOut() const override { return false; }
+    bool cleanLhs() const override { return false; }
+    bool sizeMattersLhs() const override { return false; }
+    int instrCount() const override { return 0; }
+};
 class AstCountOnes final : public AstNodeUniop {
     // Number of bits set in vector
 public:
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 2632f7679..aa1de5970 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1861,7 +1861,7 @@ private:
         UINFO(9, "CAST " << nodep << endl);
         nodep->dtypep(iterateEditMoveDTypep(nodep, nodep->subDTypep()));
         if (m_vup->prelim()) {
-            // if (debug()) nodep->dumpTree("-  CastPre: ");
+            if (debug() >= 9) nodep->dumpTree("-  CastPre: ");
             // if (debug()) nodep->backp()->dumpTree("-  CastPreUpUp: ");
             userIterateAndNext(nodep->fromp(), WidthVP{SELF, PRELIM}.p());
             AstNodeDType* const toDtp = nodep->dtypep()->skipRefToEnump();
@@ -1937,19 +1937,22 @@ private:
             }
             if (!newp) newp = nodep->fromp()->unlinkFrBack();
             nodep->fromp(newp);
-            // if (debug()) nodep->dumpTree("-  CastOut: ");
+            if (debug() >= 9) nodep->dumpTree("-  CastOut: ");
             // if (debug()) nodep->backp()->dumpTree("-  CastOutUpUp: ");
         }
         if (m_vup->final()) {
-            // if (debug()) nodep->dumpTree(cout, "-  CastFPit: ");
+            if (debug() >= 9) nodep->dumpTree(cout, "-  CastFPit: ");
             iterateCheck(nodep, "value", nodep->fromp(), SELF, FINAL, nodep->fromp()->dtypep(),
                          EXTEND_EXP, false);
-            AstNode* const underp = nodep->fromp()->unlinkFrBack();
-            // if (debug()) underp->dumpTree("-  CastRep: ");
+            if (debug() >= 9) nodep->dumpTree("-  CastFin: ");
+            AstNodeExpr* const underp = nodep->fromp()->unlinkFrBack();
             underp->dtypeFrom(nodep);
-            nodep->replaceWith(underp);
-            VL_DO_DANGLING(pushDeletep(nodep), nodep);
             underp->didWidth(true);
+            AstNodeExpr* const newp = new AstCastWrap{nodep->fileline(), underp};
+            newp->didWidth(true);
+            if (debug() >= 9) newp->dumpTree("-  CastRep: ");
+            nodep->replaceWith(newp);
+            VL_DO_DANGLING(pushDeletep(nodep), nodep);
         }
     }
     void visit(AstCastSize* nodep) override {
@@ -1974,6 +1977,10 @@ private:
         }
         // if (debug()) nodep->dumpTree("-  CastSizeOut: ");
     }
+    void visit(AstCastWrap* nodep) override {
+        // Inserted by V3Width only so we know has been resolved
+        UASSERT_OBJ(nodep->didWidth(), nodep, "CastWrap should have width'ed earlier");
+    }
     void castSized(AstNode* nodep, AstNode* underp, int width) {
         const AstBasicDType* underDtp = VN_CAST(underp->dtypep(), BasicDType);
         if (!underDtp) underDtp = underp->dtypep()->basicp();
diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h
index 5b262b058..f9b2e191b 100644
--- a/src/V3WidthCommit.h
+++ b/src/V3WidthCommit.h
@@ -177,6 +177,13 @@ private:
         }
         editDType(nodep);
     }
+    void visit(AstCastWrap* nodep) override {
+        iterateChildren(nodep);
+        editDType(nodep);
+        UINFO(6, " Replace " << nodep << " w/ " << nodep->lhsp() << endl);
+        nodep->replaceWith(nodep->lhsp()->unlinkFrBack());
+        VL_DO_DANGLING(pushDeletep(nodep), nodep);
+    }
     void visit(AstNodeDType* nodep) override {  //
         visitIterateNodeDType(nodep);
     }
diff --git a/test_regress/t/t_cast_param_type.pl b/test_regress/t/t_cast_param_type.pl
new file mode 100755
index 000000000..09b2ce4eb
--- /dev/null
+++ b/test_regress/t/t_cast_param_type.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_cast_param_type.v b/test_regress/t/t_cast_param_type.v
new file mode 100644
index 000000000..81b24c854
--- /dev/null
+++ b/test_regress/t/t_cast_param_type.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+typedef enum logic [1:0] {A, B, C } letters_t;
+
+module SubA
+  #(parameter letters_t LETTER = A)
+   ();
+endmodule
+
+module SubB
+  #(parameter letters_t LETTER = letters_t'(0))
+   ();
+endmodule
+
+module t ();
+   SubA suba0 ();
+   SubA #(.LETTER(letters_t'(1))) suba1 ();
+   SubB #(.LETTER(letters_t'(1))) subb2 ();
+endmodule
diff --git a/test_regress/t/t_debug_emitv.out b/test_regress/t/t_debug_emitv.out
index ac753a612..dc2725f00 100644
--- a/test_regress/t/t_debug_emitv.out
+++ b/test_regress/t/t_debug_emitv.out
@@ -7,7 +7,7 @@ module Vt_debug_emitv_t;
     ???? // ENUMITEM 'ZERO'
     32'h0
     ???? // ENUMITEM 'ONE'
-    'sh1
+    32'h1
     ???? // REFDTYPE 'e_t'
     struct packed 
     {

From 722e38f5321e002689cdc533ddb09a30b570fcc1 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 11 Dec 2022 13:30:00 -0500
Subject: [PATCH 142/156] Commentary, part of last commit (#3783)

---
 Changes | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Changes b/Changes
index fbba7fd90..fdfcac42b 100644
--- a/Changes
+++ b/Changes
@@ -19,7 +19,7 @@ Verilator 5.003 devel
 * Support pre_randomize and post_randomize.
 * Support $timeunit and $timeprecision.
 * Support assignment expressions.
-* Add ENUMVALUE warning when value misused for enum (#726) (#3777).
+* Add ENUMVALUE warning when value misused for enum (#726) (#3777) (#3783).
 * Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Change ENDLABEL from warning into an error.
 * Deprecate verilated_fst_sc.cpp and verilated_vcd_sc.cpp.

From afc66f6a8547a7b1dca4ddda3f51ca97cb20e731 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 11 Dec 2022 14:19:40 -0500
Subject: [PATCH 143/156] Fix make jobserver with submakes (#3758).

---
 Changes                      | 1 +
 docs/guide/environment.rst   | 6 ++++++
 docs/guide/exe_verilator.rst | 4 ++++
 src/V3Options.cpp            | 4 ++++
 src/V3Options.h              | 1 +
 src/Verilator.cpp            | 5 ++++-
 6 files changed, 20 insertions(+), 1 deletion(-)

diff --git a/Changes b/Changes
index fdfcac42b..493f37f2d 100644
--- a/Changes
+++ b/Changes
@@ -27,6 +27,7 @@ Verilator 5.003 devel
 * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
 * Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
 * Fix tracing parameters overridden with -G (#3723). [Iztok Jeras]
+* Fix make jobserver with submakes (#3758). [Gus Smith]
 * Fix wait 0.
 * Fix comparing ranged slices of unpacked arrays.
 * Fix empty string literals converting to string types (#3774). [miree]
diff --git a/docs/guide/environment.rst b/docs/guide/environment.rst
index 99ef9767c..03edf7754 100644
--- a/docs/guide/environment.rst
+++ b/docs/guide/environment.rst
@@ -20,6 +20,12 @@ associated programs.
    this variable to launch GNU make.  If this variable is not specified,
    "make" is used.
 
+.. option:: MAKEFLAGS
+
+   Flags created by :command:`make` to pass to submakes. Verilator searches
+   this variable to determine if a jobserver is used; see
+   :vlopt:`--build-jobs`.
+
 .. option:: OBJCACHE
 
    Optionally specifies a caching or distribution program to place in front
diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst
index 2ba344e72..8230d3e6b 100644
--- a/docs/guide/exe_verilator.rst
+++ b/docs/guide/exe_verilator.rst
@@ -144,6 +144,10 @@ Summary:
    be a positive integer specifying the maximum number of parallel build
    jobs.
 
+   This forms the :command:`make` option ``-j`` value, unless the
+   :option:`MAKEFLAGS` environment variable contains ``-jobserver-auth``,
+   in which case Verilator assumes that make's jobserver is being used.
+
    See also :vlopt:`-j`.
 
 .. option:: --cc
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index 688ad5bad..49ef7aeed 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -624,6 +624,10 @@ string V3Options::getenvMAKE() { return V3Os::getenvStr("MAKE", "gmake"); }
 string V3Options::getenvMAKE() { return V3Os::getenvStr("MAKE", "make"); }
 #endif
 
+string V3Options::getenvMAKEFLAGS() {  //
+    return V3Os::getenvStr("MAKEFLAGS", "");
+}
+
 string V3Options::getenvPERL() {  //
     return V3Os::getenvStr("PERL", "perl");
 }
diff --git a/src/V3Options.h b/src/V3Options.h
index 6fd2e8ac7..4d3a14280 100644
--- a/src/V3Options.h
+++ b/src/V3Options.h
@@ -660,6 +660,7 @@ public:
     // Also add to V3Options::showVersion()
     static string getenvBuiltins(const string& var);
     static string getenvMAKE();
+    static string getenvMAKEFLAGS();
     static string getenvPERL();
     static string getenvSYSTEMC();
     static string getenvSYSTEMC_ARCH();
diff --git a/src/Verilator.cpp b/src/Verilator.cpp
index 464e68e4e..aad4863cd 100644
--- a/src/Verilator.cpp
+++ b/src/Verilator.cpp
@@ -686,7 +686,10 @@ static string buildMakeCmd(const string& makefile, const string& target) {
     cmd << v3Global.opt.getenvMAKE();
     cmd << " -C " << v3Global.opt.makeDir();
     cmd << " -f " << makefile;
-    if (jobs > 0) cmd << " -j " << jobs;
+    // Unless using make's jobserver, do a -j
+    if (v3Global.opt.getenvMAKEFLAGS().find("-jobserver-auth") == string::npos) {
+        if (jobs > 0) cmd << " -j " << jobs;
+    }
     for (const string& flag : makeFlags) cmd << ' ' << flag;
     if (!target.empty()) cmd << ' ' << target;
 

From 0a3c90e51741f564aed466ac1a251f409911e882 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 11 Dec 2022 14:44:18 -0500
Subject: [PATCH 144/156] Fix forked processes compiled as slow/cold (#3766)

---
 src/V3Sched.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp
index 36dc28712..73dd6afff 100644
--- a/src/V3Sched.cpp
+++ b/src/V3Sched.cpp
@@ -237,6 +237,7 @@ void orderSequentially(AstCFunc* funcp, const LogicByScope& lbs) {
                     bodyp->unlinkFrBackWithNext();
                     // If the process is suspendable, we need a separate function (a coroutine)
                     if (procp->isSuspendable()) {
+                        funcp->slow(false);
                         subFuncp = createNewSubFuncp(scopep);
                         subFuncp->name(subFuncp->name() + "__" + cvtToStr(scopep->user2Inc()));
                         subFuncp->rtnType("VlCoroutine");

From 01b521a0ea58df407599b4ce7518a009f2f7134f Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 11 Dec 2022 15:10:23 -0500
Subject: [PATCH 145/156] Commentary: Changes update

---
 Changes | 40 ++++++++++++++++++++++++++++++++++------
 1 file changed, 34 insertions(+), 6 deletions(-)

diff --git a/Changes b/Changes
index 493f37f2d..78a4bbf28 100644
--- a/Changes
+++ b/Changes
@@ -11,27 +11,55 @@ contributors that suggested a given feature are shown in []. Thanks!
 Verilator 5.003 devel
 ==========================
 
+**Major:**
+
+* Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd]
+* Add ENUMVALUE warning when value misused for enum (#726) (#3777) (#3783).
+* Deprecate --no-threads; use --threads 1 for single threaded (#3703). [Kamil Rakoczy, Antmicro Ltd]
+
 **Minor:**
 
-* Deprecate --no-threads; use --threads 1 for single threaded (#3703). [Kamil Rakoczy, Antmicro Ltd]
-* Support named properties (#3667). [Ryszard Rozak, Antmicro Ltd]
+* Support std::semaphore and typed std::mailbox (#3708). [Krzysztof Bieganski, Antmicro Ltd]
+* Support 'with' in unique, unique_index, min, max in queues (#3772). [Ryszard Rozak, Antmicro Ltd]
+* Support events in VCD/FST traces (#3759). [Yves Mathieu]
+* Support foreach loops on strings (#3760). [Ryszard Rozak, Antmicro Ltd]
+* Support member selects in with clauses (#3775). [Ryszard Rozak, Antmicro Ltd]
+* Support super.new calls (#3789). [Ryszard Rozak, Antmicro Ltd]
 * Support randcase.
 * Support pre_randomize and post_randomize.
 * Support $timeunit and $timeprecision.
 * Support assignment expressions.
-* Add ENUMVALUE warning when value misused for enum (#726) (#3777) (#3783).
-* Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Change ENDLABEL from warning into an error.
+* Internal AST improvements, also affect XML format (#3721). [Geza Lore]
 * Deprecate verilated_fst_sc.cpp and verilated_vcd_sc.cpp.
+* Disable stack size limit (#3706) (#3751). [Mariusz Glebocki]
+* Add error when use --exe with --lib-create (#3785). [Yinan Xu]
+* Fix jump handling in do while loops (#3731). [Ryszard Rozak, Antmicro Ltd]
+* Fix 'with' clause handling in functions (#3739). [Ryszard Rozak, Antmicro Ltd]
+* Fix CONTEXT compile error on mingw64 (#3741). [William D. Jones]
+* Fix MSVC compiler errors (#3742) (#3746). [Kritik Bhimani]
 * Fix CASEINCOMPLETE when covers all enum values (#3745) (#3782). [Guy-Armand Kamendje]
 * Fix return type of $countbits functions to int (#3725). [Ryszard Rozak, Antmicro Ltd]
+* Fix timing control in while-break loops (#3733) (#3769). [Ryszard Rozak, Antmicro Ltd]
+* Fix return in constructors (#3734). [Ryszard Rozak, Antmicro Ltd]
 * Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
 * Fix tracing parameters overridden with -G (#3723). [Iztok Jeras]
+* Fix folding of LogAnd with non-bool operands (#3726). [Geza Lore]
+* Fix Dfg optimization issues (#3740) (#3771). [Geza Lore]
+* Fix pre/postincrement operations (#3744) (#3756). [Ryszard Rozak, Antmicro Ltd]
+* Fix cross-compile for MingW, Arm and RiscV (#3752). [Miodrag Milanović]
+* Fix $unit as base package for other packages (#3755). [Ryszard Rozak, Antmicro Ltd]
 * Fix make jobserver with submakes (#3758). [Gus Smith]
+* Fix to escape VERILATOR_ROOT file paths (#3764) (#3765). [Jiacheng Qian]
+* Fix empty string literals converting to string types (#3774). [miree]
+* Fix to remove $date from .vcd files (#3779). [Larry Doolittle]
+* Fix missing user objects in --lib-create mode (#3780) (#3784). [Yinan Xu]
+* Fix non-blocking assignments in forks (#3781) (#3800). [Krzysztof Bieganski, Antmicro Ltd]
+* Fix forks without any delayed statements (#3792) (#3801). [Krzysztof Bieganski, Antmicro Ltd]
+* Fix internal error in bit op tree optimization (#3793). [Yutetsu TAKATSUKASA]
+* Fix lint_off EOFNEWLINE in .vlt files (#3796). [Andrew Nolte]
 * Fix wait 0.
 * Fix comparing ranged slices of unpacked arrays.
-* Fix empty string literals converting to string types (#3774). [miree]
-* Fix lint_off EOFNEWLINE in .vlt files (#3796). [Andrew Nolte]
 
 
 Verilator 5.002 2022-10-29

From 609bfa46e8189eca595931ff9a420c4e6753d77c Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 11 Dec 2022 21:10:12 -0500
Subject: [PATCH 146/156] Fix ENUMVALUE on parameter, again (#3777).

---
 src/V3Width.cpp                     |  2 +-
 test_regress/t/t_cast_param_type.pl |  8 ++++++--
 test_regress/t/t_cast_param_type.v  | 13 +++++++++++++
 3 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index aa1de5970..a420d2a04 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -1979,7 +1979,7 @@ private:
     }
     void visit(AstCastWrap* nodep) override {
         // Inserted by V3Width only so we know has been resolved
-        UASSERT_OBJ(nodep->didWidth(), nodep, "CastWrap should have width'ed earlier");
+        userIterateAndNext(nodep->lhsp(), WidthVP{nodep->dtypep(), BOTH}.p());
     }
     void castSized(AstNode* nodep, AstNode* underp, int width) {
         const AstBasicDType* underDtp = VN_CAST(underp->dtypep(), BasicDType);
diff --git a/test_regress/t/t_cast_param_type.pl b/test_regress/t/t_cast_param_type.pl
index 09b2ce4eb..b46d46042 100755
--- a/test_regress/t/t_cast_param_type.pl
+++ b/test_regress/t/t_cast_param_type.pl
@@ -8,9 +8,13 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
 
-scenarios(linter => 1);
+scenarios(simulator => 1);
 
-lint(
+compile(
+    );
+
+execute(
+    check_finished => 1,
     );
 
 ok(1);
diff --git a/test_regress/t/t_cast_param_type.v b/test_regress/t/t_cast_param_type.v
index 81b24c854..18a50fe0d 100644
--- a/test_regress/t/t_cast_param_type.v
+++ b/test_regress/t/t_cast_param_type.v
@@ -16,8 +16,21 @@ module SubB
    ();
 endmodule
 
+function automatic letters_t lfunc(int a);
+    return letters_t'(1);
+endfunction
+
 module t ();
+   localparam FMT = lfunc(1);
+
    SubA suba0 ();
    SubA #(.LETTER(letters_t'(1))) suba1 ();
    SubB #(.LETTER(letters_t'(1))) subb2 ();
+
+   initial begin
+      if (lfunc(1) != B) $stop;
+      if (FMT != B) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
 endmodule

From 972a11537cb50cb56ff0cbe6e58603f65be5cbb3 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 11 Dec 2022 21:58:02 -0500
Subject: [PATCH 147/156] Internals: Fix lint-py warnings

---
 bin/verilator_ccache_report       |  2 +-
 bin/verilator_difftree            |  8 ++++----
 bin/verilator_gantt               |  6 +++---
 bin/verilator_profcfunc           | 27 +++++++++++++--------------
 docs/bin/vl_sphinx_extract        |  6 +++---
 docs/bin/vl_sphinx_fix            |  6 +++---
 docs/guide/conf.py                |  2 +-
 examples/xml_py/vl_file_copy      | 28 +++++++++++++---------------
 examples/xml_py/vl_hier_graph     | 30 ++++++++++++++----------------
 nodist/code_coverage              | 30 ++++++++++++++++--------------
 nodist/dot_importer               |  6 +++---
 nodist/fuzzer/generate_dictionary |  4 ++--
 nodist/install_test               |  2 +-
 src/astgen                        | 14 +++++++-------
 src/bisonpre                      | 12 ++++++------
 src/cppcheck_filtered             |  6 +++---
 src/vlcovgen                      |  8 ++++----
 test_regress/t/t_pipe_filter.pf   |  2 +-
 18 files changed, 98 insertions(+), 101 deletions(-)

diff --git a/bin/verilator_ccache_report b/bin/verilator_ccache_report
index f895db4ae..bbb69b9af 100755
--- a/bin/verilator_ccache_report
+++ b/bin/verilator_ccache_report
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0115,C0116,C0123,C0301,R0902,R0913,R0914,R0912,R0915,W0621
+# pylint: disable=C0103,C0114,C0115,C0116,C0123,C0209,C0301,R0902,R0913,R0914,R0912,R0915,W0621
 ######################################################################
 
 import argparse
diff --git a/bin/verilator_difftree b/bin/verilator_difftree
index d7c65a28e..2bede0e8d 100755
--- a/bin/verilator_difftree
+++ b/bin/verilator_difftree
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0116
+# pylint: disable=C0103,C0114,C0116,C0209
 ######################################################################
 
 import argparse
@@ -73,7 +73,7 @@ def diff_file(a, b):
 
 def version_from(filename):
     # Return dump format
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
         lineno = 0
         for line in fh:
             if lineno > 10:
@@ -86,8 +86,8 @@ def version_from(filename):
 
 def filterf(fn1, fn2):
     # Remove hex numbers before diffing
-    with open(fn1) as fh1:
-        with open(fn2, "w") as fh2:
+    with open(fn1, "r", encoding="utf8") as fh1:
+        with open(fn2, "w", encoding="utf8") as fh2:
             for line in fh1:
                 if re.search(r' This=', line):
                     continue
diff --git a/bin/verilator_gantt b/bin/verilator_gantt
index 03a7a16af..cfab96456 100755
--- a/bin/verilator_gantt
+++ b/bin/verilator_gantt
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0116,C0301,R0914,R0912,R0915,W0511,eval-used
+# pylint: disable=C0103,C0114,C0116,C0209,C0301,R0914,R0912,R0915,W0511,eval-used
 ######################################################################
 
 import argparse
@@ -29,7 +29,7 @@ def process(filename):
 
 
 def read_data(filename):
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
         re_thread = re.compile(r'^VLPROFTHREAD (\d+)$')
         re_record = re.compile(r'^VLPROFEXEC (\S+) (\d+)(.*)$')
         re_payload_mtaskBegin = re.compile(
@@ -318,7 +318,7 @@ def report_cpus():
 
 def write_vcd(filename):
     print("Writing %s" % filename)
-    with open(filename, "w") as fh:
+    with open(filename, "w", encoding="utf8") as fh:
         vcd = {
             'values':
             collections.defaultdict(lambda: {}),  # {<time>}{<code>} = value
diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc
index 4f6b82442..abf1c06b8 100755
--- a/bin/verilator_profcfunc
+++ b/bin/verilator_profcfunc
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0116,R0914,R0912,R0915,eval-used
+# pylint: disable=C0103,C0114,C0116,C0209,R0914,R0912,R0915,eval-used
 ######################################################################
 
 import argparse
@@ -13,7 +13,7 @@ import re
 def profcfunc(filename):
     funcs = {}
 
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
 
         for line in fh:
             #                  %time      cumesec   selfsec     calls     {stuff}   name
@@ -67,16 +67,15 @@ def profcfunc(filename):
     groups['design'] = collections.defaultdict(lambda: 0)
     groups['module'] = collections.defaultdict(lambda: 0)
 
-    for func in funcs:
-        pct = funcs[func]['pct']
+    for func, func_item in funcs.items():
+        pct = func_item['pct']
         vfunc = func
 
         funcarg = re.sub(r'^.*\(', '', func)
 
         design = None
-        for vde in verilated_mods:
-            if verilated_mods[vde].match(func) or verilated_mods[vde].match(
-                    funcarg):
+        for vde, vde_item in verilated_mods.items():
+            if vde_item.match(func) or vde_item.match(funcarg):
                 design = vde
                 break
 
@@ -114,12 +113,12 @@ def profcfunc(filename):
             groups['module']['C++'] += pct
 
         if vfunc not in vfuncs:
-            vfuncs[vfunc] = funcs[func]
+            vfuncs[vfunc] = func_item
             vfuncs[vfunc]['design'] = vdesign
         else:
-            vfuncs[vfunc]['pct'] += funcs[func]['pct']
-            vfuncs[vfunc]['calls'] += funcs[func]['calls']
-            vfuncs[vfunc]['sec'] += funcs[func]['sec']
+            vfuncs[vfunc]['pct'] += func_item['pct']
+            vfuncs[vfunc]['calls'] += func_item['calls']
+            vfuncs[vfunc]['sec'] += func_item['sec']
 
     for ftype in ['type', 'design', 'module']:
         missing = 100
@@ -136,9 +135,9 @@ def profcfunc(filename):
         print()
 
     design_width = 1
-    for func in vfuncs:
-        if design_width < len(vfuncs[func]['design']):
-            design_width = len(vfuncs[func]['design'])
+    for func, func_item in vfuncs.items():
+        if design_width < len(func_item['design']):
+            design_width = len(func_item['design'])
 
     print("Verilog code profile:")
     print("   These are split into three categories:")
diff --git a/docs/bin/vl_sphinx_extract b/docs/bin/vl_sphinx_extract
index 97d5b1ec5..c829482bf 100755
--- a/docs/bin/vl_sphinx_extract
+++ b/docs/bin/vl_sphinx_extract
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0112,C0114,C0115,C0116,C0301,R0201,R0903
+# pylint: disable=C0112,C0114,C0115,C0116,C0209,C0301,R0201,R0903
 # -*- Python -*- See copyright, etc below
 ######################################################################
 
@@ -14,7 +14,7 @@ class VlSphinxExtract:
     SkipBasenames = {}
 
     def process(self, filename):
-        with open(filename) as fhr:
+        with open(filename, "r", encoding="utf8") as fhr:
             fhw = None
             for line in fhr:
                 # =for VL_SPHINX_EXTRACT "file_to_write_to"
@@ -22,7 +22,7 @@ class VlSphinxExtract:
                 if match:
                     outname = match.group(1)
                     print("Writing %s" % outname)
-                    fhw = open(outname, "w")
+                    fhw = open(outname, "w", encoding="utf8")  # pylint: disable=consider-using-with
                     fhw.write(
                         ".. comment: generated by vl_sphinx_extract from " +
                         filename + "\n")
diff --git a/docs/bin/vl_sphinx_fix b/docs/bin/vl_sphinx_fix
index 3c18cb1c7..cc03c3b83 100755
--- a/docs/bin/vl_sphinx_fix
+++ b/docs/bin/vl_sphinx_fix
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0112,C0114,C0115,C0116,C0301,R0903
+# pylint: disable=C0112,C0114,C0115,C0116,C0209,C0301,R0903
 # -*- Python -*- See copyright, etc below
 ######################################################################
 
@@ -27,7 +27,7 @@ class VlSphinxFix:
 
     def _edit(self, filename):
         is_html = re.search(r'\.(html)$', filename)
-        with open(filename) as fhr:
+        with open(filename, "r", encoding="utf8") as fhr:
             origfile = fhr.read()
             wholefile = origfile
             # Option doesn't like spaces, so we use
@@ -43,7 +43,7 @@ class VlSphinxFix:
                 if self.debug:
                     print("Edit %s" % filename)
                 tempname = filename + ".tmp"
-                with open(tempname, "w") as fhw:
+                with open(tempname, "w", encoding="utf8") as fhw:
                     fhw.write(wholefile)
                 os.rename(tempname, filename)
 
diff --git a/docs/guide/conf.py b/docs/guide/conf.py
index fb9c66d1a..a10484a35 100644
--- a/docs/guide/conf.py
+++ b/docs/guide/conf.py
@@ -21,7 +21,7 @@ import sphinx_rtd_theme  # pylint: disable=wrong-import-position,
 
 def get_vlt_version():
     filename = "../../Makefile"
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
         for line in fh:
             match = re.search(r"PACKAGE_VERSION_NUMBER *= *([a-z0-9.]+)", line)
             if match:
diff --git a/examples/xml_py/vl_file_copy b/examples/xml_py/vl_file_copy
index 1ff96328e..b221eba6a 100755
--- a/examples/xml_py/vl_file_copy
+++ b/examples/xml_py/vl_file_copy
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 # -*- Python -*- See copyright, etc below
-# pylint: disable=C0114,C0115,R0903
+# pylint: disable=C0114,C0115,C0209,R0903
 ######################################################################
 
 import argparse
@@ -20,24 +20,22 @@ class VlFileCopy:
     def __init__(
             self,
             verilator_args,  # presently all verilator options are passed-thru
-            # ideally this script would check against options mentioned in help
-        debug=0,
+            debug=0,
             output_dir='copied'):  # directory name we output file uses
 
         self.debug = debug
 
-        xml_temp = tempfile.NamedTemporaryFile()
-
-        vargs = [
-            '--xml-output',
-            xml_temp.name,
-            '--bbox-sys',  # Parse some stuff can't translate
-            '--bbox-unsup',
-            '--prefix vlxml'
-        ]  # So we know name of .xml output
-        vargs += verilator_args
-        self.run_verilator(vargs)
-        self.tree = ET.parse(xml_temp.name)
+        with tempfile.NamedTemporaryFile() as xml_temp:
+            vargs = [
+                '--xml-output',
+                xml_temp.name,
+                '--bbox-sys',  # Parse some stuff can't translate
+                '--bbox-unsup',
+                '--prefix vlxml'
+            ]  # So we know name of .xml output
+            vargs += verilator_args
+            self.run_verilator(vargs)
+            self.tree = ET.parse(xml_temp.name)
 
         os.makedirs(output_dir, 0o777, True)
 
diff --git a/examples/xml_py/vl_hier_graph b/examples/xml_py/vl_hier_graph
index 566250226..a2e82fabd 100755
--- a/examples/xml_py/vl_hier_graph
+++ b/examples/xml_py/vl_hier_graph
@@ -1,6 +1,6 @@
 #!/usr/bin/env python3
 # -*- Python -*- See copyright, etc below
-# pylint: disable=C0103,C0114,C0115,C0115,C0116,R0914
+# pylint: disable=C0103,C0114,C0115,C0115,C0116,C0209,R0914
 ######################################################################
 
 import argparse
@@ -18,27 +18,25 @@ class VlHierGraph:
     def __init__(
             self,
             verilator_args,  # presently all verilator options are passed-thru
-            # ideally this script would check against options mentioned in help
-        debug=0,
+            debug=0,
             output_filename='graph.dot'):  # output filename
         self.debug = debug
         self.next_vertex_number = 0
         self.name_to_number = {}
 
-        xml_temp = tempfile.NamedTemporaryFile()
+        with tempfile.NamedTemporaryFile() as xml_temp:
+            vargs = [
+                '--xml-output',
+                xml_temp.name,
+                '--bbox-sys',  # Parse some stuff can't translate
+                '--bbox-unsup',
+                '--prefix vlxml'
+            ]  # So we know name of .xml output
+            vargs += verilator_args
+            self.run_verilator(vargs)
+            self.tree = ET.parse(xml_temp.name)
 
-        vargs = [
-            '--xml-output',
-            xml_temp.name,
-            '--bbox-sys',  # Parse some stuff can't translate
-            '--bbox-unsup',
-            '--prefix vlxml'
-        ]  # So we know name of .xml output
-        vargs += verilator_args
-        self.run_verilator(vargs)
-        self.tree = ET.parse(xml_temp.name)
-
-        with open(output_filename, "w") as fh:
+        with open(output_filename, "w", encoding="utf8") as fh:
             # For more serious purposes, use the python graphviz package instead
             fh.write("digraph {\n")
             fh.write("  dpi=300;\n")
diff --git a/nodist/code_coverage b/nodist/code_coverage
index 286397e91..5b6bcc53f 100755
--- a/nodist/code_coverage
+++ b/nodist/code_coverage
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0115,C0116,R0912,R0914,R0915,W0125,W0621,exec-used
+# pylint: disable=C0103,C0114,C0115,C0116,C0209,R0912,R0914,R0915,W0125,W0621,exec-used
 ######################################################################
 
 import argparse
@@ -26,7 +26,7 @@ if 'VERILATOR_ROOT' not in os.environ:
 def test():
     if not os.path.exists("nodist/code_coverage.dat"):
         sys.exit("%Error: Run code_coverage from the top of the verilator kit")
-    exec(open("./nodist/code_coverage.dat").read())
+    exec(open("./nodist/code_coverage.dat", "r", encoding="utf8").read())  # pylint: disable=consider-using-with
 
     if Args.stage_enabled[0]:
         ci_fold_start("distclean")
@@ -78,10 +78,11 @@ def test():
         os.makedirs(cc_dir, exist_ok=True)
         os.makedirs(cc_dir + "/info", exist_ok=True)
 
-        sp = subprocess.Popen("find . -print | grep .gcda",
+        with subprocess.Popen("find . -print | grep .gcda",
                               shell=True,
-                              stdout=subprocess.PIPE)
-        datout = sp.stdout.read()
+                              stdout=subprocess.PIPE) as sp:
+            datout = sp.stdout.read()
+
         dats = {}
         for dat in datout.splitlines():
             dat = dat.decode('utf-8')
@@ -97,10 +98,11 @@ def test():
                     del dats[dat]
                     break
 
-        sp = subprocess.Popen("find . -print | grep .gcno",
+        with subprocess.Popen("find . -print | grep .gcno",
                               shell=True,
-                              stdout=subprocess.PIPE)
-        datout = sp.stdout.read()
+                              stdout=subprocess.PIPE) as sp:
+            datout = sp.stdout.read()
+
         gcnos = {}
         for gcno in datout.splitlines():
             gcno = gcno.decode('utf-8')
@@ -204,8 +206,8 @@ def clone_sources(cc_dir):
             outfile = cc_dir + "/" + infile
             outpath = re.sub(r'/[^/]*$', '', outfile, count=1)
             os.makedirs(outpath, exist_ok=True)
-            with open(infile) as fh:
-                with open(outfile, "w") as ofh:
+            with open(infile, "r", encoding="utf8") as fh:
+                with open(outfile, "w", encoding="utf8") as ofh:
                     lineno = 0
                     for line in fh:
                         lineno += 1
@@ -249,7 +251,7 @@ def clone_sources(cc_dir):
 
 def cleanup_abs_paths_info(cc_dir, infile, outfile):
     lines = []
-    with open(infile) as fh:
+    with open(infile, "r", encoding="utf8") as fh:
         for line in fh:
             if re.search(r'^SF:', line):
                 line = re.sub(os.environ['VERILATOR_ROOT'] + '/',
@@ -261,7 +263,7 @@ def cleanup_abs_paths_info(cc_dir, infile, outfile):
                 # print("Remaining SF: "+line)
             lines.append(line)
 
-    with open(outfile, "w") as ofh:
+    with open(outfile, "w", encoding="utf8") as ofh:
         for line in lines:
             ofh.write(line)
 
@@ -270,14 +272,14 @@ def cleanup_abs_paths_json(cc_dir, infile, outfile):
     # Handcrafted cleanup, alternative would be to deserialize/serialize JSON,
     # but this is much faster
     lines = []
-    with open(infile) as fh:
+    with open(infile, "r", encoding="utf8") as fh:
         for line in fh:
             line = re.sub('"' + os.environ['VERILATOR_ROOT'] + '/', '"', line)
             line = re.sub('"' + cc_dir + '/', '"', line)
             line = re.sub(r'obj_dbg/verilog.y$', 'verilog.y', line)
             lines.append(line)
 
-    with open(outfile, "w") as ofh:
+    with open(outfile, "w", encoding="utf8") as ofh:
         for line in lines:
             ofh.write(line)
 
diff --git a/nodist/dot_importer b/nodist/dot_importer
index 29fe37fc2..cedf26696 100755
--- a/nodist/dot_importer
+++ b/nodist/dot_importer
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0115,C0116,C0301
+# pylint: disable=C0103,C0114,C0115,C0116,C0209,C0301
 ######################################################################
 
 import argparse
@@ -15,7 +15,7 @@ Edges = []
 
 
 def dotread(filename):
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
         header = True
         vnum = 0
 
@@ -61,7 +61,7 @@ def dotread(filename):
 
 
 def cwrite(filename):
-    with open(filename, "w") as fh:
+    with open(filename, "w", encoding="utf8") as fh:
         fh.write("void V3GraphTestImport::dotImport() {\n")
         fh.write("    auto* gp = &m_graph;\n")
         for ver in sorted(Vertexes, key=lambda ver: ver['num']):
diff --git a/nodist/fuzzer/generate_dictionary b/nodist/fuzzer/generate_dictionary
index 546e48fcb..c03c899ed 100755
--- a/nodist/fuzzer/generate_dictionary
+++ b/nodist/fuzzer/generate_dictionary
@@ -45,8 +45,8 @@ def print_lines(a):
 
 def write_file(filename, contents):
     # str->str->void
-    f = open(filename, 'w')
-    f.write(contents)
+    with open(filename, "w", encoding="utf8") as fh:
+        fh.write(contents)
 
 
 def parse_line(s):
diff --git a/nodist/install_test b/nodist/install_test
index 7dcc2853a..0b1c66052 100755
--- a/nodist/install_test
+++ b/nodist/install_test
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0115,C0116,R0801,R0915
+# pylint: disable=C0103,C0114,C0115,C0116,C0209,R0801,R0915
 ######################################################################
 
 import argparse
diff --git a/src/astgen b/src/astgen
index f79ddc6ab..fe85a30cc 100755
--- a/src/astgen
+++ b/src/astgen
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0115,C0116,C0123,C0301,R0902,R0913,R0914,R0912,R0915,W0621
+# pylint: disable=C0103,C0114,C0115,C0116,C0123,C0209,C0301,C0302,R0902,R0913,R0914,R0912,R0915,W0621
 ######################################################################
 
 import argparse
@@ -80,7 +80,7 @@ class Node:
         # Sort sub-classes and convert to tuple, which marks completion
         self._subClasses = tuple(
             sorted(self._subClasses,
-                   key=lambda _: (bool(_._subClasses), _.name)))
+                   key=lambda _: (bool(_._subClasses), _.name)))  # pylint: disable=protected-access
 
         self._ordIdx = ordIdx
         ordIdx = ordIdx + 1
@@ -220,7 +220,7 @@ class Cpt:
         didln = False
 
         # Read the file and parse into list of functions that generate output
-        with open(self.in_filename) as fhi:
+        with open(self.in_filename, "r", encoding="utf8") as fhi:
             for line in fhi:
                 ln += 1
                 if not didln:
@@ -570,7 +570,7 @@ def read_types(filename, Nodes, prefix):
                     p=prefix, n=node.name))
         hasAstgenMembers = False
 
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
         for (lineno, line) in enumerate(fh, start=1):
             line = line.strip()
             if not line:
@@ -715,7 +715,7 @@ def check_types(sortedTypes, prefix, abstractPrefix):
 
 
 def read_stages(filename):
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
         n = 100
         for line in fh:
             line = re.sub(r'//.*$', '', line)
@@ -731,7 +731,7 @@ def read_stages(filename):
 
 def read_refs(filename):
     basename = re.sub(r'.*/', '', filename)
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
         for line in fh:
             line = re.sub(r'//.*$', '', line)
             for match in re.finditer(r'\bnew\s*(Ast[A-Za-z0-9_]+)', line):
@@ -753,7 +753,7 @@ def read_refs(filename):
 
 
 def open_file(filename):
-    fh = open(filename, "w")
+    fh = open(filename, "w", encoding="utf8")  # pylint: disable=consider-using-with
     if re.search(r'\.txt$', filename):
         fh.write("// Generated by astgen\n")
     else:
diff --git a/src/bisonpre b/src/bisonpre
index 48f1761ff..664684c06 100755
--- a/src/bisonpre
+++ b/src/bisonpre
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0115,C0116,R0912,R0914,R0915,R1702,W0125
+# pylint: disable=C0103,C0114,C0115,C0116,C0209,R0912,R0914,R0915,R1702,W0125
 ######################################################################
 
 import argparse
@@ -17,7 +17,7 @@ def process():
 
     bison_version_check()
     supports_report = Bison_Version >= 2.3
-    supports_counter_examples = Bison_Version >= 3.8
+    # supports_counter_examples = Bison_Version >= 3.8
 
     clean_input(Args.input, tmp_prefix() + ".y")
 
@@ -88,10 +88,10 @@ def unlink_outputs():
 
 
 def bison_version_check():
-    sp = subprocess.Popen(Args.yacc + " --version",
+    with subprocess.Popen(Args.yacc + " --version",
                           shell=True,
-                          stdout=subprocess.PIPE)
-    out = str(sp.stdout.read())
+                          stdout=subprocess.PIPE) as sp:
+        out = str(sp.stdout.read())
     match = re.search(r'([0-9]+\.[0-9]+)', out)
     if match:
         v = float(match.group(1))
@@ -405,7 +405,7 @@ def clean_input(filename, outname):
             else:
                 lines.append(line)
 
-    with open(outname, "w") as fh:
+    with open(outname, "w", encoding="utf8") as fh:
         for line in lines:
             fh.write(line)
 
diff --git a/src/cppcheck_filtered b/src/cppcheck_filtered
index ce991abe3..78156e1e9 100755
--- a/src/cppcheck_filtered
+++ b/src/cppcheck_filtered
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0115,C0116,R0911,R0912,R0915,W0621
+# pylint: disable=C0103,C0114,C0115,C0116,C0209,R0911,R0912,R0915,W0621
 ######################################################################
 
 import argparse
@@ -155,11 +155,11 @@ def _suppress(filename, linenum, eid):
               file=sys.stderr)
         return False
 
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
         lineno = 0
         for line in fh:
             lineno += 1
-            if ((lineno + 1) == linenum):
+            if (lineno + 1) == linenum:
                 match = re.search(
                     r'(cppcheck|cppcheck-has-bug|cppverilator)-suppress((\s+\S+)+)',
                     line)
diff --git a/src/vlcovgen b/src/vlcovgen
index 1c749e98c..e440dca43 100755
--- a/src/vlcovgen
+++ b/src/vlcovgen
@@ -1,5 +1,5 @@
 #!/usr/bin/env python3
-# pylint: disable=C0103,C0114,C0116,eval-used
+# pylint: disable=C0103,C0114,C0116,C0209,eval-used
 ######################################################################
 
 import argparse
@@ -13,7 +13,7 @@ Items = []
 
 
 def read_keys(filename):
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
         for line in fh:
             line = re.sub(r'\/\/.*$', '', line)
             if re.match(r'^\s*$', line):
@@ -45,7 +45,7 @@ def write_keys(filename):
     orig = []
     out = []
 
-    with open(filename) as fh:
+    with open(filename, "r", encoding="utf8") as fh:
         deleting = False
         for line in fh:
             orig.append(line)
@@ -70,7 +70,7 @@ def write_keys(filename):
 
     ok = "".join(out) == "".join(orig)
     if not ok:
-        with open(filename, "w") as fhw:
+        with open(filename, "w", encoding="utf8") as fhw:
             fhw.write("".join(out))
 
 
diff --git a/test_regress/t/t_pipe_filter.pf b/test_regress/t/t_pipe_filter.pf
index 22af10c97..fe52740c7 100755
--- a/test_regress/t/t_pipe_filter.pf
+++ b/test_regress/t/t_pipe_filter.pf
@@ -27,7 +27,7 @@ for cmd in sys.stdin:
 
         wholefile = ""
         # It's faster to slurp the whole file then scan (if needed)
-        with open(filename) as fh:
+        with open(filename, "r", encoding="utf8") as fh:
             wholefile = fh.read()
 
         if 'example_lint' in wholefile:  # else short circuit

From 61d6546400249ee4aae2fb8c55f979ea9d5288b0 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 11 Dec 2022 23:03:27 -0500
Subject: [PATCH 148/156] Internals: Mark more VL_MT_SAFE functions. No
 functional change

---
 include/verilated.cpp         | 10 ++--
 include/verilated.h           |  3 +-
 include/verilated_cov.h       |  8 +--
 include/verilated_funcs.h     | 93 ++++++++++++++++++-----------------
 include/verilated_trace_imp.h |  4 +-
 include/verilated_vpi.cpp     |  3 +-
 6 files changed, 63 insertions(+), 58 deletions(-)

diff --git a/include/verilated.cpp b/include/verilated.cpp
index eff55246c..679e948e1 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -595,7 +595,7 @@ double VL_ITOR_D_W(int lbits, const WDataInP lwp) VL_PURE {
     const double d = (hi + mid + lo) * std::exp2(VL_EDATASIZE * (ms_word - 2));
     return d;
 }
-double VL_ISTOR_D_W(int lbits, const WDataInP lwp) VL_PURE {
+double VL_ISTOR_D_W(int lbits, const WDataInP lwp) VL_MT_SAFE {
     if (!VL_SIGN_W(lbits, lwp)) return VL_ITOR_D_W(lbits, lwp);
     uint32_t pos[VL_MULS_MAX_WORDS + 1];  // Fixed size, as MSVC++ doesn't allow [words] here
     VL_NEGATE_W(VL_WORDS_I(lbits), pos, lwp);
@@ -1796,12 +1796,12 @@ std::string VL_TO_STRING_W(int words, const WDataInP obj) {
     return VL_SFORMATF_NX("'h%0x", words * VL_EDATASIZE, obj);
 }
 
-std::string VL_TOLOWER_NN(const std::string& ld) VL_MT_SAFE {
+std::string VL_TOLOWER_NN(const std::string& ld) VL_PURE {
     std::string out = ld;
     for (auto& cr : out) cr = std::tolower(cr);
     return out;
 }
-std::string VL_TOUPPER_NN(const std::string& ld) VL_MT_SAFE {
+std::string VL_TOUPPER_NN(const std::string& ld) VL_PURE {
     std::string out = ld;
     for (auto& cr : out) cr = std::toupper(cr);
     return out;
@@ -2774,12 +2774,12 @@ static struct {
     VoidPCbList s_exitCbs VL_GUARDED_BY(s_exitMutex);
 } VlCbStatic;
 
-static void addCb(Verilated::VoidPCb cb, void* datap, VoidPCbList& cbs) {
+static void addCb(Verilated::VoidPCb cb, void* datap, VoidPCbList& cbs) VL_MT_UNSAFE {
     std::pair<Verilated::VoidPCb, void*> pair(cb, datap);
     cbs.remove(pair);  // Just in case it's a duplicate
     cbs.push_back(pair);
 }
-static void removeCb(Verilated::VoidPCb cb, void* datap, VoidPCbList& cbs) {
+static void removeCb(Verilated::VoidPCb cb, void* datap, VoidPCbList& cbs) VL_MT_UNSAFE {
     std::pair<Verilated::VoidPCb, void*> pair(cb, datap);
     cbs.remove(pair);
 }
diff --git a/include/verilated.h b/include/verilated.h
index d1bc8c8f2..9186ed69c 100644
--- a/include/verilated.h
+++ b/include/verilated.h
@@ -856,7 +856,8 @@ public:
     // METHODS - INTERNAL USE ONLY (but public due to what uses it)
     // Internal: Create a new module name by concatenating two strings
     // Returns pointer to thread-local static data (overwritten on next call)
-    static const char* catName(const char* n1, const char* n2, const char* delimiter = ".");
+    static const char* catName(const char* n1, const char* n2,
+                               const char* delimiter = ".") VL_MT_SAFE;
 
     // Internal: Throw signal assertion
     static void nullPointerError(const char* filename, int linenum) VL_ATTR_NORETURN VL_MT_SAFE;
diff --git a/include/verilated_cov.h b/include/verilated_cov.h
index bd92e064c..f3bde5eb4 100644
--- a/include/verilated_cov.h
+++ b/include/verilated_cov.h
@@ -128,15 +128,15 @@ public:
 #define K(n) const char* key##n
 #define A(n) const char *key##n, const char *valp##n  // Argument list
 #define D(n) const char *key##n = nullptr, const char *valp##n = nullptr  // Argument list
-    void _insertp(D(0), D(1), D(2), D(3), D(4), D(5), D(6), D(7), D(8), D(9));
+    void _insertp(D(0), D(1), D(2), D(3), D(4), D(5), D(6), D(7), D(8), D(9)) VL_MT_SAFE;
     void _insertp(A(0), A(1), A(2), A(3), A(4), A(5), A(6), A(7), A(8), A(9), A(10), D(11), D(12),
-                  D(13), D(14), D(15), D(16), D(17), D(18), D(19));
+                  D(13), D(14), D(15), D(16), D(17), D(18), D(19)) VL_MT_SAFE;
     void _insertp(A(0), A(1), A(2), A(3), A(4), A(5), A(6), A(7), A(8), A(9), A(10), A(11), A(12),
                   A(13), A(14), A(15), A(16), A(17), A(18), A(19), A(20), D(21), D(22), D(23),
-                  D(24), D(25), D(26), D(27), D(28), D(29));
+                  D(24), D(25), D(26), D(27), D(28), D(29)) VL_MT_SAFE;
     // Backward compatibility for Verilator
     void _insertp(A(0), A(1), K(2), int val2, K(3), int val3, K(4), const std::string& val4, A(5),
-                  A(6), A(7));
+                  A(6), A(7)) VL_MT_SAFE;
 
 #undef K
 #undef A
diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h
index fe6e98574..b8d30a793 100644
--- a/include/verilated_funcs.h
+++ b/include/verilated_funcs.h
@@ -37,24 +37,26 @@
 /// User code may wish to replace this function, to do so, define VL_USER_FINISH.
 /// This code does not have to be thread safe.
 /// Verilator internal code must call VL_FINISH_MT instead, which eventually calls this.
-extern void vl_finish(const char* filename, int linenum, const char* hier);
+extern void vl_finish(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE;
 
 /// Routine to call for $stop and non-fatal error
 /// User code may wish to replace this function, to do so, define VL_USER_STOP.
 /// This code does not have to be thread safe.
 /// Verilator internal code must call VL_FINISH_MT instead, which eventually calls this.
-extern void vl_stop(const char* filename, int linenum, const char* hier);
+extern void vl_stop(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE;
 
 /// Routine to call for fatal messages
 /// User code may wish to replace this function, to do so, define VL_USER_FATAL.
 /// This code does not have to be thread safe.
 /// Verilator internal code must call VL_FINISH_MT instead, which eventually calls this.
-extern void vl_fatal(const char* filename, int linenum, const char* hier, const char* msg);
+extern void vl_fatal(const char* filename, int linenum, const char* hier,
+                     const char* msg) VL_MT_UNSAFE;
 
 /// Routine to call for warning messages
 /// User code may wish to replace this function, to do so, define VL_USER_WARN.
 /// This code does not have to be thread safe.
-extern void vl_warn(const char* filename, int linenum, const char* hier, const char* msg);
+extern void vl_warn(const char* filename, int linenum, const char* hier,
+                    const char* msg) VL_MT_UNSAFE;
 
 //=========================================================================
 // Extern functions -- Slow path
@@ -82,7 +84,7 @@ extern void VL_DBG_MSGF(const char* formatp, ...) VL_ATTR_PRINTF(1) VL_MT_SAFE;
 // EMIT_RULE: VL_RANDOM:  oclean=dirty
 inline IData VL_RANDOM_I() VL_MT_SAFE { return vl_rand64(); }
 inline QData VL_RANDOM_Q() VL_MT_SAFE { return vl_rand64(); }
-extern WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp);
+extern WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp) VL_MT_SAFE;
 extern IData VL_RANDOM_SEEDED_II(IData& seedr) VL_MT_SAFE;
 extern IData VL_URANDOM_SEEDED_II(IData seed) VL_MT_SAFE;
 inline IData VL_URANDOM_RANGE_I(IData hi, IData lo) {
@@ -100,52 +102,52 @@ inline IData VL_URANDOM_RANGE_I(IData hi, IData lo) {
 
 // These are init time only, so slow is fine
 /// Random reset a signal of given width
-extern IData VL_RAND_RESET_I(int obits);
+extern IData VL_RAND_RESET_I(int obits) VL_MT_SAFE;
 /// Random reset a signal of given width
-extern QData VL_RAND_RESET_Q(int obits);
+extern QData VL_RAND_RESET_Q(int obits) VL_MT_SAFE;
 /// Random reset a signal of given width
-extern WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp);
+extern WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp) VL_MT_SAFE;
 /// Zero reset a signal (slow - else use VL_ZERO_W)
-extern WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp);
+extern WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp) VL_MT_SAFE;
 
 extern void VL_PRINTTIMESCALE(const char* namep, const char* timeunitp,
                               const VerilatedContext* contextp) VL_MT_SAFE;
 
 extern WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP const lwp, WDataInP const rwp,
-                              bool is_modulus);
+                              bool is_modulus) VL_MT_SAFE;
 
-extern IData VL_FGETS_IXI(int obits, void* destp, IData fpi);
+extern IData VL_FGETS_IXI(int obits, void* destp, IData fpi) VL_MT_SAFE;
 
-extern void VL_FFLUSH_I(IData fdi);
-extern IData VL_FSEEK_I(IData fdi, IData offset, IData origin);
-extern IData VL_FTELL_I(IData fdi);
-extern void VL_FCLOSE_I(IData fdi);
+extern void VL_FFLUSH_I(IData fdi) VL_MT_SAFE;
+extern IData VL_FSEEK_I(IData fdi, IData offset, IData origin) VL_MT_SAFE;
+extern IData VL_FTELL_I(IData fdi) VL_MT_SAFE;
+extern void VL_FCLOSE_I(IData fdi) VL_MT_SAFE;
 
 extern IData VL_FREAD_I(int width, int array_lsb, int array_size, void* memp, IData fpi,
-                        IData start, IData count);
+                        IData start, IData count) VL_MT_SAFE;
 
-extern void VL_WRITEF(const char* formatp, ...);
-extern void VL_FWRITEF(IData fpi, const char* formatp, ...);
+extern void VL_WRITEF(const char* formatp, ...) VL_MT_SAFE;
+extern void VL_FWRITEF(IData fpi, const char* formatp, ...) VL_MT_SAFE;
 
-extern IData VL_FSCANF_IX(IData fpi, const char* formatp, ...);
-extern IData VL_SSCANF_IIX(int lbits, IData ld, const char* formatp, ...);
-extern IData VL_SSCANF_IQX(int lbits, QData ld, const char* formatp, ...);
-extern IData VL_SSCANF_IWX(int lbits, WDataInP const lwp, const char* formatp, ...);
+extern IData VL_FSCANF_IX(IData fpi, const char* formatp, ...) VL_MT_SAFE;
+extern IData VL_SSCANF_IIX(int lbits, IData ld, const char* formatp, ...) VL_MT_SAFE;
+extern IData VL_SSCANF_IQX(int lbits, QData ld, const char* formatp, ...) VL_MT_SAFE;
+extern IData VL_SSCANF_IWX(int lbits, WDataInP const lwp, const char* formatp, ...) VL_MT_SAFE;
 
-extern void VL_SFORMAT_X(int obits, CData& destr, const char* formatp, ...);
-extern void VL_SFORMAT_X(int obits, SData& destr, const char* formatp, ...);
-extern void VL_SFORMAT_X(int obits, IData& destr, const char* formatp, ...);
-extern void VL_SFORMAT_X(int obits, QData& destr, const char* formatp, ...);
-extern void VL_SFORMAT_X(int obits, void* destp, const char* formatp, ...);
+extern void VL_SFORMAT_X(int obits, CData& destr, const char* formatp, ...) VL_MT_SAFE;
+extern void VL_SFORMAT_X(int obits, SData& destr, const char* formatp, ...) VL_MT_SAFE;
+extern void VL_SFORMAT_X(int obits, IData& destr, const char* formatp, ...) VL_MT_SAFE;
+extern void VL_SFORMAT_X(int obits, QData& destr, const char* formatp, ...) VL_MT_SAFE;
+extern void VL_SFORMAT_X(int obits, void* destp, const char* formatp, ...) VL_MT_SAFE;
 
 extern void VL_STACKTRACE() VL_MT_SAFE;
 extern std::string VL_STACKTRACE_N() VL_MT_SAFE;
-extern IData VL_SYSTEM_IW(int lhswords, WDataInP const lhsp);
-extern IData VL_SYSTEM_IQ(QData lhs);
+extern IData VL_SYSTEM_IW(int lhswords, WDataInP const lhsp) VL_MT_SAFE;
+extern IData VL_SYSTEM_IQ(QData lhs) VL_MT_SAFE;
 inline IData VL_SYSTEM_II(IData lhs) VL_MT_SAFE { return VL_SYSTEM_IQ(lhs); }
 
-extern IData VL_TESTPLUSARGS_I(const std::string& format);
-extern const char* vl_mc_scan_plusargs(const char* prefixp);  // PLIish
+extern IData VL_TESTPLUSARGS_I(const std::string& format) VL_MT_SAFE;
+extern const char* vl_mc_scan_plusargs(const char* prefixp) VL_MT_SAFE;  // PLIish
 
 //=========================================================================
 // Base macros
@@ -214,14 +216,14 @@ static inline double VL_ITOR_D_Q(int, QData lhs) VL_PURE {
     return static_cast<double>(static_cast<uint64_t>(lhs));
 }
 // Return double from lhs (numeric) signed
-double VL_ISTOR_D_W(int lbits, WDataInP const lwp) VL_PURE;
-static inline double VL_ISTOR_D_I(int lbits, IData lhs) VL_PURE {
+double VL_ISTOR_D_W(int lbits, WDataInP const lwp) VL_MT_SAFE;
+static inline double VL_ISTOR_D_I(int lbits, IData lhs) VL_MT_SAFE {
     if (lbits == 32) return static_cast<double>(static_cast<int32_t>(lhs));
     VlWide<VL_WQ_WORDS_E> lwp;
     VL_SET_WI(lwp, lhs);
     return VL_ISTOR_D_W(lbits, lwp);
 }
-static inline double VL_ISTOR_D_Q(int lbits, QData lhs) VL_PURE {
+static inline double VL_ISTOR_D_Q(int lbits, QData lhs) VL_MT_SAFE {
     if (lbits == 64) return static_cast<double>(static_cast<int64_t>(lhs));
     VlWide<VL_WQ_WORDS_E> lwp;
     VL_SET_WQ(lwp, lhs);
@@ -249,7 +251,7 @@ static inline QData VL_EXTENDSIGN_Q(int lbits, QData lhs) VL_PURE {
 }
 
 // Debugging prints
-extern void _vl_debug_print_w(int lbits, WDataInP const iwp);
+extern void _vl_debug_print_w(int lbits, WDataInP const iwp) VL_MT_SAFE;
 
 //=========================================================================
 // Pli macros
@@ -1158,9 +1160,10 @@ static inline QData VL_POW_QQQ(int, int, int rbits, QData lhs, QData rhs) VL_PUR
     return out;
 }
 WDataOutP VL_POW_WWW(int obits, int, int rbits, WDataOutP owp, WDataInP const lwp,
-                     WDataInP const rwp);
-WDataOutP VL_POW_WWQ(int obits, int, int rbits, WDataOutP owp, WDataInP const lwp, QData rhs);
-QData VL_POW_QQW(int obits, int, int rbits, QData lhs, WDataInP const rwp);
+                     WDataInP const rwp) VL_MT_SAFE;
+WDataOutP VL_POW_WWQ(int obits, int, int rbits, WDataOutP owp, WDataInP const lwp,
+                     QData rhs) VL_MT_SAFE;
+QData VL_POW_QQW(int obits, int, int rbits, QData lhs, WDataInP const rwp) VL_MT_SAFE;
 
 #define VL_POWSS_IIQ(obits, lbits, rbits, lhs, rhs, lsign, rsign) \
     VL_POWSS_QQQ(obits, lbits, rbits, lhs, rhs, lsign, rsign)
@@ -1212,11 +1215,11 @@ static inline QData VL_POWSS_QQQ(int obits, int, int rbits, QData lhs, QData rhs
     return VL_POW_QQQ(obits, rbits, rbits, lhs, rhs);
 }
 WDataOutP VL_POWSS_WWW(int obits, int, int rbits, WDataOutP owp, WDataInP const lwp,
-                       WDataInP const rwp, bool lsign, bool rsign);
+                       WDataInP const rwp, bool lsign, bool rsign) VL_MT_SAFE;
 WDataOutP VL_POWSS_WWQ(int obits, int, int rbits, WDataOutP owp, WDataInP const lwp, QData rhs,
-                       bool lsign, bool rsign);
+                       bool lsign, bool rsign) VL_MT_SAFE;
 QData VL_POWSS_QQW(int obits, int, int rbits, QData lhs, WDataInP const rwp, bool lsign,
-                   bool rsign);
+                   bool rsign) VL_MT_SAFE;
 
 //===================================================================
 // Concat/replication
@@ -1943,7 +1946,7 @@ static inline QData VL_RTOIROUND_Q_D(double lhs) VL_PURE {
 static inline IData VL_RTOIROUND_I_D(double lhs) VL_PURE {
     return static_cast<IData>(VL_RTOIROUND_Q_D(lhs));
 }
-static inline WDataOutP VL_RTOIROUND_W_D(int obits, WDataOutP owp, double lhs) VL_PURE {
+static inline WDataOutP VL_RTOIROUND_W_D(int obits, WDataOutP owp, double lhs) VL_MT_SAFE {
     // IEEE format: [63]=sign [62:52]=exp+1023 [51:0]=mantissa
     // This does not need to support subnormals as they are sub-integral
     lhs = VL_ROUND(lhs);
@@ -2153,7 +2156,7 @@ inline IData VL_CMP_NN(const std::string& lhs, const std::string& rhs, bool igno
 
 extern IData VL_ATOI_N(const std::string& str, int base) VL_PURE;
 
-extern IData VL_FGETS_NI(std::string& dest, IData fpi);
+extern IData VL_FGETS_NI(std::string& dest, IData fpi) VL_MT_SAFE;
 
 //======================================================================
 // Dist functions
@@ -2196,8 +2199,8 @@ inline std::string VL_REPLICATEN_NNI(const std::string& lhs, IData rep) VL_PURE
 }
 
 inline IData VL_LEN_IN(const std::string& ld) { return ld.length(); }
-extern std::string VL_TOLOWER_NN(const std::string& ld);
-extern std::string VL_TOUPPER_NN(const std::string& ld);
+extern std::string VL_TOLOWER_NN(const std::string& ld) VL_PURE;
+extern std::string VL_TOUPPER_NN(const std::string& ld) VL_PURE;
 
 extern IData VL_FERROR_IN(IData fpi, std::string& outputr) VL_MT_SAFE;
 extern IData VL_FOPEN_NN(const std::string& filename, const std::string& mode) VL_MT_SAFE;
diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h
index d925bcaf4..2aba690b5 100644
--- a/include/verilated_trace_imp.h
+++ b/include/verilated_trace_imp.h
@@ -41,7 +41,7 @@
 //=============================================================================
 // Static utility functions
 
-static double timescaleToDouble(const char* unitp) {
+static double timescaleToDouble(const char* unitp) VL_PURE {
     char* endp = nullptr;
     double value = std::strtod(unitp, &endp);
     // On error so we allow just "ns" to return 1e-9.
@@ -60,7 +60,7 @@ static double timescaleToDouble(const char* unitp) {
     return value;
 }
 
-static std::string doubleToTimescale(double value) {
+static std::string doubleToTimescale(double value) VL_PURE {
     const char* suffixp = "s";
     // clang-format off
     if      (value >= 1e0)   { suffixp = "s"; value *= 1e0; }
diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp
index 85358d731..ffabf253f 100644
--- a/include/verilated_vpi.cpp
+++ b/include/verilated_vpi.cpp
@@ -2290,7 +2290,8 @@ PLI_INT32 vpi_release_handle(vpiHandle object) {
     return 1;
 }
 
-PLI_INT32 vpi_get_vlog_info(p_vpi_vlog_info vlog_info_p) VL_MT_SAFE {
+PLI_INT32 vpi_get_vlog_info(p_vpi_vlog_info vlog_info_p) {
+    // This is VL_MT_SAFE, but not marked as can't indicate it in the standardized header file
     VerilatedVpiImp::assertOneCheck();
     VL_VPI_ERROR_RESET_();
     const auto argc_argv = Verilated::threadContextp()->impp()->argc_argv();

From 424faa883eebb481b0bbbdc12bdcc73697fda7ea Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sun, 11 Dec 2022 23:10:59 -0500
Subject: [PATCH 149/156] Internals: Mark more VL_MT_SAFE functions. No
 functional change

---
 include/verilated_dpi.cpp     |  4 ++--
 include/verilated_sym_props.h | 12 ++++++------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/include/verilated_dpi.cpp b/include/verilated_dpi.cpp
index 7f68e1bad..a9c1b3aed 100644
--- a/include/verilated_dpi.cpp
+++ b/include/verilated_dpi.cpp
@@ -181,7 +181,7 @@ void svPutPartselLogic(svLogicVecVal* dp, const svLogicVecVal s, int lbit, int w
 //======================================================================
 // Open array internals
 
-static const VerilatedDpiOpenVar* _vl_openhandle_varp(const svOpenArrayHandle h) {
+static const VerilatedDpiOpenVar* _vl_openhandle_varp(const svOpenArrayHandle h) VL_MT_SAFE {
     if (VL_UNLIKELY(!h)) {
         VL_FATAL_MT(__FILE__, __LINE__, "",
                     "%%Error: DPI svOpenArrayHandle function called with nullptr handle");
@@ -223,7 +223,7 @@ int svSizeOfArray(const svOpenArrayHandle h) {
 // Open array access internals
 
 static void* _vl_sv_adjusted_datap(const VerilatedDpiOpenVar* varp, int nargs, int indx1,
-                                   int indx2, int indx3) {
+                                   int indx2, int indx3) VL_MT_SAFE {
     void* datap = varp->datap();
     if (VL_UNLIKELY(nargs != varp->udims())) {
         VL_SVDPI_WARN_("%%Warning: DPI svOpenArrayHandle function called on"
diff --git a/include/verilated_sym_props.h b/include/verilated_sym_props.h
index c62d59faa..03228467f 100644
--- a/include/verilated_sym_props.h
+++ b/include/verilated_sym_props.h
@@ -53,14 +53,14 @@ public:
         : m_left{left}
         , m_right{right} {}
     ~VerilatedRange() = default;
-    int left() const { return m_left; }
-    int right() const { return m_right; }
-    int low() const { return (m_left < m_right) ? m_left : m_right; }
-    int high() const { return (m_left > m_right) ? m_left : m_right; }
-    int elements() const {
+    int left() const VL_PURE { return m_left; }
+    int right() const VL_PURE { return m_right; }
+    int low() const VL_PURE { return (m_left < m_right) ? m_left : m_right; }
+    int high() const VL_PURE { return (m_left > m_right) ? m_left : m_right; }
+    int elements() const VL_PURE {
         return (VL_LIKELY(m_left >= m_right) ? (m_left - m_right + 1) : (m_right - m_left + 1));
     }
-    int increment() const { return (m_left >= m_right) ? 1 : -1; }
+    int increment() const VL_PURE { return (m_left >= m_right) ? 1 : -1; }
 };
 
 //===========================================================================

From 7b073fec7d9974450c72ebd8facd1873ce27e64f Mon Sep 17 00:00:00 2001
From: Kritik Bhimani <bhimanikritik@gmail.com>
Date: Tue, 13 Dec 2022 05:15:32 +0530
Subject: [PATCH 150/156] Fix MSVC++ portability issues (#3812)

---
 include/verilatedos.h | 2 +-
 src/V3DfgDfgToAst.cpp | 8 ++++++++
 src/V3Os.cpp          | 4 ++--
 src/bisonpre          | 2 +-
 4 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/include/verilatedos.h b/include/verilatedos.h
index 72f80d0e7..d5906b526 100644
--- a/include/verilatedos.h
+++ b/include/verilatedos.h
@@ -234,7 +234,7 @@
 //=========================================================================
 // C++-2011
 
-#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__) || defined(VL_CPPCHECK)
+#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__) || defined(VL_CPPCHECK) || (defined(_MSC_VER) && _MSC_VER >= 1900)
 #else
 # error "Verilator requires a C++11 or newer compiler"
 #endif
diff --git a/src/V3DfgDfgToAst.cpp b/src/V3DfgDfgToAst.cpp
index 9075858d5..cd32b3fcb 100644
--- a/src/V3DfgDfgToAst.cpp
+++ b/src/V3DfgDfgToAst.cpp
@@ -100,21 +100,29 @@ AstShiftRS* makeNode<AstShiftRS, DfgShiftRS, AstNodeExpr*, AstNodeExpr*>(  //
 template <>
 AstCCast* makeNode<AstCCast, DfgCCast, AstNodeExpr*>(const DfgCCast* vtxp, AstNodeExpr*) {
     vtxp->v3fatalSrc("not implemented");
+    VL_UNREACHABLE;
+    return nullptr;  // LCOV_EXCL_LINE
 }
 template <>
 AstAtoN* makeNode<AstAtoN, DfgAtoN, AstNodeExpr*>(const DfgAtoN* vtxp, AstNodeExpr*) {
     vtxp->v3fatalSrc("not implemented");
+    VL_UNREACHABLE;
+    return nullptr;  // LCOV_EXCL_LINE
 }
 template <>
 AstCompareNN*
 makeNode<AstCompareNN, DfgCompareNN, AstNodeExpr*, AstNodeExpr*>(const DfgCompareNN* vtxp,
                                                                  AstNodeExpr*, AstNodeExpr*) {
     vtxp->v3fatalSrc("not implemented");
+    VL_UNREACHABLE;
+    return nullptr;  // LCOV_EXCL_LINE
 }
 template <>
 AstSliceSel* makeNode<AstSliceSel, DfgSliceSel, AstNodeExpr*, AstNodeExpr*, AstNodeExpr*>(
     const DfgSliceSel* vtxp, AstNodeExpr*, AstNodeExpr*, AstNodeExpr*) {
     vtxp->v3fatalSrc("not implemented");
+    VL_UNREACHABLE;
+    return nullptr;  // LCOV_EXCL_LINE
 }
 // LCOV_EXCL_STOP
 
diff --git a/src/V3Os.cpp b/src/V3Os.cpp
index 1bd78f583..78caceacb 100644
--- a/src/V3Os.cpp
+++ b/src/V3Os.cpp
@@ -80,10 +80,10 @@ string V3Os::getenvStr(const string& envvar, const string& defaultValue) {
 #if defined(_MSC_VER)
     // Note: MinGW does not offer _dupenv_s
     const char* envvalue = nullptr;
-    _dupenv_s(&envvalue, nullptr, envvar.c_str());
+    _dupenv_s((char **)&envvalue, nullptr, envvar.c_str());
     if (envvalue != nullptr) {
         const std::string result{envvalue};
-        free(envvalue);
+        free((void *)envvalue);
         ret = result;
     } else {
         ret = defaultValue;
diff --git a/src/bisonpre b/src/bisonpre
index 664684c06..368f1c81b 100755
--- a/src/bisonpre
+++ b/src/bisonpre
@@ -45,7 +45,7 @@ def process():
     if status != 0:
         unlink_outputs()
         sys.exit("bisonpre: %Error: " + Args.yacc + " version " +
-                 Bison_Version + " run failed due to errors\n")
+                 str(Bison_Version) + " run failed due to errors\n")
 
     clean_output(tmp_prefix() + ".output",
                  output_prefix() + ".output", True, False)

From d192372c7e91cfc40cc8feba9007825b01ecbea2 Mon Sep 17 00:00:00 2001
From: github action <action@example.com>
Date: Mon, 12 Dec 2022 23:46:23 +0000
Subject: [PATCH 151/156] Apply 'make format'

---
 src/V3Os.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/V3Os.cpp b/src/V3Os.cpp
index 78caceacb..75b82de44 100644
--- a/src/V3Os.cpp
+++ b/src/V3Os.cpp
@@ -80,10 +80,10 @@ string V3Os::getenvStr(const string& envvar, const string& defaultValue) {
 #if defined(_MSC_VER)
     // Note: MinGW does not offer _dupenv_s
     const char* envvalue = nullptr;
-    _dupenv_s((char **)&envvalue, nullptr, envvar.c_str());
+    _dupenv_s((char**)&envvalue, nullptr, envvar.c_str());
     if (envvalue != nullptr) {
         const std::string result{envvalue};
-        free((void *)envvalue);
+        free((void*)envvalue);
         ret = result;
     } else {
         ret = defaultValue;

From f331c192b4e2124e35d0feb5a67c230959f90eca Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 12 Dec 2022 21:32:45 -0500
Subject: [PATCH 152/156] Tests: Fix duplicated if.

---
 test_regress/t/t_force.v | 20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)

diff --git a/test_regress/t/t_force.v b/test_regress/t/t_force.v
index 16270e39d..d669a8d74 100644
--- a/test_regress/t/t_force.v
+++ b/test_regress/t/t_force.v
@@ -45,6 +45,7 @@ module t(/*AUTOARG*/
       else if (cyc == 2) begin
          `checkh(never_driven, 32'h888);
       end
+      //
       // Check release with no force
       else if (cyc == 10) begin
          never_forced <= 5432;
@@ -60,35 +61,36 @@ module t(/*AUTOARG*/
       end
       //
       // bus
-      else if (cyc == 10) begin
+      else if (cyc == 20) begin
          `checkh(bus, 4'b0101);
          force bus = 4'b0111;
       end
-      else if (cyc == 11) begin
+      else if (cyc == 21) begin
          `checkh(bus, 4'b0111);
          force bus = 4'b1111;
       end
-      else if (cyc == 12) begin
+      else if (cyc == 22) begin
          `checkh(bus, 4'b1111);
          release bus;
       end
-      else if (cyc == 13) begin
+      else if (cyc == 23) begin
          `checkh(bus, 4'b0101);
       end
-      else if (cyc == 20) begin
+      //
+      else if (cyc == 30) begin
          force_bus();
       end
-      else if (cyc == 21) begin
+      else if (cyc == 31) begin
          `checkh(bus, 4'b0110);
       end
-      else if (cyc == 22) begin
+      else if (cyc == 32) begin
          release bus[0];
       end
-      else if (cyc == 23) begin
+      else if (cyc == 33) begin
          `checkh(bus, 4'b0111);
          release_bus();
       end
-      else if (cyc == 24) begin
+      else if (cyc == 34) begin
          `checkh(in, 4'b0101);
          `checkh(bus, 4'b0101);
       end

From 9d2f1c607a1fe12a0410e6dcb93cfab139edddd2 Mon Sep 17 00:00:00 2001
From: Kritik Bhimani <bhimanikritik@gmail.com>
Date: Wed, 14 Dec 2022 17:37:25 +0530
Subject: [PATCH 153/156] Fix MSVCC issues (#3813)

---
 include/verilatedos.h |  8 +++++++-
 src/V3Options.cpp     | 18 +++++++++++++++++-
 src/V3Os.cpp          | 16 +++++++++++++++-
 src/V3Sched.cpp       |  2 +-
 4 files changed, 40 insertions(+), 4 deletions(-)

diff --git a/include/verilatedos.h b/include/verilatedos.h
index d5906b526..9906e876f 100644
--- a/include/verilatedos.h
+++ b/include/verilatedos.h
@@ -231,10 +231,16 @@
         } while (false); \
     } while (false)
 
+#ifdef _MSC_VER
+# if _MSC_VER < 1929
+#  error "Verilator requires at least Visual Studio 2019 version 16.11.2"
+# endif
+#endif
+
 //=========================================================================
 // C++-2011
 
-#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__) || defined(VL_CPPCHECK) || (defined(_MSC_VER) && _MSC_VER >= 1900)
+#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__) || defined(VL_CPPCHECK) || defined(_MSC_VER)
 #else
 # error "Verilator requires a C++11 or newer compiler"
 #endif
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index 49ef7aeed..3d920dfca 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -36,7 +36,12 @@
 #endif
 #include <algorithm>
 #include <cctype>
-#include <dirent.h>
+#ifdef _MSC_VER
+# include <filesystem> // C++17
+# define S_ISDIR(mode) (((mode) & _S_IFMT) == _S_IFDIR)
+#else
+# include <dirent.h>
+#endif
 #include <fcntl.h>
 #include <list>
 #include <map>
@@ -454,11 +459,17 @@ void V3Options::fileNfsFlush(const string& filename) {
     // NFS caches stat() calls so to get up-to-date information must
     // do a open or opendir on the filename.
     // Faster to just try both rather than check if a file is a dir.
+#ifdef _MSC_VER
+    if (int fd = ::open(filename.c_str(), O_RDONLY)) {  // LCOV_EXCL_BR_LINE
+        if (fd > 0) ::close(fd);
+    }
+#else
     if (DIR* const dirp = opendir(filename.c_str())) {  // LCOV_EXCL_BR_LINE
         closedir(dirp);  // LCOV_EXCL_LINE
     } else if (int fd = ::open(filename.c_str(), O_RDONLY)) {  // LCOV_EXCL_BR_LINE
         if (fd > 0) ::close(fd);
     }
+#endif
 }
 
 string V3Options::fileExists(const string& filename) {
@@ -477,10 +488,15 @@ string V3Options::fileExists(const string& filename) {
 
         std::set<string>* setp = &(diriter->second);
 
+#ifdef _MSC_VER
+        for (const auto& dirEntry : std::filesystem::directory_iterator(dir.c_str()))
+            setp->insert(dirEntry.path().filename().string());
+#else
         if (DIR* const dirp = opendir(dir.c_str())) {
             while (struct dirent* direntp = readdir(dirp)) setp->insert(direntp->d_name);
             closedir(dirp);
         }
+#endif
     }
     // Find it
     const std::set<string>* filesetp = &(diriter->second);
diff --git a/src/V3Os.cpp b/src/V3Os.cpp
index 75b82de44..5fa1ef11b 100644
--- a/src/V3Os.cpp
+++ b/src/V3Os.cpp
@@ -40,7 +40,12 @@ VL_DEFINE_DEBUG_FUNCTIONS;
 #include <cerrno>
 #include <climits>  // PATH_MAX (especially on FreeBSD)
 #include <cstdarg>
-#include <dirent.h>
+#ifdef _MSC_VER
+# include <filesystem> // C++17
+# define PATH_MAX MAX_PATH
+#else
+# include <dirent.h>
+#endif
 #include <fstream>
 #include <memory>
 
@@ -245,6 +250,14 @@ void V3Os::createDir(const string& dirname) {
 }
 
 void V3Os::unlinkRegexp(const string& dir, const string& regexp) {
+#ifdef _MSC_VER
+    for (const auto& dirEntry : std::filesystem::directory_iterator(dir.c_str())) {
+        if (VString::wildmatch(dirEntry.path().filename().string(), regexp.c_str())) {
+            const string fullname = dir + "/" + dirEntry.path().filename().string();
+            _unlink(fullname.c_str());
+        }
+    }
+#else
     if (DIR* const dirp = opendir(dir.c_str())) {
         while (struct dirent* const direntp = readdir(dirp)) {
             if (VString::wildmatch(direntp->d_name, regexp.c_str())) {
@@ -258,6 +271,7 @@ void V3Os::unlinkRegexp(const string& dir, const string& regexp) {
         }
         closedir(dirp);
     }
+#endif
 }
 
 //######################################################################
diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp
index 73dd6afff..885e5d4a0 100644
--- a/src/V3Sched.cpp
+++ b/src/V3Sched.cpp
@@ -302,7 +302,7 @@ struct TriggerKit {
     // The map from input sensitivity list to trigger sensitivity list
     const std::unordered_map<const AstSenTree*, AstSenTree*> m_map;
 
-    VL_UNCOPYABLE(TriggerKit);
+    // No VL_UNCOPYABLE(TriggerKit) as causes C++20 errors on MSVC
 
     // Utility that assigns the given index trigger to fire when the given variable is zero
     void addFirstIterationTriggerAssignment(AstVarScope* counterp, uint32_t /*index*/) const {

From fcd1306ef3d6bbea1fe33996a6dff07eb25d9ac2 Mon Sep 17 00:00:00 2001
From: github action <action@example.com>
Date: Wed, 14 Dec 2022 12:08:19 +0000
Subject: [PATCH 154/156] Apply 'make format'

---
 src/V3Os.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/V3Os.cpp b/src/V3Os.cpp
index 5fa1ef11b..5e9bbb194 100644
--- a/src/V3Os.cpp
+++ b/src/V3Os.cpp
@@ -41,10 +41,10 @@ VL_DEFINE_DEBUG_FUNCTIONS;
 #include <climits>  // PATH_MAX (especially on FreeBSD)
 #include <cstdarg>
 #ifdef _MSC_VER
-# include <filesystem> // C++17
-# define PATH_MAX MAX_PATH
+#include <filesystem>  // C++17
+#define PATH_MAX MAX_PATH
 #else
-# include <dirent.h>
+#include <dirent.h>
 #endif
 #include <fstream>
 #include <memory>

From 925fb921a2b7b83c2c6aeff968116675d0743d6b Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Wed, 14 Dec 2022 21:12:54 -0500
Subject: [PATCH 155/156] Fix missing VL_REQUIRES in definition (#3804)

---
 include/verilated.cpp   | 25 ++++++++++++++++++++-----
 include/verilated_imp.h |  4 +++-
 2 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/include/verilated.cpp b/include/verilated.cpp
index 679e948e1..7c08480f8 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -2454,14 +2454,17 @@ void VerilatedContext::threads(unsigned n) {
 }
 
 void VerilatedContext::commandArgs(int argc, const char** argv) VL_MT_SAFE_EXCLUDES(m_argMutex) {
-    const VerilatedLockGuard lock{m_argMutex};
-    m_args.m_argVec.clear();  // Empty first, then add
-    impp()->commandArgsAddGuts(argc, argv);
+    // Not locking m_argMutex here, it is done in impp()->commandArgsAddGuts
+    // m_argMutex here is the same as in impp()->commandArgsAddGuts;
+    // due to clang limitations, it doesn't properly check it
+    impp()->commandArgsGuts(argc, argv);
 }
 void VerilatedContext::commandArgsAdd(int argc, const char** argv)
     VL_MT_SAFE_EXCLUDES(m_argMutex) {
-    const VerilatedLockGuard lock{m_argMutex};
-    impp()->commandArgsAddGuts(argc, argv);
+    // Not locking m_argMutex here, it is done in impp()->commandArgsAddGuts
+    // m_argMutex here is the same as in impp()->commandArgsAddGuts;
+    // due to clang limitations, it doesn't properly check it
+    impp()->commandArgsAddGutsLock(argc, argv);
 }
 const char* VerilatedContext::commandArgsPlusMatch(const char* prefixp)
     VL_MT_SAFE_EXCLUDES(m_argMutex) {
@@ -2510,6 +2513,18 @@ VerilatedContext::enableExecutionProfiler(VerilatedVirtualBase* (*construct)(Ver
 
 //======================================================================
 // VerilatedContextImp:: Methods - command line
+void VerilatedContextImp::commandArgsGuts(int argc, const char** argv)
+    VL_MT_SAFE_EXCLUDES(m_argMutex) {
+    const VerilatedLockGuard lock{m_argMutex};
+    m_args.m_argVec.clear();  // Empty first, then add
+    commandArgsAddGuts(argc, argv);
+}
+
+void VerilatedContextImp::commandArgsAddGutsLock(int argc, const char** argv)
+    VL_MT_SAFE_EXCLUDES(m_argMutex) {
+    const VerilatedLockGuard lock{m_argMutex};
+    commandArgsAddGuts(argc, argv);
+}
 
 void VerilatedContextImp::commandArgsAddGuts(int argc, const char** argv) VL_REQUIRES(m_argMutex) {
     if (!m_args.m_argVecLoaded) m_args.m_argVec.clear();
diff --git a/include/verilated_imp.h b/include/verilated_imp.h
index e70fffd3b..6a005dc85 100644
--- a/include/verilated_imp.h
+++ b/include/verilated_imp.h
@@ -387,7 +387,9 @@ private:
 
 protected:
     // METHODS - protected
-    void commandArgsAddGuts(int argc, const char** argv);
+    void commandArgsGuts(int argc, const char** argv) VL_MT_SAFE_EXCLUDES(m_argMutex);
+    void commandArgsAddGutsLock(int argc, const char** argv) VL_MT_SAFE_EXCLUDES(m_argMutex);
+    void commandArgsAddGuts(int argc, const char** argv) VL_REQUIRES(m_argMutex);
     void commandArgVl(const std::string& arg);
     bool commandArgVlString(const std::string& arg, const std::string& prefix,
                             std::string& valuer);

From 4cefccf5d252bb154e2f186ce8eadd90eed6c851 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 14 Dec 2022 21:59:58 -0500
Subject: [PATCH 156/156] Version bump

---
 Changes      | 2 +-
 configure.ac | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/Changes b/Changes
index 78a4bbf28..7cc019b34 100644
--- a/Changes
+++ b/Changes
@@ -8,7 +8,7 @@ The changes in each Verilator version are described below.  The
 contributors that suggested a given feature are shown in []. Thanks!
 
 
-Verilator 5.003 devel
+Verilator 5.004 2022-12-14
 ==========================
 
 **Major:**
diff --git a/configure.ac b/configure.ac
index 81000ef74..1b2ca1a77 100644
--- a/configure.ac
+++ b/configure.ac
@@ -10,7 +10,7 @@
 # Then 'make maintainer-dist'
 #AC_INIT([Verilator],[#.### YYYY-MM-DD])
 #AC_INIT([Verilator],[#.### devel])
-AC_INIT([Verilator],[5.003 devel],
+AC_INIT([Verilator],[5.004 2022-12-14],
         [https://verilator.org],
         [verilator],[https://verilator.org])