From 843fdd3e57fbe32e61298b129943c5b6487215e5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Krzysztof=20Boro=C5=84ski?=
 <94375110+kboronski-ant@users.noreply.github.com>
Date: Thu, 20 Apr 2023 00:05:37 +0200
Subject: [PATCH] Resolve class lvalues after parameterization (#4131)

---
 src/Verilator.cpp                      |  1 +
 test_regress/t/t_class_param_lvalue.pl | 17 +++++++++++++++++
 test_regress/t/t_class_param_lvalue.v  | 15 +++++++++++++++
 3 files changed, 33 insertions(+)
 create mode 100755 test_regress/t/t_class_param_lvalue.pl
 create mode 100644 test_regress/t/t_class_param_lvalue.v

diff --git a/src/Verilator.cpp b/src/Verilator.cpp
index 294320613..6c6940b0c 100644
--- a/src/Verilator.cpp
+++ b/src/Verilator.cpp
@@ -152,6 +152,7 @@ static void process() {
     //   This requires some width calculations and constant propagation
     V3Param::param(v3Global.rootp());
     V3LinkDot::linkDotParamed(v3Global.rootp());  // Cleanup as made new modules
+    V3LinkLValue::linkLValue(v3Global.rootp());  // Resolve new VarRefs
     V3Error::abortIfErrors();
 
     // Remove any modules that were parameterized and are no longer referenced.
diff --git a/test_regress/t/t_class_param_lvalue.pl b/test_regress/t/t_class_param_lvalue.pl
new file mode 100755
index 000000000..13587bf85
--- /dev/null
+++ b/test_regress/t/t_class_param_lvalue.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_class_param_lvalue.v b/test_regress/t/t_class_param_lvalue.v
new file mode 100644
index 000000000..879693876
--- /dev/null
+++ b/test_regress/t/t_class_param_lvalue.v
@@ -0,0 +1,15 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+class Foo;
+endclass
+
+class Bar #(type BASE=Foo) extends BASE;
+  task body();
+    int v = 0;
+    v = 1;
+  endtask
+endclass